Texas Instruments | Generating Negative and Positive Voltage Rail With Boost Converter TLV61048 | Application notes | Texas Instruments Generating Negative and Positive Voltage Rail With Boost Converter TLV61048 Application notes

Texas Instruments Generating Negative and Positive Voltage Rail With Boost Converter TLV61048 Application notes
Application Report
SLVAEJ3 – December 2019
Generating Negative and Positive Voltage Rail With Boost
Converter TLV61048
Jasper Li
ABSTRACT
Many applications require negative and positive voltage rails to power the amplifiers from a 3.3-V or 5-V
power supply. Taking the TLV61048 device as an example, this document demonstrates a simple, costeffective boost converter and discrete charge pump circuit to generate ±12-V voltage rails.
1
2
3
4
5
Contents
Introduction ...................................................................................................................
Operating Principle ..........................................................................................................
External Components Calculation .........................................................................................
Circuit Design With TLV61048 .............................................................................................
References ...................................................................................................................
1
1
4
5
6
List of Figures
..................................................................................
1
TLV61048 Boost Converter Schematic
2
Operating Waveform at 100-mA Loading................................................................................. 2
3
Boost With Discrete Charge Pump Circuit
4
5
6
7
...............................................................................
Simplified Operating Waveform ...........................................................................................
Designed Circuit With TLV61048 ..........................................................................................
Startup Waveform by EN Pin ..............................................................................................
Load Regulation of the Negative Rail .....................................................................................
2
3
3
5
6
6
List of Tables
Trademarks
All trademarks are the property of their respective owners.
1
Introduction
The application report first introduces the operating principle of the discrete charge pump circuit to
generate negative voltage based on boost converter. Then the report derives formulas to calculate the
external component values of the charge pump circuit. Finally, the TLV61048 device is used as example
to verify the circuit designed in the lab.
2
Operating Principle
A typical boost circuit for 3.3-V input, 12-V output based on the TLV61048 device is shown in Figure 1.
The TLV61048 device is a peak-current-control boost converter IC which integrates a power switch with
current limit up to 3.7 A. The switching frequency can be configured through the FRE pin. If the FRE pin is
connected to GND, the switching frequency of the device is 1 MHz.
SLVAEJ3 – December 2019
Submit Documentation Feedback
Generating Negative and Positive Voltage Rail With Boost Converter
TLV61048
Copyright © 2019, Texas Instruments Incorporated
1
Operating Principle
www.ti.com
4.7µH
D1
3.3V
VIN
12V
SW
10 …F
R1
1M
1 …F
EN
COUT
FB
CIN
GND
R2
70.5K
GND
FRE
TLV61048
GND
GND
Figure 1. TLV61048 Boost Converter Schematic
Figure 2 shows the operating waveform at 100-mA loading. The integrated power N-MOSFET switches on
and off to regulate the output voltage, which is set by R1 and R2.
• During TON, the internal low-side FET is on. The SW pin voltage is zero and inductor current lineally
increases. The output voltage is sustained by the output capacitor.
• During TOFF, the internal N-MOSFET is off. The inductor flows through the Schottky diode D1 to charge
the output capacitor.
The sum of TON and TOFF is the switching cycle TSW, approximately 1 µs. The device operates at Continue
Conductive Mode (CCM) in Figure 2, as the inductor current is always higher than zero.
VOUT 5V/div
TOFF
TON
SW 5V/div
ICOIL 0.2A/div
400ns/div
Figure 2. Operating Waveform at 100-mA Loading
At CCM, the duty cycle can be calculated using Equation 1:
D = 1-
h ´ V IN
VOUT
where:
•
•
•
η is the efficiency
VIN is the input voltage of the boost converter
VOUT is the output voltage of the boost
(1)
The power components of the typical boost converter with discrete circuit to generate a negative voltage is
shown in Figure 3. The positive rail is VOUT1, while the negative voltage rail is VOUT2. The external
components for negative voltage rail comprise of a resistor RCHG, and a capacitor CCHG and two diodes, D2
and D3.
2
Generating Negative and Positive Voltage Rail With Boost Converter
TLV61048
Copyright © 2019, Texas Instruments Incorporated
SLVAEJ3 – December 2019
Submit Documentation Feedback
Operating Principle
www.ti.com
•
•
During TOFF, the fly capacitor CCHG is charged to SW pin voltage through the RCHG and D2.
During TON, the energy of the CCHG flows into the COUT2 through RCHG and D3.
VOUT2
D3
RCHG
CCHG
D2
+ VCHG
CIN
ICHG
VOUT1
D1
SW
GND
IOUT2
GND
GND
COUT1
IOUT1
GND
GND
GND
L1
VIN
COUT2
R1
TLV61048
FB
CTRL
R2
GND
GND
Figure 3. Boost With Discrete Charge Pump Circuit
Figure 4 shows the simplified operating waveform of the circuit, where:
• VSW is the SW pin voltage waveform at CCM
• ICOIL is the inductor current
• ICHG is the current through the CCHG
• VCHG is the voltage across the CCHG
VSW
ICOIL
ICHG
VCHG
VCOUT2
TOFF
TON
TS
Figure 4. Simplified Operating Waveform
SLVAEJ3 – December 2019
Submit Documentation Feedback
Generating Negative and Positive Voltage Rail With Boost Converter
TLV61048
Copyright © 2019, Texas Instruments Incorporated
3
External Components Calculation
3
www.ti.com
External Components Calculation
At stable condition, the average current through the CCHG and COUT2 within one switching cycle must be
zero. Thus the average current of ICHG during TON is defined by Equation 2.
ICHG1 =
TS
1
´ I OUT 2 = ´ I OUT 2
TON
D
(2)
The average current through CCHG during TOFF can be calculated by Equation 3 .
I CHG2 =
TON
1
´ I CHG1 =
´ I OUT 2
TOFF
1- D
(3)
From Equation 2 and Equation 3, the voltage ripple of the CCHG can be calculated with Equation 4.
D VCHG = I CHG1 ´
1
C CHG
´ TON =
IOUT 2
´ TSW
C CHG
(4)
As all the energy of the COUT2 is provided by during CCHG during TON, the CCHG voltage reaches valley and
VOUT2 reaches peak at the end of TON. The waveform in Figure 4 demonstrates this behavior. This means
that the voltage ripple of the CCHG would impact the voltage level of the VOUT2. So CCHG voltage ripple
should be set to typical 1% of its DC voltage.
The DC voltage of the CCHG can be calculated with Equation 5. Ignoring the voltage drops of the RCHG, the
VCHG is equal to VOUT1.
VCHG = (VOUT1 + VD1 ) - I CHG 2 ´ R CHG - V D 2
where:
•
•
•
•
VOUT1 is positive rail voltage set by the feedback resistor
VD1 is forward voltage of D1.
ICHG1 is the average current during TOFF
VD2 is the forward voltage of D2
(5)
The voltage ripple of the COUT2 is defined by Equation 6. The output voltage ripple can also be set to 1% of
its DC voltage.
D VCOUT 2 = I OUT 2 ´
1
C OUT 2
´ (1 - D ) ´ TSW
(6)
The DC voltage of COUT2 can be estimated through Equation 7, closed to (VOUT1 – 0.3) if ignoring the RCHG
voltage drop.
- VCO UT 2 = VCHG - I CHG1 ´ R CHG - VD 3 = (VO UT1 + VD1 ) - (VCHG1 + ICHG 2 ) ´ R CHG - 2 ´ VD 2
where:
•
•
VCHG is DC voltage of the CCHG
VD3 is the forward voltage of the D3, equal to VD2
(7)
The RCHG is to limit the peak current through the capacitor, internal MOSFET, and D2 and D3. From
Equation 7, high RCHG will result in low COUT2 voltage. Thus the RCHG cannot be too large. It is suggested to
select RCHG as Equation 8, which means the time constant of the RCHG and CCHG is equal to the switching
cycle.
R CHG ´ C CHG = TS
(8)
The power loss of the resistor can be estimated through Equation 9, assuming that the RMS current
through the RCHG is closed to the average current.
(
P RCHG = R CHG ´ D ´ I CHG12 + (1 - D ) ´ I CHG 2 2
4
)
Generating Negative and Positive Voltage Rail With Boost Converter
TLV61048
Copyright © 2019, Texas Instruments Incorporated
(9)
SLVAEJ3 – December 2019
Submit Documentation Feedback
Circuit Design With TLV61048
www.ti.com
4
Circuit Design With TLV61048
This section uses the TLV61048 device as an example to demonstrate the design process introduced in
this application report.
The input and output electrical requirements follow:
• Input voltage VIN: 3.3 V
• Positive rail voltage VOUT1: 12 V
• Negative rail voltage VOUT2: –12 V
• Maximum output current of VOUT1 and VOUT2: 100 mA
• Voltage ripple of VOUT2: 120 mV
Based on this requirement, the design process is as shown in the following list when setting the switching
frequency to 1 MHz:
• Duty cycle D: 75% by Equation 1
• Average current during TON, ICHG1= 133 mA by Equation 2
• Average current during TON, ICHG2= 400 mA by Equation 3
• DC voltage of the CCHG at zero loading, VCHG ≈ 12 V by Equation 5
• Voltage ripple of VCHG is 1% of its DC voltage, ΔVCHG ≈ 120 mV
• Effective capacitance of CCHG, 0.83 µF by Equation 4
• Current limit resistor, RCHG = 1.2 Ω by Equation 8
• Power loss of RCHG, 60 mW by Equation 9
• Effective capacitance of COUT2, 0.6 µF by Equation 6
• DC voltage of CCHG at 100 mA, VCHG= 11.5 V by Equation 5
• DC voltage of COUT2 at 100 mA, VOUT2= –11 V by Equation 7
Using the external components value closed to the previous calculation result , the final circuit is shown in
Figure 5. The effective capacitance of the 2.2-µF capacitor at 12-V bias condition is around 0.8 µF.
-12V
2.2µF
1Ÿ
4.7µH
2.2µF
GND
D1
3.3V
VIN
12V
SW
10 …F
R1
1M
1 …F
EN
FB
CIN
GND
R2
70.5K
GND
FRE
TLV61048
GND
GND
Figure 5. Designed Circuit With TLV61048
The startup waveform through the EN pin at a 100-mA condition is shown in Figure 6. After the EN pin
becomes logic high, the voltage of VOUT1 and VOUT2 ramp up to the setting value smoothly.
SLVAEJ3 – December 2019
Submit Documentation Feedback
Generating Negative and Positive Voltage Rail With Boost Converter
TLV61048
Copyright © 2019, Texas Instruments Incorporated
5
References
www.ti.com
VOUT1 5V/div
VOUT2 5V/div
EN 5V/div
2ms/div
Figure 6. Startup Waveform by EN Pin
The absolute value of VOUT2 from 20 mA to 100 mA is shown in Figure 7. The voltage gap between the
calculation result by Equation 7 and the bench test result is approximately 100 mV. Because of the voltage
drop of the resistor and the Schottky diode, the VOUT2 absolute value is 11.6 V at 20-mA loading and is 11
V at 100-mA loading.
12
VOUT2 (V)
11.6
11.2
10.8
BenchTest
10.4
Calculation
10
20
30
40
50
60
70
80
90
100
IOUT (mA)
Figure 7. Load Regulation of the Negative Rail
5
References
1. Texas Instruments, Design for a Discrete Charge Pump
6
Generating Negative and Positive Voltage Rail With Boost Converter
TLV61048
Copyright © 2019, Texas Instruments Incorporated
SLVAEJ3 – December 2019
Submit Documentation Feedback
IMPORTANT NOTICE AND DISCLAIMER
TI PROVIDES TECHNICAL AND RELIABILITY DATA (INCLUDING DATASHEETS), DESIGN RESOURCES (INCLUDING REFERENCE
DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND OTHER RESOURCES “AS IS”
AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS AND IMPLIED, INCLUDING WITHOUT LIMITATION ANY
IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD
PARTY INTELLECTUAL PROPERTY RIGHTS.
These resources are intended for skilled developers designing with TI products. You are solely responsible for (1) selecting the appropriate
TI products for your application, (2) designing, validating and testing your application, and (3) ensuring your application meets applicable
standards, and any other safety, security, or other requirements. These resources are subject to change without notice. TI grants you
permission to use these resources only for development of an application that uses the TI products described in the resource. Other
reproduction and display of these resources is prohibited. No license is granted to any other TI intellectual property right or to any third
party intellectual property right. TI disclaims responsibility for, and you will fully indemnify TI and its representatives against, any claims,
damages, costs, losses, and liabilities arising out of your use of these resources.
TI’s products are provided subject to TI’s Terms of Sale (www.ti.com/legal/termsofsale.html) or other applicable terms available either on
ti.com or provided in conjunction with such TI products. TI’s provision of these resources does not expand or otherwise alter TI’s applicable
warranties or warranty disclaimers for TI products.
Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265
Copyright © 2019, Texas Instruments Incorporated
Was this manual useful for you? yes no
Thank you for your participation!

* Your assessment is very important for improving the work of artificial intelligence, which forms the content of this project

Related manuals

Download PDF

advertising