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Texas Instruments Designing a Simple and Low-Cost Flybuck Solution With the TPS54308 (Rev. A) Application notes
Application Report
SLUA838A – August 2017 – Revised October 2019
Designing a Simple and Low-Cost Flybuck Solution With
the TPS54308
Ryan Hu
ABSTRACT
In many applications, simple, low part-count, isolated power supplies working from an input voltage are
needed. A popular solution to these requirements is an isolated buck power supply. This application report
presents a simple and low-cost flybuck solution using the TPS54308 device. The basic operating
principles of a flybuck converter are discussed, operating current and voltage waveforms are shown, and
key design equations are derived. Lastly, a step-by-step design example is presented.
1
2
3
4
5
6
Contents
Introduction ................................................................................................................... 2
Flybuck Converter Device Overview ...................................................................................... 2
Design Flybuck With TPS54308 ........................................................................................... 6
Experimental Results ...................................................................................................... 10
Conclusion .................................................................................................................. 14
References .................................................................................................................. 14
List of Figures
1
Isolated Buck Converter With Two Outputs .............................................................................. 2
2
Simplified Isolated Buck Operating Waveforms
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
......................................................................... 3
Current Waveforms Affected by Leakage Inductance .................................................................. 4
TPS54308 Two Output Isolated Buck Solution .......................................................................... 6
Efficiency vs IOUT1 (IOUT1 = 0 A, IOUT2 = 0 A) ............................................................................... 10
Efficiency vs IOUT2 (IOUT1 = 0 A, IOUT3 = 0 A) ............................................................................... 10
Efficiency vs IOUT3 (IOUT1 = 0 A, IOUT2 = 0 A) ............................................................................... 10
VOUT2 Regulation vs IOUT2 (IOUT1 = 0 A, IOUT3 = 0 A) ....................................................................... 11
VOUT3 Regulation vs IOUT3 (IOUT1 = 0 A, IOUT2 = 0 A) ....................................................................... 11
VOUT2 Regulation vs VIN (IOUT1 = 0 A, IOUT3 = 0 A) ........................................................................ 11
VOUT3 Regulation vs VIN (IOUT1 = 0 A, IOUT2 = 0 A) ........................................................................ 12
Steady State Waveforms (VIN = 10 V, IOUT1 = 1 A, IOUT2 = 0.2 A, and IOUT3 = 0.2 A) ................................ 12
Steady State Waveforms (VIN = 10 V, IOUT1 = 0 A, IOUT2 = 0.2 A, and IOUT3 = 0.2 A) ................................ 12
Ripple Voltage Waveforms (VIN = 10 V, IOUT1 = 1 A, IOUT2 = 0.2 A, and IOUT3 = 0.2 A) .............................. 13
Load Step Response 50 mA to 200 mA (VIN = 10 V, IOUT1 = 0 A, and IOUT3 = 0 A) ................................. 13
Line Step Response 10 V to 24 V (IOUT1 = 1 A, IOUT2 = 0.2 A, and IOUT3 = 0.2 A) .................................... 13
Power Up (VIN = 10 V, IOUT1 = 1 A, IOUT2 = 0.2 A, and IOUT3 = 0.2 A)................................................... 14
List of Tables
1
Design Parameters .......................................................................................................... 6
Trademarks
All trademarks are the property of their respective owners.
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1
Introduction
1
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Introduction
Isolated bias rails are common in many systems or subsystems, such as telecommunication equipment,
medical equipment, and industrial factory automation. It is mandatory by safety standards to protect users
from the hazardous voltage of a power supply, or the isolation is installed to break the ground loop
interference for noise-sensitive applications.
In many cases, simple, low part count, isolated power supplies working from an input voltage are needed.
This design solution is for when regulation may not be as important, but cost and board area are. A
popular solution to these requirements is an isolated buck power supply, which is a synchronous buck
converter, with the inductor replaced by a coupled inductor or flyback-type transformer. There is no need
for an optocoupler or auxiliary winding because the secondary output closely tracks the primary voltage,
resulting in smaller solution size and cost. The flybuck can support a simple, small, and cost effective
power solution making it suitable as a flyback alternative.
This application report presents the basic operating principles of a flybuck converter, shows some typical
operating current and voltage waveforms, and the key design equations are derived. The design example
shows a step-by-step procedure for designing one nonisolated and two isolated outputs with the
synchronous buck regulator TPS54308.
The TPS54308 device is a 4.5-V to 28-V input voltage range, 3-A switching regulator, that has two
integrated switching FETs, internal loop compensation, and 5-ms internal soft start to reduce component
count. By integrating the MOSFETs and employing the SOT-23 package, the TPS54308 achieves highpower density and offers a small footprint on the PCB.
2
Flybuck Converter Device Overview
2.1
Operation Description
An isolated buck converter is a synchronous buck converter with the inductor replaced by a coupled
inductor or flyback-type transformer. The primary output is still regulated as in a sync buck. The secondary
output is generated by a diode rectifying the secondary winding. Figure 1 shows an isolated buck
converter with two outputs.
D1
IOUT2
- Vd +
isec
CIN
R2
COUT2
N2
N = N2 : N1
VSW
N1
ipri + Vpri -
IOUT1
COUT1
R1
Figure 1. Isolated Buck Converter With Two Outputs
2
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Flybuck Converter Device Overview
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Figure 2 shows typical isolated buck operating waveforms. During TON, the high-side MOSFET is on, and
the rectifier diode is turned off, because the reflected voltage across the secondary winding is negative.
The isolated output capacitor COUT2 is discharged, supplying the load current, and the primary side
behaves identical to a buck regulator. During TOFF, the low-side MOSFET is on, and the reflected voltage
on the secondary winding turns positive, forcing the diode forward conducting. The current in the primary
winding splits into two parts: one part continues to supply the primary output (the magnetizing current, im,
similar to a buck converter inductor current), the other part starts to flow to the secondary output. The
secondary current waveform is determined by the load, leakage inductance, and output capacitance.
VIN
Vsw
t
VIN-VOUT1
Vpri
t
-VOUT1
VOUT2 + (VIN ± VOUT) N2
N1
t
VD
im
t
IOUT1 + IOUT2 N2
N1
¨im
ipri
IOUT1
t
IOUT2
isec
t
TON
TOFF
Figure 2. Simplified Isolated Buck Operating Waveforms
The primary output voltage is the same as a buck converter and is given by Equation 1:
Ton
VOUT1 =
VIN = D ´ VIN
Ton + Toff
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(1)
3
Flybuck Converter Device Overview
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The secondary output voltage is given by Equation 2:
N
VOUT2 = VOUT1 ´ 2 - VF
N1
where
•
•
N1 and N2 are the turns of the primary winding and secondary winding
VF is the forward voltage drop of the secondary rectifier diode
(2)
The blocking voltage of the rectifier during TON is given by Equation 3:
N
VD = VOUT2 + 2 (VIN - VOUT1 )
N1
2.2
(3)
Equations for Maximum Output Current
In practice, the transformer has more or less leakage inductance, which determines the ramp rate of the
current in the secondary winding to charge the output capacitor. The simplified current waveforms in
Figure 3 shows its relationship with leakage inductance. With lower leakage inductance, the current ramps
up quickly to a high value, charging the output capacitor quickly. With the leakage inductance increasing,
the current rises slowly, which can result in less energy being supplied to the output capacitance and less
output voltage. The higher leakage inductance is the higher peak charging current obtained in secondary
winding under the same output power rate. A high negative current is reflected in the primary winding at
the same time. Leakage inductance along with duty cycle impacts not only the output voltage regulation,
but also limits the output power resulting from the minimum low-side sink current limit. Therefore, the
leakage inductance must be minimized and the maximum duty cycle must be chosen carefully to mitigate
their impacts.
Normal leakage
Higher leakage
Lower leakage
im
t
IOUT1 + IOUT2 N2
N1
¨im
Ipri_pospk
ipri
t
Ipri_negpk
Isec_pk
isec
t
TON
TOFF
Figure 3. Current Waveforms Affected by Leakage Inductance
The winding and output currents have a relationship as shown in Equation 4 and Equation 5 on one cycle
average basis.
Ipri = IOUT1
(4)
Isec = IOUT2
4
(5)
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Flybuck Converter Device Overview
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The magnetizing current in the transformer that combines the two windings current is identical to a buck
converter. Therefore, the magnetizing current ripple can be derived as in Equation 6.
(V - VOUT1 ) VOUT1 = (VIN - VOUT1 ) D
Dim = IN
Lpri ´ fSW
VIN
Lpri
fSW
(6)
The positive primary winding and switching peak current during TON is given by Equation 7.
Di
N
iSW _ pospk = ipri _ pospk = IOUT1 + 2 IOUT2 + m
N1
2
(7)
Implementing the principle of charge balance to the secondary output capacitor, the secondary winding
peak current can be approximately derived as Equation 8 for a higher leakage case, and Equation 9 for a
normal leakage case.
Considering the worst case, the following equations are derived based on having higher leakage.
2
isec_ pk =
IOUT2
1- D
1+ D
isec_ pk =
IOUT2
1- D
(8)
(9)
Then the negative primary winding peak current can be derived as Equation 10 for a higher leakage case,
and Equation 11 for a normal leakage case.
ipri _ negpk = ipri _ negpk = -
N2
N
isec_ pk + ipri _ pospk - Dim = - 2 IOUT2
N1
N1
N2
IOUT2
N1
æ 1 + D ö Dim
+ IOUT1
ç
÷2
è1- D ø
æ 2D ö Dim
+ IOUT1
ç
÷2
è1- D ø
(10)
(11)
In fact, we must ensure that during TON the positive primary winding peak current does not exceed the
minimum high-side source current limit, ILIMHS(min), and that during TOFF, the negative primary winding peak
current does not exceed the minimum low-side sink current limit, ILIMLSSOC(min). Therefore the positive and
negative primary winding peak current should meet that of Equation 12.
ìipri _ pospk £ ILIMHS min
( )
ï
í
ï ipri _ negpk £ ILIMLSSOC(min)
î
(12)
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Design Flybuck With TPS54308
Figure 4 shows the design example with the typical flybuck circuit, using the synchronous buck regulator
TPS54308 from TI.
TP6
N24:N78:N89=1:2.5:2.5
4
T1
7
U1
TP1
J1
2
1
VIN =10V - 24V
TP4
VIN 3
VIN
BOOT
EN 5
EN
SW
6 BOOT
R3
0
C1
10µF
C2
0.1µF
C3
FB
GND
1
2
VOUT2 = 12V, 0.2A
J2
R10 100
15µH
2
8
0.1uF
C12
100pF
C13
100pF
9
R12
100
NC
4 VSENSE
1
TPS54308DDCR
GND
R2
68k
R4 0
C4
75pF
TP2
750343683
C14
100pF
NC
TP3
C8
10µF
C10
10µF
NC
R8
2.2k
TP7
C9
10µF
C11
10µF
NC
R9
2.2k
TP8
TP11
1
2
J3
R11 100
2 SW
R1
510k
JP1
D2
B270-13-F
GND_ISO
1
2
VOUT3 = -12V, 0.2A
D1
C6
B270-13-F
2200pF
NC
TP9
VOUT1 = 5V, 1A
2
1
R5 TP5
49.9
R6
100k
J4
C5
22µF
C7
22µF
R7
13.7k
TP10
GND
Copyright © 2017, Texas Instruments Incorporated
Figure 4. TPS54308 Two Output Isolated Buck Solution
Table 1 lists the design specification.
Table 1. Design Parameters
Design Parameter
Example Value
Input voltage range (VIN)
10 V to 24 V
Primary output voltage (VOUT1)
5V
Positive isolated output voltage (VOUT2)
12 V
Negative isolated output voltage (VOUT3)
–12 V
Primary load current (IOUT1)
1A
Positive isolated load current (IOUT2)
0.2 A
Negative isolated load current (IOUT3)
0.2 A
Switching frequency (fsw)
350 kHz
In this example, one primary output and two isolated outputs are obtained. We will begin with the buck
converter component calculations and qualify the steps for the isolated configuration.
3.1
Primary Voltage and Turns Ratio
The primary-side, nonisolated output is set to 5 V for several considerations. First, the setting is below the
minimum input voltage, 10 V, and the theoretical duty cycle varies from 20 to 50 percent at the full VIN
range, which is a balanced duty cycle during normal operation. Because the isolated outputs only have the
off-time window to transfer energy, for a duty cycle that is too high, the secondary winding current will
have a huge spike, which leads to poor regulation. Next, the turns ratio of the transformer is not too high
to handle for the 5 V voltage level steps up to 12 V. Last, 5 V is one of the most common voltage levels in
many applications. In this design, a transformer turns ratio (N1:N2:N3) of 1:2.5:2.5 is selected (see
Equation 13 and Equation 14).
N
VOUT2 = VOUT1 ´ 2 - VF = 12 V
N1
(13)
VOUT3 = VOUT1 ´
N3
- VF = 12 V
N1
(14)
In this design, the VF is targeted at 0.5 V.
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3.2
Feedback Resistor
With the expected primary voltage set point at 5 V, and VFB = 0.596 V (typical), VOUT1 is calculated to be as
in Equation 15:
æ
R ö
VOUT1 = VFB ´ ç 1 + 6 ÷
R7 ø
è
(15)
Start with 100 kΩ for the upper resistor divider, R6 = 100 kΩ (see Equation 16).
R6 ´ VFB
R7 =
= 13.53 kW
VOUT1 - VFB
(16)
Next choose R7 = 13.7 kΩ. The 49.9-Ω resistor, R5, is provided as a convenient location to break the
control loop for stability testing.
3.3
Rectifier Diode
The rectifier diode D1 and D2, must meet the blocking voltage and maximum current requirements (see
Equation 17, Equation 18, Equation 19, and Equation 20).
N
VD1 = 2 ´ VIN(max ) - VOUT1 + VOUT2 = 59.5 V
N1
(17)
N2
VD2 =
´ VIN(max ) - VOUT1 + VOUT3 = 59.5 V
N1
(18)
(
(
2 ´ IOUT2
= 0.8 A
1 - Dmax
(19)
2 ´ IOUT3
=
= 0.8 A
1 - Dmax
(20)
iD1_ pk =
iD2 _ pk
)
)
Considering the voltage spike and keeping some margin, as well as the less forward voltage drop, a
schottky diode of 70 V or higher reverse voltage rating is required. A 70-V, 2-A diode is selected for each
rectifier diode in this design.
3.4
Primary Inductance
For the TPS54308, the minimum high-side current is 4 A, and therefore the maximum magnetizing current
ripple that can be tolerated is given by Equation 21:
æ
æ
öö
N
N
Dim = 2 ´ ç ILIM
- ç IOUT1 + 2 IOUT2 + 3 IOUT3 ÷ ÷ = 4 A
ç HS(min)
÷
N1
N1
è
øø
è
(21)
Using Equation 21 for the maximum magnetizing current ripple calculation, the minimum primary
inductance is given by Equation 22.
Lpri(min)
VIN(max)
VOUT1
'im u fsw
VOUT1
VIN(max)
1.79 PH
(22)
Too much high Δim may not be good for the efficiency and output voltage ripple. Assuming the 30% ripple
of the rate output current of the device, then the optimized minimum primary inductance is given by
Equation 23:
Lpri
VIN(max)
VOUT1
0.3 u 3 u fsw
VOUT1
VIN(max)
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12.6 PH
(23)
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We chose 15 μH for the primary inductor, therefore Δim(max) = 0.75 A and Δim(min)= 0.48 A. Use Equation 7,
Equation 10, and Equation 11 to check the positive and negative primary winding peak current (see
Equation 24, Equation 25, and Equation 26.
'im(max)
N3
N2
isw _ pospk(max)1 IOUT1
IOUT2
IOUT3
2.38 A
N1
N1
2
(24)
æN
ö æ 1 + Dmax ö Dim(min )
N
iSW _ negpk (max )1 = - ç 2 IOUT2 + 3 IOUT3 ÷ ç
+ IOUT1 = - 2.24 A
÷N1
2
è N1
ø è 1 - Dmax ø
æN
ö æ 2Dmax ö Dim(min )
N
iSW _ negpk (max )1 = - ç 2 IOUT2 + 3 IOUT3 ÷ ç
+ IOUT1 = - 1.24 A
÷N1
2
è N1
ø è 1 - Dmax ø
(25)
(26)
The primary output side is not always loaded, and without the primary load, the negative current is more
obvious. So consider the worst case, IOUT1 = 0 A, check the positive and negative primary winding peak
current again, as given by Equation 27, Equation 28, and Equation 29.
'im(max)
N3
N2
isw _ pospk(max)2
IOUT2
IOUT3
1.38 A
N1
N1
2
(27)
æN
ö æ 1 + Dmax ö Dim(min )
N
iSW _ negpk (max )2 = - ç 2 IOUT2 + 3 IOUT3 ÷ ç
= - 3.24 A
÷N1
2
è N1
ø è 1 - Dmax ø
æN
ö æ 2Dmax ö Dim(min )
N
iSW _ negpk (max )2 = - ç 2 IOUT2 + 3 IOUT3 ÷ ç
= - 2.24 A
÷N1
2
è N1
ø è 1 - Dmax ø
(28)
(29)
For the TPS54308, the minimum high-side source current limit, ILIMHS(min), is 4 A and the minimum lowside sink current limit, ILIMLSSOC(min), is 2.6 A. Therefore the positive and negative primary winding peak
current can meet the current requirements with the normal leakage of a transformer.
3.5
Primary Turns
A coupled inductor or a flyback-type transformer is required for flybuck topology. Calculate the minimum
primary turns for a flyback-type transformer using Equation 30.
Lpri ´ iSW _ pospk (max )1
N1 =
Bmax ´ A e
where
•
•
Bmax is the maximum flux density.
Ae is the effective core area of the chosen transformer.
(30)
In this design, the 750343683 inductor from Würth is selected for the transformer. Würth offers many other
flyback-type transformers and ready-made coupled inductors, in a variety of standard values, saturation
currents, and sizes.
3.6
Input and Output Capacitor
The input capacitor must be large enough to limit the input voltage ripple, see Equation 31.
N
N
IOUT1 + 2 IOUT2 + 3 IOUT3
(1 + 2.5 ´ 0.2 + 2.5 ´ 0.2 )A = 3.6 mF
N1
N1
CIN ³
=
8 ´ fSW ´ DVIN
8 ´ 350 kHz ´ 0.2 V
(31)
Choosing ΔVIN= 0.2 V gives a minimum of CIN= 3.6 μF. Considering derating, one standard value 10-μF,
35-V capacitor is selected for better input ripple performance. Another 0.1μF capacitor has been added as
a bypass capacitor to clear high-frequency noise.
Choosing ΔVOUT1= 0.05 V gives a minimum of COUT1= 28.5 μF. Considering derating, two standard value
22-μF, 16-V capacitors are selected to maintain a small voltage ripple.
Energy is transferred from primary to secondary when the synchronous switch of the buck converter is on.
The primary output capacitance is given by Equation 32:
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æ N2
ö
N
IOUT2 + 3 IOUT3 ÷ ´ Dmax
ç
N
N
(2.5 ´ 0.2 + 2.5 ´ 0.2 ) ´ 0.5 = 28.5 mF
ø
1
=
COUT1 ³ è 1
fSW ´ DVOUT1
350 kHz ´ 0.05 V
(32)
The secondary output current is sourced by COUT2 during TON. Ignoring the current transitions time in the
secondary winding, the value of the secondary output capacitor can be calculated using Equation 33:
I
´ Dmax
0.2 ´ 0.5
COUT2 = OUT2
=
= 2.9 mF
fSW ´ DVOUT2 350 kHz ´ 0.1 V
(33)
Choosing ΔVOUT2= 0.1 V gives a minimum of COUT2= 2.9 μF. Considering derating, a standard value 10-μF,
25-V capacitor is selected, the same as the COUT3.
3.7
Pre-Load
Pre-load is necessary to prevent VOUT2 and VOUT3 from going too high at light load. The required pre-load
current is usually set around 5 mA as a starting point, but it should be adjusted based on the circuit test
and application requirements. In this design, the pre-load resistor is selected as 2.2 kΩ for ±12-V outputs.
Users can use a Zener diode instead of the pre-load resistor to increase the transfer efficiency.
3.8
Factors Affecting Voltage Regulation
A flybuck converter regulates the primary output voltage with a closed-loop controller. The isolated output
is achieved by rectifying the secondary winding of the coupled inductor when the low side MOSFET is on.
Therefore the isolated output regulation is passive, affected by the winding leakage inductance, winding
resistances, diode drop, and low-side MOSFET, RDSON.
3.9
Avoiding Low-Side Sink Current Limit
In a flybuck application, the isolated output power rate may be limited by the low-side sink current limit.
Therefore, users must select design parameters elaborately to promote the isolated power rate. From
Equation 25 and Equation 26, we know that the key factors affecting the negative primary winding peak
current are Dmax, N2/N1, N3/N1, and the output current. The following tips are for trying to keep the margin:
1. Select a reasonable range of duty cycle. TI recommends a duty cycle ranging from 20% to 50% in
most cases. Users can reduce Dmax by setting a lower primary voltage or increasing the minimum input
voltage to increase the negative current margin.
2. Minimize the leakage inductance. Leakage inductance is a crucial factor determining the ramp rate of
the current in the secondary winding which charges the output capacitor. A nominal amount of leakage
is within 1% of primary inductance.
3. Pick the correct turns ratio. A lower turns ratio (isolated side to non-isolated side) results in a lower
reflected current in the primary winding.
4. Raise the non-isolated output power, which will reduce the negative winding peak current.
5. Reduce the isolated output power. This is the most direct way to lower the level of the negative
current.
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Experimental Results
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Experimental Results
Figure 5 through Figure 17 show the experimental test results of Figure 4.
100
95
Efficiency ( )
90
85
80
75
70
VIN = 10 V
VIN = 12 V
VIN = 16 V
VIN = 24 V
65
60
55
0
0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9
IOUT1 (A)
1
1.1 1.2
D001
Figure 5. Efficiency vs IOUT1 (IOUT1 = 0 A, IOUT2 = 0 A)
90
85
80
Efficiency ( )
75
70
65
60
55
VIN = 10 V
VIN = 12 V
VIN = 16 V
VIN = 24 V
50
45
40
0
20
40
60
80 100 120
IOUT2 (mA)
140
160
180
200
D002
Figure 6. Efficiency vs IOUT2 (IOUT1 = 0 A, IOUT3 = 0 A)
90
85
80
Efficiency ( )
75
70
65
60
55
VIN = 10 V
VIN = 12 V
VIN = 16 V
VIN = 24 V
50
45
40
0
20
40
60
80 100 120
IOUT3 (mA)
140
160
180
200
D003
Figure 7. Efficiency vs IOUT3 (IOUT1 = 0 A, IOUT2 = 0 A)
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Experimental Results
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15
VIN = 10 V
VIN = 12 V
VIN = 16 V
VIN = 24 V
14.5
VOUT2 (V)
14
13.5
13
12.5
12
11.5
0
20
40
60
80 100 120
IOUT2 (mA)
140
160
180
200
D004
Figure 8. VOUT2 Regulation vs IOUT2 (IOUT1 = 0 A, IOUT3 = 0 A)
15
VIN = 10 V
VIN = 12 V
VIN = 16 V
VIN = 24 V
14.5
VOUT3 (V)
14
13.5
13
12.5
12
11.5
0
20
40
60
80 100 120
IOUT3 (mA)
140
160
180
200
D005
Figure 9. VOUT3 Regulation vs IOUT3 (IOUT1 = 0 A, IOUT2 = 0 A)
15
IOUT2 = 0 A
IOUT2 = 10 mA
IOUT2 = 80 mA
IOUT2 = 150 mA
14.5
VOUT2 (V)
14
13.5
13
12.5
12
11.5
10 11 12 13 14 15 16 17 18 19 20 21 22 23 24
VIN (V)
D006
Figure 10. VOUT2 Regulation vs VIN (IOUT1 = 0 A, IOUT3 = 0 A)
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Experimental Results
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15
14.5
VOUT2 (V)
14
IOUT2 = 0 A
IOUT2 = 10 mA
IOUT2 = 80 mA
IOUT2 = 150 mA
13.5
13
12.5
12
11.5
10 11 12 13 14 15 16 17 18 19 20 21 22 23 24
VIN (V)
D007
Figure 11. VOUT3 Regulation vs VIN (IOUT1 = 0 A, IOUT2 = 0 A)
Figure 12. Steady State Waveforms (VIN = 10 V, IOUT1 = 1 A, IOUT2 = 0.2 A, and IOUT3 = 0.2 A)
Figure 13. Steady State Waveforms (VIN = 10 V, IOUT1 = 0 A, IOUT2 = 0.2 A, and IOUT3 = 0.2 A)
12
Designing a Simple and Low-Cost Flybuck Solution With the TPS54308
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Experimental Results
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Figure 14. Ripple Voltage Waveforms (VIN = 10 V, IOUT1 = 1 A, IOUT2 = 0.2 A, and IOUT3 = 0.2 A)
Figure 15. Load Step Response 50 mA to 200 mA (VIN = 10 V, IOUT1 = 0 A, and IOUT3 = 0 A)
Figure 16. Line Step Response 10 V to 24 V (IOUT1 = 1 A, IOUT2 = 0.2 A, and IOUT3 = 0.2 A)
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Conclusion
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Figure 17. Power Up (VIN = 10 V, IOUT1 = 1 A, IOUT2 = 0.2 A, and IOUT3 = 0.2 A)
5
Conclusion
This application report presented the operating principles of a flybuck converter, showed typical operating
current and voltage waveforms, and provided a detailed, step-by-step design example which explained
how to select the external components. Data and waveforms tested based on the example design show
that the flybuck can support a simple, small, and cost effective power solution, making it suitable as a
flyback alternative, and the TPS54308 makes the advantage more obvious.
6
References
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Texas Instruments, TPS54308: 4.5-V to 28-V Input, 3-A Output, Synchronous 350-kHz FCCM StepDown Converter in SOT23 Package , data sheet
Texas Instruments, Designing an Isolated Buck (Flybuck) Converter, application report
Texas Instruments, Design a Flybuck Solution With Optocoupler to Improve Regulation Performance
Create an Inverting Power Supply, application report
Texas Instruments, Creating a Split-Rail Power Supply With a Wide Input Voltage Buck Regulator,
application report
Designing a Simple and Low-Cost Flybuck Solution With the TPS54308
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Revision History
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Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Original (August 2017) to A Revision ..................................................................................................... Page
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•
Changed Equation 6 to Equation 21 for the maximum magnetizing current ripple calculation in Section 3.4section .......
Changed Ipri(min), Iprito Lpri(min), Lpriin Equation 22, 23. ....................................................................................
Changed the values of Equation 24, 27 ................................................................................................
Changed Change ΔVOUT1 to ΔVOUT2in Section 3.6section .............................................................................
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Revision History
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