Texas Instruments | Understanding the Start-up Behavior of the TPS61178x (Rev. A) | Application notes | Texas Instruments Understanding the Start-up Behavior of the TPS61178x (Rev. A) Application notes

Texas Instruments Understanding the Start-up Behavior of the TPS61178x (Rev. A) Application notes
Application Report
SLVA940A – December 2017 – Revised April 2019
Understanding the Start-up Behavior of the TPS61178x
Jasper Li
ABSTRACT
This application report details the start-up behavior of the TPS61178x device. It also characterizes the
start-up timing and proposes a method to reduce the start-up inrush current. The proposed method is
confirmed by bench test measurements.
1
2
3
Contents
Introduction ................................................................................................................... 2
Start-up Behavior Description .............................................................................................. 2
Summary ...................................................................................................................... 5
List of Figures
1
Typical Schematic of TPS61178x ......................................................................................... 2
2
Start-up Waveform of the TPS61178 EVM at VIN = 7.2 V .............................................................. 3
3
P-FET Driving Circuitry
4
Start-up Waveform at CGATE = 47 nF ....................................................................................... 4
5
Method to Reduce the Start-up Current .................................................................................. 4
6
Start-up Waveform With Proposed Method .............................................................................. 5
.....................................................................................................
3
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SLVA940A – December 2017 – Revised April 2019
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1
Introduction
1
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Introduction
For the conventional synchronous boost converter, the output voltage follows the input voltage when the
converter is disabled. This behavior increases power loss due to the leakage current flowing through the
feedback divider and the post-load. The TPS61178x device is a 20-V, 10-A boost converter that integrates
a circuitry to drive an external P-FET to isolate the output side from the input side. Figure 1 shows a
typical schematic of the TPS61178x. Because the output voltage drops to zero after the TPS61178x shuts
down, the leakage current in the output also decreases to zero. The start-up circuitry of TPS61178x is
designed to prevent the power supply from overloading when output voltage increases from zero to the
setting value.
L
VIN
CIN
VIN
BST
VCC
CVCC
CBST
SW
TPS61178
ON
OFF
COUT1
FREQ /
SYNC
RFreq
VOUT
VOUT2
P-FET
VOUT
EN
RGATE CGATE
RUP
COUT2
DISDRV
RDOWN
FB
ILIMIT
RLIMIT
AGND
COMP
PGND
Cc
Cp
RC
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Figure 1. Typical Schematic of TPS61178x
2
Start-up Behavior Description
The start-up procedure of the TPS61178x device is divided into precharge phase and soft-start phase.
The precharge phase is the period when the output voltage (VOUT2) increases from zero to 10% higher
than VIN (1.1 × VIN); the soft-start phase is the period from 1.1 × VIN to the setting output voltage.
Figure 2 shows the start-up waveform measured in TPS61178x evaluation module (EVM) at 7.2-V input
voltage. In the waveform, CH1 is VOUT2 (after P-FET) shown in Figure 1; CH2 is the TPS61178x VOUT
pin (before P-FET); CH3 is the EN pin voltage; and CH4 is the input current of the boost converter. The
behavior of the waveform is explained as follows:
• Before t0, the EN pin is logic low, and the TPS61178x shuts down. The voltage at the VOUT pin is
(VIN – VD), where VD is the body diode voltage. The DISDRV pin is in high impedance to turn off the
external P-FET.
• At t0, the EN pin becomes logic high. After a short delay, the TPS61178x starts switching and boosts
the voltage at the VOUT pin to 1.1 × VIN. At the same time, the DISDRV pin discharges to ground with
a typical 55-µA current source, as shown in Figure 3. The gate-to-source voltage VGS of the P-FET
decreases. The slew rate is determined by Equation 1, where IGATE is typical 55 µA; τ is RGATE × CGATE.
V GS
•
2
I GATE u R GATE
§
¨1
©
e
t
W
·
¸
¹
(1)
At t1, the VGS becomes lower than the threshold voltage of the P-FET. The P-FET turns on, and
charges the output capacitor to 1.1 × VIN.
Understanding the Start-up Behavior of the TPS61178x
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Start-up Behavior Description
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•
At t2, the precharge phase finishes and the device enters soft-start phase. The period from t0 to t2 is
called precharge phase, which is approximately 2.6 ms. After t2, the rising rate of the FB pin voltage is
internally controlled by Equation 2, where VREF is typical 1.198 V and tstartup is typical 3.2 ms
V FBSS
•
V REF
t startup
(2)
At t3, the FB voltage reaches 1.198 V, and the soft-start phase finishes. The period from t2 to t3 can be
calculated by Equation 3, where VOSET is the setting output voltage.
t boost _ SS
§
t startup u ¨ 1
¨
©
·
¸
u V REF ¸¹
1.1 u VIN u R DOWN
R UP
R DOWN
t startup u
1.1 u VIN
V OSET
V OSET
(3)
VOUT2 (5V/div)
VOUT (5V/div)
EN (2V/div)
IIN (2V/div)
t
t
t
t
0
1
2
3
Figure 2. Start-up Waveform of the TPS61178 EVM at VIN = 7.2 V
VOUT
COUT1
P-FET
VGS
RGATE
VOUT_2
COUT2
CGATE
DISDRV
IGATE
Figure 3. P-FET Driving Circuitry
The RGATE in Figure 3 is used to clamp the VGS not higher than -IGATE × RGATE. Make sure the |VGS | is high
enough to drive the P-FET while lower than the maximum voltage rating. In the TPS61178x EVM, the
RGATE is 100 kΩ to get –5.5 V for the CSD25404Q3.
In the precharge phase, an inrush current charges the output capacitor when the P-FET turns on.
Increasing the CGATE can reduce the charging current because the VGS slope rate becomes slower.
However, the P-FET must effectively turn on before the precharge phase finishes, otherwise the output
voltage will be out of control as the FB pin voltage comes from VOUT2. Taking CSD25404Q3 as example,
this MOSFET effectively turns on at VGS = –1.5 V from its “Transfer Characteristics”. Therefore, the VGS
should be lower than –1.5 V before the precharge phase finishes. Because the minimum precharge time is
1.8 ms, the maximum CGATE can be calculated by Equation 4
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3
Start-up Behavior Description
C GATE _ MAX
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t PRE _ CHARGE
§
ln ¨ 1
¨
©
·
¸ u R GATE
u R GATE ¸¹
VGS
I GATE
§
ln ¨ 1
©
1.8 m
·
1.5
u 100 k
55 P u 100 k ¹¸
56 nF
(4)
As showed in Figure 4, the inrush current during the precharge phase reduces to 2 A if the CGATE
increases from 22 nF to 47 nF, and the P-FET fully turns on within 1.8 ms.
VOUT2 (5V/div)
VOUT (5V/div)
EN (2V/div)
IIN (2V/div)
Figure 4. Start-up Waveform at CGATE = 47 nF
To increase CGATE further, add a resistor in series with CGATE, as shown in Figure 5. When the TPS61178x
is enabled and the voltage of CGATE is zero, the VGS is defined by Equation 5. As the minimum threshold
voltage of the CSD25404Q3 is 0.65 V, the RG_A is set to approximately 13.4 kΩ to void the P-FET turning
on at the beginning.
P-FET
VOUT
COUT1
VGS
VOUT_2
COUT2
RGATE
CGATE
RG_A
DISDRV
IGATE
Figure 5. Method to Reduce the Start-up Current
V GS
4
I GATE
R GATE u R G _ A
R GATE
R G_A
Understanding the Start-up Behavior of the TPS61178x
(5)
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Summary
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After adding RG_A, the VGS is defined by Equation 6 after the TPS61178x is enabled, where τ is (RG_A +
RGATE) × CGATE. The maximum value of CGATE can be calculated by Equation 7.
V GS
I GATE
§
u R GATE ¨ 1
©
e
t
W
·
¸
¹
I GATE u R GATE e
t
W
u
R G_ A
R GATE
R G_ A
(6)
t PRE _ CHARGE
C GATE _ MAX
§V
I GATE u R GATE R GATE R G _ A ·
u
ln ¨ GS
¸¸ u R GATE
¨
I GATE u R GATE
R GATE
©
¹
1.8 m
§ 1.5 55 P u 100 k 100 k 13.4 k ·
ln ¨
u
¸ u 100 k u 13.4 k
55 P u 100 k
100 k
©
¹
R G_ A
82 nF
(7)
Selecting the RG_A to be 13.4k and CGATE to be 68 nF, the start-up waveform is shown in Figure 6. The
input inrush current reduces to 1.5 A, and the P-FET fully turns on within 1.8 ms after the EN pin becomes
logic high.
VOUT2 (5V/div)
VOUT (5V/div)
EN (2V/div)
IIN (2V/div)
Figure 6. Start-up Waveform With Proposed Method
3
Summary
This application report described the soft-start timing and behavior of the TPS61178x device. Theoretic
analysis and bench tests show that the input inrush current during start-up is determined by the driver
circuitry of the external P-FET. Suitable selection of the circuitry components can help reduce the inrush
current.
SLVA940A – December 2017 – Revised April 2019
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Understanding the Start-up Behavior of the TPS61178x
Copyright © 2017–2019, Texas Instruments Incorporated
5
Revision History
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Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Original (December 2017) to A Revision ................................................................................................ Page
•
•
6
Changed "1n" to "ln" in Equation 4...................................................................................................... 3
Changed "1n" to "ln" in Equation 7...................................................................................................... 5
Revision History
SLVA940A – December 2017 – Revised April 2019
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