Texas Instruments | Simple Solution for EMI Filter Stability Issue in DC/DC Converters (Rev. A) | Application notes | Texas Instruments Simple Solution for EMI Filter Stability Issue in DC/DC Converters (Rev. A) Application notes

Texas Instruments Simple Solution for EMI Filter Stability Issue in DC/DC Converters (Rev. A) Application notes
Application Report
SLUA929A – April 2019 – Revised April 2019
Simple Solution for Input Filter Stability Issue in DC/DC
Converters
Zhang, Hao
ABSTRACT
Input filters are a common solution to conducted EMI challenges in DC/DC converters. The most common
form of EMI input filter is a simple π-type filter consisting of two capacitors and one inductor. The filter can
significantly attenuate the harmonics on the input power line, which means better conducted EMI
performance. It is well-known that the component values depend on the expected attenuation. However,
there must be more considerations since inappropriate values can cause oscillation on the input. Through
the introduction of a real-world design scenario, this application report shows the input oscillation
phenomenon, analyzes why the loop becomes unstable after applying the input filter, and discusses
methods to fix this issue.
1
2
3
4
5
Contents
Introduction ................................................................................................................... 2
Instability Analysis ........................................................................................................... 3
How to Fix Input Filter Stability Issue .................................................................................... 12
Summary .................................................................................................................... 15
References .................................................................................................................. 15
List of Figures
1
Schematic of LMR14050 Application Circuit with EMI filter (Vout = 5 V, Iout_max = 5 A) ............................... 2
2
Operating Waveform at VIN = 9 V, Iout = 5 A Without Input Filter ..................................................... 2
3
Operating Waveform at VIN = 9 V, Iout = 5 A with Input Filter .......................................................... 3
4
Input Port Power Characteristic of DC/DC Converter ................................................................... 3
5
Small Voltage Change Dividing at Entry of DC/DC Converter with Input Filter
6
Typical Block Diagram of PCM Control Loop ............................................................................ 5
7
Bode Plot by MATLAB Modeling (VIN = 9 V, Vout = 5 V, Iout = 5 A) ................................................ 7
8
Bode Plot by Bench Test (VIN = 9 V, Vout = 5 V, Iout = 5 A)
9
10
11
12
13
14
15
16
17
18
19
20
.....................................
4
............................................................ 7
Simple π-type Input Filter ................................................................................................... 7
Small Signal Equivalent Circuit Model for PCM DC/DC Circuitry ..................................................... 8
Plot of |Zo(s)|, |Zd(s)| and |Zn(s)| .......................................................................................... 9
Bode Plot of π-type Filter Correction Factor ............................................................................ 10
Bode Plot of Whole Open Loop Transfer Function with Input Filter ................................................. 11
Bode Plot Bench Test Result VIN = 9 V, Vout = 5 V, Iout = 2 A ........................................................ 12
Bode Plot Bench Test Result at VIN = 9 V, Vout = 5 V, Iout = 3 A ..................................................... 12
Damping the Filter Output Impedance .................................................................................. 12
Bode plot for |ZO(s)|, |ZD(s)| and |ZN(s)| with Damp .................................................................... 13
Bode Plot of Correction Factor w, Without Damp ...................................................................... 14
Operating Waveforms by Adding an Electrolytic Capacitor at VIN = 9 V, Iout = 5 A ............................... 14
Loop Bode Plot by Adding an Electrolytic Capacitor at VIN = 9 V, Iout = 5 A ....................................... 15
List of Tables
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1
Introduction
1
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LMR14050 Internal Loop Parameters ..................................................................................... 6
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1
Introduction
LMR14050 is a 4-V to 40-V wide input voltage 5-A step down DC/DC converter. The schematic shown in
Figure 1 is designed to output 5 V at 5-A full loading based on the LMR14050. For better EMC
performance, a π-type input filter is applied on the input line.
Figure 1. Schematic of LMR14050 Application Circuit with EMI filter (Vout = 5 V, Iout_max = 5 A)
When the 9-V input voltage is applied across TP1 and TP2,(when the input filter is not involved in the
circuitry), it worked well as shown in Figure 2. When the input is applied on input terminal J1, the circuit
can work normally with the input filter in light loads. However, when the load current exceeded 3.5 A, the
circuit went unstable. Figure 3 shows the input oscillation clearly with bench test waveform.
Figure 2. Operating Waveform at VIN = 9 V, Iout = 5 A Without Input Filter
2
Simple Solution for Input Filter Stability Issue in DC/DC Converters
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Figure 3. Operating Waveform at VIN = 9 V, Iout = 5 A with Input Filter
By comparing the waveforms before and after applying the EMI input filter, the problem was addressed as
an instability issue caused by the filter. It is clear that the poorly designed EMI input filter led to a stability
issue under some specific operating conditions. This application report aims at revealing this kind of
instability phenomenon, analyzing the root cause, and providing solutions for the stability issue caused by
π-type EMI filter.
2
Instability Analysis
2.1
Increment Input Impedance of dc/dc Converter
Before any DC/DC modeling effort and mathematical induction, try to understand the issue by intuition.
For the input power PIN and output power POUT of DC/DC converter, you have:
Pout K ˜ Pin
(1)
Expend PIN and POUT and you have:
Vout ˜ Iout K˜ Vin ˜ Iin
(2)
In a normal operation, the converter always keeps the VOUT constant. IOUT is also constant as long as the
load condition is unchanged. Figure 4 shows the input port power characteristic of the DC/DC converter.
IIN
slope
Öi
op
vÖ op
1/ (Increment impedance)
Steady
operating point
VIN
Figure 4. Input Port Power Characteristic of DC/DC Converter
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Instability Analysis
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When VIN rises up, supposing there is not much change on efficiency, input current IIN decreases. The
increment input impedance of the DC/DC, is defined as:
'Vin
Zinc
'Iin
(3)
In the equation, ∆Vin is positive, while ∆Iin is negative, so the increment input impedance is actually a
negative value. Keep in mind that it is increment input impedance, which is only applicable for AC small
signal analysis.
With an input filter, small input voltage change observed at the entry of the converter is decided by simple
voltage dividing between output impedance of the filter and input impedance of the converter, as shown in
Figure 5.
Z filter
VÖ source
(Output impedance of
the input filter)
VÖ in
DC/DC
Output
+
Input Filter
±
GND
ZDC _ DC
(Increment input impedance
of the dc/dc converter)
Figure 5. Small Voltage Change Dividing at Entry of DC/DC Converter with Input Filter
Ö are the small signal of power supply voltage and input voltage observed by the
Ö
Suppose V
and V
source
in
DC/DC converter, respectively.
Taking the positive and negative sign into consideration, you have:
Z
in
VÖ in VÖ source ˜
Z filter Zin
(4)
This means, if there is a positive disturbance on Vsource, the input voltage change observed by the C/DC
Ö can be negative, as long as |Zfilter| > |Zdc/dc|.
converter V
in
Physically, when VIN ramps up, from the view of steady state, the DC/DC converter must decrease the
duty cycle to maintain the voltage regulation. Equation 4 shows entry voltage of the DC/DC converter is
decreasing, so the converter tends to increase the duty cycle to keep the output voltage stable. It is
something like the DC/DC converter control loop is "cheated" by the division in Equation 4. The loop is too
confused to decrease or increase the duty cycle. This dilemma is the root cause for the stability issue
when input filter is involved in DC/DC converter circuitry.
2.2
PCM Control Loop Modeling
To analyze how the input filter affects the control loop theoretically, obtain the loop model first. Figure 6
shows the typical block diagram of the PCM control loop. Usually, the control loop model of DC/DC
converter can be split into two parts. One is power stage and the other is feedback stage. By multiplying
them together, the open loop transfer function can be obtained.
4
Simple Solution for Input Filter Stability Issue in DC/DC Converters
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To Feedback
RFBT
VIN
Error Amp
Power Stage
±
RFBB
+
Vc
Vref
Comparator
±
Ccomp
d
GND
Croll
Type II
Compensation
Network
S
VOUT
Control
Logic
&
Gate Driver
R
+
Q
Rcomp
L
Cout
Rc
Clock
Vramp
Ro
+
GND
Ri
Feedback Stage
Slope Compensation
GND
Current Sense Gain
Figure 6. Typical Block Diagram of PCM Control Loop
Ö to VÖ )
In the power stage, the LMR14050 employs peak current mode control. The control to output (V
c
out
transfers function for peak current mode control is:
vÖ o
Ro
(1 Zz )
Gdv (s)
˜
Ro
vÖ c
(1 Zp ) ˜ (1 ZL )
Ri ˜ (1
)
K m ˜ Ri
where
•
•
•
Ro is the loading resistance
Ri is the current sensing gain in the current loop
Km is the modulator voltage gain
(5)
This is given by:
VIN
Km
(Se Sn ) ˜ Ts
where
•
Se is the slew rate for slope compensation which is design fixed inside the IC
•
Sn is the slew rate of current sense signal, which is given by Sn
Ri ˜
VIN
VO
(6)
L
ωz is the zero formed by output capacitor ESR and output capacitance, ωp is the dominant pole formed by
loading resistance and capacitance, ωL is the inductor pole at the frequency where the inductor impedance
equals the current loop gain. These zero and poles are given by:
1
Zz
ESR ˜ Cout
Zp
1
Ro ˜ Cout
ZL
K m ˜ Ri
L
(7)
In the feedback path, the LMR14050 employs a type II compensation network with a trans-conductance
Ö
error amplifier. The transfer function from V
out
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Ö is:
to V
c
Simple Solution for Input Filter Stability Issue in DC/DC Converters
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Instability Analysis
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vÖ c
vÖ o
Gvd (s)
1
ADC ˜
(1
s
Zz1
s
s
) ˜ (1
)
Zp1
Zp2
where
Vout
(8)
Vin
wz1 is the zero formed by Rcomp and Ccomp. wp1 is the pole formed by Rea and Ccomp, wp2 is the pole formed
by Rcomp and Croll. The zero and poles are given by:
1
Zz1
Rcomp ˜ Ccomp
•
ADC is the DC gain of the feedback network given by
Zp1
1
REA ˜ Ccomp
Zp2
1
Rcomp ˜ Croll
ADC
REA ˜ gmEA ˜
(9)
The open loop transfer function can be obtained by multiplying the transfer function of power stage and
feedback. It can be written as:
s
s
(1
)
1
Ro
Zz
Zz1
˜
˜
G(s) ADC ˜
Ro
s
s
s
s
) ˜ (1
) (1
) ˜ (1
)
Ri ˜ (1
) (1
Zp
ZL
Zp1
Zp2
Km ˜ Ri
(10)
Table 1 lists some of the internal loop parameters of the LMR14050. For other parameters needed for
modeling, refer to the schematic in Figure 1.
Table 1. LMR14050 Internal Loop Parameters
6
PARAMETERS
DESCRIPTION
VALUE
gmEA
Trans-conductance amplifier gain
45 µA/V
REA
Trans-conductance amplifier output equivalent resistance
10.5 MΩ
CEA
Trans-conductance amplifier equivalent capacitance
400 fF
Ri
Current sense gain
0.196 Ω
Km
Modulator voltage gain (at working condition described in
Section 1)
25.2
Simple Solution for Input Filter Stability Issue in DC/DC Converters
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By substituting the parameters listed in Figure 1 and Table 1, the bode plot of the open loop transfer
function is drawn in Figure 7 (all the bode plots in this note are done with MATLAB R2017a). Figure 8
shows the bench test result for verification.
75
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-25
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1x102
2x102
5x102
1x103
2x103
5x103
1x104
2x104
Frequency /Hz
5x104
1x105
2x105
5x105
Phase margin /degree
Gain /dB
Figure 7. Bode Plot by MATLAB Modeling (VIN = 9 V, Vout = 5 V, Iout = 5 A)
-180
1x106
Figure 8. Bode Plot by Bench Test (VIN = 9 V, Vout = 5 V, Iout = 5 A)
2.3
Middlebrook’s Extra Element Theorem
The starting point to look into the impact of applying the EMI filter is Middlebrook’s extra element theorem.
Figure 9 shows a simple π-type input filter.
Input Power
L
DCRL
To DC/DC
C1
C2
ESRC1
ESRC2
GND
GND
Figure 9. Simple π-type Input Filter
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The input filter can be regard as an extra element of the converter circuit. According to the theorem, the
extra element changes the circuit loop characteristic, and the impact can be described by introducing a
correction factor into the original control to output transfer function of the circuit:
Zo _ filter (s)
1
ZN (s)
Gvd (s) Gvd (s) Zo _ filter (s) 0 ˜
Zo _ filter (s)
1
ZD (s)
where
•
•
Gvd(s)|Zo_filter(s)=0 is the original control to output transfer function without input filter
Zo_filter(s) is the output impedance of the input filter and is given by
(11)
ZD(s) is the open loop input impedance of the DC/DC circuit, while ZN(s) is the closed loop input
impedance. For the detail expression of ZD(s) and ZN(s), Ridley’s small signal equivalent circuit model
needs to be referred, as Figure 10 illustrated.
Power stage
Öi
in
ZD (s)
Zi (s) |dÖ
-
0
vÖ in +±
vÖ o
L
Vin ˜ dÖ
1:D
Zi (s)
Öi
L
+
Cout
Ro
Ri
IL ˜ dÖ
Rc
ZN (s)
Zi (s) |vÖ
in o 0
PWM
modulator
GND
dÖ
K
Feedback
Network
Fm
+
Sampling
Effect
He(s)*
vÖ c
Compensation
Network
-Av(s)
* Sampling effect can be described as two zeros at half switching frequency, which is much higher than bandwidth, so this
item is ignored in the following discussion.
Figure 10. Small Signal Equivalent Circuit Model for PCM DC/DC Circuitry
ZD(s) represents the open loop input impedance of the dc/dc circuit, defined by:
ZD (s) Zi (S) |dÖ 0
where
•
•
Zi(s) is the input impedance of the DC/DC circuit
d̂ is the small signal of duty cycle
(12)
As the open loop condition, by setting d̂ =0, you have:
1
ZD (s)
˜ [ZL (s) Zo (s)]
D2
where
•
•
ZL(s) is the inductor impedance
ZO(s) is the impedance of Cout and Ro
(13)
They are given by:
8
Simple Solution for Input Filter Stability Issue in DC/DC Converters
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(14)
ZN(s) is the closed loop input impedance of the dc/dc circuit, defined by:
ZN (s) Zi (S) |vÖ 0
in
where
•
vÖ in is the small signal of input voltage
In the simplified model (but accurate enough for the analysis here), it is given by:
Ro
ZN (s)
D2
(15)
(16)
It must be noted that the accurate ZN(s) in current mode control loop is quite complicated and different
from the voltage mode control loop. For readers who are interested in accurate see the Understanding
and Applying Current-mode Control Theory Application Report for information on accurate ZN(s)
expression in the PCM circuit.
In the situation where the oscillation happened, by substituting the variables with parameters in Figure 1
and Table 1, |Zd(s)| and |Zn(s)| are plotted out in Figure 11.
|Zo(s)|
|ZD(s)|
|ZN(s)|
Figure 11. Plot of |Zo(s)|, |Zd(s)| and |Zn(s)|
The transfer function of correction factor can be written as:
Zo _ filter (s)
1
ZN (s)
Correction _ factor
Zo _ filter (s)
1
ZD (s)
(17)
Figure 12 shows the bode plot for the correction factor.
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Figure 12. Bode Plot of π-type Filter Correction Factor
Fluctuation can be recognized on both gain and phase curve around the L-C resonant frequency of input
filter. This is because the correction factor includes two poles and two right half plane zeros, so it shows a
dip and then a quick recovery around the input filter resonant frequency on the gain curve. While on the
phase curve, due to the zeros are in right half plane, it shows a 360⁰ degree phase shift in total.
The additional poles and zeros are further introduced into the control loop of the DC/DC circuitry.
According to the stability criterion for bode plot, a loop is stable only when it has a positive phase margin
at the frequency where gain curve crosses the zero. The fluctuation around input filter resonant frequency
may lead to violation to the stability criterion. In Section 2.4, you see how the corrector affects the DC/DC
circuitry.
2.4
Open Loop Transfer Function with Input Filter
Combining the control-to output-power stage together with the feedback stage, you are able to do the
bode plot for entire loop with the π-type input filter as Figure 13.
10
Simple Solution for Input Filter Stability Issue in DC/DC Converters
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Figure 13. Bode Plot of Whole Open Loop Transfer Function with Input Filter
Compared with the bode plot with input filter shown in docato-extra-info-title (a) Bode plot by MATLAB
modeling(b) Bode plot by bench test Figure 8, the additional poles and zeros introduced by the π type
input filter changed the bode plot so much, that the loop no longer meets the stability criterion. The
fluctuation on the gain curve changed the gain curve crossover frequency and slew rate at the crossover
point. Phase shift also happened at the same frequency range, which made the situation even worse.
Judging from Equation 17, when the following inequalities are satisfied, the magnitude of correction factor
is more close to unity and the phase shift is smaller, then the less effect brought by the input filter.
| Zo (s) | | ZD (s) |
| Zo (s) |
| ZN (s) |
(18)
In other words, the high magnitude of |ZD(s)| and |ZN(s)| makes the loop tend to be unstable. By reviewing
the expression of ZN(s) in Equation 19, |ZN(s)| tends to decrease with a higher loading current and larger
duty cycle, so it is more difficult to satisfy the inequalities in Equation 18.
Ro
ZN (s)
(19)
D2
That is why the instability issue is more likely to happen under heavy loading and large duty cycle
condition after applying the poorly designed π-type input filter.
Actually, the issue described in Section 1 did not happen until the loading increased to 4 A. Figure 14 and
Figure 15 show the bench test result at 2 A and 3 A loading. It can be seen that the loop is being closer
and closer to unstable as the loading current increases.
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0
0
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1x102
2x102
5x102
1x103
2x103
5x103
1x104
2x104
Frequency /Hz
5x104
1x105
2x105
5x105
Phase margin /degree
Gain /dB
How to Fix Input Filter Stability Issue
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1x106
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-25
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2x103
5x103
1x104
2x104
Frequency /Hz
5x104
1x105
2x105
5x105
Phase margin /degree
Gain /dB
Figure 14. Bode Plot Bench Test Result VIN = 9 V, Vout = 5 V, Iout = 2 A
-180
1x106
Figure 15. Bode Plot Bench Test Result at VIN = 9 V, Vout = 5 V, Iout = 3 A
3
How to Fix Input Filter Stability Issue
Based on previous discussion, it is known that there is sudden change on both the gain and phase curve
around the resonant frequency of Lfilter and Cfilter (the capacitor close to DC/DC input). The basic principle
to avoid the stability issue is to minimize the impact of correction factor introduced by the input filter. This
can be done from two perspectives as shown in Figure 16.
Input Power
L
Solution B1:
Singal Electrolytic Capacitor
DCRL
C1
To DC/DC
C2
Cdamp
ESRC1
ESRC2
or
Cdamp
ESR
Rdamp
GND
Solution A:
Keep filter resonant
frequency away from
that in power stage
GND
GND
GND
Solution B2:
Ceramic Capacitor + Resistor
Figure 16. Damping the Filter Output Impedance
12
Simple Solution for Input Filter Stability Issue in DC/DC Converters
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Keep the resonant frequency of the filter away from the crossover frequency of the DC/DC loop. This
leaves more margin for the gain dip and phase shift around the resonant frequency of the filter, and
makes sure that the fluctuating gain and phase does not violate the stability criterion.
From the perspective of Equation 18, decreasing the output impedance of the filter is another way to solve
the problem. The simplest way to fix the issue is to apply a resistor in mid-frequency in parallel with the C2
in Figure 16 to damp the resonant of the input filter. This can be implemented by putting a capacitor with
large ESR (such as electrolytic capacitor) in parallel with C2. The capacitance is used to block the DC
power dissipation, and the ESR is used to damp filter output impedance in mid-frequency. For some
solution size sensitive or height limited applications, an electrolytic capacitor might be too large to be
assembled on the PCB board. A ceramic capacitor in series with a small resistor can be a good choice. By
doing this, |ZO| has a smaller value in mid-frequency, making the correction factor more close to unified
gain. Figure 17 shows the relationship among damped |ZO(s)|, |ZD(s)| and |ZN(s)| by adding a 47µF, 100
mΩ electrolytic capacitor. Figure 18 shows the comparison of the correction factor bode plots with and
without the damp.
Figure 17. Bode plot for |ZO(s)|, |ZD(s)| and |ZN(s)| with Damp
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Figure 18. Bode Plot of Correction Factor w, Without Damp
Figure 19 and Figure 20 show the operating waveforms and loop characteristic by applying a 47 µF
electrolytic capacitor with 100 mΩ ESR. With this solution, the DC/DC converter circuit in Figure 1 can
work well with any loading condition now.
Figure 19. Operating Waveforms by Adding an Electrolytic Capacitor at VIN = 9 V, Iout = 5 A
14
Simple Solution for Input Filter Stability Issue in DC/DC Converters
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Summary
75
180
50
120
25
60
0
0
-25
-60
-50
-120
-75
1x102
2x102
5x102
1x103
2x103
5x103
1x104
2x104
Frequency /Hz
5x104
1x105
2x105
5x105
Phase margin /degree
Gain /dB
www.ti.com
-180
1x106
Figure 20. Loop Bode Plot by Adding an Electrolytic Capacitor at VIN = 9 V, Iout = 5 A
4
Summary
When designing an input filter for a DC/DC circuit, component values are sometimes selected only by the
calculation to get the needed attenuation. Actually it is not enough. This application report shows an input
oscillation example caused by a poorly designed input filter and provides insights to the instability and the
solutions for this kind of issue.
5
References
•
•
•
•
•
Texas Instruments, 40 V, 5 A SIMPLE SWITCHER, 2.2 MHz Step-Down Regulator with 40 μA IQ Data
Sheet
Texas Instruments, Current-Mode Modeling for Peak, Valley and Emulated Control Methods
Application Report
Fundamentals of Power Electronics, Second Edition, by Robert W. Erickson and Dragan Maksimovic.
Texas Instruments, Analysis and Design of Input Filter for DC-DC Circuit Application Report
A New Small Signal Model for Current Mode Control, by Raymond B. Ridley
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Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Original (April 2019) to A Revision .......................................................................................................... Page
•
16
Updated the application report for clarity. .............................................................................................. 1
Revision History
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