Texas Instruments | Loop Response Considerations in Peak Current Mode Buck Converter Design (Rev. A) | Application notes | Texas Instruments Loop Response Considerations in Peak Current Mode Buck Converter Design (Rev. A) Application notes

Texas Instruments Loop Response Considerations in Peak Current Mode Buck Converter Design (Rev. A) Application notes
Application Report
SLVAE09A – July 2018 – Revised April 2019
Loop Response Considerations in Peak Current Mode
Buck Converter Design
Neal Zhang, Daniel Li
ABSTRACT
The internal loop compensated Peak Current Mode (PCM) buck converter is popular. The loop response
is good for normal inductor and output capacitor design, but improper inductor and output capacitor values
can lead to instability or bad transient performance. This application report details the PCM buck
converter, analyzes the stability constraint, and provides a simple equation to calculate bandwidth and
phase margin of the converter.
The model proposed in this application report is introduced in Section 1. Section 2 provides peak current
mode loop modeling. The inside current loop is simplified as a single pole. The overall loop response
transfer function is obtained. The inductor and output capacitor design limits are derived considering loop
response. At the end of this section, the equation to calculate bandwidth and phase margin is provided. In
Section 3, the inductor and output capacitor is designed step-by-step considering loop response. The
theory is verified by simulation and bench measurement results.
1
2
3
4
5
Contents
Introduction ................................................................................................................... 2
Peak Current Mode Loop Modeling ...................................................................................... 2
Inductor and Output Capacitor Design ................................................................................... 6
Summary ................................................................................................................... 10
References .................................................................................................................. 10
List of Figures
1
Simplified Schematic for PCM Buck Converter .......................................................................... 2
2
Overall Control Implementation ............................................................................................ 2
3
Bode Plot Model for PCM Buck Converter ............................................................................... 5
4
TPS560430XF Design With 5-V Output
5
6
7
................................................................................. 8
Schematic of A Simplified SIMPLIS Model ............................................................................... 9
Bode Plot Simulation Result at VIN = 12 V, IO = 0.6 A .................................................................. 9
Bode Plot Test Result at VIN = 12 V, IO = 0.6 A ........................................................................ 10
List of Tables
.............................................................................................
1
Design Example Specification
2
Calculation, Simulation, and Bench Measurement Results Comparison ........................................... 10
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1
Introduction
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1
Introduction
The TPS560430 regulator is an easy-to-use synchronous step-down DC/DC converter operating from 4-V
to 36-V supply voltage. It is capable of delivering up to 600-mA DC load current in a very small solution
size. The family has different versions applicable for different applications, 1.1-MHz and 2.1-MHz
switching frequency, PFM and FPWM, adjustable and fixed output voltage. The device is suitable for a
wide range of applications from industrial to automotive for power conditioning from an unregulated
source. The TPS560430 employs peak-current mode control with internal loop compensation, which
reduces design time, and requires few external components.
A lot of PCM loop models are available for system design. The most popular model is provided in [2]. The
model predicted the sample and hold effects in the current loop, while using a three-terminal switch model
to calculate power stage small signal model. Using this method, a simplified loop model is provided in [3],
and an equivalent circuit is obtained to simulate the loop response. However, if all of the models require
simulation tools to draw the bode plot, then find a crossover frequency and phase margin based on the
bode plot. Besides, the transfer function of inner current loop is quite complex, making it hard to
understand how it impacts the whole loop response. In this document, a simple equation is provided to
calculate bandwidth. The phase margin is obtained by simplifying the inside current loop as a single pole.
The inner current loop stability criteria can be obtained based on the model. Each zero and pole in the
model has a clear physical meaning, making it easy to analyze the impact of each component value on
the loop response. The inductor and output capacitor design procedure of the internally compensated
PCM buck converter is given using the model. The model accuracy is verified by both simulation and
bench measurement results.
2
Peak Current Mode Loop Modeling
2.1
Overall Control Block Diagram and Transfer Function Derivation
Figure 1 shows the simplified schematic for the PCM buck converter.
iL
VO
L
IO
RESR
VIN
Ri
RFBT
RO
CO
Comparator
QN
R
Q
S
Clock
+
±
+
±
VCOMP
Gm +
RCOMP
CCOMP
Slope
Comp
VFB
RFBB
VREF
CO_EA
Figure 1. Simplified Schematic for PCM Buck Converter
vÖCOMP
Fm
He(s)
GEA(s)
-1
dÖ
Gdi(s)
iÖL
ZO(s)
vÖO
Ri
vÖFB
Gdiv(s)
Figure 2. Overall Control Implementation
2
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Figure 2 shows the overall control block model where:
• Gdi(s) is the duty cycle to iL transfer function.
• ZO(s) is the transfer function of output impedance.
• Gdiv(s) is the gain of the feedback resistor network.
• GEA(s) is the transfer function of the error amplifier with certain compensation.
• Fm is the gain of PCM PWM comparator.
• Ri is the current sensing resistor.
• He(s) is the transfer function model of inductor current sampling-hold effect.
Equation 1 shows the transfer function from the inductor current to the output voltage.
^
1
vO s
ZO s
RO
^
iL s
sR ESR C O
1 s R ESR
RO CO
(1)
Gdi(s) is the duty cycle to iL transfer function.
^
VIN 1 sC OR O
iL s
Gdi s
^
RO
d s
sL s 2 LC OR O
(2)
The internal loop compensation is designed so that the crossover frequency is much higher than the
corner frequency, 1/(2π√LCO). For crossover frequency and higher frequency, Equation 2 can be simplified
as Equation 3.
^
iL s
Gdi s
|
^
d s
VIN
sL
(3)
The sensed inductor current, external ramp, and the output of error amplifier VCOMP are compared, which
determines when to turn off the high side MOSFET, hence the duty cycle is determined. Fm is the
comparator gain. fSW is the switching frequency. Sn is the on-time slope of the sensed-current waveform
and Se is the external ramp slope.
Fm
f SW
Sn
Se
where
Sn
Se
Ri
VIN
VO
L
V Se u f SW
(4)
He(s) is the transfer function model of inductor current sampling-hold effect. [2]:
s
f SW
He s
|1
s
e
f SW
1
s
2f SW
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s2
2
Sf SW
(5)
Loop Response Considerations in Peak Current Mode Buck Converter
Design
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Peak Current Mode Loop Modeling
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Equation 6 shows the transfer function of the feedback.
^
v FB s
G div s
^
vO s
VREF
VO
(6)
Equation 7 shows the transfer function of the error amplifier with certain compensation.
^
G EA s
^
vFB s
2.2
Gm
1
sR COMP C COMP
C COMP s 1
sR COMP C O _EA
v COMP s
(7)
Inside Current Loop Model
Based on Equation 3 to Equation 5 and Figure 2, the transfer function from control to inductor current is
Gci(s):
^
iL s
G ci s
^
v COMP s
1
Ri
1
ªV f L
0.5VIN
Se SW
1 su «
VINR i f SW
«
¬
VO R i º
1
» s2 u
»
Sf SW
¼
2
(8)
For PCM buck converter, the crossover frequency is much smaller than half switching frequency, so
around crossover frequency Equation 8 can be simplified as Equation 9. The inside current loop is
simplified as a single pole, which is very helpful for the loop response analysis of PCM buck converter.
^
iL s
G ci s
^
v COMP s
1
Ri
1
ªV f L
0.5VIN
Se SW
1 su «
VINR i f SW
«
¬
VO R i º
»
»
¼
(9)
If the inside current loop Gci(s) is not stable, subharmonic oscillation occurs. A system is stable as long as
each of the poles of the closed loop transfer function lies in the left half plane. The minimum inductor
value is calculated to prevent subharmonic oscillation:
L!
2.3
R i VO
0.5VIN
V Se f SW
(10)
Overall Loop Model
fZ_EA and fP_EA are zeros and poles introduced by the error amplifier with certain compensation. fZ_OUT and
fP_OUT are zeros and poles introduced by the output capacitor and load. fP_ci is the pole introduced by the
inside current loop. Based on Equation 1, Equation 6, Equation 7, and Equation 9, the open loop transfer
function L(s) around crossover frequency is obtained:
4
Loop Response Considerations in Peak Current Mode Buck Converter
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L s
Z O s u G div s u G EA s u G ci s
K
§
¨1
¨
©
§
s u ¨1
¨
©
s
2Sf Z_EA
s
2Sf P_EA
· §
¸ u ¨1
¸ ¨
¹ ©
· §
¸ u ¨1
¸ ¨
¹ ©
·
¸
2Sf Z_OUT ¹¸
s · §
s
¸ u ¨1
¸
¨
2Sf P_ci ¹ ©
2Sf P_OUT
s
·
¸
¸
¹
where
R O VREFG m
K
R i V OC COMP
1
f Z_EA
2SR COMPC COMP
1
f P_EA
f P_ci
2SR COMPC O_EA
VIN R i f SW
2S ª V Se f SW L
¬
f Z_OUT
f P_OUT
2.4
0.5VIN
VO R i º
¼
1
2SR ESR C O
1
2S R ESR
RO CO
(11)
Inductor and Output Capacitor Design Limits
Figure 3 shows the Bode plot with proper inductor and output capacitor design. fc ≫ fP_OUT, fc ≫ fZ_EA, fc ≪
fP_EA, fc ≪ fP_ci, fc ≪ fZ_OUT
60
¦P_OUT
Gain (dB)
40
¦Z_EA
20
¦c
0
1k
10 k
100 k
¦P_ci
s 20
¦Z_OUT
s 40
¦P_EA
Frequency (Hz)
Figure 3. Bode Plot Model for PCM Buck Converter
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Peak Current Mode Loop Modeling
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The gain curve must go across 0 dB with a -20 dB/dec slew rate, so that the phase margin is enough. The
zero introduced by the compensation network fZ_EA cancels the pole of output impedance fP_OUT, and they
are placed far before crossover frequency: fP_OUT ≪ fc, fZ_EA ≪ fc. The parasitic capacitor of error amplifier
CO_EA is quite small, so fP_EA ≫ fc.
If L is too large, the pole introduced by the current loop fP_ci is smaller than the crossover frequency fc. The
gain curve goes across 0 dB with a -40 dB/dec slew rate, and the phase margin is not enough. Besides,
the loop response is influenced by VIN since fP_ci is influenced by VIN. To prevent that from happening, L
must be properly designed to ensure fP_ci ≫ fc. Equation 12 calculates the maximum inductor value.
R i VO
VIN R i
L
2Sf C V Se
0.5VIN
V Se f SW
(12)
If the Equivalent Series Resistance (ESR) of output capacitor is too large, the zero introduced by the
output capacitor fZ_OUT is smaller than the crossover frequency fc. The gain curve has a 0 dB/dec slew rate
after fZ_OUT, which makes the crossover frequency too large. Some high frequency poles introduced by the
parasitic parameters in the IC influence the phase margin, and the phase margin is not enough. To
prevent that, ESR of the output capacitor must be properly designed to ensure fZ_OUT ≫ fc. Equation 13
calculates the maximum ESR.
1
2Sf CC O
R ESR
2.5
(13)
The Equation to Calculate Bandwidth and Phase Margin
From Equation 11 and considering fc ≫ fP_OUT, fc ≫ fZ_EA, fc ≪ fP_EA, fc ≪ fP_ci, and fc ≪ fZ_OUT, the magnitude
of open loop transfer function at crossover frequency fc is shown in Equation 14.
1 j
L j2Sf C
K
2Sf c u 1 j
fC
f Z_EA
fC
f P_EA
u1 j
u1 j
fC
fC
f Z_OUT
fC
f P_ci
u1 j
fC
f Z_EA
|Ku
f P_OUT
2Sf c u
fC
1
f P_OUT
(14)
Considering RESR ≪ RO, the crossover frequency fc is obtained: Equation 15
fc
VREF G m R COMP
2SV O R i C O
(15)
Phase margin is the phase of open loop transfer function at fc minus -180º: Equation 16
PhaseMargin
90q arctan 2Sf CR OC O u
180q
S
arctan 2 Sf CR COMPC COMP u
180q
S
§ 2Sf ª V f L
0.5VIN
C ¬ Se SW
180q
arctan 2Sf CR COMPC O_EA u
arctan ¨
¨¨
S
VINR i f SW
©
180q
arctan 2Sf CR ESR C O u
S
3
V O R i º · 180q
¼ ¸u
¸¸
S
¹
(16)
Inductor and Output Capacitor Design
In this section, the inductor and output capacitor is designed in a practical application using
TPS560430XF. The loop response is considered during the process. Table 1 lists the design
specifications.
6
Loop Response Considerations in Peak Current Mode Buck Converter
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Table 1. Design Example Specification
3.1
VIN (V)
VO (V)
IO (A)
IO_min (A)
fSW (kHz)
OUTPUT
RIPPLE (mV)
VREF (V)
7 V to 36 V,
typical 12 V
5
0.6
0.1
1100
< 30
1
Inductor Design
Equation 17 calculates the value of the output conductor. KIND is a coefficient that represents the amount
of inductor ripple current relative to the maximum output current of the device. A reasonable value of KIND
is 0.2 – 0.4. Since the ripple current increases with the input voltage, the maximum input voltage is used
to calculate the minimum inductance LMIN, while KIND = 0.4 is selected. The minimum inductor value is
calculated to be 16.3 μH. Choose the nearest standard inductor: L= 18 μH.
VIN_ max
L min
VO
I O u K IND
u
VO
VIN_ max u f SW
(17)
From Equation 12, the maximum inductor value is calculated to get enough phase margin. Three times
margin is suggested and the limit is Equation 18 with the TPS560430 internal parameter. If you assume
the target crossing over frequency fc is about 20 kHz, then the result is L < 40 μH at the minimum VIN. The
selected 18-μH inductor meets the requirement.
L
ª
VIN
1«
3 « 2Sf c u 0.476
¬
0.5VIN º
»
f SW u 0.476 »
¼
VO
(18)
The TPS560430 is protected from over-current conditions by the cycle-by-cycle current limit. To prevent
inductor saturation in case of short circuit conditions, the inductor saturation current must be greater than
the device maximum peak current limit, which is 1.4 A for the TPS560430.
3.2
Output Capacitor Design
The output capacitor is designed based on output ripple and loop response. The output voltage ripple is
composed of two parts. One is caused by the inductor current ripple going through the ESR of the output
capacitor, see Equation 19. The other is caused by the inductor current ripple charging and discharging
the output capacitor, see Equation 20. The target output ripple is 30 mV, so ΔVO_ESR < 30 mV and ΔVO_C <
30 mV, then RESR < 125 mΩ and CO > 0.91 μF.
'V O_ESR
'V O_C
I O u K IND u R ESR
(19)
I O u K IND
8 u f SW u C O
(20)
From Equation 13, the maximum ESR value is calculated to get a reasonable crossover frequency and
enough phase margin. If you assume the target crossing over frequency fc is about 20 kHz, then the result
is RESR ≪ 612 mΩ. Three times margin is suggested and the result is RESR < 204 mΩ.
Output capacitor value determines loop response in internally compensated PCM buck converters, as
Equation 15 and Equation 16. With TPS560430 internal parameter, the calculation equation is as
Equation 21 and Equation 22. The target fc is about 20 kHz, so CO is about 15 μF. Consider of derating,
one 22-μF, 16-V ceramic capacitor with 4-mΩ ESR is used. The capacitance after derating is 13 μF: CO =
13 μF, RESR = 4 mΩ. The crossover frequency is fc = 23.4 kHz and the phase margin is calculated as 64.2º
at VIN = 12 V, IO = 0.6 A. The equation also indicates that the worst phase margin happens at minimum VIN
and minimum IO, while the calculation result is 59.2º at VIN = 7 V, IO = 0.1 A. They meet design specs.
fc
9.54
2SVOC O
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Design
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Inductor and Output Capacitor Design
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PhaseMargin
90q arctan 2Sf CR OC O u
180q
S
arctan 2 Sf C u 26.5 P u
§ 2Sf f L u 0.476 0.5V
C
SW
IN
arctan ¨
¨
VINf SW
©
VO · 180q
¸u
¸
S
¹
180q
180q
arctan 2 Sf C u 1.06 P u
S
S
arctan 2Sf CR ESRC O u
180q
S
(22)
3.3
Simulation and Bench Verification
Figure 4 shows the schematic for bench verification. SIMPLIS is used to simulate the loop response as
shown in Figure 5. Figure 6 and Figure 7 are the loop responses from the SIMPLIS simulation and bench
test under VIN = 12 V, VO = 5 V, IO = 0.6 A, and fSW = 1.1 MHz. Table 2 compares the calculation results,
simulation results, and bench measurement at different VIN. It can be seen that the proposed model in this
application report is accurate.
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Figure 4. TPS560430XF Design With 5-V Output
8
Loop Response Considerations in Peak Current Mode Buck Converter
Design
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D1n4148
H1
{Ri}
18u IC=0
iL
VO
L1
X2
V1
12
Io
V10
AC 50m 0
R2
4m
U1
iL-slope
E1
V6
S
Q
R
QN
R10
8.333
IN
U2
1
OUT
SW
=OUT/IN
D3
S1
C1 +
13u IC=0
S2
D4
D1n4148
V2
R5
46.4k
U4
VCOMPVT
1
VCOMP
COMP
D1
FB
D2
E2
V7
2
V8
-2
+
R3
{RCOMP}
GAIN={Gm}
C2
{CO_EA} IC=0
+
V4
1
R6
11.6k
C4
{CCOMP} IC=0
Figure 5. Schematic of A Simplified SIMPLIS Model
Figure 6. Bode Plot Simulation Result at VIN = 12 V, IO = 0.6 A
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Summary
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Figure 7. Bode Plot Test Result at VIN = 12 V, IO = 0.6 A
Table 2. Calculation, Simulation, and Bench Measurement Results Comparison
CALCULATION RESULTS
4
SIMULATION RESULTS
BENCH MEASUREMENT
fc (kHz)
PHASE
MARGIN (º)
fc (kHz)
PHASE
MARGIN (º)
fc (kHz)
PHASE
MARGIN (º)
0.1
23.4
59.2
22.8
61.3
23.6
58.4
VIN (V)
IO (A)
7
7
0.6
23.4
62.2
22.7
64.4
24.7
61.7
12
0.1
23.4
61.2
22.9
62.8
24.6
60.3
12
0.6
23.4
64.2
22.8
65.9
25.1
64
36
0.1
23.4
63
22.9
64.3
23.7
61.1
36
0.6
23.4
66
22.9
67.4
23.9
66.3
Summary
For an internally compensated, peak current mode buck converter, consider the loop response when
designing inductor and output capacitor. This application report simplifies the inside current loop as a
single pole, provides the constraint to ensure loop stability, and gives out an equation to calculate
bandwidth and phase margin. The inductor and output capacitor is designed step-by-step considering loop
response. The theory is verified by simulation and bench measurement results.
5
References
1. Texas Instruments, TPS560430 4-V to 36-V, 600-mA Synchronous Step-Down Converter Data Sheet
2. R.B. Ridley, A New Small-Signal Model for Current-Mode Control, PhD Dissertation, Virginia
Polytechnic Institute and State University, November, 1990.
3. Texas Instruments, TPS65270 Loop Compensation Design Consideration Application Report
4. Texas Instruments, How to Evaluate the Maximum Inductor in an Internal Compensation PCM Buck
Converter Application Report
10
Loop Response Considerations in Peak Current Mode Buck Converter
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Revision History
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Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Original (July 2018) to A Revision ........................................................................................................... Page
•
Edited application report for clarity. ..................................................................................................... 1
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