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Texas Instruments Create an Inverting Power Supply Using Peak Current Mode Buck Converter Application notes
Application Report
SLVAE10 – July 2018
Create an Inverting Power Supply Using Peak Current
Mode Buck Converter
Neal Zhang
ABSTRACT
The negative output voltage is required by applications such as operational amplifiers and a good solution
is inverting buck-boost topology. This application report introduces the detailed design procedure to
configure a Peak Current Mode (PCM) buck converter to the inverting buck-boost topology. The
TPS560430 is a PCM buck converter with internal loop compensation, and it makes the design quite
simple.
TPS560430 is introduced in Section 1. Section 2 provides the input voltage and output current ranges
when a buck converter IC is configured as buck-boost topology. Section 3 provides the method to choose
external components. A simple equation to calculate loop response is provided in this section, and it is
used to design output capacitor. In Section 4, bench performance characteristics are provided.
Contents
1
Introduction ................................................................................................................... 2
2
Specifications ................................................................................................................ 2
3
External Component Selection ............................................................................................ 3
4
Evaluation Results .......................................................................................................... 7
5
References .................................................................................................................. 11
Appendix A
A Simple Equation to Calculate Loop Response of Peak Current Mode Buck Boost Converter ....... 12
List of Figures
1
Configure a Buck Converter IC as Inverting Buck-Boost Topology ................................................... 2
2
Maximum Output Current of the Inverting Power Supply
3
Design Example Circuit
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
.............................................................. 3
.................................................................................................... 4
Efficiency vs Load Current ................................................................................................. 7
Load Regulation ............................................................................................................. 7
Line Regulation .............................................................................................................. 7
Output Voltage Ripple at No Load......................................................................................... 7
Output Voltage Ripple at 0.1A ............................................................................................. 7
Input Voltage Ripple at No Load ........................................................................................... 7
Input Voltage Ripple at 0.1A ............................................................................................... 8
Start Up by VIN ............................................................................................................... 8
Load Transient ............................................................................................................... 8
Short Protection .............................................................................................................. 8
Schematic of Simplified SIMPLIS Model ................................................................................. 9
Bode Plot Simulation Result at VIN = 12 V, IO = 0.1 A ................................................................ 10
Bode Plot Test Result at VIN = 12 V, IO = 0.1 A ........................................................................ 10
Simplified Schematic for PCM Buck-Boost Converter................................................................. 12
Overall Control Implementation .......................................................................................... 13
Bode Plot Model for PCM Buck-Boost Converter ...................................................................... 16
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1
Introduction
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List of Tables
1
2
3
............................................................................................. 3
Loop Response Calculation Results ...................................................................................... 6
Calculation, Simulation and Bench Measurement Results Comparison ............................................ 11
Design Example Specification
Trademarks
All trademarks are the property of their respective owners.
1
Introduction
The TPS560430 regulator is an easy to use synchronous step-down DC-DC converter operating from 4-V
to 36-V supply voltage. It is capable of delivering up to 600-mA DC load current in a very small solution
size. The family has different versions applicable for different applications, 1.1-MHz and 2.1-MHz
switching frequency, PFM and FPWM, adjustable and fixed output voltage. The TPS560430 employs
peak-current mode control with internal loop compensation, which reduces design time, and requires few
external components.
A buck converter IC can be configured as inverting buck-boost topology, as shown in Figure 1. The GND
pin of the original buck IC (GND_IC in the figure) is connected to VO of the new system.
VIN
VIN_IC
Buck Converter IC
GND_IC
CIN
Vo
CO
SW_IC
PGND
Figure 1. Configure a Buck Converter IC as Inverting Buck-Boost Topology
2
Specifications
When a buck converter IC is configured as inverting buck-boost topology, the maximum input voltage and
output current decreases. The suitable buck IC needs to be chosen to satisfy the application requirement.
The specification limit is calculated in this section. It should be pointed out that, VO is negative in all the
equations in this document.
2.1
Input Voltage Range
The difference in the maximum input voltage, output voltage should not exceed the maximum operating
voltage of the device, see Equation 1. For TPS560430 the maximum operating voltage is 36 V. For
example, when output is -12 V, the maximum input voltage of the inverting power supply is 24 V.
VIN_ max d VIC_max
VO
(1)
The minimum operating input voltage of the inverting power supply is the minimum device operating
voltage, see Equation 2. For TPS560430 the minimum input voltage is 4V, so the inverting power supply
input voltage must higher than 4 V.
VIN_ min t VIC_ min
2
(2)
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Specifications
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2.2
Output Current Range
To estimate whether the selected switching regulator is capable of delivering the output current, use
Equation 3. IO_IC_max is the maximum output current of the device (IO_IC_max = 0.6A for TPS560430). For
TPS560430 the inverting power supply output current limit is calculated as shown in Figure 2. For
example, if the minimum input voltage in the design spec is 4 V, the maximum output current is 0.15 A
when VO = -12 V.
I O_ max d I O_IC_ max u
VIN_ min
VIN_ min
VO
(3)
Figure 2. Maximum Output Current of the Inverting Power Supply
3
External Component Selection
In this section the inductor and output capacitor is designed in a practical application. The loop response
is considered during the process. It should be pointed out that VO is negative in all the equations.
Detailed design procedure is described based on a design example. For this design example, 1.1-MHz
operating frequency, forced PWM (FPWM) version TPS560430XF is used with design specs as shown in
Table 1.
Table 1. Design Example Specification
VO (V)
-12
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VIN (V)
VIN_min
VIN_norm
VIN_max
4
12
24
IO (A)
fSW (kHz)
Output Voltage
Ripple ΔVO
0.1
1100
0.5%*|VO| = 60
mV
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External Component Selection
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Figure 3 shows the reference design circuit.
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Figure 3. Design Example Circuit
3.1
Duty Cycle Calculation
Duty cycle is calculated using Equation 4. The maximum duty cycle is needed at the minimum input
voltage. In this design example, Dmax = 0.75 at VIN_min = 4 V, Dmin = 0.33 at VIN_max = 24 V, Dnorm = 0.5 at
VIN_norm = 12 V.
VO
D
VIN
3.2
VO
(4)
Output Voltage Set-Point
The output voltage of the TPS560430 device is externally adjustable using a resistor divider network. In
this example, the divider network is comprised of R1 and R2. Equation 5 is used to determine the output
voltage of the converter:
R1
VO
VREF
VREF
u R2
(5)
Choose the value of R2 to be 4.22 kΩ. With the desired output voltage set to -12 V and the VREF = 1 V, the
R1 value can then be calculated as 46.4 kΩ.
3.3
Inductor
To calculate the value of the output inductor, use Equation 6. KIND is a coefficient that represents the
amount of inductor ripple current relative to the maximum output current of the device: IO_IC_max (IO_IC_max =
0.6A for TPS560430). A reasonable value of KIND should be 0.2 – 0.4. Since the ripple current increases
with the input voltage, the maximum input voltage is used to calculate the minimum inductance LMIN, while
KIND = 0.4 is selected. The minimum inductor value is calculated to be 30.3 μH. Choose the nearest
standard inductor: L= 33 μH.
L min
VIN_ max u Dmin
f SW u I O_IC_ max u K IND
(6)
The TPS560430 is protected from over-current conditions by cycle-by-cycle current limit. To prevent
inductor saturation in case of short circuit conditions, the inductor saturation current should be greater
than the device maximum peak current limit, which is 1.4 A for TPS560430.
4
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External Component Selection
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Select the inductor to satisfy the RMS current rating using Equation 7. The minimum VIN is used to
calculate the maximum RMS current, and the result is 0.4 A in this design example.
§ I
O
¨
¨ 1 D max
©
I L_RMS
3.4
·
¸
¸
¹
2
1 § VIN_ min u D max
u¨
12 ¨©
f SW u L
·
¸
¸
¹
2
(7)
Output Capacitor
The output capacitor is designed considering output ripple and loop response. The output capacitor must
supply the current when the high-side switch is on. Use the minimum input voltage to calculate the output
capacitance needed, as shown in Equation 8. The maximum ESR of the output capacitor is calculated as
shown in Equation 9 to satisfy the output ripple requirement. The target output ripple is 60 mV, so RESR <
136 mΩ and CO > 1.1 μF. The capacitor needs to satisfy the RMS current rating, which is 0.17 A using
Equation 10.
CO!
I O u Dmax
f SW u 'V O
(8)
'V O
R ESR
IO
VIN _min u Dmax
1 D max
2 u f SW u L
I CO _RMS
IO u
D max
1 D max
(9)
(10)
The selection of output capacitor directly determines the loop response in internally compensated
converter. This article proposed a simple equation to calculate bandwidth and phase margin, which is
derived in Appendix A. The conclusion is as Equation 30 to Equation 34. RO = -VO / IO = 120 Ω in this
design example. With internal components value of TPS560430XF and considering 3 times margin, the
output capacitor limit is as shown in Equation 11: CO > 2 μF.
CO ! 3u
Dmax u 9.54
1 D max V O R O
uL
(11)
To summary, CO > 2 μF and RESR < 136 mΩ is needed considering output voltage ripple and loop
response. Consider of derating, one 4.7-μF, 25-V ceramic capacitor (part number 885012108020) is used.
The capacitance after derating is 2.3 μF: CO = 2.3 μF, RESR = 6 mΩ.
With internal components value of TPS560430XF, Equation 12 and Equation 13 are used to calculate
bandwidth and phase margin. The loop response is calculated as Table 2 and it meets the design
requirement.
fc
1 D u 9.54
2SV O CO
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External Component Selection
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PhaseMargin
§ 2SDf L ·
C
¸ u 180q
arctan ¨
2
¨
¸
S
© 1 D RO ¹
D 0.5 V O ¼º · 180q
180q
¸u
arctan 2Sf C u 26.5P u
¸
S
S
¹
180q
arctan 2Sf CR ESR C O u
S
§ 2Sf CR O C O · 180q
arctan ¨
¸u
¨ 1 D
¸
S
©
¹
90q
§ 2Sf ªDf L u 0.476
C ¬
SW
arctan ¨
¨
V O f SW
©
180q
arctan 2Sf C u 1.06P u
S
(13)
Table 2. Loop Response Calculation Results
3.5
VIN (V)
IO (A)
Crossover Frequency (kHz)
Phase Margin (º)
4
0.1
13.8
45.8
12
0.1
27.5
57.4
24
0.1
36.7
57.9
Input Capacitor
The input capacitors between VIN and ground are used to limit the voltage ripple of the input supply.
Equation 14 to Equation 16 are used to estimate the capacitance, maximum ESR, and current rating for
the input capacitor. The target input ripple ∆VIN is 2%*VIN_min=80 mV, so ESRCin < 181 mΩ and CIN > 0.85
μF. The RMS current rating is 0.17 A. Consider of derating, one 2.2-μF, 50-V ceramic capacitor is chosen.
At VIN_max = 24 V, the capacitance after derating is 1.4 μF, while ESRCin = 7 mΩ.
CIN !
I O u D max
f SW u 'VIN
ESR Cin
I CIN _RMS
3.6
(14)
'VIN
IO
VIN_ min u D max
1 D max
2 u f SW u L
IO u
(15)
D max
1 D max
(16)
Bypass Capacitor
The TPS560430 needs a tightly coupled, ceramic bypass capacitor, connected to the VIN and GND pin of
the device. Because the device GND is the power supply output voltage, the voltage rating of the
capacitor must be greater than the differences in the maximum input and output voltage of the power
supply, which is 36 V in this design example. One 0.1-μF, 50-V ceramic capacitor is chosen for highfrequency filtering and place it as close as possible to the device pins.
3.7
Bootstrap Capacitor
Every TPS560430 design requires a bootstrap capacitor. The recommended bootstrap capacitor is 0.1 μF
and rated at 16 V or higher. The bootstrap capacitor is located between the SW pin and the CB pin. The
bootstrap capacitor must be a high-quality ceramic type with X7R or X5R grade dielectric for temperature
stability.
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Evaluation Results
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4
Evaluation Results
4.1
Typical Performance
Figure 4 to Figure 13 show the experimental test results of the Figure 3 design. Unless otherwise
specified, the following conditions apply: VIN = 12 V, VO = -12 V, IO = 0.1 A, TA = 25 °C.
100
11.997
90
11.9955
11.994
80
Output Voltage (V)
70
Efficiency (%)
VIN = 4 V
VIN = 12 V
VIN = 24 V
60
50
40
30
20
11.991
11.9895
11.988
11.9865
11.985
11.9835
VIN = 4 V
VIN = 12 V
VIN = 24 V
10
11.9925
11.982
0
11.9805
0
0.02
0.04
0.06
0.08
0.1
Output Current (A)
0.12
0.14
0
0.02
Figu
Figure 4. Efficiency vs Load Current
0.04
0.06
0.08
0.1
Output Current (A)
0.12
0.14
Figu
Figure 5. Load Regulation
11.997
11.996
Output Voltage (V)
11.995
11.994
11.993
11.992
11.991
11.99
11.989
11.988
IOUT = 0 A
IOUT = 0.1 A
11.987
11.986
2.5
5
7.5
10
12.5
15
17.5
Input Voltage (V)
20
22.5
25
Figu
Figure 6. Line Regulation
Figure 7. Output Voltage Ripple at No Load
Figure 8. Output Voltage Ripple at 0.1A
Figure 9. Input Voltage Ripple at No Load
!~
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Evaluation Results
8
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Figure 10. Input Voltage Ripple at 0.1A
Figure 11. Start Up by VIN
Figure 12. Load Transient
Figure 13. Short Protection
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4.2
Loop Response Simulation and Bench Verification
SIMPLIS is used to simulate the loop response as Figure 14. Figure 15 and Figure 16 are the loop
response from SIMPLIS simulation and bench test under VIN = 12 V, VO = -12 V, IO = 0.1 A, fSW = 1.1 MHz.
The comparison of calculation results, simulation results and bench measurement at different VIN is given
in Table 3. It can be seen that the proposed model in this application report is accurate.
D1n4148
H1
{Ri}
D3
S1
33u IC=0
SW
VIN
V1
12
C8
1.7u
C7
100n
iL
L1
X2
Io
R2
6m
U1
U2
1
iL-slope
S
Q
R
QN
S2
D4
D1n4148
R10
120
+
C1
2.3u IC=0
V2
VO
E1
V6
VO
R5
46.4k
VO
V10
AC 50m 0
=OUT/IN
OUT
U3
IN
1
VCOMP
COMP
FB
D1
V7
1
D2
R4
{RCOMP}
E2
+
C5
{CO_EA} IC=0
V8
-1
+
GAIN={Gm}
R6
V4
1
4.22k
C3
{CCOMP} IC=0
VO
Figure 14. Schematic of Simplified SIMPLIS Model
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Evaluation Results
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Figure 15. Bode Plot Simulation Result at VIN = 12 V, IO = 0.1 A
Figure 16. Bode Plot Test Result at VIN = 12 V, IO = 0.1 A
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References
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Table 3. Calculation, Simulation and Bench Measurement Results Comparison
Calculation Results
5
VIN (V)
IO (A)
Simulation Results
fc (kHz)
Phase Margin
(º)
fc (kHz)
Bench Measurement
Phase Margin
(º)
fc (kHz)
Phase Margin
(º)
4
0.1
13.8
45.8
14.3
46
13.3
41.2
12
0.1
27.5
57.4
25.8
59.3
25.5
54.1
24
0.1
36.7
57.9
33.5
60.7
32.5
57.9
References
1.
2.
3.
4.
Texas Instruments, TPS560430 4-V to 36-V, 600-mA Synchronous Step-Down Converter Data Sheet
Texas Instruments, Create an Inverting Power Supply Using a Synchronous Step-Down Regulator
Texas Instruments, Create an Inverting Power Supply From a Step-Down Regulator
Texas Instruments, Achieving High-Efficiency with a Multi-Output CCM Flyback Supply Using SelfDriven Synchronous Rectifiers
5. R.B. Ridley, A New Small-Signal Model for Current-Mode Control, PhD Dissertation, Virginia
Polytechnic Institute and State University, November, 1990.
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Appendix A
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A Simple Equation to Calculate Loop Response of Peak
Current Mode Buck Boost Converter
A.1
Introduction
PCM control has been widely used in buck-boost converters for many years and lots of loop models are
available for system design. In [2] to [4], the first order model is used due to its simplicity, but the high
frequency accuracy is bad, resulting in big phase margin error. Besides, it can’t predict current loop
instability. The most popular model is provided by R. Ridley [5]. The model predicted the sample and hold
effects in the current loop. However, the model requires simulation tools to draw the bode plot, then find
crossover frequency and phase margin based on the bode plot. Besides, the transfer function of inner
current loop is quite complex, making it hard to understand how each component value impact the whole
loop response.
In this document, a simple equation to calculate bandwidth and phase margin is obtained by simplifying
the inside current loop as a single pole. Each zero and pole in the model has a clear physical meaning,
making it easy to analyze the impact of each component value on the loop response. The inductor and
output capacitor design procedure of internally compensated PCM buck converter is given using the
model. The model accuracy is verified by both simulation and bench measurement results.
A.2
Overall Control Block Diagram and Transfer Function Derivation
Figure 17 shows the simplified schematic for the PCM buck-boost converter.
VO
VREF
RESR
VIN
RO
R2
IO
R1
+
L
±
CO
iL
Gm
ICOMP
Ri
Comparator
QN
R
Q
S
Clock
+
±
+
VCOMP
RCOMP
Slope
Comp
CO_EA
CCOMP
VO
Figure 17. Simplified Schematic for PCM Buck-Boost Converter
12
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Overall Control Block Diagram and Transfer Function Derivation
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vÖCOMP
dÖ
Fm
He(s)
Gdi(s)
iÖL
Giv(s)
vÖO
Ri
Gdiv_EA(s)
Figure 18. Overall Control Implementation
Figure 18 is the overall control block model.
Where:
• Gdi(s) is the duty cycle to inductor current transfer function
• Giv(s) is the inductor current to output voltage transfer function
• Fm is the gain of PCM PWM comparator
• Ri is the current sensing resistor
• He(s) is the transfer function model of inductor current sampling-hold effect
• Gdiv_EA(s) is the output voltage to compensation voltage transfer function. It includes the feedback
resistor network and the error amplifier with certain compensation
Giv(s) and Gdi(s) is relating to the power stage small signal model. They are derived using three-terminal
switch model [4]. The transfer function from inductor current to output voltage is shown in Equation 17.
^
vO s
G iv s
1 D RO
^
§
¨1
¨
©
· §
¸ u ¨1
w Z1_iv ¸¹ ¨©
§
s
¨1
¨
wP1_iv
©
s
1 D
iL s
s
w Z2 _iv
·
¸
¸
¹
·
¸
¸
¹
(17)
Where:
2
1 D RO
w Z1_iv
DL
w Z2 _iv
1
R ESR C O
w P1_iv
1 D
R OC O
Gdi(s) is the duty cycle to inductor current transfer function, see Equation 18.
^
VIN 1
iL s
G di
^
d s
D
2
1 D ª 1 D RO
«¬
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sC OR O
sL s 2 LC OR O º
»¼
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13
Inside Current Loop Model
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The internal loop compensation is designed so that the crossover frequency is much higher than
(1-D)/(2π√LCO). For crossover frequency and higher frequency, Equation 18 can be simplified as
Equation 19.
^
VIN
iL s
G di s
|
^
d s
1 D sL
(19)
The sensed inductor current, external ramp and the output of error amplifier VCOMP are compared, which
determines when to turn off the high side MOSFET, hence the duty cycle is determined. Fm is the
comparator gain, see Equation 20. fSW is the switching frequency. Sn is the on-time slope of the sensedcurrent waveform and Se is the external ramp slope.
Fm
f SW
Sn
Se
(20)
Where:
Sn
Se
Ri
VIN
L
V Se u f SW
He(s) is the transfer function model of inductor current sampling-hold effect [5], see Equation 21.
s
f SW
He s
s
e
fSW
s
|1
2f sw
1
s2
2
Sf sw
(21)
Gdiv_EA(s) is the output voltage to compensation voltage transfer function, see Equation 22. It includes the
feedback resistor network and the error amplifier with certain compensation.
^
v COMP s
G div_EA s
VREF G m
^
V O C COMP s 1
vO s
A.3
1
sR COMPC COMP
sR COMPC CO_EA
(22)
Inside Current Loop Model
Based on Equation 19 to Equation 21 and Figure 18, the transfer function from compensation voltage to
inductor current is Gci(s), see Equation 23.
^
iL s
G ci s
^
v COMP s
14
1
Ri
1
ª DV Se f SW L D 0.5 R i V O º
1
2
1 su «
» s u
R i VO f SW
Sf SW
¬«
¼»
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Overall Loop Model
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For PCM buck-boost converter, the crossover frequency is much smaller than half switching frequency, so
around crossover frequency Equation 23 can be simplified as Equation 24. The inside current loop is
simplified as a single pole, which is very helpful for the loop response analysis of PCM buck-boost
converter.
^
iL s
G ci s
1
Ri
^
v COMP s
A.4
1
ª DV Se f SW L D 0.5 R i V O º
1 su «
»
R
V
f
i O SW
¬«
¼»
(24)
Overall Loop Model
Based on Equation 17, Equation 22 and Equation 24, the open loop transfer function L(s) around
crossover frequency is obtained, see Equation 25. fZ_EA ,fP_EA are zeros and poles introduced by the error
amplifier with certain compensation. fZ1_iv, fZ2_iv, fP1_iv are zeros and poles introduced by the power stage
inductor current to output voltage transfer function. fP_ci is the simplified pole introduced by the inside
current loop.
G iv s u G div_EA s u G ci s
L s
§
· §
s · §
s
s ·
¨1
¸ u ¨1
¸ u ¨1
¸
¨
2Sf Z1_iv ¹¸ ©¨
2Sf Z2 _iv ¹¸ ©¨
2Sf Z_EA ¹¸
©
K
§
s · §
s · §
s ·
s u ¨1
¸ u ¨1
¸ u ¨1
¸
¨
2Sf P1_iv ¹¸ ¨©
2Sf P_EA ¹¸ ¨©
2Sf P_ci ¹¸
©
(25)
Where:
1
D R O V REF G m
1
D R i V O C COMP
K
2
f Z1_iv
f Z2 _iv
f P1_iv
f Z_EA
f P_EA
f P_ci
1 D RO
2SDL
1
2SR ESR C O
1 D
2SR O C O
1
2SR COMPC COMP
1
2SR COMPC O_EA
R i V O f SW
2S ª¬DV Se f SW L
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D 0.5 R i V O º¼
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15
Inductor and Output Capacitor Design Limits
A.5
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Inductor and Output Capacitor Design Limits
With proper inductor and output capacitor design, the Bode plot is as shown in Figure 19. fP1_iv≪ fc, fZ_EA ≪
fc, fP_ci ≫ fc, |fZ1_iv| ≫ fc, fP_EA ≫ fc, fZ2_iv ≫ fc.
¦P1_iv
Gain (dB)
40
20
¦Z_EA
¦c
0
1k
10 k
100 k
¦P_ci
s 20
|¦Z1_iv|
s 40
¦P_EA
Frequency (Hz)
¦Z2_iv
Figure 19. Bode Plot Model for PCM Buck-Boost Converter
The gain curve should go across 0dB with -20dB/dec slew rate, so that the phase margin is enough. The
zero introduced by the compensation network fZ_EA cancels the pole of output impedance fP1_iv, and they
are placed before crossover frequency: fP1_iv ≪ fc, fZ_EA ≪ fc. The parasitic capacitor of error amplifier CO_EA
is quite small, so fP_EA≫ fc.
fZ1_iv is calculated to be a negative value, which means it is a right half plan zero. The right half plane zero
introduces an increasing gain and a decreasing phase, which may cause lower phase margin and
instability. It is recommended to keep cross over frequency much lower than the right half plane zero, so
that the right half plane zero doesn’t affect the overall loop significantly: |fZ1_iv| ≫ fc. The maximum inductor
value is calculated, see Equation 26.
2
L
1 D RO
2SDf c
(26)
If L is too large, the pole introduced by the current loop fP_ci will be smaller than the crossover frequency fc.
The gain curve will go across 0dB with -40dB/dec slew rate, and the phase margin will not be enough. To
prevent that happens, L should be properly designed to ensure fP_ci≫ fc. The maximum inductor value is
calculated, see Equation 27.
L
V OR i
2SDf c V Se
D 0.5 V O R i
DV Se f SW
(27)
If the Equivalent Series Resistance (ESR) of output capacitor is too large, the zero introduced by output
capacitor fZ2_iv will be smaller than the crossover frequency fc. The gain curve will have 0dB/dec slew rate
after fZ2_iv, which will make the crossover frequency too large. Some high frequency poles introduced by
the parasitic parameters in the IC will influence the phase margin, and the phase margin will not be
enough. To prevent that happens, ESR of output capacitor should be properly designed to ensure fZ2_iv ≫
fc. The maximum ESR is calculated, see Equation 28.
R ESR
16
1
2Sf c C O
(28)
Create an Inverting Power Supply Using Peak Current Mode Buck Converter
Copyright © 2018, Texas Instruments Incorporated
SLVAE10 – July 2018
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The Equation to Calculate Bandwidth and Phase Margin
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A.6
The Equation to Calculate Bandwidth and Phase Margin
From Equation 25 and considering fP1_iv ≪ fc, fZ_EA ≪ fc, fP_ci ≫ fc, |fZ1_iv| ≫ fc, fP_EA ≫ fc, fZ2_iv ≫ fc, the
magnitude of open loop transfer function at crossover frequency fc is shown in Equation 29.
1 j
L j2Sf c
K
fc
f Z1_iv
2Sf c u 1 j
u1
fc
f P1_iv
j
fc
f Z2 _iv
u1
j
u1
fc
f P_EA
j
fc
fc
f Z_EA
u1
j
fc
|Ku
f P_ci
f Z_EA
2Sf c u
fc
1
f P1_iv
(29)
Considering usually RESR ≪ RO, the crossover frequency fc is obtained, see Equation 30.
1 D VREF G m R COMP
fc
2SV OR i C O
(30)
Phase margin is the phase of open loop transfer function at fc minus -180º, see Equation 31.
PhaseMargin
§ 2Sf cR O C O · 180q
180q
arctan ¨
arctan 2Sf CR COMP C COMP u
¸u
¨ 1 D ¸
S
S
©
¹
§ 2SDf L ·
§ 2Sf ªDV f L D 0.5 R V º · 180q
C ¬
Se SW
i
O¼
C
¨
¸ u 180q arctan ¨
¸u
arctan
2
¨ 1 D R ¸
¨
¸
R i V O f SW
S
S
O ¹
©
¹
©
90q
arctan 2Sf CR COMP C O _EA u
180q
180q
arctan 2SfC R ESR C O u
S
S
(31)
Substitute Equation 30 into Equation 26 to Equation 28, inductor and output capacitor design limits is
obtained, see Equation 32 to Equation 34. It is suggested to have 3 times margin when choosing inductor
and output capacitor values.
C O !!
DVREF G m R COMP
1 D VO R i R O
ª
C O !! «L
«¬
R ESR
uL
(32)
D 0.5 V OR i º D 1 D V REFG mR COMP V Se
»u
DV Se f SW »¼
VO 2 R i2
VOR i
1 D VREFG mR COMP
SLVAE10 – July 2018
Submit Documentation Feedback
(33)
(34)
Create an Inverting Power Supply Using Peak Current Mode Buck Converter
Copyright © 2018, Texas Instruments Incorporated
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