Texas Instruments | UCC27531 35-V Gate Driver for SiC MOSFET Applications (Rev. A) | Application notes | Texas Instruments UCC27531 35-V Gate Driver for SiC MOSFET Applications (Rev. A) Application notes

Texas Instruments UCC27531 35-V Gate Driver for SiC MOSFET Applications (Rev. A) Application notes
(1)
Application Report
SLUA770A – March 2016 – Revised May 2018
UCC27531 35-V Gate Driver for SiC MOSFET Applications
Richard Herring........................................................................................... High Power Driver Solutions
ABSTRACT
SiC MOSFETs are gaining popularity in many high-power applications due to their significant switching
performance advantages. SiC MOSFETs are also available with attractive voltage ratings and current
capabilities. However, the characteristics of SiC MOSFETs require consideration of the gate-driver circuit
to optimize the switching performance of the SiC device. Although SiC MOSFETs are not difficult to drive
properly, many typical MOSFET drivers may result in compromised switching speed performance.
The UCC27531 gate driver includes features and has operating parameters that allow for driving SiC
power MOSFETs within the recommended optimum drive configuration. This application note reviews the
characteristics of SiC MOSFETs and how to drive them to achieve the performance improvement that SiC
can bring at the system level. The features of UCC27531 to achieve optimal performance of SiC are
explained and results from a demonstration circuit are provided.
1
Introduction
In the past, the majority of applications such as uninterruptible power supplies (UPS), photovoltaic (PV)
inverters, and motor drive have utilized IGBTs for the power devices due to the combination of highvoltage ratings exceeding 1 kV and high current capability. Usable switching frequency of IGBTs has
typically been limited to 20–30 kHz, due to the high turnoff losses caused by the long turnoff current tail.
Design comparisons have shown that SiC MOSFET designs can operate at considerably higher switching
frequency and achieve the same or better efficiency. Although the device cost of the SiC MOSFETs are
higher than the equivalent IGBTs, the significant savings in transformer, capacitor, and enclosure size
results in a lower system cost.
The availability of Silicon MOSFETs with voltage ratings up to 900 V and low RDS(on) below
150 mΩ is improving. Beyond 900 V, low RDS(on) MOSFETs are not available. Although Si-MOSFET
designs can be realized at considerably higher switching frequency than IGBTs, the cost of high-current
and high-voltage Si MOSFETs is considerably higher than IGBTs.
2
Advantages of Wide Bandgap SiC
The primary advantage of SiC MOSFETs over Si MOSFETs is the availability of very low RDS(on) and high
voltage ratings; up to 1200 V at 25 mΩ. SiC devices are capable of faster switching speeds than Si
MOSFETs due to the very low parasitic capacitance and associated charge during switching, refer to
Table 1 for details. Although the SiC MOSFET is driven with higher peak-to-peak gate-to-source voltage,
per the device recommendation, the total gate charge of the SiC device is over 15 times lower than an
equivalent Si MOSFET. A characteristic that must be considered in any converter design is the RDS(on) at
the anticipated highest junction temperature. SiC MOSFETs exhibit a much lower increase in RDS(on) at
high temperature than Si MOSFETs. The example SiC MOSFET curves indicate approximately 1.25 times
increase in RDS(on) from 25°C to 125°C, where the Si MOSFET curves indicate approximately 2.2 times
increase in RDS(on). At 125°C the conduction losses are higher on the Si MOSFET since the RDS(on) is
approximately 265 mΩ versus the SiC RDS(on) of 150 mΩ.
(1)
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1
SiC MOSFET Characteristics
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Table 1. SiC vs Si MOSFET Parameter Table 900 V, 120 mΩ
900 V/120 mΩ
Qg (nC)
td(on) (ns)
trise (ns)
td(off) (ns)
Tfall (ns)
Si N-Ch
270
70
20
400
25
RDS(on) factor 25–125°C
2.2
SiC N-Ch
17.3
27
10
25
8
1.25
Si IGBT characteristics include high voltage ratings and low saturation voltage at very high current,
resulting in the equivalent of a very low RDS(on) MOSFET. The well-known switching frequency limitation of
IGBTs is the long current tail during turnoff which can exceed 300 ns even with the higher switching
frequency rated devices. The IGBT long collector current fall time results in turnoff switching losses that
can be 6 to 10 times higher than SiC MOSFETs.
3
SiC MOSFET Characteristics
SiC MOSFETs have a relatively low transconductance compared to Si MOSFETs. The result is a higher
gate-to-source voltage required to achieve the lowest VDS saturation voltage at high drain current. Where
most Si MOSFETs achieve low VDS saturation at 8 V to 10 V on the gate to source, SiC MOSFETs
typically require 15 V to 20 V VGS to achieve low VDS saturation.
The turnon threshold voltage of SiC is similar or lower than Si MOSFETs which results in a larger VGS
transition when the SiC MOSFET is operating as a variable resistance.
The fast switching speed and low turnon threshold of SiC MOSFETs requires a negative VGS level during
turnoff. Depending on the device, –2 V to –5 V drive is recommended for SiC devices. Although the
MOSFET parasitic CDS (CRSS) is very low, the high VDS dV/dt during turnoff can result in coupling enough
charge from the drain-to-gate capacitance to reach the threshold voltage if negative drive and a closecoupled driver layout is not in place.
3.1
MOSFET Switching Transient Process and Effects of MOSFET Parasitics
The details of the MOSFET turnon and turnoff transient events are similar for Si and SiC MOSFETs. Both
devices have parasitic CDS, CGD, and CGS. Also Si and SiC CGD and CDS are dynamic, depending on the
voltage level, much higher capacitance at a lower voltage level, and CGS is relatively flat. There are
detailed studies of the MOSFET switching transients from universities and device manufacturers. The
following is a general summary of the switching transients in a continuous current power train for
reference.
3.1.1
MOSFET Turnon Transient
The turnon event is generally the process of charging the MOSFET parasitic capacitances to the voltage
level required to achieve low RDS(on). A basic step-by-step process is presented. Refer to Figure 1 and
Figure 2 for the current flow and timing illustrations:
1. Pulse-width modulation (PWM) and driver start charging CGS to the MOSFET turnon plateau.
• The MOSFET plateau is defined as the VGS threshold plus the voltage delta required to conduct the
current amplitude flowing in the inductor, IL. The transconductance of the MOSFET and current
level determine the additional voltage required over the threshold voltage.
2. At the VGS plateau, the VDS begins to fall to ground. During the fall time to ground, the negative dV/dt of
the drain generates a current flowing through CGD that opposes the current from the gate-driver circuit,
known generally as Miller effect current. The duration of this current flow is the VDS fall time. Also note
that the internal FET gate terminal is a lower voltage potential than observed on the gate terminal, due
to the Miller current flowing into the internal FET resistance, RG.
3. After the VDS fall time, the gate is charged to the level determined by the driver source voltage. The
MOSFET achieves the lowest RDS(on) based on the particular device parameters. Typically 8–10 V for
high voltage Si MOSFETs and 15–20 V for SiC MOSFETs.
2
UCC27531 35-V Gate Driver for SiC MOSFET Applications
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SiC MOSFET Characteristics
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IL
PWM
+
VIN
VDS
ID
CGD
VDD
time
VOUT
-
OUTH
RON
OUTL
ROFF
VDS Falling
ID
VDD
VDS
6
EN
PWM
+
VPlateau
5
CGS
IG
GND
IN
VGS
CDS
RG
Vth
4
IG
VGS Rising
t0 t1 t2
Figure 1. Turnon Circuit with Parasitic Capacitance
3.1.2
t3
t4
Figure 2. Turnon Waveform
MOSFET Turnoff Transient
The turnoff event is generally the process of discharging the MOSFET parasitic capacitances to the
voltage level required to achieve the off state. A basic step-by-step process is presented in the following
list. Refer to Figure 3 and Figure 4 for the current flow and timing illustration.
1. PWM and driver start discharging CGS to the MOSFET turnoff plateau.
2. At the VGS plateau, the VDS begins to rise from ground. During the rise time of VDS, the positive dV/dt of
the drain generates a current flowing through CGD that opposes the current from the gate-driver circuit,
known generally as Miller-effect current. The duration of this current flow is the VDS rise time. Also note
that the internal FET-gate terminal is at a higher voltage than observed on the gate terminal due to the
Miller current flowing through the internal FET resistance, RG.
3. After the VDS rise time, the gate is discharged from the plateau voltage to the driver ground reference.
IL
VIN
+
VOUT
í
ID
VDD
OUTH
EN
OUTL
+
CDS
RG
5
GND
IN
iD
VCC
vGS
CGS
IG
vDS
VDD
RON
ROFF
time
VDS Rising
CGD
6
PWM
PWM
4
VGS Falling
iG
Vth
Figure 3. Turnoff Circuit with Parasitic Capacitance
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Figure 4. Turnoff Waveform
UCC27531 35-V Gate Driver for SiC MOSFET Applications
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3
UCC27531 Advantages for SiC MOSFET Applications
4
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UCC27531 Advantages for SiC MOSFET Applications
The driver circuit voltage required for driving SiC MOSFETs within the recommended conditions includes
the sum of the positive gate-drive level and negative-drive level. Some SiC MOSFETs recommend a
positive voltage level close to 20 V and a negative drive of –5 V. The driver IC rating in this case requires
25 V minimum, plus margin for tolerance of the bias voltage and possible disturbance from line transients.
The UCC27531 VDD rating of 35 V allows the user to optimize the SiC MOSFET drive levels and have
considerable UCC27531 VDD rating margin. Many MOSFET drivers are rated at 20 V or 25 V resulting in
lower than optimum drive levels, operating very close to the driver IC VDD rating or a combination of both.
Similar to driving Si MOSFETs, the optimized turnon gate-drive resistance is usually higher than the
turnoff gate-drive resistance in a well-tuned SiC driver circuit. The process of optimizing the gate drive for
low switching losses and minimizing ringing of the VDS waveform, typically results in some gate resistance
for turnon and a lower or no resistance for gate-drive turnoff. The UCC27531 features separate high-side
and low-side driver pins to program the optimum turnon and turnoff gate resistance. The separate pins
eliminate the need for the parallel resistor and diode combination normally used with most single-pin
output drivers. Eliminating the gate-drive diode drop is also advantageous to clamp VGS low during the
high dV/dt VDS transition at turnoff.
Adequate available gate-drive current for SiC MOSFETs is important for a couple of reasons. The low
threshold and relatively low transconductance results in a larger voltage swing on the gate when the
MOSFET is in the variable resistance region. A fast transition through the variable resistance region
results in achieving the lowest VDS saturation in less time. The other consideration for driver sink current is
the capability to clamp the VGS low during the very fast VDS rise times that SiC MOSFETs can achieve.
4
UCC27531 35-V Gate Driver for SiC MOSFET Applications
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UCC27531 SiC Demonstration Circuit
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5
UCC27531 SiC Demonstration Circuit
A common circuit knows as the double pulse tester is utilized in testing power devices is used to
demonstrate the switching waveforms. Refer to Figure 5 for the circuit schematic. A boost configuration is
used as the power train for the SiC switching test. The power device can be switched at the desired VDS
and ID peak current by adjusting the on time and frequency of the driver input. Since the output is
connected to the input, the boost voltage is the VF of the boost diode; hence the off time must be long to
allow the inductor current to decline to the desired turnon current. In order to keep layout parasitic
inductance as low as possible, a low inductance 50-mΩ current shunt is used to measure the current on
the SiC MOSFET source. All probe connections are Kelvin-referenced to the MOSFET device pins, and
current shunt.
The details of turnon and turnoff are examined with the SiC MOSFET in hard-switching operation at high
drain-to-source voltage and high drain-current condition.
600 µH
+
VIN
SiC Schottky Diode
VOUT
í
UCC27531
OUTH
EN
1
IN
2
+
OUTL
DUT
0Ÿ
1200 V
80 mŸ
5
GND
VDD
3
18 V
15 Ÿ
6
4
+
í
+
4.3 V í
50-mŸ Low Inductance Shunt
Figure 5. UCC27531 SiC MOSFET Demonstration Circuit Diagram
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Test Data
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6
Test Data
6.1
Test Data With Sufficient SiC MOSFET Drive
The full cycle turnon and turnoff of the SiC MOSFET and the details of the turnon and turnoff are
presented in the following oscilloscope waveform graphs.
br
The waveform in Figure 6 illustrates the VDS high
dV/dt during the turnon and turnoff transitions.
The waveform clearly shows that the UCC27531
driver maintains the VGS voltage during the Miller
plateau during turnon without any significant
negative voltage being induced.
space
During turnoff, the VGS is falling and held low by
the UCC27531 driver during the entire VDS rising
edge.
a
CH1 ± VDS: 100 V/div
CH2 ± VGS: 10 V/div
CH4 ± IS: 5 A/div
Figure 6. VDS, VGS, IS Switching Cycle
br
The expanded scale zoom in Figure 7 of the
turnon transition shows the VDS falling within 30 ns
and the Miller plateau occurring at approximately
12-V VGS. The gate voltage initial rise to VDS falling
is approximately 30 ns and the gate voltage is
maintained without significant dip during the VDS
rise time. This is with 15-Ω resistance for the
driver OUTH source current.
CH1 ± VDS: 100 V/div
CH2 ± VGS: 10 V/div
CH4 ± IS: 5 A/div
Figure 7. VDS, VGS, IS Turnon Transition
br
The expanded scale zoom in Figure 8 of the
turnoff transition shows the VDS rising within 21 ns
and the Miller plateau occurring at approximately
12-V VGS. The gate voltage initial fall to VDS rising
is < 20 ns and the gate voltage is falling during the
entire VDS rising time. If the driver does not have
adequate sink current, the fast dV/dt on VDS can
cause the VGS to rise during the turnoff event,
extending the turnoff switching time and increasing
switching loss. The VGS ringing peaks are below
ground due to the negative drive bias.
CH2 ± VGS: 10 V/div
CH4 ± IS: 5 A/div
CH1 ± VDS: 100 V/div
Figure 8. VDS, VGS, ID Turnoff Transition
6
UCC27531 35-V Gate Driver for SiC MOSFET Applications
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Test Data
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6.2
Test Data With Inadequate SiC MOSFET Drive
If the SiC MOSFET driver is not rated for adequate VDD voltage to provide the suggested operating
conditions for VGS high plus the recommended negative drive voltage, the driver will not be able to fully
enhance the MOSFET to the lowest RDS(on), or the VGS may not be held to voltages comfortably below the
threshold during switching. Also, if the driver does not have adequate current drive capability, the VGS may
not be maintained at the plateau during turnon or below the threshold during turnoff.
Figure 9 and Figure 10 show example waveforms that occur if the gate drive does not have adequate
parameters to support well-tuned switching of SiC MOSFETs.
br
Figure 9 illustrates the lack of negative drive on
the SiC MOSFET.
space
Without the negative drive bias, the VGS does not
have the margin to comfortably avoid the gate
threshold voltage that can be as low as 1.6 V to 2
V during the turnoff transition.
a
CH2 ± VGS: 10 V/div
VGS Ring § 2 V
CH4 ± IS: 5 A/div
CH1 ± VDS: 100 V/div
Figure 9. VDS, VGS, IS Turnoff,
No Negative Drive
br
Figure 10 illustrates if the gate drive has
inadequate sink current. The lower sink current
was duplicated by inserting a 10-Ω series
resistance into the OUTL driver path.
space
Without high sink current capability from the driver,
the driver cannot prevent the VGS from rising due
to the Miller charge coupled into the gate during
the VDS rising. The VGS can rise close to the
threshold voltage and inhibit or delay the turnoff
transition.
CH2 ± VGS: 10 V/div
VGS Ring § 2 V
CH4 ± IS: 5 A/div
CH1 ± VDS: 100 V/div
Figure 10. VDS, VGS, IS, Reduce
Driver Sink Current
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7
Increasing the UCC27531 VDD Turnon
7
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Increasing the UCC27531 VDD Turnon
Most high power systems' sequencing usually allows time or monitoring for the bias supply voltages to
reach the normal operating point before the power train switching is enabled. If the power up sequencing
is not controlled, or if there are concerns about fault conditions of the controller and driver bias, the UVLO
of the UCC27531 can be increased from the device's internal threshold of 8.9 V.
A simple voltage supervisor as shown in Figure 11 increases the VDD turnon of the UCC27531 to the
desired threshold. The TPS3711 has a VDD rating of up to 36 V, so the VDD operating range of the
UC27531 is not compromised.
The UCC27531 enable pin has an internal pullup resistance connected to a 5.6-V bias, which is
compatible with the open-drain configuration of the TPS3711. The open-drain configuration of the
TPS3711, and internal pullup of the UCC27531 allows the user to program the desired VDD turnon and
hysteresis, if desired, by connecting a resistance from the TPS3711 OUT to SENSE pins.
UCC27531
TPS3711
EN
Optional
Hysteresis
GND
OUT
1
6
2
5
GND
1
IN
2
+
VDD
3
VIT
+
+ Bias
4
OUTL
ROFF
GND
3
R1
RON
5
VDD
GND
SENSE
OUTH
6
4
+
í
+
í
íBias
R2
Figure 11. TPS3711 to Program UCC27531 UVLO Thresholds
Determine TPS3711 resistor values based on Equation 1.
(VVDD _ ON - VIT + ) ´ R2
R1 =
VIT +
where
•
•
•
R2 recommended range is 20 kΩ to 50 kΩ.
VVDD_ON is target VDD UVLO turn on threshold
VIT+ is the TPS3711 SENSE pin positive input threshold, 405.5 mV nominal.
(1)
There is hysteresis on the TPS3711 SENSE pin with a falling threshold of 400 mV nominal (VIT–). The
UVLO turn off is determined using Equation 2:
VIT - ´ VVDD _ ON
VVDD _ OFF =
VIT +
where
•
•
VDD_ON = 12 V
VDD_OFF = 11.83 V
(2)
The hysteresis can be increased as shown in Figure 11 with an additional resistor.
8
UCC27531 35-V Gate Driver for SiC MOSFET Applications
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Layout Recommendations
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8
Layout Recommendations
The switching speed of SiC MOSFETs makes it critical to provide close placement and good layout of the
gate-driver circuit. The driver IC performance will be compromised if the gate-drive layout loop parasitic
inductance is not kept to a minimum. Compact layout becomes simple due to the UCC27531's small
package size and separate IC pins for the high- and low-side drive. A driver layout illustrating close
placement and short connections is shown in Figure 12.
SiC FET
UCC27531
íBias
OUTH 6
2 IN
OUTL 5
3 VDD
GND 4
R
1 EN
C
C
GND
Figure 12. Driver and MOSFET Layout
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9
Conclusion
9
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Conclusion
Silicon Carbide MOSFETs are capable of very good switching performance in high-voltage, high-power
applications. In order to maximize the capabilities of the SiC power MOSFETs, a high performance gatedrive circuit and good driver layout is required. The negative drive bias requirement and higher optimum
positive VGS require a drive circuit with higher VDD ratings than typical Si MOSFET drivers. The UCC27531
35-V rating allows the designer to optimize the drive levels and have considerable driver circuit margin.
The fast switching of SiC devices will challenge many typical driver circuits during the switching
transitions. The Miller charge can inhibit or even cause false triggering during the switching events if the
driver is not low enough resistance, or high enough current capability. Also, since the SiC MOSFETs have
a larger VGS delta in the variable-resistance region, it is important to slew the VGS as fast as possible. The
UCC27531 split pins for the high- and low-side drive circuits provides an advantage to maintaining the VGS
during the Miller plateau. Additionally, the drive current capability of the UCC27531 enables fast turnon
and turnoff of SiC MOSFETs. The UCC27532 is a driver in the same family as the UCC27531 and has
CMOS compatible input thresholds if increased input threshold hysteresis is desired.
10
References
1. Infineon “IPW90R120C3 CoolMOS Power Transistor Datasheet,” Rev 1.0, July 30, 2008
2. Cree “C3M01120090D Silicon Carbide Power MOSFET Datasheet,” November, 2015
3. Jimmy Liu, Kin Lap Wong, Scott Allen, John Mookken, “Performance Evaluations of Hard-Switching
Interleaved DC/DC Boost Converter with New Generation Silicon Carbide MOSFETs”
4. Cree “Application Considerations for Silicon Carbide MOSFETs”, (Online) under “Power Application
Notes”
Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Original (#IMPLIED) to A Revision .......................................................................................................... Page
•
10
Changed Figure 4. ........................................................................................................................ 3
Revision History
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