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Texas Instruments How to Estimate Overshoot and Undershoot of Load Transients of a DC/DC Regulator Application notes
Application Report
SLUA847 – December 2017
How to Estimate Overshoot and Undershoot of Load
Transients of a DC/DC Regulator
Luke Pan, Iven Su
ABSTRACT
In a DC-to-DC circuit design, output capacitance is a critical design parameter, which directly affects the
output voltage ripple, loop stability, and the overshoot and undershoot during load transient. The intent of
this application report is to show how to estimate the overshoot and undershoot of load transients of a
design before PCB fabrication. A typical topology, peak current mode (PCM) control buck regulator circuit,
is used as an example to explain the mechanism.
1
2
3
4
Contents
PCM Buck Regulator Block Diagram......................................................................................
Load Transient Analysis in Both Frequency and Time Domain .......................................................
2.1
PCM Buck Regulator Small Signal Model .......................................................................
2.2
Overshoot and Undershoot Prediction ...........................................................................
Simulation Verification.......................................................................................................
3.1
Output Filter Components Design ................................................................................
3.2
Compensation Circuit Design .....................................................................................
3.3
Comparison of Simulation and Calculation Result .............................................................
References ...................................................................................................................
2
2
2
3
5
5
5
6
7
List of Figures
1
Simplified Schematic of PCM Buck Regulator ........................................................................... 2
2
PCM Buck Regulator Small Signal Model ................................................................................ 2
3
Simplis™ Simulation Circuit ................................................................................................ 7
4
Comparison of Simulation and Calculation Result
......................................................................
7
List of Tables
1
Design Example Specifications ............................................................................................ 5
2
Design Parameters .......................................................................................................... 6
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1
PCM Buck Regulator Block Diagram
1
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PCM Buck Regulator Block Diagram
For most popular DC/DC regulators available, the switching frequency gets extremely high, may reach
several MHz, which allows smaller output inductance and capacitance. In many cases, output capacitance
is small, allowing the use of only ceramic capacitors. In this application report, ceramic capacitors with low
ESR and ESL are employed for the analysis.
Figure 1 shows a simplified schematic of PCM buck regulator.
VOUT
iL
COUT
RL
RSNS
VIN
VFB
QN
R
Q
S
VCOMP
Clock
Gm
RCOMP
VREF
RFBT
RFBB
CCOMP
Figure 1. Simplified Schematic of PCM Buck Regulator
2
Load Transient Analysis in Both Frequency and Time Domain
2.1
PCM Buck Regulator Small Signal Model
Figure 2 shows a simplified small signal model of a PCM control buck regulator. This model adopts a
voltage controlled current-sourcing concept. In this model, the inductor current is treated as well-controlled
current source, which is a simple interpretation of current-loop effects. This model provides excellent
physical insight to readers, and is accurate enough for a preliminary design loop analysis.
GCS
÷i
L
_ ÷iOUT
ZO(s)
v÷ OUT
v÷ COMP
GEA(s)
v÷ ERR
_
v÷ FB
K
v÷ REF
Figure 2. PCM Buck Regulator Small Signal Model
Equation 1 through Equation 4 show calculations for some of the elements in Figure 2.
vÖ FB
RFBB
VREF
K
vÖ OUT RFBT RFBB
VOUT
where
•
2
K is the feedback divider proportionality coefficient.
How to Estimate Overshoot and Undershoot of Load Transients of a DC/DC
Regulator
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(1)
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Load Transient Analysis in Both Frequency and Time Domain
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vÖ COMP
vÖ ERR
G EA s
§
G m u ¨ R COMP
¨
©
1
s u C COMP
·
¸
¸
¹
where
•
•
•
GEA(s) is the compensation circuit transfer function
Gm is the gain of the transconductance amplifier
RCOMP and CCOMP is the compensation RC
Öi
L
GCS
vÖ COMP
(2)
1
RSNS
where
•
ZO s
GCS is the transconductance of inductor current sense circuit, which is the reciprocal value of the
current sense resistor RSNS in Figure 1
vÖ OUT
Öi
L
(3)
RL
1
|| R L
s u C OUT
1
s u COUT u R L
where
•
ZO(s) is open-loop output impedance, because the inductor current is treated as voltage controlled
current-sourcing, so the open-loop output impedance equals the output capacitance COUT parallel with
the load resistance RL
(4)
The open-loop transfer function T(s) can be derived by multiplying every element in the loop (see
Equation 5):
T s
K u G EA s u G CS u Z O s
VREF
VOUT
§
u G m u ¨ R COMP
¨
©
1
C COMP
·
1
u
¸u
¸ R SNS 1
¹
RL
s u C OUT u R L
Then the close-loop output impedance can be calculated by Equation 6.
vÖ OUT
ZO s
Z OC s
Öi
1 T s
OUT
2.2
(5)
(6)
Overshoot and Undershoot Prediction
According to the definition, the output variation vOUT(s) equals the output impedance ZOC(s) multiplying the
load variation iOUT(s). For a transient load step of ΔIOUT, it can be transferred to ΔIOUT/s according to the
Laplace transform (see Equation 7).
Â, OUT
=O V
Öi
vÖ OUT s
u
OUT s u Z OC s
s
1 T s
(7)
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Load Transient Analysis in Both Frequency and Time Domain
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The entire small signal analysis is based on frequency domain; however, the system-required overshoot
and undershoot limitation specification is defined in time domain. To obtain the time domain behavior of
vOUT(t), transfer vOUT(s) into time domain with inverse Laplace transform. With the help of the mathematic
tool Mathcad®, finally a simplified time domain equation is derived by doing inverse Laplace transform of
Equation 7 (see Equation 8):
vÖ OUT t
InvLaplace vÖ OUT s
- Â,
u H A×tu VLQ % $ 2 u W
° OUT
°
COUT u B - A 2
°
|®
2
2
° Â, OUT u H A×t u H A -B×t H A
°
°
2 u C OUT u A 2 B
¯
while A 2 < B
B×t
while A 2 > B
where
A
G m u G CS u VREF u R COMP
2 u C OUT u VOUT
•
G m u G CS u VREF
B
C OUT u VOUT u C COMP
•
(8)
To get the overshoot peak value or undershoot valley value, calculate the extremum point tEP when the
derivative of vOUT(t) equals 0 (see Equation 9).
dv÷ OUT t EP
dt
- 'I u e
° OUT
°
°
°
®
ª
° 'I OUT u «
°
«¬
°
°¯
Au t EP
u ª B A2 u cos
¬«
B A2 u t EP
C OUT u B A
§ A 2 B A ·u t
¨
¸ EP
¹
A 2 B A u e©
A u sin
B A2 u t EP º
¼»
0 whileA2
B
2
A2 B
§
¨
A2 B A ¸·u t EP
¹
A u e©
º
»
»¼
2 u C OUT u A2 B
0 whileA2 ! B
(9)
According to Equation 10, tEP can be calculated:
t EP
§ B A2
° arctan ¨
¨
A
°
©
°
°°
B A2
®
° §A
A2 B
° ln ¨
A2 B
° ¨© A
°
2
°̄ 2 u A B
·
¸
¸
¹
while A 2
·
¸
¸
¹
while A 2 ! B
B
(10)
Substitute tEP back into Equation 8, calculate the overshoot peak value or undershoot valley value with
Equation 11.
VOS/US
VOUT
vÖ OUT t EP
°
° VOUT
°
|®
°
°V
° OUT
¯
Â, OUT u H
A u tEP
u VLQ
% $ 2 u W EP
COUT u B A
Â, OUT u H
A u tEP
u H
while A 2
B
2
A 2 B×tEP
2 u COUT u A
2
H-
A 2 -B utEP
while A 2 ! B
B
(11)
VOUT(t) values at every moment can be calculated with Equation 11. So a time-continuous curve can be
plotted with a mathematic tool like Mathcad or Excel.
4
How to Estimate Overshoot and Undershoot of Load Transients of a DC/DC
Regulator
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Simulation Verification
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3
Simulation Verification
Here we take TPS54335A as an example. We have made a design of a PCM buck regulator, working in
the condition involved: VIN = 12 V, VOUT = 5 V, switching frequency 1 MHz, max load current 3 A. Load
transient from 1 A to 3 A ( ΔIOUT = 1 A – 3 A = –2 A ).
Table 1. Design Example Specifications
3.1
Design Parameter
Value
Input voltage, VIN
9 V to 15 V, Typical 12 V
Output voltage, VOUT
5.0 V
Maximum output current IOUT_MAX
3A
Undershoot or overshoot during load transient of 1 A to 3 A
3% of VOUT
Switching frequency, fSW
1 MHz
TPS54335A reference voltage, VREF
0.8 V
TPS54335A error amplifier gain, Gm
1.3 A/V
TPS54335A power stage gain, GCS
8 A/V
Output Filter Components Design
The inductance is based on the desired peak-to-peak ripple current ΔiL. Because the ripple current
increases with the input voltage, the maximum input voltage is always used to calculate the minimum
inductance LMIN. Use Equation 12 to calculate the minimum value of the output inductor. KIND is a
coefficient that represents the amount of inductor ripple current relative to the maximum output current. A
reasonable value of KIND should be 30% to 50%. For this application, choose KIND = 0.5 for smaller
inductance.
VOUT
VIN_MAX - VOUT
15 - 5
5
L MIN
u
u
2.2 é+
I OUT_MAX u KIND VIN_MAX u SW
f
3 u 0.5 15 ×1
(12)
The desired response to a large load current change is usually the first criterion for output capacitance
selection. When a large load step occurs, output capacitors provide the required charge before the
inductor current can regulate to the appropriate level. The control loop of the regulator usually needs
several clock cycles to regulate the inductor current equal to the new load level. The output capacitance
must be large enough to supply or absorb the current difference to maintain the output voltage within the
specified range. An engineering empirical formula, Equation 13, shows the minimum output capacitance
needed for specified output overshoot or undershoot.
COUT
§ 1
1 ·
Â,OUT u ¨
¸
© 4 u fC fSW ¹
!
2 u Â9OUT
§
1
2u¨
© 4 u 0.05
u u
1·
¸
1¹
40 uF
where
•
fC = crossover frequency
(13)
A good starting value for fC is 1/20 to 1/10 of the switching frequency, fSW.
For this application, choose fC to be 1/20 × 1 MHz = 0.05 MHz. To leave some margin, choose 47 µF as
the COUT.
3.2
Compensation Circuit Design
The general design guidelines for device loop compensation are as follows:
1. Determine the crossover frequency, fC. In this application, choose fC = 0.05 MHz.
2. Use Equation 14 to calculate the value of RCOMP. A standard 8.87-kΩ resistor is selected as RCOMP.
R COMP
2í u I C u & OUT u 9 OUT
VREF u G m u G CS
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u
u
2í u
0.8 u 1.3 u 8
8.9 kÖ
How to Estimate Overshoot and Undershoot of Load Transients of a DC/DC
Regulator
Copyright © 2017, Texas Instruments Incorporated
(14)
5
Simulation Verification
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3. Design the RCOMP and CCOMP zero at 1/4 of the fC. CCOMP can be calculated by Equation 15.
2
í u I C u 5 COMP
C COMP
2
íu
1.4 nF
u
(15)
A standard 1.5-nF capacitor is selected as CCOMP.
3.3
Comparison of Simulation and Calculation Result
After completing the previous design procedure, all the design parameters are obtained in Table 2.
Table 2. Design Parameters
L
COUT
RL
VREF
Gm
RCOMP
CCOMP
GCS
2.2 µH
47 µF
5Ω
0.8 V
1.3 mA/V
8.87 kΩ
1.5 nF
8 A/V
With all the known parameters in Table 2, A and B can be calculated by and .
G m u G CS u VREF u R COMP
A
1.57 u 105
2 u COUT u VOUT
B
G m u G CS u VREF
COUT u VOUT u CCOMP
(16)
2.36 u 1010
(17)
2
Because A > B, the critical point tEP can be calculated by the second formula in Equation 10.
t EP
§A
ln ¨
¨A
©
B·
¸
B ¸¹
A2
A2
2u A
2
6.46 u 10
6
B
(18)
Finally, the undershoot can be calculated by Equation 11.
Â,OUT u H
VOS/US
VOUT
vÖ OUT tEP | VOUT +
A×t EP
§
u ¨H
©
A 2 B×t EP
2 u C OUT u A 2 B
H
A 2 B×t EP
·
¸
¹
4.9 V
(19)
To verify the calculation result, we built a simulation model of PCM buck regulator according to Figure 1 in
Simplis™. Figure 3 shows the Simplis simulation circuit diagram. A load transient from 1 A to 3 A occurs
at 0.1 ms (Figure 4 shows the simulation result). The undershoot valley value 4.9 V occurs at 6.5 µs after
the load transient happens, which is almost the same as the calculated values in Equation 18 and
Equation 19. In Figure 4, an additional time-continuous curve is plotted using Mathcad with Equation 11.
The calculated curve matches well with the simulated curve during the entire period.
6
How to Estimate Overshoot and Undershoot of Load Transients of a DC/DC
Regulator
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GCS = 1 / ( 10 PŸ [ 12.5 )
= 8 A/V
Figure 3. Simplis™ Simulation Circuit
5.02
5
Simplis
Mathcad
VOUT (V)
4.98
4.96
4.94
4.92
( 0.107 ms, 4.9 V )
4.9
6.5 µs
4.88
0
0.05
0.1
0.15
0.2
0.25
Time (ms)
Figure 4. Comparison of Simulation and Calculation Result
4
References
1. CHEN Xiao-fei, ZOU Xue-cheng, CHENG Jun, YU Kai, LIN Shuang-xi. "System Modeling and Stability
Design for Peak Current-mode Buck Power Converter."
2. S. P. Hsu, A. Brown, L. Rensink, and R. D. Middlebrook, "Modeling and analysis of switching dc-to-dc
converters in constant-frequency current-programmed mode."
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