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Texas Instruments Two Parallel Synchronous 4-Switch Buck-Boost Converters With Master Slave Method Application notes
Application Report
SNVA792 – September 2017
Two Parallel, Synchronous Four-Switch Buck-Boost
Converters With Master Slave Method for Higher Power
Hongija Wu, Vijay Choudhary, Gautam Hari, Daniel Li, Kim Nielson
ABSTRACT
The synchronous, four-switch buck-boost controller LM5176 is widely used in automotive start-stop
systems, industrial PCs, and a variety of other applications. Paralleling two LM5176 converters is an
appealing way to meet a larger power requirement while providing many other benefits, such as enhanced
modularity, design flexibility, minimized component ratings, and so forth. The benefits, however, can only
be effective if the load currents of each module are equally shared, which is the fundamental difficulty of
paralleling supplies.
This application report addresses the use of an active current-sharing architecture that is based on a
dedicated master-slave method. Due to an elaborate external circuit with only a few components, the
slave can accurately follow the master to deliver the same amount of load current with an error within
±1.2%. Despite paralleling the converters, the other indexes of the whole system remain satisfactory,
including load regulation, load transient, start-up, output ripple, and current limit behavior.
1
2
3
4
5
Contents
Introduction ................................................................................................................... 3
Active Current Sharing for Dedicated Master Slave and its Realization ............................................. 4
Test Results ................................................................................................................. 8
Conclusion .................................................................................................................. 20
Related Documentation.................................................................................................... 20
List of Figures
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
...................................................................... 4
Simplified Architecture of Dedicated Master-Slave Active-Current Sharing ......................................... 5
Adjust Output Voltage of Slave Unit Through FB Pin ................................................................... 6
Load Regulation of Parallel Power ....................................................................................... 8
Load Distribution of Two Phases .......................................................................................... 8
36-V Buck Region With 40-A Load—Four Switch Nodes .............................................................. 8
36-V Buck Region With 40-A Load—Inductor Current Waveforms ................................................... 8
12-V Buck-Boost Region With 40-A Load—Four Switch Nodes ...................................................... 8
12-V Buck-Boost Region With 40-A Load—Inductor Current Waveforms ........................................... 8
9-V Boost Region With 40-A Load—Four Switch Nodes ............................................................... 9
9-V Boost Region With 40-A Load—Inductor Current Waveforms .................................................... 9
Load Transient in 36-V Buck Region—With 20-A to 40-A Load Step ............................................... 10
Load Transient in 36-V Buck Region—With 0-A to 40-A Load Step ................................................ 10
Load Transient in 12-V Buck-Boost Region—With 20-A to 40-A Load Step ....................................... 10
Load Transient in 12-V Buck-Boost Region—With 0-A to 40-A Load Step ........................................ 10
Load Transient in 9-V Boost Region—With 20-A to 40-A Load Step ............................................... 10
Load Transient in 9-V Boost Region—With 0-A to 40-A Load Step ................................................. 10
Output Voltage Ripple in 36-V Buck Region—No Load ............................................................... 11
Output Voltage Ripple in 36-V Buck Region—40-A Load ............................................................ 11
Simplified Architecture of Active Current Sharing
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20
Output Voltage Ripple in 12-V Buck-Boost Region—No Load ....................................................... 11
21
Output Voltage Ripple in 12-V Buck-Boost Region—40-A Load..................................................... 11
22
Output Voltage Ripple in 9-V Boost Region—No Load ............................................................... 12
23
Output Voltage Ripple in 9-V Boost Region—40-A Load ............................................................. 12
24
40-A Start-Up in 36-V Buck Region—Total Output Current Waveform ............................................. 13
25
40-A Start-Up in 36-V Buck Region—Two Phase Inductor Currents................................................ 13
26
40-A Start-Up in 12-V Buck-Boost Region—Total Output Current Waveform ..................................... 13
27
40-A Start-Up in 12-V Buck-Boost Region—Two Phase Inductor Currents ........................................ 13
28
40-A Start-Up in 9-V Boost Region—Total Output Current Waveform .............................................. 13
29
40-A Start-Up in 9-V Boost Region—Two Phase Inductor Currents ................................................ 13
30
Current Limit Behavior in 36-V Buck Region—Hiccup Enabled
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
.....................................................
Current Limit Behavior in 36-V Buck Region—No Hiccup ............................................................
Current Limit Behavior in 12-V Buck-Boost Region—Hiccup Enabled ..............................................
Current Limit Behavior in 12-V Buck-Boost Region—No Hiccup ....................................................
Current Limit Behavior in 9-V Boost Region—Hiccup Enabled ......................................................
Current Limit Behavior in 9-V Boost Region—No Hiccup.............................................................
40-A Load Thermal Condition in 36-V Buck Region ...................................................................
40-A Load Thermal Condition in 12-V Buck-Boost Region ...........................................................
40-A Load Thermal Condition in 9-V Boost Region ...................................................................
36-V Buck Region With 40-A Load—Four Switch Nodes .............................................................
36-V Buck Region With 40-A Load—Inductor Current Waveforms ..................................................
12-V Buck-Boost Region With 40-A Load—Four Switch Nodes .....................................................
12-V Buck-Boost Region With 40-A Load—Inductor Current Waveforms ..........................................
9-V Boost Region With 40-A Load—Four Switch Nodes .............................................................
9-V Boost Region With 40-A Load—Inductor Current Waveforms ..................................................
Output Voltage Ripple in 36-V Buck Region—No Load ...............................................................
Output Voltage Ripple in 36-V Buck Region—40-A Load ............................................................
Output Voltage Ripple in 12-V Buck-Boost Region—No Load .......................................................
Output Voltage Ripple in 12-V Buck-Boost Region—40-A Load.....................................................
Output Voltage Ripple in 9-V Boost Region—No Load ...............................................................
Output Voltage Ripple in 9-V Boost Region—40-A Load .............................................................
14
14
14
14
15
15
16
16
16
17
17
17
17
17
17
18
18
18
18
19
19
List of Tables
1
Component Parameters for Dedicated Master-Slave Active-Sharing Circuit ........................................ 7
Trademarks
All trademarks are the property of their respective owners.
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Introduction
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1
Introduction
The LM5176 is a synchronous, four-switch, buck-boost DC/DC controller capable of regulating the output
voltage at, above, or below the input voltage. The wide input voltage range of 4 V to 55 V (60-V
maximum) makes the controller suitable for automotive start-stop systems, industrial PCs, battery backup
systems, point-of-sale (POS) terminals, and a variety of other applications.
One single LM5176 converter can deliver power greater than 200 W because of its synchronous switching
topology; however, at a higher power, the increased switching and conduction losses can eventually
overwhelm a single converter due to excessive board heating. This overheating makes it necessary to
parallel power stages to distribute heat sources, which at the same time provides many other benefits:
enhanced modularity, design flexibility, and minimized component ratings. These benefits, however, can
only be effective if the load currents of each module are equally shared.
Many sources of literature address different load sharing implementations and often note the trade-off
between complexity and accuracy. When using the simplest structure and circuit, the droop-based current
sharing method can achieve a comparatively-accurate and even load distribution, at the cost of sacrificing
excellent load regulation performance. See Paralleling Power – Choosing and Applying the Best
Technique for Load Sharing (Balogh 2003) and Two Parallel, Synchronous, Four-Switch Buck-Boost
Converters With Droop Method for Higher Power for further details.
This application report presents a dedicated, master-slave-based, active-current sharing architecture. With
an elaborate external circuit of only a few components, the slave can accurately follow the master to
deliver the same amount of load current and with an error that is within ±1.2%. At the same time, all of the
other indexes of the entire system are satisfactory, including load regulation, load transient, start-up,
output ripple, and current limit behavior.
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Active Current Sharing for Dedicated Master Slave and its Realization
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Active Current Sharing for Dedicated Master Slave and its Realization
2.1
Active Current Sharing for Dedicated Master Slave
The most accurate way to achieve load sharing is through the means of a closed loop with negative
feedback, which also explains the origin of the name "active current sharing". The information for both of
the actual load currents and desired load currents must be available to make this approach work. The final
goal is to make load currents evenly distributed; therefore, the system must be able to generate the
information of average current for all the paralleled power supplies to follow. Figure 1 shows a simplified
architecture of the active current-sharing method, where ISNS is used to sample actual currents and ISHARE
serves as the load sharing bus and carries the average current information.
#1 LM5176
Power stage
ISNS
VIN
Driver1
±
CMP1
+
±
EA2
+
FB1
±
EA1
+
Load
VOUT
ISHARE
VREF
#2 LM5176
Power stage
ISNS
Driver2
±
CMP2
+
±
EA4
+
FB2
±
EA3
+
VREF
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Figure 1. Simplified Architecture of Active Current Sharing
As the previous Figure 1 shows, the actual output current of one power supply is compared to the average
current represented by the load sharing bus. The error is amplified and can be summed either to the FB
pin or to the reference voltage of the voltage error amplifier EA2 (EA4). After this step, the output voltage
of each power supply is adjusted to achieve equally-distributed load currents.
The designer can choose from three different solutions to implement the active current-sharing method;
however, the dedicated master-slave sharing, as compared to automatic master-slave sharing and
democratic load sharing, is an excellent combination of both high accuracy and less complexity.
Figure 2 shows the simplified architecture of the dedicated master-slave sharing. One power supply is the
master and the remaining power supply functions as the slave. Only the master controls the average
current information, which the load sharing bus represents, and the slave follows the master. Whenever
the master load is higher, the slave load adjusts higher by increasing its output voltage and vice versa.
In this case, the load sharing bus is actually the command bus for the slave unit. If the slave can deliver
exactly the same current as the master does, the total load perfectly distributes between two modules.
Consequently, the signal that the load sharing bus carries is equal to the average current in the system.
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Master LM5176
Power stage
ISNS
VIN
±
CMP1
+
±
EA2
+
Load
VREF
VOUT
ISHARE
Driver1
FB1
Slave LM5176
Power stage
ISNS
Driver2
±
CMP2
+
±
EA4
+
FB2
±
EA3
+
VREF
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Figure 2. Simplified Architecture of Dedicated Master-Slave Active-Current Sharing
2.2
Schematic Realization
Dedicated master-slave active-current sharing involves comparing the load of the slave to the load of the
master and then amplifying the error between these two using an error amplifier. Adjust the output voltage
of the slave unit by summing the error to either the FB pin or reference pin of the voltage error amplifier.
Figure 3 shows an intuitive schematic version, which adjusts the output voltage through the FB pin.
As Figure 3 shows, the output current of the master IM is sampled through RCS1 and amplified by the
current sense amplifier INA194. The RF1-CF1 network filters the corresponding voltage (VM). The VM then
serves as the command signal for the slave and is sent to the negative input of the error amplifier
LM8261. Similarly, VS, which carries the current information of the slave, is sent to the positive input of
LM8261. The INA194 device amplifies the error between VM and VS to VC. Use a coupling resistor divider
to inject or withdraw a current from the FB pin to adjust the output voltage of the slave lower or higher if its
output current IS is larger or smaller than that of the master unit IM.
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Master
VOM
RCS1
IM
VOUT
R3
LM5176
+
±
VIN
FB
RP
INA194
R4
RF1
CP
VC
R7
±
LM8261
+
CF1
VO
VM
Load
VS
R8
RF2
CF2
INA194
+
±
Slave
VOS
VIN
VIN
VOUT
IS
R1
LM5176
R5
RCS2
VFBs
FB
R2
R6
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Figure 3. Adjust Output Voltage of Slave Unit Through FB Pin
In the previous Figure 3, the network of the error amplifier LM8261 plays an important role. R7 and RP
determine the DC gain while RP and CP introduce a pole to the system. Assume the LM8261 to be an ideal
amplifier, meaning that the gain of LM8261 is infinite and no current flows into the input end. Under these
assumptions, Equation 1 can be calculated as follows:
VM - VS
=
VS - VC
R7
ZP
(1)
where ZP equals as follows in Equation 2:
ZP =
RP
sR PC P +1
(2)
therefore, calculate VC as follows in Equation 3.
VC = VS -
VM - VS
R7
ZP
(3)
VM serves as the command signal (for AC small signal analysis); therefore, write the gain A1 from VS to VC
as follows in Equation 4.
Z
RP
A1 = 1 + P = 1 +
R7
R7 ´ (sRP CP + 1)
(4)
According to Equation 4, the DC gain approximately equals RP / R7 and the pole locates at:
1 / (2π × RP × CP). Because the current-sharing loop has a position on the outmost section of the whole
system, its bandwidth must be an approximate one-fifth to one-tenth of the inner loop (from VOS to VOS and
from VOM to VOM) to prevent chaos.
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If an extreme condition were to occur, the output of LM8261 has the risk of being railed to the VCC or
ground. Carefully select R5 and R6 to ensure control of the output voltage of the slave unit. According to
the previous Figure 3, the node current calculation for the FB pin is as follows in Equation 5:
VC - VFBs
R5
+
VOS - VFBs
R1
=
VFBs
R 2 || R 6
(5)
therefore, write VOS as follows in Equation 6.
æ
R1
R ö
R
+ 1 ÷ ´ VR - 1 ´ VC
VOS = ç 1 +
R
||
R
R
R
2
6
5 ø
5
è
(6)
Substitute VC with VCC and ground to obtain two corresponding VOS values. For a 12-V output condition,
with R1 equal to 280 kΩ and R2 equal to 20 kΩ, select R5 as 800 kΩ and R6 as 400 kΩ to establish the
boundary of VOS as 12.84 V and 10.27 V.
Table 1 lists all of the component parameters for the dedicated master-slave active-sharing circuit.
Table 1. Component Parameters for Dedicated Master-Slave Active-Sharing Circuit
RCS1 (mΩ)
RF1 (kΩ)
CF2 (µF)
R7 (kΩ)
RP (MΩ)
R5 (kΩ)
R1 (kΩ)
R2 (kΩ)
2
1
1
1
1
800
280
20
RCS2 (mΩ)
RF2 (kΩ)
CF2 (µF)
R8 (kΩ)
CP (µΩ)
R6 (kΩ)
R3 (kΩ)
R4 (kΩ)
2
1
1
1
1
400
280
20
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Test Results
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3
Test Results
3.1
Load Regulation and Load Distribution
Figure 4 shows the load regulation of the whole system. The variation of the output voltage is within
±2.5%, which indicates an excellent load regulation performance. Figure 5 shows the test results of a load
distributed over an increasing load. Under different input voltage conditions, the output current lines of the
master and slave nearly overlap and the error at a 40-A full load is within ±1.2%.
22
12.08
20
18
Load of Each Phase
Output Voltage (A)
12.06
12.04
12.02
VIN = 9 V
VIN = 12 V
VIN = 20 V
VIN = 36 V
4
8
12
16
20
24
Total Load (A)
28
32
36
12
10
8
6
4
VIN = 9 V, LOAD1
VIN = 9 V, LOAD2
VIN = 12 V, LOAD1
VIN = 12 V, LOAD2
0
40
VIN = 20 V, LOAD1
VIN = 20 V, LOAD2
VIN = 36 V, LOAD1
VIN = 36 V, LOAD2
-2
0
4
8
snva
Figure 4. Load Regulation of Parallel Power
3.2
14
2
12
0
16
12
16
20
24
Total Load (A)
28
32
36
40
snva
Figure 5. Load Distribution of Two Phases
SYNC Operation
Use the RT/SYNC pin of the LM5176 device to synchronize the pulse-width modulation (PWM) controller
to an external clock. The clocks for two parallel LM5176 converters can either be in-phase or 180° out-ofphase. With in-phase clocks, the current distribution condition is more intuitive.
Figure 6 through Figure 11 show the four switching nodes and inductor current waveforms in the 36-V
buck, 12-V buck-boost, and 9-V boost regions, respectively. The waveforms show that each operation
region is stable and the inductor current waveforms of the two phases nearly overlap, which indicates
equally-distributed load currents.
SW1 (#1)
IL1
IL2
SW2 (#1)
SW1 (#2)
SW1 (#1)
SW2 (#2)
Figure 6. 36-V Buck Region With 40-A Load—Four
Switch Nodes
8
SW2 (#1)
Figure 7. 36-V Buck Region With 40-A Load—Inductor
Current Waveforms
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SW1 (#1)
IL2
IL1
SW2 (#1)
SW1 (#1)
SW1 (#2)
SW2 (#1)
SW2 (#2)
Figure 8. 12-V Buck-Boost Region With 40-A Load—Four
Switch Nodes
Figure 9. 12-V Buck-Boost Region With 40-A
Load—Inductor Current Waveforms
IL1
SW1 (#1)
IL2
SW1 (#1)
SW2 (#1)
SW1 (#2)
SW2 (#1)
SW2 (#2)
Figure 10. 9-V Boost Region With 40-A Load—Four
Switch Nodes
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Figure 11. 9-V Boost Region With 40-A Load—Inductor
Current Waveforms
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Figure 12 through Figure 17 show the load transient waveforms in the 36-V buck, 12-V buck-boost, and
9-V boost regions, respectively. The waveforms show two load-step conditions of 20 A to 40 A and 0 A to
40 A.
Io
Io
Vo
Vo
Figure 12. Load Transient in 36-V Buck Region—With
20-A to 40-A Load Step
Figure 13. Load Transient in 36-V Buck Region—With
0-A to 40-A Load Step
Io
Io
Vo
Vo
Figure 14. Load Transient in 12-V Buck-Boost
Region—With 20-A to 40-A Load Step
10
Figure 15. Load Transient in 12-V Buck-Boost
Region—With 0-A to 40-A Load Step
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Io
Io
Vo
Vo
Figure 16. Load Transient in 9-V Boost Region—With
20-A to 40-A Load Step
Figure 17. Load Transient in 9-V Boost Region—With
0-A to 40-A Load Step
Figure 18 through Figure 23 show the output ripple waveforms in the 36-V buck, 12-V buck-boost, and 9-V
boost region, respectively.
Vo
Vo
Figure 18. Output Voltage Ripple in 36-V Buck
Region—No Load
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Figure 19. Output Voltage Ripple in 36-V Buck
Region—40-A Load
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Vo
Vo
Figure 20. Output Voltage Ripple in 12-V Buck-Boost
Region—No Load
Figure 21. Output Voltage Ripple in 12-V Buck-Boost
Region—40-A Load
Vo
Vo
Figure 22. Output Voltage Ripple in 9-V Boost
Region—No Load
12
Figure 23. Output Voltage Ripple in 9-V Boost
Region—40-A Load
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Figure 24 through Figure 29 show the start-up waveforms in the 36-V buck, 12-V buck-boost, and 9-V
boost regions, respectively. The loads are not equally distributed during a certain period of the startprocess due to a sequential order during start-up and the necessary time for a current sharing-circuit to
build up and get ready.
Vin
Vin
Vo
Vo
Io
IL1
IL2
Figure 24. 40-A Start-Up in 36-V Buck Region—Total
Output Current Waveform
Figure 25. 40-A Start-Up in 36-V Buck Region—Two
Phase Inductor Currents
Vin
Vin
Vo
Vo
Io
IL1
IL2
Figure 26. 40-A Start-Up in 12-V Buck-Boost
Region—Total Output Current Waveform
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Figure 27. 40-A Start-Up in 12-V Buck-Boost
Region—Two Phase Inductor Currents
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Vin
Vin
Vo
Vo
Io
IL1
IL2
Figure 28. 40-A Start-Up in 9-V Boost Region—Total
Output Current Waveform
Figure 29. 40-A Start-Up in 9-V Boost Region—Two
Phase Inductor Currents
Figure 30 through Figure 35 show the current limit behavior of both hiccup enabled and no hiccup in the
36-V buck, 12-V buck-boost, and 9-V boost regions, respectively. The 36-V buck does not have a nohiccup mode, even when it has been enabled, because the average current limit is triggered before the
hiccup can occur.
Vin
Vin
Vo
Vo
IL1
IL1
IL2
IL2
Figure 30. Current Limit Behavior in 36-V Buck
Region—Hiccup Enabled
14
Figure 31. Current Limit Behavior in 36-V Buck
Region—No Hiccup
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Vin
Vin
Vo
Vo
IL1
IL1
IL2
IL2
Figure 32. Current Limit Behavior in 12-V Buck-Boost
Region—Hiccup Enabled
Figure 33. Current Limit Behavior in 12-V Buck-Boost
Region—No Hiccup
Vin
Vin
Vo
Vo
IL1
IL2
IL1
IL2
Figure 34. Current Limit Behavior in 9-V Boost
Region—Hiccup Enabled
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Figure 35. Current Limit Behavior in 9-V Boost
Region—No Hiccup
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Due to the parallel structure of two LM5176 converters, the heat sources are also distributed. With a
600-CFM airflow, Figure 36 through Figure 38 show the 40-A load thermal condition in the 36-V buck, 12V buck-boost, and 9-V boost regions, respectively.
Figure 36. 40-A Load Thermal Condition in 36-V Buck
Region
Figure 37. 40-A Load Thermal Condition in 12-V
Buck-Boost Region
Figure 38. 40-A Load Thermal Condition in 9-V Boost Region
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3.3
Interleaved Operation
As previously mentioned, the user can configure two LM5176 converters as 180° out-of-phase, otherwise
known as an interleaved architecture. Interleaved architecture provides a better solution for smaller output
voltage ripple.
To underscore the discrimination with in-phase operation, Figure 39 through Figure 44 show the four SW
nodes and inductor current waveforms in the 36-V buck, 12-V buck-boost, and 9-V boost regions,
respectively.
SW1 (#1)
IL1
SW2 (#1)
IL2
SW1 (#2)
SW1 (#1)
SW2 (#2)
Figure 39. 36-V Buck Region With 40-A Load—Four
Switch Nodes
SW2 (#1)
Figure 40. 36-V Buck Region With 40-A Load—Inductor
Current Waveforms
IL1
SW1 (#1)
IL2
SW2 (#1)
SW1 (#2)
SW1 (#1)
SW2 (#1)
SW2 (#2)
Figure 41. 12-V Buck-Boost Region With 40-A
Load—Four Switch Nodes
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Figure 42. 12-V Buck-Boost Region With 40-A
Load—Inductor Current Waveforms
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IL1
SW1 (#1)
IL2
SW1 (#1)
SW2 (#1)
SW1 (#2)
SW2 (#1)
SW2 (#2)
Figure 43. 9-V Boost Region With 40-A Load—Four
Switch Nodes
Figure 44. 9-V Boost Region With 40-A Load—Inductor
Current Waveforms
Figure 45 through Figure 50 show the output ripple in the 36-V buck, 12-V buck-boost, and 9-V boost
regions, respectively. In comparison to Figure 14 through Figure 16, the amplitude of the output voltage
ripple is reduced while the frequency is doubled.
Vo
Vo
Figure 45. Output Voltage Ripple in 36-V Buck
Region—No Load
18
Figure 46. Output Voltage Ripple in 36-V Buck
Region—40-A Load
Two Parallel, Synchronous, Four-Switch Buck-Boost Converters With Master
Slave Method for Higher Power
Copyright © 2017, Texas Instruments Incorporated
SNVA792 – September 2017
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Test Results
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Vo
Vo
Figure 47. Output Voltage Ripple in 12-V Buck-Boost
Region—No Load
Figure 48. Output Voltage Ripple in 12-V Buck-Boost
Region—40-A Load
Vo
Vo
Figure 49. Output Voltage Ripple in 9-V Boost
Region—No Load
SNVA792 – September 2017
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Figure 50. Output Voltage Ripple in 9-V Boost
Region—40-A Load
Two Parallel, Synchronous, Four-Switch Buck-Boost Converters With Master
Slave Method for Higher Power
Copyright © 2017, Texas Instruments Incorporated
19
Conclusion
4
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Conclusion
Unequal load distribution is the fundamental difficulty of parallel power supplies. This application report
details a dedicated master-slave-based current-sharing architecture. With an elaborate external circuit of
only a few components, the slave can accurately follow the master to deliver the same amount of load
current and with an error that is within ±1.2%. This report also shares the experiment results for parallel
LM5176 converters with a 480-W capability, which provide an attractive solution for high-power
applications.
5
Related Documentation
1. Balogh, Laszlo; Paralleling Power – Choosing and Applying the Best Technique for Load Sharing,
(2003)
2. Texas Instruments, Two Parallel, Synchronous, Four-Switch Buck-Boost Converters With Droop
Method for Higher Power, Application Report (SNVA794)
20
Two Parallel, Synchronous, Four-Switch Buck-Boost Converters With Master
Slave Method for Higher Power
Copyright © 2017, Texas Instruments Incorporated
SNVA792 – September 2017
Submit Documentation Feedback
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