Texas Instruments | bq77905 20S Cell Stacking Configuration (Rev. A) | Application notes | Texas Instruments bq77905 20S Cell Stacking Configuration (Rev. A) Application notes

Texas Instruments bq77905 20S Cell Stacking Configuration (Rev. A) Application notes
Application Report
SLUA774A – July 2016 – Revised July 2017
bq77905 20S Cell Stacking Configuration
Taylor Vogt ........................................................................................... BMS: Monitoring and Protection
ABSTRACT
The bq77905 is a 3–5S Low Power Protector with easy stacking capabilities for higher than 5S cell battery
packs. This document provides an example for setting up a stacking configuration with the bq77905 and
exhibits detailed analysis of the stacking functionality.
1
2
3
4
5
Contents
Configuration ................................................................................................................. 1
Functionality .................................................................................................................. 2
Load Current ................................................................................................................. 5
Troubleshooting FAQ ...................................................................................................... 10
References .................................................................................................................. 11
List of Figures
1
Block Diagram................................................................................................................ 2
2
UV Detection ................................................................................................................. 3
3
UV Recovery ................................................................................................................. 3
4
OV Detection ................................................................................................................. 4
5
OV Recovery ................................................................................................................. 4
6
Loading for Stacked Devices
7
Example CTRx pin Characteristic ......................................................................................... 6
8
Load Matching Resistors
9
FET Drive Voltage With Cell Variation
10
11
..............................................................................................
5
................................................................................................... 7
................................................................................... 9
Measurement Loading Example on CTRC ............................................................................. 11
Schematic ................................................................................................................... 12
Trademarks
All trademarks are the property of their respective owners.
1
Configuration
The following stacking configuration represents a battery pack protection system for a 20S cell pack.
Therefore, the setup requires four stacked bq77905 devices supporting 5 cells each. Each device is
numbered and labeled as a device under test (DUT) in the high-level block diagram illustrated in Figure 1.
NOTE: For other configurations where one or more devices on the stack supports a lower cell count
(for example, 3 or 4) than the rest of the stacked devices, TI recommends using the uppermost device on the stack to support the highest cell count. For example, if the user wants to
protect a 9S cell pack, DUT#2 shown in Figure 1 supports 5 cells while DUT#1 would
support 4 cells. In that case, DUT#2 supports more cells because it is the higher and uppermost device on the stack. Furthermore, If the user wants to protect a 17S cell pack, DUT#4
would support 5 cells while DUT#1–3 would support 4. When possible, configure each DUT
to support the same number of cells.
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1
Configuration
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CTRC
VC20
To
VC16
bq77905
DUT#4
CTRD
DSG
CHGU
RCTRC
RCTRD
CTRC
Cell20:Cell16
VC15
To
VC11
bq77905
DUT#3
CTRD
DSG
CHGU
Cell15:Cell11
RCTRC RCTRD
Cell Simulator
CTRC
Cell10:Cell6
Cell5:Cell1
VC10
To
VC6
bq77905
DUT#2
CTRD
DSG
CHGU
RCTRC RCTRD
CTRC
VC5
To
VC1
bq77905
DUT#1
CTRD
CHGU
DSG
CHG
TO DSG
TO FET
CHG
FET
Copyright © 2016, Texas Instruments Incorporated
Figure 1. Block Diagram
1.1
General Setup Instructions
The following instructions are useful when constructing any stacking configuration with the bq77905. The
instructions refer to DUTs #1–4 shown in Figure 1 representing the devices labeled U1–U4, respectively,
in the detailed schematic in Figure 11. Many of the steps refer to pin connections that can best be
understood by observing the schematic. Further information on the setup of Stacking Implementations can
be found on the bq77904 / bq77905: 3-5S Low Power Protector data sheet (SLUSCM3).
1. For the bottom device (DUT#1 or U1), use the CHG pin to drive the CHG FET, and leave the CHGU
pin unconnected.
2. For the upper devices (all except DUT#1 or U1), connect the CHGU pin to the CTRC pin of the
immediately lower device with a RCTRC and leave the CHG pin unconnected.
3. Connect the DSG pins of the upper devices with a RCTRD to the CTRD pin of the immediate lower
devices.
4. Ensure that the SRP and SRN pins of the upper devices are connected to its corresponding AVSS pin.
Each device should have its own separate plane for referencing the AVSS/DVSS pin or any other pins.
5. Ensure that the CCFG pin for each device is connected appropriately (5 cells = floating, 4 cells =
AVDD, 3 cells = AVSS)
6. Ground the CTRC and CTRD pins of the upper-most device (in this case DUT#4 or U4) to its
corresponding reference plane.
7. If load removal is not used for UV recovery, connect the LD pin of the upper devices to its
corresponding reference plane. Otherwise, refer to the data sheet link (SLUSCM3).
2
Functionality
The following sections describe a fault detected by a DUT and displays the results in several images.
Each device in the stack is functional in protecting OV, UV, OTC, OTD, UTC, and UTD faults, but the
following results display protection of cell 17 on the upper-most device (DUT#4). This is so the data can
focus on FET switching time in response to a fault on the top of the stack. Typically this was recorded
within a few ms of the response time of faults on the bottom device, so the bq77905 functions efficiently
across a stack.
2
bq77905 20S Cell Stacking Configuration
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Functionality
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2.1
Undervoltage (UV)
The UV fault test focuses on the DSG turn-off time as cell 17 is monitored below the desired threshold. In
Figure 2, it is clear that DSG will fall and stay low while any cell has a UV fault detected. When examining
the delay of DSG rise/fall by measuring the delta between the UV fault threshold (red arrows in Figure 2
and Figure 3) and DSG rise/fall, both figures display a similar response time of close to 1s due to the large
RGS. This is expected for the bq77905 and will need to be accounted for appropriately in any system.
Figure 2. UV Detection
Figure 3. UV Recovery
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Functionality
2.2
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Overvoltage (OV)
The OV fault test is almost identical to the UV fault test, but instead focuses on the CHG turn-off time as a
cell is monitored above the desired threshold. As shown in Figure 4, the CHG pin falls due to the OV fault
(threshold designated by red arrows in Figure 4 and Figure 5) after a delay of approximately 400–600 ms.
Figure 4. OV Detection
Figure 5. OV Recovery
4
bq77905 20S Cell Stacking Configuration
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Load Current
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3
Load Current
In the data sheet stacking schematics and Figure 11, the bottom device has the load of the FET gatesource resistors while the upper devices have only the load from the RCTRD and RCTRC resistors. Since the
load is needed for the FETs, add load to the upper devices to more closely match the load between the
devices. Adding the load on the CHG or CHGU and DSG output allows the load to match the mode of the
battery rather than simply adding a load to the cells. Figure 6 shows currents into the FETs and stacking
interface pins.
UPPER
RVDD2
VDD
bq77905
RCD
RCC
Group2
CTRD
CTRC
AVSS
CHGU
DVSS
DSG
LOWER
RVDD1
VDD
ICTRD
bq77905
RCD
CTRD
RCC
CTRC
RCTRD
ICTRC
RCTRC
Group1
AVSS
CHG
ICHG1
DVSS
DSG
RCHG
IDSG1
RDSG
RSNS
Rlim
RDGS
D2
RCGS
D1
PACK-
Copyright © 201 7, Texas Instrumen ts Incorpor ate d
Figure 6. Loading for Stacked Devices
Since the RDSG and RCHG are small with respect to the gate resistors, these can usually be neglected when
estimating current and are omitted from the following equations. The currents for the DSG and CHG FET
drive:
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Load Current
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(1)
(2)
The CTRC and CTRD pins have an internal resistance which will limit the current into the clamp at the
maximum pin voltage. The clamp voltage is shown at a specific test current in the data sheet, VCTR(MAXV).
The internal resistance RCD = RCC or RCx has a nominal value of 440 kΩ but may vary significantly and is
not a characterized value in the data sheet. The CTRC and CTRD characteristic for an example device is
shown in Figure 7.
18
CTRD
CTRC
16
14
Input current (µA)
12
10
8
6
4
2
0
0
2
4
6
8
CTRx - VDD (V)
10
12
D001
Figure 7. Example CTRx pin Characteristic
At low currents the data sheet test conditions may be a good representation of the control input operating
point and the equation for the input current is:
(3)
Using typical values in the data sheet and 10 MΩ for RCTRx, ICTRx would be 800 nA, near the 600 nA data
sheet test current.
One method to match the load of the FETs would be to adjust RCTRx. However, at much higher currents it
is better to consider the internal resistance and an internal clamp value VC in an equation for ICTRx:
(4)
As RCTRx is decreased to increase the current, the current becomes more sensitive to the internal RCx
resistance variation. A designer may want to avoid using the RCTRx resistor to match the current of the FET
unless the RxGS resistance were very large.
A better method to match the FET load current on the upper device would be to add resistors from the
upper device FET outputs to the VSS reference, RDLD and RCLD as shown in Figure 8.
6
bq77905 20S Cell Stacking Configuration
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Load Current
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UPPER
RVDD2
VDD
bq77905
RCD
RCC
Group2
CTRD
CTRC
AVSS
CHGU
DVSS
DSG
RDLD
RCLD IDLD
ICLD
LOWER
RVDD1
VDD
bq77905
RCD
CTRD
RCC
CTRC
ICTRD
RCTRD
ICTRC
RCTRC
Group1
AVSS
CHG
ICHG1
DVSS
DSG
RCHG
IDSG1
RDSG
RSNS
Rlim
RDGS
D2
RCGS
D1
PACK-
Copyright © 201 7, Texas Instrumen ts Incorpor ate d
Figure 8. Load Matching Resistors
The currents in these load matching resistances are added to the stacking interface currents to match the
FET drive currents of the lower device:
(5)
(6)
These RxLD load resistances receive the full V(FETON) voltage and are unaffected by the clamp voltage for a
predictable load current.
(7)
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Load Current
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Since ICTRx provides some load, RDLD and RCLD will be larger than the RxGS resistance of the lower device.
The designer would solve for the equations and select a suitable load resistance from available values.
Example calculations in Table 1 and Table 2 show that load matching resistors can improve the capacity
mismatch caused by the FET load.
Table 1. Example DSG Load Calculations
Parameter
Source
V(FETON)
Data sheet
Value
12 V
RDGS
Figure 11 R47
1 MΩ
IDSG1
Equation 1
12 µA
VCTR(MAXV)
Data sheet
RCTRD
Figure 11 R32
ICTRD
Equation 3
0.8 µA
IDLD desired
Equation 5
11.2 µA
4V
10 MΩ
Capacity difference without matching load Load mismatch current × 24 hours per day × 365 days per
year
RDLD desired
Equation 7
RDLD selected
Standard 5% value
Nominal current error
12 × (1 / 1.07 – 1 / 1.1)
Capacity difference with 5% matching
load resistor value
Load mismatch current × 24 hours per day × 365 days per
year
98 mAH per year
1.07 MΩ
1.1 MΩ
0.305 µA
2.68 mAH per year
Table 2. Example CHG Load Calculations
Parameter
Source
Value
V(FETON)
Data sheet
12 V
VD2
Estimate from data sheet
0.4 V
RCGS
Figure 11 R48
3.3 MΩ
ICHG1
Equation 2
3.52 µA
VCTR(MAXV)
Data sheet
RCTRC
Figure 11 R33
10 MΩ
ICTRC
Equation 3
0.8 µA
ICLD desired
Equation 6
2.72 µA
Capacity difference without matching load Load mismatch current × 24 hours per day × 365 days
per year
24 mAH per year
4V
RCLD desired
Equation 7
RCLD selected
Standard 5% value
4.41 MΩ
Nominal current error
12 × (1 / 4.41 – 1 / 4.3)
Capacity difference with 5% matching
load resistor value
Load mismatch current × 24 hours per day × 365 days
per year
4.3 MΩ
–70.7 nA
–0.62 mAH per year
The previous calculations assume the V(FETON) voltage is in regulation as would be the case with 5 cell
stacks and high voltage cells. With lower cell counts and voltages, the FET drive voltage will drop out of
regulation as shown in Figure 9. When each device supports the same number of cells, the voltages
should match and not be a concern. When the devices have different numbers of cells, use the V(FETON)
from the normal system condition in calculations to equalize currents.
8
bq77905 20S Cell Stacking Configuration
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Load Current
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13
VFETON typical (V)
11
9
3 cells
4 cells
5 cells
7
5
2
2.25
2.5
2.75
3 3.25 3.5
Cell voltage (V)
3.75
4
4.25
4.5
D002
Figure 9. FET Drive Voltage With Cell Variation
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Troubleshooting FAQ
4
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Troubleshooting FAQ
Q: What is the limit to how many devices you can stack?
A: The bq77905 has no technical limitation on the number of devices in a stack. However, keep in mind
that the larger the stack becomes, the greater the noise impact on the CTRC/D signal strength and the
greater the total delay time from the top to bottom of the stack. This delay time is not an increase in the
individual DUT protections, but it is a minimal increase due to logic propagation across each device in the
stack. Typically, this is only 1–10 ms per device added to the stack, so it must be decided if this is a small
enough margin for the application.
Q: What will happen if I make a lower device support more cells than an upper device (for example,
if you made DUT#1 support 5 cells and DUT#4 support 3 cells)?
A: The system should function appropriately, but this is not recommended as doing so could impact
CTRC/D signal strength across the stack. However, the tradeoff would be lower gate voltage on the FETs,
so determine if one option is better than the other.
Q: What changes need to be made for a DUT to support only 3 or 4 cells?
A: As mentioned in Section 1.1 and in the data sheet, the CCFG pin must be configured appropriately,
and the unused cells must always be chosen as the upper-most cells and shorted to the immediate lower
cell (for example, in an 8S cell stack configuration, C4 could be shorted to C3 for 4 cells in DUT#1).
Q: How do I implement Load Detect for UV Fault Recovery on upper devices?
A: As shown in Figure 11, connect the LD pins of all devices to PACK– through a RLD (R8, R18, R28,
R44) equal to 300 kΩ and a blocking diode. Also, the RGS_CHG (R48) should be increased from the typical 1
MΩ to 3.3 MΩ. Refer to the data sheet ( SLUSCM3) for further detail and explanations.
Q: How would I decrease the CHG FET turn off time without affecting the UV Load Detect?
A: Instead of decreasing the value of the RGS_CHG (R48), it is more effective to implement a CHG FET turn
off speed circuit. Further detail is explained in Section 3 of the bq77905 Using Multiple FETs (SLUA773)
Application Note.
Q: With a small battery the cells on the bottom device have a lower voltage than the cells of an
upper device. Why is this and how can it be avoided?
A: The bottom device has a greater load than the upper device due to the FET drive load of the gatesource resistors (Figure 11) R47 and R48 being smaller than the stacking interface load on the upper
device, RCTR resistors R32 and R33 for example. See Section 3.
Q: The FETs turn on, but the voltage measured at CTRC or CTRD indicates the FETs should be off.
Why is this?
A: The CTRC and CTRD nodes have a high impedance source. When a meter is attached such as in
Figure 10 the meter becomes part of the circuit forming a voltage divider and alters the voltage at CTRx. If
the gate voltage is measured at the same time the FETs may be observed to turn off. Measuring CTRx
with respect to VDD will reduce the influence of the meter. If the meter input can be set to high
impedance, a better measurement will be obtained, but loading will still occur.
10
bq77905 20S Cell Stacking Configuration
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References
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UPPER
RVDD2
VDD
bq77905
RCD
CTRD
RCC
Group2
CTRC
AVSS
CHGU
DVSS
DSG
10 MQ
+
-
LOWER
RVDD1
VDD
bq77905
RCD
CTRD
RCC
CTRC
RCTRD
10 MQ
RCTRC
10 MQ
Group1
AVSS
CHG
DVSS
DSG
RCHG
RDSG
Rlim
RDGS
RSNS
D2
RCGS
D1
PACK-
Copyright © 201 7, Texas Instrumen ts Incorpor ate d
Figure 10. Measurement Loading Example on CTRC
5
References
For additional information, refer to the following documents available at www.ti.com:
• bq77904 / bq77905: 3-5S Low Power Protector data sheet ( SLUSCM3)
• bq77905 EVM User's Guide (SLVUAN2)
• bq77905 Using Multiple FETs (SLUA773)
• bq77905 Separate Current Paths (SLUA772)
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References
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R1
1.00k
R2
C20
C1
C2
1µF
1µF
1.00k
C3
0.1 µF
R3
C19
1.00k
C4
0.1 µF
R4
C18
VC20
U1
1.00k
C5
0.1 µF
VC19
R5
C17
1.00k
C6
0.1 µF
VC18
VC17
VC16
R7
C16
1.00k
C7
0.1 µF
1
2
3
4
5
6
7
8
9
10
VDD
AVDD
VC5
VC4
VC3
VC2
VC1
AVSS
SRP
SRN
DVSS
CTRD
CTRC
CCFG
VTB
TS
LD
CHG
CHGU
DSG
20
19
18
17
16
15
14
13
12
11
R6
RT1
10.0k
D1
R8
t°
450k
10.0k ohm
1N4148W-7-F
BQ77905
R9
U4_VSS
1.00k
R10
C15
C8
C9
1µF
1µF
1.00k
C10
0.1 µF
R11
C14
1.00k
C11
0.1 µF
R14
C13
R12
10M
VC15
C12
0.1 µF
VC14
R15
C12
1.00k
C13
0.1 µF
VC13
VC12
VC11
R17
C11
R13
10M
U2
1.00k
1.00k
C14
0.1 µF
1
2
3
4
5
6
7
8
9
10
VDD
AVDD
VC5
VC4
VC3
VC2
VC1
AVSS
SRP
SRN
DVSS
CTRD
CTRC
CCFG
VTB
TS
LD
CHG
CHGU
DSG
20
19
18
17
16
15
14
13
12
11
R16
RT2
10.0k
D2
R18
t°
450k
10.0k ohm
1N4148W-7-F
BQ77905
R19
U3_VSS
1.00k
R20
C10
C15
C16
1µF
1µF
1.00k
C17
0.1 µF
R21
C9
1.00k
C18
0.1 µF
R24
C8
R22
10M
VC10
C19
0.1 µF
VC9
R25
C7
1.00k
C20
0.1 µF
VC8
VC7
VC6
R27
C6
R23
10M
U3
1.00k
1.00k
C21
0.1 µF
1
2
3
4
5
6
7
8
9
10
VDD
AVDD
VC5
VC4
VC3
VC2
VC1
AVSS
SRP
SRN
DVSS
CTRD
CTRC
CCFG
VTB
TS
LD
CHG
CHGU
DSG
20
19
18
17
16
15
14
13
12
11
R26
10.0k
RT3
D3
R28
t°
450k
10.0k ohm
1N4148W-7-F
BQ77905
R29
U2_VSS
1.00k
R30
C5
C22
C23
1µF
1µF
1.00k
C24
0.1 µF
R31
C4
1.00k
C25
0.1 µF
R32
10M
VC5
R34
C3
U4
C26
0.1 µF
R35
C2
1.00k
C27
0.1 µF
VC3
VC2
VC1
R37
C1
R33
10M
VC4
1.00k
1.00k
C28
0.1 µF
1
2
3
4
5
6
7
8
9
10
VDD
AVDD
VC5
VC4
VC3
VC2
VC1
AVSS
SRP
SRN
DVSS
CTRD
CTRC
CCFG
VTB
TS
LD
CHG
CHGU
DSG
20
19
18
17
16
15
14
13
12
11
R36
RT4
10.0k
t°
10.0k ohm
GND
BQ77905
1
GND
R38
0
GND
3
2
R39
0
Q1
SI2325DS-T1-E3
R40
1.00k
C30
0.1 µF
0.1 µF
R42
3.0
GND
R43
3.0
R44
450k
1
R46
100
R47
1.0M
J1
R49
1
D4
1N4148W-7-F
0.1 µF
GND
R45
100
R41
1M
C31
1
C29
D5
1N4148W-7-F
DSG FET
3
CHG FET
2
2
R48
3.3M
3
D6
MMSZ5246B-7-F
16V
J2
1
0.05
BAT-
D7
SMCJ110A
110V
3
BAT+
J3
Q2
FQP19N20C
R50
R51
3.0
3.0
1
NT1
Net-Tie
2
Q4
FQP19N20C
GND
Q3
FQP19N20C
8199
PACK-
1
8199
2
D8
SMCJ110A
110V
3
Q5
FQP19N20C
1
PACK+
J4
1
8199
8199
Copyright © 2016, Texas Instruments Incorporated
Figure 11. Schematic
12
bq77905 20S Cell Stacking Configuration
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Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Original (July 2016) to A Revision ........................................................................................................... Page
•
•
•
Added Load Current section. ............................................................................................................ 5
Added FAQ about lower voltage in the lower device. ............................................................................... 10
Added FAQ on CTRx measurement with image. .................................................................................... 10
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