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Texas Instruments Power and Dimming LED with TPS54200 and TPS54201 Application notes
Application Report
SLVA881 – April 2017
Power and Dimming LED With TPS54200 and TPS54201
Mike Wang
ABSTRACT
The TPS54200 and TPS54201 (TPS5420X) devices are 28-V wide input range, 1.5-A maximum output
current, synchronous buck LED drivers supporting deep dimming ratio with high dimming accuracy. The
TPS5420X supports both analog and PWM dimming mode. Especially, in analog dimming mode, a 1%
dimming ratio is easily attained by inputting a PWM signal with 1% duty cycle. This is a welcomed feature
in surveillance applications. In some other applications where LED color shift is not allowed, PWM
dimming mode may be used. To use this part flexibly, the dimming mechanism implemented inside the
TPS5420X is explained in detail, and various dimming methods in applications are discussed as well in
this report.
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Contents
Typical Application .......................................................................................................... 2
TPS5420X Dimming Mechanism .......................................................................................... 3
Dimming Method in Application ............................................................................................ 9
Test Results ................................................................................................................. 13
References .................................................................................................................. 17
List of Figures
1
Typical LED Driver Circuit With TPS5420X .............................................................................. 2
2
Dimming Mode Detection Circuit
3
Peak Detector Block Diagram .............................................................................................. 3
4
Normal Power On Timing Sequence ...................................................................................... 4
5
Very Slow PWM Rising Speed May Prevent Device From Entering Analog Dimming Mode
6
Very Slow VIN Rising Speed May Prevent Device From Entering Analog Dimming Mode ......................... 6
7
VLDO vs VIN ..................................................................................................................... 7
8
Internal Voltage Reference Generation Circuit
9
10
11
12
13
14
15
16
17
18
19
..........................................................................................
.....................
3
5
.......................................................................... 7
Internal Voltage Reference VREF vs PWM Duty Cycle................................................................... 7
PWM Dimming Operation .................................................................................................. 8
PDIM Operation With Higher Than 2-V Amplitude PWM Signal ...................................................... 9
ADIM Operation by Applying DC Bias at the FB Pin .................................................................. 10
Application Without Dimming ............................................................................................. 11
LED Current vs PWM Duty in ADIM Mode ............................................................................. 13
Deep Dimming in ADIM Mode ............................................................................................ 13
LED Current vs VDIM Voltage .............................................................................................. 14
PWM Dimming With 2% Duty, 250 kHz ................................................................................. 15
PWM Dimming With 50% Duty, 250 kHz ............................................................................... 16
PWM Dimming With 99% Duty, 250 kHz ............................................................................... 17
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Typical Application
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List of Tables
1
Mode Detection Condition .................................................................................................. 4
2
Suggested Resistor Divider for Some Common Logic Level PWM Inputs ........................................... 9
3
Design Parameters for the Example of Analog Dimming at the FB Pin
4
Suggested Resistor Divider for Some Commonly Used Input Rail .................................................. 12
5
Dimming Method Summary ............................................................................................... 12
............................................
10
Trademarks
All trademarks are the property of their respective owners.
1
Typical Application
The TPS5420X family is a 4.5- to 28-V input voltage, 1.5-A output current, synchronous buck LED driver.
With SOT23-6 small package, the device offers a compact, efficient, and cost-effective solution in many
kinds of LED lighting markets, such as video surveillance cameras, industrial and commercial illumination,
architecture lighting, and so forth.
The TPS5420X supports both PWM dimming mode and analog dimming mode. Especially, in analog
dimming mode, the TPS5420X can achieve extreme wide dimming range from 100% to 0.1%, provide a
super-smooth transition from LED on to LED off status. Since the LED current amplitude is directly
controlled by PWM duty, the device achieves a very accurate LED current control even under low dimming
ratio. This is welcomed in surveillance camera applications.
Complete protection features in the TPS5420X guarantee a safe operation of the LED circuit. Besides the
cycle-by-cycle current limit implemented for the built-in high-side and low-side power FET, LED open and
short, sense resistor open and short protection are also implemented. To maximize the system flexibility,
TPS54200 and TPS54201 adopts different protection modes. The TPS54200 uses shutdown-and-latch
protection mode, while the TPS54201 adopts hiccup mode protection.
LO
CBOOT
1
GND
2
SW
PWM 5
3
VIN
FB 4
CO
BOOT 6
PWM Input
RF
VIN
CIN
CF
RSENSE
Figure 1. Typical LED Driver Circuit With TPS5420X
External component selection includes the determination of LO, CO, CIN, RSENSE, RF and CF.
The allowed voltage ripple at the input rail will determine the input capacitance needed. The output
capacitance CO will affect the ripple current through the LED string. The selection of output inductance, LO,
is a tradeoff between LED ripple current, efficiency, cost, and solution size. Current sense resistor RSENSE
is sized for a target LED current. The RC filter at the FB pin, RF and CF, generates a pole to cancel the
internal zero for loop stability consideration. Detail design procedures for these components is found in the
TPS5420X data sheet (SLUSCO8).
2
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2
TPS5420X Dimming Mechanism
The TPS5420X has two dimming modes, its behavior is different in these two dimming modes. The
magnitude of the PWM signal is used to determine which dimming mode the device will enter at power on.
Once the dimming mode is detected and locked, it will not change unless VIN or PWM is recycled.
2.1
2.1.1
Dimming Mode Detection
Normal Mode Detection Process
The internal dimming mode detection circuit is shown in Figure 2.
PWM
+
EN
±
Vth
VIN
LDO
VLDO
PWM
VPD
Peak
Detector
+
VADIM
+
VPDIM
+
VPWM
A
±
B
±
Internal
PWM
±
Figure 2. Dimming Mode Detection Circuit
The output of the peak detector at the PWM pin, VPD, will hold the magnitude of the PWM signal as long
as it is less than the upper limit of peak detector output voltage which is around VLDO – 1 V (worst case);
otherwise, VPD will be clamped at VLDO – 1 V, see Figure 7 for the relationship between VIN and VLDO. VLDO
is the power supply of the peak detector, it limits the maximum output voltage of the peak detector at
VLDO – 1 V. Here, 1 V is the minimum voltage drop between VLDO and VPD. See Figure 3 for the block
diagram of the peak detector.
VLDO
PWM
+
VPD
±
Figure 3. Peak Detector Block Diagram
Once the device is enabled, and after a 300-μs delay, the output of the peak detector will be compared
with two voltage thresholds VADIM and VPDIM, which is typically 1 V and 2.07 V, respectively. See the
TPS5420X data sheet (SLUSCO8) for the variation of these two parameters. If the output of the peak
detector is higher than 2.07 V, analog dimming mode will be chosen and locked. If it is between 1 V and
2.07 V, PWM dimming mode will be chosen and locked. If it is less than 1 V, the device will wait another
300-μs and compare again, and this process will repeat until at least one mode is chosen and locked.
Refer to Table 1 for the dimming mode detection condition summary.
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Table 1. Mode Detection Condition
A
B
Mode
H
H
Enter Analog dimming mode
L
H
Enter PWM dimming mode
L
L
Keep detecting until one dimming mode is locked
To detect and lock dimming mode correctly, proper timing sequence at power on is required. TI suggests
applying VIN at first, followed by the PWM signal, see Figure 4 for a normal power on timing sequence.
4.5 V
VIN
Vth (~0.56 V)
PWM
H
EN
(Internal)
L
300 µs
The Upper Limit for VPD is VLDO í 1 V. As Long as VPD is Less
Than This Limit, it Will Follow the Peak Envelope of the PWM
Signal.
VPDIM (~1 V)
VPD
(Internal)
Mode Detected and Locked at This Moment,
SST Begins Ramp Up.
SST
(Internal)
Figure 4. Normal Power On Timing Sequence
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2.1.2
Potential Wrong Mode Detection
There are two extreme conditions in which the TPS5420X may fail to enter analog dimming mode
correctly. One of these two conditions is that PWM rising speed very slow, for example, less than 5 V /
ms. Another condition is that VIN is applied after the PWM signal, and VIN has a very slow rising slew rate.
Be careful not to run into these two conditions if analog dimming mode is needed. Refer to Figure 5 and
Figure 6 for the timing diagram of these two cases.
In Figure 5, VIN is applied at first, then PWM is applied. PWM has a 3.3-V amplitude, the device should
enter analog dimming mode as expected. However, since PWM rising edge is very slow, it is possible to
detect dimming mode before VPD reaches the VADIM threshold (2 V), and thus may cause the device to
enter PWM dimming mode falsely.
4.5 V
VIN
3.3 V
PWM
Vth (~0.56 V)
H
EN
(Internal)
The Upper Limit for VPD is VLDO í 1 V. As
Long as VPD is Less Than This Limit, it Will
Follow the Peak Envelope of the PWM Signal.
L
300 µs
300 µs
3.3 V
VADIM (~2 V)
VPD
(Internal)
SST
(Internal)
VPDIM (~1 V)
PWM Dimming Mode
Detected and Locked at
This Moment, SST
Begins to Ramp Up.
~0.56 V
At This Moment, VPD < VPDIM, None
of the Two Dimming Modes can be
Entered, the Device Will Wait
Another 300 µs and Detect Again.
Figure 5. Very Slow PWM Rising Speed May Prevent Device From Entering Analog Dimming Mode
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In Figure 6, the PWM signal is applied at first, then VIN is ramped up slowly. Normally the device will be
activated when VIN approaches 4.2 V, while in the worst case, the device may be enabled when VIN
approaches 3.9 V. Once the device is enabled, the internal LDO output VLDO is approximately 2.5 V due to
the minimum voltage drop of LDO. After that, VLDO will ramp up toward 6.5-V steady state all the way as
VIN ramps up. Figure 7 shows the relationship between VIN and VLDO.
In this example, the external PWM signal is 5-V amplitude. However, due to the minimum voltage drop
between VLDO and VPD, VPD will be only approximately 1.5 V at the moment the device is enabled. After
that, VPD will ramp up slowly as VIN and VLDO ramp up. Since VIN ramps up slowly, in turn VPD will also ramp
up slowly. It is possible to detect and lock the dimming mode before VPD reaches the VADIM threshold (2 V),
and thus may cause the device to enter PWM dimming mode falsely.
12 V
~7.9 V
VIN
Worst Case 3.9 V
5V
PWM
H
EN
(Internal)
L
6.5 V
6V
VLDO
(Internal)
2.5 V
300 µs
5V
VPD
(Internal)
2V
1.5 V
VPD < VADIM, Device Enters PWM Dimming
Mode Falsely at This Moment. This is Due
to VIN Slowly Rising.
SST
(Internal)
Figure 6. Very Slow VIN Rising Speed May Prevent Device From Entering Analog Dimming Mode
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Figure 7 shows the relationship between VIN and VLDO. When VIN < 7.9 V, VLDO is around 1.4 V lower than
VIN. When VIN > 7.9 V, VLDO will be fixed at approximately 6.5 V.
7
6.5
VLDO (V)
6
5.5
5
4.5
4
3.5
3
4.5
5.5
6.5
7.5
8.5
Vin (V)
9.5
10.5
11.5
Figure 7. VLDO vs VIN
2.2
Analog Dimming Mode Operation
Once analog dimming mode is entered , the duty cycle of the PWM input signal will be used to generate
the internal voltage reference for the FB pin. Figure 8 shows this process. The PWM pin signal is fed to a
comparator with 400-mV hysteresis, then an internal PWM signal is generated. To make sure the PWM
pin signal is correctly identified, the high level of PWM signal should be higher than 1 V, and the low level
should be lower than 0.6 V. Figure 10 shows the relationship between the external PWM and internal
PWM signal. The amplitude of the internal PWM signal is fixed at 200 mV. This internal PWM signal will
be fed to an RC filter to generate the internal voltage reference, which has an average voltage
proportional to the PWM duty cycle as shown in Figure 9. LED current is sensed and compared with this
internal voltage reference. The LED current is continuous in this mode, and the current magnitude can be
adjusted by changing the PWM duty cycle.
3.3 V
200 mV
0V
0V
200 mV
PWM
VPWM
+
Internal Reference for FB pin
±
Figure 8. Internal Voltage Reference Generation Circuit
VREF (mV)
200
PWM Duty (%)
100
Figure 9. Internal Voltage Reference VREF vs PWM Duty Cycle
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Since the internal voltage reference is generated by the RC filter, a PWM frequency that is too low may
cause a bigger ripple at voltage reference. To minimize this ripple, TI recommends making the PWM
signal frequency 10 kHz, or higher. 50 kHz is suggested as a typical value.
Notice that the PWM signal amplitude is not required to be larger than 2 V once the analog dimming mode
is locked. In other words, the PWM signal amplitude can be 1.5 V, for example, after the dimming mode is
locked.
2.3
PWM Dimming Mode Operation
In PWM dimming mode, the internal voltage reference for the FB pin will be fixed at 100 mV, LED current
will be on or off, corresponding to the internal PWM signal duty cycle, see Figure 10. Due to the limited
control loop response, to get a relatively linear dimming performance, the suggested PWM signal
frequency should be less than 1 kHz.
Notice that the PWM signal amplitude is not required to be lower than 2 V once the PWM dimming mode
is locked. In other words, the PWM signal amplitude can be 3.3 V, for example, after the dimming mode is
locked.
1V
PWM Pin Signal
0.6 V
Internal PWM
100 mV / RSENSE
LED Current
0
Figure 10. PWM Dimming Operation
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Dimming Method in Application
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3
Dimming Method in Application
3.1
PWM Dimming Mode Application
3.1.1
PWM Signal With Amplitude Higher Than 2 V
As described in Dimming Mode Detection, to enter the PWM dimming mode, the PWM signal amplitude
should be between 1 V and 2 V. Typically 1.5 V is chosen for the best variation tolerance. If the PWM
input signal has an amplitude higher than 2 V, a resistor divider must be added to scale down the PWM
amplitude at the PWM pin. Figure 11 shows a typical application circuit for this case.
LO
CBOOT
1
GND
BOOT
6
CO
2
3
VIN
SW
PWM
VIN
FB
5
RF
4
CIN
CF
RSENSE
PWM
RTOP
RBOT
Figure 11. PDIM Operation With Higher Than 2-V Amplitude PWM Signal
TI suggests using less than 100 kΩ for the bottom resistor of the divider, RBOT. Once the value of RBOT, is
chosen, Equation 1 can be used to estimate the value of RTOP.
æV
ö
RTOP = R BOT ´ ç PWM - 1÷
1.5
è
ø
where
•
VPWM is the amplitude of PWM input signal
(1)
Table 2 shows the suggested resistor divider for some commonly used logic level PWM inputs.
Table 2. Suggested Resistor Divider for Some
Common Logic Level PWM Inputs
3.1.2
PWM Amplitude
RTOP
RBOT
5V
24 kΩ
10 kΩ
3.3 V
12 kΩ
10 kΩ
2.5 V
6.8 kΩ
10 kΩ
PWM Signal With Amplitude Lower Than 2 V
When the amplitude of the PWM signal is between 1 V and 2 V, this PWM signal can be fed to the PWM
pin directly as Figure 1 shows. The device will work in PDIM mode.
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Dimming Method in Application
3.2
3.2.1
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Analog Dimming Mode Application
Analog Dimming on PWM Pin
To enter analog dimming mode, the PWM signal amplitude should be higher than 2.07 V (typical). Most of
the commonly used logic levels meet this requirement, such as 5 V, 3.3 V, and 2.5 V. As long as this
requirement is met, the PWM signal can be fed to the PWM pin directly to perform analog dimming. See
Figure 1 for the typical application circuit.
To make sure the device enters analog dimming mode correctly, at power on, ensure VIN is applied before
the PWM input. Also pay attention to the rising slew rate of the PWM signal, which should be higher than
5 V / ms.
Implementing analog dimming by applying the PWM signal to the PWM pin is the preferred method. This
gives the end user an excellent dimming linearity, even under deep dimming conditions which means the
dimming duty ratio is lower than 1%.
3.2.2
Analog Dimming on the FB Pin
If analog dimming mode is needed, but the high-frequency PWM signal is not available, keep the PWM pin
higher than 1 V and apply a variable DC voltage to the FB pin through a resistor. See Figure 12 for this
method.
LO
1
GND
BOOT
6
CBOOT
CO
2
3
VIN
SW
PWM
VIN
FB
CIN
5
RF
4
CF
RSENSE
RTOP
RDIM
RBOT
VDIM
Figure 12. ADIM Operation by Applying DC Bias at the FB Pin
The RTOP and RBOT resistor divider is sized to make the device enter PWM dimming mode. See
Section 3.3, No Dimming Application for reasons to choose PWM dimming mode, as well as how to
choose RTOP and RBOT.
Selecting RDIM and RSENSE is a combined work. Obviously, from the circuit shown in Figure 12, the LED
current will be inversely proportional to VDIM voltage. Before starting the design, several parameters must
be determined. Table 3 shows the design parameter for this example.
Table 3. Design Parameters for the Example of Analog Dimming at the FB Pin
Parameter
Value
Maximum input dimming voltage, VDIM_MAX
5V
Minimum input dimming voltage, VDIM_MIN
0V
Minimum LED current ILED_MIN at VDIM_MAX
0 mA
Maximum LED current ILED_MAX at VDIM_MIN
1500 mA
Resistor of FB filter, RF
10
475 Ω
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Step 1.
When VDIM is maximum, the LED current is 0 mA, which means the voltage across RSENSE,
VSENSE_MIN, is 0 V. Use Equation 2 to estimate RDIM.
VDIM _ MAX - 0.1
´ RF
R DIM =
0.1 - VSENSE _ MIN
(2)
The calculated RDIM is 23.275 kΩ.
Step 2. Choose the closest standard value for RDIM, here 23.7 kΩ is used. Use Equation 3 and
Equation 4 to calculate the minimum and maximum voltage across RSENSE, VSENSE_MIN, and
VSENSE_MAX, respectively.
VSENSE _ MIN = 0.1 -
VSENSE _ MAX = 0.1 -
(VDIM _ MAX - 0.1) ´ R F
R DIM
(3)
(VDIM _ MIN - 0.1) ´ R F
R DIM
(4)
The calculated result is VSENSE_MIN = 1.8 mV and VSENSE_MAX = 102 mV.
Step 3. Use Equation 5 to calculate RSENSE.
æ VSENSE _ MAX ö
÷
RSENSE = ç
ç I LED _ MAX ÷
è
ø
(5)
The calculated RSENSE = 68 mΩ. Here we choose 2-piece 33 mΩ in series.
3.3
No Dimming Application
In applications where dimming is not needed, connect the resistor divider from VIN to the PWM pin as
Figure 13 shows.
LO
1
GND
BOOT
6
CBOOT
CO
2
3
VIN
SW
PWM
VIN
FB
CIN
5
RF
4
CF
RSENSE
RTOP
RBOT
Figure 13. Application Without Dimming
The RTOP and RBOT resistor divider is sized to give a DC voltage between 1 V and 2 V at the PWM pin
when VIN reaches its steady-state voltage. The purpose is to make the device enter PWM dimming mode.
There are two reasons for choosing PWM dimming mode here. One is for better efficiency (100 mV at the
FB pin, instead of 200 mV), another is that entering PWM dimming mode has no requirement about the
rising slew rate of VIN, as described in Section 2.1.2, Potential Wrong Mode Detection.
10 kΩ is a good starting point for RBOT, then choose RTOP according to Equation 6:
æV
ö
RTOP = R BOT ´ ç IN - 1÷
è 1.5
ø
(6)
Table 4 shows the suggested resistor divider for several commonly used input rails.
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Dimming Method in Application
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Table 4. Suggested Resistor Divider for Some
Commonly Used Input Rail
3.4
VIN Amplitude
RTOP
RBOT
5V
24 kΩ
10 kΩ
12 V
68 kΩ
10 kΩ
24 V
150 kΩ
10 kΩ
Summary
The TPS5420X can support both analog dimming and PWM dimming. Table 5 summarizes these use
cases, as well as the advantage of each use case.
Table 5. Dimming Method Summary
Case
LED Current
Dimming Mode
Device
Dimming
Mode
1
PWM Dimming
PDIM
Analog
Dimming (LED
Current is
Continuous DC
Waveform)
ADIM
4
5
No dimming
Ref Circuit Advantage
● No color shift effect
● Easy for MCU control
PWM, amplitude > 2 V, < 1 kHz
Figure 11
PWM, amplitude between 1 V and 2 V, < 1 kHz
Figure 1
PWM, amplitude > 2 V, > 10 kHz
Figure 1
● Excellent dimming linearity
● Deep dimming (100% to 0.1%)
● Easy for MCU control
● Excellent uniformity of LED current
even under 1% PWM duty
● Free from beat frequency
interference
PDIM
Variable DC voltage
Figure 12
● Easy for DC dimming voltage
application
● Free from beat frequency
interference
PDIM
No need
Figure 13
● No dimming signal needed,
simplest interface for use
2
3
Input Dimming Signal
Both analog dimming mode and PWM dimming mode have their own limitations in application. For analog
dimming mode, the LED is always on, and the brightness is changed by changing the LED current
amplitude. Since the LED color temperature has a slight shift under different LED current amplitude, this
implies that analog dimming method will cause a color shift problem. For PWM dimming mode, the LED is
on and off (flashing) according to the PWM signal. LED brightness is changed by changing the PWM duty
cycle. Sometimes, this kind of flashing can be captured by a video system, such as surveillance system,
and become visible, this is called beat frequency interference.
A proper dimming mode should be chosen based on the specific system requirements. For the application
where color shift is not allowed, that is, an LED-illumination system, then the PWM dimming mode (case 1
and 2) should be chosen. While some applications care more about beat frequency interference, then the
analog dimming mode (case 3 and 4) should be used. Especially, for surveillance systems, not only is
beat frequency interference important, but they also need a very deep dimming range (100% down to
0.1%), for these situations, case 3 is the best choice. In case 3, the LED current amplitude uniformity can
be ensured under low dim ratio in mass production.
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Test Results
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4
Test Results
4.1
Analog Dimming Result
4.1.1
Analog Dimming on the PWM Pin
Using Figure 1 as the test circuit, 12-V input voltage, 3-piece IR LED in series as load, RSENSE = 133 mΩ,
PWM signal with 3.3-V amplitude is applied to the PWM pin, PWM frequency is 50 kHz. The measurement
result of the LED current under different PWM duty is shown in Figure 14. The dimming linearity is very
good.
1600
1400
LED Current (mA)
1200
1000
800
600
400
200
0
0
20%
40%
60%
PWM Duty (%)
80%
100%
Figure 14. LED Current vs PWM Duty in ADIM Mode
To check the deep dimming performance, the LED current to PWM duty relationship curves are zoomed in
the 1% to 5% PWM duty range, see Figure 15. The dimming linearity is very good in low dim ratio range.
7.00%
ILED / ILED_Full (%)
6.00%
5.00%
4.00%
Unit 1
Unit 2
Unit 3
Unit 4
Unit 5
Unit 6
Unit 7
Unit 8
3.00%
2.00%
1.00%
0.00
0
1%
2%
3%
4%
PWM Duty (%)
5%
6%
Figure 15. Deep Dimming in ADIM Mode
Figure 15 shows the result of 8 devices, the LED current uniformity is also good under the low dim ratio
range.
4.1.2
Analog Dimming on the FB Pin
Figure 16 is the experiment result based on the design in Analog Dimming on the FB Pin. 12-V input
voltage, 2-piece IR LED in series is used as load, RSENSE = 66 mΩ, 1.5-V DC voltage is applied at the
PWM pin. Variable DC voltage VDIM from 0 V to 5 V is applied to the FB pin through a 23.7-kΩ resistor.
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1600
1400
LED current (mA)
1200
1000
800
600
400
200
0
0
1
2
3
Dim Voltage (V)
4
5
Figure 16. LED Current vs VDIM Voltage
This measurement result matches the design target very well. LED current is inversely proportional with
dim voltage. When VDIM is maximum 5 V, the LED current reaches a minimum value of 23 mA which is
very close to the design target (0 mA). When VDIM is minimum 0 V, the LED current reaches a maximum
value of 1495 mA which is also close to the design target (1500 mA). The small difference between the
experiment result and the design target is due to the fact that RDIM can only be a standard resistance
value, which is a little different from the calculated value.
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Power and Dimming LED With TPS54200 and TPS54201
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4.2
PWM Dimming Waveform
Using Figure 11 as the test circuit: 24-V input voltage, 4-piece white LED, in series, is used as load. LO
and CO is 10 µH and 10 µF, respectively. RSENSE is 100 mΩ to get a 1-A LED current when PWM duty is
100%. RF is 200 Ω, CF is 82 nF.
The amplitude of input PWM signal is 5 V. RTOP and RBOT is 24 kΩ and 10 kΩ, respectively, thus the 5-V
input PWM is scaled down to 1.5 V and fed to the PWM pin.
Figure 17, Figure 18, and Figure 19 show the PWM dimming waveform at 2%, 50%, and 99% duty cycle,
respectively. CH1 is the input PWM signal, CH3 is the scaled signal fed at PWM pin, and CH4 is the LED
current waveform.
Figure 17. PWM Dimming With 2% Duty, 250 kHz
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Figure 18. PWM Dimming With 50% Duty, 250 kHz
16
Power and Dimming LED With TPS54200 and TPS54201
Copyright © 2017, Texas Instruments Incorporated
SLVA881 – April 2017
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References
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Figure 19. PWM Dimming With 99% Duty, 250 kHz
5
References
1. TPS54200 and TPS54201 4.5-V to 28-V Input Voltage, 1.5-A Output Current Synchronous Buck
WLED Driver data sheet (SLUSCO8)
2. TPS54200EVM-818 28-V, 1.5-A Buck LED Driver Evaluation Module user's guide (SLUUBI2)
3. TPS54201EVM-818 28-V, 1.5-A Buck LED Driver Evaluation Module user 's guide (SLUUBM3)
SLVA881 – April 2017
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