Texas Instruments | UCC21520, a Universal Isolated Gate Driver with Fast Dynamic Response (Rev. A) | Application notes | Texas Instruments UCC21520, a Universal Isolated Gate Driver with Fast Dynamic Response (Rev. A) Application notes

Texas Instruments UCC21520, a Universal Isolated Gate Driver with Fast Dynamic Response (Rev. A) Application notes
UCC21520: A Universal Isolated Gate Driver
with Fast Dynamic Response
Application Report
Literature Number: SLUA778A
June 2016 – Revised July 2016
Application Report
SLUA778A – June 2016 – Revised July 2016
UCC21520: A Universal Isolated Gate Driver with Fast
Dynamic Response
Wei Zhang
ABSTRACT
Developed for high-voltage applications where isolation and reliability is required, the UCC21520 delivers
reinforced isolation of 5.7 kVRMS along with a common mode transient immunity (CMTI) greater than 100
V/ns, and it has the industry’s best-in-class propagation delay of 19 ns and the best channel-to-channel
delay matching of less than 5 ns which enables high switching frequency, high-power density and
efficiency. In this application report, design considerations and benefits of the UCC21520’s fast dynamic
response are introduced with discussion of its wide application in a great variety of power electronics
topologies.
1
Trademarks
2
Introduction
To fully enhance the performance of the latest high-voltage power semiconductors, such as super junction
MOSFETs, trench/field stop IGBTs, wide band-gap SiC and GaN transistors, a universal gate driver
becomes a critical interface which not only supports enough peak source/sink current, but also facilitates
fast dynamic response with robustness and protection for higher switching frequency and higher efficiency
applications.
The flexible, universal capability of the UCC21520 with up to 18-V VCCI and 25-V VDDA/VDDB allows the
device to be used as a low-side, high-side, high-side/low-side or half-bridge driver with MOSFETs, IGBTs
or SiC MOSFETs. With its integrated components, advanced protection features (UVLO, deadtime and
disable) and the optimized dynamic performances, the UCC21520 enables designers to build smaller,
more robust designs for enterprise, telecom, automotive and industrial applications allowing for faster time
to market.
2
UCC21520: A Universal Isolated Gate Driver with Fast Dynamic Response
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Introduction
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The two output buffer stages of UCC21520 provides 4-A source and 6-A sink current, which provides
satisfied rising and falling time (<30 ns) with load capacitance up to 10 nF. However, in some scenarios
where the load is larger than 10 nF, external totem-pole buffer stage with discrete transistor should be
applied for achieving required rising and falling switching time. Figure 1 shows the UCC21520 drives 30
nF with single channel (green), and the rising time is 110 ns from 5 V to 20 V on the output waveform,
which is too long and does increase the switching loss. UCC21520 has two identical designed channels
with both propagation delay matching and pulse width distortion less than 5 ns, which make it possible to
parallel the output channel and double the gate drive strength. This application note will investigate the
dynamic performance of the UCC21520, and also discusses feasibility of paralleling UCC21520 two output
channels.
Figure 1. Single Channel Driving 30-nF Load Capacitance
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UCC21520: A Universal Isolated Gate Driver with Fast Dynamic Response
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3
Internal Shoot-Through with Mismatched Propagation Delay
3
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Internal Shoot-Through with Mismatched Propagation Delay
The propagation delay mismatch will introduce internal shoot-through if the two output channels are
paralleled. Figure 2 shows the simplified circuit diagram with UCC21520 two output channels in parallel
driving a heavy load. In this example, it is assumed that the channel A turn-on happens earlier than
channel B, or channel A turn-off later than channel B. The red dotted line shows the shoot-through path
which shorts VDD to ground with very small impedance, which is typically 1.5 Ω combining pull-up and
pull-down resistance. Therefore, there will be large current flow through the gate driver device, and will
result in additional internal heat. The estimated loss per cycle can be calculated by:
ª¬VDD ˜ IST ˜ tDM _ Rise VDD ˜ IST ˜ tDM _ Fall º¼ u fSW
PST
where
•
•
•
•
•
•
PST: Shoot-through introduced extra loss;
VDD: Supply voltage on VDDA and VDDB;
IST: Shoot-through current, decided by the pull-up and pull-down circuit design;
tDM_Rise: Propagation delay matching at rising edge;
tDM_Fall: Propagation delay matching at falling edge;
fSW: switching frequency;
(1)
To make sure UCC21520 two channels can be used in parallel, it is essential to quantify the delay
matching data at different VDD voltage and temperature.
Shoot-through path if
propagation delay mismatches
UCC21520
VDD
VDDA
INA
1
16
2
15
3
14
INB
GND
4
DIS
5
INPUT LOGIC
VCCI
13
12
DT
NC
VCCI
CBys
OUTA
6
11
7
10
8
9
VSSA
NC
NC
VDDB
VDD
CBys
OUTB
VSSB
>10 nF
Copyright © 2016 , Texas Instruments Incorporated
Figure 2. Internal Shoot-Through with Mismatched Propagation Delay Between Output Channels
4
UCC21520: A Universal Isolated Gate Driver with Fast Dynamic Response
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UCC21520 Dynamic Characteristics
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4
UCC21520 Dynamic Characteristics
To evaluate the dynamic characteristics of the UCC21520, propagation delay, propagation delay matching
and pulse width distortion performance are tested through different VDD voltage and temperature corners.
For definition of these parameters, please refer to UCC21520 datasheet.
Figure 3 and Figure 4 show the propagation delay measurement data with temperature and VDD voltage
corners. It can be seen that the propagation delay is independent of VDD voltage, and the typical
propagation delay is less than 20 ns across wide temperature range, which helps to improve system
response for high frequency applications, for example, timing control of zero voltage switching (ZVS), fast
response for system protection, etc.
VDD=12V
TA=25ƒC
25
Propagation Delay (ns)
Propagation Delay (ns)
25
20
15
TPDLH
TPDHL
10
-50
-25
0
25
50
75
100
20
15
TPDLH
TPDHL
10
125
10
15
Temperature (ƒC)
20
25
VDD (V)
Figure 3. Propagation Delay vs. Temperature
Figure 4. Propagation Delay vs. VDD
VDD=12V
6
4
2
0
-2
TDM-Rising
-4
TDM-Falling
-6
-50
-25
0
25
50
75
100
125
Propagation Delay Matching
(ns)
Propagation Delay Matching
(ns)
Figure 5 and Figure 6 show the propagation delay matching measurement data at temperature and VDD
voltage corners. It can be seen that the delay matching at both the rising and falling edges is less than 2
ns within wide temperature and VDD ranges, which does help the channel parallel performance to drive
large capacitance load.
TA=25ƒC
6
4
2
0
-2
TDM-Rising
-4
TDM-Falling
-6
10
Temperature (ƒC)
20
25
VDD (V)
Figure 5. Propagation Delay Matching vs. Temperature
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15
Figure 6. Propagation Delay Matching vs. VDD
UCC21520: A Universal Isolated Gate Driver with Fast Dynamic Response
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5
UCC21520 Dynamic Characteristics
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VDD=12V
6
Pulse Width Distortion (ns)
Pulse Width Distortion (ns)
Figure 7 and Figure 8 shows the pulse width distortion (PWD) measurement data, and it is less than 1 ns
through all the temperature and VDD voltage corners. Low PWD does help deliver the correct and precise
response with the given input signal, and maintain stable system operation.
4
2
0
-2
-4
-6
-50
-25
0
25
50
75
Temperature (ƒC)
100
125
TA=25ƒC
6
4
2
0
-2
-4
-6
10
Figure 7. PWD vs. Temperature
15
20
25
VDD (V)
Figure 8. PWD vs. VDD
In summary, low propagation delay, low propagation delay matching and low pulse width distortion does
position the UCC21520 as the best-in-class gate driver with the best-in-class dynamic response. It is
important to note that less than 2-ns propagation delay matching help to parallel the two output channels,
double the gate drive strength and increase the versatility of the UCC21520 for a variety of applications.
6
UCC21520: A Universal Isolated Gate Driver with Fast Dynamic Response
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SLUA778A – June 2016 – Revised July 2016
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Parallel UCC21520 Output Channels
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5
Parallel UCC21520 Output Channels
5.1
UCC21520 Efficiently Drives Heavy Capacitive Loads by Paralleling its Output Channels
To further evaluate the UCC21520 with two output channels in parallel, two test setups are prepared to
investigate the performance difference. As discussed in Section 3, extra power loss introduced by
propagation delay mismatch will add to the typical power consumption.
VDDA
INA
1
Function
Generator
16
VDDA
CBYP =10µF+1µF+220 nF
INB
2
15
VCCI
VCC=5V
3
14
INPUT LOGIC
GND
4
5
DIS
VOUTA
VSSA
15nF
VSSA
VDDB
11
6
DT
10
VCC
VCCI
8
VOUTB
9
VDDB
CBYP =10µF+1µF+220 nF
VSSB
15nF
VSSB
Copyright © 2016 , Texas Instruments Incorporated
Figure 9. Setup A: UCC21520 Drives Two 15-nF Loads with Two Channels Separately
VDD
INA
VCC=5V
1
16
VDDA
CBYP =10µF+1µF+220 nF
INB
2
VCCI
GND
15
3
4
5
DIS
INPUT LOGIC
Function
Generator
14
11
VOUTA
VSSA
VDDB
VSS
VDD
6
DT
10
VCC
VCCI
8
9
15nF X 2
VOUTB
VSSB
CBYP
10µF+1µF
+220 nF
VSS
Copyright © 2016 , Texas Instruments Incorporated
Figure 10. Setup B: UCC21520 Two Channel in Parallel Drives Two 15-nF Load
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7
Parallel UCC21520 Output Channels
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Figure 11 through Figure 13 show the total VDD (VDD = 12 V and 25 V) operating current consumption
measurement with different switching frequencies at 25°C/-40°C/125°C ambient temperatures. And it can
be seen that the current consumption differences between these two setups is negligible.
V DDA=VDDB=12V @25°C
200
80
160
IDD_Tot(mA)
IDD_Tot(mA)
VDDA=VDDB=25V @25°C
100
60
40
25V-25C-Separate
20
120
80
12V-25C-Separate
40
25V-25C-Paral
12V-25C-Paral
0
0
20
40
60
80
100
120
140
0
100
Switching Fs (kHz)
200
300
400
500
600
Switching Fs (kHz)
Figure 11. VDD Total Operating Current vs. FS at 25°C
V DDA=VDDB=12V@-40°C
200
80
160
IDD_Tot(mA)
IDD_Tot(mA)
VDDA=VDDB=25V @-40°C
100
60
40
25C--40C-Separate
120
80
12V--40C-Separate
40
20
12V--40C-Parl
25V--40C-Paral
0
0
20
40
60
80
100
120
0
140
100
Switching Fs (kHz)
200
300
400
500
600
Switching Fs (kHz)
Figure 12. VDD Total Operating Current vs. FS at –40°C
V DDA=VDDB=12V@125°C
200
80
160
IDD_Tot(mA)
IDD_Tot(mA)
VDDA=VDDB=25V @125°C
100
60
40
25V-125C-Paral
20
120
80
12V-125C-Paral
40
25V-125C-Separate
12V-125C-Separate
0
0
20
40
60
80
100
120
140
0
100
Switching Fs (kHz)
200
300
400
500
600
Switching Fs (kHz)
Figure 13. VDD Total Operating Current vs. FS at 125°C
8
UCC21520: A Universal Isolated Gate Driver with Fast Dynamic Response
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Figure 14 puts the current consumption data with tri-temperature performance in one graph with zoom-in
on the vertical axis.
VDDA=VDDB=25V @120kHz
VDDA=VDDB=12V@550kHz
95
200
IDD_Tot(mA)
Parallel
85
80
75
70
Separate
IDD_Tot(mA)
Separate
90
Parallel
190
180
170
160
-40°C
25°C
125°C
-40°C
Temperature
25°C
125°C
Temperature
Figure 14. VDD Total Operating Current vs. Temperature at VDD = 12 V and 25 V
Importantly, the VDD total current consumption data is measured with the device under test (DUT)
operating (switching) within only a short moment after the DUT, as well as junction temperature, soaks to
the ambient temperature, and the UCC21520 is not running into thermal stable state at the given switching
and load condition. The major purpose is to validate the driver device performance at given junction
temperature, and the users should not try to run the test conditions for a long time, since it may damage
the UCC21520 due to overheating. For UCC21520 safety-related performance, please refer to UCC21520
datasheet.
In summary, the UCC21520 shows very good performance with two output channels in parallel at all
operating switching frequencies, VDD range and temperature corners. Due to the best-in-class
propagation delay matching performance, the internal shoot-through caused extra loss is negligible.
Figure 15 shows the UCC21520 driving 30 nF with parallel and separate output, and it can be seen that
the output parallel can effectively increase the gate drive strength by 50%. The rising time is decreased to
be 50 ns from 5 V to 20 V on the output, which is less than half when using only single channel.
Figure 15. UCC21520 Single Channel Driving 30-nF Load Capacitance
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Parallel UCC21520 Output Channels
5.2
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Schematic and PCB Layout Recommendations when Paralleling Output Channels
To maintain the optimal performance of the UCC21520 with output channel in parallel, it is recommended
to follow the following schematic and PCB layout design considerations,
1. Short the INA and INB as close to the device as possible to make sure there is little delay introduced
between the two signal inputs.
2. Use the same bypassing capacitor for channel A and channel B respectively to minimize the timing
imbalance introduced due to parasitic inductance.
3. Make sure the PCB layout are symmetrical between channel A output and channel B output, refer to
Figure 16. More PCB layout information can be found in UCC21520 datasheet.
Figure 16. Layout Example for Paralleling UCC21520 Two Output Channels
4. If the external output resistor is used for system trade-offs, it is recommended to have two resistors
with the same resistance value placed in output A and output B to further minimize the parasitic
inductance introduced channel imbalance, refer to Figure 17.
UCC21520
INA
1
16
2
15
VCCI
3
14
VSSA
GND
4
13
NC
DIS
5
12
NC
DT
6
11
VDDB
NC
7
10
VCCI
8
9
VDDA
INPUT LOGIC
OUTA
INB
RExt_A
OUTB
VSSB
RExt_B
Copyright © 2016 , Texas Instruments Incorporated
Figure 17. Paralleling UCC21520 Two Output Channels with External Resistor
10
UCC21520: A Universal Isolated Gate Driver with Fast Dynamic Response
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UCC21520 Driving Different Power Topologies
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6
UCC21520 Driving Different Power Topologies
The flexible, universal capability of the UCC21520 with up to 18-V VCCI and 25-V VDDA/VDDB allows the
device to be used as a low-side, high-side, high-side/low-side or half-bridge driver with MOSFETs, IGBTs
or SiC MOSFETs. Here are some topology examples where the UCC21520 can fit very well. Synchronous
buck or boost is shown in Figure 18 and Figure 19; full bridge isolated converter is shown in Figure 20;
Motor drives application is shown in Figure 21.
VIN HV DC-Link
+
±
UCC21520
VDDA
INA
1
16
2
15
3
14
INB
OUTA
GND
INPUT LOGIC
VCCI
VSSA
VOUT
13
NC
12
NC
6
11
VDDB
7
10
8
9
4
DIS
5
DT
NC
VCCI
OUTB
VSSB
Copyright © 2016 , Texas Instruments Incorporated
Figure 18. UCC21520 Used in Synchronous Buck
VOUT HV DC-Link
UCC21520
VDDA
INA
1
16
2
15
3
14
INB
OUTA
GND
4
DIS
5
INPUT LOGIC
VCCI
VSSA
VIN
13
NC
12
NC
11
VDDB
DT
6
NC
VCCI
7
10
8
9
+
±
OUTB
VSSB
Copyright © 2016 , Texas Instruments Incorporated
Figure 19. UCC21520 Used in Synchronous Boost
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11
Summary
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VIN
+
±
UCC21520
VDDA
INA
1
UCC21520
VDDA
16
INB
2
15
3
14
VCCI
INPUT LOGIC
4
DIS
5
OUTA
VSSA
VSSA
INA
1
15
2
14
3
INB
VCCI
INPUT LOGIC
GND
OUTA
16
GND
13
NC
NC
13
4
12
NC
NC
12
VDDB
VDDB
11
6
OUTB
OUTB
10
7
VSSB
VSSB
9
8
DIS
5
DT
DT
6
NC
VCCI
11
7
10
8
9
NC
VCCI
Secondary Side
Copyright © 2016 , Texas Instruments Incorporated
Figure 20. UCC21520 Used in Full-Bridge Isolated Converter
VIN
UCC21520
2
15
3
14
4
DIS
5
INPUT LOGIC
VCCI
GND
VDDA
INA
OUTA
INB
16
13
1
VSSA
15
3
14
GND
4
DIS
12
NC
11
VDDB
5
INA
OUTA
INB
13
VSSA
B
7
10
8
9
OUTB
VSSB
NC
16
2
15
3
14
OUTA
GND
4
DIS
12
NC
11
VDDB
5
VSSA
13
NC
12
NC
6
11
VDDB
7
10
8
9
C
+
±
DT
6
VCCI
VDDA
1
VCCI
NC
DT
6
NC
2
VCCI
NC
DT
VCCI
A
UCC21520
VDDA
16
INPUT LOGIC
1
INB
INPUT LOGIC
UCC21520
INA
7
10
8
9
OUTB
NC
VSSB
VCCI
OUTB
VSSB
M
Copyright © 2016 , Texas Instruments Incorporated
Figure 21. UCC21520 Used in Motor Drives
7
Summary
The UCC21520 is a dual-channel gate driver with reinforced isolation of 5.7 kVRMS along with a commonmode transient immunity (CMTI) greater than 100 V/ns. This application report discussed the UCC21520’s
best-in-class propagation delay of 19 ns and the best channel-to-channel delay matching of less than 5 ns
which enables high-switching frequency, high-power density and efficiency. Importantly, design
considerations and benefits with the UCC21520’s fast dynamic response and two output channels in
parallel are addressed in detail with its wide application in a great variety of power electronics topologies.
Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Original (June 2016) to A Revision ......................................................................................................... Page
•
12
Changed text from "The rising time is increased..." to "The rising time is decreased..."
Revision History
........................................
9
SLUA778A – June 2016 – Revised July 2016
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