Texas Instruments | Dual TPS2378 PD for 51-W High-Power Four-Pair PoE (Rev. A) | Application notes | Texas Instruments Dual TPS2378 PD for 51-W High-Power Four-Pair PoE (Rev. A) Application notes

Texas Instruments Dual TPS2378 PD for 51-W High-Power Four-Pair PoE (Rev. A) Application notes
Application Report
SLVA625A – November 2013 – Revised June 2016
Dual TPS2378 PD for 51-W High Power-Four Pair PoE
Eric Wright
ABSTRACT
This application report discusses a high-power four-pair solution for Power-over-Ethernet (PoE)
applications requiring power in excess as defined in the current IEEE 802.3at standard. Specifically, this
report provides a dual TPS2378-based, forced four-pair solution providing 45 W to the load.
1
2
3
4
5
Contents
Introduction ...................................................................................................................
Requirements ................................................................................................................
2.1
Criteria................................................................................................................
2.2
Importance of PD Efficiency and Current Sharing..............................................................
Reference Design Description .............................................................................................
3.1
DC-DC Converter ...................................................................................................
Conclusion ....................................................................................................................
References ...................................................................................................................
2
2
3
3
3
7
8
8
List of Figures
....................................................................
1
Top Level Block Diagram: Forced Four-Pair UPOE
2
Schematic Diagram: Ethernet Power Input and Diode Bridge ......................................................... 4
2
3
Schematic Diagram: Dual TPS2378, ON Control, and MPS ........................................................... 5
4
Schematic Diagram: High Power DC-DC Converter .................................................................... 6
1
Requirements Summary .................................................................................................... 2
List of Tables
UPOE is a trademark of Cisco.
All other trademarks are the property of their respective owners.
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1
Introduction
1
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Introduction
The TPS2378 device is an IEEE 802.3at compliant, Type 2 PoE Powered Device (PD) controller.
TPS2378 supports use with high power auxiliary adapters and provides startup control for the DC-DC
converter. The TPS2378 device can be arranged in a dual fashion to support high-power, four-pair
operation at 51 W at the input RJ45 connector which therefore enables Cisco System’s Universal Power
Over Ethernet (UPOE™) concept.
There are two basic forms of UPOE. One is based on Link Layer Discovery Protocol (LLDP) which is
through the Ethernet data path. The other form is forced using circuit hardware only. In both forms, the
power sourcing equipment (PSE) proceeds by detecting, classifying, and ramping up voltage to one pair
set according to the IEEE 802.3at standard. The method used at the PD (LLDP or forced) determines how
the operating voltage is applied to the second pair set. The focus of this application report is on a forced
four-pair PD as shown in Figure 1.
Power Sourcing Equipment
(PSE)
PSE
RJ45
100-m Link
Segment
Powered Device (PD)
PD
RJ45
48-V OUT
(Optional)
1
1
(+)
TX
2
2
3
3
TX
Port 1
54 V
TPS2378
Port 1
DC-DC
Converter
Bridge
RX
TX
6
6
Signal
Pairs
RX
(±)
4
4
5
5
7
7
8
8
TX
Port 2
RX
TPS2378
Port 2
Bridge
RX
Figure 1. Top Level Block Diagram: Forced Four-Pair UPOE
A key concept of the forced design is that it prevents reverse biasing of the bridge on the second PSE port
pair by using the additional PD controller series diodes. This concept allows for normal detection and
classification on the second PSE port while the first pair set is powered. The PD must not exceed the
power consumption requirements for standard Type 2 PDs until the second pair set is powered.
2
Requirements
The PD solution requirements shown in Table 1 reflect the following system level assumptions shown in
Figure 1.
• Dual IEEE 802.3at type 2 PSE ports (each port uses two signal pairs) delivering power to the PD over
a single Ethernet cable.
• PSE output power (at PSE RJ45 connector): 30 W maximum for each port or 60 W maximum for both
ports.
• PSE output voltage (at PSE RJ45 connector): 50 V minimum for each port.
• Link segment (Ethernet cabling): Each port modeled as 12.5 Ω maximum DC pair loop resistance for
the 100-m Ethernet link segment.
Table 1. Requirements Summary
Parameter
2
Limit
PD input power
51 W
PD input voltage
42.5 V
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Requirements
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Table 1. Requirements Summary (continued)
Parameter
2.1
Limit
Load power requirement
45 W
Converter efficiency
> 88%
Pair current (max for both)
1.2 A
Converter output voltage
19 V
Converter output current
2.9 A
Criteria
The high-power solution meets the following basic criteria:
• Current sharing between both pair sets provides at least 51 W available at the PD power interface (PI).
NOTE:
•
•
•
2.2
Inadequate current sharing can result in port turn-off, erratic behavior (PSE or PD) or other
negative results. Erratic behavior occurs because of current-limit onset or inadequate PD
input voltage on the pair set carrying the higher current. Saturation of data transformers is
another concern of inadequate current sharing.
Avoids data transformer saturation through the use of magnetic components compatible with IEEE
802.3at standard (minimum). Based on the current sharing balance, higher current data transformers
may be required.
No overheating in the PD circuitry.
A high efficiency DC-DC converter is required to maximize the power available to the load.
Importance of PD Efficiency and Current Sharing
The maximum ensured PD input power is 51 W with the PD input voltage as low as 42.5 V because of the
cable impedance excluding of the effect of current imbalance between pairs. As a consequence, the PD
output power is limited by efficiency which includes a bridge, a return switch, and a DC-DC converter. The
required output power imposes an efficiency requirement on the PD.
In order to ensure reliable system level operation, a worst case PD efficiency analysis is required. The
worst case efficiency includes the input bridge, the PD front-end return switch, any additional series diode,
the PoE data transformers, and the efficiency of the DC-DC converter stage.
With passive current sharing, any impedance difference through each power feed and return impacts the
current imbalance between each pair set. Passive current sharing requires that the PSE provide power
through a single cable and from a common voltage source to minimize the impedance difference.
In some cases, the use of a standard or a Schottky bridge with negative temperature coefficient, impairs
sharing when the Ethernet link segment is short. To minimize this effect, diode characteristics must match
with good temperature matching along with good PCB thermal management.
In summary, the PD architecture and efficiency must carefully be selected to meet the maximum output
power requirement.
3
Reference Design Description
Figure 2, Figure 3, and Figure 4 show a dual-TPS2378, high-power, four-pair reference design
(TPS2378EVM-602). For the BOM, refer to the user's guide for the EVM (SLVUAG7). Dual-TPS2378 PD
controllers are used in Figure 3 to OR both pair sets together. Each TPS2378 device provides a typical
current limit of 1 A. With PD input power of 51 W at 42.5 V minimum, the total pair set current is 1.2 A or
600 mA, assuming equal current sharing for both.
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Reference Design Description
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T3
24
1
1
2
3
4
5
6
7
8
POE INPUT
42.5-57VDC
23
2
R28
75.0
1
2
3
4
5
6
7
8
3
22
1:1
21
4
20
5
R29
75.0
J3
ETHERNET DATA
J4
6
19
1:1
18
7
17
8
R30
75.0
9
16
1:1
15
10
14
11
R31
75.0
12
13
1:1
PAIR12
TP12
PAIR36
C25
1000pF
TP13
PAIR45
TP14
PAIR78
TP15
CHGND
L3
VDD
100 ohm
D8
C26
0.01µF
C27
0.01µF
C28
0.01µF
L4
D9
C29
0.01µF
DNP
R32
75.0
R33
75.0
R34
75.0
R35
75.0
100 ohm
J9
D10
C30
1000pF
+BRG1
-BRG1
C31
1000pF
D11
J10
DNP
+BRG2
-BRG2
J8
TP16
C32
1000pF
CHGND
4
~BRG1
3
2DNP
1
~BRG2
L5
VSS2
100 ohm
D12
L6
D13
VSS1
100 ohm
CHGND
D14
D15
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Figure 2. Schematic Diagram: Ethernet Power Input and Diode Bridge
4
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Reference Design Description
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VOUT
VOUT
J5
T2P-VPU1
R46
49.9k
D16
LO E6SF-ABCB-24-1-Z
VBIAS
U5
R47
10.0k
J6
1
4
2
3
1
2
3
4
FOD817DS
T2P1+
T2P1T2P2+
T2P2-
PGND
VDD
VDD
TP17
VBIAS
R49
24.9k
U3
1
VDD
APD
DEN
T2P
CLS
CDB
VSS
PWPD
RTN
R50
DNP
20.0k
8
7
4
2
UPOE
OUTPUT
60W MAX
R48
100k
C33
47µF
3
C34
0.1µF
4
9
D17
SMAJ58A
58V
6
5,6,
7,8
RTN1
5
TPS2378DDA
1,2,3
Q9
FDMS86105
PWRGND
R52
63.4
VOUT
VOUT
VSS1
J7
TP18
T2P-VPU2
VSS1
R53
49.9k
LO E6SF-ABCB-24-1-Z
D18
VBIAS
U8
R54
1
10.0k
4
2
3
FOD817DS
PGND
R55
24.9k
APD
8
2
3
DEN
T2P
7
CLS
CDB
6
4
9
VSS
PWPD
RTN
5
VOUT
R37
5.6k
1W
4
VDD
R56
100k
C35
47µF
U4
1
D19
SMAJ58A
58V
C36
0.1µF
RTN2
R51
78.7k
R45
8.87k
R57
R58
12.1k
33.2k
U7
1,2,3
Q5
MMBT5550LT1G
TPS2378DDA
R44
63.4
5,6,
7,8
R36
5.6k
1W
4
Q8
FDMS86105
1
3
2
HMHA2801A
VBIAS
R43
DNP
0
R59
DNP
100
VSS2
PWRGND
D20
TP19
BAT46W-7-F
VSS2
R41
100k
PGND
R42
30.1k
SS
R40
100k
D21
D22
Q6
BSS123
BAT46W-7-F
R39
10.0k
C37
0.01µF
Q7
BSS123
BAT46W-7-F
C38
0.01µF
R38
10.0k
Copyright © 2016, Texas Instruments Incorporated
Figure 3. Schematic Diagram: Dual TPS2378, ON Control, and MPS
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Reference Design Description
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RL_INHBT
Optional Load Delay Circuit
TP20
R62
R63
25.5k
VOUT
25.5k
U9
PGND
8
R60
47.5k
4
R61
1.43k
2
6
7
VCC
RESET
RL_INHBT
SENSE
C40
0.1µF
CT
C1
1
3
C39
2.2µF
NC
NC
NC
GND
5
TL7700CDGKR
PGND
2200pF
VDD
PGND
PGND
L1
1
T1
10
11
12
LPS4018-332MLB
C2
0.1µF
C3
2.2µF
C4
2.2µF
R1
39k
C5
2.2µF
C6
0.1µF
VOUT
5
7
8
9
C8
10µF
6
C9
10µF
VOUT
19V/2.9A
SPGND
C7
68µF
C10
10µF
C11
1µF
J1
RL_INHBT
PWRGND
PWRGND
PWRGND
C41
0.1µF
4
D1
MURA120T3G
TP2
TP1
L2
3
5,6,
7,8
1,2,3
TP21
TP3
5,6,
7,8
OUT
TP5
D2
PGND
Q1
FDMS86252
4
Q10
CSD18504Q5A
MMSD4148T1G
J2
PGND
2
1
4.7
SPGND
TP4
1,2,3
R2
DRAIN
J11
Q2
MMBT3906
Load Delay Disable
C12
470pF
CS
PWRGND
1.00k
R3
10.0k
Q3
FDMS86105
TP7
4
R6
10
1W
PWRGND
C13
100pF
1,2,3
R5
7,8
5,6,
R4
0.1
TP6
D4
BAT54S-7-F
D3
LY E6SF-AABA-46-1-Z
PWRGND
VBIAS
PGND
Q4
MMBT3906
PWRGND
TP8
VBIAS
D5
C14
22µF
MMSD4148T1G
PGND
R7
20.0
R8
20.0
PGND
PWRGND
D6
BAT54S-7-F
C15
T2
1
4
0.47µF
C16
8
R9
121k
2.61k
R12
R13
121k
4.22k
5
PGND
PA0184NLT
R10
0.47µF
R11
10.0k
PWRGND
PWRGND
C17
PGND
SS
PWRGND
C18
R14
0
2200pF
U6
7.50k
R16 80.6k
R20 61.9k
R21 100k
1µF
PWRGND
7
SYNC
LINEUV
18
3
RTDEL
AUX
14
4
RON
OUT
15
5
10
2
20
C22
19
1
16
17
ROFF
CS
RSLOPE
FB
VREF
VIN
PVDD
VDD
TP9
R17
3.83k
9
11
VREF
PGND
GND
U1
C19
BAT54S-7-F
47pF
R23
49.9k
1.21M
C20
1µF
13
8
R19
10.0k
D7
TP11
R22
6
R18
10.0k
FB
TP10
NC
NC
LOOP
PGND
R24
HMHA2801A
UCC2897APW
200k
PWRGND
PWRGND
U2
TL431AIDBV
PWRGND
2
1
C23
1µF
R25
6.81k
R27
2.00k
C21
0.047µF
3
R15
LINEOV
4
NC
NC
0.01µF
SS/SD
R26
7.5k
5
12
PGND
C24
0.039µF
PGND
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Figure 4. Schematic Diagram: High Power DC-DC Converter
6
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Detection and classification occurs on either pair set independently because of the body diodes in the
ORing MOSFETs (Q8 and Q9) in the RTN side of each TPS2378 device. If each TPS2378 RTN pin was
connected together, the first powered pair set backs the bias of the diode bridges of the second pair set.
In this case, the second pair set does not undergo detection and classification.
In addition to Q8 and Q9, there are two required circuits to ensure that the following must occur. Figure 3
shows these circuits.
(a) The converter does not start until both TPS2378 circuits are powered.
(b) The maintain power signature (MPS) remains presented to each PSE port until the converter is
powered.
The converter disable circuit holds off converter startup by holding the DC-DC controller soft-start pin low
until both TPS2378 RTN pins are low. The Q6 and Q7 circuits provide this function through a wire OR
connection of their drains, respectively. The gates of each monitor the TPS2378 RTN pin (the drain
connection of the TPS2378 internal MOSFET) and Q6 or Q7 remains ON until the respective TPS2378
RTN pin falls to a sufficient level. When both Q6 and Q7 are OFF, then SS releases. When UCDB is
released, VOUT ramps up and current flows through U7 and releases Q5; the ORing MOSFETs, Q8 and
Q9, turn on which shorts out the respective body diodes and further reduces the ORing loss. Diode D20
blocks any voltage from affecting the UCC2897A SS pin. R42 can be chosen at the discretion of the user.
The MPS circuit detects when the DC-DC converter output voltage is OFF. The MPS circuit then applies
the minimum DC load to the PSE ports to allow the ports to remain powered until the converter draws
power. When VOUT is OFF, then U8 transistor is also OFF which allows Q17 to turn ON and loads the
ports with current greater than 10 mA. When VOUT is ON, then the U8 transistor turns ON and turns OFF
Q17 which removes the MPS load and the additional loss element.
Type 2 PSE (T1P) hardware detection circuitry is also available for each TPS2378 device. Each T1P pin
on the respective TPS2378 is connected to J4 through optocouplers. The optocoupler outputs are
configured such that when both T1P signals are active (active low) each optocoupler is ON. Through wire
AND’ing the optocouplers together, a single T1P signal is used to alert downstream loads that 51 W is
available.
For additional information on the TPS2378 device, see the TPS2378 datasheet (SLVSB99).
3.1
DC-DC Converter
This section provides a short description of the circuit elements.
The following circuit elements form the power stage of the converter: transformer T1, transistors Q1 and
Q3, input capacitor C2, output capacitor C10, and L2, C7, and C11 which provide additional ripple filtering.
The power resistor, R36, senses the primary-switch current and converts this current into a voltage to be
sensed by the primary-side controller feedback-comparator.
The primary-side voltage clamp comprises of resistor R1, capacitor C6, and diode D1. The secondary-side
snubbing is provided by resistor R6 and capacitor C12.
The operating current for the UCC2897A device is provided through the self-biasing components R8, D5,
and C22.
Resistor R5 and capacitor C13 filter out leading-edge current spikes which are caused by the reverse
recovery of the rectifier, equivalent capacitive loading on the secondary, and parasitic circuit inductances.
Capacitor C18 programs the soft-start time.
The primary side gate-drive circuitry is composed of the phasing network, R2, Q2, and D2. The
secondary-side synchronous rectifier gate-drive circuitry is composed of D6, C15, T2, C16, R11, R7, D4,
and Q4.
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Conclusion
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The resistor-divider network, R23 and R26, comprises the voltage-sense feedback loop with R14 providing
a 50-Ω injection point for small-signal control-loop analysis. Feedback components R24 and C21 provide
the necessary gain and pole to stabilize the control loop. R17 provides bias current to optocoupler U1, and
secondary-side error-amplifier and voltage-reference U2. R27 provides the proper offset for the voltagefeedback signal to be summed with the current-sense signal and the slope compensation at the FB pin of
the UCC2897A device. R25 and C24 provide a compensation zero.
R18 and C23 provide secondary-side soft start. D7 helps ensure that C23 is discharged when the supply
shuts down.
4
Conclusion
In conclusion, this application report provides a means to force four-pair PoE operation using only a
limited amount of additional circuitry. This forced four-pair method allows for exploration of high-power
PoE operation without implementation of LLDP software.
5
References
1. TPS2378 Data Sheet, SLVSB99
2. TPS2378EVM-105 User’s Guide, SLVU682
3. TPS2378EVM-602 User's Guide, SLVUAG7
8
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Revision History
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Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Original (November 2013) to A Revision ................................................................................................ Page
•
•
•
•
Changed the Ethernet power Input schematic ........................................................................................
Changed the Dual TPS2378, ON Control, and MPS schematic ....................................................................
Changed the High Power DC-DC Converter schematic .............................................................................
Changed references to component designators to match updated schematics ..................................................
SLVA625A – November 2013 – Revised June 2016
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Revision History
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