Texas Instruments | UCD3138064A Migration | Application notes | Texas Instruments UCD3138064A Migration Application notes

Texas Instruments UCD3138064A Migration Application notes
Application Report
SLUA766 – November 2015
UCD3138064A Migration Guide
HPCS / HVPS
ABSTRACT
This application note describes differences between Texas Instruments'
UCD3138064 and UCD3138064A Digital power controllers to assist
customers in migrating application. While the main focus of this document
is migration from UCD3138064 to UCD3138064A, this document is also
useful if you are considering migrating in the reverse direction. Functions
that are identical in both devices are not included in this document. All
efforts have been made to provide a comprehensive list of the differences
between the two devices in the UCD3138 family.
1
2
3
4
<TOCtitle> Contents
Introduction ..................................................................................................................................... 8
Device Overview summary ............................................................................................................. 9
2.1 New Features ............................................................................................................................ 9
2.1.1 Body diode conduction time sensing ............................................................................. 9
2.1.2 UART Auto Baud Enhacement .................................................................................... 11
2.2 Bug Fix/ Enhancements .......................................................................................................... 12
2.3 Pinmultiplexing updates .......................................................................................................... 15
2.4 Revision update ....................................................................................................................... 16
Application Migration care about ................................................................................................ 16
3.1 Change to Device ID ............................................................................................................... 16
3.2 Possible Changes to Layout and Power Supply Filtering ........................................................ 16
3.3 LLC Topology .......................................................................................................................... 16
3.4 PS- LLC Topology ................................................................................................................... 16
3.5 HSFB Topology ....................................................................................................................... 17
3.6 PSFB Topology ....................................................................................................................... 17
3.7 PFC Topology ......................................................................................................................... 18
Memory Map for UCD3138064A ...................................................................................................18
4.1 Loop Mux Registers ................................................................................................................ 18
4.1.1 Front End Control 0 Mux Register (FECTRL0MUX) .................................................... 18
4.1.2 Front End Control 1 Mux Register (FECTRL1MUX) .................................................... 21
4.1.3 Front End Control 2 Mux Register (FECTRL2MUX) .................................................... 23
4.1.4 Sample Trigger Control Register (SAMPTRIGCTRL).................................................. 25
4.1.5 External DAC Control Register (EXTDACCTRL)......................................................... 26
4.1.6 Filter Mux Register (FILTERMUX) ............................................................................... 28
4.1.7 Filter KComp A Register (FILTERKCOMPA)............................................................... 30
4.1.8 Filter KComp B Register (FILTERKCOMPB)............................................................... 30
4.1.9 DPWM Mux Register (DPWMMUX) ............................................................................ 31
Page 1 of 319
SLUA766 – November 2015
4.1.10 Constant Power Control Register (CPCTRL) .............................................................. 33
4.1.11 Constant Power Nominal Threshold Register (CPNOM) ............................................. 34
4.1.12 Constant Power Max Threshold Register (CPMAX) .................................................... 35
4.1.13 Constant Power Configuration Register (CPCONFIG) ................................................ 35
4.1.14 Constant Power Max Power Register (CPMAXPWR) ................................................. 37
4.1.15 Constant Power Integrator Threshold Register (CPINTTHRESH) .............................. 37
4.1.16 Constant Power Firmware Divisor Register (CPFWDIVISOR) .................................... 37
4.1.17 Constant Power Status Register (CPSTAT) ................................................................ 38
4.1.18 Cycle Adjustment Control Register (CYCADJCTRL)................................................... 39
4.1.19 Cycle Adjustment Limit Register (CYCADJLIM) .......................................................... 40
4.1.20 Cycle Adjustment Status Register (CYCADJSTAT) .................................................... 40
4.1.21 Global Enable Register (GLBEN) ................................................................................ 41
4.1.22 PWM Global Period Register (PWMGLBPRD) ............................................................ 42
4.1.23 Sync Control Register (SYNCCTRL) ........................................................................... 42
4.1.24 Light Load Control Register (LLCTRL) ........................................................................ 43
4.1.25 Light Load Enable Threshold Register (LLENTHRESH) ............................................. 43
4.1.26 Light Load Disable Threshold Register (LLDISTHRESH) ........................................... 44
4.1.27 Analog Peak Current Mode Ramp Register (APCMRAMP) ........................................ 44
4.1.28 Analog Peak Current Mode Control Register (APCMCTRL) ....................................... 44
4.1.29 DTC Control (DTCCTRL)............................................................................................. 45
4.1.30 DTC Target (DTCTARGET)......................................................................................... 47
4.1.31 DTC Auto Control Limit (DTCLIMIT) ............................................................................ 47
4.1.32 DTC Manual Control (DTCMANUAL) .......................................................................... 47
4.1.33 DTC Monitor (DTCMONITOR)..................................................................................... 48
4.1.34 DTC Status (DTCSTAT) .............................................................................................. 48
4.2 Fault Mux Registers ................................................................................................................ 49
4.2.1 Analog Comparator Control 0 Register (ACOMPCTRL0)............................................ 49
4.2.2 Analog Comparator Control 1 Register (ACOMPCTRL1)............................................ 50
4.2.3 Analog Comparator Control 2 Register (ACOMPCTRL2)............................................ 53
4.2.4 Analog Comparator Control 3 Register (ACOMPCTRL3)............................................ 54
4.2.5 External Fault Control Register (EXTFAULTCTRL) .................................................... 55
4.2.6 Fault Mux Interrupt Status Register (FAULTMUXINTSTAT) ....................................... 57
4.2.7 Fault Mux Raw Status Register (FAULTMUXRAWSTAT) ........................................... 59
4.2.8 Comparator Ramp Control 0 Register (COMPRAMP0)............................................... 61
4.2.9 Digital Comparator Control 0 Register (DCOMPCTRL0)............................................. 62
4.2.10 Digital Comparator Control 1 Register (DCOMPCTRL1)............................................. 63
4.2.11 Digital Comparator Control 2 Register (DCOMPCTRL2)............................................. 64
4.2.12 Digital Comparator Control 3 Register (DCOMPCTRL3)............................................. 65
4.2.13 Digital Comparator Counter Status Register (DCOMPCNTSTAT) .............................. 66
4.2.14 DPWM 0 Current Limit Control Register (DPWM0CLIM) ............................................ 67
4.2.15 DPWM 0 Fault AB Detection Register (DPWM0FLTABDET) ...................................... 69
4.2.16 DPWM 0 Fault Detection Register (DPWM0FAULTDET) ........................................... 72
4.2.17 DPWM 0 IDE Detection Register (DPWM0IDEDET) ................................................... 77
4.2.18 DPWM 1 Current Limit Control Register (DPWM1CLIM) ............................................ 79
4.2.19 DPWM 1 Fault AB Detection Register (DPWM1FLTABDET) ...................................... 82
4.2.20 DPWM 1 Fault Detection Register (DPWM1FAULTDET) ........................................... 84
4.2.21 DPWM 1 IDE Detection Register (DPWM1IDEDET) ................................................... 89
4.2.22 DPWM 2 Current Limit Control Register (DPWM2CLIM) ............................................ 91
4.2.23 DPWM 2 Fault AB Detection Register (DPWM2FLTABDET) ...................................... 94
4.2.24 DPWM 2 Fault Detection Register (DPWM2FAULTDET) ........................................... 96
4.2.25 DPWM 2 IDE Detection Register (DPWM2IDEDET) ................................................. 101
Application Report
SLUA766 – November 2015
4.3
4.4
4.5
4.6
4.2.26 DPWM 3 Current Limit Control Register (DPWM3CLIM) .......................................... 103
4.2.27 DPWM 3 Fault AB Detection Register (DPWM3FLTABDET) .................................... 106
4.2.28 DPWM 3 Fault Detection Register (DPWM3FAULTDET) ......................................... 108
4.2.29 DPWM 3 IDE Detection Register (DPWM3IDEDET) ................................................. 113
4.2.30 HFO Fail Detect Register (HFOFAILDET) ................................................................. 114
4.2.31 LFO Fail Detect Register (LFOFAILDET) .................................................................. 114
4.2.32 IDE Control Register (IDECTRL) ............................................................................... 115
I2C – Serial Bus Interface ..................................................................................................... 116
4.3.1 I2C Control Register 1 (I2CCTRL1) ........................................................................... 116
4.3.2 I2C Transmit Data Buffer (I2CTXBUF) ...................................................................... 117
4.3.3 I2C Receive Data Register (I2CRXBUF) ................................................................... 117
4.3.4 I2C Acknowledge Register (I2CACK) ........................................................................ 117
4.3.5 I2C Status Register (I2CST) ...................................................................................... 119
4.3.6 I2C Interrupt Mask Register (I2CINTM) ..................................................................... 121
4.3.7 I2C Control Register 3 (I2CCTRL3) ........................................................................... 123
SPI – Serial Peripheral Interface ........................................................................................... 125
4.4.1 SPI Control Register (SPICTRL) ............................................................................... 125
4.4.2 SPI Status Register (SPISTAT) ................................................................................. 126
4.4.3 SPI Pin Function Register (SPIFUNC) ...................................................................... 126
4.4.4 SPI Pin Direction Register (SPIDIR) .......................................................................... 127
4.4.5 SPI Pin GP Out Register (SPIGPOUT) ..................................................................... 127
4.4.6 SPI Pin GP In Register (SPIGPIN) ............................................................................ 128
4.4.7 SPI TX Buffer Register 0 (SPITX0) ........................................................................... 128
4.4.8 SPI TX Buffer Register 1 (SPITX1) ........................................................................... 129
4.4.9 SPI Read Buffer Register 0 (SPIRX0) ....................................................................... 129
4.4.10 SPI Read Buffer Register 1 (SPIRX1) ....................................................................... 129
4.4.11 SPI Read Buffer Register 2 (SPIRX2) ....................................................................... 130
4.4.12 SPI Read Buffer Register 3 (SPIRX3) ....................................................................... 130
UART Registers .................................................................................................................... 130
4.5.1 UART Control Register 0 (UARTCTRL0) .................................................................. 130
4.5.2 UART Receive Status Register (UARTRXST)........................................................... 131
4.5.3 UART Transmit Status Register (UARTTXST) .......................................................... 133
4.5.4 UART Control Register 3 (UARTCTRL3) .................................................................. 134
4.5.5 UART Interrupt Status Register (UARTINTST) ......................................................... 135
4.5.6 UART Baud Divisor High Byte Register (UARTHBAUD) ........................................... 137
4.5.7 UART Baud Divisor Middle Byte Register (UARTMBAUD) ....................................... 137
4.5.8 UART Baud Divisor Low Byte Register (UARTLBAUD) ............................................ 137
4.5.9 UART Receive Buffer (UARTRXBUF) ....................................................................... 137
4.5.10 UART Transmit Buffer (UARTTXBUF) ...................................................................... 139
4.5.11 UART I/O Control Register (UARTIOCTRLSCLK, UARTIOCTRLRX,
UARTIOCTRLTX) ...................................................................................................... 139
4.5.12 UART Baud Divisor Sub Bits Register (UARTSBAUD) ............................................. 139
4.5.13 UART RX Control Register 4 (UARTRXCTRL4) ....................................................... 140
4.5.14 UART RX Control Register 5 (UARTRXCTRL5) ....................................................... 141
4.5.15 UART RX Baud Divisor Middle Byte Register (UARTRXMBAUD) ............................ 142
4.5.16 UART RX Baud Divisor Low Byte Register (UARTRXLBAUD) ................................. 142
4.5.17 UART RX Baud Divisor Sub Bits Register (UARTRXSBAUD) .................................. 142
ADC Registers ....................................................................................................................... 144
Page 3 of 319
SLUA766 – November 2015
4.6.1 ADC Control Register (ADCCTRL) ............................................................................ 144
4.6.2 ADC Status Register (ADCSTAT) ............................................................................. 146
4.6.3 ADC Test Control Register (ADCTSTCTRL) ............................................................. 147
4.6.4 ADC Sequence Select Register 0 (ADCSEQSEL0) .................................................. 147
4.6.5 ADC Sequence Select Register 1 (ADCSEQSEL1) .................................................. 148
4.6.6 ADC Sequence Select Register 2 (ADCSEQSEL2) .................................................. 149
4.6.7 ADC Sequence Select Register 3 (ADCSEQSEL3) .................................................. 151
4.6.8 ADC Result Registers 0-15 (ADCRESULTx, x=0:15) ................................................ 153
4.6.9 ADC Averaged Result Registers 0-5 (ADCAVGRESULTx, x=0:15) .......................... 153
4.6.10 ADC Digital Compare Limits Register 0-5 (ADCCOMPLIMx, x=0:5) ......................... 154
4.6.11 ADC Digital Compare Enable Register (ADCCOMPEN) ........................................... 155
4.6.12 ADC Digital Compare Results Register (ADCCOMPRESULT) ................................. 158
4.6.13 ADC Averaging Control Register (ADCAVGCTRL) ................................................... 162
4.7 DPWM 0-3 Registers ............................................................................................................. 164
4.7.1 DPWM Control Register 0 (DPWMCTRL0) ............................................................... 164
4.7.2 DPWM Control Register 1 (DPWMCTRL1) ............................................................... 168
4.7.3 DPWM Control Register 2 (DPWMCTRL2) ............................................................... 172
4.7.4 DPWM Period Register (DPWMPRD) ....................................................................... 174
4.7.5 DPWM Event 1 Register (DPWMEV1) ...................................................................... 174
4.7.6 DPWM Event 2 Register (DPWMEV2) ...................................................................... 175
4.7.7 DPWM Event 4 Register (DPWMEV4) ...................................................................... 176
4.7.8 DPWM Sample Trigger 1 Register (DPWMSAMPTRIG1) ......................................... 176
4.7.9 DPWM Sample Trigger 2 Register (DPWMSAMPTRIG2) ......................................... 177
4.7.10 DPWM Phase Trigger Register (DPWMPHASETRIG) .............................................. 177
4.7.11 DPWM Cycle Adjust A Register (DPWMCYCADJA) ................................................. 178
4.7.12 DPWM Cycle Adjust B Register (DPWMCYCADJB) ................................................. 178
4.7.13 179
4.7.14 DPWM Fault Control Register (DPWMFLTCTRL) ..................................................... 179
4.7.15 DPWM Overflow Register (DPWMOVERFLOW) ...................................................... 180
4.7.16 DPWM Flags/Interrupt Register (DPWMINT) ............................................................ 182
4.7.17 DPWM Counter Preset Register (DPWMCNTPRE) .................................................. 185
4.7.18 DPWM Blanking A Begin Register (DPWMBLKABEG) ............................................. 185
4.7.19 DPWM Blanking A End Register (DPWMBLKAEND) ................................................ 185
4.7.20 DPWM Blanking B Begin Register (DPWMBLKBBEG) ............................................. 187
4.7.21 DPWM Blanking B End Register (DPWMBLKBEND) ................................................ 187
4.7.22 DPWM Minimum Duty Cycle High Register (DPWMMINDUTYHI) ............................ 187
4.7.23 DPWM Minimum Duty Cycle Low Register (DPWMMINDUTYLO) ........................... 189
4.7.24 DPWM Adaptive Sample Register (DPWMADAPTIVE) ............................................ 189
4.7.25 DPWM Fault Status (DPWMFLTSTAT) ..................................................................... 189
4.7.26 DPWM Auto Switch High Upper Thresh Register
(DPWMAUTOSWHIUPTHRESH) .............................................................................. 190
4.7.27 DPWM Auto Switch High Lower Thresh Register
(DPWMAUTOSWHILOWTHRESH)........................................................................... 191
4.7.28 DPWM Auto Switch Low Upper Thresh Register
(DPWMAUTOSWLOUPTHRESH)............................................................................. 191
4.7.29 DPWM Auto Switch Low Lower Thresh Register
(DPWMAUTOSWLOLOWTHRESH) ......................................................................... 192
4.7.30 DPWM Auto Config Max Register (DPWMAUTOMAX) ............................................. 193
4.7.31 DPWM Auto Config Mid Register (DPWMAUTOMID) ............................................... 195
4.7.32 DPWM Edge PWM Generation Control Register (DPWMEDGEGEN)...................... 197
4.7.33 DPWM Filter Duty Read Register (DPWMFILTERDUTYREAD) ............................... 199
Application Report
SLUA766 – November 2015
4.7.34 DPWM CBC Location Register (DPWMCBCLOCATION) ...................................... 199
4.8 Filter Registers ...................................................................................................................... 201
4.8.1 Filter Status Register (FILTERSTATUS) ................................................................... 201
4.8.2 Filter Control Register (FILTERCTRL)....................................................................... 202
4.8.3 CPU XN Register (CPUXN) ....................................................................................... 203
4.8.4 Filter XN Read Register (FILTERXNREAD) .............................................................. 205
4.8.5 Filter KI_YN Read Register (FILTERKIYNREAD) ..................................................... 205
4.8.6 Filter KD_YN Read Register (FILTERKDYNREAD) .................................................. 205
4.8.7 Filter YN Read Register (FILTERYNREAD) .............................................................. 206
4.8.8 Coefficient Configuration Register (COEFCONFIG).................................................. 206
4.8.9 Filter KP Coefficient 0 Register (FILTERKPCOEF0) ................................................. 209
4.8.10 Filter KP Coefficient 1 Register (FILTERKPCOEF1) ................................................. 209
4.8.11 Filter KI Coefficient 0 Register (FILTERKICOEF0) .................................................... 210
4.8.12 Filter KI Coefficient 1 Register (FILTERKICOEF1) .................................................... 211
4.8.13 Filter KD Coefficient 0 Register (FILTERKDCOEF0)................................................. 211
4.8.14 Filter KD Coefficient 1 Register (FILTERKDCOEF1)................................................. 211
4.8.15 Filter KD Alpha Register (FILTERKDALPHA)............................................................ 213
4.8.16 Filter Nonlinear Limit Register 0 (FILTERNL0) .......................................................... 213
4.8.17 Filter Nonlinear Limit Register 1 (FILTERNL1) .......................................................... 213
4.8.18 Filter Nonlinear Limit Register 2 (FILTERNL2) .......................................................... 214
4.8.19 Filter KI Feedback Clamp High Register (FILTERKICLPHI)...................................... 214
4.8.20 Filter KI Feedback Clamp Low Register (FILTERKICLPLO) ..................................... 214
4.8.21 Filter YN Clamp High Register (FILTERYNCLPHI) ................................................... 216
4.8.22 Filter YN Clamp Low Register (FILTERYNCLPLO) ................................................... 216
4.8.23 Filter Output Clamp High Register (FILTEROCLPHI)................................................ 216
4.8.24 Filter Output Clamp Low Register (FILTEROCLPLO) ............................................... 217
4.8.25 Filter Preset Register (FILTERPRESET) ................................................................... 217
4.9 Front End Control Registers ..................................................................................................218
4.9.1 Ramp Control Register (RAMPCTRL) ....................................................................... 218
4.9.2 Ramp Status Register (RAMPSTAT)......................................................................... 221
4.9.3 Ramp Cycle Register (RAMPCYCLE) ....................................................................... 222
4.9.4 EADC DAC Value Register (EADCDAC)................................................................... 224
4.9.5 Ramp DAC Ending Value Register (RAMPDACEND) ............................................... 224
4.9.6 DAC Step Register (DACSTEP) ................................................................................ 224
4.9.7 DAC Saturation Step Register (DACSATSTEP)........................................................ 226
4.9.8 EADC Control Register (EADCCTRL) ....................................................................... 226
4.9.9 230
4.9.10 Pre-Bias Control Register 0 (PREBIASCTRL0)......................................................... 230
4.9.11 Pre-Bias Control Register 1 (PREBIASCTRL1)......................................................... 230
4.9.12 SAR Control Register (SARCTRL) ............................................................................ 231
4.9.13 SAR Timing Register (SARTIMING) .......................................................................... 232
4.9.14 EADC Value Register (EADCVALUE) ....................................................................... 232
4.9.15 EADC Raw Value Register (EADCRAWVALUE) ...................................................... 233
4.9.16 DAC Status Register (DACSTAT) ............................................................................. 233
4.10 Miscellaneous Analog Control ............................................................................................... 234
4.10.1 Package ID Register (PKGID) ................................................................................... 234
4.10.2 Brownout Register (BROWNOUT) ............................................................................ 234
4.10.3 Global I/O EN Register (GLBIOEN) ........................................................................... 236
Page 5 of 319
SLUA766 – November 2015
4.10.4 Global I/O OE Register (GLBIOOE) .......................................................................... 238
4.10.5 Global I/O Open Drain Control Register (GLBIOOD) ................................................ 240
4.10.6 Global I/O Value Register (GLBIOVAL) ..................................................................... 241
4.10.7 Global I/O Read Register (GLBIOREAD) .................................................................. 242
4.10.8 243
4.10.9 I/O Mux Control Register (IOMUX) ............................................................................ 243
4.10.10 Current Sharing Control Register (CSCTRL) ......................................................... 244
4.10.11 Temperature Reference Register (TEMPREF) ...................................................... 245
4.10.12 Power Disable Control Register (PWRDISCTRL).................................................. 246
4.10.13 DTC UART Pin Mux Select Register (DTCUARTSEL) .......................................... 248
4.11 PMBus Interface .................................................................................................................... 250
4.11.1 PMBUS Control Register 1 (PMBCTRL1) ................................................................. 250
4.11.2 PMBus Transmit Data Buffer (PMBTXBUF) .............................................................. 251
4.11.3 PMBus Receive Data Register (PMBRXBUF) ........................................................... 251
4.11.4 PMBus Acknowledge Register (PMBACK) ................................................................ 251
4.11.5 PMBus Status Register (PMBST) .............................................................................. 253
4.11.6 PMBus Interrupt Mask Register (PMBINTM) ............................................................. 255
4.11.7 PMBus Control Register 2 (PMBCTRL2)................................................................... 256
4.11.8 PMBus Hold Slave Address Register (PMBHSA)...................................................... 258
4.11.9 PMBus Control Register 3 (PMBCTRL3)................................................................... 259
4.12 GIO – General Purpose Input/Output Module ....................................................................... 263
4.12.1 Fault IO Direction Register (FAULTDIR) ................................................................... 263
4.12.2 Fault Input Register (FAULTIN) ................................................................................. 264
4.12.3 Fault Output Register (FAULTOUT) .......................................................................... 264
4.12.4 Fault Interrupt Enable Register (FAULTINTENA) ...................................................... 265
4.12.5 Fault Interrupt Polarity Register (FAULTINTPOL) ..................................................... 266
4.12.6 Fault Interrupt Pending Register (FAULTINTPEND) ................................................. 268
4.12.7 External Interrupt Direction Register (EXTINTDIR) ................................................... 270
4.12.8 External Interrupt Input Register (EXTINTIN) ............................................................ 270
4.12.9 External Interrupt Output Register (EXTINTOUT) ..................................................... 270
4.12.10 External Interrupt Enable Register (EXTINTENA) ................................................. 270
4.12.11 External Interrupt Polarity Register (EXTTINTPOL) .............................................. 271
4.12.12 External Interrupt Pending Register (EXTINTPEND)............................................. 271
4.13 Timer Module ........................................................................................................................ 272
4.13.1 24-bit Counter Data Register (T24CNTDAT) ............................................................. 272
4.13.2 24-bit Counter Control Register (T24CNTCTRL)....................................................... 272
4.13.3 24-bit Capture Channel Data Register (T24CAPDAT) .............................................. 274
4.13.4 24-bit Capture Channel Control Register (T24CAPCTRL) ........................................ 274
4.13.5 24-bit Capture I/O Control and Data Register (T24CAPIO) ....................................... 274
4.13.6 24-bit Output Compare Channel 0 Data Register (T24CMPDAT0) ........................... 275
4.13.7 24-bit Output Compare Channel 1 Data Register (T24CMPDAT1) ........................... 275
4.13.8 24-bit Output Compare Channel 0 Control Register (T24CMPCTRL0) ..................... 275
4.13.9 24-bit Output Compare Channel 1 Control Register (T24CMPCTRL1) ..................... 276
4.13.10 PWMx Counter Data Register (T16PWMxCNTDAT) ............................................. 276
4.13.11 PWMx Counter Control Register (T16PWMxCNTCTRL)....................................... 278
4.13.12 PWMx 16-bit Compare Channel 0-1 Data Register
(T16PWMxCMPyDAT) .............................................................................................. 279
4.13.13 PWM Compare Control Register (T16PWMxCMPCTRL) ...................................... 280
4.13.14 PWMx Compare Control Register (T16PWMxCMPCTRL) .................................... 281
4.13.15 Watchdog Status (WDST) ..................................................................................... 283
4.13.16 Watchdog Control (WDCTRL) ............................................................................... 283
Application Report
SLUA766 – November 2015
4.14 Memory Controller - MMC ..................................................................................................... 284
4.14.1 Static Memory Control Register (SMCTRL)............................................................... 285
4.14.2 Write Control Register (WCTRL) ............................................................................... 286
4.14.3 Peripheral Location Register (PLOC) ........................................................................ 287
4.14.4 Peripheral Protection Register (PPROT) ................................................................... 287
4.15 DEC – Address Manager ...................................................................................................... 288
4.15.1 Memory Fine Base Address High Register 0 (MFBAHR0) ........................................ 288
4.15.2 Memory Fine Base Address Low Register 0 (MFBALR0) ......................................... 289
4.15.3 Memory Fine Base Address High Register 1-3,17 (MFBAHRx) ................................ 290
4.15.4 Memory Fine Base Address Low Register 1-3,17(MFBALRx) .................................. 290
4.15.5 Memory Fine Base Address High Register 4 (MFBAHR4) ........................................ 291
4.15.6 Memory Fine Base Address Low Register 4-16 (MFBALRx) .................................... 291
4.15.7 Memory Fine Base Address High Register 5 (MFBAHR5) ........................................ 292
4.15.8 Memory Fine Base Address High Register 6 (MFBAHR6) ........................................ 293
4.15.9 Memory Fine Base Address High Register 7 (MFBAHR7) ........................................ 293
4.15.10 Memory Fine Base Address High Register 8 (MFBAHR8) .................................... 293
4.15.11 Memory Fine Base Address High Register 9 (MFBAHR9) .................................... 293
4.15.12 Memory Fine Base Address High Register 10 (MFBAHR10) ................................ 294
4.15.13 Memory Fine Base Address High Register 11 (MFBAHR11) ................................ 294
4.15.14 Memory Fine Base Address High Register 12 (MFBAHR12) ................................ 294
4.15.15 Memory Fine Base Address High Register 13 (MFBAHR13) ................................ 295
4.15.16 Memory Fine Base Address High Register 14 (MFBAHR14) ................................ 295
4.15.17 Memory Fine Base Address High Register 15 (MFBAHR15) ................................ 295
4.15.18 Memory Fine Base Address High Register 16 (MFBAHR16) ................................ 296
4.15.19 Program Flash Block 1 Control Register (PFLASHCTRL1) .................................. 296
4.15.20 Data Flash Control Register (DFLASHCTRL)........................................................ 297
4.15.21 Flash Interlock Register (FLASHILOCK) ............................................................... 297
4.15.22 Program Flash Block 2 Control Register (PFLASHCTRL2) ................................... 298
4.16 CIM – Central Interrupt Module ............................................................................................. 298
4.16.1 IRQ Index Offset Vector Register (IRQIVEC) ............................................................ 299
4.16.2 FIQ Index Offset Vector Register (FIQIVEC) ............................................................. 299
4.16.3 FIQ/IRQ Program Control Register (FIRQPR)........................................................... 300
4.16.4 Pending Interrupt Read Location Register (INTREQ)................................................ 304
4.16.5 Interrupt Mask Register (REQMASK) ........................................................................ 308
4.17 SYS – System Module ..........................................................................................................312
4.17.1 Clock Control Register (CLKCNTL) ........................................................................... 312
4.17.2 System Exception Control Register (SYSECR) ......................................................... 313
4.17.3 System Exception Status Register (SYSESR) .......................................................... 313
4.17.4 Abort Exception Status Register (ABRTESR) ........................................................... 316
4.17.5 Global Status Register (GLBSTAT) ........................................................................... 317
4.17.6 Device Identification Register (DEV) ......................................................................... 318
4.17.7 System Software Interrupt Flag Register (SSIF) ....................................................... 318
4.17.8 System Software Interrupt Request Register (SSIR)................................................. 319
Figure 1.
Figure 2.
Figure 1.
Figures
UCD3138064 Block diagram .............................................................................................. 9
UCD3138064A Block diagram ........................................................................................... 9
DTC Waveforms ................................................................................................................10
Page 7 of 319
SLUA766 – November 2015
Figure 2.
Figure 3.
Low Side Gate Driver with Body Diode Conduction Sensing ...................................... 11
UART Enhancements ....................................................................................................... 12
Table 1.
Table 2.
Table 3.
Table 4.
Table 5.
Tables
New Features in UCD3138064A ........................................................................................ 9
Enhancements in UCD3138064A .................................................................................... 12
UCD3138064ARGC Package ........................................................................................... 15
UCD3138064ARMH Package ........................................................................................... 15
Chip Revision ID field updated ....................................................................................... 16
1
Introduction
The UCD3138064A device is newest member of UCD3138 integrated digital power controller
platform family. In addition, to existing features form UCD3138064, this device also includes
following enhancements
Features:
 The General Purpose ADC has been improved for better accuracy and performance at
extreme cold temperatures (-40C)
 The UART peripheral has been modified to include a hardware based auto-baud rate
adjustment feature
 A new, Synchronous Rectifier Dead Time Optimization hardware peripheral has been
added
 A Duty Cycle Read Function has been added to improve use in peak current mode
 PMBus/I2C peripherals can now operate up to 1MHz
Application Report
SLUA766 – November 2015
Loop MUX
EAP0
EAP1
PID Based
Filter 1
DPWM1
PID Based
Filter 2
DPWM2
3-AFE
Constant Power Constant
Current
EADC
2AFE
EAN2
2
X
DPWM1A
EAP1
DPWM1B
EAN1
Avg()
Digital Comparators
Ramp
EAP2
EAN2
EADC
2AFE
2
3-AFE
A0
SYNC
Input Voltage Feed Forward
Value
Dither
Abs()
Peak Current Mode
Control Comparator
Peak Current Mode
Control Comparator
Advanced Power Control
Mode Switching, Burst Mode, IDE,
Synchronous Rectification soft on & off
Advanced Power Control
Mode Switching, Burst Mode, IDE,
Synchronous Rectification soft on & off
PMBUS_ALERT
ADC12 Control
Sequencing, Averaging,
Digital Compare, Dual
Sample and hold
ADC_EXT_TRIG
ADC12
PMBUS_CTRL
PMBus
PMBUS_DATA
AD[13:0]
ADC12
PMBUS_CLK
Internal Temperature
Sensor
Current Share
Analog, Average, Master/Slave
Oscillator
PMBUS_CTRL
PMBus
PMBUS_DATA
PMBUS_CLK
AD01
Internal Temperature
Sensor
PWM0
Timers
4 – 16 bit (PWM)
1 – 24 bit
PMBUS_ALERT
ADC12 Control
Sequencing, Averaging,
Digital Compare, Dual
Sample and hold
AD00
AD00
AD01
AD13
PWM1
AD02
AGND
TCAP
AD13
Current Share
Analog, Average, Master/Slave
PWM0
Timers
4 – 16 bit (PWM)
1 – 24 bit
Oscillator
ARM7TDMI-S
32 bit, 31.25 MHz
Analog
Comparators
C
AD04
VREG
DGND
D
Fault MUX &
Control
E
Cycle by Cycle
Current Limit
AD13
Power and
1.8 V Voltage
Regulator
AD06
Power On Reset
FAULT1
FAULT3
/RESET
Brown Out Detection
JTAG
AGND
SCI_RX0
UART1
SCI_RX1
EXT_INT
FAULT0
PFLASH 64 kB
C
AD04
FAULT2
G
V33A
B
FAULT0
GPIO
Control
TCAP
UART0
SCI_TX1
Memory
DFLASH 2 kB
RAM 4 kB
ROM 4 kB
A
AD03
EXT_INT
Digital
Comparators
F
AD07
ARM7TDMI-S
32 bit, 31.25 MHz
Analog
Comparators
AD02
SCI_RX1
Memory
PFLASH 64 kB
DFLASH 2 kB
RAM 4 kB
ROM 4 kB
B
V33DIO
SCI_RX0
SCI_TX1
AD03
V33D
UART0
UART1
A
D
V33D
AD13
V33DIO
TCK
VREG
TDI
DGND
TMS
V33A
TDO
AGND
Power and
1.8 V Voltage
Regulator
Bank 1
32kB
Fault MUX &
Control
GPIO
Control
Cycle by Cycle
Current Limit
F
Digital
Comparators
FAULT3
/RESET
Brown Out Detection
JTAG
G
TDI(DTC0)
DTC
TDO(DTC1)
SPI_MISO
SPI_MOSI
SPI_MOSI
SPI
SPI_CLK
SPI_CLK
SPI_CS
SPI_CS
I2C_DATA
I2C_DATA
2
Device Overview summary
2.1
New Features
Table 1.
I2C
I2C_CLK
UCD3138064 Block diagram
TCK
TMS
AD07
SPI
Figure 1.
FAULT1
FAULT2
Power On Reset
E
AD06
Bank 2
32kB
SPI_MISO
I2C
PWM1
SCI_TX0
SCI_TX0
AD02
DPWM3A
DPWM3B
CPCC
Abs()
AGND
DPWM2B
Filter x
Σ
Value
Dither
AD02
DPWM3
DPWM2A
Digital Comparators
Ramp
CPCC
AD[13:0]
Constant Power Constant
Current
DPWM1B
Avg()
SAR/Prebias
Filter x
Σ
DPWM2
Front End Averaging
X
DAC0
Input Voltage Feed Forward
DPWM1A
DPWM1
AFE
DPWM3
DPWM0B
PID Based
Filter 2
Front End 2
DPWM3A
DPWM0
PID Based
Filter 1
Front End 1
DPWM2A
DPWM3B
DPWM0A
PID Based
Filter 0
Front End 0
SYNC
SAR/Prebias
A0
EAP0
EAN0
DPWM2B
Front End Averaging
DAC0
DPWM0A
DPWM0B
DPWM0
Front End 2
AFE
Front End 1
EAN1
EAP2
Loop MUX
PID Based
Filter 0
Front End 0
EAN0
Figure 2.
I2C_CLK
UCD3138064A Block diagram
New Features in UCD3138064A
Peripheral Features/ Changes
DTC (new) Synchronous Rectifier Optimization
Algorithm with body diode
conduction time sensing
UART
UART enhancements
Detail Description
Addition of DTC pins for UCD7138 Synchronous Rectifier
Driver with Body Diode Conduction Time Reporting
UCD3138064: no auto baud rate adjustment
UCD3138064A: UART auto calibration to correct BAUD
Rate
2.1.1 Body diode conduction time sensing
Benefits:
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•
Maximize system efficiency by minimizing MOSFET body diode conduction time
•
Robust fast negative current protection.
•
Simple interface
•

Minimum component count

No external sense element

Easy layout
Superior to RDSon sensing techniques

Better accuracy across entire load range

No minimum on time requirement

No parasitic L & R concerns
UCD3138064A has an advanced dead time control interface where it can accept
UCD7138 output signals and optimize SR gate driver signals accordingly. The UCD7138
low-side MOSFET driver is a high performance driver for secondary-side synchronous
rectification (SR) with body diode conduction sensing. The device is suitable for high
power high efficiency isolated converter applications where dead-time optimization is
desired.
The UCD7138 gate driver is a companion device to UCD3138064A highly
integrated digital controller for isolated power. DTC0 and DTC1 are received body
diode conduction inputs from UCD7138. SR0_DPWM and SR1_DPWM are the
DPWM waveforms for the SRs. The yellow and green edges are moving edges
controlled by both the filter output and the DTC interface. In each cycle, right after
the falling edge of the SR DPWM waveform, a body diode conduction time
detection window is generated. The detection window is defined by both
DETECT_BLANK and DETECT_LEN registers. During this detection window, a 4ns timer capture counts how long the body diode conducts. Then the SR DPWM
turn off edge of the next cycle is adjusted accordingly.
SR0_DPWM
ADJUST
SR1_DPWM
DETECT
DETECT
ADJUST
DTC0
DETECT
DTC1
DETECT_BLANK
DETECT_LEN
* Note: DETECT_BLANK and DETECT_LEN starts 1MCLK (32ns) before the falling edge of SR0_DPWM or SR1_DPWM
Figure 1.
DTC Waveforms
DETECT
Application Report
SLUA766 – November 2015
UCD3138A
UCD7138
SR1 DPWM
IN
1
Connect to GND
or leave floating
6
CTRL
S
DPWM
module
DCT
2
Thermal Pad
(GND)
G
4
OUT
SR2 DPWM
VCC
4ns timer
capture and
dead time
control logic
1uF
3
5
D
VD
UCD7138
IN
1
DCT
2
1Ω
20Ω
Connect to GND
or leave floating
6
CTRL
S
DCT0
DCT
decoder
DCT1
VCC
3
Thermal Pad
(GND)
OUT
G
4
1Ω
5
VD
D
20Ω
1uF
Figure 2.
Low Side Gate Driver with Body Diode Conduction
Sensing
2.1.2 UART Auto Baud Enhacement
Benefits: The UCD3138064A has many UART enhancements. One of them is that it has
an in built hardware dedicated just to capture the receiving pulses on the Rx pin of the
UART. This along with some minimal firmware can be used to calculate the exact BAUD
rate of the other device.
Some of the other UART enhancements are:
1)
It has a finer resolution. The BAUD rate granularity is about 64 nS. Hence
a new register is introduced “UARTSBAUD”.
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2)
It has an auto sync on start bit . The free running counter of the UART
gets reset when it detects a start bit. This makes the sampling time well aligned
with the center of the pulses.
3)
It allows independent Rx and Tx BAUD rate capability. The UART Rx has some
new registers: UARTRXMBAUD, UARTRXLBAUD and UARTRXSBAUD. They have the
same meaning as the general UART registers: UARTMBAUD, UARTLBAUD and
UARTSBAUD.
UART Module
UART Registers
UARTMBAUD
UARTLBAUD
UARTSBAUD
RX_CAL_EN
RX_INDEP_BAUD_EN
Tx
UART Rx Capture Module
Rx
RX_CAL_CONT_EN
RX_CAL_MODE_BIT_WIDTH
Figure 3.
UARTRXMBAUD
UARTRXLBAUD
UARTRXSBAUD
UART Enhancements
For more details please refer to App Note - Hardware based UART Auto BAUD
correction [SPRxxxx]
2.2
Bug Fix/ Enhancements
Table 2.
Enhancements in UCD3138064A
Peripheral Features/ Changes
Detail Description
ADC
Improved ADC INL accuracy at
cold temp ‐40C
DPWM
DPWMxB can be restarted on
the fly without resetting the
DPWM module.
IO
GPIO status during power up
and power down
UCD3138064: INL +/‐2.5 LSBs typical from 25°C to 125°C
UCD3138064A: INL +/‐ 4.5 LSBs max across temperature ‐
40°C to 125°C
UCD3138064: If DPWMxB is latched off by fault, the whole
DPWM module has to be re‐enabled.
UCD3138064A: Adds a control so the DPWMxB can be reset
without turning off the entire module
UCD3138064: DPWM outputs are low after reset. Other
GPIO pins are configured as inputs after reset. During power
up or power down, GPIO pins are in high impedance state;
DPWM pins output low.
UCD3138064A: DPWM outputs are low after reset. Other
GPIO pins are configured as inputs after reset. During power
Application Report
SLUA766 – November 2015
up or power down, all GPIO and DPWM pins output low.
DPWM
Larger Fault Counters
Front End
PCMC ‐Configurable APCM
Blanking in all FE's enables
flexibility to use any FE for
PCM.
CBC–Blanking time for CBC fault
and counter will not change
due to voltage spikes
DPWM
UCD3138064: 5 bits – counts up to 32 consecutive faults
before triggering shutdown
UCD3138064A: 7 bits –up to 128 consecutive faults before
triggering shutdown
UCD3138064: Only Front End2 can be used for PCM as this
supports configurable blanking.
UCD3138064A: Any Front end can be used for PCM as
Configurable blanking is supported on all Front End.
UCD3138064: CBC counter is active during blanking time
UCD3138064A: CBC Counter will not increment due to
voltage spikes
PMBus
High Clock Timeout Capability
UCD3138064: The UCD3138064 PMBus interface did not
properly report the “Clock High Detected” event.
UCD3138064A: In UCD3138064A , if the clock is high for more
than 50 msec in the middle of a message, the PMBus
interface will be reset and the CLOCK_HIGH_DETECTED bit
will be set.
PMBus
PMBus–Interface status after
Interrupted/Corrupted
Messages
ADC
ADC Sample & Hold buffer
Enable
ADC
ADC Stop mid‐sequence
capability for quick changes to
sequence
UCD3138064: No proper response after interrupted
messages or certain corrupted messages.
UCD3138064A: The PMBus interface will respond properly
after interrupted messages or certain corrupted messages.
UCD3138064: has to enable dual sample and hold function to
use the buffer.
UCD3138064A: Ability to buffer certain ADC inputs without
enabling dual sample and hold function
UCD3138064: ADC stops at end of conversion sequence.
UCD3138064A: ADC can stop after any conversion, even in
the middle of a sequence.
Oscillator
HFO Low Noise Filter disabled
PMBus
1 MHz support
Front end
PCMC Correct A0 offset
UCD3138064: HFO filter is enabled by default, needs to be
disabled in program
UCD3138064A: HFO filter disabled by default in the ROM
UCD3138064: 400kHz support
UCD3138064A: 1 MHz support
UCD3138064: 100mV offset in PCMC front end.
UCD3138064A: A0 offset is changed from 100mV to
30mVmax;
Less offset applied EAP;PCM response time is reduced;
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DAC
Enhanced DAC Dither on each
sample
DPWM
DPWM Interrupt
DPWM
LLC Fixed rate sampling
enabled, update window size
increases. Improved transient
response and regulation over
line and load variations for LLC
converter.
DPWM–Fault Turn Off & Burst
mode
DPWM
ROM
Add 0xEA check of PFLASH #2
UCD3138064: dithers once per period
UCD3138064A: adds option of dither once on each EADC
sample
UCD3138064: DPWM period interrupt is generated every
switching period at previous chip if DPWM is disabled.
UCD3138064A: it is disabled when DPWM disabled.
UCD3138064: DPWM has pulse extension if fixed rate
sampling is used. Filter sample rate must follow LLC
frequency.
UCD3138064A: Fixed rate sampling is safe, update window
increased from 72ns to 132 ns
UCD3138064: When Edgegen module is used, fault may not
be able to turn off all DPWMs.
UCD3138064A: In Edgegen applications, all faults will result in
DPWMs going low
The EA Check means we check the first byte of the flash for a
0xEA, a jump. This shows that it is programmed, probably with a
reset vector. If there’s no EA, we don’t even check for a checksum,
just go to ROM mode.
UCD3138064: Default this check was not enabled. Effect was
that we jumped to program mode if the flash was programmed to all
zeroes, since the checksum of zero at the end would be correct.
UCD3138064A: Default this check is enabled thus avoiding
above scenario.
ROM
Disallow flash execution if trim
data is invalid.
UCD3138064: we set a bit to flag that the trim data is incorrect, but
went to execution anyway without doing trim.
UCD3138064A: this prevents code execution from program flash &
goes back to ROM mode if trim is incorrect thus providing
additional robustness
Front End
PCMC–Duty cycle read
Ability to read duty cycle during PCMC or CBC.
Reset
Disable
Disabling the RESET Pin
Filter
Yn Consistent Read
Chip Level
Current consumption
Added capability to disable the RESET pin. This may be useful in
very noisy systems. Here is the code to disable the reset:
MiscAnalogRegs.CLKTRIM.bit.RESET_DISABLE = 1. Note that
the Reset Pin should no longer be tied to 3.3 Volts directly. A 220
ohm resistor should now be used.
UCD3138064: although YN value is always correct, YN_READ
register may read back wrong values occasionally.
UCD3138064A: YN_READ register always have consistent read
value.
Please refer to electrical specification of UCD3138064A datasheet.
[SLUSCA5]
Event
Resonant mode dead times are
determined only by Event 1
UCD3138064: Dead time is programmed by all 4 Event registers.
Dead Time 1 = Event 3 – Event 2
Dead Time 2 = Event 1 + Period Register – Event 4
Average Dead Time = (Dead Time 1 + Dead Time 2)/2
DPWM A Rising Edge = Event 1
DPWM A Falling Edge = Event 1 + Filter Duty – Average Dead
Time
Application Report
SLUA766 – November 2015
Adaptive Sample Trigger A = Event 1 + Filter Duty + Adaptive
Sample Register
Adaptive Sample Trigger B = Event 1 + Filter Duty/2 + Adaptive
Sample Register
DPWM B Rising Edge = Event 1 + Filter Duty – Average Dead
Time + (Event 3 – Event 2)
DPWM B Falling Edge = Filter Period – (Period Register – Event 4)
Phase Trigger = Phase Trigger Register value or Filter Duty
UCD3138064A: Dead times are determined only be Event 1 register
value.
DPWM A Rising Edge = Event 1
DPWM A Falling Edge = Filter Duty – Event 1 + DTC Adjustment
Adaptive Sample Trigger A = Event 1 + Filter Duty + Adaptive
Sample Register or
Adaptive Sample Trigger B = Event 1 + Filter Duty/2 + Adaptive
Sample Register
DPWM B Rising Edge = Filter Duty + Event 1
DPWM B Falling Edge = Filter Period – Event 1 + DTC Adjustment
Phase Trigger = Phase Trigger Register value or Filter Duty
SyncFET behavior
2.3
UCD3138064:
SYNCFET soft on starts with the rising edge in its final position,
and the falling edge moves out in time until it reaches its calculated
position; Soft off moves the falling edge towards the rising edge
UCD3138064A:
SYNCFET soft on starts with the falling edge in its calculated
position, and the rising edge moves forward in time until it reaches
its final position. Soft off moves the rising edge back towards the
falling edge.
Pinmultiplexing updates
This device is 100 % pin to pin backward compatible to UCD3138064. New DTC
pins are available and multiplexed behind JTAG pins.
Table 3.
Pin #
Name
15
16
26
37
38
39
PMBUS_CLK
PMBUS_DATA
SYNC
TCK
TDO
TDI
Primary
assignment
PMBUS_CLK
PMBUS_DATA
SYNC
TCK
TDO
TDI
Table 4.
Pin #
Name
21
22
TCK
TDO
UCD3138064ARGC Package
Primary
assignment
TCK
TDO
No 1
No 2
No 3
No 4
SCI_TX0
SCI_RX0
TCAP
TCAP
SCI_TX0
SCI_RX0
DTC0
DTC1
ADC_EXT_TRIG
SYNC
PMBUS_ALERT
PMBUS_CTRL
PWM0
PWM0
FAULT0
FAULT1
DTC1
DTC0
DTC1
DTC0
UCD3138064ARMH Package
No 1
No 2
No 3
No 4
TCAP
SCI_TX0
SYNC
PMBUS_ALERT
PWM0
FAULT0
DTC0
DTC1
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23
2.4
TDI
TDI
SCI_RX0
PMBUS_CTRL
FAULT1
DTC0
Revision update
Table 5.
Chip Revision ID field updated
Module
Features/ Changes
Chip
Level
Device ID/Revision Update
Detail Description
UCD3138064: Device ID is 0x447F & Rev: 0x____ &
Firmware: “UCD3138064V1”
UCD3138064A: Device ID is 0x947F & Rev: 0x447F &
Firmware: “UCD3138064A”
3
Application Migration care about
3.1
Change to Device ID
The TI GUIs designed for use with the UCD parts use a PMBus command called
DEVICE_ID to determine which device is being used. On the UCD3138064A, the
initial part of the DEVICE_ID string should change to “UCD3138064A”.
The string for the UCD3138064 is “UCD310064V1”
3.2
Possible Changes to Layout and Power Supply Filtering
The UCD3138064A has different sensitivity to EMI and power supply noise than
the UCD3138064. Designs that are marginal with the non-A may require changes
to board layout and filtering to work with the A version. See the datasheet and the
UCD3138 - Practical Design Guideline Application Note for more information.
The added features of the UCD3138A will require a bit more power consumption
for the chip, see the datasheet for details.
3.3
LLC Topology
1)
Remove the following code:
MiscAnalogRegs.CLKTRIM.bit.HFO_LN_FILTER_EN = 0;
2)
The event update window is increased to 132 ns. Make sure that the
moving edges are outside of the event update window.
UCD3138064A has DTC interface that works in conjunction with UCD7138, helps
improve reliability and efficiency and reduce development cycle. This peripheral is
disabled by default. Please refer to Application note [xxx] for more details on how
to program DTC.
3.4
PS- LLC Topology
Remove the following code:
Application Report
SLUA766 – November 2015
MiscAnalogRegs.CLKTRIM.bit.HFO_LN_FILTER_EN = 0;
2)
The event update window is increased to 132 ns. Make sure that the
moving edges are outside of the event update window.
UCD3138064A has DTC interface that works in conjunction with UCD7138, helps
improve reliability and efficiency and reduce development cycle. This peripheral is
disabled by default. Please refer to Application note [SPRxxx] for more details on
how to program DTC.
3.5
HSFB Topology
For voltage mode control, only events update window are necessary to be
adjusted. At normal mode, change DpwmxRegs.DPWMEV1.all = 480 or greater.
At multiple mode, EVT3 should be greater than 480ns.
For peak current mode control, the EVTs update windows follow the same criteria
as voltage mode control. Besides those changes, PCM blanking time should be
programmed by PCM_BLANK_EN bit. For example, to select DPWM0 blanking
time and DPWM1 blanking time, the below code should be used.
Dpwm0Regs.DPWMCTRL2.bit.BLANK_PCM_EN = 1;
Dpwm1Regs.DPWMCTRL2.bit.BLANK_PCM_EN = 1;
Delete the code MiscAnalogRegs.CLKTRIM.bit.HFO_LN_FILTER_EN = 0 to
improve high frequency clock accuracy.
UCD3138064A has DTC interface that works in conjunction with UCD7138, helps
improve reliability and efficiency and reduce development cycle. This peripheral is
disabled by default. Please refer to Application note [xxx] for more details on how
to program DTC.
The dead time initialization may need to be changed because the algorithm for
dead time calculation has changed. See Table 2 - Enhancements in
UCD3138064A
3.6
PSFB Topology
The required changes of events update window in the PSFB topology are the
same as the HSFB topology. In addition, few other changes are highlighted.
`First, EDGEGEN modules are used in PSFB topology, at burst mode or fault
condition, one of DPWMs aren’t turned off in UCD3138064 while all DPWMs are
turned off in UCD3138064A. This can affect power stage design. With
UCD3138064A, gate transformers can be used for driving primary side
MOSFETs.
Second, the blanking time windows are programmed by the below codes for each
half period.
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Dpwm2Regs.DPWMCTRL2.bit.BLANK_PCM_EN = 1;
Dpwm3Regs.DPWMCTRL2.bit.BLANK_PCM_EN = 1;
Third, at Peak Current mode control, the offset applied on EAP pin (EAP2 for
PWR027) is significantly reduced to less than 30mV. The offset voltage can be
removed if a small voltage step is acceptable.
Fourth, delete the code MiscAnalogRegs.CLKTRIM.bit.HFO_LN_FILTER_EN = 0,
which is needed any more;
The dead time initialization may need to be changed because the algorithm for
dead time calculation has changed. See Table 2 - Enhancements in
UCD3138064A
Some other enhancements are listed in the Table 2, such as DAC dithering,
reading duty cycle when CBC happens or PCM control, and so on.
3.7
PFC Topology
Please note following modifications are required to support UCD3138064A
•
Delete this code:
MiscAnalogRegs.CLKTRIM.bit.HFO_LN_FILTER_EN = 0;
•
The event update window is increased to 132 ns, so set:
DpwmxRegs.DPWMEV1.all = 480; //normal mode
And also set EVENT3 if in multi mode:
DpwmxRegs.DPWMEV3.all = 480;//multi mode
In addition to above changes please make sure if any of changes listed in Table 1
and/or Table 2 are applicable to you.
4
Memory Map for UCD3138064A
This section describes all the peripheral registers of the UCD3138064A. Registers and
bitfields highlighted in green have been changed from the UDC3138064.
4.1
Loop Mux Registers
4.1.1 Front End Control 0 Mux Register (FECTRL0MUX)
Address 00120000
Bit Number
Bit Name
Access
Default
13:12
NL_SEL
R/W
00
11
DPWM3_FRAME_SYNC_EN
R/W
0
Application Report
SLUA766 – November 2015
Bit Number
Bit Name
Access
Default
10
DPWM2_FRAME_SYNC_EN
R/W
0
9
DPWM1_FRAME_SYNC_EN
R/W
0
Bit Number
Bit Name
Access
Default
8
DPWM0_FRAME_SYNC_EN
R/W
0
7
DPWM3_B_TRIG_EN
R/W
0
6
DPWM2_B_TRIG_EN
R/W
0
Bit Number
Bit Name
Access
Default
5
DPWM1_B_TRIG_EN
R/W
0
4
DPWM0_B_TRIG_EN
R/W
0
3
DPWM3_A_TRIG_EN
R/W
0
Bit Number
Bit Name
Access
Default
2
DPWM2_A_TRIG_EN
R/W
0
1
DPWM1_A_TRIG_EN
R/W
0
0
DPWM0_A_TRIG_EN
R/W
0
Bits 13-12: NL_SEL – Configures source of Non-Linear (NL) comparison results
used in Automatic Gain Shifting
0 = Filter 0 NL Results used
1 = Filter 1 NL Results used
2 = Filter 2 NL Results used (Default)
Bit 11: DPWM3_FRAME_SYNC_EN – Enables DPWM Trigger from DPWM
3 Frame Sync to Front End Control
0 = DPWM 3 Frame Sync not routed to Front End Control (Default)
1 = DPWM 3 Frame Sync routed to Front End Control
Bit 10: DPWM2_FRAME_SYNC_EN – Enables DPWM Trigger from DPWM
2 Frame Sync to Front End Control
0 = DPWM 2 Frame Sync not routed to Front End Control (Default)
1 = DPWM 2 Frame Sync routed to Front End Control
Bit 9: DPWM1_FRAME_SYNC_EN – Enables DPWM Trigger from DPWM 1
Frame Sync to Front End Control
0 = DPWM 1 Frame Sync not routed to Front End Control (Default)
1 = DPWM 1 Frame Sync routed to Front End Control
Bit 8: DPWM0_FRAME_SYNC_EN – Enables DPWM Trigger from DPWM 0
Frame Sync to Front End Control
0 = DPWM 0 Frame Sync not routed to Front End Control (Default)
1 = DPWM 0 Frame Sync routed to Front End Control
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Bit 7: DPWM3_B_TRIG_EN – Enables DPWM Trigger from DPWM 3 PWMB to Front End Control
0 = DPWM 3 PWM-B trigger not routed to Front End Control (Default)
1 = DPWM 3 PWM-B trigger routed to Front End Control
Bit 6: DPWM2_B_TRIG_EN – Enables DPWM Trigger from DPWM 2 PWMB to Front End Control
0 = DPWM 2 PWM-B trigger not routed to Front End Control (Default)
1 = DPWM 2 PWM-B trigger routed to Front End Control
Bit 5: DPWM1_B_TRIG_EN – Enables DPWM Trigger from DPWM 1 PWMB to Front End Control
0 = DPWM 1 PWM-B trigger not routed to Front End Control (Default)
1 = DPWM 1 PWM-B trigger routed to Front End Control
Bit 4: DPWM0_B_TRIG_EN – Enables DPWM Trigger from DPWM 0 PWMB to Front End Control
0 = DPWM 0 PWM-B trigger not routed to Front End Control (Default)
1 = DPWM 0 PWM-B trigger routed to Front End Control
Bit 3: DPWM3_A_TRIG_EN – Enables DPWM Trigger from DPWM 3 PWMA to Front End Control
0 = DPWM 3 PWM-A trigger not routed to Front End Control (Default)
1 = DPWM 3 PWM-A trigger routed to Front End Control
Bit 2: DPWM2_A_TRIG_EN – Enables DPWM Trigger from DPWM 2 PWMB to Front End Control
0 = DPWM 2 PWM-A trigger not routed to Front End Control (Default)
1 = DPWM 2 PWM-A trigger routed to Front End Control
Bit 1: DPWM1_A_TRIG_EN – Enables DPWM Trigger from DPWM 1 PWMB to Front End Control
0 = DPWM 1 PWM-A trigger not routed to Front End Control (Default)
1 = DPWM 1 PWM-A trigger routed to Front End Control
Bit 0: DPWM0_A_TRIG_EN – Enables DPWM Trigger from DPWM 0 PWMB to Front End Control
0 = DPWM 0 PWM-A trigger not routed to Front End Control (Default)
1 = DPWM 0 PWM-A trigger routed to Front End Control
Application Report
SLUA766 – November 2015
4.1.2 Front End Control 1 Mux Register (FECTRL1MUX)
Address 00120004
Bit Number
Bit Name
Access
Default
13:12
NL_SEL
R/W
01
11
DPWM3_FRAME_SYNC_EN
R/W
0
Bit Number
Bit Name
Access
Default
10
DPWM2_FRAME_SYNC_EN
R/W
0
9
DPWM1_FRAME_SYNC_EN
R/W
0
Bit Number
Bit Name
Access
Default
8
DPWM0_FRAME_SYNC_EN
R/W
0
7
DPWM3_B_TRIG_EN
R/W
0
6
DPWM2_B_TRIG_EN
R/W
0
Bit Number
Bit Name
Access
Default
5
DPWM1_B_TRIG_EN
R/W
0
4
DPWM0_B_TRIG_EN
R/W
0
3
DPWM3_A_TRIG_EN
R/W
0
Bit Number
Bit Name
Access
Default
2
DPWM2_A_TRIG_EN
R/W
0
1
DPWM1_A_TRIG_EN
R/W
0
0
DPWM0_A_TRIG_EN
R/W
0
Bits 13-12: NL_SEL – Configures source of Non-Linear (NL) comparison results
used in Automatic Gain Shifting
0 = Filter 0 NL Results used
1 = Filter 1 NL Results used
2 = Filter 2 NL Results used (Default)
Bit 11: DPWM3_FRAME_SYNC_EN – Enables DPWM Trigger from DPWM
3 Frame Sync to Front End Control
0 = DPWM 3 Frame Sync not routed to Front End Control (Default)
1 = DPWM 3 Frame Sync routed to Front End Control
Bit 10: DPWM2_FRAME_SYNC_EN – Enables DPWM Trigger from DPWM
2 Frame Sync to Front End Control
0 = DPWM 2 Frame Sync not routed to Front End Control (Default)
1 = DPWM 2 Frame Sync routed to Front End Control
Bit 9: DPWM1_FRAME_SYNC_EN – Enables DPWM Trigger from DPWM 1
Frame Sync to Front End Control
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SLUA766 – November 2015
0 = DPWM 1 Frame Sync not routed to Front End Control (Default)
1 = DPWM 1 Frame Sync routed to Front End Control
Bit 8: DPWM0_FRAME_SYNC_EN – Enables DPWM Trigger from DPWM 0
Frame Sync to Front End Control
0 = DPWM 0 Frame Sync not routed to Front End Control (Default)
1 = DPWM 0 Frame Sync routed to Front End Control
Bit 7: DPWM3_B_TRIG_EN – Enables DPWM Trigger from DPWM 3 PWMB to Front End Control
0 = DPWM 3 PWM-B trigger not routed to Front End Control (Default)
1 = DPWM 3 PWM-B trigger routed to Front End Control
Bit 6: DPWM2_B_TRIG_EN – Enables DPWM Trigger from DPWM 2 PWMB to Front End Control
0 = DPWM 2 PWM-B trigger not routed to Front End Control (Default)
1 = DPWM 2 PWM-B trigger routed to Front End Control
Bit 5: DPWM1_B_TRIG_EN – Enables DPWM Trigger from DPWM 1 PWMB to Front End Control
0 = DPWM 1 PWM-B trigger not routed to Front End Control (Default)
1 = DPWM 1 PWM-B trigger routed to Front End Control
Bit 4: DPWM0_B_TRIG_EN – Enables DPWM Trigger from DPWM 0 PWMB to Front End Control
0 = DPWM 0 PWM-B trigger not routed to Front End Control (Default)
1 = DPWM 0 PWM-B trigger routed to Front End Control
Bit 3: DPWM3_A_TRIG_EN – Enables DPWM Trigger from DPWM 3 PWMA to Front End Control
0 = DPWM 3 PWM-A trigger not routed to Front End Control (Default)
1 = DPWM 3 PWM-A trigger routed to Front End Control
Bit 2: DPWM2_A_TRIG_EN – Enables DPWM Trigger from DPWM 2 PWMB to Front End Control
0 = DPWM 2 PWM-A trigger not routed to Front End Control (Default)
1 = DPWM 2 PWM-A trigger routed to Front End Control
Bit 1: DPWM1_A_TRIG_EN – Enables DPWM Trigger from DPWM 1 PWMB to Front End Control
0 = DPWM 1 PWM-A trigger not routed to Front End Control (Default)
1 = DPWM 1 PWM-A trigger routed to Front End Control
Bit 0: DPWM0_A_TRIG_EN – Enables DPWM Trigger from DPWM 0 PWMB to Front End Control
0 = DPWM 0 PWM-A trigger not routed to Front End Control (Default)
1 = DPWM 0 PWM-A trigger routed to Front End Control
Application Report
SLUA766 – November 2015
4.1.3 Front End Control 2 Mux Register (FECTRL2MUX)
Address 00120008
Bit Number
Bit Name
Access
Default
13:12
NL_SEL
R/W
10
11
DPWM3_FRAME_SYNC_EN
R/W
0
Bit Number
Bit Name
Access
Default
10
DPWM2_FRAME_SYNC_EN
R/W
0
9
DPWM1_FRAME_SYNC_EN
R/W
0
Bit Number
Bit Name
Access
Default
8
DPWM0_FRAME_SYNC_EN
R/W
0
7
DPWM3_B_TRIG_EN
R/W
0
6
DPWM2_B_TRIG_EN
R/W
0
Bit Number
Bit Name
Access
Default
5
DPWM1_B_TRIG_EN
R/W
0
4
DPWM0_B_TRIG_EN
R/W
0
3
DPWM3_A_TRIG_EN
R/W
0
Bit Number
Bit Name
Access
Default
2
DPWM2_A_TRIG_EN
R/W
0
1
DPWM1_A_TRIG_EN
R/W
0
0
DPWM0_A_TRIG_EN
R/W
0
Bits 13-12: NL_SEL – Configures source of Non-Linear (NL) comparison results
used in Automatic Gain Shifting
0 = Filter 0 NL Results used
1 = Filter 1 NL Results used
2 = Filter 2 NL Results used (Default)
Bit 11: DPWM3_FRAME_SYNC_EN – Enables DPWM Trigger from DPWM
3 Frame Sync to Front End Control
0 = DPWM 3 Frame Sync not routed to Front End Control (Default)
1 = DPWM 3 Frame Sync routed to Front End Control
Bit 10: DPWM2_FRAME_SYNC_EN – Enables DPWM Trigger from DPWM
2 Frame Sync to Front End Control
0 = DPWM 2 Frame Sync not routed to Front End Control (Default)
1 = DPWM 2 Frame Sync routed to Front End Control
Bit 9: DPWM1_FRAME_SYNC_EN – Enables DPWM Trigger from DPWM 1
Frame Sync to Front End Control
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0 = DPWM 1 Frame Sync not routed to Front End Control (Default)
1 = DPWM 1 Frame Sync routed to Front End Control
Bit 8: DPWM0_FRAME_SYNC_EN – Enables DPWM Trigger from DPWM 0
Frame Sync to Front End Control
0 = DPWM 0 Frame Sync not routed to Front End Control (Default)
1 = DPWM 0 Frame Sync routed to Front End Control
Bit 7: DPWM3_B_TRIG_EN – Enables DPWM Trigger from DPWM 3 PWMB to Front End Control
0 = DPWM 3 PWM-B trigger not routed to Front End Control (Default)
1 = DPWM 3 PWM-B trigger routed to Front End Control
Bit 6: DPWM2_B_TRIG_EN – Enables DPWM Trigger from DPWM 2 PWMB to Front End Control
0 = DPWM 2 PWM-B trigger not routed to Front End Control (Default)
1 = DPWM 2 PWM-B trigger routed to Front End Control
Bit 5: DPWM1_B_TRIG_EN – Enables DPWM Trigger from DPWM 1 PWMB to Front End Control
0 = DPWM 1 PWM-B trigger not routed to Front End Control (Default)
1 = DPWM 1 PWM-B trigger routed to Front End Control
Bit 4: DPWM0_B_TRIG_EN – Enables DPWM Trigger from DPWM 0 PWMB to Front End Control
0 = DPWM 0 PWM-B trigger not routed to Front End Control (Default)
1 = DPWM 0 PWM-B trigger routed to Front End Control
Bit 3: DPWM3_A_TRIG_EN – Enables DPWM Trigger from DPWM 3 PWMA to Front End Control
0 = DPWM 3 PWM-A trigger not routed to Front End Control (Default)
1 = DPWM 3 PWM-A trigger routed to Front End Control
Bit 2: DPWM2_A_TRIG_EN – Enables DPWM Trigger from DPWM 2 PWMB to Front End Control
0 = DPWM 2 PWM-A trigger not routed to Front End Control (Default)
1 = DPWM 2 PWM-A trigger routed to Front End Control
Bit 1: DPWM1_A_TRIG_EN – Enables DPWM Trigger from DPWM 1 PWMB to Front End Control
0 = DPWM 1 PWM-A trigger not routed to Front End Control (Default)
1 = DPWM 1 PWM-A trigger routed to Front End Control
Bit 0: DPWM0_A_TRIG_EN – Enables DPWM Trigger from DPWM 0 PWMB to Front End Control
0 = DPWM 0 PWM-A trigger not routed to Front End Control (Default)
1 = DPWM 0 PWM-A trigger routed to Front End Control
Application Report
SLUA766 – November 2015
4.1.4 Sample Trigger Control Register (SAMPTRIGCTRL)
Address 0012000C
Bit Number
Bit Name
Access
Default
11
FE2_TRIG_DPWM3_EN
R/W
0
10
FE2_TRIG_DPWM2_EN
R/W
0
9
FE2_TRIG_DPWM1_EN
R/W
0
Bit Number
Bit Name
Access
Default
8
FE2_TRIG_DPWM0_EN
R/W
0
7
FE1_TRIG_DPWM3_EN
R/W
0
6
FE1_TRIG_DPWM2_EN
R/W
0
Bit Number
Bit Name
Access
Default
5
FE1_TRIG_DPWM1_EN
R/W
0
4
FE1_TRIG_DPWM0_EN
R/W
0
3
FE0_TRIG_DPWM3_EN
R/W
0
Bit Number
Bit Name
Access
Default
2
FE0_TRIG_DPWM2_EN
R/W
0
1
FE0_TRIG_DPWM1_EN
R/W
0
0
FE0_TRIG_DPWM0_EN
R/W
0
Bit 11: FE2_TRIG_DPWM3_EN – Enables Sample Trigger from DPWM 3 to
Front End Control 2
0 = DPWM 3 Sample Trigger not routed to Front End Control 2 (Default)
1 = DPWM 3 Sample Trigger routed to Front End Control 2
Bit 10: FE2_TRIG_DPWM2_EN – Enables Sample Trigger from DPWM 2 to
Front End Control 2
0 = DPWM 2 Sample Trigger not routed to Front End Control 2 (Default)
1 = DPWM 2 Sample Trigger routed to Front End Control 2
Bit 9: FE2_TRIG_DPWM1_EN – Enables Sample Trigger from DPWM 1 to
Front End Control 2
0 = DPWM 1 Sample Trigger not routed to Front End Control 2 (Default)
1 = DPWM 1 Sample Trigger routed to Front End Control 2
Bit 8: FE2_TRIG_DPWM0_EN – Enables Sample Trigger from DPWM 0 to
Front End Control 2
0 = DPWM 0 Sample Trigger not routed to Front End Control 2 (Default)
1 = DPWM 0 Sample Trigger routed to Front End Control 2
Bit 7: FE1_TRIG_DPWM3_EN – Enables Sample Trigger from DPWM 3 to
Front End Control 1
0 = DPWM 3 Sample Trigger not routed to Front End Control 1 (Default)
1 = DPWM 3 Sample Trigger routed to Front End Control 1
Page 25 of 319
SLUA766 – November 2015
Bit 6: FE1_TRIG_DPWM2_EN – Enables Sample Trigger from DPWM 2 to
Front End Control 1
0 = DPWM 2 Sample Trigger not routed to Front End Control 1 (Default)
1 = DPWM 2 Sample Trigger routed to Front End Control 1
Bit 5: FE1_TRIG_DPWM1_EN – Enables Sample Trigger from DPWM 1 to
Front End Control 1
0 = DPWM 1 Sample Trigger not routed to Front End Control 1 (Default)
1 = DPWM 1 Sample Trigger routed to Front End Control 1
Bit 4: FE1_TRIG_DPWM0_EN – Enables Sample Trigger from DPWM 0 to
Front End Control 1
0 = DPWM 0 Sample Trigger not routed to Front End Control 1 (Default)
1 = DPWM 0 Sample Trigger routed to Front End Control 1
Bit 3: FE0_TRIG_DPWM3_EN – Enables Sample Trigger from DPWM 3 to
Front End Control 0
0 = DPWM 3 Sample Trigger not routed to Front End Control 0 (Default)
1 = DPWM 3 Sample Trigger routed to Front End Control 0
Bit 2: FE0_TRIG_DPWM2_EN – Enables Sample Trigger from DPWM 2 to
Front End Control 0
0 = DPWM 2 Sample Trigger not routed to Front End Control 0 (Default)
1 = DPWM 2 Sample Trigger routed to Front End Control 0
Bit 1: FE0_TRIG_DPWM1_EN – Enables Sample Trigger from DPWM 1 to
Front End Control 0
0 = DPWM 1 Sample Trigger not routed to Front End Control 0 (Default)
1 = DPWM 1 Sample Trigger routed to Front End Control 0
Bit 0: FE0_TRIG_DPWM0_EN – Enables Sample Trigger from DPWM 0 to
Front End Control 0
0 = DPWM 0 Sample Trigger not routed to Front End Control 0 (Default)
1 = DPWM 0 Sample Trigger routed to Front End Control 0
4.1.5 External DAC Control Register (EXTDACCTRL)
Address 00120010
Bit Number
Bit Name
Access
Default
26:24
DAC2_SEL
R/W
000
Bit Number
Bit Name
Access
Default
7:3
RESERVED
0_0000
23:19
RESERVED
0_0000
18:16
DAC1_SEL
R/W
000
2
EXT_DAC2_EN
R/W
0
15:11
RESERVED
0_0000
1
EXT_DAC1_EN
R/W
0
10:8
DAC0_SEL
R/W
000
0
EXT_DAC0_EN
R/W
0
Bits 26-24: DAC2_SEL – Configures DAC 2 setpoint in External DAC Mode
0 = DAC 0 Setpoint Selected (Default)
1 = DAC 1 Setpoint Selected
3 = Output of Constant Power Module Selected
4 = Filter 0 Output Selected
Application Report
SLUA766 – November 2015
5 = Filter 1 Output Selected
6 = Filter 2 Output Selected
Bits 23-19: RESERVED – Unused bits
Bits 18-16: DAC1_SEL – Configures DAC 1 setpoint in External DAC Mode
0 = DAC 0 Setpoint Selected (Default)
2 = DAC 2 Setpoint Selected
3 = Output of Constant Power Module Selected
4 = Filter 0 Output Selected
5 = Filter 1 Output Selected
6 = Filter 2 Output Selected
Bits 15-11: RESERVED – Unused bits
Bits 10-8: DAC0_SEL – Configures DAC 0 setpoint in External DAC Mode
1 = DAC 1 Setpoint Selected
2 = DAC 2 Setpoint Selected
3 = Output of Constant Power Module Selected
4 = Filter 0 Output Selected
5 = Filter 1 Output Selected
6 = Filter 2 Output Selected
Bits 7-3: RESERVED – Unused bits
Bit 2: EXT_DAC2_EN – External DAC 2 Mode Enable
0 = External DAC Mode disabled. DAC 2 setpoint driven from Front End
Control Module (Default)
1 = External DAC Mode enabled, DAC 2 setpoint driven by DAC2_SEL
configuration
Bit 1: EXT_DAC1_EN – External DAC 1 Mode Enable
0 = External DAC Mode disabled. DAC 1 setpoint driven from Front End
Control Module (Default)
1 = External DAC Mode enabled, DAC 1 setpoint driven by DAC1_SEL
configuration
Bit 0: EXT_DAC0_EN – External DAC 0 Mode Enable
0 = External DAC Mode disabled. DAC 0 setpoint driven from Front End
Control Module (Default)
1 = External DAC Mode enabled, DAC 0 setpoint driven by DAC0_SEL
configuration
Page 27 of 319
SLUA766 – November 2015
4.1.6 Filter Mux Register (FILTERMUX)
Address 00120014
Bit Number
Bit Name
Access
Default
29:28
FILTER2_KCOMP_SEL
R/W
00
Bit Number
Bit Name
Access
Default
23:19
RESERVED
R/W
0_0000
27:26
FILTER1_KCOMP_SEL
R/W
00
18
FILTER2_FFWD_SEL
R/W
0
25:24
FILTER0_KCOMP_SEL
R/W
00
17
FILTER1_FFWD_SEL
R/W
0
16
FILTER0_FFWD_SEL
R/W
0
Bit Number
Bit Name
Access
Default
15:14
RESERVED
R/W
00
13:12
FILTER2_PER_SEL
R/W
00
11:10
FILTER1_PER_SEL
R/W
00
9:8
FILTER0_PER_SEL
R/W
00
Bit Number
Bit Name
Access
Default
7:6
RESERVED
00
5:4
FILTER2_FE_SEL
R/W
10
3:2
FILTER1_FE_SEL
R/W
01
1:0
FILTER0_FE_SEL
R/W
00
Bits 29-28: FILTER2_KCOMP_SEL – Selects KComp value routed to Filter 2
Module
0 = KComp 0 Value Selected (Default)
1 = KComp 1 Value Selected
2 = KComp 2 Value Selected
Bits 27-26: FILTER1_KCOMP_SEL – Selects KComp value routed to Filter 1
Module
0 = KComp 0 Value Selected (Default)
1 = KComp 1 Value Selected
2 = KComp 2 Value Selected
Bits 25-24: FILTER0_KCOMP_SEL – Selects KComp value routed to Filter 0
Module
0 = KComp 0 Value Selected (Default)
1 = KComp 1 Value Selected
2 = KComp 2 Value Selected
Bits 23-19: RESERVED – Unused bits
Bit 18: FILTER2_FFWD_SEL – Configures Feedforward value routed to Filter
2 Module
0 = Filter 0 Output Selected (Default)
1 = Filter 1 Output Selected
Bit 17: FILTER1_FFWD_SEL – Configures Feedforward value routed to Filter
1 Module
0 = Filter 0 Output Selected (Default)
Application Report
SLUA766 – November 2015
1 = Filter 2 Output Selected
Bit 16: FILTER0_FFWD_SEL – Configures Feedforward value routed to Filter
0 Module
0 = Filter 1 Output Selected (Default)
1 = Filter 2 Output Selected
Bits 15-14: RESERVED – Unused bits
Bits 13-12: FILTER2_PER_SEL – Selects source of switching cycle period for
Filter 2 Module
0 = DPWM 0 Switching Period (Default)
1 = DPWM 1 Switching Period
2 = DPWM 2 Switching Period
3 = DPWM 3 Switching Period
Bits 11-10: FILTER1_PER_SEL – Selects source of switching cycle period for
Filter 1 Module
0 = DPWM 0 Switching Period (Default)
1 = DPWM 1 Switching Period
2 = DPWM 2 Switching Period
3 = DPWM 3 Switching Period
Bits 9-8: FILTER0_PER_SEL – Selects source of switching cycle period for
Filter 0 Module
0 = DPWM 0 Switching Period (Default)
1 = DPWM 1 Switching Period
2 = DPWM 2 Switching Period
3 = DPWM 3 Switching Period
Bits 7-6: RESERVED – Unused bits
Bits 5-4: FILTER2_FE_SEL – Selects which Front End Module provides data
for Filter 2 Module
0 = Front End Module 0 provides data to Filter
1 = Front End Module 1 provides data to Filter
2 = Front End Module 2 provides data to Filter (Default)
Bits 3-2: FILTER1_FE_SEL – Selects which Front End Module provides data
for Filter 1 Module
0 = Front End Module 0 provides data to Filter
1 = Front End Module 1 provides data to Filter (Default)
2 = Front End Module 2 provides data to Filter
Bits 1-0: FILTER0_FE_SEL – Selects which Front End Module provides data
for Filter 0 Module
0 = Front End Module 0 provides data to Filter (Default)
1 = Front End Module 1 provides data to Filter
2 = Front End Module 2 provides data to Filter
Page 29 of 319
SLUA766 – November 2015
4.1.7 Filter KComp A Register (FILTERKCOMPA)
Address 00120018
Bit Number
Bit Name
Access
Default
29:16
KCOMP1
R/W
00_0000_0000_0000
15:14
RESERVED
00
13:0
KCOMP0
R/W
00_0000_0111_1101
Bits 29-16: KCOMP1 – 14-bit value used in filter output calculations replacing
the DPWM switching period value
Bits 15-14: RESERVED – Unused bits
Bits 13-0: KCOMP0 – 14-bit value used in filter output calculations replacing
the DPWM switching period value
4.1.8 Filter KComp B Register (FILTERKCOMPB)
Address 0012001C
Bit Number
Bit Name
Access
Default
13:0
KCOMP2
R/W
00_0000_0000_0000
Bits 13-0: KCOMP2 – 14-bit value used in filter output calculations replacing
the DPWM switching period value
Application Report
SLUA766 – November 2015
4.1.9 DPWM Mux Register (DPWMMUX)
Address 00120020
Bit Number
Bit Name
Access
Default
31:30
DPWM3_SYNC_FET_SEL
R/W
00
29:28
DPWM2_SYNC_FET_SEL
R/W
00
Bit Number
Bit Name
Access
Default
27:26
DPWM1_SYNC_FET_SEL
R/W
00
25:24
DPWM0_SYNC_FET_SEL
R/W
00
Bit Number
Bit Name
Access
Default
23:20
RESERVED
0000
Bit Number
Bit Name
Access
Default
15:14
DPWM1_SYNC_SEL
R/W
00
Bit Number
Bit Name
Access
Default
8:6
DPWM2_FILTER_SEL
R/W
010
19:18
DPWM3_SYNC_SEL
R/W
00
13:12
DPWM0_SYNC_SEL
R/W
00
5:3
DPWM1_FILTER_SEL
R/W
001
17:16
DPWM2_SYNC_SEL
R/W
00
11:9
DPWM3_FILTER_SEL
R/W
010
2:0
DPWM0_FILTER_SEL
R/W
000
Bits 31-30: DPWM3_SYNC_FET_SEL – Selects Ramp source for DPWM3
PWM-B SyncFET soft on/off
0 = Front End 0 Ramp output selected (Default)
1 = Front End 1 Ramp output selected
2 = Front End 2 Ramp output selected
Bits 29-28: DPWM2_SYNC_FET_SEL – Selects Ramp source for DPWM2
PWM-B SyncFET soft on/off
0 = Front End 0 Ramp output selected (Default)
1 = Front End 1 Ramp output selected
2 = Front End 2 Ramp output selected
Bits 27-26: DPWM1_SYNC_FET_SEL – Selects Ramp source for DPWM1
PWM-B SyncFET soft on/off
0 = Front End 0 Ramp output selected (Default)
1 = Front End 1 Ramp output selected
2 = Front End 2 Ramp output selected
Page 31 of 319
SLUA766 – November 2015
Bits 25-24: DPWM0_SYNC_FET_SEL – Selects Ramp source for DPWM0
PWM-B SyncFET soft on/off
0 = Front End 0 Ramp output selected (Default)
1 = Front End 1 Ramp output selected
2 = Front End 2 Ramp output selected
Bits 23-20: RESERVED – Unused bits
Bits 19-18: DPWM3_SYNC_SEL – Selects Master Sync for DPWM 3 when
DPWM 3 configured in slave mode
0 = DPWM 0 Sync (Default)
1 = DPWM 1 Sync
2 = DPWM 2 Sync
3 = DPWM 3 Sync
Bits 17-16: DPWM2_SYNC_SEL – Selects Master Sync for DPWM 2 when
DPWM 2 configured in slave mode
0 = DPWM 0 Sync (Default)
1 = DPWM 1 Sync
2 = DPWM 2 Sync
3 = DPWM 3 Sync
Bits 15-14: DPWM1_SYNC_SEL – Selects Master Sync for DPWM 1 when
DPWM 1 configured in slave mode
0 = DPWM 0 Sync (Default)
1 = DPWM 1 Sync
2 = DPWM 2 Sync
3 = DPWM 3 Sync
Bits 13-12: DPWM0_SYNC_SEL – Selects Master Sync for DPWM 0 when
DPWM 0 configured in slave mode
0 = DPWM 0 Sync (Default)
1 = DPWM 1 Sync
2 = DPWM 2 Sync
3 = DPWM 3 Sync
Bits 11-9: DPWM3_FILTER_SEL – Selects source of duty cycle/resonant
period for DPWM Module 3
0 = Filter 0 Output Selected (Default)
1 = Filter 1 Output Selected
2 = Filter 2 Output Selected
3 = Constant Power Module Selected
4 = DPWM_ON_TIME value from Light Load Control Register
Bits 8-6: DPWM2_FILTER_SEL – Selects source of duty cycle/resonant period
for DPWM Module 2
0 = Filter 0 Output Selected (Default)
1 = Filter 1 Output Selected
2 = Filter 2 Output Selected
3 = Constant Power Module Selected
4 = DPWM_ON_TIME value from Light Load Control Register
Bits 5-3: DPWM1_FILTER_SEL – Selects source of duty cycle/resonant period
for DPWM Module 1
Application Report
SLUA766 – November 2015
0 = Filter 0 Output Selected (Default)
1 = Filter 1 Output Selected
2 = Filter 2 Output Selected
3 = Constant Power Module Selected
4 = DPWM_ON_TIME value from Light Load Control Register
Bits 2-0: DPWM0_FILTER_SEL – Selects source of duty cycle/resonant period
for DPWM Module 0
0 = Filter 0 Output Selected (Default)
1 = Filter 1 Output Selected
2 = Filter 2 Output Selected
3 = Constant Power Module Selected
4 = DPWM_ON_TIME value from Light Load Control Register
4.1.10 Constant Power Control Register (CPCTRL)
Address 00120024
Bit Number
Bit Name
Access
Default
16
CPCC_INT_EN
R/W
0
Bit Number
Bit Name
Access
Default
11:10
VLOOP_SEL
R/W
00
Bit Number
Bit Name
Access
Default
15
DAC_COMP_EN
R/W
0
9:8
CLOOP_SEL
R/W
00
2:1
CPCC_CONFIG
R/W
00
14
FW_DIVISOR_EN
R/W
0
7:5
THRESH_SEL
R/W
000
13
LOWER_COMP_EN
R/W
0
4:3
DIVISOR_SEL
R/W
00
0
CPCC_EN
R/W
0
Bit 16: CPCC_INT_EN – Constant Power/Constant Current Interrupt Enable
0 = Interrupt disabled on mode switches (Default)
1 = Interrupt enabled on mode switches
Bit 15: DAC_COMP_EN – Enables comparison of DAC Setpoint and quotient
of Max Power/Sense Current in Loop Switching Mode. Minimum of DAC
setpoint and calculated quotient sets voltage loop setpoint in Constant Voltage
and Constant Power modes
0 = Operating Mode controls Voltage Loop DAC Setpoint (Default)
1 = Minimum of DAC setpoint and calculated quotient used as Voltage
Loop DAC Setpoint
Bit 14: FW_DIVISOR_EN – Enables Firmware value for divisor in Constant
Power calculations
Page 33 of 319
SLUA766 – November 2015
0 = Divisor selected by DIVISOR_SEL (Bits 7:6) (Default)
1 = Divisor driven by Firmware Current Register
Bit 13: LOWER_COMP_EN – Enables output of lowest duty from current or
voltage loop when Constant Power/Constant Current module controls loop output
0 = Loop output controlled by mode selection, voltage loop selected in
constant voltage and constant power mode, current loop selected in
constant current mode (Default)
1 = Loop output controlled by lowest duty from voltage or current loops
Bit 12: VLOOP_FREEZE_EN – Enables freezing of Voltage Loop Integrator
when current loop selected in Loop Switching configuration
0 = Freezing of Voltage Loop Integrator disabled (Default)
1 = Freezing of Voltage Loop Integrator enabled
Bits 11-10: VLOOP_SEL – Configures voltage loop for loop switching mode
0 = Filter 0 Output Selected (Default)
1 = Filter 1 Output Selected
2 = Filter 2 Output Selected
Bits 9-8: CLOOP_SEL – Configures current loop for loop switching mode
0 = Filter 0 Output Selected (Default)
1 = Filter 1 Output Selected
2 = Filter 2 Output Selected
Bits 7-5: THRESH_SEL – Configures input threshold selected for use in
Constant Power comparison
0 = Filter 0 Output Selected (Default)
1 = Filter 1 Output Selected
2 = Filter 2 Output Selected
3 = Front End 0 Absolute Value Data Selected
4 = Front End 1 Absolute Value Data Selected
5 = Front End 2 Absolute Value Data Selected
Bits 4-3: DIVISOR_SEL – Configures value used for divisor in Constant Power
calculations
0 = Front End 0 Absolute Value Data Selected (Default)
1 = Front End 1 Absolute Value Data Selected
2 = Front End 2 Absolute Value Data Selected
Bit 2-1: CPCC_CONFIG – Controls Constant Power/Constant Current module
configuration
00 = Average Current Mode (Default)
01 = Constant Power Module controls selection of voltage/current loop
10 = Front End Switching Mode
11 = Reserved
Bit 0: CPCC_EN – Constant Power Constant/Current Module Enable
0 = Constant Power/Constant Current Module disabled (Default)
1 = Constant Power/Constant Current Module enabled
4.1.11 Constant Power Nominal Threshold Register (CPNOM)
Address 00120028
Bit Number
25:16
15:10
9:0
Application Report
SLUA766 – November 2015
Bit Name
Access
Default
NOM_CURRENT_UPPER
R/W
00_0000_0000
RESERVED
00_0000
NOM_CURRENT_LOWER
R/W
00_0000_0000
Bits 25-16: NOM_CURRENT_UPPER – Configures INOM value used in
Constant Power/Constant Current Calculations, when sensed value exceeds
NOM_CURRENT_UPPER in Constant Voltage mode, setpoint will switch to
Constant Power mode
Bits 15-10: RESERVED – Unused Bits
Bits 9-0: NOM_CURRENT_LOWER – Configures INOM value used in Constant
Power/Constant Current Calculations, when sensed value falls below
NOM_CURRENT_LOWER in Constant Power mode, setpoint will switch to
Constant Voltage mode
4.1.12 Constant Power Max Threshold Register (CPMAX)
Address 0012002C
Bit Number
Bit Name
Access
Default
25:16
MAX_CURRENT_UPPER
R/W
00_0000_0000
15:10
RESERVED
00_0000
9:0
MAX_CURRENT_LOWER
R/W
00_0000_0000
Bits 25-16: MAX_CURRENT_UPPER – Configures IMAX value used in
Constant Power/Constant Current Calculations, when sensed value exceeds
MAX_CURRENT_UPPER in Constant Power mode, setpoint will switch to Max
Current mode
Bits 15-10: RESERVED – Unused Bits
Bits 9-0: MAX_CURRENT_LOWER – Configures IMAX value used in Constant
Power/Constant Current Calculations, when sensed value falls below
MAX_CURRENT_LOWER in Max Current mode, setpoint will switch to
Constant Power mode
4.1.13 Constant Power Configuration Register (CPCONFIG)
Address 00120030
Bit Number
Bit Name
Access
Default
25:16
MAX_CURRENT
R/W
00_0000_0000
15:10
RESERVED
00_0000
9:0
NOM_VOLTAGE
R/W
00_0000_0000
Bits 25-16: MAX_CURRENT – Configures IMAX setpoint used in Constant
Power/Constant Current Calculations in Max Current mode
Bits 15-10: RESERVED – Unused Bits
Page 35 of 319
SLUA766 – November 2015
Bits 9-0: NOM_VOLTAGE – Configures VNOM setpoint used in Constant
Power/Constant Current Calculations in Constant Voltage mode (Loop Oring
configuration selected)
Application Report
SLUA766 – November 2015
4.1.14 Constant Power Max Power Register (CPMAXPWR)
Address 00120034
Bit Number
Bit Name
Access
Default
19:0
MAX_POWER
R/W
0000_0000_0000_0000_0000
Bits 19-0: MAX_POWER – Configures PMAX value used in Constant
Power/Constant Current calculations in Constant Power mode
4.1.15 Constant Power Integrator Threshold Register (CPINTTHRESH)
Address 00120038
Bit Number
Bit Name
Access
Default
23:0
INT_THRESH
R/W
0000_0000_0000_0000_0000
Bits 23-0: INT_THRESH – 24-bit signed value added to Current Loop Duty
value to determine when to freeze Current Loop Integrator
4.1.16 Constant Power Firmware Divisor Register (CPFWDIVISOR)
Address 0012003C
Bit Number
Bit Name
Access
Default
9:0
FW_DIVISOR
R/W
00_0000_0000
Bits 9-0: FW_DIVISOR– 10-bit value used in Constant Power calculation when
firmware value is selected in Bit 17 of Constant Power Control Register
Page 37 of 319
SLUA766 – November 2015
4.1.17 Constant Power Status Register (CPSTAT)
Address 00120040
Bit Number
Bit Name
Access
Default
8
CONSTANT_CUR
R
-
7
CONSTANT_PWR
R
-
6
CONSTANT_VOLT
R
-
Bit Number
Bit Name
Access
Default
5
CC_TO_CV_INT
R
-
4
CV_TO_CC_INT
R
-
3
CC_TO_CP_INT
R
-
Bit Number
Bit Name
Access
Default
2
CP_TO_CC_INT
R
-
1
CP_TO_CV_INT
R
-
0
CV_TO_CP_INT
R
-
Bit 8: CONSTANT_CUR – Constant Current Mode Indication
0 = Constant Current Mode not enabled
1 = Constant Current Mode enabled
Bit 7: CONSTANT_PWR – Constant Power Mode Indication
0 = Constant Power Mode not enabled
1 = Constant Power Mode enabled
Bit 6: CONSTANT_VOLT – Constant Voltage Mode Indication
0 = Constant Voltage Mode not enabled
1 = Constant Voltage Mode enabled
Bit 5: CC_TO_CV_INT – Constant Current Mode to Constant Voltage Mode
latched status, cleared on read
0 = No transition from Constant Current to Constant Voltage detected
1 = Transition from Constant Current to Constant Voltage detected
Bit 4: CV_TO_CC_INT – Constant Voltage Mode to Constant Current Mode
latched status, cleared on read
0 = No transition from Constant Voltage to Constant Current detected
1 = Transition from Constant Voltage to Constant Current detected
Bit 3: CC_TO_CP_INT – Constant Current Mode to Constant Power Mode
latched status, cleared on read
0 = No transition from Constant Current to Constant Power detected
1 = Transition from Constant Current to Constant Power detected
Bit 2: CP_TO_CC_INT – Constant Power Mode to Constant Current Mode
latched status, cleared on read
0 = No transition from Constant Power to Constant Current detected
1 = Transition from Constant Power to Constant Current detected
Bit 1: CP_TO_CV_INT – Constant Power Mode to Constant Voltage Mode
latched status, cleared on read
0 = No transition from Constant Power to Constant Voltage detected
Application Report
SLUA766 – November 2015
1 = Transition from Constant Power to Constant Voltage detected
Bit 0: CV_TO_CP_INT – Constant Voltage Mode to Constant Power Mode
latched status, cleared on read
0 = No transition from Constant Voltage to Constant Power detected
1 = Transition from Constant Voltage to Constant Power detected
4.1.18 Cycle Adjustment Control Register (CYCADJCTRL)
Address 00120044
Bit Number
Bit Name
Access
Default
Bit Number
Bit Name
Access
Default
9:7
CYC_ADJ_GAIN
R/W
000
4:3
SECOND_SAMPLE_SEL
R/W
00
6:5
CYC_ADJ_SYNC
R/W
00
2:1
FIRST_SAMPLE_SEL
R/W
00
0
CYC_ADJ_EN
R/W
0
Bits 9-7: CYC_ADJ_GAIN – Configures gain of Cycle Adjustment calculation
0 = 1x gain (Default)
1 = 2x gain
2 = 4x gain
3 = 8x gain
4 = 16x gain
5 = 32x gain
6 = 64x gain
7 = 128x gain
Bits 6-5: CYC_ADJ_SYNC – Selects which DPWM trigger synchronizes cycle
adjustment calculation, first 2 samples after receipt of DPWM trigger will be used
for Cycle Adjustment Calculation.
0 = DPWM-0 frame sync trigger selected (Default)
1 = DPWM-1 frame sync trigger selected
2 = DPWM-2 frame sync trigger selected
3 = DPWM-3 frame sync trigger selected
Bits 4-3: SECOND_SAMPLE_SEL – Configures Front End Module Data used
for Second Sample of Cycle Adjustment Calculation
0 = Front End Module 0 Error Data selected (Default)
1 = Front End Module 1 Error Data selected
2 = Front End Module 2 Error Data selected
Bits 2-1: FIRST_SAMPLE_SEL – Configures Front End Module Data used for
First Sample of Cycle Adjustment Calculation
0 = Front End Module 0 Error Data selected (Default)
1 = Front End Module 1 Error Data selected
2 = Front End Module 2 Error Data selected
Page 39 of 319
SLUA766 – November 2015
Bit 0: CYC_ADJ_EN – Cycle Adjustment Calculation Enable
0 = Cycle Adjustment Calculation disabled (Default)
1 = Cycle Adjustment Calculation enabled
4.1.19 Cycle Adjustment Limit Register (CYCADJLIM)
Address 00120048
Bit Number
Bit Name
Access
Default
28:16
CYC_ADJ_UPPER_LIMIT
R/W
0_0000_0000_0000
15:13
RESERVED
000
12:0
CYC_ADJ_LOWER_LIM
R/W
0_0000_0000_0000
Bits 28-16: CYC_ADJ_UPPER_LIMT – Cycle Adjustment Calculation signed
upper limit value, output of Cycle Adjustment Calculation is clamped at the upper
limit, if calculated result exceeds the upper limit. LSB resolution equals High
Frequency Oscillator period/16.
Bits 15-13: RESERVED – Unused Bits
Bits 12-0: CYC_ADJ_LOWER_LIMT – Cycle Adjustment Calculation signed
lower limit value, output of Cycle Adjustment Calculation is clamped at the lower
limit, if calculated result falls below the lower limit. LSB resolution equals High
Frequency Oscillator period/16.
4.1.20 Cycle Adjustment Status Register (CYCADJSTAT)
Address 0012004C
Bit Number
Bit Name
Access
Default
28:16
CYC_ADJ_CALC
R
-
15:10
RESERVED
00_0000
9:0
CYC_ADJ_ERROR
R
-
Bits 28-16: CYC_ADJ_CALC – 13-bit signed value representing calculated
Cycle Adjustment provided to DPWM module based on first 2 error samples
Bits 15-10: RESERVED – Unused Bits
Bits 9-0: CYC_ADJ_ERROR – 10-bit signed value representing calculated error
of the first 2 error samples received
Application Report
SLUA766 – November 2015
4.1.21 Global Enable Register (GLBEN)
Address 00120050
Bit Number
Bit Name
Access
Default
10
FE_CTRL2_EN
R/W
0
Bit Number
Bit Name
Access
Default
3
DPWM3_EN
R/W
0
9
FE_CTRL1_EN
R/W
0
8
FE_CTRL0_EN
R/W
0
7:4
RESERVED
0000
2
DPWM2_EN
R/W
0
1
DPWM1_EN
R/W
0
0
DPWM0_EN
R/W
0
Bit 10: FE_CTRL2_EN – Global Firmware Enable for Front End Control 2
Module
0 = Front End Control 2 Module Disabled (Default)
1 = Front End Control 2 Module Enabled
Bit 9: FE_CTRL1_EN – Global Firmware Enable for Front End Control 1
Module
0 = Front End Control 1 Module Disabled (Default)
1 = Front End Control 1 Module Enabled
Bit 8: FE_CTRL0_EN – Global Firmware Enable for Front End Control 0
Module
0 = Front End Control 0 Module Disabled (Default)
1 = Front End Control 0 Module Enabled
Bits 7-4: RESERVED – Unused Bits
Bit 3: DPWM3_EN – Global Firmware Enable for DPWM 3 Module
0 = DPWM 3 Module Disabled (Default)
1 = DPWM 3 Module Enabled
Bit 2: DPWM2_EN – Global Firmware Enable for DPWM 2 Module
0 = DPWM 2 Module Disabled (Default)
1 = DPWM 2 Module Enabled
Bit 1: DPWM1_EN – Global Firmware Enable for DPWM 1 Module
0 = DPWM 1 Module Disabled (Default)
1 = DPWM 1 Module Enabled
Bit 0: DPWM0_EN – Global Firmware Enable for DPWM 0 Module
0 = DPWM 0 Module Disabled (Default)
1 = DPWM 0 Module Enabled
Page 41 of 319
SLUA766 – November 2015
4.1.22 PWM Global Period Register (PWMGLBPRD)
Address 00120054
Bit Number
Bit Name
Access
Default
17:4
PRD
R/W
00_0000_0000_0000
3:0
RESERVED
0000
Bits 17-4: PRD – Global PWM Period value, overriding DPWM Period settings
when global PWM period is selected within each DPWM module
Bits 3-0: RESERVED – Unused Bits
4.1.23 Sync Control Register (SYNCCTRL)
Address 00120058
Bit Number
Bit Name
Access
Default
5
SYNC_IN
R
-
4:2
SYNC_MUX_SEL
R/W
000
1
SYNC_OUT
R/W
1
0
SYNC_DIR
R/W
1
Bit 5: SYNC_IN – Value of Sync pin
0 = Logic level low present on Sync pin
1 = Logic level high present on Sync pin
Bits 4-2: SYNC_MUX_SEL – Selects which module controls Sync pin output
000 = DPWM 0 Sync Output (Default)
001 = DPWM 1 Sync Output
010 = DPWM 2 Sync Output
011 = DPWM 3 Sync Output
100 = Value from SYNC_OUT (Bit 1)
101 = Value from CLKOUT signal (See Section 4.17.1)
110 = Low-Frequency Oscillator Clock Output
111 = Driven low
Bit 1: SYNC_OUT – Configure output value for Sync pin, if used as an output
0 = Sync pin driven low in output mode
1 = Sync pin driven high in output mode (Default)
Bit 0: SYNC_DIR – Configure direction of Sync pin
0 = Sync pin configured as an output pin
1 = Sync pin configured as an input pin (Default)
Application Report
SLUA766 – November 2015
4.1.24 Light Load Control Register (LLCTRL)
Address 0012005C
Bit Number
Bit Name
Access
Default
25:8
DPWM_ON_TIME
R/W
00_0000_0000_0000_0000
7:4
RESERVED
0000
3
CYCLE_CNT_EN
R/W
0
2:1
LL_FILTER_SEL
R/W
00
0
LL_EN
R/W
0
Bits 25-8: DPWM_ON_TIME – DPWM pulse width used for EADC-based light
load mode operation, when selected Filter data exceeds TURN_ON_THRESH
value
Bits 7-3: RESERVED – Unused Bits
Bit 3: CYCLE_CNT_EN – Enables Switching Cycle Counter for enabling
constant pulse widths when configured in Light Load operation
0 = Switching Cycle Counter disabled (Default)
1 = Switching Cycle Counter enabled
Bits 2-1: LL_FILTER_SEL – Configures source of filter data for Light Load
comparisons
0 = Filter 0 data selected (Default)
1 = Filter 1 data selected
2 = Filter 2 data selected
Bit 0: LL_EN – Light Load Mode Enable
0 = Mode disabled (Default)
1 = Mode enabled
4.1.25 Light Load Enable Threshold Register (LLENTHRESH)
Address 00120060
Bit Number
Bit Name
Access
Default
31:24
CYCLE_CNT_THRESH
R/W
0000_0000
23:18
RESERVED
0000_00
17:0
TURN_ON_THRESH
R/W
00_0000_0000_0000_0000
Bits 31-24: CYCLE_CNT_THRESH – Switching Cycle threshold where
constant width DPWM pulses are enabled when number of switching cycles
without pulses exceeds threshold
Bits 23-18: RESERVED – Unused Bits
Bits 17-0: TURN_ON_THRESH – Filter data threshold where constant width
DPWM pulses are enabled when filter data exceeds threshold
Page 43 of 319
SLUA766 – November 2015
4.1.26 Light Load Disable Threshold Register (LLDISTHRESH)
Address 00120064
Bit Number
Bit Name
Access
Default
17:0
TURN_OFF_THRESH
R/W
00_0000_0000_0000_0000
Bits 17-0: TURN_OFF_THRESH – Filter data threshold where constant width
DPWM pulses are disabled when filter data falls below threshold
4.1.27 Analog Peak Current Mode Ramp Register (APCMRAMP)
Address 00120068
Bit Number
Bit Name
Access
Default
5:4
PCM_FILTER_SEL
R/W
00
3:0
RESERVED
R
00
Bits 5-4: PCM_FILTER_SEL – Selects source of Peak Current Slope
Compensation Ramp Start
0 = Filter 0 data selected (Default)
1 = Filter 1 data selected
2 = Filter 2 data selected
3 = Constant Power/Constant Current data selected
Bits 3-0: Reserved
4.1.28 Analog Peak Current Mode Control Register (APCMCTRL)
Address 00120070
Bit Number
Bit Name
Access
Default
3
PCM_LATCH_EN
R/W
0
2:1
PCM_FE_SEL
R/W
00
0
PCM_EN
R/W
0
Bit 3: PCM_LATCH_EN – Enables latching of Peak Current Flag to end of
frame
0 = PCM Flag is not latched to end of PCM Frame (Default)
1 = PCM Flag is latched to end of PCM Frame
Bits 2-1: PCM_FE_SEL – Selects source of Front End Comparator output for
Analog Peak Current Mode Control
0 = Front End Control 0 Comparator output selected (Default)
1 = Front End Control 1 Comparator output selected
2 = Front End Control 2 Comparator output selected
Bit 0: PCM_EN – Analog Peak Current Mode Control Module Enable
0 = Analog Peak Current Mode Control Module disabled (Default)
Application Report
SLUA766 – November 2015
1 = Analog Peak Current Mode Control Module enabled
4.1.29 DTC Control (DTCCTRL)
Address 00120078
Bit Number
Bit Name
Access
Default
22
FLT_INT_EN
R/W
0
21:20
FLT_MAX
R/W
0
19:17
FLT_STEP
R/W
0
Bit Number
Bit Name
Access
Default
16:13
FLT_THRESH
R/W
0
12:9
PWM_A_SEL
R/W
0
8:5
PWM_B_SEL
R/W
0
4
A_POL
R/W
0
Bit Number
Bit Name
Access
Default
3
B_POL
R/W
0
1
MODE
R/W
0
0
DTC_EN
R/W
0
2
INPUT_ MODE
R/W
0
Bit 22: FLT_INT_EN– Enables interrupt generation when a fault flag condition
has been met
0 = Interrupt disabled (default)
1 = Interrupt enabled
Bit 21:20: FLT_MAX– Sets the number of consecutive detected faults before a
fault step is utilized
0 = 1 (default)
1=2
2=4
3=8
Bit 19-17: FLT_STEP– Sets the negative step size when a fault condition is
detected that exceeds the fault max value. If the fault_max condition has not been
met the step size is -1. Step size is in HFO clock increments.
0 = -1 (default)
1 = -5
2 = -10
3 = -25
4 = -50
5 = -75
6 = -100
7 = -125
Bit 16-13: FLT_THRESH– Sets the measurement threshold for a fault condition
to initiate a fault step. Threshold is in HFO clock increments.
Page 45 of 319
SLUA766 – November 2015
Bit 12-9 PWM_A_SEL – Selects the phase A negative edge reference to begin a
measurement window
0 = Disabled (Default)
1 = DPWM-0-A
2 = DPWM-1-A
3 = DPWM-2-A
4 = DPWM-3-A
5 = DPWM-0-B
6 = DPWM-1-B
7 = DPWM-2-B
8 = DPWM-3-B
Bit 8-5: PWM_B_SEL – Selects the phase B negative edge reference to begin a
measurement window
0 = Disabled (Default)
1 = DPWM-0-A
2 = DPWM-1-A
3 = DPWM-2-A
4 = DPWM-3-A
5 = DPWM-0-B
6 = DPWM-1-B
7 = DPWM-2-B
8 = DPWM-3-B
Bit 4: A_POL – Sets the signal polarity of the DTC input to the device
0 = Active Low (Default)
1 = Active High
Bit 3: B_POL – Sets the signal polarity of the DTC input to the device
0 = Active Low (Default)
1 = Active High
Bit 2: INPUT_MODE – Sets the input method for the DTC module
0 = Phase A and Phase B input signals occur on separate inputs (Default)
1 = Phase A and Phase B input signals occur on the same input
Bit 1: MODE – Sets mode control of the DTC phase accumulator values
0 = Automatic Mode. Accumulators A and B are changed by hardware
and stay within limits programmed in the DTCLIMIT register. (Default)
1 = Manual Mode. Accumulator A and B set by programmed values in the
DTCMANUAL register.
Bit 0: DTC_EN – DTC Enable
0 = Dead-time Compensate Module disabled (Default)
1 = Dead-time Compensate Module enabled
Application Report
SLUA766 – November 2015
4.1.30 DTC Target (DTCTARGET)
Address 0012007C
Bit Number
Bit Name
Access
Default
23:17
DETECT_BLANK
R/W
000_0000
16:9
DETECT_LEN
R/W
0000_0000
8:7
TARGET_OFFSET
R/W
00
6:0
TARGET_LOW
R/W
000_0000
Bit 23-17: DETECT_BLANK– Sets the target measurement window blanking
length, in HFO clock increments.
Bit 16-9: DETECT_LEN– Sets the target measurement window length, in HFO
clock increments.
Bit 8-7: TARGET_OFFSET– Target Threshold Offset. Target upper threshold
= target low + target offset
0 = 0 (Default)
1 = 2 HFO clocks
2 = 4 HFO clocks
3 = 8 HFO clocks
Bit 6-0: TARGET_LOW – Target Lower Threshold, in HFO clock increments
4.1.31 DTC Auto Control Limit (DTCLIMIT)
Address 00120080
Bit Number
Bit Name
Access
Default
19:10
ADJ_MAX
R/W
01_1111_1111
9:0
ADJ_MIN
R/W
10_0000_0000
Bit 19-10: ADJ_MAX – Sets the signed integer upper clamp for the
accumulators. The integer range is (-512 to 511)
Bit 9-0: ADJ_MIN – Sets the signed integer lower clamp for the accumulators.
The integer range is (-512 to 511)
4.1.32 DTC Manual Control (DTCMANUAL)
Address 00120084
Bit Number
Bit Name
Access
Default
19:10
A_ADJ
R/W
00_0000_0000
9:0
B_ADJ
R/W
00_0000_0000
Register is ignored in automatic mode.
Page 47 of 319
SLUA766 – November 2015
Bit 19-10: A_ADJ – Sets the signed A accumulator value when manual control is
enabled.
Bit 9-0: B_ADJ Sets the signed B accumulator value when manual control is
enabled.
4.1.33 DTC Monitor (DTCMONITOR)
Address 00120088
Bit Number
Bit Name
Access
Default
19:10
A_ADJ
R
0_0000_0000
9:0
B_ADJ
R
0_0000_0000
Bit 19-10: A_ADJ – Monitored accumulator A value from the DTC module
Bit 9-0: B_ADJ - Monitored accumulator B value from the DTC module
4.1.34 DTC Status (DTCSTAT)
Address 0012008C
Bit Number
Bit Name
Access
Default
14:8
A_CNT
R
000_0000
7:1
B_CNT
R
000_0000
0
FLAG
R
0
Bit 14-8: A_CNT – Last measurement value for phase A input signal
Bit 7-1: B_CNT – Last measurement value for phase B input signal
Bit 0: FLAG – Flag is set when the fault count exceeds the FLT MAX value
programmed in the DTCCTRL register.
SLUA766
4.2
Fault Mux Registers
4.2.1 Analog Comparator Control 0 Register (ACOMPCTRL0)
Address 00130000
Bit Number
Bit Name
Access
Default
30:24
ACOMP_B_THRESH
R/W
000_0000
23:22
RESERVED
00
21:19
ACOMP_B_SEL
R/W
000
18
ACOMP_B_POL
R/W
1
Bit Number
Bit Name
Access
Default
17
ACOMP_B_INT_EN
R/W
0
16:15
RESERVED
00
14:8
ACOMP_A_THRESH
R/W
000_0000
7:6
RESERVED
00
Bit Number
Bit Name
Access
Default
5:3
ACOMP_A_SEL
R/W
000
2
ACOMP_A_POL
R/W
1
1
ACOMP_A_INT_EN
R/W
0
0
ACOMP_EN
R/W
0
Bits 30-24: ACOMP_B_THRESH – Configures Analog Comparator B
Threshold value
0 = Comparator Reference of 19.53125 mV (Default)
1 = Comparator Reference of 39.0625 mV
……..
127 = Comparator Reference of 2.5 V
Bits 23-22: RESERVED – Unused bits
Bits 21-19: ACOMP_B_SEL – Configures Analog Comparator B Threshold
0 = Analog Comparator B Threshold set by ACOMP_B_THRESH
(Default)
1 = Analog Comparator B Threshold set by Comparator Ramp 0
2 = Analog Comparator B Threshold set by Filter 0 Output
3 = Analog Comparator B Threshold set by Filter 1 Output
4 = Analog Comparator B Threshold set by Filter 2 Output
Bit 18: ACOMP_B_POL – Analog Comparator B Polarity
0 = Comparator result enabled when input falls below threshold
1 = Comparator result enabled when input exceeds threshold (Default)
Bit 17: ACOMP_B_INT_EN – Analog Comparator B Interrupt Enable
0 = Disables Analog Comparator B Interrupt generation (Default)
UCD3138064A Migration Guide
49
SLUA766 – November 2015
1 = Enables Analog Comparator B Interrupt generation
Bits 16-15: RESERVED – Unused bits
Bits 14-8: ACOMP_A_THRESH – Configures Analog Comparator A Threshold
0 = Comparator Reference of 19.53125 mV (Default)
1 = Comparator Reference of 39.0625 mV
……..
127 = Comparator Reference of 2.5 V
Bits 7-6: RESERVED – Unused bits
Bits 5-3: ACOMP_A_SEL – Configures Analog Comparator A Threshold
0 = Analog Comparator A Threshold set by ACOMP_A_THRESH
(Default)
1 = Analog Comparator A Threshold set by Comparator Ramp 0
2 = Analog Comparator A Threshold set by Filter 0 Output
3 = Analog Comparator A Threshold set by Filter 1 Output
4 = Analog Comparator A Threshold set by Filter 2 Output
Bit 2: ACOMP_A_POL – Analog Comparator A Polarity
0 = Comparator result enabled when input falls below threshold
1 = Comparator result enabled when input exceeds threshold (Default)
Bit 1: ACOMP_A_INT_EN – Analog Comparator A Interrupt Enable
0 = Disables Analog Comparator A Interrupt generation (Default)
1 = Enables Analog Comparator A Interrupt generation
Bit 0: ACOMP_EN – Analog Comparators Enable
0 = Analog Comparators Disabled (Default)
1 = Analog Comparators Enabled
4.2.2 Analog Comparator Control 1 Register (ACOMPCTRL1)
Address 00130004
Bit Number
Bit Name
Access
Default
30:24
ACOMP_D_THRESH
R/W
000_0000
Bit Number
Bit Name
Access
Default
17
ACOMP_D_INT_EN
R/W
0
Bit Number
Bit Name
Access
7:6
RESERVED
-
50
23:22
RESERVED
00
16
ACOMP_D_OUT_EN
R/W
0
5:3
ACOMP_C_SEL
R/W
UCD3138064A Migration Guide
21:19
ACOMP_D_SEL
R/W
000
15
RESERVED
0
2
ACOMP_C_POL
R/W
18
ACOMP_D_POL
R/W
1
14:8
ACOMP_C_THRESH
R/W
000_0000
1
ACOMP_C_INT_EN
R/W
0
RESERVED
-
SLUA766
Default
00
000
1
0
0
Bits 30-24: ACOMP_D_THRESH – Configures Analog Comparator D
Threshold
0 = Comparator Reference of 19.53125 mV (Default)
1 = Comparator Reference of 39.0625 mV
……..
127 = Comparator Reference of 2.5 V
Bits 23-22: RESERVED – Unused bits
Bits 21-19: ACOMP_D_SEL – Configures Analog Comparator D Threshold
0 = Analog Comparator D Threshold set by ACOMP_D_THRESH
(Default)
1 = Analog Comparator D Threshold set by Comparator Ramp 0
2 = Analog Comparator D Threshold set by Filter 0 Output
3 = Analog Comparator D Threshold set by Filter 1 Output
4 = Analog Comparator D Threshold set by Filter 2 Output
Bit 18: ACOMP_D_POL – Analog Comparator D Polarity
0 = Comparator result enabled when input falls below threshold
1 = Comparator result enabled when input exceeds threshold (Default)
Bit 17: ACOMP_D_INT_EN – Analog Comparator D Interrupt Enable
0 = Disables Analog Comparator D Interrupt generation (Default)
1 = Enables Analog Comparator D Interrupt generation
Bit 16: ACOMP_D_OUT_EN – Analog Comparator D DAC Output Enable
0 = Disables output of Comparator DAC D onto AD pin (Default)
1 = Enables output of Comparator DAC D onto AD pin
Bit 15: RESERVED – Unused bit
Bits 14-8: ACOMP_C_THRESH – Configures Analog Comparator C Threshold
0 = Comparator Reference of 19.53125 mV (Default)
1 = Comparator Reference of 39.0625 mV
……..
127 = Comparator Reference of 2.5 V
Bits 7-6: RESERVED – Unused bits
Bits 5-3: ACOMP_C_SEL – Configures Analog Comparator C Threshold
0 = Analog Comparator C Threshold set by ACOMP_C_THRESH
(Default)
1 = Analog Comparator C Threshold set by Comparator Ramp 0
2 = Analog Comparator C Threshold set by Filter 0 Output
3 = Analog Comparator C Threshold set by Filter 1 Output
4 = Analog Comparator C Threshold set by Filter 2 Output
Bit 2: ACOMP_C_POL – Analog Comparator C Polarity
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0 = Comparator result enabled when input falls below threshold
1 = Comparator result enabled when input exceeds threshold (Default)
Bit 1: ACOMP_C_INT_EN – Analog Comparator C Interrupt Enable
0 = Disables Analog Comparator C Interrupt generation (Default)
1 = Enables Analog Comparator C Interrupt generation
Bit 0: RESERVED – Unused bit
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4.2.3 Analog Comparator Control 2 Register (ACOMPCTRL2)
Address 00130008
Bit Number
Bit Name
Access
Default
30:24
ACOMP_F_THRESH
R/W
000_0000
Bit Number
Bit Name
Access
Default
18
ACOMP_F_POL
R/W
1
Bit Number
Bit Name
Access
Default
14:8
ACOMP_E_THRESH
R/W
000_0000
Bit Number
Bit Name
Access
Default
2
ACOMP_E_POL
R/W
1
23
RESERVED
0
17
ACOMP_F_INT_EN
R/W
0
22
ACOMP_F_REF_SEL
R/W
0
16
ACOMP_F_OUT_EN
R/W
0
7:6
RESERVED
00
21:19
ACOMP_F_SEL
R/W
000
15
RESERVED
0
5:3
ACOMP_E_SEL
R/W
000
1
ACOMP_E_INT_EN
R/W
0
0
ACOMP_E_OUT_EN
R/W
0
Bits 30-24: ACOMP_F_THRESH – Configures Analog Comparator F
Threshold
0 = Comparator Reference of 19.53125 mV (Default)
1 = Comparator Reference of 39.0625 mV
……..
127 = Comparator Reference of 2.5 V
Bit 23: RESERVED – Unused bit
Bit 22: ACOMP_F_REF_SEL – Analog Comparator F Reference Select
0 = Selects internal DAC reference (Default)
1 = Selects reference driven from AD-07 pin
Bits 21-19: ACOMP_F_SEL – Configures Analog Comparator F Threshold
0 = Analog Comparator F Threshold set by ACOMP_F_THRESH
(Default)
1 = Analog Comparator F Threshold set by Comparator Ramp 0
2 = Analog Comparator F Threshold set by Filter 0 Output
3 = Analog Comparator F Threshold set by Filter 1 Output
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4 = Analog Comparator F Threshold set by Filter 2 Output
Bit 18: ACOMP_F_POL – Analog Comparator F Polarity
0 = Comparator result enabled when input falls below threshold
1 = Comparator result enabled when input exceeds threshold (Default)
Bit 17: ACOMP_F_INT_EN – Analog Comparator F Interrupt Enable
0 = Disables Analog Comparator F Interrupt generation (Default)
1 = Enables Analog Comparator F Interrupt generation
Bit 16: ACOMP_F_OUT_EN – Analog Comparator F DAC Output Enable
0 = Disables output of Comparator DAC F onto AD pin (Default)
1 = Enables output of Comparator DAC F onto AD pin
Bit 15: RESERVED – Unused bit
Bits 14-8: ACOMP_E_THRESH – Configures Analog Comparator E Threshold
0 = Comparator Reference of 19.53125 mV (Default)
1 = Comparator Reference of 39.0625 mV
……..
127 = Comparator Reference of 2.5 V
Bits 7-6: RESERVED – Unused bits
Bits 5-3: ACOMP_E_SEL – Configures Analog Comparator E Threshold
0 = Analog Comparator E Threshold set by ACOMP_E_THRESH
(Default)
1 = Analog Comparator E Threshold set by Comparator Ramp 0
2 = Analog Comparator E Threshold set by Filter 0 Output
3 = Analog Comparator E Threshold set by Filter 1 Output
4 = Analog Comparator E Threshold set by Filter 2 Output
Bit 2: ACOMP_E_POL – Analog Comparator E Polarity
0 = Comparator result enabled when input falls below threshold
1 = Comparator result enabled when input exceeds threshold (Default)
Bit 1: ACOMP_E_INT_EN – Analog Comparator E Interrupt Enable
0 = Disables Analog Comparator E Interrupt generation (Default)
1 = Enables Analog Comparator E Interrupt generation
Bit 0: ACOMP_E_OUT_EN – Analog Comparator E DAC Output Enable
0 = Disables output of Comparator DAC E onto AD pin (Default)
1 = Enables output of Comparator DAC E onto AD pin
4.2.4 Analog Comparator Control 3 Register (ACOMPCTRL3)
Address 0013000C
Bit Number
Bit Name
Access
Default
54
14:8
ACOMP_G_THRESH
R/W
000_0000
UCD3138064A Migration Guide
7:6
RESERVED
00
5:3
ACOMP_G_SEL
R/W
000
SLUA766
Bit Number
Bit Name
Access
Default
2
ACOMP_G_POL
R/W
1
1
ACOMP_G_INT_EN
R/W
0
0
ACOMP_G_OUT_EN
R/W
0
Bits 14-8: ACOMP_G_THRESH – Configures Analog Comparator G Threshold
0 = Comparator Reference of 19.53125 mV (Default)
1 = Comparator Reference of 39.0625 mV
……..
127 = Comparator Reference of 2.5 V
Bits 7-6: RESERVED – Unused bits
Bits 5-3: ACOMP_G_SEL – Configures Analog Comparator G Threshold
0 = Analog Comparator G Threshold set by ACOMP_G_THRESH
(Default)
1 = Analog Comparator G Threshold set by Comparator Ramp 0
2 = Analog Comparator G Threshold set by Filter 0 Output
3 = Analog Comparator G Threshold set by Filter 1 Output
4 = Analog Comparator G Threshold set by Filter 2 Output
Bit 2: ACOMP_G_POL – Analog Comparator G Polarity
0 = Comparator result enabled when input falls below threshold
1 = Comparator result enabled when input exceeds threshold (Default)
Bit 1: ACOMP_G_INT_EN – Analog Comparator G Interrupt Enable
0 = Disables Analog Comparator G Interrupt generation (Default)
1 = Enables Analog Comparator G Interrupt generation
Bit 0: ACOMP_G_OUT_EN – Analog Comparator G DAC Output Enable
0 = Disables output of Comparator DAC G onto AD pin (Default)
1 = Enables output of Comparator DAC G onto AD pin
4.2.5 External Fault Control Register (EXTFAULTCTRL)
Address 00130010
Bit Number
Bit Name
Access
Default
11
FAULT3_POL
R/W
1
10
FAULT2_POL
R/W
1
9
FAULT1_POL
R/W
1
8
FAULT0_POL
R/W
1
Bit Number
Bit Name
Access
Default
7
FAULT3_INT_EN
R/W
0
6
FAULT2_INT_EN
R/W
0
5
FAULT1_INT_EN
R/W
0
4
FAULT0_INT_EN
R/W
0
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Bit Number
Bit Name
Access
Default
3
FAULT3_DET_EN
R/W
0
2
FAULT2_DET_EN
R/W
0
1
FAULT1_DET_EN
R/W
0
Bit 11: FAULT3_POL – Polarity configuration for FAULT[3] pin
0 = Fault detection enabled on falling edge
1 = Fault detection enabled on rising edge (Default)
Bit 10: FAULT2_POL – Polarity configuration for FAULT[2] pin
0 = Fault detection enabled on falling edge
1 = Fault detection enabled on rising edge (Default)
Bit 9: FAULT1_POL – Polarity configuration for FAULT[1] pin
0 = Fault detection enabled on falling edge
1 = Fault detection enabled on rising edge (Default)
Bit 8: FAULT0_POL – Polarity configuration for FAULT[0] pin
0 = Fault detection enabled on falling edge
1 = Fault detection enabled on rising edge (Default)
Bit 7: FAULT3_INT_EN – FAULT[3] Pin Interrupt Enable
0 = Disables Fault Detection Interrupt generation (Default)
1 = Enables Fault Detection Interrupt generation
Bit 6: FAULT2_INT_EN – FAULT[2] Pin Interrupt Enable
0 = Disables Fault Detection Interrupt generation (Default)
1 = Enables Fault Detection Interrupt generation
Bit 5: FAULT1_INT_EN – FAULT[1] Pin Interrupt Enable
0 = Disables Fault Detection Interrupt generation (Default)
1 = Enables Fault Detection Interrupt generation
Bit 4: FAULT0_INT_EN – FAULT[0] Pin Interrupt Enable
0 = Disables Fault Detection Interrupt generation (Default)
1 = Enables Fault Detection Interrupt generation
Bit 3: FAULT3_DET_EN – FAULT[3] Pin Detection Enable
0 = Fault Detection Disabled (Default)
1 = Fault Detection Enabled
Bit 2: FAULT2_DET_EN – FAULT[2] Pin Detection Enable
0 = Fault Detection Disabled (Default)
1 = Fault Detection Enabled
Bit 1: FAULT1_DET_EN – FAULT[1] Pin Detection Enable
0 = Fault Detection Disabled (Default)
1 = Fault Detection Enabled
Bit 0: FAULT0_DET_EN – FAULT[0] Pin Detection Enable
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0
FAULT0_DET_EN
R/W
0
SLUA766
0 = Fault Detection Disabled (Default)
1 = Fault Detection Enabled
4.2.6 Fault Mux Interrupt Status Register (FAULTMUXINTSTAT)
Address 00130014
Bit Number
Bit Name
Access
Default
16
DCOMP3
R
-
Bit Number
Bit Name
Access
Default
11
FAULT3
R
-
Bit Number
Bit Name
Access
Default
5
ACOMP_F
R
-
15
DCOMP2
R
10
FAULT2
R
4
ACOMP_E
R
-
14
DCOMP1
R
9
FAULT1
R
3
ACOMP_D
R
-
13
DCOMP0
R
-
8
FAULT0
R
-
12
LFO_FAIL
R
-
7
DCM_DETECT
R
-
2
ACOMP_C
R
-
1
ACOMP_B
R
-
6
ACOMP_G
R
0
ACOMP_A
R
-
Bit 16: DCOMP3 – Digital Comparator 3 Interrupt Status, cleared by read of
status register
0 = Comparator threshold interrupt disabled
1 = Comparator threshold interrupt enabled
Bit 15: DCOMP2 – Digital Comparator 2 Interrupt Status, cleared by read of
status register
0 = Comparator threshold interrupt disabled
1 = Comparator threshold interrupt enabled
Bit 14: DCOMP1 – Digital Comparator 1 Interrupt Status, cleared by read of
status register
0 = Comparator threshold interrupt disabled
1 = Comparator threshold interrupt enabled
Bit 13: DCOMP0 – Digital Comparator 0 Interrupt Status, cleared by read of
status register
0 = Comparator threshold interrupt disabled
1 = Comparator threshold interrupt enabled
Bit 12: LFO_FAIL– Low Frequency Oscillator Failure Interrupt Status, cleared
by read of status register
0 = Low Frequency Oscillator operational
1 = Low Frequency Oscillator failure detected
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Bit 11: FAULT3 – External FAULT[2] Interrupt Detection
0 = No External GPIO detection found
1 = External GPIO detection found
Bit 10: FAULT2 – External FAULT[2] Interrupt Detection
0 = No External GPIO detection found
1 = External GPIO detection found
Bit 9: FAULT1 – External FAULT[1] Interrupt Detection
0 = No External GPIO detection found
1 = External GPIO detection found
Bit 8: FAULT0 – External FAULT[0] Interrupt Detection
0 = No External GPIO detection found
1 = External GPIO detection found
Bit 7: DCM_DETECT – Discontinuous Conduction Mode Interrupt Status,
cleared by read of status register
0 = Discontinuous Conduction Mode detected
1 = Discontinuous Conduction Mode not detected
Bit 6: ACOMP_G – Analog Comparator G Interrupt Status, cleared by read of
status register
0 = Comparator threshold interrupt disabled
1 = Comparator threshold interrupt enabled
Bit 5: ACOMP_F – Analog Comparator F Interrupt Status, cleared by read of
status register
0 = Comparator threshold interrupt disabled
1 = Comparator threshold interrupt enabled
Bit 4: ACOMP_E – Analog Comparator E Interrupt Status, cleared by read of
status register
0 = Comparator threshold interrupt disabled
1 = Comparator threshold interrupt enabled
Bit 3: ACOMP_D – Analog Comparator D Interrupt Status, cleared by read of
status register
0 = Comparator threshold interrupt disabled
1 = Comparator threshold interrupt enabled
Bit 2: ACOMP_C – Analog Comparator C Interrupt Status, cleared by read of
status register
0 = Comparator threshold interrupt disabled
1 = Comparator threshold interrupt enabled
Bit 1: ACOMP_B – Analog Comparator B Interrupt Status, cleared by read of
status register
0 = Comparator threshold interrupt disabled
1 = Comparator threshold interrupt enabled
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Bit 0: ACOMP_A – Analog Comparator A Interrupt Status, cleared by read of
status register
0 = Comparator threshold interrupt disabled
1 = Comparator threshold interrupt enabled
4.2.7 Fault Mux Raw Status Register (FAULTMUXRAWSTAT)
Address 00130018
Bit Number
Bit Name
Access
Default
16
DCOMP3
R
-
Bit Number
Bit Name
Access
Default
11
FAULT3
R
-
Bit Number
Bit Name
Access
Default
5
ACOMP_F
R
-
15
DCOMP2
R
10
FAULT2
R
4
ACOMP_E
R
-
14
DCOMP1
R
9
FAULT1
R
3
ACOMP_D
R
-
13
DCOMP0
R
-
8
FAULT0
R
-
12
LFO_FAIL
R
-
7
DCM_DETECT
R
-
2
ACOMP_C
R
-
1
ACOMP_B
R
-
6
ACOMP_G
R
0
ACOMP_A
R
-
Bit 16: DCOMP3 – Digital Comparator 3 Raw Status
0 = Comparator threshold not exceeded
1 = Comparator threshold exceeded
Bit 15: DCOMP2 – Digital Comparator 2 Raw Status
0 = Comparator threshold not exceeded
1 = Comparator threshold exceeded
Bit 14: DCOMP1 – Digital Comparator 1 Raw Status
0 = Comparator threshold not exceeded
1 = Comparator threshold exceeded
Bit 13: DCOMP0 – Digital Comparator 0 Raw Status
0 = Comparator threshold not exceeded
1 = Comparator threshold exceeded
Bit 12: LFO_FAIL – Low Frequency Oscillator Failure Raw Status
0 = Low Frequency Oscillator operational
1 = Low Frequency Oscillator failure detected
Bit 11: FAULT3 – External Fault Detection on FAULT[3] pin
0 = No External FAULT[2] detection found
1 = External GPIO detection found
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Bit 10: FAULT2 – External Fault Detection on FAULT[2] pin
0 = No External FAULT[2] detection found
1 = External GPIO detection found
Bit 9: FAULT1 – External Fault Detection on FAULT[1] pin
0 = No External FAULT[1] detection found
1 = External GPIO detection found
Bit 8: FAULT0 – External Fault Detection on FAULT[0] pin
0 = No External FAULT[0] detection found
1 = External GPIO detection found
Bit 7: DCM_DETECT – Discontinuous Conduction Mode Raw Status
0 = Discontinuous Conduction Mode detected
1 = Discontinuous Conduction Mode not detected
Bit 6: ACOMP_G – Analog Comparator G Raw Result
0 = Comparator threshold not exceeded
1 = Comparator threshold exceeded
Bit 5: ACOMP_F – Analog Comparator F Raw Result
0 = Comparator threshold not exceeded
1 = Comparator threshold exceeded
Bit 4: ACOMP_E – Analog Comparator E Raw Result
0 = Comparator threshold not exceeded
1 = Comparator threshold exceeded
Bit 3: ACOMP_D – Analog Comparator D Raw Result
0 = Comparator threshold not exceeded
1 = Comparator threshold exceeded
Bit 2: ACOMP_C – Analog Comparator C Raw Result
0 = Comparator threshold not exceeded
1 = Comparator threshold exceeded
Bit 1: ACOMP_B – Analog Comparator B Raw Result
0 = Comparator threshold not exceeded
1 = Comparator threshold exceeded
Bit 0: ACOMP_A – Analog Comparator A Raw Result
0 = Comparator threshold not exceeded
1 = Comparator threshold exceeded
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4.2.8 Comparator Ramp Control 0 Register (COMPRAMP0)
Address 0013001C
Bit Number
Bit Name
Access
Default
31:28
START_VALUE_SEL
R/W
0000
Bit Number
Bit Name
Access
Default
9:5
CLKS_PER_STEP
R/W
0_0000
Bit Number
Bit Name
Access
Default
2
DPWM1_TRIG_EN
R/W
00
27:10
STEP_SIZE
R/W
00_0000_0000_0000_0000
4
DPWM3_TRIG_EN
R/W
0
1
DPWM0_TRIG_EN
R/W
00
3
DPWM2_TRIG_EN
R/W
00
0
RAMP_EN
R/W
0
Bits 31-28: START_VALUE_SEL – Configures comparator ramp starting value
0 = Filter 0 Output (Bits 17-11) (Default)
1 = Filter 1 Output (Bits 17-11)
2 = Filter 2 Output (Bits 17-11)
3 = Analog Comparator Threshold A Value
4 = Analog Comparator Threshold B Value
5 = Analog Comparator Threshold C Value
6 = Analog Comparator Threshold D Value
7 = Analog Comparator Threshold E Value
8 = Analog Comparator Threshold F Value
9 = Analog Comparator Threshold G Value
Bits 27-10: STEP_SIZE - Programmable 18-bit unsigned comparator step with
Bits 27:24 representing the integer portion of the comparator step (0-15
Comparator steps of 19.5mV each) and Bits 23:10 representing the fractional
portion of the comparator step
Bits 9-5: CLKS_PER_STEP – Selects number of MCLK (HFO_OSC/8) clock
cycles per comparator step where number of subcycles can vary from 1 to 32
0 = 1 MCLK clock cycles per step (Default)
1 = 2 MCLK clock cycles per step
2 = 3 MCLK clock cycles per step
…….
31 = 32 MCLK clock cycles per step
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Bit 4: DPWM3_TRIG_EN – Enables DPWM Trigger from DPWM 3 to Analog
Comparator Ramp 0
0 = DPWM 3 trigger not routed to Analog Comparator Ramp 0 (Default)
1 = DPWM 3 trigger routed to Analog Comparator Ramp 0
Bit 3: DPWM2_TRIG_EN – Enables DPWM Trigger from DPWM 2 to Analog
Comparator Ramp 0
0 = DPWM 2 trigger not routed to Analog Comparator Ramp 0 (Default)
1 = DPWM 2 trigger routed to Analog Comparator Ramp 0
Bit 2: DPWM1_TRIG_EN – Enables DPWM Trigger from DPWM 1 to Analog
Comparator Ramp 0
0 = DPWM 1 trigger not routed to Analog Comparator Ramp 0 (Default)
1 = DPWM 1 trigger routed to Analog Comparator Ramp 0
Bit 1: DPWM0_TRIG_EN – Enables DPWM Trigger from DPWM 0 to Analog
Comparator Ramp 0
0 = DPWM 0 trigger not routed to Analog Comparator Ramp 0 (Default)
1 = DPWM 0 trigger routed to Analog Comparator Ramp 0
Bit 0: RAMP_EN – Enable for Analog Comparator Ramp 0
0 = Analog Comparator Ramp disabled (Default)
1 = Analog Comparator Ramp enabled
4.2.9 Digital Comparator Control 0 Register (DCOMPCTRL0)
Address 0x00130020
Bit Number
Bit Name
Access
Default
31:24
CNT_THRESH
R/W
0000_0000
Bit Number
Bit Name
Access
Default
13
CNT_CONFIG
R/W
0
23:19
RESERVED
0000_0
12
INT_EN
R/W
0
18
COMP_POL
R/W
0
11
COMP_EN
R/W
0
17:15
FE_SEL
R/W
000
10:0
THRESH
R/W
000_0000_0000
Bits 31-24: CNT_THRESH – Sets the number of received comparator events
before declaring a fault
Bits 23-19: RESERVED – Unused bits
Bit 18: COMP_POL – Digital Comparator 0 Polarity
0 = Digital Comparator result asserted if value below threshold (Default)
1 = Digital Comparator result asserted if value above threshold
Bits 17-15: FE_SEL – Selects which Front End absolute data is used for Digital
Comparison with threshold
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CNT_CLR
R/W
0
SLUA766
0 = Front End 0 absolute data selected (Default)
1 = Front End 1 absolute data selected
2 = Front End 2 absolute data selected
3 = Front End 0 error data selected
4 = Front End 1 error data selected
5 = Front End 2 error data selected
Bit 14: CNT_CLR – Comparator Detection Counter clear
0 = No clear of Comparator Detection Counter (Default)
1 = Clear Comparator Detection counter and associated fault
Bit 13: CNT_CONFIG – Comparator Detection Counter configuration
0 = Counter clears upon receipt of sample which does not exceed
comparator threshold (Default)
1 = Counter decrements by 1 upon receipt of sample which does not
exceed comparator threshold
Bit 12: INT_EN – Comparator Interrupt Enable
0 = Disables Comparator Interrupt generation (Default)
1 = Enables Comparator Interrupt generation
Bit 11: COMP_EN – Digital Comparator 0 Enable
0 = Disables Digital Comparator 0 (Default)
1 = Enables Digital Comparator 0
Bits 10-0: THRESH – Sets the digital comparator threshold, 11-bit signed value
with resolution of 1.5625mV/bit
4.2.10 Digital Comparator Control 1 Register (DCOMPCTRL1)
Address 0x00130024
Bit Number
Bit Name
Access
Default
31:24
CNT_THRESH
R/W
0000_0000
Bit Number
Bit Name
Access
Default
13
CNT_CONFIG
R/W
0
23:19
RESERVED
0000_0
12
INT_EN
R/W
0
18
COMP_POL
R/W
0
11
COMP_EN
R/W
0
17:15
FE_SEL
R/W
000
14
CNT_CLR
R/W
0
10:0
THRESH
R/W
000_0000_0000
Bits 31-24: CNT_THRESH – Sets the number of received comparator events
before declaring a fault
Bits 23-19: RESERVED – Unused bits
Bit 18: COMP_POL – Digital Comparator 1 Polarity
0 = Digital Comparator result asserted if value below threshold (Default)
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1 = Digital Comparator result asserted if value above threshold
Bits 17-15: FE_SEL – Selects which Front End absolute data is used for Digital
Comparison with threshold
0 = Front End 0 absolute data selected (Default)
1 = Front End 1 absolute data selected
2 = Front End 2 absolute data selected
3 = Front End 0 error data selected
4 = Front End 1 error data selected
5 = Front End 2 error data selected
Bit 14: CNT_CLR – Comparator Detection Counter clear
0 = No clear of Comparator Detection Counter (Default)
1 = Clear Comparator Detection counter and associated fault
Bit 13: CNT_CONFIG – Comparator Detection Counter configuration
0 = Counter clears upon receipt of sample which does not exceed
comparator threshold (Default)
1 = Counter decrements by 1 upon receipt of sample which does not
exceed comparator threshold
Bit 12: INT_EN – Comparator Interrupt Enable
0 = Disables Comparator Interrupt generation (Default)
1 = Enables Comparator Interrupt generation
Bit 11: COMP_EN – Digital Comparator 1 Enable
0 = Disables Digital Comparator 1 (Default)
1 = Enables Digital Comparator 1
Bits 10-0: THRESH – Sets the digital comparator threshold, 11-bit signed value
with resolution of 1.5625mV/bit
4.2.11 Digital Comparator Control 2 Register (DCOMPCTRL2)
Address 0x00130028
Bit Number
Bit Name
Access
Default
31:24
CNT_THRESH
R/W
0000_0000
Bit Number
Bit Name
Access
Default
13
CNT_CONFIG
R/W
0
23:19
RESERVED
0000_0
12
INT_EN
R/W
0
18
COMP_POL
R/W
0
11
COMP_EN
R/W
0
17:15
FE_SEL
R/W
000
10:0
THRESH
R/W
000_0000_0000
Bits 31-24: CNT_THRESH – Sets the number of received comparator events
before declaring a fault
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CNT_CLR
R/W
0
SLUA766
Bits 23-19: RESERVED – Unused bits
Bit 18: COMP_POL – Digital Comparator 1 Polarity
0 = Digital Comparator result asserted if value below threshold (Default)
1 = Digital Comparator result asserted if value above threshold
Bits 17-15: FE_SEL – Selects which Front End absolute data is used for Digital
Comparison with threshold
0 = Front End 0 absolute data selected (Default)
1 = Front End 1 absolute data selected
2 = Front End 2 absolute data selected
3 = Front End 0 error data selected
4 = Front End 1 error data selected
5 = Front End 2 error data selected
Bit 14: CNT_CLR – Comparator Detection Counter clear
0 = No clear of Comparator Detection Counter (Default)
1 = Clear Comparator Detection counter and associated fault
Bit 13: CNT_CONFIG – Comparator Detection Counter configuration
0 = Counter clears upon receipt of sample which does not exceed
comparator threshold (Default)
1 = Counter decrements by 1 upon receipt of sample which does not
exceed comparator threshold
Bit 12: INT_EN – Comparator Interrupt Enable
0 = Disables Comparator Interrupt generation (Default)
1 = Enables Comparator Interrupt generation
Bit 11: COMP_EN – Digital Comparator 2 Enable
0 = Disables Digital Comparator 2 (Default)
1 = Enables Digital Comparator 2
Bits 10-0: THRESH – Sets the digital comparator threshold, 11-bit signed value
with resolution of 1.5625mV/bit
4.2.12 Digital Comparator Control 3 Register (DCOMPCTRL3)
Address 0x0013002C
Bit Number
Bit Name
Access
Default
31:24
CNT_THRESH
R/W
0000_0000
Bit Number
Bit Name
Access
Default
13
CNT_CONFIG
R/W
0
23:19
RESERVED
0000_0
12
INT_EN
R/W
0
18
COMP_POL
R/W
0
11
COMP_EN
R/W
0
17:15
FE_SEL
R/W
000
14
CNT_CLR
R/W
0
10:0
THRESH
R/W
000_0000_0000
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Bits 31-24: CNT_THRESH – Sets the number of received comparator events
before declaring a fault
Bits 23-19: RESERVED – Unused bits
Bit 18: COMP_POL – Digital Comparator 1 Polarity
0 = Digital Comparator result asserted if value below threshold (Default)
1 = Digital Comparator result asserted if value above threshold
Bits 17-15: FE_SEL – Selects which Front End absolute data is used for Digital
Comparison with threshold
0 = Front End 0 absolute data selected (Default)
1 = Front End 1 absolute data selected
2 = Front End 2 absolute data selected
3 = Front End 0 error data selected
4 = Front End 1 error data selected
5 = Front End 2 error data selected
Bit 14: CNT_CLR – Comparator Detection Counter clear
0 = No clear of Comparator Detection Counter (Default)
1 = Clear Comparator Detection counter and associated fault
Bit 13: CNT_CONFIG – Comparator Detection Counter configuration
0 = Counter clears upon receipt of sample which does not exceed
comparator threshold (Default)
1 = Counter decrements by 1 upon receipt of sample which does not
exceed comparator threshold
Bit 12: INT_EN – Comparator Interrupt Enable
0 = Disables Comparator Interrupt generation (Default)
1 = Enables Comparator Interrupt generation
Bit 11: COMP_EN – Digital Comparator 3 Enable
0 = Disables Digital Comparator 3 (Default)
1 = Enables Digital Comparator 3
Bits 10-0: THRESH – Sets the digital comparator threshold, 11-bit signed value
with resolution of 1.5625mV/bit
4.2.13 Digital Comparator Counter Status Register (DCOMPCNTSTAT)
Address 0x00130030
Bit Number
Bit Name
Access
Default
31:24
DCOMP3_CNT
R
-
31:24
DCOMP2_CNT
R
-
31:24
DCOMP1_CNT
R
-
31:24
DCOMP0_CNT
R
-
Bits 31-24: DCOMP3_CNT – Current value of Digital Comparator 3 detection
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counter
Bits 23-16: DCOMP2_CNT – Current value of Digital Comparator 2 detection
counter
Bits 15-8: DCOMP1_CNT – Current value of Digital Comparator 1 detection
counter
Bits 7-0: DCOMP0_CNT – Current value of Digital Comparator 0 detection
counter
4.2.14 DPWM 0 Current Limit Control Register (DPWM0CLIM)
Address 0x00130034
Bit Number
Bit Name
Access
Default
16
ANALOG_PCM_EN
R/W
0
15
DCOMP3_EN
R/W
0
14
DCOMP2_EN
R/W
0
Bit Number
Bit Name
Access
Default
13
DCOMP1_EN
R/W
0
12
DCOMP0_EN
R/W
0
11
RESERVED
R
0
10
FAULT3_EN
R/W
0
9
FAULT2_EN
R/W
0
Bit Number
Bit Name
Access
Default
8
FAULT1_EN
R/W
0
7
FAULT0_EN
R/W
0
6
ACOMP_G_EN
R/W
0
5
ACOMP_F_EN
R/W
0
4
ACOMP_E_EN
R/W
0
Bit Number
Bit Name
Access
Default
3
ACOMP_D_EN
R/W
0
2
ACOMP_C_EN
R/W
0
1
ACOMP_B_EN
R/W
0
0
ACOMP_A_EN
R/W
0
Bit 16: ANALOG_PCM_EN – Enables Analog Peak Current detection result for
DPWM 0 Current Limit
0 = Analog Peak Current detection disabled for current limit (Default)
1 = Analog Peak Current detection enabled for current limit
Bit 15: DCOMP3_EN – Enables Digital Comparator 3 result for DPWM 0
Current Limit
0 = Digital Comparator 3 result disabled for current limit (Default)
1 = Digital Comparator 3 result enabled for current limit
Bit 14: DCOMP2_EN – Enables Digital Comparator 2 result for DPWM 0
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Current Limit
0 = Digital Comparator 2 result disabled for current limit (Default)
1 = Digital Comparator 2 result enabled for current limit
Bit 13: DCOMP1_EN – Enables Digital Comparator 1 result for DPWM 0
Current Limit
0 = Digital Comparator 1 result disabled for current limit (Default)
1 = Digital Comparator 1 result enabled for current limit
Bit 12: DCOMP0_EN – Enables Digital Comparator 0 result for DPWM 0
Current Limit
0 = Digital Comparator 0 result disabled for current limit (Default)
1 = Digital Comparator 0 result enabled for current limit
Bit 11: RESERVED – Unused Bit
Bit 10: FAULT3_EN – Enables FAULT[3] pin for DPWM 0 Current Limit
0 = External Fault pin disabled for current limit (Default)
1 = External Fault pin enabled for current limit
Bit 9: FAULT2_EN – Enables FAULT[2] pin for DPWM 0 Current Limit
0 = External Fault pin disabled for current limit (Default)
1 = External Fault pin enabled for current limit
Bit 8: FAULT1_EN – Enables FAULT[1] pin for DPWM 0 Current Limit
0 = External Fault pin disabled for current limit (Default)
1 = External Fault pin enabled for current limit
Bit 7: FAULT0_EN – Enables FAULT[0] pin for DPWM 0 Current Limit
0 = External Fault pin disabled for current limit (Default)
1 = External Fault pin enabled for current limit
Bit 6: ACOMP_G_EN – Enables Analog Comparator G result for DPWM 0
Current Limit
0 = Analog Comparator result disabled for current limit (Default)
1 = Analog Comparator result enabled for current limit
Bit 5: ACOMP_F_EN – Enables Analog Comparator F result for DPWM 0
Current Limit
0 = Analog Comparator result disabled for current limit (Default)
1 = Analog Comparator result enabled for current limit
Bit 4: ACOMP_E_EN – Enables Analog Comparator E result for DPWM 0
Current Limit
0 = Analog Comparator result disabled for current limit (Default)
1 = Analog Comparator result enabled for current limit
Bit 3: ACOMP_D_EN – Enables Analog Comparator D result for DPWM 0
Current Limit
0 = Analog Comparator result disabled for current limit (Default)
1 = Analog Comparator result enabled for current limit
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Bit 2: ACOMP_C_EN – Enables Analog Comparator C result for DPWM 0
Current Limit
0 = Analog Comparator result disabled for current limit (Default)
1 = Analog Comparator result enabled for current limit
Bit 1: ACOMP_B_EN – Enables Analog Comparator B result for DPWM 0
Current Limit
0 = Analog Comparator result disabled for current limit (Default)
1 = Analog Comparator result enabled for current limit
Bit 0: ACOMP_A_EN – Enables Analog Comparator A result for DPWM 0
Current Limit
0 = Analog Comparator result disabled for current limit (Default)
1 = Analog Comparator result enabled for current limit
4.2.15 DPWM 0 Fault AB Detection Register (DPWM0FLTABDET)
Address 0x00130038
Bit Number
Bit Name
Access
Default
14
DCOMP3_EN
R/W
0
13
DCOMP2_EN
R/W
0
12
DCOMP1_EN
R/W
0
11
DCOMP0_EN
R/W
0
10
FAULT3_EN
R/W
0
Bit Number
Bit Name
Access
Default
9
FAULT2_EN
R/W
0
8
FAULT1_EN
R/W
0
7
FAULT0_EN
R/W
0
6
ACOMP_G_EN
R/W
0
5
ACOMP_F_EN
R/W
0
Bit Number
Bit Name
Access
Default
4
ACOMP_E_EN
R/W
0
3
ACOMP_D_EN
R/W
0
2
ACOMP_C_EN
R/W
0
1
ACOMP_B_EN
R/W
0
0
ACOMP_A_EN
R/W
0
Bit 14: DCOMP3_EN – Enables Digital Comparator 3 result for DPWM 0 Fault
AB Detection
0 = Digital Comparator 3 disabled for Fault AB detection (Default)
1 = Digital Comparator 3 enabled for Fault AB detection
Bit 13: DCOMP2_EN – Enables Digital Comparator 2 result for DPWM 0 Fault
AB Detection
0 = Digital Comparator 2 disabled for Fault AB detection (Default)
1 = Digital Comparator 2 enabled for Fault AB detection
Bit 12: DCOMP1_EN – Enables Digital Comparator 1 result for DPWM 0 Fault
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AB Detection
0 = Digital Comparator 1 disabled for Fault AB detection (Default)
1 = Digital Comparator 1 enabled for Fault AB detection
Bit 11: DCOMP0_EN – Enables Digital Comparator 0 result for DPWM 0 Fault
AB Detection
0 = Digital Comparator 0 disabled for Fault AB detection (Default)
1 = Digital Comparator 0 enabled for Fault AB detection
Bit 10: FAULT3_EN – Enables FAULT[3] pin for DPWM 0 Fault AB detection
0 = External Fault pin disabled for Fault AB detection (Default)
1 = External Fault pin enabled for Fault AB detection
Bit 9: FAULT2_EN – Enables FAULT[2] pin for DPWM 0 Fault AB detection
0 = External Fault pin disabled for Fault AB detection (Default)
1 = External Fault pin enabled for Fault AB detection
Bit 8: FAULT1_EN – Enables FAULT[1] pin for DPWM 0 Fault AB detection
0 = External Fault pin disabled for Fault AB detection (Default)
1 = External Fault pin enabled for Fault AB detection
Bit 7: FAULT0_EN – Enables FAULT[0] pin for DPWM 0 Fault AB detection
0 = External Fault pin disabled for Fault AB detection (Default)
1 = External Fault pin enabled for Fault AB detection
Bit 6: ACOMP_A_EN – Enables Analog Comparator G result for DPWM 0
Fault AB detection
0 = Analog Comparator result disabled for Fault AB detection (Default)
1 = Analog Comparator result enabled for Fault AB detection
Bit 5: ACOMP_F_EN – Enables Analog Comparator F result for DPWM 0 Fault
AB detection
0 = Analog Comparator result disabled for Fault AB detection (Default)
1 = Analog Comparator result enabled for Fault AB detection
Bit 4: ACOMP_E_EN – Enables Analog Comparator E result for DPWM 0 Fault
AB detection
0 = Analog Comparator result disabled for Fault AB detection (Default)
1 = Analog Comparator result enabled for Fault AB detection
Bit 3: ACOMP_D_EN – Enables Analog Comparator D result for DPWM 0
Fault AB detection
0 = Analog Comparator result disabled for Fault AB detection (Default)
1 = Analog Comparator result enabled for Fault AB detection
Bit 2: ACOMP_C_EN – Enables Analog Comparator C result for DPWM 0
Fault AB detection
0 = Analog Comparator result disabled for Fault AB detection (Default)
1 = Analog Comparator result enabled for Fault AB detection
Bit 1: ACOMP_B_EN – Enables Analog Comparator B result for DPWM 0
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Fault AB detection
0 = Analog Comparator result disabled for Fault AB detection (Default)
1 = Analog Comparator result enabled for Fault AB detection
Bit 0: ACOMP_A_EN – Enables Analog Comparator A result for DPWM 0
Fault AB detection
0 = Analog Comparator result disabled for Fault AB detection (Default)
1 = Analog Comparator result enabled for Fault AB detection
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4.2.16 DPWM 0 Fault Detection Register (DPWM0FAULTDET)
Address 0x0013003C
Bit Number
Bit Name
Access
Default
30
PWMB_DCOMP3_EN
R/W
0
29
PWMB_DCOMP2_EN
R/W
0
Bit Number
Bit Name
Access
Default
27
PWMB_DCOMP0_EN
R/W
0
Bit Number
Bit Name
Access
Default
24
PWMB_FAULT1_EN
R/W
0
23
PWMB_FAULT0_EN
R/W
0
22
PWMB_ACOMP_G_EN
R/W
0
Bit Number
Bit Name
Access
Default
21
PWMB_ACOMP_F_EN
R/W
0
20
PWMB_ACOMP_E_EN
R/W
0
19
PWMB_ACOMP_D_EN
R/W
0
Bit Number
Bit Name
Access
Default
18
PWMB_ACOMP_C_EN
R/W
0
17
PWMB_ACOMP_B_EN
R/W
0
16
PWMB_ACOMP_A_EN
R/W
0
Bit Number
Bit Name
Access
Default
Bit Number
Bit Name
Access
Default
72
15
RESERVED
0
13
PWMA_DCOMP2_EN
R/W
0
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PWMB_FAULT3_EN
R/W
0
28
PWMB_DCOMP1_EN
R/W
0
25
PWMB_FAULT2_EN
R/W
0
14
PWMA_DCOMP3_EN
R/W
0
12
PWMA_DCOMP1_EN
R/W
0
11
PWMA_DCOMP0_EN
R/W
0
SLUA766
Bit Number
Bit Name
Access
Default
10
PWMA_FAULT3_EN
R/W
0
9
PWMA_FAULT2_EN
R/W
0
Bit Number
Bit Name
Access
Default
8
PWMA_FAULT1_EN
R/W
0
7
PWMA_FAULT0_EN
R/W
0
6
PWMA_ACOMP_G_EN
R/W
0
Bit Number
Bit Name
Access
Default
5
PWMA_ACOMP_F_EN
R/W
0
4
PWMA_ACOMP_E_EN
R/W
0
3
PWMA_ACOMP_D_EN
R/W
0
Bit Number
Bit Name
Access
Default
2
PWMA_ACOMP_C_EN
R/W
0
1
PWMA_ACOMP_B_EN
R/W
0
0
PWMA_ACOMP_A_EN
R/W
0
Bit 30: PWMB_DCOMP3_EN – Enables Digital Comparator 3 result for
DPWM 0 PWM-B Fault Detection
0 = Digital Comparator 3 disabled for fault detection (Default)
1 = Digital Comparator 3 enabled for fault detection
Bit 29: PWMB_DCOMP2_EN – Enables Digital Comparator 2 result for
DPWM 0 PWM-B Fault Detection
0 = Digital Comparator 2 disabled for fault detection (Default)
1 = Digital Comparator 2 enabled for fault detection
Bit 28: PWMB_DCOMP1_EN – Enables Digital Comparator 1 result for
DPWM 0 PWM-B Fault Detection
0 = Digital Comparator 1 disabled for fault detection (Default)
1 = Digital Comparator 1 enabled for fault detection
Bit 27: PWMB_DCOMP0_EN – Enables Digital Comparator 0 result for
DPWM 0 PWM-B Fault Detection
0 = Digital Comparator 0 disabled for fault detection (Default)
1 = Digital Comparator 0 enabled for fault detection
Bit 26: PWMB_FAULT3_EN – Enables FAULT[3] pin for DPWM 0 PWM-B
Fault Detection
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0 = External Fault pin disabled for fault detection (Default)
1 = External Fault pin enabled for fault detection
Bit 25: PWMB_FAULT2_EN – Enables FAULT[2] pin for DPWM 0 PWM-B
Fault Detection
0 = External Fault pin disabled for fault detection (Default)
1 = External Fault pin enabled for fault detection
Bit 24: PWMB_FAULT1_EN – Enables FAULT[1] pin for DPWM 0 PWM-B
Fault Detection
0 = External Fault pin disabled for fault detection (Default)
1 = External Fault pin enabled for fault detection
Bit 23: PWMB_FAULT0_EN – Enables FAULT[0] pin for DPWM 0 PWM-B
Fault Detection
0 = External Fault pin disabled for fault detection (Default)
1 = External Fault pin enabled for fault detection
Bit 22: PWMB_ACOMP_G_EN – Enables Analog Comparator G result for
DPWM 0 PWM-B Fault detection
0 = Analog Comparator result disabled for fault detection (Default)
1 = Analog Comparator result enabled for fault detection
Bit 21: PWMB_ACOMP_F_EN – Enables Analog Comparator F result for
DPWM 0 PWM-B Fault detection
0 = Analog Comparator result disabled for fault detection (Default)
1 = Analog Comparator result enabled for fault detection
Bit 20: PWMB_ACOMP_E_EN – Enables Analog Comparator E result for
DPWM 0 PWM-B Fault detection
0 = Analog Comparator result disabled for fault detection (Default)
1 = Analog Comparator result enabled for fault detection
Bit 19: PWMB_ACOMP_D_EN – Enables Analog Comparator D result for
DPWM 0 PWM-B Fault detection
0 = Analog Comparator result disabled for fault detection (Default)
1 = Analog Comparator result enabled for fault detection
Bit 18: PWMB_ACOMP_C_EN – Enables Analog Comparator C result for
DPWM 0 PWM-B Fault detection
0 = Analog Comparator result disabled for fault detection (Default)
1 = Analog Comparator result enabled for fault detection
Bit 17: PWMB_ACOMP_B_EN – Enables Analog Comparator B result for
DPWM 0 PWM-B Fault detection
0 = Analog Comparator result disabled for fault detection (Default)
1 = Analog Comparator result enabled for fault detection
Bit 16: PWMB_ACOMP_A_EN – Enables Analog Comparator A result for
DPWM 0 PWM-B Fault detection
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0 = Analog Comparator result disabled for fault detection (Default)
1 = Analog Comparator result enabled for fault detection
Bit 15: RESERVED – Unused bit
Bit 14: PWMA_DCOMP3_EN – Enables Digital Comparator 3 result for
DPWM 0 PWM-A Fault Detection
0 = Digital Comparator 3 disabled for fault detection (Default)
1 = Digital Comparator 3 enabled for fault detection
Bit 13: PWMA_DCOMP2_EN – Enables Digital Comparator 2 result for
DPWM 0 PWM-A Fault Detection
0 = Digital Comparator 2 disabled for fault detection (Default)
1 = Digital Comparator 2 enabled for fault detection
Bit 12: PWMA_DCOMP1_EN – Enables Digital Comparator 1 result for
DPWM 0 PWM-A Fault Detection
0 = Digital Comparator 1 disabled for fault detection (Default)
1 = Digital Comparator 1 enabled for fault detection
Bit 11: PWMA_DCOMP0_EN – Enables Digital Comparator 0 result for
DPWM 0 PWM-A Fault Detection
0 = Digital Comparator 0 disabled for fault detection (Default)
1 = Digital Comparator 0 enabled for fault detection
Bit 10: PWMA_FAULT3_EN – Enables FAULT[3] pin for DPWM 0 PWM-A
Fault Detection
0 = External Fault pin disabled for fault detection (Default)
1 = External Fault pin enabled for fault detection
Bit 9: PWMA_FAULT2_EN – Enables FAULT[2] pin for DPWM 0 PWM-A
Fault Detection
0 = External Fault pin disabled for fault detection (Default)
1 = External Fault pin enabled for fault detection
Bit 8: PWMA_FAULT1_EN – Enables FAULT[1] pin for DPWM 0 PWM-A
Fault Detection
0 = External Fault pin disabled for fault detection (Default)
1 = External Fault pin enabled for fault detection
Bit 7: PWMA_FAULT0_EN – Enables FAULT[0] pin for DPWM 0 PWM-A
Fault Detection
0 = External Fault pin disabled for fault detection (Default)
1 = External Fault pin enabled for fault detection
Bit 6: PWMA_ACOMP_G_EN – Enables Analog Comparator G result for
DPWM 0 PWM-A Fault detection
0 = Analog Comparator result disabled for fault detection (Default)
1 = Analog Comparator result enabled for fault detection
Bit 5: PWMA_ACOMP_F_EN – Enables Analog Comparator F result for
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DPWM 0 PWM-A Fault detection
0 = Analog Comparator result disabled for fault detection (Default)
1 = Analog Comparator result enabled for fault detection
Bit 4: PWMA_ACOMP_E_EN – Enables Analog Comparator E result for
DPWM 0 PWM-A Fault detection
0 = Analog Comparator result disabled for fault detection (Default)
1 = Analog Comparator result enabled for fault detection
Bit 3: PWMA_ACOMP_D_EN – Enables Analog Comparator D result for
DPWM 0 PWM-A Fault detection
0 = Analog Comparator result disabled for fault detection (Default)
1 = Analog Comparator result enabled for fault detection
Bit 2: PWMA_ACOMP_C_EN – Enables Analog Comparator C result for
DPWM 0 PWM-A Fault detection
0 = Analog Comparator result disabled for fault detection (Default)
1 = Analog Comparator result enabled for fault detection
Bit 1: PWMA_ACOMP_B_EN – Enables Analog Comparator B result for
DPWM 0 PWM-A Fault detection
0 = Analog Comparator result disabled for fault detection (Default)
1 = Analog Comparator result enabled for fault detection
Bit 0: PWMA_ACOMP_A_EN – Enables Analog Comparator A result for
DPWM 0 PWM-A Fault detection
0 = Analog Comparator result disabled for fault detection (Default)
1 = Analog Comparator result enabled for fault detection
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4.2.17 DPWM 0 IDE Detection Register (DPWM0IDEDET)
Address 0x00130040
Bit Number
Bit Name
Access
Default
6
ACOMP_G_EN
R/W
0
Bit Number
Bit Name
Access
Default
2
ACOMP_C_EN
R/W
0
5
ACOMP_F_EN
R/W
0
4
ACOMP_E_EN
R/W
0
1
ACOMP_B_EN
R/W
0
3
ACOMP_D_EN
R/W
0
0
ACOMP_A_EN
R/W
0
Bit 6: ACOMP_6_EN – Enables Analog Comparator G result for DPWM 0 IDE
detection
0 = Analog Comparator result disabled for IDE detection (Default)
1 = Analog Comparator result enabled for IDE detection
Bit 5: ACOMP_5_EN – Enables Analog Comparator F result for DPWM 0 IDE
detection
0 = Analog Comparator result disabled for IDE detection (Default)
1 = Analog Comparator result enabled for IDE detection
Bit 4: ACOMP_4_EN – Enables Analog Comparator E result for DPWM 0 IDE
detection
0 = Analog Comparator result disabled for IDE detection (Default)
1 = Analog Comparator result enabled for IDE detection
Bit 3: ACOMP_3_EN – Enables Analog Comparator D result for DPWM 0 IDE
detection
0 = Analog Comparator result disabled for IDE detection (Default)
1 = Analog Comparator result enabled for IDE detection
Bit 2: ACOMP_2_EN – Enables Analog Comparator C result for DPWM 0 IDE
detection
0 = Analog Comparator result disabled for IDE detection (Default)
1 = Analog Comparator result enabled for IDE detection
Bit 1: ACOMP_1_EN – Enables Analog Comparator B result for DPWM 0 IDE
detection
0 = Analog Comparator result disabled for IDE detection (Default)
1 = Analog Comparator result enabled for IDE detection
Bit 0: ACOMP_0_EN – Enables Analog Comparator A result for DPWM 0 IDE
detection
0 = Analog Comparator result disabled for IDE detection (Default)
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1 = Analog Comparator result enabled for IDE detection
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4.2.18 DPWM 1 Current Limit Control Register (DPWM1CLIM)
Address 0x00130044
Bit Number
Bit Name
Access
Default
16
ANALOG_PCM_EN
R/W
0
15
DCOMP3_EN
R/W
0
14
DCOMP2_EN
R/W
0
Bit Number
Bit Name
Access
Default
13
DCOMP1_EN
R/W
0
12
DCOMP0_EN
R/W
0
11
RESERVED
R
0
10
FAULT3_EN
R/W
0
9
FAULT2_EN
R/W
0
Bit Number
Bit Name
Access
Default
8
FAULT1_EN
R/W
0
7
FAULT0_EN
R/W
0
6
ACOMP_G_EN
R/W
0
5
ACOMP_F_EN
R/W
0
4
ACOMP_E_EN
R/W
0
Bit Number
Bit Name
Access
Default
3
ACOMP_D_EN
R/W
0
2
ACOMP_C_EN
R/W
0
1
ACOMP_B_EN
R/W
0
0
ACOMP_A_EN
R/W
0
Bit 16: ANALOG_PCM_EN – Enables Analog Peak Current detection result for
DPWM 1 Current Limit
0 = Analog Peak Current detection disabled for current limit (Default)
1 = Analog Peak Current detection enabled for current limit
Bit 15: DCOMP3_EN – Enables Digital Comparator 3 result for DPWM 1
Current Limit
0 = Digital Comparator 3 result disabled for current limit (Default)
1 = Digital Comparator 3 result enabled for current limit
Bit 14: DCOMP2_EN – Enables Digital Comparator 2 result for DPWM 1
Current Limit
0 = Digital Comparator 2 result disabled for current limit (Default)
1 = Digital Comparator 2 result enabled for current limit
Bit 13: DCOMP1_EN – Enables Digital Comparator 1 result for DPWM 1
Current Limit
0 = Digital Comparator 1 result disabled for current limit (Default)
1 = Digital Comparator 1 result enabled for current limit
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Bit 12: DCOMP0_EN – Enables Digital Comparator 0 result for DPWM 1
Current Limit
0 = Digital Comparator 0 result disabled for current limit (Default)
1 = Digital Comparator 0 result enabled for current limit
Bit 11: Reserved – Unused Bit
Bit 10: FAULT3_EN – Enables FAULT[3] pin for DPWM 1 Current Limit
0 = External Fault pin disabled for current limit (Default)
1 = External Fault pin enabled for current limit
Bit 9: FAULT2_EN – Enables FAULT[2] pin for DPWM 1 Current Limit
0 = External Fault pin disabled for current limit (Default)
1 = External Fault pin enabled for current limit
Bit 8: FAULT1_EN – Enables FAULT[1] pin for DPWM 1 Current Limit
0 = External Fault pin disabled for current limit (Default)
1 = External Fault pin enabled for current limit
Bit 7: FAULT0_EN – Enables FAULT[0] pin for DPWM 1 Current Limit
0 = External Fault pin disabled for current limit (Default)
1 = External Fault pin enabled for current limit
Bit 6: ACOMP_G_EN – Enables Analog Comparator G result for DPWM 1
Current Limit
0 = Analog Comparator result disabled for current limit (Default)
1 = Analog Comparator result enabled for current limit
Bit 5: ACOMP_F_EN – Enables Analog Comparator F result for DPWM 1
Current Limit
0 = Analog Comparator result disabled for current limit (Default)
1 = Analog Comparator result enabled for current limit
Bit 4: ACOMP_E_EN – Enables Analog Comparator E result for DPWM 1
Current Limit
0 = Analog Comparator result disabled for current limit (Default)
1 = Analog Comparator result enabled for current limit
Bit 3: ACOMP_D_EN – Enables Analog Comparator D result for DPWM 1
Current Limit
0 = Analog Comparator result disabled for current limit (Default)
1 = Analog Comparator result enabled for current limit
Bit 2: ACOMP_C_EN – Enables Analog Comparator C result for DPWM 1
Current Limit
0 = Analog Comparator result disabled for current limit (Default)
1 = Analog Comparator result enabled for current limit
Bit 1: ACOMP_B_EN – Enables Analog Comparator B result for DPWM 1
Current Limit
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0 = Analog Comparator result disabled for current limit (Default)
1 = Analog Comparator result enabled for current limit
Bit 0: ACOMP_A_EN – Enables Analog Comparator A result for DPWM 1
Current Limit
0 = Analog Comparator result disabled for current limit (Default)
1 = Analog Comparator result enabled for current limit
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4.2.19 DPWM 1 Fault AB Detection Register (DPWM1FLTABDET)
Address 0x00130048
Bit Number
Bit Name
Access
Default
14
DCOMP3_EN
R/W
0
13
DCOMP2_EN
R/W
0
12
DCOMP1_EN
R/W
0
11
DCOMP0_EN
R/W
0
10
FAULT3_EN
R/W
0
Bit Number
Bit Name
Access
Default
9
FAULT2_EN
R/W
0
8
FAULT1_EN
R/W
0
7
FAULT0_EN
R/W
0
6
ACOMP_G_EN
R/W
0
5
ACOMP_F_EN
R/W
0
Bit Number
Bit Name
Access
Default
4
ACOMP_E_EN
R/W
0
3
ACOMP_D_EN
R/W
0
2
ACOMP_C_EN
R/W
0
1
ACOMP_B_EN
R/W
0
0
ACOMP_A_EN
R/W
0
Bit 14: DCOMP3_EN – Enables Digital Comparator 3 result for DPWM 1 Fault
AB Detection
0 = Digital Comparator 3 disabled for Fault AB detection (Default)
1 = Digital Comparator 3 enabled for Fault AB detection
Bit 13: DCOMP2_EN – Enables Digital Comparator 2 result for DPWM 1 Fault
AB Detection
0 = Digital Comparator 2 disabled for Fault AB detection (Default)
1 = Digital Comparator 2 enabled for Fault AB detection
Bit 12: DCOMP1_EN – Enables Digital Comparator 1 result for DPWM 1 Fault
AB Detection
0 = Digital Comparator 1 disabled for Fault AB detection (Default)
1 = Digital Comparator 1 enabled for Fault AB detection
Bit 11: DCOMP0_EN – Enables Digital Comparator 0 result for DPWM 1 Fault
AB Detection
0 = Digital Comparator 0 disabled for Fault AB detection (Default)
1 = Digital Comparator 0 enabled for Fault AB detection
Bit 10: FAULT3_EN – Enables FAULT[3] pin for DPWM 1 Fault AB detection
0 = External Fault pin disabled for Fault AB detection (Default)
1 = External Fault pin enabled for Fault AB detection
Bit 9: FAULT2_EN – Enables FAULT[2] pin for DPWM 1 Fault AB detection
0 = External Fault pin disabled for Fault AB detection (Default)
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1 = External Fault pin enabled for Fault AB detection
Bit 8: FAULT1_EN – Enables FAULT[1] pin for DPWM 1 Fault AB detection
0 = External Fault pin disabled for Fault AB detection (Default)
1 = External Fault pin enabled for Fault AB detection
Bit 7: FAULT0_EN – Enables FAULT[0] pin for DPWM 1 Fault AB detection
0 = External Fault pin disabled for Fault AB detection (Default)
1 = External Fault pin enabled for Fault AB detection
Bit 6: ACOMP_G_EN – Enables Analog Comparator G result for DPWM 1
Fault AB detection
0 = Analog Comparator result disabled for Fault AB detection (Default)
1 = Analog Comparator result enabled for Fault AB detection
Bit 5: ACOMP_F_EN – Enables Analog Comparator F result for DPWM 1 Fault
AB detection
0 = Analog Comparator result disabled for Fault AB detection (Default)
1 = Analog Comparator result enabled for Fault AB detection
Bit 4: ACOMP_E_EN – Enables Analog Comparator E result for DPWM 1 Fault
AB detection
0 = Analog Comparator result disabled for Fault AB detection (Default)
1 = Analog Comparator result enabled for Fault AB detection
Bit 3: ACOMP_D_EN – Enables Analog Comparator D result for DPWM 1
Fault AB detection
0 = Analog Comparator result disabled for Fault AB detection (Default)
1 = Analog Comparator result enabled for Fault AB detection
Bit 2: ACOMP_C_EN – Enables Analog Comparator C result for DPWM 1
Fault AB detection
0 = Analog Comparator result disabled for Fault AB detection (Default)
1 = Analog Comparator result enabled for Fault AB detection
Bit 1: ACOMP_B_EN – Enables Analog Comparator B result for DPWM 1
Fault AB detection
0 = Analog Comparator result disabled for Fault AB detection (Default)
1 = Analog Comparator result enabled for Fault AB detection
Bit 0: ACOMP_A_EN – Enables Analog Comparator A result for DPWM 1
Fault AB detection
0 = Analog Comparator result disabled for Fault AB detection (Default)
1 = Analog Comparator result enabled for Fault AB detection
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4.2.20 DPWM 1 Fault Detection Register (DPWM1FAULTDET)
Address 0x0013004C
Bit Number
Bit Name
Access
Default
30
PWMB_DCOMP3_EN
R/W
0
29
PWMB_DCOMP2_EN
R/W
0
28
PWMB_DCOMP1_EN
R/W
0
Bit Number
Bit Name
Access
Default
27
PWMB_DCOMP0_EN
R/W
0
26
PWMB_FAULT3_EN
R/W
0
25
PWMB_FAULT2_EN
R/W
0
Bit Number
Bit Name
Access
Default
24
PWMB_FAULT1_EN
R/W
0
23
PWMB_FAULT0_EN
R/W
0
22
PWMB_ACOMP_G_EN
R/W
0
Bit Number
Bit Name
Access
Default
21
PWMB_ACOMP_F_EN
R/W
0
20
PWMB_ACOMP_E_EN
R/W
0
19
PWMB_ACOMP_D_EN
R/W
0
Bit Number
18
17
PWMB_ACOMP_B_E
N
R/W
0
16
Bit Name
Access
Default
Bit Number
Bit Name
Access
Default
Bit Number
Bit Name
Access
Default
84
PWMB_ACOMP_C_EN
R/W
0
15
RESERVED
0
13
PWMA_DCOMP2_EN
R/W
0
UCD3138064A Migration Guide
PWMB_ACOMP_A_EN
R/W
0
14
PWMA_DCOMP3_EN
R/W
0
12
PWMA_DCOMP1_EN
R/W
0
11
PWMA_DCOMP0_EN
R/W
0
SLUA766
Bit Number
Bit Name
Access
Default
10
PWMA_FAULT3_EN
R/W
0
9
PWMA_FAULT2_EN
R/W
0
Bit Number
Bit Name
Access
Default
8
PWMA_FAULT1_EN
R/W
0
7
PWMA_FAULT0_EN
R/W
0
6
PWMA_ACOMP_G_EN
R/W
0
Bit Number
Bit Name
Access
Default
5
PWMA_ACOMP_F_EN
R/W
0
4
PWMA_ACOMP_E_EN
R/W
0
3
PWMA_ACOMP_D_EN
R/W
0
Bit Number
Bit Name
Access
Default
2
PWMA_ACOMP_C_EN
R/W
0
1
PWMA_ACOMP_B_EN
R/W
0
0
PWMA_ACOMP_A_EN
R/W
0
Bit 30: PWMB_DCOMP3_EN – Enables Digital Comparator 3 result for
DPWM 1 PWM-B Fault Detection
0 = Digital Comparator 3 disabled for fault detection (Default)
1 = Digital Comparator 3 enabled for fault detection
Bit 29: PWMB_DCOMP2_EN – Enables Digital Comparator 2 result for
DPWM 1 PWM-B Fault Detection
0 = Digital Comparator 2 disabled for fault detection (Default)
1 = Digital Comparator 2 enabled for fault detection
Bit 28: PWMB_DCOMP1_EN – Enables Digital Comparator 1 result for
DPWM 1 PWM-B Fault Detection
0 = Digital Comparator 1 disabled for fault detection (Default)
1 = Digital Comparator 1 enabled for fault detection
Bit 27: PWMB_DCOMP0_EN – Enables Digital Comparator 0 result for
DPWM 1 PWM-B Fault Detection
0 = Digital Comparator 0 disabled for fault detection (Default)
1 = Digital Comparator 0 enabled for fault detection
Bit 26: PWMB_FAULT3_EN – Enables FAULT[3] pin for DPWM 1 PWM-B
Fault Detection
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0 = External Fault pin disabled for fault detection (Default)
1 = External Fault pin enabled for fault detection
Bit 25: PWMB_FAULT2_EN – Enables FAULT[2] pin for DPWM 1 PWM-B
Fault Detection
0 = External Fault pin disabled for fault detection (Default)
1 = External Fault pin enabled for fault detection
Bit 24: PWMB_FAULT1_EN – Enables FAULT[1] pin for DPWM 1 PWM-B
Fault Detection
0 = External Fault pin disabled for fault detection (Default)
1 = External Fault pin enabled for fault detection
Bit 23: PWMB_FAULT0_EN – Enables FAULT[0] pin for DPWM 1 PWM-B
Fault Detection
0 = External Fault pin disabled for fault detection (Default)
1 = External Fault pin enabled for fault detection
Bit 22: PWMB_ACOMP_G_EN – Enables Analog Comparator G result for
DPWM 1 PWM-B Fault detection
0 = Analog Comparator result disabled for fault detection (Default)
1 = Analog Comparator result enabled for fault detection
Bit 21: PWMB_ACOMP_F_EN – Enables Analog Comparator F result for
DPWM 1 PWM-B Fault detection
0 = Analog Comparator result disabled for fault detection (Default)
1 = Analog Comparator result enabled for fault detection
Bit 20: PWMB_ACOMP_E_EN – Enables Analog Comparator E result for
DPWM 1 PWM-B Fault detection
0 = Analog Comparator result disabled for fault detection (Default)
1 = Analog Comparator result enabled for fault detection
Bit 19: PWMB_ACOMP_D_EN – Enables Analog Comparator D result for
DPWM 1 PWM-B Fault detection
0 = Analog Comparator result disabled for fault detection (Default)
1 = Analog Comparator result enabled for fault detection
Bit 18: PWMB_ACOMP_C_EN – Enables Analog Comparator C result for
DPWM 1 PWM-B Fault detection
0 = Analog Comparator result disabled for fault detection (Default)
1 = Analog Comparator result enabled for fault detection
Bit 17: PWMB_ACOMP_B_EN – Enables Analog Comparator B result for
DPWM 1 PWM-B Fault detection
0 = Analog Comparator result disabled for fault detection (Default)
1 = Analog Comparator result enabled for fault detection
Bit 16: PWMB_ACOMP_A_EN – Enables Analog Comparator A result for
DPWM 1 PWM-B Fault detection
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0 = Analog Comparator result disabled for fault detection (Default)
1 = Analog Comparator result enabled for fault detection
Bit 15: RESERVED – Unused bit
Bit 14: PWMA_DCOMP3_EN – Enables Digital Comparator 3 result for
DPWM 1 PWM-A Fault Detection
0 = Digital Comparator 3 disabled for fault detection (Default)
1 = Digital Comparator 3 enabled for fault detection
Bit 13: PWMA_DCOMP2_EN – Enables Digital Comparator 2 result for
DPWM 1 PWM-A Fault Detection
0 = Digital Comparator 2 disabled for fault detection (Default)
1 = Digital Comparator 2 enabled for fault detection
Bit 12: PWMA_DCOMP1_EN – Enables Digital Comparator 1 result for
DPWM 1 PWM-A Fault Detection
0 = Digital Comparator 1 disabled for fault detection (Default)
1 = Digital Comparator 1 enabled for fault detection
Bit 11: PWMA_DCOMP0_EN – Enables Digital Comparator 0 result for
DPWM 1 PWM-A Fault Detection
0 = Digital Comparator 0 disabled for fault detection (Default)
1 = Digital Comparator 0 enabled for fault detection
Bit 10: PWMA_FAULT2_EN – Enables FAULT[2] pin for DPWM 1 PWM-A
Fault Detection
0 = External Fault pin disabled for fault detection (Default)
1 = External Fault pin enabled for fault detection
Bit 9: PWMA_FAULT2_EN – Enables FAULT[2] pin for DPWM 1 PWM-A
Fault Detection
0 = External Fault pin disabled for fault detection (Default)
1 = External Fault pin enabled for fault detection
Bit 8: PWMA_FAULT1_EN – Enables FAULT[1] pin for DPWM 1 PWM-A
Fault Detection
0 = External Fault pin disabled for fault detection (Default)
1 = External Fault pin enabled for fault detection
Bit 7: PWMA_FAULT0_EN – Enables FAULT[0] pin for DPWM 1 PWM-A
Fault Detection
0 = External Fault pin disabled for fault detection (Default)
1 = External Fault pin enabled for fault detection
Bit 6: PWMA_ACOMP_G_EN – Enables Analog Comparator G result for
DPWM 1 PWM-A Fault detection
0 = Analog Comparator result disabled for fault detection (Default)
1 = Analog Comparator result enabled for fault detection
Bit 5: PWMA_ACOMP_F_EN – Enables Analog Comparator F result for
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DPWM 1 PWM-A Fault detection
0 = Analog Comparator result disabled for fault detection (Default)
1 = Analog Comparator result enabled for fault detection
Bit 4: PWMA_ACOMP_E_EN – Enables Analog Comparator E result for
DPWM 1 PWM-A Fault detection
0 = Analog Comparator result disabled for fault detection (Default)
1 = Analog Comparator result enabled for fault detection
Bit 3: PWMA_ACOMP_D_EN – Enables Analog Comparator D result for
DPWM 1 PWM-A Fault detection
0 = Analog Comparator result disabled for fault detection (Default)
1 = Analog Comparator result enabled for fault detection
Bit 2: PWMA_ACOMP_C_EN – Enables Analog Comparator C result for
DPWM 1 PWM-A Fault detection
0 = Analog Comparator result disabled for fault detection (Default)
1 = Analog Comparator result enabled for fault detection
Bit 1: PWMA_ACOMP_B_EN – Enables Analog Comparator B result for
DPWM 1 PWM-A Fault detection
0 = Analog Comparator result disabled for fault detection (Default)
1 = Analog Comparator result enabled for fault detection
Bit 0: PWMA_ACOMP_A_EN – Enables Analog Comparator A result for
DPWM 1 PWM-A Fault detection
0 = Analog Comparator result disabled for fault detection (Default)
1 = Analog Comparator result enabled for fault detection
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4.2.21 DPWM 1 IDE Detection Register (DPWM1IDEDET)
Address 0x00130050
Bit Number
Bit Name
Access
Default
6
ACOMP_G_EN
R/W
0
Bit Number
Bit Name
Access
Default
2
ACOMP_C_EN
R/W
0
5
ACOMP_F_EN
R/W
0
4
ACOMP_E_EN
R/W
0
1
ACOMP_B_EN
R/W
0
3
ACOMP_D_EN
R/W
0
0
ACOMP_A_EN
R/W
0
Bit 6: ACOMP_6_EN – Enables Analog Comparator G result for DPWM 1 IDE
detection
0 = Analog Comparator result disabled for IDE detection (Default)
1 = Analog Comparator result enabled for IDE detection
Bit 5: ACOMP_5_EN – Enables Analog Comparator F result for DPWM 1 IDE
detection
0 = Analog Comparator result disabled for IDE detection (Default)
1 = Analog Comparator result enabled for IDE detection
Bit 4: ACOMP_4_EN – Enables Analog Comparator E result for DPWM 1 IDE
detection
0 = Analog Comparator result disabled for IDE detection (Default)
1 = Analog Comparator result enabled for IDE detection
Bit 3: ACOMP_3_EN – Enables Analog Comparator D result for DPWM 1 IDE
detection
0 = Analog Comparator result disabled for IDE detection (Default)
1 = Analog Comparator result enabled for IDE detection
Bit 2: ACOMP_2_EN – Enables Analog Comparator C result for DPWM 1 IDE
detection
0 = Analog Comparator result disabled for IDE detection (Default)
1 = Analog Comparator result enabled for IDE detection
Bit 1: ACOMP_1_EN – Enables Analog Comparator B result for DPWM 1 IDE
detection
0 = Analog Comparator result disabled for IDE detection (Default)
1 = Analog Comparator result enabled for IDE detection
Bit 0: ACOMP_0_EN – Enables Analog Comparator A result for DPWM 1 IDE
detection
0 = Analog Comparator result disabled for IDE detection (Default)
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1 = Analog Comparator result enabled for IDE detection
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4.2.22 DPWM 2 Current Limit Control Register (DPWM2CLIM)
Address 0x00130054
Bit Number
Bit Name
Access
Default
16
ANALOG_PCM_EN
R/W
0
15
DCOMP3_EN
R/W
0
14
DCOMP2_EN
R/W
0
Bit Number
Bit Name
Access
Default
13
DCOMP1_EN
R/W
0
12
DCOMP0_EN
R/W
0
11
RESERVED
R
0
10
FAULT3_EN
R/W
0
9
FAULT2_EN
R/W
0
Bit Number
Bit Name
Access
Default
8
FAULT1_EN
R/W
0
7
FAULT0_EN
R/W
0
6
ACOMP_G_EN
R/W
0
5
ACOMP_F_EN
R/W
0
4
ACOMP_E_EN
R/W
0
Bit Number
Bit Name
Access
Default
3
ACOMP_D_EN
R/W
0
2
ACOMP_C_EN
R/W
0
1
ACOMP_B_EN
R/W
0
0
ACOMP_A_EN
R/W
0
Bit 16: ANALOG_PCM_EN – Enables Analog Peak Current detection result for
DPWM 2 Current Limit
0 = Analog Peak Current detection disabled for current limit (Default)
1 = Analog Peak Current detection enabled for current limit
Bit 15: DCOMP3_EN – Enables Digital Comparator 3 result for DPWM 2
Current Limit
0 = Digital Comparator 3 result disabled for current limit (Default)
1 = Digital Comparator 3 result enabled for current limit
Bit 14: DCOMP2_EN – Enables Digital Comparator 2 result for DPWM 2
Current Limit
0 = Digital Comparator 2 result disabled for current limit (Default)
1 = Digital Comparator 2 result enabled for current limit
Bit 13: DCOMP1_EN – Enables Digital Comparator 1 result for DPWM 2
Current Limit
0 = Digital Comparator 1 result disabled for current limit (Default)
1 = Digital Comparator 1 result enabled for current limit
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Bit 11: RESERVED – Unused Bit
Bit 12: DCOMP0_EN – Enables Digital Comparator 0 result for DPWM 2
Current Limit
0 = Digital Comparator 0 result disabled for current limit (Default)
1 = Digital Comparator 0 result enabled for current limit
Bit 10: FAULT3_EN – Enables FAULT[3] pin for DPWM 2 Current Limit
0 = External Fault pin disabled for current limit (Default)
1 = External Fault pin enabled for current limit
Bit 9: FAULT2_EN – Enables FAULT[2] pin for DPWM 2 Current Limit
0 = External Fault pin disabled for current limit (Default)
1 = External Fault pin enabled for current limit
Bit 8: FAULT1_EN – Enables FAULT[1] pin for DPWM 2 Current Limit
0 = External Fault pin disabled for current limit (Default)
1 = External Fault pin enabled for current limit
Bit 7: FAULT0_EN – Enables FAULT[0] pin for DPWM 2 Current Limit
0 = External Fault pin disabled for current limit (Default)
1 = External Fault pin enabled for current limit
Bit 6: ACOMP_G_EN – Enables Analog Comparator G result for DPWM 2
Current Limit
0 = Analog Comparator result disabled for current limit (Default)
1 = Analog Comparator result enabled for current limit
Bit 5: ACOMP_F_EN – Enables Analog Comparator F result for DPWM 2
Current Limit
0 = Analog Comparator result disabled for current limit (Default)
1 = Analog Comparator result enabled for current limit
Bit 4: ACOMP_E_EN – Enables Analog Comparator E result for DPWM 2
Current Limit
0 = Analog Comparator result disabled for current limit (Default)
1 = Analog Comparator result enabled for current limit
Bit 3: ACOMP_D_EN – Enables Analog Comparator D result for DPWM 2
Current Limit
0 = Analog Comparator result disabled for current limit (Default)
1 = Analog Comparator result enabled for current limit
Bit 2: ACOMP_C_EN – Enables Analog Comparator C result for DPWM 2
Current Limit
0 = Analog Comparator result disabled for current limit (Default)
1 = Analog Comparator result enabled for current limit
Bit 1: ACOMP_B_EN – Enables Analog Comparator B result for DPWM 2
Current Limit
0 = Analog Comparator result disabled for current limit (Default)
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1 = Analog Comparator result enabled for current limit
Bit 0: ACOMP_A_EN – Enables Analog Comparator A result for DPWM 2
Current Limit
0 = Analog Comparator result disabled for current limit (Default)
1 = Analog Comparator result enabled for current limit
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4.2.23 DPWM 2 Fault AB Detection Register (DPWM2FLTABDET)
Address 0x00130058
Bit Number
Bit Name
Access
Default
14
DCOMP3_EN
R/W
0
13
DCOMP2_EN
R/W
0
12
DCOMP1_EN
R/W
0
11
DCOMP0_EN
R/W
0
10
FAULT3_EN
R/W
0
Bit Number
Bit Name
Access
Default
9
FAULT2_EN
R/W
0
8
FAULT1_EN
R/W
0
7
FAULT0_EN
R/W
0
6
ACOMP_G_EN
R/W
0
5
ACOMP_F_EN
R/W
0
Bit Number
Bit Name
Access
Default
4
ACOMP_E_EN
R/W
0
3
ACOMP_D_EN
R/W
0
2
ACOMP_C_EN
R/W
0
1
ACOMP_B_EN
R/W
0
0
ACOMP_A_EN
R/W
0
Bit 14: DCOMP3_EN – Enables Digital Comparator 3 result for DPWM 2 Fault
AB Detection
0 = Digital Comparator 3 disabled for Fault AB detection (Default)
1 = Digital Comparator 3 enabled for Fault AB detection
Bit 13: DCOMP2_EN – Enables Digital Comparator 2 result for DPWM 2 Fault
AB Detection
0 = Digital Comparator 2 disabled for Fault AB detection (Default)
1 = Digital Comparator 2 enabled for Fault AB detection
Bit 12: DCOMP1_EN – Enables Digital Comparator 1 result for DPWM 2 Fault
AB Detection
0 = Digital Comparator 1 disabled for Fault AB detection (Default)
1 = Digital Comparator 1 enabled for Fault AB detection
Bit 11: DCOMP0_EN – Enables Digital Comparator 0 result for DPWM 2 Fault
AB Detection
0 = Digital Comparator 0 disabled for Fault AB detection (Default)
1 = Digital Comparator 0 enabled for Fault AB detection
Bit 10: FAULT3_EN – Enables FAULT[3] pin for DPWM 2 Fault AB detection
0 = External Fault pin disabled for Fault AB detection (Default)
1 = External Fault pin enabled for Fault AB detection
Bit 9: FAULT2_EN – Enables FAULT[2] pin for DPWM 2 Fault AB detection
0 = External Fault pin disabled for Fault AB detection (Default)
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1 = External Fault pin enabled for Fault AB detection
Bit 8: FAULT1_EN – Enables FAULT[1] pin for DPWM 2 Fault AB detection
0 = External Fault pin disabled for Fault AB detection (Default)
1 = External Fault pin enabled for Fault AB detection
Bit 7: FAULT0_EN – Enables FAULT[0] pin for DPWM 2 Fault AB detection
0 = External Fault pin disabled for Fault AB detection (Default)
1 = External Fault pin enabled for Fault AB detection
Bit 6: ACOMP_G_EN – Enables Analog Comparator G result for DPWM 2
Fault AB detection
0 = Analog Comparator result disabled for Fault AB detection (Default)
1 = Analog Comparator result enabled for Fault AB detection
Bit 5: ACOMP_F_EN – Enables Analog Comparator F result for DPWM 2 Fault
AB detection
0 = Analog Comparator result disabled for Fault AB detection (Default)
1 = Analog Comparator result enabled for Fault AB detection
Bit 4: ACOMP_E_EN – Enables Analog Comparator E result for DPWM 2 Fault
AB detection
0 = Analog Comparator result disabled for Fault AB detection (Default)
1 = Analog Comparator result enabled for Fault AB detection
Bit 3: ACOMP_D_EN – Enables Analog Comparator D result for DPWM 2
Fault AB detection
0 = Analog Comparator result disabled for Fault AB detection (Default)
1 = Analog Comparator result enabled for Fault AB detection
Bit 2: ACOMP_C_EN – Enables Analog Comparator C result for DPWM 2
Fault AB detection
0 = Analog Comparator result disabled for Fault AB detection (Default)
1 = Analog Comparator result enabled for Fault AB detection
Bit 1: ACOMP_B_EN – Enables Analog Comparator B result for DPWM 2
Fault AB detection
0 = Analog Comparator result disabled for Fault AB detection (Default)
1 = Analog Comparator result enabled for Fault AB detection
Bit 0: ACOMP_A_EN – Enables Analog Comparator A result for DPWM 2
Fault AB detection
0 = Analog Comparator result disabled for Fault AB detection (Default)
1 = Analog Comparator result enabled for Fault AB detection
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4.2.24 DPWM 2 Fault Detection Register (DPWM2FAULTDET)
Address 0x0013005C
Bit Number
Bit Name
Access
Default
30
PWMB_DCOMP3_EN
R/W
0
29
PWMB_DCOMP2_EN
R/W
0
28
PWMB_DCOMP1_EN
R/W
0
Bit Number
Bit Name
Access
Default
27
PWMB_DCOMP0_EN
R/W
0
26
PWMB_FAULT3_EN
R/W
0
25
PWMB_FAULT2_EN
R/W
0
Bit Number
Bit Name
Access
Default
24
PWMB_FAULT1_EN
R/W
0
23
PWMB_FAULT0_EN
R/W
0
22
PWMB_ACOMP_G_EN
R/W
0
Bit Number
Bit Name
Access
Default
21
PWMB_ACOMP_F_EN
R/W
0
20
PWMB_ACOMP_E_EN
R/W
0
19
PWMB_ACOMP_D_EN
R/W
0
Bit Number
Bit Name
Access
Default
18
PWMB_ACOMP_C_EN
R/W
0
17
PWMB_ACOMP_B_EN
R/W
0
16
PWMB_ACOMP_A_EN
R/W
0
Bit Number
Bit Name
Access
Default
Bit Number
Bit Name
Access
Default
96
15
RESERVED
0
13
PWMA_DCOMP2_EN
R/W
0
UCD3138064A Migration Guide
14
PWMA_DCOMP3_EN
R/W
0
12
PWMA_DCOMP1_EN
R/W
0
11
PWMA_DCOMP0_EN
R/W
0
SLUA766
Bit Number
Bit Name
Access
Default
10
PWMA_FAULT3_EN
R/W
0
9
PWMA_FAULT2_EN
R/W
0
Bit Number
Bit Name
Access
Default
8
PWMA_FAULT1_EN
R/W
0
7
PWMA_FAULT0_EN
R/W
0
6
PWMA_ACOMP_G_EN
R/W
0
Bit Number
Bit Name
Access
Default
5
PWMA_ACOMP_F_EN
R/W
0
4
PWMA_ACOMP_E_EN
R/W
0
3
PWMA_ACOMP_D_EN
R/W
0
Bit Number
Bit Name
Access
Default
2
PWMA_ACOMP_C_EN
R/W
0
1
PWMA_ACOMP_B_EN
R/W
0
0
PWMA_ACOMP_A_EN
R/W
0
Bit 30: PWMB_DCOMP3_EN – Enables Digital Comparator 3 result for
DPWM 2 PWM-B Fault Detection
0 = Digital Comparator 3 disabled for fault detection (Default)
1 = Digital Comparator 3 enabled for fault detection
Bit 29: PWMB_DCOMP2_EN – Enables Digital Comparator 2 result for
DPWM 2 PWM-B Fault Detection
0 = Digital Comparator 2 disabled for fault detection (Default)
1 = Digital Comparator 2 enabled for fault detection
Bit 28: PWMB_DCOMP1_EN – Enables Digital Comparator 1 result for
DPWM 2 PWM-B Fault Detection
0 = Digital Comparator 1 disabled for fault detection (Default)
1 = Digital Comparator 1 enabled for fault detection
Bit 27: PWMB_DCOMP0_EN – Enables Digital Comparator 0 result for
DPWM 2 PWM-B Fault Detection
0 = Digital Comparator 0 disabled for fault detection (Default)
1 = Digital Comparator 0 enabled for fault detection
Bit 26: PWMB_FAULT3_EN – Enables FAULT[3] pin for DPWM 2 PWM-B
Fault Detection
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0 = External Fault pin disabled for fault detection (Default)
1 = External Fault pin enabled for fault detection
Bit 25: PWMB_FAULT2_EN – Enables FAULT[2] pin for DPWM 2 PWM-B
Fault Detection
0 = External Fault pin disabled for fault detection (Default)
1 = External Fault pin enabled for fault detection
Bit 24: PWMB_FAULT1_EN – Enables FAULT[1] pin for DPWM 2 PWM-B
Fault Detection
0 = External Fault pin disabled for fault detection (Default)
1 = External Fault pin enabled for fault detection
Bit 23: PWMB_FAULT0_EN – Enables FAULT[0] pin for DPWM 2 PWM-B
Fault Detection
0 = External Fault pin disabled for fault detection (Default)
1 = External Fault pin enabled for fault detection
Bit 22: PWMB_ACOMP_G_EN – Enables Analog Comparator G result for
DPWM 2 PWM-B Fault detection
0 = Analog Comparator result disabled for fault detection (Default)
1 = Analog Comparator result enabled for fault detection
Bit 21: PWMB_ACOMP_F_EN – Enables Analog Comparator F result for
DPWM 2 PWM-B Fault detection
0 = Analog Comparator result disabled for fault detection (Default)
1 = Analog Comparator result enabled for fault detection
Bit 20: PWMB_ACOMP_E_EN – Enables Analog Comparator E result for
DPWM 2 PWM-B Fault detection
0 = Analog Comparator result disabled for fault detection (Default)
1 = Analog Comparator result enabled for fault detection
Bit 19: PWMB_ACOMP_D_EN – Enables Analog Comparator D result for
DPWM 2 PWM-B Fault detection
0 = Analog Comparator result disabled for fault detection (Default)
1 = Analog Comparator result enabled for fault detection
Bit 18: PWMB_ACOMP_C_EN – Enables Analog Comparator C result for
DPWM 2 PWM-B Fault detection
0 = Analog Comparator result disabled for fault detection (Default)
1 = Analog Comparator result enabled for fault detection
Bit 17: PWMB_ACOMP_B_EN – Enables Analog Comparator B result for
DPWM 2 PWM-B Fault detection
0 = Analog Comparator result disabled for fault detection (Default)
1 = Analog Comparator result enabled for fault detection
Bit 16: PWMB_ACOMP_A_EN – Enables Analog Comparator A result for
DPWM 2 PWM-B Fault detection
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0 = Analog Comparator result disabled for fault detection (Default)
1 = Analog Comparator result enabled for fault detection
Bit 15: RESERVED – Unused bit
Bit 14: PWMA_DCOMP3_EN – Enables Digital Comparator 3 result for
DPWM 2 PWM-A Fault Detection
0 = Digital Comparator 3 disabled for fault detection (Default)
1 = Digital Comparator 3 enabled for fault detection
Bit 13: PWMA_DCOMP2_EN – Enables Digital Comparator 2 result for
DPWM 2 PWM-A Fault Detection
0 = Digital Comparator 2 disabled for fault detection (Default)
1 = Digital Comparator 2 enabled for fault detection
Bit 12: PWMA_DCOMP1_EN – Enables Digital Comparator 1 result for
DPWM 2 PWM-A Fault Detection
0 = Digital Comparator 1 disabled for fault detection (Default)
1 = Digital Comparator 1 enabled for fault detection
Bit 11: PWMA_DCOMP0_EN – Enables Digital Comparator 0 result for
DPWM 2 PWM-A Fault Detection
0 = Digital Comparator 0 disabled for fault detection (Default)
1 = Digital Comparator 0 enabled for fault detection
Bit 10: PWMA_FAULT3_EN – Enables FAULT[3] pin for DPWM 2 PWM-A
Fault Detection
0 = External Fault pin disabled for fault detection (Default)
1 = External Fault pin enabled for fault detection
Bit 9: PWMA_FAULT2_EN – Enables FAULT[2] pin for DPWM 2 PWM-A
Fault Detection
0 = External Fault pin disabled for fault detection (Default)
1 = External Fault pin enabled for fault detection
Bit 8: PWMA_FAULT1_EN – Enables FAULT[1] pin for DPWM 2 PWM-A
Fault Detection
0 = External Fault pin disabled for fault detection (Default)
1 = External Fault pin enabled for fault detection
Bit 7: PWMA_FAULT0_EN – Enables FAULT[0] pin for DPWM 2 PWM-A
Fault Detection
0 = External Fault pin disabled for fault detection (Default)
1 = External Fault pin enabled for fault detection
Bit 6: PWMA_ACOMP_G_EN – Enables Analog Comparator G result for
DPWM 2 PWM-A Fault detection
0 = Analog Comparator result disabled for fault detection (Default)
1 = Analog Comparator result enabled for fault detection
Bit 5: PWMA_ACOMP_F_EN – Enables Analog Comparator F result for
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DPWM 2 PWM-A Fault detection
0 = Analog Comparator result disabled for fault detection (Default)
1 = Analog Comparator result enabled for fault detection
Bit 4: PWMA_ACOMP_E_EN – Enables Analog Comparator E result for
DPWM 2 PWM-A Fault detection
0 = Analog Comparator result disabled for fault detection (Default)
1 = Analog Comparator result enabled for fault detection
Bit 3: PWMA_ACOMP_D_EN – Enables Analog Comparator D result for
DPWM 2 PWM-A Fault detection
0 = Analog Comparator result disabled for fault detection (Default)
1 = Analog Comparator result enabled for fault detection
Bit 2: PWMA_ACOMP_C_EN – Enables Analog Comparator C result for
DPWM 2 PWM-A Fault detection
0 = Analog Comparator result disabled for fault detection (Default)
1 = Analog Comparator result enabled for fault detection
Bit 1: PWMA_ACOMP_B_EN – Enables Analog Comparator B result for
DPWM 2 PWM-A Fault detection
0 = Analog Comparator result disabled for fault detection (Default)
1 = Analog Comparator result enabled for fault detection
Bit 0: PWMA_ACOMP_A_EN – Enables Analog Comparator A result for
DPWM 2 PWM-A Fault detection
0 = Analog Comparator result disabled for fault detection (Default)
1 = Analog Comparator result enabled for fault detection
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4.2.25 DPWM 2 IDE Detection Register (DPWM2IDEDET)
Address 0x00130060
Bit Number
Bit Name
Access
Default
6
ACOMP_G_EN
R/W
0
Bit Number
Bit Name
Access
Default
2
ACOMP_C_EN
R/W
0
5
ACOMP_F_EN
R/W
0
4
ACOMP_E_EN
R/W
0
1
ACOMP_B_EN
R/W
0
3
ACOMP_D_EN
R/W
0
0
ACOMP_A_EN
R/W
0
Bit 6: ACOMP_6_EN – Enables Analog Comparator G result for DPWM 2 IDE
detection
0 = Analog Comparator result disabled for IDE detection (Default)
1 = Analog Comparator result enabled for IDE detection
Bit 5: ACOMP_5_EN – Enables Analog Comparator F result for DPWM 2 IDE
detection
0 = Analog Comparator result disabled for IDE detection (Default)
1 = Analog Comparator result enabled for IDE detection
Bit 4: ACOMP_4_EN – Enables Analog Comparator E result for DPWM 2 IDE
detection
0 = Analog Comparator result disabled for IDE detection (Default)
1 = Analog Comparator result enabled for IDE detection
Bit 3: ACOMP_3_EN – Enables Analog Comparator D result for DPWM 2 IDE
detection
0 = Analog Comparator result disabled for IDE detection (Default)
1 = Analog Comparator result enabled for IDE detection
Bit 2: ACOMP_2_EN – Enables Analog Comparator C result for DPWM 2 IDE
detection
0 = Analog Comparator result disabled for IDE detection (Default)
1 = Analog Comparator result enabled for IDE detection
Bit 1: ACOMP_1_EN – Enables Analog Comparator B result for DPWM 2 IDE
detection
0 = Analog Comparator result disabled for IDE detection (Default)
1 = Analog Comparator result enabled for IDE detection
Bit 0: ACOMP_0_EN – Enables Analog Comparator A result for DPWM 2 IDE
detection
0 = Analog Comparator result disabled for IDE detection (Default)
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1 = Analog Comparator result enabled for IDE detection
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4.2.26 DPWM 3 Current Limit Control Register (DPWM3CLIM)
Address 0x00130064
Bit Number
Bit Name
Access
Default
16
ANALOG_PCM_EN
R/W
0
15
DCOMP3_EN
R/W
0
14
DCOMP2_EN
R/W
0
Bit Number
Bit Name
Access
Default
13
DCOMP1_EN
R/W
0
12
DCOMP0_EN
R/W
0
11
RESERVED
R
0
10
FAULT3_EN
R/W
0
9
FAULT2_EN
R/W
0
Bit Number
Bit Name
Access
Default
8
FAULT1_EN
R/W
0
7
FAULT0_EN
R/W
0
6
ACOMP_G_EN
R/W
0
5
ACOMP_F_EN
R/W
0
4
ACOMP_E_EN
R/W
0
Bit Number
Bit Name
Access
Default
3
ACOMP_D_EN
R/W
0
2
ACOMP_C_EN
R/W
0
1
ACOMP_B_EN
R/W
0
0
ACOMP_A_EN
R/W
0
Bit 16: ANALOG_PCM_EN – Enables Analog Peak Current detection result for
DPWM 2 Current Limit
0 = Analog Peak Current detection disabled for current limit (Default)
1 = Analog Peak Current detection enabled for current limit
Bit 15: DCOMP3_EN – Enables Digital Comparator 3 result for DPWM 3
Current Limit
0 = Digital Comparator 3 result disabled for current limit (Default)
1 = Digital Comparator 3 result enabled for current limit
Bit 14: DCOMP2_EN – Enables Digital Comparator 2 result for DPWM 3
Current Limit
0 = Digital Comparator 2 result disabled for current limit (Default)
1 = Digital Comparator 2 result enabled for current limit
Bit 13: DCOMP1_EN – Enables Digital Comparator 1 result for DPWM 3
Current Limit
0 = Digital Comparator 1 result disabled for current limit (Default)
1 = Digital Comparator 1 result enabled for current limit
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Bit 12: DCOMP0_EN – Enables Digital Comparator 0 result for DPWM 3
Current Limit
0 = Digital Comparator 0 result disabled for current limit (Default)
1 = Digital Comparator 0 result enabled for current limit
Bit 11: RESERVED – Unused Bit
Bit 10: FAULT3_EN – Enables FAULT[3] pin for DPWM 3 Current Limit
0 = External Fault pin disabled for current limit (Default)
1 = External Fault pin enabled for current limit
Bit 9: FAULT2_EN – Enables FAULT[2] pin for DPWM 3 Current Limit
0 = External Fault pin disabled for current limit (Default)
1 = External Fault pin enabled for current limit
Bit 8: FAULT1_EN – Enables FAULT[1] pin for DPWM 3 Current Limit
0 = External Fault pin disabled for current limit (Default)
1 = External Fault pin enabled for current limit
Bit 7: FAULT0_EN – Enables FAULT[0] pin for DPWM 3 Current Limit
0 = External Fault pin disabled for current limit (Default)
1 = External Fault pin enabled for current limit
Bit 6: ACOMP_G_EN – Enables Analog Comparator G result for DPWM 3
Current Limit
0 = Analog Comparator result disabled for current limit (Default)
1 = Analog Comparator result enabled for current limit
Bit 5: ACOMP_F_EN – Enables Analog Comparator F result for DPWM 3
Current Limit
0 = Analog Comparator result disabled for current limit (Default)
1 = Analog Comparator result enabled for current limit
Bit 4: ACOMP_E_EN – Enables Analog Comparator E result for DPWM 3
Current Limit
0 = Analog Comparator result disabled for current limit (Default)
1 = Analog Comparator result enabled for current limit
Bit 3: ACOMP_D_EN – Enables Analog Comparator D result for DPWM 3
Current Limit
0 = Analog Comparator result disabled for current limit (Default)
1 = Analog Comparator result enabled for current limit
Bit 2: ACOMP_C_EN – Enables Analog Comparator C result for DPWM 3
Current Limit
0 = Analog Comparator result disabled for current limit (Default)
1 = Analog Comparator result enabled for current limit
Bit 1: ACOMP_B_EN – Enables Analog Comparator B result for DPWM 3
Current Limit
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0 = Analog Comparator result disabled for current limit (Default)
1 = Analog Comparator result enabled for current limit
Bit 0: ACOMP_A_EN – Enables Analog Comparator A result for DPWM 3
Current Limit
0 = Analog Comparator result disabled for current limit (Default)
1 = Analog Comparator result enabled for current limit
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4.2.27 DPWM 3 Fault AB Detection Register (DPWM3FLTABDET)
Address 0x00130068
Bit Number
Bit Name
Access
Default
14
DCOMP3_EN
R/W
0
13
DCOMP2_EN
R/W
0
12
DCOMP1_EN
R/W
0
11
DCOMP0_EN
R/W
0
10
FAULT3_EN
R/W
0
Bit Number
Bit Name
Access
Default
9
FAULT2_EN
R/W
0
8
FAULT1_EN
R/W
0
7
FAULT0_EN
R/W
0
6
ACOMP_G_EN
R/W
0
5
ACOMP_F_EN
R/W
0
Bit Number
Bit Name
Access
Default
4
ACOMP_E_EN
R/W
0
3
ACOMP_D_EN
R/W
0
2
ACOMP_C_EN
R/W
0
1
ACOMP_B_EN
R/W
0
0
ACOMP_A_EN
R/W
0
Bit 14: DCOMP3_EN – Enables Digital Comparator 3 result for DPWM 3 Fault
AB Detection
0 = Digital Comparator 3 disabled for Fault AB detection (Default)
1 = Digital Comparator 3 enabled for Fault AB detection
Bit 13: DCOMP2_EN – Enables Digital Comparator 2 result for DPWM 3 Fault
AB Detection
0 = Digital Comparator 2 disabled for Fault AB detection (Default)
1 = Digital Comparator 2 enabled for Fault AB detection
Bit 12: DCOMP1_EN – Enables Digital Comparator 1 result for DPWM 3 Fault
AB Detection
0 = Digital Comparator 1 disabled for Fault AB detection (Default)
1 = Digital Comparator 1 enabled for Fault AB detection
Bit 11: DCOMP0_EN – Enables Digital Comparator 0 result for DPWM 3 Fault
AB Detection
0 = Digital Comparator 0 disabled for Fault AB detection (Default)
1 = Digital Comparator 0 enabled for Fault AB detection
Bit 10: FAULT3_EN – Enables FAULT[3] pin for DPWM 3 Fault AB detection
0 = External Fault pin disabled for Fault AB detection (Default)
1 = External Fault pin enabled for Fault AB detection
Bit 9: FAULT2_EN – Enables FAULT[2] pin for DPWM 3 Fault AB detection
0 = External Fault pin disabled for Fault AB detection (Default)
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1 = External Fault pin enabled for Fault AB detection
Bit 8: FAULT1_EN – Enables FAULT[1] pin for DPWM 3 Fault AB detection
0 = External Fault pin disabled for Fault AB detection (Default)
1 = External Fault pin enabled for Fault AB detection
Bit 7: FAULT0_EN – Enables FAULT[0] pin for DPWM 3 Fault AB detection
0 = External Fault pin disabled for Fault AB detection (Default)
1 = External Fault pin enabled for Fault AB detection
Bit 6: ACOMP_G_EN – Enables Analog Comparator G result for DPWM 3
Fault AB detection
0 = Analog Comparator result disabled for Fault AB detection (Default)
1 = Analog Comparator result enabled for Fault AB detection
Bit 5: ACOMP_F_EN – Enables Analog Comparator F result for DPWM 3 Fault
AB detection
0 = Analog Comparator result disabled for Fault AB detection (Default)
1 = Analog Comparator result enabled for Fault AB detection
Bit 4: ACOMP_E_EN – Enables Analog Comparator E result for DPWM 3 Fault
AB detection
0 = Analog Comparator result disabled for Fault AB detection (Default)
1 = Analog Comparator result enabled for Fault AB detection
Bit 3: ACOMP_D_EN – Enables Analog Comparator D result for DPWM 3
Fault AB detection
0 = Analog Comparator result disabled for Fault AB detection (Default)
1 = Analog Comparator result enabled for Fault AB detection
Bit 2: ACOMP_C_EN – Enables Analog Comparator C result for DPWM 3
Fault AB detection
0 = Analog Comparator result disabled for Fault AB detection (Default)
1 = Analog Comparator result enabled for Fault AB detection
Bit 1: ACOMP_B_EN – Enables Analog Comparator B result for DPWM 3
Fault AB detection
0 = Analog Comparator result disabled for Fault AB detection (Default)
1 = Analog Comparator result enabled for Fault AB detection
Bit 0: ACOMP_A_EN – Enables Analog Comparator A result for DPWM 3
Fault AB detection
0 = Analog Comparator result disabled for Fault AB detection (Default)
1 = Analog Comparator result enabled for Fault AB detection
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4.2.28 DPWM 3 Fault Detection Register (DPWM3FAULTDET)
Address 0x0013006C
Bit Number
Bit Name
Access
Default
30
PWMB_DCOMP3_EN
R/W
0
29
PWMB_DCOMP2_EN
R/W
0
28
PWMB_DCOMP1_EN
R/W
0
Bit Number
Bit Name
Access
Default
27
PWMB_DCOMP0_EN
R/W
0
26
PWMB_FAULT3_EN
R/W
0
25
PWMB_FAULT2_EN
R/W
0
Bit Number
Bit Name
Access
Default
24
PWMB_FAULT1_EN
R/W
0
23
PWMB_FAULT0_EN
R/W
0
22
PWMB_ACOMP_G_EN
R/W
0
Bit Number
Bit Name
Access
Default
21
PWMB_ACOMP_F_EN
R/W
0
20
PWMB_ACOMP_E_EN
R/W
0
19
PWMB_ACOMP_D_EN
R/W
0
Bit Number
Bit Name
Access
Default
Bit Number
Bit Name
Access
Default
Bit Number
Bit Name
Access
Default
108
18
PWMB_ACOMP_C_EN
R/W
0
15
RESERVED
0
13
PWMA_DCOMP2_EN
R/W
0
UCD3138064A Migration Guide
17
PWMB_ACOMP_B_EN
R/W
0
16
PWMB_ACOMP_A_EN
R/W
0
14
PWMA_DCOMP3_EN
R/W
0
12
PWMA_DCOMP1_EN
R/W
0
11
PWMA_DCOMP0_EN
R/W
0
SLUA766
Bit Number
Bit Name
Access
Default
10
PWMA_FAULT3_EN
R/W
0
9
PWMA_FAULT2_EN
R/W
0
Bit Number
Bit Name
Access
Default
8
PWMA_FAULT1_EN
R/W
0
7
PWMA_FAULT0_EN
R/W
0
6
PWMA_ACOMP_G_EN
R/W
0
Bit Number
Bit Name
Access
Default
5
PWMA_ACOMP_F_EN
R/W
0
4
PWMA_ACOMP_E_EN
R/W
0
3
PWMA_ACOMP_D_EN
R/W
0
Bit Number
Bit Name
Access
Default
2
PWMA_ACOMP_C_EN
R/W
0
1
PWMA_ACOMP_B_EN
R/W
0
0
PWMA_ACOMP_A_EN
R/W
0
Bit 30: PWMB_DCOMP3_EN – Enables Digital Comparator 3 result for
DPWM 3 PWM-B Fault Detection
0 = Digital Comparator 3 disabled for fault detection (Default)
1 = Digital Comparator 3 enabled for fault detection
Bit 29: PWMB_DCOMP2_EN – Enables Digital Comparator 2 result for
DPWM 3 PWM-B Fault Detection
0 = Digital Comparator 2 disabled for fault detection (Default)
1 = Digital Comparator 2 enabled for fault detection
Bit 28: PWMB_DCOMP1_EN – Enables Digital Comparator 1 result for
DPWM 3 PWM-B Fault Detection
0 = Digital Comparator 1 disabled for fault detection (Default)
1 = Digital Comparator 1 enabled for fault detection
Bit 27: PWMB_DCOMP0_EN – Enables Digital Comparator 0 result for
DPWM 3 PWM-B Fault Detection
0 = Digital Comparator 0 disabled for fault detection (Default)
1 = Digital Comparator 0 enabled for fault detection
Bit 26: PWMB_FAULT3_EN – Enables FAULT[3] pin for DPWM 3 PWM-B
Fault Detection
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0 = External Fault pin disabled for fault detection (Default)
1 = External Fault pin enabled for fault detection
Bit 25: PWMB_FAULT2_EN – Enables FAULT[2] pin for DPWM 3 PWM-B
Fault Detection
0 = External Fault pin disabled for fault detection (Default)
1 = External Fault pin enabled for fault detection
Bit 24: PWMB_FAULT1_EN – Enables FAULT[1] pin for DPWM 3 PWM-B
Fault Detection
0 = External Fault pin disabled for fault detection (Default)
1 = External Fault pin enabled for fault detection
Bit 23: PWMB_FAULT0_EN – Enables FAULT[0] pin for DPWM 3 PWM-B
Fault Detection
0 = External Fault pin disabled for fault detection (Default)
1 = External Fault pin enabled for fault detection
Bit 22: PWMB_ACOMP_G_EN – Enables Analog Comparator G result for
DPWM 3 PWM-B Fault detection
0 = Analog Comparator result disabled for fault detection (Default)
1 = Analog Comparator result enabled for fault detection
Bit 21: PWMB_ACOMP_F_EN – Enables Analog Comparator F result for
DPWM 3 PWM-B Fault detection
0 = Analog Comparator result disabled for fault detection (Default)
1 = Analog Comparator result enabled for fault detection
Bit 20: PWMB_ACOMP_E_EN – Enables Analog Comparator E result for
DPWM 3 PWM-B Fault detection
0 = Analog Comparator result disabled for fault detection (Default)
1 = Analog Comparator result enabled for fault detection
Bit 19: PWMB_ACOMP_D_EN – Enables Analog Comparator D result for
DPWM 3 PWM-B Fault detection
0 = Analog Comparator result disabled for fault detection (Default)
1 = Analog Comparator result enabled for fault detection
Bit 18: PWMB_ACOMP_C_EN – Enables Analog Comparator C result for
DPWM 3 PWM-B Fault detection
0 = Analog Comparator result disabled for fault detection (Default)
1 = Analog Comparator result enabled for fault detection
Bit 17: PWMB_ACOMP_B_EN – Enables Analog Comparator B result for
DPWM 3 PWM-B Fault detection
0 = Analog Comparator result disabled for fault detection (Default)
1 = Analog Comparator result enabled for fault detection
Bit 16: PWMB_ACOMP_A_EN – Enables Analog Comparator A result for
DPWM 3 PWM-B Fault detection
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0 = Analog Comparator result disabled for fault detection (Default)
1 = Analog Comparator result enabled for fault detection
Bit 15: RESERVED – Unused bit
Bit 14: PWMA_DCOMP3_EN – Enables Digital Comparator 3 result for
DPWM 3 PWM-A Fault Detection
0 = Digital Comparator 3 disabled for fault detection (Default)
1 = Digital Comparator 3 enabled for fault detection
Bit 13: PWMA_DCOMP2_EN – Enables Digital Comparator 2 result for
DPWM 3 PWM-A Fault Detection
0 = Digital Comparator 2 disabled for fault detection (Default)
1 = Digital Comparator 2 enabled for fault detection
Bit 12: PWMA_DCOMP1_EN – Enables Digital Comparator 1 result for
DPWM 3 PWM-A Fault Detection
0 = Digital Comparator 1 disabled for fault detection (Default)
1 = Digital Comparator 1 enabled for fault detection
Bit 11: PWMA_DCOMP0_EN – Enables Digital Comparator 0 result for
DPWM 3 PWM-A Fault Detection
0 = Digital Comparator 0 disabled for fault detection (Default)
1 = Digital Comparator 0 enabled for fault detection
Bit 10: PWMA_FAULT3_EN – Enables FAULT[3] pin for DPWM 3 PWM-A
Fault Detection
0 = External Fault pin disabled for fault detection (Default)
1 = External Fault pin enabled for fault detection
Bit 9: PWMA_FAULT2_EN – Enables FAULT[2] pin for DPWM 3 PWM-A
Fault Detection
0 = External Fault pin disabled for fault detection (Default)
1 = External Fault pin enabled for fault detection
Bit 8: PWMA_FAULT1_EN – Enables FAULT[1] pin for DPWM 3 PWM-A
Fault Detection
0 = External Fault pin disabled for fault detection (Default)
1 = External Fault pin enabled for fault detection
Bit 7: PWMA_FAULT0_EN – Enables FAULT[0] pin for DPWM 3 PWM-A
Fault Detection
0 = External Fault pin disabled for fault detection (Default)
1 = External Fault pin enabled for fault detection
Bit 6: PWMA_ACOMP_G_EN – Enables Analog Comparator G result for
DPWM 3 PWM-A Fault detection
0 = Analog Comparator result disabled for fault detection (Default)
1 = Analog Comparator result enabled for fault detection
Bit 5: PWMA_ACOMP_F_EN – Enables Analog Comparator F result for
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DPWM 3 PWM-A Fault detection
0 = Analog Comparator result disabled for fault detection (Default)
1 = Analog Comparator result enabled for fault detection
Bit 4: PWMA_ACOMP_E_EN – Enables Analog Comparator E result for
DPWM 3 PWM-A Fault detection
0 = Analog Comparator result disabled for fault detection (Default)
1 = Analog Comparator result enabled for fault detection
Bit 3: PWMA_ACOMP_D_EN – Enables Analog Comparator D result for
DPWM 3 PWM-A Fault detection
0 = Analog Comparator result disabled for fault detection (Default)
1 = Analog Comparator result enabled for fault detection
Bit 2: PWMA_ACOMP_C_EN – Enables Analog Comparator C result for
DPWM 3 PWM-A Fault detection
0 = Analog Comparator result disabled for fault detection (Default)
1 = Analog Comparator result enabled for fault detection
Bit 1: PWMA_ACOMP_B_EN – Enables Analog Comparator B result for
DPWM 3 PWM-A Fault detection
0 = Analog Comparator result disabled for fault detection (Default)
1 = Analog Comparator result enabled for fault detection
Bit 0: PWMA_ACOMP_A_EN – Enables Analog Comparator A result for
DPWM 3 PWM-A Fault detection
0 = Analog Comparator result disabled for fault detection (Default)
1 = Analog Comparator result enabled for fault detection
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4.2.29 DPWM 3 IDE Detection Register (DPWM3IDEDET)
Address 0x00130070
Bit Number
Bit Name
Access
Default
6
ACOMP_G_EN
R/W
0
Bit Number
Bit Name
Access
Default
2
ACOMP_C_EN
R/W
0
5
ACOMP_F_EN
R/W
0
4
ACOMP_E_EN
R/W
0
1
ACOMP_B_EN
R/W
0
3
ACOMP_D_EN
R/W
0
0
ACOMP_A_EN
R/W
0
Bit 6: ACOMP_6_EN – Enables Analog Comparator G result for DPWM 3 IDE
detection
0 = Analog Comparator result disabled for IDE detection (Default)
1 = Analog Comparator result enabled for IDE detection
Bit 5: ACOMP_5_EN – Enables Analog Comparator F result for DPWM 3 IDE
detection
0 = Analog Comparator result disabled for IDE detection (Default)
1 = Analog Comparator result enabled for IDE detection
Bit 4: ACOMP_4_EN – Enables Analog Comparator E result for DPWM 3 IDE
detection
0 = Analog Comparator result disabled for IDE detection (Default)
1 = Analog Comparator result enabled for IDE detection
Bit 3: ACOMP_3_EN – Enables Analog Comparator D result for DPWM 3 IDE
detection
0 = Analog Comparator result disabled for IDE detection (Default)
1 = Analog Comparator result enabled for IDE detection
Bit 2: ACOMP_2_EN – Enables Analog Comparator C result for DPWM 3 IDE
detection
0 = Analog Comparator result disabled for IDE detection (Default)
1 = Analog Comparator result enabled for IDE detection
Bit 1: ACOMP_1_EN – Enables Analog Comparator B result for DPWM 3 IDE
detection
0 = Analog Comparator result disabled for IDE detection (Default)
1 = Analog Comparator result enabled for IDE detection
Bit 0: ACOMP_0_EN – Enables Analog Comparator A result for DPWM 3 IDE
detection
0 = Analog Comparator result disabled for IDE detection (Default)
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1 = Analog Comparator result enabled for IDE detection
4.2.30 HFO Fail Detect Register (HFOFAILDET)
Address 0x00130074
Bit Number
Bit Name
Access
Default
17:1
HFO_FAIL_THRESH
R/W
0_0000_0000_1111_1111
0
HFO_DETECT_EN
R/W
0
Bits 17-1: HFO_FAIL_THRESH – Configures threshold where a clear flag is
used to clear a counter in the Low Frequency Oscillator domain (if LFO counter
overflows, a reset will be generated), resolution of threshold equals High
Frequency Oscillator period
Bit 0: HFO_DETECT_EN – Enables High Frequency Oscillator Failure
Detection logic, device will be reset upon detection of an oscillator failure
0 = Disables High Frequency Oscillator Failure Detection (Default)
1 = Enables High Frequency Oscillator Failure Detection
4.2.31 LFO Fail Detect Register (LFOFAILDET)
Address 0x00130078
Bit Number
Bit Name
Access
Default
6:2
LFO_FAIL_THRESH
R/W
0_0011
1
LFO_FAIL_INT_EN
R/W
0
0
LFO_DETECT_EN
R/W
0
Bits 6-2: LFO_FAIL_THRESH – Configures threshold where a clear flag is
used to clear a counter in the High Frequency Oscillator domain (if HFO counter
overflows, a reset will be generated), resolution of threshold equals Low
Frequency Oscillator period
Bit 1: LFO_FAIL_INT_EN – Low Frequency Oscillator Fail Interrupt Enable
0 = Disables Interrupt Generation upon LFO Failure Detection (Default)
1 = Enables Interrupt Generation upon LFO Failure Detection
Bit 0: LFO_DETECT_EN – Enables Low Frequency Oscillator Failure
Detection logic, interrupt will be generated upon detection of an oscillator failure
0 = Disables Low Frequency Oscillator Failure Detection (Default)
1 = Enables Low Frequency Oscillator Failure Detection
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4.2.32 IDE Control Register (IDECTRL)
Address 0013007C
Bit Number
Bit Name
Access
Default
Bit Number
Bit Name
Access
Default
31:24
DCM_LIMIT_H
R/W
0000_0000
15:14
RESERVED
00
23:16
DCM_LIMIT_L
R/W
0000_0000
13
DCM_INT_EN
R/W
0
12:0
IDE_KD
R/W
0_0000_0000_0000
Bits 31-24: DCM_LIMIT_H – Value added to 1-Da value to provide hysteresis
for exiting DCM mode
Bits 23-16: DCM_LIMIT_L – Value subtracted from 1-Da value to provide
hysteresis for entering DCM mode
Bit 15-14: RESERVED – Unused Bits
Bit 13: DCM_INT_EN – Enables Discontinuous Conduction Mode (DCM)
interrupt generation based on selected Filter outputs
0 = Disables DCM Detection Interrupt (Default)
1 = Enables DCM Detection Interrupt
Bits 12-0: IDE_KD – 13-bit unsigned value used to calculate the DPWM B Pulse
width when configured in IDE Mode. IDE_KD is configured in 4.9 format, with
the integer portion of the KD value ranging from 0 to 15 and 9 fractional bits
available for the pulse width calculation.
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4.3
I2C – Serial Bus Interface
4.3.1 I2C Control Register 1 (I2CCTRL1)
Address FFF7E400
Bit Number
Bit Name
Access
Default
20
PRC_CALL
R/W
0
19
GRP_CMD
R/W
0
18
PEC_ENA
R/W
0
17
EXT_CMD
R/W
0
Bit Number
Bit Name
Access
Default
16
CMD_ENA
R/W
0
15:8
BYTE_COUNT
R/W
0000_0000
7:1
SLAVE_ADDR
R/W
000_0000
0
RW
R/W
0
Bit 20: PRC_CALL – Master Process Call Message Enable
0 = Default state for all messages besides Process Call message (Default)
1 = Enables transmission of Process Call message
Bit 19: GRP_CMD – Master Group Command Message Enable
0 = Default state for all messages besides Group Command message
(Default)
1 = Enables transmission of Group Command message
Bit 18: PEC_ENA – Master PEC Processing Enable
0 = Disables PEC processing (Default)
1 = Enables PEC byte transmission/reception
Bit 17: EXT_CMD – Master Extended Command Code Enable
0 = Use 1 byte for Command Code (Default)
1 = Use 2 bytes for Command Code
Bit 16: CMD_ENA – Master Command Code Enable
0 = Disables use of command code on Master initiated messages (Default)
1 = Enables use of command code on Master initiated messages
Bits 15-8: BYTE_COUNT – Indicates number of data bytes transmitted in
current message. Byte count does not include any device addresses, command
words or block lengths in block messages. In block messages, the I2C Interface
automatically inserts the block length into the message based on the byte count
setting. The firmware only needs to load the address, command words and data to
be transmitted. I2C Interface supports byte writes up to 255 bytes.
Bits 7-1: SLAVE_ADDR – Specifies the address of the slave to which the
current message is directed towards.
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Bit 0: RW – Indicates if current Master initiated message is read operation or
write operation.
0 = Message is a write transaction (data from Master to Slave) (Default)
1 = Message is a read transaction (data from Slave to Master)
4.3.2 I2C Transmit Data Buffer (I2CTXBUF)
Address FFF7E404
Bit Number
Bit Name
Access
Default
31:24
BYTE3
R/W
0000_0000
23:16
BYTE2
R/W
0000_0000
15:8
BYTE1
R/W
0000_0000
7:0
BYTE0
R/W
0000_0000
Bits 31-24: BYTE3 – Last data byte transmitted from Transmit Data Buffer
Bits 23-16: BYTE2 – Third data byte transmitted from Transmit Data Buffer
Bits 15-8: BYTE1 – Second data byte transmitted from Transmit Data Buffer
Bits 7-0: BYTE0 – First data byte transmitted from Transmit Data Buffer
4.3.3 I2C Receive Data Register (I2CRXBUF)
Address FFF7E408
Bit Number
Bit Name
Access
Default
31:24
BYTE3
R
-
23:16
BYTE2
R
-
15:8
BYTE1
R
-
7:0
BYTE0
R
-
Bits 31-24: BYTE3 – Last data byte received in Receive Data Buffer
Bits 23-16: BYTE2 – Third data byte received in Receive Data Buffer
Bits 15-8: BYTE1 – Second data byte received in Receive Data Buffer
Bits 7-0: BYTE0 – First data byte received in Receive Data Buffer
4.3.4 I2C Acknowledge Register (I2CACK)
Address FFF7E40C
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Bit Number
Bit Name
Access
Default
0
ACK
R/W
0
Bit 0: ACK – Allows firmware to acknowledge or not acknowledge received data
0 = NACK received data (Default)
1 = Acknowledge received data, bit clears upon issue of ACK on I2C
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4.3.5 I2C Status Register (I2CST)
Address FFF7E410
Bit Number
Bit Name
Access
Default
Bit Number
Bit Name
Access
Default
Bit Number
Bit Name
Access
Default
Bit Number
Bit Name
Access
Default
21
SCL_RAW
R
14
LOST_ARB
R
-
20
SDA_RAW
R
-
13
BUS_FREE
R
-
9
CLK_HIGH_DETECTED
R
5
EOM
R
-
12
UNIT_BUSY
R
-
19:16
RESERVED
R
11
RESERVED
R
-
8
CLK_LOW_TIMEOUT
R
-
4
DATA_REQUEST
R
-
15
MASTER
R
10
SLAVE_ADDR_READY
R
-
7
PEC_VALID
R
-
3
DATA_READY
R
-
6
NACK
R
2:0
RD_BYTE_COUNT
R
-
Bit 21: SCL_RAW – I2C Clock Pin Real Time Status
0 = I2C clock pin observed at logic level low
1 = I2C clock pin observed at logic level high
Bit 20: SDA_RAW – I2C Data Pin Real Time Status
0 = I2C data pin observed at logic level low
1 = I2C data pin observed at logic level high
Bit 19:16 Reserved – Reserved Bits
Bit 15: MASTER – Master Indicator
0 = I2C Interface in Slave Mode or Idle Mode
1 = I2C Interface in Master Mode
Bit 14: LOST_ARB – Lost Arbitration Flag
0 = Master has attained control of I2C
1 = Master has lost arbitration and control of I2C
Bit 13: BUS_FREE – I2C Free Indicator
0 = I2C processing current message
1 = I2C available for new message
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Bit 12: UNIT_BUSY – I2C Busy Indicator
0 = I2C Interface is idle, ready to transmit/receive message
1 = I2C Interface is busy, processing current message
Bit 11: RESERVED – Reserved Bit
Bit 10: SLAVE_ADDR_READY – Slave Address Ready
0 = Indicates no slave address is available for reading
1 = Slave address ready to be read from Receive Data Register (Bits 6:0)
Bit 9: CLK_HIGH_DETECTED – Clock High Detection Status
0 = No Clock High condition detected
1 = Clock High exceeded 50us during message
Bit 8: CLK_LOW_TIMEOUT – Clock Low Timeout Status
0 = No clock low timeout detected
1 = Clock low timeout detected, clock held low for greater than 35ms
Bit 7: PEC_VALID – PEC Valid Indicator
0 = Received PEC not valid (if EOM is asserted)
1 = Received PEC is valid
Bit 6: NACK – Not Acknowledge Flag Status
0 = Data transmitted has been accepted by receiver
1 = Receiver has not accepted transmitted data
Bit 5: EOM – End of Message Indicator
0 = Message still in progress or I2C in idle state.
1 = End of current message detected
Bit 4: DATA_REQUEST – Data Request Flag
0 = No data needed by I2C Interface
1 = I2C Interface request additional data. I2C clock stretching enabled to
stall bus until firmware provides transmit data.
Bit 3: DATA_READY – Data Ready Flag
0 = No data available for reading by processor
1 = I2C Interface read buffer full, firmware required to read data prior to
further bus activity. I2C clock stretching enabled to stall bus until data is
read by firmware.
Bits 2-0: RD_BYTE_COUNT – Number of Data Bytes available in Receive
Data Register
0 = No received data
1 = 1 byte received. Data located in Receive Data Register, Bits 7-0
2 = 2 bytes received. Data located in Receive Data Register, Bits 15-0
3 = 3 bytes received. Data located in Receive Data Register, Bits 23-0
4 = 4 bytes received. Data located in Receive Data Register, Bits 31-0
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4.3.6 I2C Interrupt Mask Register (I2CINTM)
Address FFF7E414
Bit Number
Bit Name
Access
Default
9
CLK_HIGH_DETECT
R/W
1
8
LOST_ARB
R/W
1
7:6
RESERVED
R
-
Bit Number
Bit Name
Access
Default
5
EOM
R/W
1
4
SLAVE_ADDR_READY
R/W
1
3
DATA_REQUEST
R/W
1
Bit Number
Bit Name
Access
Default
2
DATA_READY
R/W
1
1
BUS_LOW_TIMEOUT
R/W
1
0
BUS_FREE
R/W
1
Bit 9: CLK_HIGH_DETECT – Clock High Detection Interrupt Mask
0 = Generates interrupt if clock high exceeds 50us during message
1 = Disables interrupt generation for Clock High detection (Default)
Bit 8: LOST_ARB – Lost Arbitration Interrupt Mask
0 = Generates interrupt upon assertion of Lost Arbitration flag
1 = Disables interrupt generation upon assertion of Lost Arbitration flag
(Default)
Bit 7:6 Reserved – Reserved Bits
Bit 5: EOM – End of Message Interrupt Mask
0 = Generates interrupt upon assertion of End of Message flag
1 = Disables interrupt generation upon assertion of End of Message flag
(Default)
Bit 4: SLAVE_ADDR_READY – Slave Address Ready Interrupt Mask
0 = Generates interrupt upon assertion of Slave Address Ready flag
1 = Disables interrupt generation upon assertion of Slave Address Ready
flag (Default)
Bit 3: DATA_REQUEST – Data Request Interrupt Mask
0 = Generates interrupt upon assertion of Data Request flag
1 = Disables interrupt generation upon assertion of Data Request flag
(Default)
Bit 2: DATA_READY – Data Ready Interrupt Mask
0 = Generates interrupt upon assertion of Data Ready flag
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1 = Disables interrupt generation upon assertion of Data Ready flag
(Default)
Bit 1: BUS_LOW_TIMEOUT – Clock Low Timeout Interrupt Mask
0 = Generates interrupt upon assertion of Clock Low Timeout flag
1 = Disables interrupt generation upon assertion of Clock Low Timeout
flag (Default)
Bit 0: BUS_FREE – Bus Free Interrupt Mask
0 = Generates interrupt upon assertion of Bus Free flag
1 = Disables interrupt generation upon assertion of Bus Free flag (Default)
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4.3.7 I2C Control Register 3 (I2CCTRL3)
Address FFF7E420
Bit Number
Bit Name
Access
Default
23
I2C_MODE_EN
R/W
0
22
MASTER_EN
R/W
0
21
RESERVED
R
-
Bit Number
Bit Name
Access
Default
20
CLK_LO_DIS
R/W
0
19
IBIAS_B_EN
R/W
0
18
IBIAS_A_EN
R/W
0
17
SCL_DIR
R/W
0
16
SCL_VALUE
R/W
0
Bit Number
Bit Name
Access
Default
15
SCL_MODE
R/W
0
14
SDA_DIR
R/W
0
13
SDA_VALUE
R/W
0
12
SDA_MODE
R/W
0
11:5
Reserved
R
-
Bit Number
Bit Name
Access
Default
4
FAST_MODE_PLUS
R/W
0
3
FAST_MODE
R/W
0
2
BUS_LO_INT_EDGE
R/W
0
1
RESERVED
R
-
Bit 23: I2C_MODE_EN – I2C Mode Enable
0 = Enables I2C interface capability (Default)
1 = Enables I2C interface capability
Bit 22: MASTER_EN – I2C Master Enable
0 = Disables I2C Master capability (Default)
1 = Enables I2C Master capability
Bit 21: Reserved – Reserved Bit
Bit 20: CLK_LO_DIS – Clock Low Timeout Disable
0 = Clock Low Timeout Enabled (Default)
1 = Clock Low Timeout Disabled
Bit 19: IBIAS_B_EN – I2C Current Source B Control
0 = Disables Current Source for I2C address detection thru ADC (Default)
1 = Enables Current Source for I2C address detection thru ADC
Bit 18: IBIAS_A_EN – I2C Current Source A Control
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RESET
R/W
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0 = Disables Current Source for I2C address detection thru ADC (Default)
1 = Enables Current Source for I2C address detection thru ADC
Bit 17: SCL_DIR – Configures direction of I2C clock pin in GPIO mode
0 = I2C clock pin configured as output (Default)
1 = I2C clock pin configured as input
Bit 16: SCL_VALUE – Configures output value of I2C clock pin in GPIO Mode
0 = I2C clock pin driven low in GPIO Mode (Default)
1 = I2C clock pin driven high in GPIO Mode
Bit 15: SCL_MODE – Configures mode of I2C Clock pin
0 = I2C clock pin configured in functional mode (Default)
1 = I2C clock pin configured as GPIO
Bit 14: SDA_DIR – Configures direction of I2C data pin in GPIO mode
0 = I2C data pin configured as output (Default)
1 = I2C data pin configured as input
Bit 13: SDA_VALUE – Configures output value of I2C data pin in GPIO Mode
0 = I2C data pin driven low in GPIO Mode (Default)
1 = I2C data pin driven high in GPIO Mode
Bit 12: SDA_MODE – Configures mode of I2C Data pin
0 = I2C data pin configured in functional mode (Default)
1 = I2C data pin configured as GPIO
Bit 11:5: Reserved – Reserved Bits
Bit 4: FAST_MODE_PLUS – Fast Mode Plus Enable
0 = Standard 100 KHz mode enabled (Default)
1 = Fast Mode Plus enabled (1MHz operation on I2C)
Bit 3: FAST_MODE – Fast Mode Enable
0 = Standard 100 KHz mode enabled (Default)
1 = Fast Mode enabled (400KHz operation on I2C)
Bit 2: BUS_LO_INT_EDGE – Clock Low Timeout Interrupt Edge Select
0 = Interrupt generated on rising edge of clock low timeout (Default)
1 = Interrupt generated on falling edge of clock low timeout
Bit 1: Reserved – Reserved Bit
Bit 0: RESET – I2C Interface Synchronous Reset
0 = No reset of internal state machines (Default)
1 = Control state machines are reset to initial states
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4.4
SPI – Serial Peripheral Interface
4.4.1 SPI Control Register (SPICTRL)
Address FFF7E800
Bit Number
Bit Name
Access
Default
23:21
CLKRATE
R/W
000
Bit Number
Bit Name
Access
Default
20:16
FRMLEN
R/W
00000
15:11
RXCNT
R/W
00000
10:7
TXCNT
R/W
0000
6
WRSTORE
R/W
0
5
WRSTART
R/W
0
Bit Number
Bit Name
Access
Default
4
POL
R/W
0
3
PHA
R/W
0
2
INTEN
R/W
0
1
MODE
R/W
0
0
SPIEN
R/W
0
Bit 23:21: CLKRATE – Master clock rate relative to ICLK
0 = SCK is ICLK/2 (Default)
1 = SCK is ICLK/4
2 = SCK is ICLK/8
3 = SCK is ICLK/16
Bit 20:16: FRMLEN – Sets the number of messages (TXCNT + RXCNT) to
hold CS low.
Bit 15:11: RXCNT – Sets the number bytes to receive after TXCNT bytes have
been transmitted
Bit 10:7: TXCNT – Sets the bytes to transmit from the SPITX registers
Bit 6: WRSTORE – Places or discards data received during TXCNT
0 = Data received during TXCNT discarded (Default)
1 = Data received during TXCNT placed in RXBUF
Bit 5: WRSTART- Sets which WRREG initiates transfer
0 = Write to SPITX-0 starts message transfer (Default)
1 = Write to SPITX-1 starts message transfer
Bit 4: POL – The polarity bit, together with the phase bit, determines the transfermode.
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Bit 3: PHA – The phase bit, together with the polarity bit, determines the
transfer-mode.
Bit 2: INTEN – Enable interrupt generation to the CPU
0 = Disabled (Default)
1 = Enabled
Bit 1: MODE – Configures SPI mode
0 = Master Mode (Default)
1 = Slave mode
Bit 0: SPIEN – Enable for SPI Module
0 = Disabled (Default)
1 = Enabled
4.4.2 SPI Status Register (SPISTAT)
Address FFF7E804
Bit Number
Bit Name
Access
Default
7:3
FRMCNT
R
-
2
WRCOL
R
-
1
BUSY
R
-
0
SPIF
R
-
Bit 12:4: FRMCNT – Indicates the number of messages remaining in the
FRMLEN before SCS will go inactive.
Bit 2: WCOL – SPI interface is busy
Bit 1: BUSY – SPI interface is busy
Bit 0: SPIF – SPI Flag, set when current message is complete. Write a ‘1’ to clear
4.4.3 SPI Pin Function Register (SPIFUNC)
Address FFF7E808
Bit Number
Bit Name
Access
Default
3
MISO
R/W
0
2
MOSI
R/W
0
Bit 3: MISO
0=Functional Mode (default)
1=GPIO Mode
Bit 2: MOSI
0=Functional Mode (default)
1=GPIO Mode
Bit 1: SCS
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SCS
R/W
0
0
SCK
R/W
0
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0=Functional Mode (default)
1=GPIO Mode
Bit 0: SCK
0=Functional Mode (default)
1=GPIO Mode
4.4.4 SPI Pin Direction Register (SPIDIR)
Address FFF7E80C
Bit Number
Bit Name
Access
Default
3
MISO
R/W
0
2
MOSI
R/W
0
1
SCS
R/W
0
0
SCK
R/W
0
Bit 3: MISO
0=Output in GPIO Mode (default)
1=Input in GPIO Mode
Bit 2: MOSI
0=Output in GPIO Mode (default)
1=Input in GPIO Mode
Bit 1: SCS
0=Output in GPIO Mode (default)
1=Input in GPIO Mode
Bit 0: SCK
0=Output in GPIO Mode (default)
1=Input in GPIO Mode
4.4.5 SPI Pin GP Out Register (SPIGPOUT)
Address FFF7E810
Bit Number
Bit Name
Access
Default
3
MISO
R/W
0
2
MOSI
R/W
0
1
SCS
R/W
0
0
SCK
R/W
0
Bit 3: MISO
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0= Pin driven to 0 when configured as an output in GPIO Mode (default)
1= Pin driven to 1 when configured as an output in GPIO Mode
Bit 2: MOSI
0= Pin driven to 0 when configured as an output in GPIO Mode (default)
1= Pin driven to 1 when configured as an output in GPIO Mode
Bit 1: SCS
0= Pin driven to 0 when configured as an output in GPIO Mode (default)
1= Pin driven to 1 when configured as an output in GPIO Mode
Bit 0: SCK
0= Pin driven to 0 when configured as an output in GPIO Mode (default)
1= Pin driven to 1 when configured as an output in GPIO Mode
4.4.6 SPI Pin GP In Register (SPIGPIN)
Address FFF7E814
Bit Number
Bit Name
Access
Default
3
MISO
R
-
2
MOSI
R
-
1
SCS
R
-
Bit 3: MISO
0= Pin Value is 0
1= Pin Value is 1
Bit 2: MOSI
0= Pin Value is 0
1= Pin Value is 1
Bit 1: SCS
0= Pin Value is 0
1= Pin Value is 1
Bit 0: SCK
0= Pin Value is 0
1= Pin Value is 1
4.4.7 SPI TX Buffer Register 0 (SPITX0)
Address FFF7E818
Bit Number
Bit Name
Access
128
31:0
DATA
R/W
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SCK
R
-
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Default
0
Bit 31-0: DATA – First 32-bit word to be transmitted in SPI-Master mode. Only
32-bit word to be transmitted in SPI-Slave mode.
4.4.8 SPI TX Buffer Register 1 (SPITX1)
Address FFF7E81C
Bit Number
Bit Name
Access
Default
31:0
DATA
R/W
0
Bits 31-0: DATA – Second 32-bit word to be transmitted in SPI-Master mode.
Not used in SPI-Slave Mode.
4.4.9 SPI Read Buffer Register 0 (SPIRX0)
Address FFF7E820
Bit Number
Bit Name
Access
Default
31:0
DATA
R
-
Bits 31-0: DATA – First 32-bit word received in SPI-Master/Slave mode.
4.4.10 SPI Read Buffer Register 1 (SPIRX1)
Address FFF7E824
Bit Number
Bit Name
Access
Default
31:0
DATA
R
-
Bits 31-0: DATA – Second 32-bit word received in SPI-Master mode. Not used
in SPI-Slave Mode.
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4.4.11 SPI Read Buffer Register 2 (SPIRX2)
Address FFF7E828
Bit Number
Bit Name
Access
Default
31:0
DATA
R
-
Bits 31-0: DATA – Third 32-bit word received in SPI-Master mode. Not used in
SPI-Slave Mode.
4.4.12 SPI Read Buffer Register 3 (SPIRX3)
Address FFF7E82C
Bit Number
Bit Name
Access
Default
31:0
DATA
R
-
Bits 31-0: DATA – Fourth 32-bit word received in SPI-Master mode. Not used in
SPI-Slave Mode.
4.5
UART Registers
4.5.1 UART Control Register 0 (UARTCTRL0)
Address FFF7EC00 – UART 0 Control Register 0
Address FFF7ED00 – UART 1 Control Register 0
Bit Number
Bit Name
Access
Default
7
STOP
R/W
0
6
PARITY
R/W
0
5
PARITY_ENA
R/W
0
Bit Number
Bit Name
Access
Default
4
SYNC_MODE
R/W
0
3
ADDR_MODE
R/W
0
2:0
DATA_SIZE
R/W
000
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Bit 7: STOP – Configures stop bits for each frame
0 = One STOP bit included in each frame (Default)
1 = Two STOP bits included in each frame
Bit 6: PARITY – Sets odd or even parity
0 = Odd parity (Default)
1 = Even parity
Bit 5: PARITY_ENA - Enables parity transmission
0 = No parity bit included in each frame (Default)
1 = One parity bit included in each frame
Bit 4: SYNC_MODE – Selects between Synchronous mode and Asynchronous
mode
0 = Synchronous (Default)
1 = Asynchronous
Bit 3: ADDR_MODE – Selects between Idle and Address Bit Mode
0 = IDLE Line mode with no Address bit (Default)
1 = Address Bit mode with one Address bit
Bits 2-0: DATA_SIZE – Determines the TX and RX byte size
000 = 1 bit of data (Default)
001 = 2 bit of data
010 = 3 bits of data
011 = 4 bits of data
100 = 5 bits of data
101 = 6 bits of data
110 = 7 bits of data
111 = 8 bits of data
4.5.2 UART Receive Status Register (UARTRXST)
Address FFF7EC04 – UART 0 Receive Status Register
Address FFF7ED04 – UART 1 Receive Status Register
Bit Number
Bit Name
Access
Default
4
RX_IDLE
R
-
3
SLEEP
R/W
0
2
RX_RDY
R
-
1
RX_WAKE
R
-
0
RX_ENA
R/W
0
Bit 4: RX_IDLE –RX Idle status bit
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0 = Not in Rx Idle State
1 = Rx Idle detected
Bit 3: SLEEP – Sleep Mode Configuration
0 = Sleep Mode disabled (Default)
1 = Sleep Mode enabled
Bit 2: RX_RDY – UART Receiver ready status bit
0 = UART Receiver not ready
1 = UART Receiver ready
Bit 1: RX_WAKE – UART Receiver wake status bit
0 = UART Receiver has not entered wakeup state
1 = UART Receiver has entered wakeup state
Bit 0: RX_ENA – Turns on UART Receiver
0 = UART Receiver disabled (Default)
1 = UART Receiver enabled
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4.5.3 UART Transmit Status Register (UARTTXST)
Address FFF7EC08 – UART 0 Transmit Status Register
Address FFF7ED08 – UART 1 Transmit Status Register
Bit Number
Bit Name
Access
Default
7
CONTINUE
R/W
0
6
LOOPBACK
R/W
0
Bit Number
Bit Name
Access
Default
3
TX_EMPTY
R
-
2
TX_RDY
R
-
5:4
RESERVED
00
1
TX_WAKE
R/W
0
0
TX_ENA
R/W
0
Bit 7: CONTINUE – Configure operation in suspend mode
0 = Stop transmitting on suspend (Default)
1 = Continue transmitting after initiation of suspend
Bit 6: LOOPBACK – Loopback Mode Configuration
0 = Normal mode (Default)
1 = Loopback Mode
Bit 5-4: RESERVED – Unused bits – Default to 00
Bit 3: TX_EMPTY – Transmit buffer status
0 = Transmit buffer is not empty
1 = Transmit buffer is empty
Bit 2: TX_RDY – Transmitter Ready
0 = UART Transmitter is not ready
1 = UART Transmitter is ready to transmit data
Bit 1: TX_WAKE – TX wake control bit
0 = UART Transmitter Wakeup disabled (Default)
1 = UART Transmitter Wakeup enabled
Bit 0: TX_ENA – Turns on TX module
0 = UART Transmitter Disabled (Default)
1 = UART Transmitter Enabled
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4.5.4 UART Control Register 3 (UARTCTRL3)
Address FFF7EC0C – UART 0 Control Register 3
Address FFF7ED0C – UART 1 Control Register 3
Bit Number
Bit Name
Access
Default
7
SW_RESET
R/W
0
6
POWERDOWN
R/W
0
5
CLOCK
R/W
0
4
RX_INT_ENA
R/W
0
Bit Number
Bit Name
Access
Default
3
TX_INT_ENA
R/W
0
2
WAKEUP_INT_ENA
R/W
0
1
BRKDT_INT_ENA
R/W
0
0
ERR_INT_ENA
R/W
0
Bit 7: SW_RESET – Software reset for UART Transmitter/Receiver
0 = Enables Software Reset (Default)
1 = Disables Software Reset
Bit 6: POWERDOWN – Power-down Transmitter/Receiver Control
0 = Disables Power-down mode (Default)
1 = Enables Power-down mode
Bit 5: CLOCK_ENA – UART Clock Select
0 = Selects external clock (Default)
1 = Selects internal clock
Bit 4: RX_INT_ENA – Enables the interrupts from UART Receiver
0 = Disables interrupts from UART Receiver (Default)
1 = Enables interrupts from UART Receiver
Bit 3: TX_INT_ENA – Enables the interrupts from UART Transmitter
0 = Disables interrupts from UART Transmitter (Default)
1 = Enables interrupts from UART Transmitter
Bit 2: WAKEUP_INT_ENA – Enables the wakeup interrupt from UART
0 = Disables Wakeup Interrupt (Default)
1 = Enables Wakeup Interrupt
Bit 1: BRKDT_INT_ENA – Enables the Broken Circuit interrupt from UART
Receiver
0 = Disables Broken Circuit Interrupt (Default)
1 = Enables Broken Circuit Interrupt
Bit 0: ERR_INT_ENA – Enables UART Receiver Error Interrupt
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0 = Disables UART Receiver Error Interrupt (Default)
1 = Enables UART Receiver Error Interrupt
Bit Number
Bit Name
Access
Default
3
PARITY_ERR
R
-
2
WAKEUP_INT
R
-
1
BRKDT_INT
R
-
0
RX_ERR
R
-
Bit Number
Bit Name
Access
Default
7
BUS_BUSY
R
-
6
RESERVED
0
5
FRAME_ERR
R
-
4
OVERRUN_ERR
R
-
4.5.5 UART Interrupt Status Register (UARTINTST)
Address FFF7EC10 – UART 0 Interrupt Status Register
Address FFF7ED10 – UART 1 Interrupt Status Register
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Bit 7: BUS_BUSY – UART Receiver Busy Indicator
0 = UART Receiver ready to accept new frame
1 = UART Receiver currently processing message
Bit 6: RESERVED – Unused bit – Default to 0
Bit 5: FRAME_ERR – UART Receiver Framing Error
0 = No framing error found within incoming data message
1 = Indicates the incoming data message had a framing error
Bit 4: OVERRUN_ERR – UART Receiver Buffer Overflow
0 = No overflow condition found in receive buffer
1 = Indicates the receive buffer has overflowed
Bit 3: PARITY_ERR – UART Receiver Parity Error
0 = No parity error found on the incoming data message
1 = Indicates a parity error found on the incoming data message
Bit 2: WAKEUP_INT – UART Receiver Wakeup Interrupt
0 = No Wakeup Interrupt received from UART Receiver
1 = Wakeup Interrupt received from UART Receiver
Bit 1: BRKDT_INT – UART Receiver Broken Circuit Interrupt
0 = No Broken Circuit interrupt received from UART Receiver
1 = Indicates a Broken Circuit interrupt received from UART Receiver
Bit 0: RX_ERR – UART Receiver Error
0 = No UART Receiver Errors detected
1 = Frame Error or Overrun error or Parity Error or Broken Circuit error
received from UART Receiver
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4.5.6 UART Baud Divisor High Byte Register (UARTHBAUD)
Address FFF7EC14 – UART 0 Baud Divisor High Byte Register
Address FFF7ED14 – UART 1 Baud Divisor High Byte Register
Bit Number
Bit Name
Access
Default
7:0
BAUD_DIV_H
R/W
0000_0000
Bits 7-0: BAUD_DIV_H - Sets the high byte of the 24 bit baud rate selector
4.5.7 UART Baud Divisor Middle Byte Register (UARTMBAUD)
Address FFF7EC18 – UART 0 Baud Divisor Middle Byte Register
Address FFF7ED18 – UART 1 Baud Divisor Middle Byte Register
Bit Number
Bit Name
Access
Default
7:0
BAUD_DIV_M
R/W
0000_0000
Bits 7-0: BAUD_DIV_M - Sets the middle byte of the 24 bit baud rate selector
4.5.8 UART Baud Divisor Low Byte Register (UARTLBAUD)
Address FFF7EC1C – UART 0 Baud Divisor Low Byte Register
Address FFF7ED1C – UART 1 Baud Divisor Low Byte Register
Bit Number
Bit Name
Access
Default
7:0
BAUD_DIV_L
R/W
0000_0000
Bits 7-0: BAUD_DIV_L - Sets the low byte of the 24 bit baud rate selector
4.5.9 UART Receive Buffer (UARTRXBUF)
Address FFF7EC24 – UART 0 Receive Buffer
Address FFF7ED24 – UART 1 Receive Buffer
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Bit Number
Bit Name
Access
Default
7:0
RXDAT
R
-
Bits 7-0: RXDAT – Contains the last data byte received from the UART
Receiver
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4.5.10 UART Transmit Buffer (UARTTXBUF)
Address FFF7EC28 – UART 0 Transmit Buffer
Address FFF7ED28 – UART 1 Transmit Buffer
Bit Number
Bit Name
Access
Default
7:0
TXDAT
R/W
0000_0000
Bits 7-0: TXDAT – Contains the data byte to be transmitted by the UART
Transmitter
4.5.11 UART I/O Control Register (UARTIOCTRLSCLK, UARTIOCTRLRX,
UARTIOCTRLTX)
Address FFF7EC2C – UART 0 I/O (SCLK) Control Register
Address FFF7ED2C – UART 1 I/O (SCLK) Control Register
Address FFF7EC30 – UART 0 I/O (RX) Control Register
Address FFF7ED30 – UART 1 I/O (RX) Control Register
Address FFF7EC34 – UART 0 I/O (TX) Control Register
Address FFF7ED34 – UART 1 I/O (TX) Control Register
Bit Number
Bit Name
Access
Default
3
DATA_IN
R
-
2
DATA_OUT
R/W
0
1
IO_FUNC
R/W
0
0
IO_DIR
R/W
0
Bit 3: DATA_IN – Data received from pin when configured as GPIO
Bit 2: DATA_OUT – Data transmitted to pin when configured as GPIO
Bit 1: IO_FUNC – Selects the function for UART pins
0 = GPIO mode (Default)
1 = Baud Clock for SCLK, Normal operation for SCI_RX/SCI_TX
Bit 0: IO_DIR – Pin direction when configured as GPIO
0 = Input (Default)
1 = Output
4.5.12 UART Baud Divisor Sub Bits Register (UARTSBAUD)
Address FFF7EC38 – UART 0 Baud Divisor Sub Bits Register
Address FFF7ED38 – UART 1 Baud Divisor Sub Bits Register
Bit Number
Bit Name
2:0
BAUD_SUB
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Access
Default
R/W
000
Bit 2-0: BAUD_SUB – Each LSB adds one ICLK period to the baud period
calculated via the values programed in the UARTHBAUD, UARTMBAUD, and
UARTLBAUD registers.
4.5.13 UART RX Control Register 4 (UARTRXCTRL4)
Address FFF7EC3C – UART 0 RX Control Register 4
Address FFF7ED3C – UART 1 RX Control Register 4
Bit Number
7:6
5
4:3
RX_CENTER_SAMPLE_EN
RX_CAL_CONTINUOUS_EN
RX_CAL_MODE_BIT_WIDTH
Access
R/W
R/W
R/W
Default
00
0
00
Bit Name
Bit Number
Bit Name
Access
Default
2
RX_CAL_MODE_EN
R/W
0
1
RESERVED
R
-
0
RX_SYNC_ON_START_EN
R/W
0
Bit 7-6: RX_CENTER_SAMPLE_EN – Sample position for the UART RX
00 = Takes 3 samples to the right of the data eye (Default)
01 = Takes 3 samples in the center of the data eye
10 = Takes 3 samples to the left of the data eye
11 = Reserved
Bit 5: RX_CAL_CONTINUOUS_EN – Continuously captures baud pulses
0 = Baud pulses will not be captured without a low to high toggle of the
RX_CAL_MODE_EN bit. (Default)
1 = Baud pulses will continue to be captured and the updated values will
be written to the UARTRXMBAUD, UARTRXLBAUD, and
UARTRXSBAUD registers.
Bit 4-3: RX_CAL_MODE_BIT_WIDTH – Sets the maximum number of baud
periods a pulse (transition on the RX line of 1->0->1 or 0->1->0) can span and
still be recorded in the UARTRXMBAUD, UARTRXLBAUD, and
UARTRXSBAUD registers. The CAL mode feature helps refine the baud period
programmed in the UARTHBAUD, UARTMBAUD, UARTLBAUD, and
UARTSBAUD registers.
00 = Captures a low pulse (1->0->1) that spans 1 baud period (Default)
01 = Captures a low pulse (1->0->1) that spans 1-4 baud periods
10 = Captures a low pulse (1->0->1) that spans 1-12 baud periods
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11 = Captures a low/high pulse that spans 1 baud period
Bit 2: RX_CAL_MODE_EN – Enables the capture feature of the UART.
Recorded pulses are stored in the UARTRXMBAUD, UARTRXLBAUD,
and UARTRXSBAUD registers.
0 = Disables the capture features of the UART (Default)
1 = Enables the capture feature of the UART
Bit 1: RESERVED – Unused Bit
Bit 0: RX_SYNC_ON_START_EN – Enables the sync on start feature of the
UART RX. Set RX_INDEP_BAUD_EN to ‘1’ and the program the
UARTRXMBAUD, UARTRXLBAUD, and UARTRXSBAUD registers with the
desired communication speed to utilize this feature.
0 = Start bit is detected based on the free running TX baud rate counter.
(Default)
1 = Start bit immediately detected.
4.5.14 UART RX Control Register 5 (UARTRXCTRL5)
Address FFF7EC40 – UART 0 RX Control Register 5
Address FFF7ED40 – UART 1 RX Control Register 5
Bit
Number
Bit Name
Access
Default
1
0
RX_OVERSAMPLE_ERR
R
0
RX_INDEP_BAUD_EN
R/W
0
Bit 1: RX_OVERSAMPLE_ERR – Indicates when the 3 data samples taken in
the eye of the transmission are not identical.
0 = All sampled bits are identical
1 = Sampled bits are not identical
Bit 0: RX_INDEP_BAUD_EN – UART RX independent baud rate enabled
0 = Universal baud rate registers are used (UARTHBAUD,
UARTMBAUD, and UARTLBAUD) to program both the TX and RX
baud rates. One counter is used for both the TX and RX; therefore,
sync on start mode must be disabled. (Default)
1 = UART RX baud rate is programmed by the UARTRXMBAUD,
UARTRXLBAUD, and UARTRXSBAUD registers. UART TX baud
rate is programmed by the UARTHBAUD, UARTMBAUD,
UARTLBAUD, and UARTSBAUD registers. Two independent
counters are used for the TX and RX; therefore, sync on start mode
can be enabled.
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4.5.15 UART RX Baud Divisor Middle Byte Register (UARTRXMBAUD)
Address FFF7EC44– UART 0 RX Baud Divisor Middle Byte Register
Address FFF7ED44 – UART 1 RX Baud Divisor Middle Byte Register
Bit Number
Bit Name
Access
Default
7:0
RX_M_BAUD
R/W
0000_0000
Bits 7-0: RX_M_BAUD – Middle byte of the 16-bit RX baud rate selector.
This is a dual purpose register.
When RX_INDEP_BAUD_EN = 0 and RX_CAL_MODE_EN = 1 this register is
used to read the middle byte of the measured input baud pulse width.
When RX_INDEP_BAUD_EN = 1 this register is used to program the middle
byte of the 16-bit RX baud rate selector.
4.5.16 UART RX Baud Divisor Low Byte Register (UARTRXLBAUD)
Address FFF7EC48– UART 0 RX Baud Divisor Low Byte Register
Address FFF7ED48 – UART 1 RX Baud Divisor Low Byte Register
Bit Number
Bit Name
Access
Default
7:0
RX_L_BAUD
R/W
0000_0000
Bits 7-0: RX_L_BAUD – Low byte of the 16-bit RX baud rate selector.
This is a dual purpose register.
When RX_INDEP_BAUD_EN = 0 and RX_CAL_MODE_EN = 1 this register is
used to read the low byte of the measured input baud pulse width.
When RX_INDEP_BAUD_EN = 1 this register is used to program the low byte
of the 16-bit RX baud rate selector.
4.5.17 UART RX Baud Divisor Sub Bits Register (UARTRXSBAUD)
Address FFF7EC4C– UART 0 RX Baud Divisor Sub Bits Register
Address FFF7ED4C – UART 1 RX Baud Divisor Sub Bits Register
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Bit Number
Bit Name
Access
Default
2:0
RX_S_BAUD
R/W
000
Bit 2-0: RX_S_BAUD – Each LSB adds one ICLK period to the baud period
calculated via the values programed in the UARTRXMBAUD and
UARTRXLBAUD registers.
This is a dual purpose register.
When RX_INDEP_BAUD_EN = 0 and RX_CAL_MODE_EN = 1 this register is
used to read the sub bits of the measured input baud pulse width.
When RX_INDEP_BAUD_EN = 1 this register is used to program the sub bits of
the RX baud rate selector.
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4.6
ADC Registers
4.6.1 ADC Control Register (ADCCTRL)
Address 00140000
Bit Number
Bit Name
Access
Default
31:24
EXT_TRIG_DLY
R/W
0000_0000
23
EXT_TRIG_GPIO_VAL
R/W
0
Bit Number
Bit Name
Access
Default
21
EXT_TRIG_GPIO_EN
R/W
0
Bit Number
Bit Name
Access
Default
12
ADC_SEL_REF
R/W
0
Bit Number
Bit Name
Access
Default
3
SINGLE_SWEEP
R/W
0
20
EXT_TRIG_EN
R/W
0
11
ADC_ROUND
R/W
0
2
SW_START
R/W
0
22
EXT_TRIG_GPIO_DIR
R/W
0
19:16
EXT_TRIG_SEL
R/W
0000
10:8
BYPASS_EN
R/W
111
1
ADC_INT_EN
R/W
0
15:13
SAMPLING_SEL
R/W
000
7:4
MAX_CONV
R/W
0000
0
ADC_EN
R/W
0
Bits 31-24: EXT_TRIG_DLY – 8-bit External ADC Trigger Delay
configuration, LSB bit resolution equals period of ADC Clock (High Frequency
Oscillator Frequency divided by 4)
Bit 23: EXT_TRIG_GPIO_VAL – Output value of ADC_EXT_TRIG pin when
configured in GPIO mode
0 = ADC_EXT_TRIG pin driven low (Default)
1 = ADC_EXT_TRIG pin driven high
Bit 22: EXT_TRIG_GPIO_DIR – Direction of ADC_EXT_TRIG pin when
configured in GPIO mode
0 = ADC_EXT_TRIG pin configured as input (Default)
1 = ADC_EXT_TRIG pin configured as output
Bit 21: EXT_TRIG_GPIO_EN – Configuration of ADC_EXT_TRIG pin
0 = ADC_EXT_TRIG pin configured in functional mode (Default)
1 = ADC_EXT_TRIG pin configured in GPIO mode
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Bit 20: EXT_TRIG_EN – External Trigger Enable, conversions are started using
the external trigger as selectable by the EXT_TRIG_SEL bits.
0 = Disable External Trigger capability (Default)
1 = Enable External Trigger capability
Bits 19-16: EXT_TRIG_SEL – Selects which external trigger can start a
conversion loop.
0 = HS Loop1 Event 1 (DPWMA Low Resolution Edge) (Default)
1 = HS Loop1 Event 3 (DPWMB Low Resolution Edge)
2 = HS Loop2 Event 1 (DPWMA Low Resolution Edge)
3 = HS Loop2 Event 3 (DPWMB Low Resolution Edge)
4 = HS Loop3 Event 1 (DPWMA Low Resolution Edge)
5 = HS Loop3 Event 3 (DPWMB Low Resolution Edge)
6 = HS Loop4 Event 1 (DPWMA Low Resolution Edge)
7 = HS Loop4 Event 3 (DPWMB Low Resolution Edge)
8 = ADC_EXT_TRIG pin
9 = Analog Comparator A Output
A = Analog Comparator B Output
B = Analog Comparator C Output
C = Analog Comparator D Output
D = Analog Comparator E Output
E = Analog Comparator F Output
F = Analog Comparator G Output
Bits 15-13: ADC_SAMPLINGSEL - Defines ADC sampling and hold timing
setup, refer to ADC Specification for details on timing options
111 = 539KS/s
110 = 267KS/s
101 = 530KS/s
100 = 267KS/s
011 = 504KS/s
010 = 453KS/s
001 = 422KS/s
000 = 267KS/s (Default) (Setting at Production Test)
Bit 12: ADC_SEL_REF – ADC Voltage Reference Select
0 = Selects Internal ADC voltage reference (Default)
1 = Selects AVDD as ADC voltage reference
Bit 11: ADC_ROUND – Enables rounding of ADC Result to 10 bits
0 = ADC Results are not rounded (Default)
1 = ADC Results are rounded to 10 most significant bits
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Bits 10-8: BYPASS_EN – Enables dual sample/hold for specific channels. There
are only four valid settings:
011 = Dual Sample/Hold enabling on Channel 2
101 = Dual Sample/Hold enabling on Channel 1
110 = Dual Sample/Hold enabling on Channel 0
111 = Dual Sample/Hold Disabled (Default)
Bits 7-4: MAX_CONV – Maximum number of conversion done in one
conversion loop
0x0 = 1 conversion selection converted in the loop (Default)
0xF = All 16 conversion selections converted in the loop
Bit 3: SINGLE_SWEEP – ADC Conversion Mode
0 = Continuous conversion loop runs (Default)
1 = Single conversion loop run
Bit 2: SW_START - Firmware ADC Conversion Start, bit will be cleared
automatically by hardware at end of ADC conversion
0 = Conversions not initiated by firmware (Default)
1 = Initiate an ADC conversion loop
Bit 1: ADC_INT_EN – End-of-conversion Interrupt Enable
0 = Disable End-of-Conversion Interrupt (Default)
1 = Enable End-of-Conversion Interrupt
Bit 0: ADC_EN – ADC12 Enable Control
0 = Disables ADC (Default)
1 = Enables ADC
4.6.2 ADC Status Register (ADCSTAT)
Address 00140004
Bit Number
Bit Name
Access
Default
6:3
CURRENT_CH
R
-
2
ADC_EXT_TRIG_VAL
R
-
1
ADC_INT_RAW
R
-
0
ADC_INT
R
-
Bits 6-3: CURRENT_CH – Register shows the currently converting channel
Bit 2: ADC_EXT_TRIG_VAL – ADC_EXT_TRIG pin value
0 = ADC_EXT_TRIG pin driven low
1 = ADC_EXT_TRIG pin driven high
Bit 1: ADC_INT_RAW – End-of-conversion interrupt flag, raw version
0 = No End-of-conversion interrupt detected
1 = End-of-conversion interrupt found
Bit 0: ADC_INT – End-of-conversion interrupt flag, latched version
0 = No End-of-conversion interrupt detected
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1 = End-of-conversion interrupt found
4.6.3 ADC Test Control Register (ADCTSTCTRL)
Address 00140008
Bit Number
Bit Name
Access
Default
1
ADC_SH_BUFFER_EN
R/W
0
0
RESERVED
0
Bit 1: ADC_SH_BUFFER_EN - ADC Sample and Hold Buffer Enable
0 = Disables ADC SH Buffer (Default)
1 = Enables ADC SH Buffer
Bit 0: RESERVED – Unused bit
Note: Only zeroes should be written to other bits in this register besides ADC_SH_BUFFER_EN
4.6.4 ADC Sequence Select Register 0 (ADCSEQSEL0)
Address 0014000C
Bit Number
Bit Name
Access
Default
28
SEQ3_SH
R/W
0
Bit Number
Bit Name
Access
Default
15:13
RESERVED
000
27:24
SEQ3
R/W
0000
12
SEQ1_SH
R/W
0
23:21
RESERVED
000
11:8
SEQ1
R/W
0000
20
SEQ2_SH
R/W
0
7:5
RESERVED
000
4
SEQ0_SH
R/W
0
19:16
SEQ2
R/W
0000
3:0
SEQ0
R/W
0000
Bit 28: SEQ3_SH – Dual channel sequence select
0 = Not selected for Dual Sampling (Default)
1 = Selected for Dual Sampling
Bits 27-24: SEQ3 - Channel to be converted fourth
0000 = Channel 0 selected (Default)
0001 = Channel 1 selected
…….
1111 = Channel 15 selected
Bits 23-21: RESERVED – Unused bits
Bit 20: SEQ2_SH – Dual channel sequence select
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0 = Not selected for Dual Sampling (Default)
1 = Selected for Dual Sampling
Bits 19-16: SEQ2 - Channel to be converted third
0000 = Channel 0 selected (Default)
0001 = Channel 1 selected
…….
1111 = Channel 15 selected
Bits 15-13: RESERVED – Unused bits
Bit 12: SEQ1_SH – Dual channel sequence select
0 = Not selected for Dual Sampling (Default)
1 = Selected for Dual Sampling
Bits 11-8: SEQ1 - Channel to be converted second
0000 = Channel 0 selected (Default)
0001 = Channel 1 selected
…….
1111 = Channel 15 selected
Bits 7-5: RESERVED – Unused bits
Bit 4: SEQ0_SH – Dual channel sequence select
0 = Not selected for Dual Sampling (Default)
1 = Selected for Dual Sampling
Bits 3-0: SEQ0 - Channel to be converted first
0000 = Channel 0 selected (Default
0001 = Channel 1 selected
…….
1111 = Channel 15 selected
4.6.5 ADC Sequence Select Register 1 (ADCSEQSEL1)
Address 00140010
Bit Number
Bit Name
Access
Default
28
SEQ7_SH
R/W
0
Bit Number
Bit Name
Access
Default
15:13
RESERVED
000
27:24
SEQ7
R/W
0000
12
SEQ5_SH
R/W
0
23:21
RESERVED
000
11:8
SEQ5
R/W
0000
7:5
RESERVED
000
Bit 28 SEQ7_SH – Dual channel sequence select
0 = Not selected for Dual Sampling (Default)
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SEQ6_SH
R/W
0
4
SEQ4_SH
R/W
0
19:16
SEQ6
R/W
0000
3:0
SEQ4
R/W
0000
SLUA766
1 = Selected for Dual Sampling
Bits 27-24: SEQ7- Channel to be converted eighth
0000 = Channel 0 selected (Default)
0001 = Channel 1 selected
…….
1111 = Channel 15 selected
Bits 23-21: RESERVED – Unused bits
Bit 20: SEQ6_SH – Dual channel sequence select
0 = Not selected for Dual Sampling (Default)
1 = Selected for Dual Sampling
Bits 19-16: SEQ6 - Channel to be converted seventh
0000 = Channel 0 selected (Default)
0001 = Channel 1 selected
…….
1111 = Channel 15 selected
Bits 15-13: RESERVED – Unused bits
Bit 12: SEQ5_SH – Dual channel sequence select
0 = Not selected for Dual Sampling (Default)
1 = Selected for Dual Sampling
Bits 11-8: SEQ5 - Channel to be converted sixth
0000 = Channel 0 selected (Default)
0001 = Channel 1 selected
…….
1111 = Channel 15 selected
Bits 7-5: RESERVED – Unused bits
Bit 4: SEQ4_SH – Dual channel sequence select
0 = Not selected for Dual Sampling (Default)
1 = Selected for Dual Sampling
Bits 3-0: SEQ4 - Channel to be converted fifth
0000 = Channel 0 selected (Default)
0001 = Channel 1 selected
…….
1111 = Channel 15 selected
4.6.6 ADC Sequence Select Register 2 (ADCSEQSEL2)
Address 00140014
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Bit Number
Bit Name
Access
Default
28
SEQ11_SH
R/W
0
27:24
SEQ11
R/W
0000
Bit Number
Bit Name
Access
Default
15:13
RESERVED
000
12
SEQ9_SH
R/W
0
23:21
RESERVED
000
11:8
SEQ9
R/W
0000
7:5
RESERVED
000
Bit 28: SEQ11_SH – Dual channel sequence select
0 = Not selected for Dual Sampling (Default)
1 = Selected for Dual Sampling
Bits 27-24: SEQ11 - Channel to be converted twelth
0000 = Channel 0 selected (Default)
0001 = Channel 1 selected
…….
1111 = Channel 15 selected
Bits 23-21: RESERVED – Unused bits
Bit 20: SEQ10_SH – Dual channel sequence select
0 = Not selected for Dual Sampling (Default)
1 = Selected for Dual Sampling
Bits 19-16: SEQ10 - Channel to be converted eleventh
0000 = Channel 0 selected (Default)
0001 = Channel 1 selected
…….
1111 = Channel 15 selected
Bits 15-13: RESERVED – Unused bits
Bit 12: SEQ9_SH – Dual channel sequence select
0 = Not selected for Dual Sampling (Default)
1 = Selected for Dual Sampling
Bits 11-8: SEQ9 - Channel to be converted tenth
0000 = Channel 0 selected (Default)
0001 = Channel 1 selected
…….
1111 = Channel 15 selected
Bits 7-5: RESERVED – Unused bits
Bit 4: SEQ8_SH – Dual channel sequence select
0 = Not selected for Dual Sampling (Default)
1 = Selected for Dual Sampling
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SEQ10_SH
R/W
0
4
SEQ8_SH
R/W
0
19:16
SEQ10
R/W
0000
3:0
SEQ8
R/W
00000
SLUA766
Bits 3-0: SEQ8 - Channel to be converted ninth
0000 = Channel 0 selected (Default)
0001 = Channel 1 selected
…….
1111 = Channel 15 selected
4.6.7 ADC Sequence Select Register 3 (ADCSEQSEL3)
Address 00140018
Bit Number
Bit Name
Access
Default
28
SEQ15_SH
R/W
0
Bit Number
Bit Name
Access
Default
15:13
RESERVED
000
27:24
SEQ15
R/W
0000
12
SEQ13_SH
R/W
0
23:21
RESERVED
000
11:8
SEQ13
R/W
0000
20
SEQ14_SH
R/W
0
7:5
RESERVED
000
4
SEQ12_SH
R/W
0
19:16
SEQ14
R/W
0000
3:0
SEQ12
R/W
0000
Bit 28: SEQ15_SH – Dual channel sequence select
0 = Not selected for Dual Sampling (Default)
1 = Selected for Dual Sampling
Bits 27-24: SEQ15 - Channel to be converted sixteenth
0000 = Channel 0 selected (Default)
0001 = Channel 1 selected
…….
1111 = Channel 15 selected
Bits 23-21: RESERVED – Unused bits
Bit 20: SEQ14_SH – Dual channel sequence select
0 = Not selected for Dual Sampling (Default)
1 = Selected for Dual Sampling
Bits 19-16: SEQ14 - Channel to be converted fifteenth
0000 = Channel 0 selected (Default)
0001 = Channel 1 selected
…….
1111 = Channel 15 selected
Bits 15-13: RESERVED – Unused bits
Bit 12: SEQ13_SH – Dual channel sequence select
0 = Not selected for Dual Sampling (Default)
1 = Selected for Dual Sampling
Bits 11-8: SEQ13 - Channel to be converted fourteenth
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0000 = Channel 0 selected (Default)
0001 = Channel 1 selected
…….
1111 = Channel 15 selected
Bits 7-5: RESERVED – Unused bits
Bit 4: SEQ12_SH – Dual channel sequence select
0 = Not selected for Dual Sampling (Default)
1 = Selected for Dual Sampling
Bits 3-0: SEQ12 - Channel to be converted thirteenth
0000 = Channel 0 selected (Default)
0001 = Channel 1 selected
…….
1111 = Channel 15 selected
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4.6.8 ADC Result Registers 0-15 (ADCRESULTx, x=0:15)
Address 0014001C – ADC Result Register 0
Address 00140020 – ADC Result Register 1
Address 00140024 – ADC Result Register 2
Address 00140028 – ADC Result Register 3
Address 0014002C – ADC Result Register 4
Address 00140030 – ADC Result Register 5
Address 00140034 – ADC Result Register 6
Address 00140038 – ADC Result Register 7
Address 0014003C – ADC Result Register 8
Address 00140040 – ADC Result Register 9
Address 00140044 – ADC Result Register 10
Address 00140048 – ADC Result Register 11
Address 0014004C – ADC Result Register 12
Address 00140050 – ADC Result Register 13
Address 00140054 – ADC Result Register 14
Address 00140058 – ADC Result Register 15
Bit Number
Bit Name
Access
Default
11:0
RESULT
R
-
Bits 11-0: RESULT – Each sequence has a dedicated result register.
4.6.9 ADC Averaged Result Registers 0-5 (ADCAVGRESULTx, x=0:15)
Address 0014005C – ADC Averaged Result Register 0
Address 00140060 – ADC Averaged Result Register 1
Address 00140064 – ADC Averaged Result Register 2
Address 00140068 – ADC Averaged Result Register 3
Address 0014006C – ADC Averaged Result Register 4
Address 00140070 – ADC Averaged Result Register 5
Bit Number
Bit Name
Access
Default
11:0
RESULT
R
-
Bits 11-0: RESULT – First 6 ADC Results have an averaged result
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4.6.10 ADC Digital Compare Limits Register 0-5 (ADCCOMPLIMx, x=0:5)
Address 00140074 – ADC Digital Compare Limits Register 0
Address 00140078 – ADC Digital Compare Limits Register 1
Address 0014007C – ADC Digital Compare Limits Register 2
Address 00140080 – ADC Digital Compare Limits Register 3
Address 00140084 – ADC Digital Compare Limits Register 4
Address 00140088 – ADC Digital Compare Limits Register 5
Bit Number
Bit Name
Access
Default
27:16
UPPER_LIMIT
R/W
1111_1111_1111
15:12
RESERVED
0000
11:0
LOWER_LIMIT
R/W
0000_0000_0000
Bits 27-16: UPPER_LIMIT – Configures the upper limit value. If the ADC
conversion selected is equal or greater than the limit, the Digital Compare
Interrupt Flag is set (bit 22 of ADC Control Register 1). Results of comparison
can be read from the ADC Digital Compare Results Register (see Section 4.6.12).
Bits 15-12: RESERVED – Unused bits – Default to 0000
Bits 11-0: LOWER_LIMIT – Configures the lower limit value. If the ADC
conversion selected is equal or less than the limit, the Digital Compare Interrupt
Flag is set (bit 22 of ADC Control Register 1). Results of comparison can be read
from the ADC Digital Compare Results Register (see Section 4.6.12).
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4.6.11 ADC Digital Compare Enable Register (ADCCOMPEN)
Address 0014008C
Bit Number
Bit Name
Access
Default
27
COMP5_UP_INT_EN
R/W
0
26
COMP5_LO_INT_EN
R/W
0
25
COMP4_UP_INT_EN
R/W
0
24
COMP4_LO_INT_EN
R/W
0
Bit Number
Bit Name
Access
Default
23
COMP3_UP_INT_EN
R/W
0
22
COMP3_LO_INT_EN
R/W
0
21
COMP2_UP_INT_EN
R/W
0
20
COMP2_LO_INT_EN
R/W
0
Bit Number
Bit Name
Access
Default
19
COMP1_UP_INT_EN
R/W
0
18
COMP1_LO_INT_EN
R/W
0
17
COMP0_UP_INT_EN
R/W
0
16
COMP0_LO_INT_EN
R/W
0
Bit Number
Bit Name
Access
Default
15:14
RESERVED
00
13
COMP5_DATA_SEL
R/W
0
12
COMP4_DATA_SEL
R/W
0
11
COMP3_DATA_SEL
R/W
0
Bit Number
Bit Name
Access
Default
10
COMP2_DATA_SEL
R/W
0
9
COMP1_DATA_SEL
R/W
0
8
COMP0_DATA_SEL
R/W
0
7:6
RESERVED
00
Bit Number
Bit Name
Access
Default
5
COMP5_EN
R/W
0
4
COMP4_EN
R/W
0
3
COMP3_EN
R/W
0
2
COMP2_EN
R/W
0
1
COMP1_EN
R/W
0
Bit 27: COMP5_UP_INT_EN – Digital Comparator 5 Upper Limit Interrupt
Enable
0 = Interrupt generation disabled on result above upper limit (Default)
1 = Interrupt generation enabled on result above upper limit
Bit 26: COMP5_LO_INT_EN – Digital Comparator 5 Lower Limit Interrupt
Enable
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0
COMP0_EN
R/W
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0 = Interrupt generation disabled on result below lower limit (Default)
1 = Interrupt generation enabled on result below lower limit
Bit 25: COMP4_UP_INT_EN – Digital Comparator 4 Upper Limit Interrupt
Enable
0 = Interrupt generation disabled on result above upper limit (Default)
1 = Interrupt generation enabled on result above upper limit
Bit 24: COMP4_LO_INT_EN – Digital Comparator 4 Lower Limit Interrupt
Enable
0 = Interrupt generation disabled on result below lower limit (Default)
1 = Interrupt generation enabled on result below lower limit
Bit 23: COMP3_UP_INT_EN – Digital Comparator 3 Upper Limit Interrupt
Enable
0 = Interrupt generation disabled on result above upper limit (Default)
1 = Interrupt generation enabled on result above upper limit
Bit 22: COMP3_LO_INT_EN – Digital Comparator 3 Lower Limit Interrupt
Enable
0 = Interrupt generation disabled on result below lower limit (Default)
1 = Interrupt generation enabled on result below lower limit
Bit 21: COMP2_UP_INT_EN – Digital Comparator 2 Upper Limit Interrupt
Enable
0 = Interrupt generation disabled on result above upper limit (Default)
1 = Interrupt generation enabled on result above upper limit
Bit 20: COMP2_LO_INT_EN – Digital Comparator 2 Lower Limit Interrupt
Enable
0 = Interrupt generation disabled on result below lower limit (Default)
1 = Interrupt generation enabled on result below lower limit
Bit 19: COMP1_UP_INT_EN – Digital Comparator 1 Upper Limit Interrupt
Enable
0 = Interrupt generation disabled on result above upper limit (Default)
1 = Interrupt generation enabled on result above upper limit
Bit 18: COMP1_LO_INT_EN – Digital Comparator 1 Lower Limit Interrupt
Enable
0 = Interrupt generation disabled on result below lower limit (Default)
1 = Interrupt generation enabled on result below lower limit
Bit 17: COMP0_UP_INT_EN – Digital Comparator 0 Upper Limit Interrupt
Enable
0 = Interrupt generation disabled on result above upper limit (Default)
1 = Interrupt generation enabled on result above upper limit
Bit 16: COMP0_LO_INT_EN – Digital Comparator 0 Lower Limit Interrupt
Enable
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0 = Interrupt generation disabled on result below lower limit (Default)
1 = Interrupt generation enabled on result below lower limit
Bits 15-14: RESERVED – Unused bits
Bit 13: COMP5_DATA_SEL – Digital Comparator 5 Data Select
0 = Raw ADC Result 5 used for comparison (Default)
1 = Averaged ADC Result 5 used for comparison
Bit 12: COMP4_DATA_SEL – Digital Comparator 4 Data Select
0 = Raw ADC Result 4 used for comparison (Default)
1 = Averaged ADC Result 4 used for comparison
Bit 11: COMP3_DATA_SEL – Digital Comparator 3 Data Select
0 = Raw ADC Result 3 used for comparison (Default)
1 = Averaged ADC Result 3 used for comparison
Bit 10: COMP2_DATA_SEL – Digital Comparator 2 Data Select
0 = Raw ADC Result 2 used for comparison (Default)
1 = Averaged ADC Result 2 used for comparison
Bit 9: COMP1_DATA_SEL – Digital Comparator 1 Data Select
0 = Raw ADC Result 1 used for comparison (Default)
1 = Averaged ADC Result 1 used for comparison
Bit 8: COMP0_DATA_SEL – Digital Comparator 0 Data Select
0 = Raw ADC Result 0 used for comparison (Default)
1 = Averaged ADC Result 0 used for comparison
Bits 7-6: RESERVED – Unused bits
Bit 5: COMP5_EN – Digital Comparator 5 Enable
0 = Comparator Disabled (Default)
1 = Comparator Enabled
Bit 4: COMP4_EN – Digital Comparator 4 Enable
0 = Comparator Disabled (Default)
1 = Comparator Enabled
Bit 3: COMP3_EN – Digital Comparator 3 Enable
0 = Comparator Disabled (Default)
1 = Comparator Enabled
Bit 2: COMP2_EN – Digital Comparator 2 Enable
0 = Comparator Disabled (Default)
1 = Comparator Enabled
Bit 1: COMP1_EN – Digital Comparator 1 Enable
0 = Comparator Disabled (Default)
1 = Digital Comparator 1 Enabled
Bit 0: COMP0_EN – Digital Comparator 0 Enable
0 = Comparator Disabled (Default)
1 = Comparator Enabled
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4.6.12 ADC Digital Compare Results Register (ADCCOMPRESULT)
Address 00140090
Bit Number
Bit Name
Access
Default
27
DCOMP5_UP_RAW
R
-
26
DCOMP5_LO_RAW
R
-
25
DCOMP4_UP_RAW
R
-
24
DCOMP4_LO_RAW
R
-
Bit Number
Bit Name
Access
Default
23
DCOMP3_UP_RAW
R
-
22
DCOMP3_LO_RAW
R
-
21
DCOMP2_UP_RAW
R
-
20
DCOMP2_LO_RAW
R
-
Bit Number
Bit Name
Access
Default
19
DCOMP1_UP_RAW
R
-
18
DCOMP1_LO_RAW
R
-
17
DCOMP0_UP_RAW
R
-
16
DCOMP0_LO_RAW
R
-
Bit Number
Bit Name
Access
Default
15:12
RESERVED
0000
11
DCOMP5_UP_INT
R
-
10
DCOMP5_LO_INT
R
-
9
DCOMP4_UP_INT
R
-
Bit Number
Bit Name
Access
Default
8
DCOMP4_LO_INT
R
-
7
DCOMP3_UP_INT
R
-
6
DCOMP3_LO_INT
R
-
5
DCOMP2_UP_INT
R
-
Bit Number
Bit Name
Access
Default
4
DCOMP2_LO_INT
R
-
3
DCOMP1_UP_INT
R
-
2
DCOMP1_LO_INT
R
-
1
DCOMP0_UP_INT
R
-
Bit Number
Bit Name
Access
Default
0
DCOMP0_LO_INT
R
-
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Bit 27: DCOMP5_UP_RAW – Digital Comparator 5 Upper Limit Raw Result
0 = Limit not exceeded
1 = Limit exceeded
Bit 26: DCOMP5_LO_RAW – Digital Comparator 5 Lower Limit Raw Result
0 = Limit not exceeded
1 = Limit exceeded
Bit 25: DCOMP4_UP_RAW – Digital Comparator 4 Upper Limit Raw Result
0 = Limit not exceeded
1 = Limit exceeded
Bit 24: DCOMP4_LO_RAW – Digital Comparator 4 Lower Limit Raw Result
0 = Limit not exceeded
1 = Limit exceeded
Bit 23: DCOMP3_UP_RAW – Digital Comparator 3 Upper Limit Raw Result
0 = Limit not exceeded
1 = Limit exceeded
Bit 22: DCOMP3_LO_RAW – Digital Comparator 3 Lower Limit Raw Result
0 = Limit not exceeded
1 = Limit exceeded
Bit 21: DCOMP2_UP_RAW – Digital Comparator 2 Upper Limit Raw Result
0 = Limit not exceeded
1 = Limit exceeded
Bit 20: DCOMP2_LO_RAW – Digital Comparator 2 Lower Limit Raw Result
0 = Limit not exceeded
1 = Limit exceeded
Bit 19: DCOMP1_UP_RAW – Digital Comparator 1 Upper Limit Raw Result
0 = Limit not exceeded
1 = Limit exceeded
Bit 18: DCOMP1_LO_RAW – Digital Comparator 1 Lower Limit Raw Result
0 = Limit not exceeded
1 = Limit exceeded
Bit 17: DCOMP0_UP_RAW – Digital Comparator 0 Upper Limit Raw Result
0 = Limit not exceeded
1 = Limit exceeded
Bit 16: DCOMP0_LO_RAW – Digital Comparator 0 Lower Limit Raw Result
0 = Limit not exceeded
1 = Limit exceeded
Bits 15-12: RESERVED – Unused bits
Bit 11: DCOMP5_UP_INT – Digital Comparator 5 Upper Limit Interrupt
Result, cleared on read
0 = Limit not exceeded
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1 = Limit exceeded
Bit 10: DCOMP5_LO_INT – Digital Comparator 5 Lower Limit Interrupt
Result, cleared on read
0 = Limit not exceeded
1 = Limit exceeded
Bit 9: DCOMP4_UP_INT – Digital Comparator 4 Upper Limit Interrupt Result,
cleared on read
0 = Limit not exceeded
1 = Limit exceeded
Bit 8: DCOMP4_LO_INT – Digital Comparator 4 Lower Limit Interrupt Result,
cleared on read
0 = Limit not exceeded
1 = Limit exceeded
Bit 7: DCOMP3_UP_INT – Digital Comparator 3 Upper Limit Interrupt Result,
cleared on read
0 = Limit not exceeded
1 = Limit exceeded
Bit 6: DCOMP3_LO_INT – Digital Comparator 3 Lower Limit Interrupt Result,
cleared on read
0 = Limit not exceeded
1 = Limit exceeded
Bit 5: DCOMP2_UP_INT – Digital Comparator 2 Upper Limit Interrupt Result,
cleared on read
0 = Limit not exceeded
1 = Limit exceeded
Bit 4: DCOMP2_LO_INT – Digital Comparator 2 Lower Limit Interrupt Result,
cleared on read
0 = Limit not exceeded
1 = Limit exceeded
Bit 3: DCOMP1_UP_INT – Digital Comparator 1 Upper Limit Interrupt Result,
cleared on read
0 = Limit not exceeded
1 = Limit exceeded
Bit 2: DCOMP1_LO_INT – Digital Comparator 1 Lower Limit Interrupt Result,
cleared on read
0 = Limit not exceeded
1 = Limit exceeded
Bit 1: DCOMP0_UP_INT – Digital Comparator 0 Upper Limit Interrupt Result,
cleared on read
0 = Limit not exceeded
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1 = Limit exceeded
Bit 0: DCOMP0_LO_INT – Digital Comparator 0 Lower Limit Interrupt Result,
cleared on read
0 = Limit not exceeded
1 = Limit exceeded
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4.6.13 ADC Averaging Control Register (ADCAVGCTRL)
Address 00140094
Bit Number
Bit Name
Access
Default
22:21
AVG5_CONFIG
R/W
00
Bit Number
Bit Name
Access
Default
15
RESERVED
0
20
AVG5_EN
R/W
0
19
RESERVED
0
14:13
AVG3_CONFIG
R/W
00
Bit Number
Bit Name
Access
Default
10:9
AVG2_CONFIG
R/W
00
8
AVG2_EN
R/W
0
Bit Number
Bit Name
Access
Default
4
AVG1_EN
R/W
0
3
RESERVED
0
18:17
AVG4_CONFIG
R/W
00
12
AVG3_EN
R/W
0
7
RESERVED
0
2:1
AVG0_CONFIG
R/W
00
16
AVG4_EN
R/W
0
11
RESERVED
0
6:5
AVG1_CONFIG
R/W
00
0
AVG0_EN
R/W
0
.
Bits 22-21: AVG5_CONFIG – ADC Averaging Module 5 Configuration
0 = Moving average of 4 samples (Default)
1 = Moving average of 8 samples
2 = Moving average of 16 samples
3 = Moving average of 32 samples
Bit 20: AVG5_EN – ADC Averaging Module 5 Enable
0 = ADC Averaging Disabled (Default)
1 = ADC Averaging Enabled
Bit 19: RESERVED – Unused bit
Bits 18-17: AVG4_CONFIG – ADC Averaging Module 4 Configuration
0 = Moving average of 4 samples (Default)
1 = Moving average of 8 samples
2 = Moving average of 16 samples
3 = Moving average of 32 samples
Bit 16: AVG4_EN – ADC Averaging Module 4 Enable
0 = ADC Averaging Disabled (Default)
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1 = ADC Averaging Enabled
Bit 15: RESERVED – Unused bit
Bits 14-13: AVG3_CONFIG – ADC Averaging Module 3 Configuration
0 = Moving average of 4 samples (Default)
1 = Moving average of 8 samples
2 = Moving average of 16 samples
3 = Moving average of 32 samples
Bit 12: AVG3_EN – ADC Averaging Module 3 Enable
0 = ADC Averaging Disabled (Default)
1 = ADC Averaging Enabled
Bit 11: RESERVED – Unused bit
Bits 10-9: AVG2_CONFIG – ADC Averaging Module 2 Configuration
0 = Moving average of 4 samples (Default)
1 = Moving average of 8 samples
2 = Moving average of 16 samples
3 = Moving average of 32 samples
Bit 8: AVG2_EN – ADC Averaging Module 4 Enable
0 = ADC Averaging Disabled (Default)
1 = ADC Averaging Enabled
Bit 7: RESERVED – Unused bit
Bits 6-5: AVG1_CONFIG – ADC Averaging Module 1 Configuration
0 = Moving average of 4 samples (Default)
1 = Moving average of 8 samples
2 = Moving average of 16 samples
3 = Moving average of 32 samples
Bit 4: AVG1_EN – ADC Averaging Module 1 Enable
0 = ADC Averaging Disabled (Default)
1 = ADC Averaging Enabled
Bit 3: RESERVED – Unused bit
Bits 2-1: AVG0_CONFIG – ADC Averaging Module 0 Configuration
0 = Moving average of 4 samples (Default)
1 = Moving average of 8 samples
2 = Moving average of 16 samples
3 = Moving average of 32 samples
Bit 0: AVG0_EN – ADC Averaging Module 0 Enable
0 = ADC Averaging Disabled (Default)
1 = ADC Averaging Enabled
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4.7
DPWM 0-3 Registers
4.7.1 DPWM Control Register 0 (DPWMCTRL0)
Address 00150000 – DPWM 3 Control Register 0
Address 00170000 – DPWM 2 Control Register 0
Address 001A0000 – DPWM 1 Control Register 0
Address 001D0000 – DPWM 0 Control Register 0
Bit Number
Bit Name
Access
Default
Bit Number
Bit Name
Access
Default
31:28
PWM_B_INTRA_MUX
R/W
0000
27:24
PWM_A_INTRA_MUX
R/W
0000
23
CBC_PWM_C_EN
R/W
0
Bit Number
Bit Name
Access
Default
22:21
RESERVED
R
0
20
CBC_PWM_AB_EN
R/W
0
19
CBC_ADV_CNT_EN
R/W
0
Bit Number
Bit Name
Access
Default
18:17
MIN_DUTY_MODE
R/W
00
16
RESERVED
R
0
15
MSYNC_SLAVE_EN
R/W
0
Bit Number
14
13
D_ENABLE
RESERVED
Access
R/W
R
Default
0
0
Bit Name
Bit Number
Bit Name
Access
Default
164
12
RESON_MODE_FIXED_DUTY_EN
R/W
0
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PWM_B_FLT_POL
R/W
0
10
PWM_A_FLT_POL
R/W
0
SLUA766
Bit Number
Bit Name
Access
Default
Bit Number
Bit Name
Access
Default
9
BLANK_B_EN
R/W
0
3
PWM_B_INV
R/W
0
8
BLANK_A_EN
R/W
0
2
PWM_A_INV
R/W
0
7
RESERVED
R
0
6:4
PWM_MODE
R/W
010
1
CLA_EN
R/W
1
0
PWM_EN
R/W
0
Bits 31-28: PWM_B_INTRA_MUX – Interchanges signals post edge generation
0 = Pass-through (Default)
1 = Edge-gen output, this module
2 = PWM-C, this module
3 = Crossover, this module
4 = Pass-through below A
5 = Pass-through below B
6 = Pass-through below C
7 = Pass-through below level-2 C
8 = Pass-through below level-3 C
Bits 27-24: PWM_A_INTRA_MUX – Combines signals prior to HR module
0 = Pass-through (Default)
1 = Edge-gen output, this module
2 = PWM-C, this module
3 = Crossover, this module
4 = Pass-through below A
5 = Pass-through below B
6 = Pass-through below C
7 = Pass-through below level-2 C
8 = Pass-through below level-3 C
Bit 23: CBC_PWM_C_EN – Set if Fault CBC changes PWM-C output
0 = PWM-C unaffected by Fault CBC (Default)
1 = PWM-C affected by Fault CBC
Bits 22-21: RESERVED – Unused Bits
Bit 20: CBC_PWM_AB_EN – Set if Fault CBC changes output waveform for
PWM-A and PWM-B
0 = PWM-A and PWM-B unaffected by Fault CBC (Default)
1 = PWM-A and PWM-B affected by Fault CBC
Bit 19: CBC_ADV_CNT_EN – Selects cycle-by-cycle of operation
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Normal Mode
0 = CBC disabled (Default)
1 = CBC enabled
Multi and Resonant Modes
0 = PWM-A and PWM-B operate independently (Default)
1 = PWM-A and PWM-B pulse matching enabled
Bits 18-17: MIN_DUTY_MODE – Minimum Duty Cycle Mode
00 = Suppression of minimum duty cycles is disabled (Default)
01 = CLA value is clamped to zero when below input value is less than
MIN_DUTY_LOW
10 = CLA value is clamped to MIN_DUTY_LOW register value when
input value is less than MIN_DUTY_LOW
Bit 16: RESERVED – Unused Bit
Bit 15: MSYNC_SLAVE_EN – Multi-Sync Slave Mode Control
0 = PWM not synchronized to another PWM channel (Default)
1 = Enable Multi-Sync Slave Mode, current channel will be slaved from
corresponding channel
Bit 14: D_ENABLE – Converts CLA duty value to DPWM as period-CLA duty
value
0 = Value used for event calculations if CLA Duty (Default)
1 = Value used for event calculations is period minus CLA duty value
Bit 13: RESERVED – Unused Bit
Bit 12: RESON_MODE_FIXED_DUTY_EN – Configures how duty cycle is
controlled in Resonance Mode
0 = Resonant mode duty cycle set by Filter duty (Default)
1 = Resonant mode duty cycle set by Auto Switch High Register
Bit 11: PWM_B_FLT_POL – Sets the fault output polarity during a disable
condition (i.e. fault or module disabled)
0 = PWM B fault output polarity is set to low (Default)
1 = PWM B fault output polarity is set to high
Bit 10: PWM_A_FLT_POL – Sets the fault output polarity during a disable
condition (i.e. fault or module disabled)
0 = PWM A fault output polarity is set to low (Default)
1 = PWM A fault output polarity is set to high
Bit 9: BLANK_B_EN – Comparator Blanking Window B Enable
0 = Comparator Blanking Window for PWM-B Disabled (Default)
1 = Comparator Blanking Window for PWM-B Enabled
Bit 8: BLANK_A_EN – Comparator Blanking Window A Enable
0 = Comparator Blanking Window for PWM-A Disabled (Default)
1 = Comparator Blanking Window for PWM-B Enabled
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Bit 7: RESERVED – Unused Bit
Bits 6-4: PWM_MODE – DPWM Mode
0 = Normal Mode
1 = Resonant Mode
2 = Multi-Output Mode
3 = Triangular Mode
4 = Leading Mode
Bit 3: PWM_B_INV – PWM B Output Polarity Control
0 = Non-inverted PWM B output (Default)
1 = Inverts PWM B output
Bit 2: PWM_A_INV – PWM A Output Polarity Control
0 = Non-inverted PWM A output (Default)
1 = Inverted PWM A output
Bit 1: CLA_EN– CLA Processing Enable
0 = Generate PWM waveforms from PWM Register values (Default)
1 = Enable CLA input
Bit 0: PWM_EN – PWM Processing Enable
0 = Disable PWM module, outputs zero (Default)
1 = Enable PWM operation
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4.7.2 DPWM Control Register 1 (DPWMCTRL1)
Address 00150004 – DPWM 3 Control Register 1
Address 00170004 – DPWM 2 Control Register 1
Address 001A0004 – DPWM 1 Control Register 1
Address 001D0004 – DPWM 0 Control Register 1
Bit Number
Bit Name
Access
Default
Bit Number
Bit Name
Access
Default
Bit Number
Bit Name
Access
Default
Bit Number
Bit Name
Access
Default
Bit Number
Bit Name
Access
Default
Bit Number
Bit Name
Access
Default
31
PRESET_EN
R/W
0
30
SYNC_FET_EN
R/W
0
27:24
SYNC_OUT_DIV_SEL
R/W
0000
29
BURST_EN
R/W
0
23:21
CLA_SCALE
R/W
000
28
CLA_DUTY_ADJ_EN
R/W
0
20
EXT_SYNC_EN
R/W
0
18
17
16
15
AUTO_MODE_SEL
RESERVED
EVENT_UP_SEL
CHECK_OVERRIDE
R/W
0
R
0
R/W
01
R/W
1
13
PWM_B_OE
R/W
0
12
PWM_A_OE
R/W
0
11
GPIO_B_VAL
R/W
0
8
GPIO_A_EN
R/W
0
7
PWM_HR_MULTI_OUT_EN
R/W
0
4
PWM_A_PROT_DIS
R/W
0
3:2
HIRES_SCALE
R/W
00
10
GPIO_B_EN
R/W
0
6
SFRAME_EN
R/W
0
1
RESERVED
R
0
Bit 31: PRESET_EN – Counter Preset Enable
0 = Counter reset to 0 upon detection of sync (Default)
168
19
CBC_BSIDE_ACTIVE EN
R/W
0
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GLOBAL
PERIOD EN
R/W
0
9
GPIO_A_VAL
R/W
0
5
PWM_B_PROT_DIS
R/W
0
0
HIRES_DIS
R/W
0
SLUA766
1 = Counter preset to Preset Count Value upon detection of sync
Bit 30: SYNC_FET_EN – SyncFET Mode Enabled
0 = SyncFET Mode Disabled (Default)
1 = SyncFET Mode Enabled (Default)
Bit 29: BURST_EN – Burst (Light Load) Mode Detection Enable
0 = Burst Mode (Light Load) Detection disabled (Default)
1 = Burst Mode (Light Load) Detection enabled
Bit 28: CLA_DUTY_ADJ_EN – Enables CLA Duty Adjust from Current/Flux
Balancing
0 = CLA Duty Adjust not enabled (Default)
1 = CLA Duty Adjust enabled
Bits 27-24: SYNC_OUT_DIV_SEL – Sets the divider for generating the Sync
Out pulse.
0000 = Sync Out generated on every switching cycle (Default)
0001 = Sync Out generated once every 2 switching cycles
0010 = Sync Out generated once every 3 switching cycles
……….
1111 = Sync Out generated once every 16 switching cycles
Bits 23-21: CLA_SCALE – Scaling for CLA Input Data
000 = CLA Value (Default)
001 = CLA Value multiplied by 2
010 = CLA Value divided by 2
011 = CLA Value multiplied by 4
100 = CLA Value divided by 4
101 = CLA Value multiplied by 8
110 = CLA Value divided by 8
111 = CLA Value
Bit 20: EXT SYNC_EN – Slave DPWM to external sync
0 = DPWM not synchronized to external sync (Default)
1 = Slave DPWM to external sync
Bit 19: CBC_BSIDE_ACTIVE_EN – Sets if CBC responds to Fault CBC when
PWM-B is active, only available in Multi and Reson modes
0 = Response to Fault CBC when PWM-A active (Default)
1 = Response to Fault CBC when PWM-A or PWM-B active
Bit 18: AUTO_MODE_SEL – Auto Switching Mode Select
0 = Auto Switching Mode disabled (Default)
1 = Auto Switching Mode enabled
Bits 17: RESERVED – Unused Bit
Bits 16: EVENT_UP_SEL – Update End Period Mode
0 = Events update at any time
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1 = Events update at the end of the period (recommended)
Bit 15: CHECK_OVERRIDE – PWM Check Override
0 = DPWM checks mathematical settings within module, correct
placement of Event settings/period settings. Invalid configurations are not
allowed. (Default)
1 = Overrides checking for invalid configurations and turns off PWM
mathematical checking functions
Bit 14: GLOBAL_PERIOD_EN
0 = Event calculations use DPWM Period register (Default)
1 = Event calculations use Global Period register
Bit 13: PWM_B_OE – Direction for PWM B pin
0 = PWM B configured as output (Default)
1 = PWM B configured as input
Bit 12: PWM_A_OE – Direction for PWM A pin
0 = PWM A configured as output (Default)
1 = PWM A configured as input
Bit 11: GPIO_B_VAL – Sets value of PWM B output in GPIO mode
0 = PWM B driven low in GPIO mode (Default)
1 = PWM B driven high in GPIO mode
Bit 10: GPIO_B_EN – Enables GPIO mode for PWM B output
0 = PWM B in DPWM mode (Default)
1 = PWM B in GPIO mode
Bit 9: GPIO_A_VAL – Sets value of PWM A output in GPIO mode
0 = PWM A driven low in GPIO mode (Default)
1 = PWM A driven high in GPIO mode
Bit 8: GPIO_A_EN – Enables GPIO mode for PWM A output
0 = PWM A in DPWM mode (Default)
1 = PWM A in GPIO mode
Bit 7: PWM_HR_MULT_OUT_EN – Control bit for Hi-Res Block
0 = Disabled (Default)
1 = Enabled
Bit 6: SFRAME_EN – PWM Single Step Frame Mode Enable
0 = Disable Single Frame Mode (Default)
1 = Enable Single Step Frame Mode. One EADC sample is requested,
CLA then Filters, then one PWM duty cycle performed, then wait on
Single Frame Trigger toggle before advancing to next frame.
Bit 5: PWM_B_PROT_DIS – PWM B Asynchronous Protection Disable
0 = Allows asynchronous protection to turn off PWM B Output (Default)
1 = Disables asynchronous protection from turning off PWM B Output
Bit 4: PWM_A_PROT_DIS – PWM A Asynchronous Protection Disable
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0 = Allows asynchronous protection to turn off PWM A Output (Default)
1 = Disables asynchronous protection from turning off PWM A Output
Bits 3-2: HIRES_SCALE – Determines resolution of high resolution steps
00 = Resolution of 16 phases. Full resolution enabled. Resolution step =
PCLK/16 (Default)
11 = Resolution of 2 phases. Resolution step = PCLK/2
10 = Resolution of 4 phases. Resolution step = PCLK/4
01 = Resolution of 8 phases. Resolution step = PCLK/8
00 = Resolution of 16 phases. Full Resolution enabled.
Resolution step = PCLK/16
Bit 1: RESERVED – Unused Bit
Bit 0: HIRES_DIS – PWM High Resolution Disable
0 = Enable High Resolution logic (Default)
1 = Disable High Resolution logic
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4.7.3 DPWM Control Register 2 (DPWMCTRL2)
Address 00150008 – DPWM 3 Control Register 2
Address 00170008 – DPWM 2 Control Register 2
Address 001A0008 – DPWM 1 Control Register 2
Address 001D0008 – DPWM 0 Control Register 2
Bit Number
Bit Name
Access
Default
Bit Number
Bit Name
Access
Default
Bit Number
Bit Name
Access
Default
Bit Number
Bit Name
Access
Default
Bit Number
Bit Name
Access
Default
19:18
DTC_MODE
R/W
00
17
DTC_EN
R/W
0
15:12
SYNC_IN_DIV_RATIO
R/W
0000
9:8
FILTER_DUTY_SEL
R/W
00
7
IDE_DUTY_B_EN
R/W
0
5:4
SAMPLE_TRIG_1_OVERSAMPLE
R/W
00
1
SAMPLE_TRIG_2_EN
R/W
0
16
BLANK_PCM_EN
R/W
0
11:10
RESERVED
R
0
6
IDE_DETECT_EN
R/W
0
3:2
SAMPLE_TRIG_1_MODE
R/W
00
0
SAMPLE_TRIG_1_EN
R/W
1
Bit 19-18: DTC_MODE – DTC Mode Select
00 = Only DTC phase adjust A utilized in edge adjustments (Default)
01 = Only DTC phase adjust B utilized in edge adjustments
10 = Both DTC phase adjust A and B utilized in edge adjustments
11 = Reserved
Bit 17: DTC_EN – Enables Dead Time Compensation Mode
0 = Disabled (Default)
1 = Enabled
Bit 16: BLANK_PCM_EN – PCM Blanking Enable
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0 = Blanking A window is not used with the PCM input (Default)
1 = Blanking A window is used with the PCM input
Bits 15-12: SLAVE_SYNC_IN_DIV_RATIO – Sets the number of syncs to be
masked before a resync
Bit 11-10: RESERVED – Unused Bit
Bits 9-8: FILTER_DUTY_SEL – Sets which register is used for the max duty
calculation at the Filter in RESON and MESH modes.
0 = PWM Period Register (Default)
1 = Event 2
2 = PWM Period Adjust Register (Bits 13:0)
Bit 7: IDE_DUTY_B_EN – IDE Duty Cycle Side B Enable
0 = Disabled (Default)
1 = Enabled
Bit 6: IDE_DETECT_EN – IDE Detect Enable
0 = Disabled (Default)
1 = Enabled
Bits 5-4: SAMPLE_TRIG_1_OVERSAMPLE – Oversample Select for Sample
Trigger 1
00 = Trigger an EADC Sample at PWM Sample Trig Register value
(Default)
01 = Trigger an EADC Sample at PWM Sample Trig Register value and at
PWM Sample Trig Register value divided by 2
10 = Trigger a EADC Sample at PWM Sample Trig Register value, at
PWM Sample Trig Register value divided by 2 and at PWM Sample Trig
Register value divided by 4
11 = Trigger a EADC Sample at PWM Sample Trig Register value, at
PWM Sample Trig Register value divided by 2, at PWM Sample Trig
Register value divided by 4 and at PWM Sample Trig Register value
divided by 8
Bits 3-2: SAMPLE_TRIG_1_MODE – Mode select for Sample Trigger 1
00 = Trigger value is set using PWM Sample Trig Register value (Default)
01 = Trigger value is adaptive midpoint (EV1+CLA_DUTY/2 + Adaptive
Offset) and uses current CLA value at update event
10 = Trigger value is adaptive midpoint (EV1+CLA_DUTY + Adaptive
Offset) and uses current CLA value at update event
11 = Trigger value is adaptive based on previous CBC location + Adaptive
Offset
Bit 1: SAMPLE_TRIG_2_EN – Sample Trigger 2 Enable
0 = Disable Sample Trigger 2 (Default)
1 = Enable Sample Trigger 2
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Bit 0: SAMPLE_TRIG_1_EN – Sample Trigger 1 Enable
0 = Disable Sample Trigger 1
1 = Enable Sample Trigger 1(Default)
4.7.4 DPWM Period Register (DPWMPRD)
Address 0015000C – DPWM 3 Period Register
Address 0017000C – DPWM 2 Period Register
Address 001A000C – DPWM 1 Period Register
Address 001D000C – DPWM 0 Period Register
Bit Number
Bit Name
Access
Default
17:4
PRD
R/W
00_0011_0100_0001
3:0
RESERVED
0000
Bits 17-4: PRD – PWM Period. Low resolution register, last 4 bits are read-only.
Bits 3-0: RESERVED – Unused bits
4.7.5 DPWM Event 1 Register (DPWMEV1)
Address 00150010 – DPWM 3 Event 1 Register
Address 00170010 – DPWM 2 Event 1 Register
Address 001A0010 – DPWM 1 Event 1 Register
Address 001D0010 – DPWM 0 Event 1 Register
Bit Number
Bit Name
Access
Default
17:4
EVENT1
R/W
00_0000_0001_0100
3:0
RESERVED
0000
Bits 17-4: EVENT1 – Configures the location of Event 1. Low resolution
register, last 4 bits are unused.
Bits 3-0: RESERVED – Unused bits
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4.7.6 DPWM Event 2 Register (DPWMEV2)
Address 00150014 – DPWM 3 Event 2 Register
Address 00170014 – DPWM 2 Event 2 Register
Address 001A0014 – DPWM 1 Event 2 Register
Address 001D0014 – DPWM 0 Event 2 Register
Bit Number
Bit Name
Access
Default
17:0
EVENT2
R/W
0_0000_0011_0000_0000
Bits 17-0: EVENT2 – Configures the location of Event 2. Value equals number
of PCLK clock periods in Bits 17:4 and number of high resolution clock phases of
PCL in Bits 3:0 (dependent on Bits 3:2 of DPWM Control Register 2). DPWM
Event 3 Register (DPWMEV3)
Address 00150018 – Loop 4 DPWM Event 3 Register
Address 00170018 – Loop 3 DPWM Event 3 Register
Address 001A0018 – Loop 2 DPWM Event 3 Register
Address 001D0018 – Loop 1 DPWM Event 3 Register
Bit Number
Bit Name
Access
Default
17:0
EVENT3
R/W
00_0000_0011_1110_0000
Bits 17-0: EVENT3 – Configures the location of Event 3. Value equals number
of PCLK clock periods in Bits 17:4 and number of high resolution clock phases of
PCL in Bits 3:0.
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4.7.7 DPWM Event 4 Register (DPWMEV4)
Address 0015001C – Loop 4 DPWM Event 4 Register
Address 0017001C – Loop 3 DPWM Event 4 Register
Address 001A001C – Loop 2 DPWM Event 4 Register
Address 001D001C – Loop 1 DPWM Event 4 Register
Bit Number
Bit Name
Access
Default
17:0
EVENT4
R/W
00_0000_0111_0000_0000
Bits 17-0: EVENT4 – Configures the location of Event 4. Value equals number
of PCLK clock periods in Bits 17:4 and number of high resolution clock phases of
PCL in Bits 3:0.
4.7.8 DPWM Sample Trigger 1 Register (DPWMSAMPTRIG1)
Address 00150020 – DPWM 3 Sample Trigger 1 Register
Address 00170020 – DPWM 2 Sample Trigger 1 Register
Address 001A0020 – DPWM 1 Sample Trigger 1 Register
Address 001D0020 – DPWM 0 Sample Trigger 1 Register
Bit Number
Bit Name
Access
Default
17:6
SAMPLE_TRIGGER
R/W
0000_0000_0100
5:0
RESERVED
00_0000
Bits 17-6: SAMPLE_TRIGGER – Configures the location of the sample trigger
within a PWM period. Value equals the number of PCLK clock periods. Enables
start of conversion for EADC. Low resolution register, last 6 bits are read-only.
Bits 5-0: RESERVED – Unused bits
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4.7.9 DPWM Sample Trigger 2 Register (DPWMSAMPTRIG2)
Address 00150024 – DPWM 3 Sample Trigger 1 Register
Address 00170024 – DPWM 2 Sample Trigger 1 Register
Address 001A0024 – DPWM 1 Sample Trigger 1 Register
Address 001D0024 – DPWM 0 Sample Trigger 1 Register
Bit Number
Bit Name
Access
Default
17:6
SAMPLE_TRIGGER
R/W
0000_0000_0100
5:0
RESERVED
00_0000
Bits 17-6: SAMPLE_TRIGGER – Configures the location of the sample trigger
within a PWM period. Value equals the number of PCLK clock periods. Enables
start of conversion for EADC. Low resolution register, last 6 bits are read-only.
Bits 5-0: RESERVED – Unused bits
4.7.10 DPWM Phase Trigger Register (DPWMPHASETRIG)
Address 00150028 – DPWM 3 Phase Trigger Register
Address 00170028 – DPWM 2 Phase Trigger Register
Address 001A0028 – DPWM 1 Phase Trigger Register
Address 001D0028 – DPWM 0 Phase Trigger Register
Bit Number
Bit Name
Access
Default
17:4
PHASE_TRIGGER
R/W
00_0000_0000_0000
3:0
RESERVED
0000
Bits 17-4: PHASE_TRIGGER – Configures the phase trigger delay within
multi-output mode. Value equals the number of PCLK clock periods. Low
resolution register, last 4 bits are read-only
Bits 3-0: RESERVED – Unused bits
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4.7.11 DPWM Cycle Adjust A Register (DPWMCYCADJA)
Address 0015002C – DPWM 3 Cycle Adjust A Register
Address 0017002C – DPWM 2 Cycle Adjust A Register
Address 001A002C – DPWM 1 Cycle Adjust A Register
Address 001D002C – DPWM 0 Cycle Adjust A Register
Bit Number
Bit Name
Access
Default
15:0
CYCLE_ADJUST_A
R/W
0000_0000_0000_0000
Bits 15-0: CYCLE_ADJUST_A – Adjusts PWM A output signal. 16-bit signed
number allows output signal to be delayed or sped up.
4.7.12 DPWM Cycle Adjust B Register (DPWMCYCADJB)
Address 00150030 – DPWM 3 Cycle Adjust B Register
Address 00170030 – DPWM 2 Cycle Adjust B Register
Address 001A0030 – DPWM 1 Cycle Adjust B Register
Address 001D0030 – DPWM 0 Cycle Adjust B Register
Bit Number
Bit Name
Access
Default
15:0
CYCLE_ADJUST_B
R/W
0000_0000_0000_0000
Bits 15-0: CYCLE_ADJUST_B – Adjusts the PWM B output signal. 16-bit
signed number allows output signal to be delayed or sped up.
i. DPWM Filter Reference Register (DPWMRESDUTY)
Address 00050034 – DPWM 3 Filter Reference Register
Address 00070034 – DPWM 2 Filter Reference Register
Address 000A0034 – DPWM 1 Filter Reference Register
Address 000D0034 – DPWM 0 Filter Reference Register
Bit Number
13:0
RESONANT_DUTY
Bit Name
R/W
Access
00_0000_0000_0000
Default
Bits 13-0: RESONANT_DUTY – Sends resonant duty multiplier to a connected filter, if
applicable
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4.7.13
4.7.14 DPWM Fault Control Register (DPWMFLTCTRL)
Address 00150038 – DPWM 3 Fault Control Register
Address 00170038 – DPWM 2 Fault Control Register
Address 001A0038 – DPWM 1 Fault Control Register
Address 001D0038 – DPWM 0 Fault Control Register
Bit Number
Bit Name
Access
Default
31
ALL_FAULT_EN
R/W
0
Bit Number
Bit Name
Access
Default
30
CBC_FAULT_EN
R/W
0
Bit Number
Bit Name
Access
Default
15
FLT_RESTART
R/W
0
29:24
CBC_MAX_COUNT
R/W
00_0000
14:8
A_MAX_COUNT
R/W
000_0000
23
RESERVED
0
22:16
AB_MAX_COUNT
R/W
000_0000
7
CBC_FAULT_MODE
R/W
0
6:0
B_MAX_COUNT
R/W
000_0000
Bit 31: ALL_FAULT_EN – DPWM Fault Module enable
0 = All DPWM Fault Modules disabled (Default)
1 = All DPWM Fault Modules enabled
Bit 30: CBC_FAULT_EN – CBC Fault Module enable
0 = CBC Fault Modules disabled (Default)
1 = CBC Fault Modules enabled
Bits 29-24: CBC_MAX_COUNT – Cycle-by-Cycle Fault Count, sets the
number of received sequential faults on Cycle-by-Cycle Fault input before
asserting the fault
Bits 23: RESERVED – Unused bit
Bits 22-16: AB_MAX_COUNT – Fault AB Count, sets the number of received
sequential faults on Fault AB input before asserting the fault
Bits 15: FLT_RESTART – Enables DPWM after Fault.
1->0 = Enables DPWM on Falling Edge Transition of Bit.
Does nothing otherwise.
Bits 14-8: A_MAX_COUNT – Fault A Count, sets the number of received
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sequential faults on Fault A input before asserting the fault
Bits 7: CBC_FAULT_MODE – CBC Fault Mode
0 = CBC Fault reacts to fault cbc input from fault mux
1 = CBC Fault reacts to output of frame CBC
Bits 6-0: B_MAX_COUNT – Fault B Count, sets the number of received
sequential faults on Fault B input before asserting the fault
4.7.15 DPWM Overflow Register (DPWMOVERFLOW)
Address 0015003C – DPWM 3 Overflow Register
Address 0017003C – DPWM 2 Overflow Register
Address 001A003C – DPWM 1 Overflow Register
Address 001D003C – DPWM 0 Overflow Register
Bit Number
Bit Name
Access
Default
7
PWM_B_CHECK
R
-
6
PWM_A_CHECK
R
-
5
GPIO_B_IN
R
-
4
GPIO_A_IN
R
-
Bit 7: PWM_B_CHECK – Value of PWM B internal check
0 = Passed checks
1 = Failed checks (override required to enable output)
Bit 6: PWM_A_CHECK – Value of PWM B input
0 = Passed check
1 = Failed check (override required to enable output)
Bit 5: GPIO_B_IN0 – Value of PWM B input
0 = Low signal on PWM B
1 = High signal on PWM B
Bit 4: GPIO_A_IN – Value of PWM A input
0 = Low signal on PWM A
1 = High value on PWM A
Bit 3: OVERFLOW – PWM Event 4 Overflow Status
0 = CLA Event 4 has not overflowed
1 = Overflow condition found on CLA Event 4
Bit 2: OVERFLOW[2] – CLA Event 4 Overflow Status
0 = PWM Event 4 has not overflowed
1 = Overflow condition found on PWM Event 4
Bit 1: OVERFLOW[1] – CLA Event 3 Overflow Status
0 = CLA Event 3 has not overflowed
1 = Overflow condition found on CLA Event 3
Bit 0: OVERFLOW[0] – CLA Event 2 Overflow Status
0 = CLA Event 2 has not overflowed
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OVERFLOW
R
-
SLUA766
1 = Overflow condition found on CLA Event 2
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4.7.16 DPWM Flags/Interrupt Register (DPWMINT)
Address 00150040 – DPWM 3 Flags/Interrupt Register
Address 00170040 – DPWM 2 Flags/Interrupt Register
Address 001A0040 – DPWM 1 Flags/Interrupt Register
Address 001D0040 – DPWM 0 Flags/Interrupt Register
Bit Number
Bit Name
Access
Default
Bit Number
Bit Name
Access
Default
Bit Number
Bit Name
Access
Default
Bit Number
Bit Name
Access
Default
23
DTC_DISABLE
R
-
22
MODE_SWITCH
R
-
15:12
RESERVED
0000
20
FLT_B
R
-
11
MODE_SWITCH_FLAG_CLR
R/W
0
9
MODE_SWITCH_INT_EN
R/W
0
6
FLT_AB_INT_EN
R/W
0
21
FLT_A
R
-
8
FLT_A_INT_EN
R/W
0
5
FLT_CBC_INT_EN
R/W
0
4
PRD_INT_EN
R/W
0
Bit 23: DTC_DISABLE – DTC Disabled Flag
0 = Flag is not asserted
1 = Flag is set
Bit 22: MODE_SWITCH – Mode Switching Flag
0 = Flag is not asserted
1 = Flag is set
Bit 21: FLT_A – Fault A Flag
0 = Flag is not asserted
1 = Flag is set
Bit 20: FLT_B – Fault B Flag
0 = Flag is not asserted
1 = Flag is set
Bit 19: FLT_AB – Fault AB Flag
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FLT_AB
R
-
18
FLT_CBC
R
-
17
PRD
R
-
10
MODE_SWITCH_FLAG_EN
R/W
0
7
FLT_B_INT_EN
R/W
0
3:0
PRD_INT_SCALE
R/W
1111
16
INT
R
-
SLUA766
0 = Flag is not asserted
1 = Flag is set
Bit 18: FLT_CBC – Fault Cycle-by-Cycle Flag
0 = Flag is not asserted
1 = Flag is set
Bit 17: PRD – PWM Period Interrupt Flag
0 = PWM Period Interrupt Flag is not asserted
1 = PWM Period Interrupt Flag is set
Bit 16: INT– Interrupt Out
0 = INT is not asserted
1 = INT is set
Bits 15-12: RESERVED – Unused bits
Bit 11: MODE_SWITCH_FLAG_CLR– Mode Switching Flag Clear
0 = (Default)
1 = Risedge 0-1 clears flag generated.
Bit 10: MODE_SWITCH_FLAG_EN– Mode Switching Flag Enable
0 = Disables generation of flag for Mode Switching (Default)
1 = Enables generation of flag for Mode Switching.
Bit 9: MODE_SWITCH_INT_EN – Mode Switching Interrupt Enable
0 = Interrupt is not enabled (Default)
1 = Interrupt is enabled
Bit 8: FLT_A_INT_EN – Fault A Flag Interrupt Enable
0 = Interrupt is not enabled (Default)
1 = Interrupt is enabled
Bit 7: FLT_B_INT_EN – Fault B Flag Interrupt Enable
0 = Interrupt is not enabled (Default)
1 = Interrupt is enabled
Bit 6: FLT_AB_INT_EN – Fault AB Flag Interrupt Enable
0 = Interrupt is not enabled (Default)
1 = Interrupt is enabled
Bit 5: FLT_CBC_INT_EN – Fault Cycle-by-Cycle Flag Interrupt Enable
0 = Interrupt is not enabled (Default)
1 = Interrupt is enabled
Bit 4: PRD_INT_EN – PWM Period Interrupt Enable
0 = Disables generation of periodic PWM interrupt (Default)
1 = Enables generation of periodic PWM interrupt
Bits 3-0: PRD_INT_SCALE – This value scales the period interrupt signal from
an interrupt every switching cycle to 16 switching cycles
0000 = Period Interrupt generated every switching cycle (Default)
0001 = Period Interrupt generated once every 2 switching cycles
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0010 = Period Interrupt generated once every 4 switching cycles
0011 = Period Interrupt generated once every 6 switching cycles
0100 = Period Interrupt generated once every 8 switching cycles
0101 = Period Interrupt generated once every 16 switching cycles
0110 = Period Interrupt generated once every 32 switching cycles
0111 = Period Interrupt generated once every 48 switching cycles
1000 = Period Interrupt generated once every 64 switching cycles
1001 = Period Interrupt generated once every 80 switching cycles
1010 = Period Interrupt generated once every 96 switching cycles
1011 = Period Interrupt generated once every 128 switching cycles
1100 = Period Interrupt generated once every 160 switching cycles
1101 = Period Interrupt generated once every 192 switching cycles
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4.7.17 DPWM Counter Preset Register (DPWMCNTPRE)
Address 00150044 – DPWM 3 Counter Preset Register
Address 00170044 – DPWM 2 Counter Preset Register
Address 001A0044 – DPWM 1 Counter Preset Register
Address 001D0044 – DPWM 0 Counter Preset Register
Bit Number
Bit Name
Access
Default
17:4
PRESET
R/W
00_0000_0000_0000
3:0
RESERVED
0000
Bit 17-4: PRESET – Counter preset value, counter reset to this value upon
detection of sync when PRESET_EN bit in DPWMCTRL1 is enabled. Low
resolution register, last 4 bits are read-only
Bits 3-0: RESERVED – Unused bits
4.7.18 DPWM Blanking A Begin Register (DPWMBLKABEG)
Address 00150048 – DPWM 3 Blanking A Begin Register
Address 00170048 – DPWM 2 Blanking A Begin Register
Address 001A0048 – DPWM 1 Blanking A Begin Register
Address 001D0048 – DPWM 0 Blanking A Begin Register
Bit Number
Bit Name
Access
Default
17:4
3:0
BLANK_A_BEGIN
R/W
00_0000_0000_0000
RESERVED
0000
Bit 17-4: BLANK_A_BEGIN – Configures start of Comparator Blanking
Window for PWM A. Low resolution register, last 4 bits are read-only.
Bits 3-0: RESERVED – Unused bits
4.7.19 DPWM Blanking A End Register (DPWMBLKAEND)
Address 0015004C – DPWM 3 Blanking A End Register
Address 0017004C – DPWM 2 Blanking A End Register
Address 001A004C – DPWM 1 Blanking A End Register
Address 001D004C – DPWM 0 Blanking A End Register
Bit Number
Bit Name
Access
Default
17:4
3:0
BLANK_A_END
R/W
00_0000_0000_0000
RESERVED
0000
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Bit 17-4: BLANK_A_END – Configures end of Comparator Blanking Window
for PWM A. Low resolution register, last 4 bits are read-only.
Bits 3-0: RESERVED – Unused bits
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4.7.20 DPWM Blanking B Begin Register (DPWMBLKBBEG)
Address 00150050 – DPWM 3 Blanking B Begin Register
Address 00170050 – DPWM 2 Blanking B Begin Register
Address 001A0050 – DPWM 1 Blanking B Begin Register
Address 001D0050 – DPWM 0 Blanking B Begin Register
Bit Number
Bit Name
Access
Default
17:4
3:0
BLANK_B_BEGIN
R/W
00_0000_0000_0000
RESERVED
0000
Bit 17-4: BLANK_B_BEGIN – Configures start of Comparator Blanking
Window for PWM B. Low resolution register, last 4 bits are read-only.
Bits 3-0: RESERVED – Unused bits
4.7.21 DPWM Blanking B End Register (DPWMBLKBEND)
Address 00150054 – DPWM 3 Blanking B End Register
Address 00170054 – DPWM 2 Blanking B End Register
Address 001A0054 – DPWM 1 Blanking B End Register
Address 001D0054 – DPWM 0 Blanking B End Register
Bit Number
Bit Name
Access
Default
17:4
3:0
BLANK_B_END
R/W
00_0000_0000_0000
RESERVED
0000
Bit 17-4: BLANK_B_END – Configures end of Comparator Blanking Window
for PWM B. Low resolution register, last 4 bits are read-only.
Bits 3-0: RESERVED – Unused bits
4.7.22 DPWM Minimum Duty Cycle High Register (DPWMMINDUTYHI)
Address 00150058 – DPWM 3 Minimum Duty Cycle High Register
Address 00170058 – DPWM 2 Minimum Duty Cycle High Register
Address 001A0058 – DPWM 1 Minimum Duty Cycle High Register
Address 001D0058 – DPWM 0 Minimum Duty Cycle High Register
Bit Number
Bit Name
Access
Default
17:4
3: 0
MIN_DUTY_HIGH
R/W
00_0000_0000_0000
RESERVED
0000
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Bit 17-4: MIN_DUTY_HIGH– Configures upper threshold for minimum duty
cycle logic. Low resolution register, last 4 bits are read-only.
Bits 3-0: RESERVED – Unused bits
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4.7.23 DPWM Minimum Duty Cycle Low Register (DPWMMINDUTYLO)
Address 0015005C – DPWM 3 Minimum Duty Cycle Low Register
Address 0017005C – DPWM 2 Minimum Duty Cycle Low Register
Address 001A005C – DPWM 1 Minimum Duty Cycle Low Register
Address 001D005C – DPWM 0 Minimum Duty Cycle Low Register
Bit Number
Bit Name
Access
Default
17:4
3: 0
MIN_DUTY_LOW
R/W
00_0000_0000_0000
RESERVED
0000
Bit 17-4: MIN_DUTY_LOW– Configures lower threshold for minimum duty
cycle logic. Low resolution register, last 4 bits are read-only.
Bits 3-0: RESERVED – Unused bits
4.7.24 DPWM Adaptive Sample Register (DPWMADAPTIVE)
Address 00150060 – DPWM 3 Adaptive Sample Register
Address 00170060 – DPWM 2 Adaptive Sample Register
Address 001A0060 – DPWM 1 Adaptive Sample Register
Address 001D0060 – DPWM 0 Adaptive Sample Register
Bit Number
Bit Name
Access
Default
11:0
ADAPT_SAMP
R/W
0000_0000_0000
Bit 13-0: ADAPT_SAMP – Configures Adaptive Sample Adjust
4.7.25 DPWM Fault Status (DPWMFLTSTAT)
Address 00150064 – DPWM 3 Fault Input Status Register
Address 00170064 – DPWM 2 Fault Input Status Register
Address 001A0064 – DPWM 1 Fault Input Status Register
Address 001D0064 – DPWM 0 Fault Input Status Register
Bit Number
Bit Name
Access
Default
5
BURST
R
-
4
IDE_DETECT
R
-
3
FLT_A
R
-
2
FLT_B
R
-
1
FLT_AB
R
-
0
FLT_CBC
R
-
Bit 5: BURST – Burst Mode Detection Status
0 = Burst Mode Detection is not asserted
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1 = Burst Mode Detection is set
Bit 4: IDE_DETECT – IDE Detection Status (from Analog Comparators)
0 = IDE Detection is not asserted
1 = IDE Detection is set
Bit 3: FLT_A – Fault A Detection Status
0 = Fault A Detection is not asserted
1 = Fault A Detection is set
Bit 2: FLT_B – Fault B Detection Status
0 = Fault B Detection is not asserted
1 = Fault B Detection is set
Bit 1: FLT_AB – Fault AB Detection Status
0 = Fault AB Detection is not asserted
1 = Fault AB Detection is set
Bit 0: FLT_CBC – Current Limit Detection Status
0 = Current Limit Detection is not asserted
1 = Current Limit Detection is set
4.7.26 DPWM Auto Switch High Upper Thresh Register
(DPWMAUTOSWHIUPTHRESH)
Address 00150068 – DPWM 3 Auto Switch High Upper Thresh Register
Address 00170068 – DPWM 2 Auto Switch High Upper Thresh Register
Address 001A0068 – DPWM 1 Auto Switch High Upper Thresh Register
Address 001D0068 – DPWM 0 Auto Switch High Upper Thresh Register
Bit Number
Bit Name
Access
Default
17:4
3:0
AUTO_SWITCH_HIGH_UPPER
R/W
00_0000_0000_0000
RESERVED
0000
Bit 17-4: AUTO_SWITCH_HIGH_UPPER– Configures upper threshold for
Auto Switch Mode High operation. Mode switching does not occur between Auto
Switch High Upper and Auto Switch High Lower thresholds. Low resolution
register, last 4 bits are read-only.
Bits 3-0: RESERVED – Unused bits
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4.7.27 DPWM Auto Switch High Lower Thresh Register
(DPWMAUTOSWHILOWTHRESH)
Address 0015006C – DPWM 3 Auto Switch High Lower Thresh Register
Address 0017006C – DPWM 2 Auto Switch High Lower Thresh Register
Address 001A006C – DPWM 1 Auto Switch High Lower Thresh Register
Address 001D006C – DPWM 0 Auto Switch High Lower Thresh Register
Bit Number
Bit Name
Access
Default
17:4
3:0
AUTO_SWITCH_HIGH_LOWER
R/W
00_0000_0000_0000
RESERVED
0000
Bit 17-4: AUTO_SWITCH_HIGH_LOWER– Configures lower threshold for
Auto Switch Mode High operation. Mode switching does not occur between Auto
Switch High Upper and Auto Switch High Lower thresholds. Low resolution
register, last 4 bits are read-only.
Bits 3-0: RESERVED – Unused bits
4.7.28 DPWM Auto Switch Low Upper Thresh Register
(DPWMAUTOSWLOUPTHRESH)
Address 00150070 – DPWM 3 Auto Switch Low Upper Thresh Register
Address 00170070 – DPWM 2 Auto Switch Low Upper Thresh Register
Address 001A0070 – DPWM 1 Auto Switch Low Upper Thresh Register
Address 001D0070 – DPWM 0 Auto Switch Low Upper Thresh Register
Bit Number
Bit Name
Access
Default
17:4
3:0
AUTO_SWITCH_LOW_UPPER
R/W
00_0000_0000_0000
RESERVED
0000
Bit 29-16: AUTO_SWITCH_LOW_UPPER– Configures upper threshold for
Auto Switch Mode Low operation. Mode switching does not occur between Auto
Switch Low Upper and Auto Switch Low Lower thresholds. Low resolution
register, last 4 bits are read-only.
Bits 3-0: RESERVED – Unused bits
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4.7.29 DPWM Auto Switch Low Lower Thresh Register
(DPWMAUTOSWLOLOWTHRESH)
Address 00150074 – DPWM 3 Auto Switch Low Lower Thresh Register
Address 00170074 – DPWM 2 Auto Switch Low Lower Thresh Register
Address 001A0074 – DPWM 1 Auto Switch Low Lower Thresh Register
Address 001D0074 – DPWM 0 Auto Switch Low Lower Thresh Register
Bit Number
Bit Name
Access
Default
17:4
3:0
AUTO_SWITCH_LOW_LOWER
R/W
00_0000_0000_0000
RESERVED
0000
Bit 29-16: AUTO_SWITCH_LOW_LOWER– Configures lower threshold for
Auto Switch Mode Low operation. Mode switching does not occur between Auto
Switch Low Upper and Auto Switch Low Lower thresholds. Low resolution
register, last 4 bits are read-only.
Bits 3-0: RESERVED – Unused bits
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4.7.30 DPWM Auto Config Max Register (DPWMAUTOMAX)
Address 00150078 – DPWM 3 Auto Config Max Register
Address 00170078 – DPWM 2 Auto Config Max Register
Address 001A0078 – DPWM 1 Auto Config Max Register
Address 001D0078 – DPWM 0 Auto Config Max Register
Bit Number
Bit Name
Access
Default
31:28
PWM_B_INTRA_MUX
R/W
000
27:24
PWM_A_INTRA_MUX
R/W
000
23
CBC_PWM_C_EN
R/W
0
Bit Number
Bit Name
Access
Default
22:21
RESERVED
00
20
CBC_PWM_AB_EN
R/W
0
Bit Number
Bit Name
Access
Default
19
CBC_ADV_CNT_EN
R/W
0
18:13
RESERVED
00_0000
Bit Number
Bit Name
Access
Default
Bit Number
Bit Name
Access
Default
12
RESON_MODE_FIXED_DUTY_EN
R/W
0
11:7
RESERVED
00000
6:4
PWM_MODE
R/W
000
3:2
RESERVED
00
1
CLA_EN
R/W
0
0
RESERVED
0
Bits 31-28: PWM_B_INTRA_MUX – Interchanges signals post edge generation
0 = Pass-through (Default)
1 = Edge-gen output, this module
2 = PWM-C, this module
3 = Crossover, this module
4 = Pass-through below A
5 = Pass-through below B
6 = Pass-through below C
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7 = Pass-through below level-2 C
8 = Pass-through below level-3 C
Bits 27-24: PWM_A_INTRA_MUX – Combines signals prior to HR module
0 = Pass-through (Default)
1 = Edge-gen output, this module
2 = PWM-C, this module
3 = Crossover, this module
4 = Pass-through below A
5 = Pass-through below B
6 = Pass-through below C
7 = Pass-through below level-2 C
8 = Pass-through below level-3 C
Bit 23: CBC_PWM_C_EN – Sets if Fault CBC changes PWM-C output
0 = PWM-C unaffected by Fault CBC (Default)
1 = PWM-C affected by Fault CBC
Bit 22-21: RESERVED – Unused Bit
Bit 20: CBC_PWM_AB_EN – Sets if Fault CBC changes output waveform for
PWM-A and PWM-B
0 = PWM-A and PWM-B unaffected by Fault CBC (Default)
1 = PWM-A and PWM-B affected by Fault CBC
Bit 19: CBC_ADV_CNT_EN – Selects cycle-by-cycle of operation
Normal Mode
0 = CBC disabled (Default)
1 = CBC enabled
Multi and Resonant Modes
0 = PWM-A and PWM-B operate independently (Default)
1 = PWM-A and PWM-B pulse matching enabled
Bits 18-13: RESERVED – Unused Bits
Bit 12: RESON_MODE_FIXED_DUTY_EN – Configures how duty cycle is
controlled in Resonance Mode
0 = Resonant mode duty cycle set by Filter duty (Default)
1 = Resonant mode duty cycle set by Auto Switch High Register
Bits 11-7: RESERVED – Unused Bits
Bits 6-4: PWM_MODE – DPWM Mode
0 = Normal Mode
1 = Resonant Mode
2 = Multi-Output Mode
3 = Triangular Mode
4 = Leading Mode
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Bits 3-2: RESERVED – Unused Bits
Bit 1: CLA_EN– CLA Processing Enable
0 = Generate PWM waveforms from PWM Register values (Default)
1 = Enable CLA input
Bit 0: RESERVED – Unused bit
4.7.31 DPWM Auto Config Mid Register (DPWMAUTOMID)
Address 0015007C – DPWM 3 Auto Config Mid Register
Address 0017007C – DPWM 2 Auto Config Mid Register
Address 001A007C – DPWM 1 Auto Config Mid Register
Address 001D007C – DPWM 0 Auto Config Mid Register
Bit Number
Bit Name
Access
Default
31:28
PWM_B_INTRA_MUX
R/W
0000
27:24
PWM_A_INTRA_MUX
R/W
0000
23
CBC_PWM_C_EN
R/W
0
Bit Number
Bit Name
Access
Default
22:21
RESERVED
00
20
CBC_PWM_AB_EN
R/W
0
Bit Number
Bit Name
Access
Default
19
CBC_ADV_CNT_EN
R/W
0
18:13
RESERVED
00_0000
Bit Number
Bit Name
Access
Default
Bit Number
Bit Name
Access
12
RESON_MODE_FIXED_DUTY_EN
R/W
0
11:8
RESERVED
-
6:4
PWM_MODE
R/W
3:2
RESERVED
-
1
CLA_EN
R/W
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RESERVED
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Default
0000
0000
00
0
0
Bits 31-28: PWM_B_INTRA_MUX – Interchanges signals post edge generation
0 = Pass-through (Default)
1 = Edge-gen output, this module
2 = PWM-C, this module
3 = Crossover, this module
4 = Pass-through below A
5 = Pass-through below B
6 = Pass-through below C
7 = Pass-through below level-2 C
8 = Pass-through below level-3 C
Bits 27-24: PWM_A_INTRA_MUX – Combines signals prior to HR module
0 = Pass-through (Default)
1 = Edge-gen output, this module
2 = PWM-C, this module
3 = Crossover, this module
4 = Pass-through below A
5 = Pass-through below B
6 = Pass-through below C
7 = Pass-through below level-2 C
8 = Pass-through below level-3 C
Bit 23: CBC_PWM_C_EN – Sets if Fault CBC changes PWM-C output
0 = PWM-C unaffected by Fault CBC (Default)
1 = PWM-C affected by Fault CBC
Bit 22-21: RESERVED – Unused Bits
Bit 20: CBC_PWM_AB_EN – Sets if Fault CBC changes output waveform for
PWM-A and PWM-B
0 = PWM-A and PWM-B unaffected by Fault CBC (Default)
1 = PWM-A and PWM-B affected by Fault CBC
Bit 19: CBC_ADV_CNT_EN – Selects cycle-by-cycle of operation
Normal Mode
0 = CBC disabled (Default)
1 = CBC enabled
Multi and Resonant Modes
0 = PWM-A and PWM-B operate independently (Default)
1 = PWM-A and PWM-B pulse matching enabled
Bits 18-13: RESERVED – Unused Bits
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Bit 12: RESON_MODE_FIXED_DUTY_EN – Configures how duty cycle is
controlled in Resonance Mode
0 = Resonant mode duty cycle set by Filter duty (Default)
1 = Resonant mode duty cycle set by Auto Switch High Register
Bits 11-7: RESERVED – Unused Bits
Bits 6-4: PWM_MODE – DPWM Mode
0 = Normal Mode
1 = Resonant Mode
2 = Multi-Output Mode
3 = Triangular Mode
4 = Leading Mode
Bits 3-2: RESERVED – Unused Bits
Bit 1: CLA_EN– CLA Processing Enable
0 = Generate PWM waveforms from PWM Register values (Default)
1 = Enable CLA input
Bit 0: RESERVED – Unused bit
4.7.32 DPWM Edge PWM Generation Control Register (DPWMEDGEGEN)
Address 00150080 – DPWM 3 Edge PWM Generation Control Register
Address 00170080 – DPWM 2 Edge PWM Generation Control Register
Address 001A0080 – DPWM 1 Edge PWM Generation Control Register
Address 001D0080 – DPWM 0 Edge PWM Generation Control Register
Bit Number
Bit Name
Access
Default
16
EDGE_EN
R/W
0
Bit Number
Bit Name
Access
Default
10:8
A_OFF_EDGE
R/W
01
15
RESERVED
0
7
RESERVED
0
14:12
A_ON_EDGE
R/W
000
6:4
B_ON_EDGE
R/W
10
3
RESERVED
0
11
RESERVED
0
2:0
B_OFF_EDGE
R/W
11
Bit 16: EDGE_EN – Enables edge generate module. When combining dpwm’s,
all modules must have this bit enabled.
Bits 14-12: A_ON_EDGE – Select input edge to trigger A ON output edge
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0 = Current DPWM posedge A
1 = Current DPWM negedge A
2 = Current DPWM posedge B
3 = Current DPWM negedge B
4 = Below (n+1) DPWM posedge A
5 = Below (n+1) DPWM negedge A
6 = Below (n+1) DPWM posedge B
7 = Below (n+1) DPWM negedge B
Bit 15: RESERVED – Unused bit
Bits 10-8: A_OFF_EDGE – Select input edge to trigger A OFF output edge
0 = Current DPWM posedge A
1 = Current DPWM negedge A
2 = Current DPWM posedge B
3 = Current DPWM negedge B
4 = Below (n+1) DPWM posedge A
5 = Below (n+1) DPWM negedge A
6 = Below (n+1) DPWM posedge B
7 = Below (n+1) DPWM negedge B
Bit 7: RESERVED – Unused bit
Bits 6-4: B_ON_EDGE – Select input edge to trigger B ON output edge
0 = Current DPWM posedge A
1 = Current DPWM negedge A
2 = Current DPWM posedge B
3 = Current DPWM negedge B
4 = Below (n+1) DPWM posedge A
5 = Below (n+1) DPWM negedge A
6 = Below (n+1) DPWM posedge B
7 = Below (n+1) DPWM negedge B
Bit 3: RESERVED – Unused bit
Bit 2-0: B_OFF_EDGE – Select input edge to trigger B OFF output edge
0 = Current DPWM posedge A
1 = Current DPWM negedge A
2 = Current DPWM posedge B
3 = Current DPWM negedge B
4 = Below (n+1) DPWM posedge A
5 = Below (n+1) DPWM negedge A
6 = Below (n+1) DPWM posedge B
7 = Below (n+1) DPWM negedge B
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4.7.33 DPWM Filter Duty Read Register (DPWMFILTERDUTYREAD)
Address 00150084 – DPWM 3 Filter Duty Read Register
Address 00170084 – DPWM 2 Filter Duty Read Register
Address 001A0084 – DPWM 1 Filter Duty Read Register
Address 001D0084 – DPWM 0 Filter Duty Read Register
Bit Number
Bit Name
Access
Default
17:0
FILTER_DUTY
R
-
Bits 17-0: FILTER_DUTY – Filter Duty value received by DPWM Module
4.7.34 DPWM CBC Location Register (DPWMCBCLOCATION)
Address 00150088 – DPWM 3 CBC Location Register
Address 00170088 – DPWM 2 CBC Location Register
Address 001A0088 – DPWM 1 CBC Location Register
Address 001D0088 – DPWM 0 CBC Location Register
Bit Number
Bit Name
Access
Default
13:0
CBC_LOCATION
R
-
Bits 13-0: CBC_LOCATION – Counter Value when CBC occurs
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4.7.35
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4.8 Filter Registers
Registers for Filter Modules 0-2 are identical in their bit definitions.
4.8.1 Filter Status Register (FILTERSTATUS)
Address 00160000 – Filter 2 Status Register
Address 00190000 – Filter 1 Status Register
Address 001C0000 – Filter 0 Status Register
Bit Number
Bit Name
Access
Default
4
FILTER_BUSY
R
-
3
YN_LOW_CLAMP
R
-
Bit Number
Bit Name
Access
Default
1
KI_YN_LOW_CLAMP
R
-
0
KI_YN_HIGH_CLAMP
R
-
2
YN_HIGH_CLAMP
R
-
Bit 4: FILTER_BUSY – Filter Busy Indicator
0 = Filter is waiting for new data
1 = Filter busy calculating
Bit 3: YN_LOW_CLAMP – PID Output Low Rail Indicator
0 = PID Output not equal to low rail
1 = PID Output equal to low rail
Bit 2: YN_HIGH_CLAMP – PID Output High Rail Indicator
0 = PID Output not equal to high rail
1 = PID Output equal to high rail
Bit 1: KI_YN_LOW_CLAMP – KI Feedback Low Rail Indicator
0 = KI Feedback not equal to low rail
1 = KI Feedback equal to low rail
Bit 0: KI_YN_HIGH_CLAMP – KI Feedback High Rail Indicator
0 = KI Feedback not equal to high rail
1 = KI Feedback equal to high rail
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4.8.2 Filter Control Register (FILTERCTRL)
Address 00160004 – Filter 2 Control Register
Address 00190004 – Filter 1 Control Register
Address 001C0004 – Filter 0 Control Register
Bit Number
Bit Name
Access
Default
Bit Number
Bit Name
Access
Default
Bit Number
Bit Name
Access
Default
15
KI_ADDER_MODE
R/W
1
11:9
YN_SCALE
R/W
000
4
KD_OFF
R/W
0
14
PERIOD_MULT_SEL
R/W
0
8
NL_MODE
R/W
0
3
KI_OFF
R/W
0
7
KD_STALL
R/W
0
2
FORCE_START
R/W
0
13:12
OUTPUT_MULT_SEL
R/W
00
6
KI_STALL
R/W
0
1
USE_CPU_SAMPLE
R/W
0
5
KP_OFF
R/W
0
0
FILTER_EN
R/W
1
Bit 15: KI_ADDER_MODE – Configures addition of Xn and Xn-1 in Integral
branch
0 = Only Xn used for addition (Xn + 0)
1 = Xn + Xn-1 used for addition (Default)
Bit 14: PERIOD_MULT_SEL – Selects output multiplicand used for
multiplying with filter output to calculate DPWM Period value in Resonant Mode
0 = Switching period received from Loop Mux module (Default)
1 = KComp received from Loop Mux module
Bits 13-12: OUTPUT_MULT_SEL – Selects output multiplicand used for
multiplying with filter output to calculate DPWM Duty value
0 = KComp received from Loop Mux module (Default)
1 = Switching period received from Loop Mux module
2 = Feed-Forward value received from Loop Mux module
3 = Resonant Duty value received from DPWM Module
Bit 11-9: YN_SCALE – Controls scaling of Yn value to compensate for filter
coefficient scaling
0 = Filter output (Yn) not scaled (Default)
1 = Filter output (Yn) right shifted by 1
2 = Filter output (Yn) right shifted by 2
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3 = Filter output (Yn) right shifted by 3
4 = Filter output (Yn) left shifted by 4
5 = Filter output (Yn) left shifted by 3
6 = Filter output (Yn) left shifted by 2
7 = Filter output (Yn) left shifted by 1
Bit 8: NL_MODE – Sets non-linear gain table configuration. Coefficient Bin
mapping is controlled by Coefficient Configuration Register. Limit configuration
is controlled by the Filter Nonlinear Limit Registers (See Sections 4.8.16 to
4.8.18)
0 = Non-symmetric mode (Default)
1 = Symmetric mode
Bit 7: KD_STALL – Freezes KD Branch, KD_YN remains at current value
0 = KD_YN recalculated on each filter update (Default)
1 = KD_YN stalled at present value
Bit 6: KI_STALL – Freezes KI Branch, KI_YN remains at current value
0 = KI_YN recalculated on each filter update (Default)
1 = KI_YN stalled at present value
Bit 5: KP_OFF – Turns off the KP branch
0 = KP branch calculating new outputs (Default)
1 = KP branch turned off
Bit 4: KD_OFF – Turns off the KD branch, KD_YN cleared to zero
0 = KD branch calculating new outputs (Default)
1 = KD branch turned off
Bit 3: KI_OFF – Turns off the KI branch, KI_YN cleared to zero
0 = KI branch calculating new outputs (Default)
1 = KI branch halted
Bit 2: FORCE_START – Initiates a filter calculation under firmware control
0 = No calculation started (Default)
1 = Calculation started
Bit 1: USE_CPU_SAMPLE – Forces filter to use error sample from CPU XN
register (Section 4.8.3)
0 = Filter Mode, input data received from EADC (Default)
1 = CPU Mode, input data based on CPU XN register
Bit 0: FILTER_EN – Filter Enable
0 = Disables Filter operation
1 = Enables Filter operation (Default)
4.8.3 CPU XN Register (CPUXN)
Address 00160008 – Filter 2 CPU XN Register
Address 00190008 – Filter 1 CPU XN Register
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Address 001C0008 – Filter 0 CPU XN Register
Bit Number
Bit Name
Access
Default
8:0
CPU_SAMPLE
R/W
0_0000_0000
Bits 8-0: CPU_SAMPLE – Forced Xn value, allows processor to use filter as
ALU. Set Bit 2 of Filter Control Register to ‘1’ to force CPU_SAMPLE as input
to Filter.
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4.8.4 Filter XN Read Register (FILTERXNREAD)
Address 0016000C – Filter 2 XN Read Register
Address 0019000C – Filter 1 XN Read Register
Address 001C000C – Filter 0 XN Read Register
Bit Number
Bit Name
Access
Default
24:16
XN_M1
R
-
15:9
RESERVED
000_0000
8:0
XN
R
-
Bits 24-16: XN_M1 – 9-bit signed XN_M1 register value, read-only
Bits 15-9: RESERVED
Bits 8-0: XN – 9-bit signed XN register value, read-only
4.8.5 Filter KI_YN Read Register (FILTERKIYNREAD)
Address 00160010 – Filter 2 KI_YN Read Register
Address 00190010 – Filter 1 KI_YN Read Register
Address 001C0010 – Filter 0 KI_YN Read Register
Bit Number
Bit Name
Access
Default
23:0
KI_YN
R
-
Bits 23-0: KI_YN – 24-bit signed KI_YN register value, read-only
4.8.6 Filter KD_YN Read Register (FILTERKDYNREAD)
Address 00160014 – Filter 2 KD_YN Register
Address 00190014 – Filter 1 KD_YN Register
Address 001C0014 – Filter 0 KD_YN Register
Bit Number
Bit Name
Access
Default
23:0
KD_YN
R
-
Bits 23-0: KD_YN – 24-bit signed KD_YN register value, read-only
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4.8.7 Filter YN Read Register (FILTERYNREAD)
Address 00160018 – Filter 2 YN Read Register
Address 00190018 – Filter 1 YN Read Register
Address 001C0018 – Filter 0 YN Read Register
Bit Number
Bit Name
Access
Default
23:0
YN
R
-
Bits 23-0: YN – 24-bit signed YN register value, read-only
4.8.8 Coefficient Configuration Register (COEFCONFIG)
Address 0016001C – Filter 2 Coefficient Configuration Register
Address 0019001C – Filter 1 Coefficient Configuration Register
Address 001C001C – Filter 0 Coefficient Configuration Register
Bit Number
Bit Name
Access
Default
27
BIN6_ALPHA
R/W
0
Bit Number
Bit Name
Access
Default
19
BIN4_ALPHA
R/W
0
Bit Number
Bit Name
Access
Default
10:8
BIN2_CONFIG
R/W
000
26:24
BIN6_CONFIG
R/W
000
18:16
BIN4_CONFIG
R/W
000
7
BIN1_ALPHA
R/W
0
23
BIN5_ALPHA
R/W
0
15
BIN3_ALPHA
R/W
0
6:4
BIN1_CONFIG
R/W
000
22:20
BIN5_CONFIG
R/W
000
14:12
BIN3_CONFIG
R/W
000
3
BIN0_ALPHA
R/W
0
11
BIN2_ALPHA
R/W
0
2:0
BIN0_CONFIG
R/W
000
Bit 27: BIN6_ALPHA – Selects which alpha value to use in Bin 6 of Non-Linear
Table. These bits are shadowed and updated to filter when filter is not processing
an EADC sample
0 = Bank 0 KD Alpha (KD_ALPHA_0) selected (Default)
1 = Bank 1 KD Alpha (KD_ALPHA_1) selected
Bits 26-24: BIN6_CONFIG – Selects which coefficient set to place in Bin 6 of
Non-Linear Table. These bits are shadowed and updated to filter when filter is not
processing an EADC sample.
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0 = Coefficient Set A Selected (Default)
1 = Coefficient Set B Selected
2 = Coefficient Set C Selected
3 = Coefficient Set D Selected
4 = Coefficient Set E Selected
5 = Coefficient Set F Selected
6 = Coefficient Set G Selected
Bit 23: BIN5_ALPHA – Selects which alpha value to use in Bin 5 of Non-Linear
Table. These bits are shadowed and updated to filter when filter is not processing
an EADC sample
0 = Bank 0 KD Alpha (KD_ALPHA_0) selected (Default)
1 = Bank 1 KD Alpha (KD_ALPHA_1) selected
Bits 22-20: BIN5_CONFIG – Selects which coefficient set to place in Bin 5 of
Non-Linear Table. These bits are shadowed and updated to filter when filter is not
processing an EADC sample.
0 = Coefficient Set A Selected (Default)
1 = Coefficient Set B Selected
2 = Coefficient Set C Selected
3 = Coefficient Set D Selected
4 = Coefficient Set E Selected
5 = Coefficient Set F Selected
6 = Coefficient Set G Selected
Bit 19: BIN4_ALPHA – Selects which alpha value to use in Bin 4 of Non-Linear
Table. These bits are shadowed and updated to filter when filter is not processing
an EADC sample
0 = Bank 0 KD Alpha (KD_ALPHA_0) selected (Default)
1 = Bank 1 KD Alpha (KD_ALPHA_1) selected
Bits 18-16: BIN4_CONFIG – Selects which coefficient set to place in Bin 4 of
Non-Linear Table. These bits are shadowed and updated to filter when filter is not
processing an EADC sample.
0 = Coefficient Set A Selected (Default)
1 = Coefficient Set B Selected
2 = Coefficient Set C Selected
3 = Coefficient Set D Selected
4 = Coefficient Set E Selected
5 = Coefficient Set F Selected
6 = Coefficient Set G Selected
Bit 15: BIN3_ALPHA – Selects which alpha value to use in Bin 3 of Non-Linear
Table. These bits are shadowed and updated to filter when filter is not processing
an EADC sample
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0 = Bank 0 KD Alpha (KD_ALPHA_0) selected (Default)
1 = Bank 1 KD Alpha (KD_ALPHA_1) selected
Bits 14-12: BIN3_CONFIG – Selects which coefficient set to place in Bin 3 of
Non-Linear Table. These bits are shadowed and updated to filter when filter is not
processing an EADC sample.
0 = Coefficient Set A Selected (Default)
1 = Coefficient Set B Selected
2 = Coefficient Set C Selected
3 = Coefficient Set D Selected
4 = Coefficient Set E Selected
5 = Coefficient Set F Selected
6 = Coefficient Set G Selected
Bit 11: BIN2_ALPHA – Selects which alpha value to use in Bin 2 of Non-Linear
Table. These bits are shadowed and updated to filter when filter is not processing
an EADC sample
0 = Bank 0 KD Alpha (KD_ALPHA_0) selected (Default)
1 = Bank 1 KD Alpha (KD_ALPHA_1) selected
Bits 10-8: BIN2_CONFIG – Selects which coefficient set to place in Bin 2 of
Non-Linear Table. These bits are shadowed and updated to filter when filter is not
processing an EADC sample.
0 = Coefficient Set A Selected (Default)
1 = Coefficient Set B Selected
2 = Coefficient Set C Selected
3 = Coefficient Set D Selected
4 = Coefficient Set E Selected
5 = Coefficient Set F Selected
6 = Coefficient Set G Selected
Bit 7: BIN1_ALPHA – Selects which alpha value to use in Bin 1 of Non-Linear
Table. These bits are shadowed and updated to filter when filter is not processing
an EADC sample
0 = Bank 0 KD Alpha (KD_ALPHA_0) selected (Default)
1 = Bank 1 KD Alpha (KD_ALPHA_1) selected
Bits 6-4: BIN1_CONFIG – Selects which coefficient set to place in Bin 1 of
Non-Linear Table. These bits are shadowed and updated to filter when filter is not
processing an EADC sample.
0 = Coefficient Set A Selected (Default)
1 = Coefficient Set B Selected
2 = Coefficient Set C Selected
3 = Coefficient Set D Selected
4 = Coefficient Set E Selected
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5 = Coefficient Set F Selected
6 = Coefficient Set G Selected
Bit 3: BIN0_ALPHA – Selects which alpha value to use in Bin 0 of Non-Linear
Table. These bits are shadowed and updated to filter when filter is not processing
an EADC sample
0 = Bank 0 KD Alpha (KD_ALPHA_0) selected (Default)
1 = Bank 1 KD Alpha (KD_ALPHA_1) selected
Bits 2-0: BIN1_CONFIG – Selects which coefficient set to place in Bin 1 of
Non-Linear Table. These bits are shadowed and updated to filter when filter is not
processing an EADC sample.
0 = Coefficient Set A Selected (Default)
1 = Coefficient Set B Selected
2 = Coefficient Set C Selected
3 = Coefficient Set D Selected
4 = Coefficient Set E Selected
5 = Coefficient Set F Selected
6 = Coefficient Set G Selected
4.8.9 Filter KP Coefficient 0 Register (FILTERKPCOEF0)
Address 00160020 – Filter 2 KP Coefficient 0 Register
Address 00190020 – Filter 1 KP Coefficient 0 Register
Address 001C0020 – Filter 0 KP Coefficient 0 Register
Bit Number
Bit Name
Access
Default
31:16
15:0
KP_COEF_1
R/W
0000_0000_0000_0000
KP_COEF_0
R/W
0100_0010_0011_0100
Bits 31-16: KP_COEF_1 – KP Coefficient 1, 16-bit signed coefficient,
configurable to any bin using the Coefficient Control Register
Bits 15-0: KP_COEF_0 – KP Coefficient 0, 16-bit signed coefficient,
configurable to any bin using the Coefficient Control Register
4.8.10 Filter KP Coefficient 1 Register (FILTERKPCOEF1)
Address 00160024 – Filter 2 KP Coefficient 1 Register
Address 00190024 – Filter 1 KP Coefficient 1 Register
Address 001C0024 – Filter 0 KP Coefficient 1 Register
Bit Number
Bit Name
Access
15:0
KP_COEF_2
R/W
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Default
0000_0000_0000_0000
Bits 15-0: KP_COEF_2 – KP Coefficient 2, 16-bit signed coefficient,
configurable to any bin using the Coefficient Control Register
4.8.11 Filter KI Coefficient 0 Register (FILTERKICOEF0)
Address 00160028 – Filter 2 KI Coefficient 0 Register
Address 00190028 – Filter 1 KI Coefficient 0 Register
Address 001C0028 – Filter 0 KI Coefficient 0 Register
Bit Number
Bit Name
Access
Default
31:16
15:0
KI_COEF_1
R/W
0000_0000_0000_0000
KI_COEF_0
R/W
0010_0100_0001_0010
Bits 31-16: KI_COEF_1 – KI Coefficient 1, 16-bit signed coefficient,
configurable to any bin using the Coefficient Control Register
Bits 15-0: KI_COEF_0 – KI Coefficient 0, 16-bit signed coefficient,
configurable to any bin using the Coefficient Control Register
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4.8.12 Filter KI Coefficient 1 Register (FILTERKICOEF1)
Address 0016002C – Filter 2 KI Coefficient 1 Register
Address 0019002C – Filter 1 KI Coefficient 1 Register
Address 001C002C – Filter 0 KI Coefficient 1 Register
Bit Number
Bit Name
Access
Default
31:16
15:0
KI_COEF_3
R/W
0000_0000_0000_0000
KI_COEF_2
R/W
0000_0000_0000_0000
Bits 31-16: KI_COEF_3 – KI Coefficient 3, 16-bit signed coefficient,
configurable to any bin using the Coefficient Control Register
Bits 15-0: KI_COEF_2 – KI Coefficient 2, 16-bit signed coefficient,
configurable to any bin using the Coefficient Control Register
4.8.13 Filter KD Coefficient 0 Register (FILTERKDCOEF0)
Address 00160030 – Filter 2 KD Coefficient 0 Register
Address 00190030 – Filter 1 KD Coefficient 0 Register
Address 001C0030 – Filter 0 KD Coefficient 0 Register
Bit Number
Bit Name
Access
Default
31:16
15:0
KD_COEF_1
R/W
0000_0000_0000_0000
KD_COEF_0
R/W
1100_0100_0000_0001
Bits 31-16: KD_COEF_1 – KD Coefficient 1, 16-bit signed coefficient,
configurable to any bin using the Coefficient Control Register
Bits 15-0: KD_COEF_0 – KD Coefficient 0, 16-bit signed coefficient,
configurable to any bin using the Coefficient Control Register
4.8.14 Filter KD Coefficient 1 Register (FILTERKDCOEF1)
Address 00160034 – Filter 2 KD Coefficient 1 Register
Address 00190034 – Filter 1 KD Coefficient 1 Register
Address 001C0034 – Filter 0 KD Coefficient 1 Register
Bit Number
Bit Name
Access
Default
15:0
KD_COEF_2
R/W
0000_0000_0000_0000
Bits 15-0: KD_COEF_2 – KD Coefficient 2, 16-bit signed coefficient,
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configurable to any bin using the Coefficient Control Register
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4.8.15 Filter KD Alpha Register (FILTERKDALPHA)
Address 00160038 – Filter 2 KD Alpha Register
Address 00190038 – Filter 1 KD Alpha Register
Address 001C0038 – Filter 0 KD Alpha Register
Bit Number
Bit Name
Access
Default
24:16
15:9
8:0
KD_ALPHA_1
R/W
0_0000_0000
RESERVED
000_0000
KD_ALPHA_0
R/W
0_0101_0010
Bits 24-16: KD_ALPHA_1 – Bank 1 KD Alpha, 9-bit signed value, configurable
to any bin using the Coefficient Control Register
Bits 15-9: RESERVED
Bits 8-0: KD_ALPHA_0 – Bank 0 KD Alpha, 9-bit signed value, configurable to
any bin using the Coefficient Control Register
4.8.16 Filter Nonlinear Limit Register 0 (FILTERNL0)
Address 0016003C – Filter 2 Nonlinear Limit Register 0
Address 0019003C – Filter 1 Nonlinear Limit Register 0
Address 001C003C – Filter 0 Nonlinear Limit Register 0
Bit Number
Bit Name
Access
Default
24:16
15:9
8:0
LIMIT1
R/W
0_0000_0000
RESERVED
000_0000
LIMIT0
R/W
0_1111_1111
Bits 24-16: LIMIT1 – Configures LIMIT1 in Nonlinear Coefficient tables
Bits 15-9: RESERVED
Bits 8-0: LIMIT0 – Configures LIMIT0 in Nonlinear Coefficient tables
4.8.17 Filter Nonlinear Limit Register 1 (FILTERNL1)
Address 00160040 – Filter 2 Nonlinear Limit Register 1
Address 00190040 – Filter 1 Nonlinear Limit Register 1
Address 001C0040 – Filter 0 Nonlinear Limit Register 1
Bit Number
Bit Name
Access
Default
24:16
15:9
8:0
LIMIT3
R/W
0_0000_0000
RESERVED
000_0000
LIMIT2
R/W
0_0000_0000
Bits 24-16: LIMIT3 – Configures LIMIT3 in Nonlinear Coefficient tables
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Bits 15-9: RESERVED
Bits 8-0: LIMIT2 – Configures LIMIT2 in Nonlinear Coefficient tables
4.8.18 Filter Nonlinear Limit Register 2 (FILTERNL2)
Address 00160044 – Filter 2 Nonlinear Limit Register 2
Address 00190044 – Filter 1 Nonlinear Limit Register 2
Address 001C0044 – Filter 0 Nonlinear Limit Register 2
Bit Number
Bit Name
Access
Default
24:16
15:9
8:0
LIMIT5
R/W
0_0000_0000
RESERVED
000_0000
LIMIT4
R/W
0_0000_0000
Bits 24-16: LIMIT5 – Configures LIMIT5 in Nonlinear Coefficient tables
Bits 15-9: RESERVED
Bits 8-0: LIMIT4 – Configures LIMIT4 in Nonlinear Coefficient tables
4.8.19 Filter KI Feedback Clamp High Register (FILTERKICLPHI)
Address 00160048 – Filter 2 KI Feedback Clamp High Register
Address 00190048 – Filter 1 KI Feedback Clamp High Register
Address 001C0048 – Filter 0 KI Feedback Clamp High Register
Bit Number
Bit Name
Access
Default
23:0
KI_CLAMP_HIGH
R/W
0111_1111_1111_1111_1111_1111
Bits 23-0: KI_CLAMP_HIGH – Sets the upper limit of KI_YN value. If
calculated KI_YN exceeds this threshold, the KI_YN register will be set to
KI_CLAMP_HIGH
4.8.20 Filter KI Feedback Clamp Low Register (FILTERKICLPLO)
Address 0016004C– Filter 2 KI Feedback Clamp Low Register
Address 0019004C– Filter 1 KI Feedback Clamp Low Register
Address 001C004C – Filter 0 KI Feedback Clamp Low Register
Bit Number
Bit Name
Access
214
23:0
KI_CLAMP_LOW
R/W
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Default
0000_0000_0000_0000_0000_0000
Bits 23-0: KI_CLAMP_LOW – Sets the lower limit of KI_YN value. If
calculated KI_YN falls below this threshold, the KI_YN register will be set to
KI_CLAMP_LOW
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4.8.21 Filter YN Clamp High Register (FILTERYNCLPHI)
Address 00160050 – Filter 2 YN Clamp High Register
Address 00190050 – Filter 1 YN Clamp High Register
Address 001C0050 – Filter 0 YN Clamp High Register
Bit Number
Bit Name
Access
Default
23:0
YN_CLAMP_HIGH
R/W
0111_1111_1111_1111_1111_1111
Bits 23-0: YN_CLAMP_HIGH – Sets the upper limit of YN value. If calculated
YN exceeds this threshold, the YN register will be set to YN_CLAMP_HIGH
4.8.22 Filter YN Clamp Low Register (FILTERYNCLPLO)
Address 00160054 – Filter 2 YN Clamp Low Register
Address 00190054 – Filter 1 YN Clamp Low Register
Address 001C0054 – Filter 0 YN Clamp Low Register
Bit Number
Bit Name
Access
Default
23:0
YN_CLAMP_LOW
R/W
0000_0000_0000_0000_0000_0000
Bits 23-0: YN_CLAMP_LOW – Sets the lower limit of YN value. If calculated
YN falls below this threshold, the YN register will be set to YN_CLAMP_LOW
4.8.23 Filter Output Clamp High Register (FILTEROCLPHI)
Address 00160058 – Filter 2 Output Clamp High Register
Address 00190058 – Filter 1 Output Clamp High Register
Address 001C0058 – Filter 0 Output Clamp High Register
Bit Number
Bit Name
Access
Default
17:0
OUTPUT_CLAMP_HIGH
R/W
11_1111_1111_1111_1111
Bits 17-0: OUTPUT_CLAMP_HIGH – Sets the upper limit of filter output
value. If calculated filter output exceeds this threshold, the filter output will be set
to OUTPUT_CLAMP_HIGH
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4.8.24 Filter Output Clamp Low Register (FILTEROCLPLO)
Address 0016005C – Filter 2 Output Clamp Low Register
Address 0019005C – Filter 1 Output Clamp Low Register
Address 001C005C – Filter 0 Output Clamp Low Register
Bit Number
Bit Name
Access
Default
17:0
OUTPUT_CLAMP_LOW
R/W
00_0000_0000_0000_0000
Bits 17-0: OUTPUT_CLAMP_LOW – Sets the lower limit of filter output
value. If calculated filter output falls below this threshold, the filter output will be
set to OUTPUT_CLAMP_LOW
4.8.25 Filter Preset Register (FILTERPRESET)
Address 00160060 – Filter 2 Filter Preset Register
Address 00190060 – Filter 1 Filter Preset Register
Address 001C0060 – Filter 0 Filter Preset Register
Bit Number
Bit Name
Access
Default
27
PRESET_EN
R/W
00
26:24
PRESET_REG_SEL
R/W
000
23:0
PRESET_VALUE
R/W
0000_0000_0000_0000_0000_0000
Bit 27: PRESET_EN – Set to ‘1’ to initiate write of internal filter register (Self
cleared by hardware after successful programming)
Bits 26-24: PRESET_REG_SEL – Selects internal filter register to preset by
processor
0 = XN_M1 Register (only bits 10:0 of PRESET_VALUE will be
programmed into register)
1 = KI_YN Register
2 = KD_YN Register
3 = YN Register
4 = 18-bit Filter Data Register (after multiplication)
Bits 23-0: PRESET_VALUE – Value to preset into selected register
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4.9
Front End Control Registers
Registers for Front End Control modules 0-2 are identical in their bit definitions
4.9.1
Ramp Control Register (RAMPCTRL)
Address 0x0018_0000 – Front End Control 2 Ramp Control Register
Address 0x001B_0000 – Front End Control 1 Ramp Control Register
Address 0x001E_0000 – Front End Control 0 Ramp Control Register
Bit Number
Bit Name
Access
Default
29:16
SYNC_FET_RAMP_START
R/W
00_0000_0000_0000
15:13
RESERVED
00
12
RAMP_SAT_EN
R/W
0
Bit Number
Bit Name
Access
Default
11
RAMP_COMP_INT_EN
R/W
0
10
RAMP_DLY_INT_EN
R/W
0
9
PREBIAS_INT_EN
R/W
0
Bit Number
Bit Name
Access
Default
8
PCM_START_SEL
R/W
0
7
SYNC_FET_EN
R/W
0
Bit Number
Bit Name
Access
Default
3
SLAVE_DELAY_EN
R/W
0
2
CONTROL_EN
R/W
0
6:5
MASTER_SEL
R/W
00
1
FIRMWARE_START
R/W
0
4
SLAVE_COMP_EN
R/W
0
0
RAMP_EN
R/W
0
Bits 29-16: SYNC_FET_RAMP_START – Provides the starting value for the
SyncFET Ramp with a resolution of High Frequency Oscillator Period/bit
Bits 15-13: RESERVED – Unused Bits
Bit 12: RAMP_SAT_EN – Enables addition or subtraction of DAC Saturation
Step when EADC is in saturation.
0 = DAC Saturation Step logic is disabled, DAC
incremented/decremented by value calculated by Ramp logic when EADC
is in saturation (Default)
1 = DAC Saturation Step logic is enabled, DAC incremented/decremented
by value stored in DAC Saturation Step register when EADC is in
saturation
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Bit 11: RAMP_COMP_INT_EN – Enables Ramp I/F Interrupt when softstart/power-down ramp procedure is complete
0 = Soft-start/Power-Down Ramp Complete Interrupt is disabled (Default)
1 = Soft-start/Power-Down Ramp Complete Interrupt is enabled
Bit 10: RAMP_DLY_INT_EN – Enables Ramp I/F Interrupt when ramp delay
procedure is complete
0 = Soft-start/Power-Down Ramp Delay Complete Interrupt is disabled
(Default)
1 = Soft-start/Power-Down Ramp Delay Complete Interrupt is enabled
Bit 9: PREBIAS_INT_EN – Enables Ramp I/F Interrupt when Pre-Bias
procedure is completed
0 = Pre-bias Complete Interrupt is disabled (Default)
1 = Pre-bias Complete Interrupt is enabled
Bit 8: PCM_START_SEL – Peak Current Mode Ramp Start Value Select
0 = Ramp starts from value programmed in DAC_VALUE bits in
EADC_DAC_VALUE Register (Default)
1 = Ramp starts from filter output selected by PCM_SEL bits in Front End
Control Mux Register
Bit 7: SYNC_FET_EN – Enables SyncFET Ramp Operation
0 = SyncFET Ramp Operation disabled (Default)
1 = SyncFET Ramp Operation enabled
Bits 6-5: MASTER_SEL – Selects Master Ramp I/F in slave mode
0 = Front End Control 0 acts as master (Default)
1 = Front End Control 1 acts as master
2 = Front End Control 2 acts as master
Bit 4: SLAVE_COMP_EN – Enables syncing of ramp start to Master Ramp I/F
Complete pulse
0 = Ramp initiated by Master Ramp Complete pulse disabled (Default)
1 = Ramp initiated by Master Ramp Complete pulse enabled
Bit 3: SLAVE_DELAY_EN – Enables syncing of ramp start to Master Ramp I/F
Delay Complete pulse
0 = Ramp initiated by Master Ramp Delay Complete pulse disabled
(Default)
1 = Ramp initiated by Master Ramp Delay Complete pulse enabled
Bit 2: CONTROL_EN – Enables PMBus Control line to initiate ramp
0 = PMBus Control does not initiate ramp (Default)
1 = PMBus Control initiates ramp
Bit 1: FIRMWARE_START – Ramp start bit, self-clearing by ramp logic
0 = No ramp sequence initiated by firmware (Default)
1 = Ramp sequence initiated by firmware
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Bit 0: RAMP_EN – Enable Ramp Logic (Pre-biasing should be disabled before
asserting ramp, bit 16 of Pre-Bias Control Register)
0 = No soft start or power-down ramp controlled by hardware (Default)
1 = Enables hardware control of soft start or power-down ramp
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4.9.2 Ramp Status Register (RAMPSTAT)
Address 0x0018_0004 – Front End Control 2 Ramp Status Register
Address 0x001B_0004 – Front End Control 1 Ramp Status Register
Address 0x001E_0004 – Front End Control 0 Ramp Status Register
Bit Number
Bit Name
Access
Default
11
EADC_DONE_RAW
R
-
10
RAMP_COMP_INT_STATUS
R
-
Bit Number
Bit Name
Access
Default
8
PREBIAS_INT_STATUS
R
-
7
EADC_SAT_HIGH
R
-
Bit Number
Bit Name
Access
Default
Bit Number
Bit Name
Access
Default
5
EADC_EOC
R
2
RAMP_COMP_STATUS
R
-
4
PREBIAS_BUSY
R
-
9
RAMP_DLY_INT_STATUS
R
6
EADC_SAT_LOW
R
3
RAMP_BUSY
R
-
1
RAMP_DLY_STATUS
R
-
0
PREBIAS_STATUS
R
-
Bit 11: EADC_DONE_RAW – EADC Conversion Done Raw Status
0 = EADC Conversion has not completed
1 = EADC Conversion has completed
Bit 10: RAMP_COMP_INT_STATUS – Ramp Complete latched status
0 = No Ramp Complete has been declared
1 = Ramp Complete has been declared
Bit 9: RAMP_DLY_INT_STATUS – Ramp Delay Complete latched status
0 = No Ramp Delay Complete has been declared
1 = Ramp Delay Complete has been declared
Bit 8: PREBIAS_INT_STATUS – Pre-Bias Complete latched status
0 = No Pre-Bias Complete has been declared
1 = Pre-Bias Complete has been declared
Bit 7: EADC_SAT_HIGH – EADC Saturation High Indicator
0 = EADC output is not saturated at high limit
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1 = EADC output is saturated at high limit
Bit 6: EADC_SAT_LOW – EADC Saturation Low Indicator
0 = EADC output is not saturated at low limit
1 = EADC output is saturated at low limit
Bit 5: EADC_EOC – Indicates EADC end of conversion
Bit 4: PRE_BIAS_BUSY – Pre-Bias Busy
0 = Pre-Bias is not in progress
1 = Pre-Bias in progress
Bit 3: RAMP_BUSY – Ramp Busy
0 = Soft-Start/Power-Down Ramp is not in progress
1 = Soft-Start/Power-Down Ramp is in progress
Bit 2: RAMP_COMP_STATUS – Ramp Complete, Raw Status
0 = Ramp procedure is not complete
1 = Ramp procedure is complete
Bit 1: RAMP_DLY_STATUS – Ramp Delay Complete, Raw Status
0 = Ramp delay procedure is not complete
1 = Ramp delay procedure is complete
Bit 0: PRE_BIAS_STATUS – Pre-Bias Complete, Raw Status
0 = Pre-Bias is not completed
1 = Pre-Bias is completed
4.9.3 Ramp Cycle Register (RAMPCYCLE)
Address 0x0018_0008 – Front End Control 2 Ramp Cycle Register
Address 0x001B_0008 – Front End Control 1 Ramp Cycle Register
Address 0x001E_0008 – Front End Control 0 Ramp Cycle Register
Bit Number
Bit Name
Access
Default
23:8
DELAY_CYCLES
R/W
0000_0000_0000_0000
7
RESERVED
0
6:0
SWITCH_CYC_PER_STEP
R/W
000_0000
Bits 23-8: DELAY_CYCLES – Configures the number of delay cycles before an
initiation of ramp sequence. Each delay cycle consists of n switching cycles, as
specified by SWITCH_CYC_PER_STEP (Bits 6-0). Number of delay cycles can
vary from 0 to 65535
0 = Ramp starts without delay (Default)
1 = Ramp starts after (1*SWITCH_CYC_PER_STEP) switching cycles
2 = Ramp starts after (2*SWITCH_CYC_PER_STEP) switching cycles
…….
65535 = Ramp starts after (65535*SWITCH_CYC_PER_STEP)
switching cycles
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Bit 7: RESERVED
Bits 6-0: SWITCH_CYC_PER_STEP – Selects number of switching cycles per
DAC step. Number of subcycles can vary from 1 to 128.
0 = 1 switching cycle per step (Default)
1 = 2 subcycles per cycle
2 = 3 subcycles per cycle
…….
127 = 128 subcycles per cycle
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4.9.4 EADC DAC Value Register (EADCDAC)
Address 0x0018_000C – Front End Control 2 EADC DAC Value Register
Address 0x001B_000C – Front End Control 1 EADC DAC Value Register
Address 0x001E_000C– Front End Control 0 EADC DAC Value Register
Bit Number
Bit Name
Access
Default
16
DAC_DITHER_ON_SAMPLE
R/W
0
15
DAC_DITHER_EN
R/W
0
14
RESERVED
0
13:0
DAC_VALUE
R/W
00_1111_1111_0000
Bit 16: DAC_DITHER_ON_SAMPLE – DAC Dither on Sample
0 = Dither on sample trigger disabled (default)
1 = Dither on sample trigger enabled
Bit 15: DAC_DITHER_EN – DAC Dithering Enable
0 = DAC Dithering disabled (Default)
1 = DAC Dithering enabled
Bit 15: RESERVED
Bits 13-0: DAC_VALUE - Programmable DAC Value, effective LSB equals
0.09765625mV
4.9.5 Ramp DAC Ending Value Register (RAMPDACEND)
Address 0x0018_0010 – Front End Control 2 Ramp DAC Ending Register
Address 0x001B_0010 – Front End Control 1 Ramp DAC Ending Register
Address 0x001E_0010 – Front End Control 0 Ramp DAC Ending Register
Bit Number
Bit Name
Access
Default
13:0
RAMP_DAC_VALUE
R/W
00_0000_0000_0000
Bits 13-0: RAMP_DAC_VALUE – Programmable Ramp Ending DAC Value,
LSB equals 0.09765625mV
4.9.6 DAC Step Register (DACSTEP)
Address 0x0018_0014 – Front End Control 2 DAC Step Register
Address 0x001B_0014 – Front End Control 1 DAC Step Register
Address 0x001E_0014 – Front End Control 0 DAC Step Register
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Bit Number
Bit Name
Access
Default
17:0
DAC_STEP
R/W
00_0000_0000_0000_0000
Bits 17-0: DAC_STEP – Programmable 18-bit unsigned DAC Step. Bits 17:10
represent the real portion of the DAC Step (0-255 DAC counts at bit resolution of
0.09765625mV). Bits 9:0 represent the fractional portion of the DAC Step.
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4.9.7 DAC Saturation Step Register (DACSATSTEP)
Address 0x0018_0018 – Front End Control 2 DAC Saturation Step Register
Address 0x001B_0018 – Front End Control 1 DAC Saturation Step Register
Address 0x001E_0018 – Front End Control 0 DAC Saturation Step Register
Bit Number
Bit Name
Access
Default
13:0
DAC_SAT_STEP
R/W
00_0000_0000_0000
Bits 13-0: DAC_SAT_STEP – Programmable DAC Saturation Step, LSB equals
0.009765625mV
0 = DAC not adjusted on EADC saturation during ramp (Default)
1 = DAC adjusted by 1 DAC count on EADC saturation during ramp
…..
1023 = DAC adjusted by 1023 DAC counts on EADC saturation during
ramp
4.9.8 EADC Control Register (EADCCTRL)
Address 0x0018_0020 – Front End Control 2 EADC Control Register
Address 0x001B_0020 – Front End Control 1 EADC Control Register
Address 0x001E_0020 – Front End Control 0 EADC Control Register
Bit Number
Bit Name
Access
Default
28
D2S_COMP_EN
R/W
0
27
EN_HYST_HIGH
R/W
0
26
EN_HYST_LOW
R/W
0
Bit Number
Bit Name
Access
Default
25:22
SAMP_TRIG_SCALE
R/W
0000
21
FRAME_SYNC_EN
R/W
0
20
SCFE_CNT_RST
R/W
0
Bit Number
Bit Name
Access
Default
19:16
SCFE_CNT_INIT
R/W
0000
Bit Number
Bit Name
226
13
AUTO_GAIN_SHIFT_EN
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15
EADC_INV
R/W
0
12
AVG_WEIGHT_EN
14
AUTO_GAIN_SHIFT_MODE
R/W
0
11
AVG_SPATIAL_EN
SLUA766
Access
Default
Bit Number
Bit Name
Access
Default
Bit Number
Bit Name
Access
Default
R/W
0
R/W
0
R/W
0
10:9
AVG_MODE_SEL
R/W
00
8:6
EADC_MODE
R/W
000
5:4
AFE_GAIN
R/W
11
3
SCFE_GAIN_FILTER_SEL
R/W
1
2
SCFE_CLK_DIV_2
R/W
1
1
SCFE_ENA
R/W
1
0
EADC_ENA
R/W
1
Bit 28: D2S_COMP_EN – Analog Front End Ramp Comparator Enable
0 = Analog Front End Ramp Comparator disabled (Default)
1 = Analog Front End Ramp Comparator enabled
Bit 27: EN_HYST_HIGH – Increase comparator trip point by ~70mV
0 = Disables increase of ramp comparator trip point (Default)
1 = Enables increase of ramp comparator trip point
Bit 26: EN_HYST_LOW – Decrease comparator trip point by ~70mV
0 = Disables decrease of ramp comparator trip point (Default)
1 = Enables decrease of ramp comparator trip point
Bits 25-22: SAMP_TRIG_SCALE – Provides capability to mask incoming
sample triggers to Front End Control
0 = EADC conversion initiated on every received sample trigger (Default)
1 = EADC conversion initiated once every 2 received sample triggers
2 = EADC conversion initiated once every 3 received sample triggers
…..
15 = EADC conversion initiated once every 16 received sample triggers
Bit 21: FRAME_SYNC_EN – Enable synchronization of switched cap front end
counter to Switching Cycle Frame boundary
0 = Switch Cap Front End Counter not synchronized to frame (Default)
1 = Switch Cap Front End Counter synchronized to frame boundary
Bit 20: SCFE_CNT_RST – Force reset of Switched Cap Front End Counter
0 = Switch Cap Front End Counter operational (Default)
1 = Switch Cap Front End Counter reset
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Bits 19-16: SCFE_CNT_INIT – Configures initial Switched Cap Front End
Counter value out of reset or at start of switching cycle in Peak Current mode
Bit 15: EADC_INV – Enables EADC Data Inversion on data to filter module
0 = EADC Data is not inverted (Default)
1 = EADC Data Inverted
Bit 14: AUTO_GAIN_SHIFT_MODE – Configures Automatic Gain Shifting
mode
0 = Fixed mode, gain shifting dependent on saturation of EADC for
decreasing gain and less than 1/4 of dynamic range for increasing gain
(Default)
1 = NL mode, gain shifting dependent on Non-Linear limit thresholds
Bit 13: AUTO_GAIN_SHIFT_EN – Enables Automatic Gain Shifting mode
0 = Automatic Gain Shifting Mode disabled (Default)
1 = Automatic Gain Shifting Mode enabled
Bit 12: AVG_WEIGHT_EN – Enables weighted averaging in EADC averaging
mode (EADC_MODE = 1), only applicable in 4x and 8x averaging mode
(AVG_MODE_SEL = 1 or 2). For 4x averaging, two oldest samples are each
weighted by 1/8, the next oldest sample has a weight of ¼ and the newest sample
is weighted by ½. For 8x averaging, the four oldest samples are each weighted by
1/16, the next 2 oldest samples are weighted by 1/8, the next oldest sample is
weighted by ¼ and the newest sample is weighted by ¼.
0 = Weighted averaging disabled (Default)
1 = Weighted averaging enabled
Bit 11: AVG_SPATIAL_EN – Enables spatial mode in EADC averaging mode
0 = (Default)
For 2x averaging, Each sample trigger from DPWM triggers 2 EADC start
of conversions.
For 4x averaging, Each sample trigger from DPWM triggers 4 EADC start
of conversions.
For 8x averaging, Each sample trigger from DPWM triggers 8 EADC start
of conversions.
For 2x, 4x and 8x averaging; Each sample trigger from DPWM results in a
single averaged sample to filter.
1 = EADC samples averaged based on received sample triggers from
DPWM modules. Each sample trigger from DPWM triggers one EADC
start of conversion.
For 2x averaging, 2 sample triggers from DPWM results in a single
averaged sample to filter.
For 4x averaging, 4 sample triggers from DPWM results in a single
averaged sample to filter.
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For 8x averaging, 8 sample triggers from DPWM results in a single
averaged sample to filter.
Bit 10-9: AVG_MODE_SEL – Averaging Mode Configuration
0 = 2x Averaging (Default)
1 = 4x Averaging
2 = 8x Averaging
Bits 8-6: EADC_MODE – Selects EADC Mode Operation
0 = Standard mode, EADC samples based on sample triggers from
DPWM module (Default)
1 = Averaging Mode, configured by AVG_MODE_SEL
2 = Non-continuous SAR Mode
3 = Continuous SAR Mode
4 = Reserved
5 = Peak Current Mode
6 = Constant Power/Constant Current Control Mode (CPCC module
controls switching between Standard Mode and Non-Continuous SAR
Mode)
7 = Constant Power/Constant Current Control 2 Mode (CPCC module
controls switching between Standard mode and Continuous SAR Mode)
Bits 5-4: AFE_GAIN – AFE Front End Gain Setting
0 = 1x Gain, 8mV/LSB
1 = 2x Gain, 4mV/LSB
2 = 4x Gain, 2mV/LSB
3 = 8x Gain, 1mV/LSB (Default)
Bit 3: SCFE_GAIN_FILTER_SEL – Switched Cap Noise Filter Enable
0 = Disables Switch Cap Noise Filter
1 = Enables Switch Cap Noise Filter (Default)
Bit 2: SCFE_CLK_DIV_2 – Switched Cap Front End Clock Divider Select
0 = Switch Cap Clock divide by 2
1 = Switch Cap Clock divide by 1 (Default)
Bit 1: SCFE_ENA – Switch Cap Front Enable
0 = Disables Switch Cap Front End logic
1 = Enables Switch Cap Front End logic (Default)
Bit 0: EADC_ENA – EADC Enable
0 = Disables EADC
1 = Enables EADC (Default)
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4.9.9
4.9.10 Pre-Bias Control Register 0 (PREBIASCTRL0)
Address 0x0018_0028 – Front End Control 2 Pre-Bias Control Register 0
Address 0x001B_0028 – Front End Control 1 Pre-Bias Control Register 0
Address 0x001E_0028 – Front End Control 0 Pre-Bias Control Register 0
Bit Number
Bit Name
Access
Default
17
PRE_BIAS_POL
R/W
0
16
PRE_BIAS_EN
R/W
0
15:8
PRE_BIAS_RANGE
R/W
1111_1111
7:0
PRE_BIAS_LIMIT
R/W
0000_0000
Bit 17: PRE_BIAS_POL – Configures polarity of received error voltage
0 = Error equals Vref-Vin (Default)
1 = Error equals Vin-Vref
Bit 16: PRE_BIAS_EN – Enable Pre-Biasing of Error ADC (Ramp should be
disabled during pre-biasing, bit 0 of Ramp Control Register)
0 = Pre-Biasing has not been initiated (Default)
1 = Pre-Biasing by hardware has been enabled
Bits 15-8: PRE_BIAS_RANGE – Sets the acceptable range around the zero
error point. If Error ADC value stays in range for number of samples specified by
PRE_BIAS_LIMIT (Bits 7:0), PREBIAS_STATUS (Bit 0 of Ramp Status
Register) is enabled. Range will be +/- PRE_BIAS_RANGE around zero error
point.
Bits 7-0: PRE_BIAS_LIMIT – Sets the acceptable number of samples in which
the Error ADC value stays in range before asserting PREBIAS_STATUS (Bit 0
of Ramp Status Register). Counter limit ranges from 0 to 255. If
PREBIAS_STATUS is set, it will take PRE_BIAS_LIMIT samples outside of
acceptable range before clearing PREBIAS_STATUS.
4.9.11 Pre-Bias Control Register 1 (PREBIASCTRL1)
Address 0x0018_002C – Front End Control 2 Pre-Bias Control Register 1
Address 0x001B_002C – Front End Control 1 Pre-Bias Control Register 1
Address 0x001E_002C – Front End Control 0 Pre-Bias Control Register 1
Bit Number
Bit Name
Access
Default
23:16
SAMPLES_PER_ADJ
R/W
0000_0000
15:14
RESERVED
00
13:0
MAX_DAC_ADJ
R/W
00_0000_0000_0000
Bits 23-16: SAMPLES_PER_ADJ – Configures the number of EADC samples
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between Pre-Bias DAC setpoint adjustments
0 = DAC Setpoint adjustment on each EADC sample
1 = DAC Setpoint adjustment after 2 EADC sample
2 = DAC Setpoint adjustment after 3 EADC samples
…….
255 = DAC Setpoint adjustment after 256 EADC samples
Bits 15-14: RESERVED – Unused Bits
Bits 13-0: MAX_DAC_ADJ – Configures the maximum DAC setpoint
adjustment step
4.9.12 SAR Control Register (SARCTRL)
Address 0x0018_0030 – Front End Control 2 SAR Control Register
Address 0x001B_0030 – Front End Control 1 SAR Control Register
Address 0x001E_0030 – Front End Control 0 SAR Control Register
Bit Number
Bit Name
Access
Default
31:24
EADC_WINDOW_2
R/W
0010_1000
Bit Number
Bit Name
Access
Default
7:2
RESERVED
0000_00
23:16
EADC_WINDOW_1
R/W
0110_0000
15:8
SAR_RANGE
R/W
0001_0000
1:0
SAR_RESOLUTION
R/W
00
Bits 31-24: EADC_WINDOW_2 – Configures acceptable range of error values
to transition to AFE Gain of 2 during SAR process
Bits 23-16: EADC_WINDOW_1 – Configures acceptable range of error values
to transition to AFE Gain of 1 during SAR process
Bits 15-8: SAR_RANGE – Configures acceptable range of error values before
declaring SAR completion
Bits 7-2: RESERVED – Unused bits
Bits 1-0: SAR_RESOLUTION – Configures the final resolution for SAR
Conversions
0 = 8mV Resolution, 1x AFE Gain
1 = 4mV Resolution, 2x AFE Gain
2 = 2mV Resolution, 4x AFE Gain
3 = 1mV Resolution, 8x AFE Gain
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4.9.13 SAR Timing Register (SARTIMING)
Address 0x0018_0034 – Front End Control 2 SAR Timing Register
Address 0x001B_0034– Front End Control 1 SAR Timing Register
Address 0x001E_0034 – Front End Control 0 SAR Timing Register
Bit Number
Bit Name
Access
Default
Bit Number
Bit Name
Access
Default
10:8
SAR_TIMING_UPPER
R/W
100
6:4
SAR_TIMING_MID
R/W
011
7
RESERVED
0
3
RESERVED
0
2:0
SAR_TIMING_LOWER
R/W
010
Bits 10-8: SAR_TIMING_UPPER – Configures timing for Bits 9:8 of DAC
setpoint for SAR Algorithm
Bit 7: RESERVED – Unused bit
Bits 6-4: SAR_TIMING_MID – Configures timing for Bits 7:6 of DAC setpoint
for SAR Algorithm
Bit 3: RESERVED – Unused bit
Bits 2-0: SAR_TIMING_LOWER – Configures timing for Bits 5:0 of DAC
setpoint for SAR Algorithm
4.9.14 EADC Value Register (EADCVALUE)
Address 0x0018_0038 – Front End Control 2 EADC Value Register
Address 0x001B_0038 – Front End Control 1 EADC Value Register
Address 0x001E_0038 – Front End Control 0 EADC Value Register
Bit Number
Bit Name
Access
Default
Bit Number
Bit Name
Access
Default
25:16
ABS_VALUE
R
-
15
EADC_SAT_HIGH
R
-
13:9
RESERVED
0_0000
14
EADC_SAT_LOW
R
-
8:0
ERROR_VALUE
R
-
Bits 25-16: ABS_VALUE – 10-bit Absolute Value calculated by Front End
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Control Module with a resolution of 1.5625mV/bit
Bit 15: EADC_SAT_HIGH – EADC Saturation High Indicator
0 = EADC output is not saturated at high limit
1 = EADC output is saturated at high limit
Bit 14: EADC_SAT_LOW – EADC Saturation Low Indicator
0 = EADC output is not saturated at low limit
1 = EADC output is saturated at low limit
Bits 13-9: RESERVED – Unused bits
Bits 8-0: ERROR_VALUE – Signed 9-bit Error value measured by Front End
Control Module with a resolution of 1mV/bit
4.9.15 EADC Raw Value Register (EADCRAWVALUE)
Address 0x0018_003C – Front End Control 2 EADC Raw Value Register
Address 0x001B_003C – Front End Control 1 EADC Raw Value Register
Address 0x001E_003C – Front End Control 0 EADC Raw Value Register
Bit Number
Bit Name
Access
Default
8:0
RAW_ERROR_VALUE
R
-
Bits 8-0: RAW_ERROR_VALUE – Signed 9-bit Error value measured by Front
End Control Module with a resolution of 1mV/bit. Value is raw EADC data
before averaging.
4.9.16 DAC Status Register (DACSTAT)
Address 0x0018_0040 – Front End Control 2 DAC Status Register
Address 0x001B_0040 – Front End Control 1 DAC Status Register
Address 0x001E_0040 – Front End Control 0 DAC Status Register
Bit Number
Bit Name
Access
Default
9:0
DAC_VALUE
R
00_0000_0000
Bits 9-0: DAC_VALUE – Current 10-bit Value sent to DAC
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4.10
Miscellaneous Analog Control
The Miscellaneous Analog Control module provides control signals to the oscillator
and AFE blocks.
i. Clock Trim Register (CLKTRIM)
Address FFF7F000
Bit Number
Bit Name
Access
Default
16
RESET_DISABLE
R/W
0
15:0
RESERVED
xx
Bits 16: RESET_DISABLE
0 = Reset pin resets device (Default)
1 = Reset pin does not reset the device
Bits 15-0: RESERVED – may be non-zero, should not be changed by firmware
4.10.1 Package ID Register (PKGID)
Address FFF7F010
Bit Number
Bit Name
Access
Default
1:0
PKG_ID
R/W
00
Bits 1-0: PKG_ID – Represents package type of device
0 = 64-pin package (Default)
1 = 40-pin package
2 = 48-pin package
4.10.2 Brownout Register (BROWNOUT)
Address FFF7F014
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Bit Number
Bit Name
Access
Default
2
INT
R
-
1
INT_EN
R/W
0
0
COMP_EN
R/W
0
Bit 2: INT – Brownout Interrupt Status
0 = No Brownout Condition observed
1 = Brownout Condition observed
Bit 1: INT_EN – Brownout Interrupt Enable
0 = Brownout Interrupt disabled (Default)
1 = Brownout Interrupt enabled
Bit 0: COMP_EN – Brownout Comparator Enable
0 = Brownout comparator logic disabled (Default)
1 = Brownout comparator logic enabled
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4.10.3 Global I/O EN Register (GLBIOEN)
Address FFF7F018
Bit Number
Bit Name
Access
Default
29:0
GLOBAL_IO_EN
R/W
00_0000_0000_0000_0000_0000_0000_0000
Bits 29-0: GLOBAL_IO_EN – This register enables the global control of digital
I/O pins
0 = Control of IO is done by the functional block assigned to the IO
(Default)
1 = Control of IO is done by Global IO registers.
Bit assignment is done by this table:
236
BIT
PIN_NAME
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
FAULT[3]
ADC_EXT_TRIG
TCK
TDO
TMS
TDI
SCI_TX[1]
SCI_TX[0]
SCI_RX[1]
SCI_RX[0]
TMR_CAP
TMR_PWM[1]
TMR_PWM[0]
PMBUS-CLK
PMBUS-DATA
CONTROL
ALERT
EXT_INT
FAULT[2]
FAULT[1]
FAULT[0]
SYNC
DPWM3B
DPWM3A
DPWM2B
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4
3
2
1
0
DPWM2A
DPWM1B
DPWM1A
DPWM0B
DPWM0A
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4.10.4 Global I/O OE Register (GLBIOOE)
Address FFF7F01C
Bit Number
Bit Name
Access
Default
29:0
GLOBAL_IO_OE
R/W
00_0000_0000_0000_0000_0000_0000_0000
Bits 29-0: GLOBAL_IO_OE – This register controls the output enable signals
for all digital I/O pins
0 = Input (Default)
1 = Output
Bit assignment is done by this table:
238
BIT
PIN_NAME
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
FAULT[3]
ADC_EXT_TRIG
TCK
TDO
TMS
TDI
SCI_TX[1]
SCI_TX[0]
SCI_RX[1]
SCI_RX[0]
TMR_CAP
TMR_PWM[1]
TMR_PWM[0]
PMBUS-CLK
PMBUS-DATA
CONTROL
ALERT
EXT_INT
FAULT[2]
FAULT[1]
FAULT[0]
SYNC
DPWM3B
DPWM3A
DPWM2B
DPWM2A
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3
2
1
0
DPWM1B
DPWM1A
DPWM0B
DPWM0A
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4.10.5 Global I/O Open Drain Control Register (GLBIOOD)
Address FFF7F020
Bit Number
Bit Name
Access
Default
29:0
GLOBAL_IO_OD
R/W
00_0000_0000_0000_0000_0000_0000_0000
Bits 29-0: GLOBAL_IO_OD – This register controls if the global IO is
configured as an open drain. This bit multiplexes the GLOBAL_IO_VALUE
register to the OE signals
0 = Normal I/O (Default)
1 = Open Drain
Bit assignment is done by this table:
240
BIT
PIN_NAME
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
FAULT[3]
ADC_EXT_TRIG
TCK
TDO
TMS
TDI
SCI_TX[1]
SCI_TX[0]
SCI_RX[1]
SCI_RX[0]
TMR_CAP
TMR_PWM[1]
TMR_PWM[0]
PMBUS-CLK
PMBUS-DATA
CONTROL
ALERT
EXT_INT
FAULT[2]
FAULT[1]
FAULT[0]
SYNC
DPWM3B
DPWM3A
DPWM2B
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4
3
2
1
0
DPWM2A
DPWM1B
DPWM1A
DPWM0B
DPWM0A
4.10.6 Global I/O Value Register (GLBIOVAL)
Address FFF7F024
Bit Number
Bit Name
Access
Default
29:0
GLOBAL_IO_VALUE
R/W
00_0000_0000_0000_0000_0000_0000_0000
Bits 29-0: GLOBAL_IO_VALUE – This register set the output value of the
digital I/O pins when configured as outputs
0 = Digital I/O pin configured as low in output mode (Default)
1 = Digital I/O pin configured as high in output mode
Bit assignment is done by this table:
BIT
PIN_NAME
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
FAULT[3]
ADC_EXT_TRIG
TCK
TDO
TMS
TDI
SCI_TX[1]
SCI_TX[0]
SCI_RX[1]
SCI_RX[0]
TMR_CAP
TMR_PWM[1]
TMR_PWM[0]
PMBUS-CLK
PMBUS-DATA
CONTROL
ALERT
EXT_INT
FAULT[2]
FAULT[1]
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9
8
7
6
5
4
3
2
1
0
FAULT[0]
SYNC
DPWM3B
DPWM3A
DPWM2B
DPWM2A
DPWM1B
DPWM1A
DPWM0B
DPWM0A
4.10.7 Global I/O Read Register (GLBIOREAD)
Address FFF7F028
Bit Number
Bit Name
Access
Default
29:0
GLOBAL_IO_READ
R
-
Bits 29-0: GLOBAL_IO_READ – This register provides the value on these
signals after I/O muxing
0 = Digital I/O pin low (Default)
1 = Digital I/O pin high
Bit assignment is done by this table:
242
BIT
PIN_NAME
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
FAULT[3]
ADC_EXT_TRIG
TCK
TDO
TMS
TDI
SCI_TX[1]
SCI_TX[0]
SCI_RX[1]
SCI_RX[0]
TMR_CAP
TMR_PWM[1]
TMR_PWM[0]
PMBUS-CLK
PMBUS-DATA
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14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
CONTROL
ALERT
EXT_INT
FAULT[2]
FAULT[1]
FAULT[0]
SYNC
DPWM3B
DPWM3A
DPWM2B
DPWM2A
DPWM1B
DPWM1A
DPWM0B
DPWM0A
4.10.8
4.10.9 I/O Mux Control Register (IOMUX)
Address FFF7F030
Bit Number
Bit Name
Access
Default
12:11
FAULT_01 _MUX_SEL
R/W
00
Bit Number
Bit Name
Access
Default
10:9
EXT_TRIG_MUX_SEL
R/W
00
8:7
JTAG_CLK_MUX_SEL
R/W
01
6:4
JTAG_DATA_MUX_SEL
R/W
000
Bit Number
Bit Name
Access
Default
3:2
SYNC_MUX_SEL
R/W
00
1
UART_MUX_SEL
R/W
0
0
PMBUS_MUX_SEL
R/W
0
Bits 12-11: FAULT_01_MUX_SEL – Fault 0 and 1 Pin Mux Select
I/O Pin
FAULT-0
FAULT-1
0
FAULT-0
FAULT-1
1
SPI-CS
SPI-CLK
2
I2C-DATA
I2C-CLK
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Bits 10-9: EXT_TRIG_MUX_SEL – EXT_TRIG Pin Mux Select
I/O Pin
EXT_TRIG
0
EXT_TRIG
1
TCAP
2
SYNC
3
PWM-0
2
SYNC
3
PWM-0
Bits 8-7: JTAG_CLK_MUX_SEL – TCK Pin Mux Select
I/O Pin
TCK
0
TCK
1
TCAP
Bits 6-4: JTAG_DATA_MUX_SEL – TDO/TDI Pin Mux Select
I/O Pin
TDO
TDI
0
TDO
TDI
1
SCI_TX-0
SCI_RX-0
2
ALERT
CONTROL
3
FAULT-0
FAULT-1
4
SPI-MOSI
SPI-MISO
Bits 3-2: SYNC_MUX_SEL – SYNC Pin Mux Select
I/O Pin
SYNC
0
SYNC
1
TCAP
2
EXT_TRIG
Bit 1: UART_MUX_SEL – SCI_RX_1/SCI_TX_1 Pins Mux Select
I/O Pin
SCI_TX-1
SCI_RX-1
0
SCI_TX-1
SCI_RX-1
1
ALERT
CONTROL
Bit 0: PMBUS_MUX_SEL – SCL/SDA Pins Mux Select
I/O Pin
SCL
SDA
0
SCL
SDA
1
SCI_TX-0
SCI_RX-0
4.10.10
Current Sharing Control Register (CSCTRL)
Address FFF7F038
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PWM-0
SLUA766
Bit Number
Bit Name
Access
Default
23:16
DPWM_DUTY
R/W
0000_0000
15:8
DPMW_PERIOD
R/W
0000_0000
7:4
RESERVED
0000
3:0
TEST_MODE
R/W
0000
Bits 23-16: DPWM_DUTY – Configures Pulse Width/Duty Cycle for DPWM
output to Current Sharing circuit. Resolution of LSB equals period of MCLK
clock
Bits 15-8: DPWM_PERIOD – Configures Period for DPWM output to Current
Sharing circuit. Output period equals DPWM_PERIOD+1 * LSB resolution.
Resolution of LSB equals period of MCLK clock
Bits 7-4: RESERVED – Unused bits
Bits 3-0: TEST_MODE – Controls Current Sharing Operation
Test
Mode
0000
0001
0010
0011
01XX
10XX
11XX
EN_SW1
EN_SW2
DIS_RES DPWM
EN_HALF_CURR
0
1
0
0
1
0
1
0
0
0
1
0
0
0
1
0
1
1
1
0
0
0
0
0
0
0
0
1
0
ACTIVE
0
0
1
0
1
4.10.11
Temperature Reference Register (TEMPREF)
Address FFF7F03C
Bit Number
Bit Name
Access
Default
11:0
TEMP_REF
R/W
0000_0000_0000
Bits 11-0: TEMP_REF – Reference measurement taken during factory trim,
ADC12 measurement of the internal temperature sensor at room temperature for
use in offset calibration
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4.10.12
Power Disable Control Register (PWRDISCTRL)
Address FFF7F040
Bit Number
Bit Name
Access
Default
19
I2C_CLK_EN
R/W
1
Bit Number
Bit Name
Access
Default
17
PCM_CLK_EN
R/W
1
18
SPI_CLK_EN
R/W
1
16
CPCC_CLK_EN
R/W
1
13
FILTER0_CLK_EN
R/W
1
15
FILTER2_CLK_EN
R/W
1
Bit Number
Bit Name
Access
Default
14
FILTER1_CLK_EN
R/W
1
12
FE_CTRL2_CLK_EN
R/W
1
Bit Number
Bit Name
Access
Default
10
FE_CTRL0_CLK_EN
R/W
1
Bit Number
Bit Name
Access
Default
7
DPWM1_CLK_EN
R/W
1
6
DPWM0_CLK_EN
R/W
1
5
SCI1_CLK_EN
R/W
1
4
SCI0_CLK_EN
R/W
1
Bit Number
Bit Name
Access
Default
3
ADC12_CLK_EN
R/W
1
2
PMBUS_CLK_EN
R/W
1
1
GIO_CLK_EN
R/W
1
0
TIMER_CLK_EN
R/W
1
9
DPWM3_CLK_EN
R/W
1
8
DPWM2_CLK_EN
R/W
1
Bit 19: I2C_CLK_EN – Clock Enable for I2C Module
0 = Disables clocks to I2C Module
1 = Enables clocks to I2C Module (Default)
Bit 18: SPI_CLK_EN – Clock Enable for SPI Module
0 = Disables clocks to SPI Module
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FE_CTRL1_CLK_EN
R/W
1
SLUA766
1 = Enables clocks to SPI Module (Default)
Bit 17: PCM_CLK_EN – Clock Enable for Digital Peak Current Control Module
0 = Disables clocks to Digital Peak Current Control Module
1 = Enables clocks to Digital Peak Current Control Module (Default)
Bit 16: CPCC_CLK_EN – Clock Enable for Constant Power/Constant Current
Module
0 = Disables clocks to Constant Power/Constant Current Module
1 = Enables clocks to Constant Power/Constant Current Module (Default)
Bit 15: FILTER2_CLK_EN – Clock Enable for Filter 2 Module
0 = Disables clocks to Filter 2 Module
1 = Enables clocks to Filter 2 Module (Default)
Bit 14: FILTER1_CLK_EN – Clock Enable for Filter 1 Module
0 = Disables clocks to Filter 1 Module
1 = Enables clocks to Filter 1 Module (Default)
Bit 13: FILTER0_CLK_EN – Clock Enable for Filter 0 Module
0 = Disables clocks to Filter 0 Module
1 = Enables clocks to Filter 0 Module (Default)
Bit 12: FE_CTRL2_CLK_EN – Clock Enable for Front End Control 2 Module
0 = Disables clocks to Front End Control 2 Module
1 = Enables clocks to Front End Control 2 Module (Default)
Bit 11: FE_CTRL1_CLK_EN – Clock Enable for Front End Control 1 Module
0 = Disables clocks to Front End Control 1 Module
1 = Enables clocks to Front End Control 1 Module (Default)
Bit 10: FE_CTRL0_CLK_EN – Clock Enable for Front End Control 0 Module
0 = Disables clocks to Front End Control 0 Module
1 = Enables clocks to Front End Control 0 Module (Default)
Bit 9: DPWM3_CLK_EN – Clock Enable for DPWM 3 Module
0 = Disables clocks to DPWM 3 Module
1 = Enables clocks to DPWM 3 Module (Default)
Bit 8: DPWM2_CLK_EN – Clock Enable for DPWM 2 Module
0 = Disables clocks to DPWM 2 Module
1 = Enables clocks to DPWM 2 Module (Default)
Bit 7: DPWM1_CLK_EN – Clock Enable for DPWM 1 Module
0 = Disables clocks to DPWM 1 Module
1 = Enables clocks to DPWM 1 Module (Default)
Bit 6: DPWM0_CLK_EN – Clock Enable for DPWM 0 Module
0 = Disables clocks to DPWM 0 Module
1 = Enables clocks to DPWM 0 Module (Default)
Bit 5: SCI1_CLK_EN – Clock Enable for SCI/UART 1Module
0 = Disables clocks to SCI/UART 1 Module
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1 = Enables clocks to SCI/UART 1 Module (Default)
Bit 4: SCI0_CLK_EN – Clock Enable for SCI/UART 0 Module
0 = Disables clocks to SCI/UART 0 Module
1 = Enables clocks to SCI/UART 0 Module (Default)
Bit 3: ADC12_CLK_EN – Clock Enable for ADC12 Control Module
0 = Disables clocks to ADC12 Control Module
1 = Enables clocks to ADC12 Control Module (Default)
Bit 2: PMBUS_CLK_EN – Clock Enable for PMBus Interface Module
0 = Disables clocks to PMBus Interface Module
1 = Enables clocks to PMBus Interface Module (Default)
Bit 1: GIO_CLK_EN – Clock Enable for GIO Module
0 = Disables clocks to GIO Module
1 = Enables clocks to GIO Module (Default)
Bit 0: TIMER_CLK_EN – Clock Enable for Timer Module
0 = Disables clocks to Timer Module
1 = Enables clocks to Timer Module (Default)
4.10.13
DTC UART Pin Mux Select Register (DTCUARTSEL)
Address FFF7F048
Bit Number
Bit Name
Access
Default
4
DTC_ON_UART
R/W
0
3
DTC_B_SEL
R/W
0
2
DTC_A_SEL
R/W
0
Bit 4: DTC_ON_UART – DTC Phase A/B on UART pins
0 = DTC Phase-A input from TDI pin
DTC Phase-B input from TDO pin
1 = DTC Phase-A input from SCI_TX 0 pin
DTC Phase-B input from SCI_RX 0 pin
Bit 3: DTC_B_SEL – DTC Phase-B Pin Mux Select
0 = DTC Phase-B input from TDO pin
1 = DTC Phase-B input from SYNC pin
Bit 2: DTC_A_SEL – DTC Phase-A Pin Mux Select
0 = DTC Phase-A input from TDI pin
1 = DTC Phase-A input from TCK pin
Bit 1: UART1_RX_SEL – UART 1 RX Mux
0 = UART 1 RX input from UART 1 RX pin
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UART1_RX_SEL
R/W
0
0
UART0_RX_SEL
R/W
0
SLUA766
1 = UART 1 RX input from UART 0 RX pin
Bit 0: UART0_RX_SEL – UART 0 RX Mux
0 = UART 0 RX input from UART 0 RX pin
1 = UART 0 RX input from UART 1 RX pin
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4.11 PMBus Interface
4.11.1 PMBUS Control Register 1 (PMBCTRL1)
Address FFF7F600
Bit Number
Bit Name
Access
Default
20
PRC_CALL
R/W
0
19
GRP_CMD
R/W
0
18
PEC_ENA
R/W
0
17
EXT_CMD
R/W
0
Bit Number
Bit Name
Access
Default
16
CMD_ENA
R/W
0
15:8
BYTE_COUNT
R/W
0000_0000
7:1
SLAVE_ADDR
R/W
000_0000
0
RW
R/W
0
Bit 20: PRC_CALL – Master Process Call Message Enable
0 = Default state for all messages besides Process Call message (Default)
1 = Enables transmission of Process Call message
Bit 19: GRP_CMD – Master Group Command Message Enable
0 = Default state for all messages besides Group Command message
(Default)
1 = Enables transmission of Group Command message
Bit 18: PEC_ENA – Master PEC Processing Enable
0 = Disables PEC processing (Default)
1 = Enables PEC byte transmission/reception
Bit 17: EXT_CMD – Master Extended Command Code Enable (Only for Read)
0 = Use 1 byte for Command Code (Default)
1 = Use 2 bytes for Command Code
Bit 16: CMD_ENA – Master Command Code Enable
0 = Disables use of command code on Master initiated messages (Default)
1 = Enables use of command code on Master initiated messages
Bits 15-8: BYTE_COUNT – Indicates number of data bytes transmitted in
current message. Byte count does not include any device addresses, command
words or block lengths in block messages. In block messages, the PMBus
Interface automatically inserts the block length into the message based on the byte
count setting. The firmware only needs to load the address, command words and
data to be transmitted. PMBus Interface supports byte writes up to 255 bytes.
Bits 7-1: SLAVE_ADDR – Specifies the address of the slave to which the
current message is directed towards.
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Bit 0: RW – Indicates if current Master initiated message is read operation or
write operation.
0 = Message is a write transaction (data from Master to Slave) (Default)
1 = Message is a read transaction (data from Slave to Master)
4.11.2 PMBus Transmit Data Buffer (PMBTXBUF)
Address FFF7F604
Bit Number
Bit Name
Access
Default
31:24
BYTE3
R/W
0000_0000
23:16
BYTE2
R/W
0000_0000
15:8
BYTE1
R/W
0000_0000
7:0
BYTE0
R/W
0000_0000
Bits 31-24: BYTE3 – Last data byte transmitted from Transmit Data Buffer
Bits 23-16: BYTE2 – Third data byte transmitted from Transmit Data Buffer
Bits 15-8: BYTE1 – Second data byte transmitted from Transmit Data Buffer
Bits 7-0: BYTE0 – First data byte transmitted from Transmit Data Buffer
4.11.3 PMBus Receive Data Register (PMBRXBUF)
Address FFF7F608
Bit Number
Bit Name
Access
Default
31:24
BYTE3
R
-
23:16
BYTE2
R
-
15:8
BYTE1
R
-
7:0
BYTE0
R
-
Bits 31-24: BYTE3 – Last data byte received in Receive Data Buffer
Bits 23-16: BYTE2 – Third data byte received in Receive Data Buffer
Bits 15-8: BYTE1 – Second data byte received in Receive Data Buffer
Bits 7-0: BYTE0 – First data byte received in Receive Data Buffer
4.11.4 PMBus Acknowledge Register (PMBACK)
Address FFF7F60C
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Bit Number
Bit Name
Access
Default
0
ACK
R/W
0
Bit 0: ACK – Allows firmware to acknowledge or not acknowledge received data
0 = NACK received data (Default)
1 = Acknowledge received data, bit clears upon issue of ACK on PMBus
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4.11.5 PMBus Status Register (PMBST)
Address FFF7F610
Bit Number
Bit Name
Access
Default
Bit Number
Bit Name
Access
Default
Bit Number
Bit Name
Access
Default
Bit Number
Bit Name
Access
Default
Bit Number
Bit Name
Access
Default
21
SCL_RAW
R
-
20
SDA_RAW
R
-
17
CONTROL_EDGE
R
14
LOST_ARB
R
-
5
EOM
R
-
18
ALERT_RAW
R
-
16
ALERT_EDGE
R
-
13
BUS_FREE
R
-
9
CLK_HIGH_DETECTED
R
-
19
CONTROL_RAW
R
-
12
UNIT_BUSY
R
-
11
RPT_START
R
-
8
CLK_LOW_TIMEOUT
R
-
4
DATA_REQUEST
R
-
15
MASTER
R
10
SLAVE_ADDR_READY
R
-
7
PEC_VALID
R
-
3
DATA_READY
R
-
6
NACK
R
2:0
RD_BYTE_COUNT
R
-
Bit 21: SCL_RAW – PMBus Clock Pin Real Time Status
0 = PMBus clock pin observed at logic level low
1 = PMBus clock pin observed at logic level high
Bit 20: SDA_RAW – PMBus Data Pin Real Time Status
0 = PMBus data pin observed at logic level low
1 = PMBus data pin observed at logic level high
Bit 19: CONTROL_RAW – Control Pin Real Time Status
0 = Control pin observed at logic level low
1 = Control pin observed at logic level high
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Bit 18: ALERT_RAW – Alert Pin Real Time Status
0 = Alert pin observed at logic level low
1 = Alert pin observed at logic level high
Bit 17: CONTROL_EDGE – Control Edge Detection Status
0 = Control pin has not transitioned
1 = Control pin has been asserted by another device on PMBus
Bit 16: ALERT_EDGE – Alert Edge Detection Status
0 = Alert pin has not transitioned
1 = Alert pin has been asserted by another device on PMBus
Bit 15: MASTER – Master Indicator
0 = PMBus Interface in Slave Mode or Idle Mode
1 = PMBus Interface in Master Mode
Bit 14: LOST_ARB – Lost Arbitration Flag
0 = Master has attained control of PMBus
1 = Master has lost arbitration and control of PMBus
Bit 13: BUS_FREE – PMBus Free Indicator
0 = PMBus processing current message
1 = PMBus available for new message
Bit 12: UNIT_BUSY – PMBus Busy Indicator
0 = PMBus Interface is idle, ready to transmit/receive message
1 = PMBus Interface is busy, processing current message
Bit 11: RPT_START – Repeated Start Flag
0 = No Repeated Start received by interface
1 = Repeated Start condition received by interface
Bit 10: SLAVE_ADDR_READY – Slave Address Ready
0 = Indicates no slave address is available for reading
1 = Slave address ready to be read from Receive Data Register (Bits 6:0)
Bit 9: CLK_HIGH_DETECTED – Clock High Detection Status
0 = No Clock High condition detected
1 = Clock High exceeded 50ms during message
Bit 8: CLK_LOW_TIMEOUT – Clock Low Timeout Status
0 = No clock low timeout detected
1 = Clock low timeout detected, clock held low for greater than 35ms
Bit 7: PEC_VALID – PEC Valid Indicator
0 = Received PEC not valid (if EOM is asserted)
1 = Received PEC is valid
Bit 6: NACK – Not Acknowledge Flag Status
0 = Data transmitted has been accepted by receiver
1 = Receiver has not accepted transmitted data
Bit 5: EOM – End of Message Indicator
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0 = Message still in progress or PMBus in idle state.
1 = End of current message detected
Bit 4: DATA_REQUEST – Data Request Flag
0 = No data needed by PMBus Interface
1 = PMBus Interface request additional data. PMBus clock stretching
enabled to stall bus until firmware provides transmit data.
Bit 3: DATA_READY – Data Ready Flag
0 = No data available for reading by processor
1 = PMBus Interface read buffer full, firmware required to read data prior
to further bus activity. PMBus clock stretching enabled to stall bus until
data is read by firmware.
Bits 2-0: RD_BYTE_COUNT – Number of Data Bytes available in Receive
Data Register
0 = No received data
1 = 1 byte received. Data located in Receive Data Register, Bits 7-0
2 = 2 bytes received. Data located in Receive Data Register, Bits 15-0
3 = 3 bytes received. Data located in Receive Data Register, Bits 23-0
4 = 4 bytes received. Data located in Receive Data Register, Bits 31-0
4.11.6 PMBus Interrupt Mask Register (PMBINTM)
Address FFF7F614
Bit Number
Bit Name
Access
Default
9
CLK_HIGH_TIMEOUT
R/W
1
8
LOST_ARB
R/W
1
7
CONTROL
R/W
1
6
ALERT
R/W
1
Bit Number
Bit Name
Access
Default
5
EOM
R/W
1
4
SLAVE_ADDR_READY
R/W
1
3
DATA_REQUEST
R/W
1
Bit Number
Bit Name
Access
Default
2
DATA_READY
R/W
1
1
BUS_LOW_TIMEOUT
R/W
1
0
BUS_FREE
R/W
1
Bit 9: CLK_HIGH_TIMEOUT – Clock High Timeout Interrupt Mask
0 = Generates interrupt if clock high exceeds 55ms during message
1 = Disables interrupt generation for Clock High timeout (Default)
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Bit 8: LOST_ARB – Lost Arbitration Interrupt Mask
0 = Generates interrupt upon assertion of Lost Arbitration flag
1 = Disables interrupt generation upon assertion of Lost Arbitration flag
(Default)
Bit 7: CONTROL – Control Detection Interrupt Mask
0 = Generates interrupt upon assertion of Control flag
1 = Disables interrupt generation upon assertion of Control flag (Default)
Bit 6: ALERT – Alert Detection Interrupt Mask
0 = Generates interrupt upon assertion of Alert flag
1 = Disables interrupt generation upon assertion of Alert flag (Default)
Bit 5: EOM – End of Message Interrupt Mask
0 = Generates interrupt upon assertion of End of Message flag
1 = Disables interrupt generation upon assertion of End of Message flag
(Default)
Bit 4: SLAVE_ADDR_READY – Slave Address Ready Interrupt Mask
0 = Generates interrupt upon assertion of Slave Address Ready flag
1 = Disables interrupt generation upon assertion of Slave Address Ready
flag (Default)
Bit 3: DATA_REQUEST – Data Request Interrupt Mask
0 = Generates interrupt upon assertion of Data Request flag
1 = Disables interrupt generation upon assertion of Data Request flag
(Default)
Bit 2: DATA_READY – Data Ready Interrupt Mask
0 = Generates interrupt upon assertion of Data Ready flag
1 = Disables interrupt generation upon assertion of Data Ready flag
(Default)
Bit 1: BUS_LOW_TIMEOUT – Clock Low Timeout Interrupt Mask
0 = Generates interrupt upon assertion of Clock Low Timeout flag
1 = Disables interrupt generation upon assertion of Clock Low Timeout
flag (Default)
Bit 0: BUS_FREE – Bus Free Interrupt Mask
0 = Generates interrupt upon assertion of Bus Free flag
1 = Disables interrupt generation upon assertion of Bus Free flag (Default)
4.11.7 PMBus Control Register 2 (PMBCTRL2)
Address FFF7F618
Bit Number
Bit Name
Access
256
22:21
RX_BYTE_ACK_CNT
R/W
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MAN_CMD
R/W
19
TX_PEC
R/W
18:16
TX_COUNT
R/W
SLUA766
Default
Bit Number
Bit Name
Access
Default
11
15
PEC_ENA
R/W
0
0
14:8
SLAVE_MASK
R/W
111_1111
0
7
MAN_SLAVE_ACK
R/W
0
000
6:0
SLAVE_ADDR
R/W
111_1100
Bit 22-21: RX_BYTE_ACK_CNT – Configures number of data bytes to
automatically acknowledge when receiving data in slave mode.
00 = 1 byte received by slave. Firmware is required to manually
acknowledge every received byte.
01 = 2 bytes received by slave. Hardware automatically acknowledges the
first received byte. Firmware is required to manually acknowledge after
the second received byte.
10 = 3 bytes received by slave. Hardware automatically acknowledges the
first 2 received bytes. Firmware is required to manually acknowledge after
the third received byte.
11 = 4 bytes received by slave. Hardware automatically acknowledges the
first 3 received bytes. Firmware is required to manually acknowledge after
the fourth received byte (Default)
Bit 20: MAN_CMD – Manual Command Acknowledgement Mode
0 = Slave automatically acknowledges received command code (Default)
1 = Data Request flag generated after receipt of command code, firmware
required to issue ACK to continue message
Bit 19: TX_PEC – Asserted when the slave needs to send a PEC byte at end of
message. PMBus Interface will transmit the calculated PEC byte after
transmitting the number of data bytes indicated by TX Byte Cnt(Bits 19:17).
0 = No PEC byte transmitted (Default)
1 = PEC byte transmitted at end of current message
Bit 18-16: TX_COUNT– Number of valid bytes in Transmit Data Register
0 = No bytes valid (Default)
1 = One byte valid, Byte #0 (Bits 7:0 of Receive Data Register)
2 = Two bytes valid, Bytes #0 and #1 (Bits 15:0 of Receive Data Register)
3 = Three bytes valid, Bytes #0-2 (Bits 23:0 of Receive Data Register)
4 = Four bytes valid, Bytes #0-3 (Bits 31:0 of Receive Data Register)
Bit 15: PEC_ENA – PEC Processing Enable
0 = PEC processing disabled (Default)
1 = PEC processing enabled
Bit 14-8: SLAVE_MASK – Used in address detection, the slave mask enables
acknowledgement of multiple device addresses by the slave. Writing a ‘0’ to a bit
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within the slave mask enables the corresponding bit in the slave address to be
either ‘1’ or ‘0’ and still allow for a match. Writing a ‘0’ to all bits in the mask
enables the PMBus Interface to acknowledge any device address. Upon power-up,
the slave mask defaults to 7Fh, indicating the slave will only acknowledge the
address programmed into the Slave Address (Bits 6-0).
Bit 7: MAN_SLAVE_ACK– Manual Slave Address Acknowledgement Mode
0 = Slave automatically acknowledges device address specified in
SLAVE_ADDR, Bits 6-0 (Default)
1 = Enables the Manual Slave Address Acknowledgement Mode.
Firmware is required to read received address and acknowledge on every
message
Bits 6-0: SLAVE_ADDR – Configures the current device address of the slave.
Used in automatic slave address acknowledge mode (default mode). The PMBus
Interface will compare the received device address with the value stored in the
Slave Address bits and the mask configured in the Slave Mask bits. If matching,
the slave will acknowledge the device address.
4.11.8 PMBus Hold Slave Address Register (PMBHSA)
Address FFF7F61C
Bit Number
Bit Name
Access
Default
7:1
SLAVE_ADDR
R
-
0
SLAVE_RW
R
-
Bits 7-1: SLAVE_ADDR – Stored device address acknowledged by the slave
Bit 0: SLAVE_RW – Stored R/W bit from address acknowledged by the slave
0 = Write Access
1 = Read Access
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4.11.9 PMBus Control Register 3 (PMBCTRL3)
Address FFF7F620
Bit Number
Bit Name
Access
Default
25
CLK_HI_EN
R/W
0
24:23
Reserved
R/W
0
Bit Number
Bit Name
Access
Default
22
MASTER_EN
R/W
0
21
SLAVE_EN
R/W
1
20
CLK_LO_DIS
R/W
0
19
IBIAS_B_EN
R/W
0
18
IBIAS_A_EN
R/W
0
Bit Number
Bit Name
Access
Default
17
SCL_DIR
R/W
0
16
SCL_VALUE
R/W
0
15
SCL_MODE
R/W
0
14
SDA_DIR
R/W
0
13
SDA_VALUE
R/W
0
Bit Number
12
11
10
9
Bit Name
Access
Default
SDA_MODE
R/W
0
CNTL_DIR
R/W
0
CNTL_VALUE
R/W
0
CNTL_MODE
R/W
0
Bit Number
Bit Name
Access
Default
8
ALERT_DIR
R/W
0
Bit Number
Bit Name
Access
Default
4
FAST_MODE_PLUS
R/W
0
7
ALERT _VALUE
R/W
0
3
FAST_MODE
R/W
0
6
ALERT_MODE
R/W
0
2
BUS_LO_INT_EDGE
R/W
0
5
CNTL_INT_EDGE
R/W
0
1
ALERT_EN
R/W
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RESET
R/W
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Bit 25: CLK_HI_EN – PMBus Clock High Timeout Enable
0 = PMBus Clock High Timeout disabled (Default)
1 = PMBus Clock High Timeout enabled
Bit 24-23: Reserved – Unused Bits
Bit 22: MASTER_EN – PMBus Master Enable
0 = Disables PMBus Master capability (Default)
1 = Enables PMBus Master capability
Bit 21: SLAVE_EN – PMBus Slave Enable
0 = Disables PMBus Slave capability
1 = Enables PMBus Slave capability (Default)
Bit 20: CLK_LO_DIS – Clock Low Timeout Disable
0 = Clock Low Timeout Enabled (Default)
1 = Clock Low Timeout Disabled
Bit 19: IBIAS_B_EN – PMBus Current Source B Control
0 = Disables Current Source for PMBUS address detection thru ADC
(Default)
1 = Enables Current Source for PMBUS address detection thru ADC
Bit 18: IBIAS_A_EN – PMBus Current Source A Control
0 = Disables Current Source for PMBUS address detection thru ADC
(Default)
1 = Enables Current Source for PMBUS address detection thru ADC
Bit 17: SCL_DIR – Configures direction of PMBus clock pin in GPIO mode
0 = PMBus clock pin configured as output (Default)
1 = PMBus clock pin configured as input
Bit 16: SCL_VALUE – Configures output value of PMBus clock pin in GPIO
Mode
0 = PMBus clock pin driven low in GPIO Mode (Default)
1 = PMBus clock pin driven high in GPIO Mode
Bit 15: SCL_MODE – Configures mode of PMBus Clock pin
0 = PMBus clock pin configured in functional mode (Default)
1 = PMBus clock pin configured as GPIO
Bit 14: SDA_DIR – Configures direction of PMBus data pin in GPIO mode
0 = PMBus data pin configured as output (Default)
1 = PMBus data pin configured as input
Bit 13: SDA_VALUE – Configures output value of PMBus data pin in GPIO
Mode
0 = PMBus data pin driven low in GPIO Mode (Default)
1 = PMBus data pin driven high in GPIO Mode
Bit 12: SDA_MODE – Configures mode of PMBus Data pin
0 = PMBus data pin configured in functional mode (Default)
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1 = PMBus data pin configured as GPIO
Bit 11: CNTL_DIR – Configures direction of Control pin in GPIO mode
0 = Control pin configured as output (Default)
1 = Control pin configured as input
Bit 10: CNTL_VALUE – Configures output value of Control pin in GPIO Mode
0 = Control pin driven low in GPIO Mode (Default)
1 = Control pin driven high in GPIO Mode
Bit 9: CNTL_MODE – Configures mode of Control pin
0 = Control pin configured in functional mode (Default)
1 = Control pin configured as GPIO
Bit 8: ALERT_DIR – Configures direction of Alert pin in GPIO mode
0 = Control pin configured as output (Default)
1 = Control pin configured as input
Bit 7: ALERT_VALUE – Configures output value of Alert pin in GPIO Mode
0 = Alert pin driven low in GPIO Mode (Default)
1 = Alert pin driven high in GPIO Mode
Bit 6: ALERT_MODE – Configures mode of Alert pin
0 = Alert pin configured in functional mode (Default)
1 = Aler3 pin configured as GPIO
Bit 5: CNTL_INT_EDGE – Control Interrupt Edge Select
0 = Interrupt generated on falling edge of Control (Default)
1 = Interrupt generated on rising edge of Control
Bit 4: FAST_MODE_PLUS – Fast Mode Plus Enable
0 = Standard 100 KHz mode enabled (Default)
1 = Fast Mode Plus enabled (1MHz operation on PMBus)
Bit 3: FAST_MODE – Fast Mode Enable
0 = Standard 100 KHz mode enabled (Default)
1 = Fast Mode enabled (400KHz operation on PMBus)
Bit 2: BUS_LO_INT_EDGE – Clock Low Timeout Interrupt Edge Select
0 = Interrupt generated on rising edge of clock low timeout (Default)
1 = Interrupt generated on falling edge of clock low timeout
Bit 1: ALERT_EN – Slave Alert Enable
0 = PMBus Alert is not driven by slave, pulled up high on PMBus
(Default)
1 = PMBus Alert driven low by slave
Bit 0: RESET – PMBus Interface Synchronous Reset
0 = No reset of internal state machines (Default)
1 = Control state machines are reset to initial states
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4.12 GIO – General Purpose Input/Output Module
GIO Registers have the following attributes:
- Addresses placed on word boundaries
- Byte, Half-word and Word Writes are permitted
- All Registers can be read in any mode
- All Registers are writeable
4.12.1 Fault IO Direction Register (FAULTDIR)
Address FFF7FA00
Bit Number
Bit Name
Access
Default
6
TMS_DIR
R/W
0
5
TDI_DIR
R/W
0
4
TDO_DIR
R/W
0
3
FLT3_DIR
R/W
0
2
FLT2_DIR
R/W
0
1
FLT1_DIR
R/W
0
Bit 6: TMS_DIR – TMS Pin Configuration
0 = TMS pin configured as an input pin in GPIO mode (Default)
1 = TMS pin configured as an output pin in GPIO mode
Bit 5: TDI_DIR – TDI Pin Configuration
0 = TDI pin configured as an input pin in GPIO mode (Default)
1 = TDI pin configured as an output pin in GPIO mode
Bit 4: TDO_DIR – TDO Pin Configuration
0 = TDO pin configured as an input pin in GPIO mode (Default)
1 = TDO pin configured as an output pin in GPIO mode
Bit 3: FLT3_DIR – FAULT[3] Pin Configuration
0 = FAULT[3] pin configured as an input pin (Default)
1 = FAULT[3] pin configured as an output pin
Bit 2: FLT2_DIR – FAULT[2] Pin Configuration
0 = FAULT[2] pin configured as an input pin (Default)
1 = FAULT[2] pin configured as an output pin
Bit 1: FLT1_DIR – FAULT[1] Pin Configuration
0 = FAULT[1] pin configured as an input pin (Default)
1 = FAULT[1] pin configured as an output pin
Bit 0: FLT0_DIR – FAULT[0] Pin Configuration
0 = FAULT[0] pin configured as an input pin (Default)
1 = FAULT[0] pin configured as an output pin
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FLT0_DIR
R/W
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4.12.2 Fault Input Register (FAULTIN)
Address FFF7FA04
Bit Number
Bit Name
Access
Default
6
TMS_IN
R
-
5
TDI_IN
R
-
4
TDO_IN
R
-
3
FLT3_IN
R
-
Bit 6: TMS_IN – Input Value of TMS Pin
0 = TMS pin driven low in GPIO mode
1 = TMS pin driven high in GPIO mode
Bit 5: TDI_IN – Input Value of TDI Pin
0 = TDI pin driven low in GPIO mode
1 = TDI pin driven high in GPIO mode
Bit 4: TDO_IN – Input Value of TDO Pin
0 = TDO pin driven low in GPIO mode
1 = TDO pin driven high in GPIO mode
Bit 3: FLT3_IN – Input Value of FAULT[3] Pin
0 = FAULT[3] pin driven low
1 = FAULT[3] pin driven high
Bit 2: FLT2_IN – Input Value of FAULT[2] Pin
0 = FAULT[2] pin driven low
1 = FAULT[2] pin driven high
Bit 1: FLT1_IN – Input Value of FAULT[1] Pin
0 = FAULT[1] pin driven low
1 = FAULT[1] pin driven high
Bit 0: FLT0_IN – Input Value of FAULT[0] Pin
0 = FAULT[0] pin driven low
1 = FAULT[0] pin driven high
4.12.3 Fault Output Register (FAULTOUT)
Address FFF7FA08
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FLT2_IN
R
-
1
FLT1_IN
R
-
0
FLT0_IN
R
-
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Bit Number
Bit Name
Access
Default
Bit Number
Bit Name
Access
Default
6
TMS_OUT
R/W
0
2
FLT2_OUT
R/W
0
5
TDI_OUT
R/W
0
4
RESERVED
0
1
FLT1_OUT
R/W
0
3
FLT3_OUT
R/W
0
0
FLT0_OUT
R/W
0
Bit 6: TMS_OUT – TMS Pin Output Value
0 = TMS pin driven low when configured as output in GPIO mode
(Default)
1 = TMS pin driven high when configured as output in GPIO mode
Bit 5: TDI_OUT – TDI Pin Output Value
0 = TDI pin driven low when configured as output in GPIO mode
(Default)
1 = TDI pin driven high when configured as output in GPIO mode
Bit 4: RESERVED – Unused Bit
Bit 3: FLT3_OUT – FAULT[3] Pin Output Value
0 = FAULT[3] pin driven low when configured as output (Default)
1 = FAULT[3] pin driven high when configured as output
Bit 2: FLT2_OUT – FAULT[2] Pin Output Value
0 = FAULT[2] pin driven low when configured as output (Default)
1 = FAULT[2] pin driven high when configured as output
Bit 1: FLT1_OUT – FAULT[1] Pin Output Value
0 = FAULT[1] pin driven low when configured as output (Default)
1 = FAULT[1] pin driven high when configured as output
Bit 0: FLT0_OUT – FAULT[0] Pin Output Value
0 = FAULT[0] pin driven low when configured as output (Default)
1 = FAULT[0] pin driven high when configured as output
4.12.4 Fault Interrupt Enable Register (FAULTINTENA)
Address FFF7FA14
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Bit Number
Bit Name
Access
Default
Bit Number
Bit Name
Access
Default
6
TMS_INT_EN
R/W
0
3
FLT3_INT_EN
R/W
0
5
TDI_INT_EN
R/W
0
2
FLT2_INT_EN
R/W
0
1
FLT1_INT_EN
R/W
0
Bit 6: TMS_INT_EN – TMS Interrupt Enable
0 = Interrupt disabled for TMS pin (Default)
1 = Interrupt enabled for TMS pin in GPIO mode
Bit 5: TDI_INT_EN – TDI Interrupt Enable
0 = Interrupt disabled for TDI pin (Default)
1 = Interrupt enabled for TDI pin in GPIO mode
Bit 4: TDO_INT_EN – TDO Interrupt Enable
0 = Interrupt disabled for TDO pin (Default)
1 = Interrupt enabled for TDO pin in GPIO mode
Bit 3: FLT3_INT_EN – FAULT[3] Interrupt Enable
0 = Interrupt disabled for FAULT[3] pin (Default)
1 = Interrupt enabled for FAULT[3] pin
Bit 2: FLT2_INT_EN – FAULT[2] Interrupt Enable
0 = Interrupt disabled for FAULT[2] pin (Default)
1 = Interrupt enabled for FAULT[2] pin
Bit 1: FLT1_INT_EN – FAULT[1] Interrupt Enable
0 = Interrupt disabled for FAULT[1] pin (Default)
1 = Interrupt enabled for FAULT[1] pin
Bit 0: FLT0_INT_EN – FAULT[0] Interrupt Enable
0 = Interrupt disabled for FAULT[0] pin (Default)
1 = Interrupt enabled for FAULT[0] pin
4.12.5 Fault Interrupt Polarity Register (FAULTINTPOL)
Address FFF7FA18
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TDO_INT_EN
R/W
0
0
FLT0_INT_EN
R/W
0
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Bit Number
Bit Name
Access
Default
Bit Number
Bit Name
Access
Default
6
TMS_INT_POL
R/W
0
3
FLT3_INT_POL
R/W
0
5
TDI_INT_POL
R/W
0
2
FLT2_INT_POL
R/W
0
4
TDO_INT_POL
R/W
0
1
FLT1_INT_POL
R/W
0
0
FLT0_INT_POL
R/W
0
Bit 6: TMS_INT_POL – TMS Interrupt Polarity Select
0 = Interrupt generated on falling edge (Default)
1 = Interrupt generated on rising edge
Bit 5: TDI_INT_POL – TDI Interrupt Polarity Select
0 = Interrupt generated on falling edge (Default)
1 = Interrupt generated on rising edge
Bit 4: TDO_INT_POL – TDO Interrupt Polarity Select
0 = Interrupt generated on falling edge (Default)
1 = Interrupt generated on rising edge
Bit 3: FLT3_INT_POL – FAULT[3] Interrupt Polarity Select
0 = Interrupt generated on falling edge (Default)
1 = Interrupt generated on rising edge
Bit 2: FLT2_INT_POL – FAULT[2] Interrupt Polarity Select
0 = Interrupt generated on falling edge (Default)
1 = Interrupt generated on rising edge
Bit 1: FLT1_INT_POL – FAULT[1] Interrupt Polarity Select
0 = Interrupt generated on falling edge (Default)
1 = Interrupt generated on rising edge
Bit 0: FLT0_INT_POL – FAULT[0] Interrupt Polarity Select
0 = Interrupt generated on falling edge (Default)
1 = Interrupt generated on rising edge
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4.12.6 Fault Interrupt Pending Register (FAULTINTPEND)
Address FFF7FA1C
Bit Number
Bit Name
Access
Default
Bit Number
Bit Name
Access
Default
6
TMS_INT_PEND
R/W
0
3
FLT3_INT_PEND
R/W
0
5
TDI_INT_PEND
R/W
0
2
FLT2_INT_PEND
R/W
0
4
TDO_INT_PEND
R/W
0
1
FLT1_INT_PEND
R/W
0
0
FLT0_INT_PEND
R/W
0
Bit 6: TMS_INT_PEND – TMS has caused an interrupt. Writing a 1 to a bit will
clear the interrupt flag
0 = No Interrupt detected (Default)
1 = Interrupt pending
Bit 5: TDI_INT_PEND – TDI has caused an interrupt. Writing a 1 to a bit will
clear the interrupt flag
0 = No Interrupt detected (Default)
1 = Interrupt pending
Bit 4: TDO_INT_PEND – TDO has caused an interrupt. Writing a 1 to a bit will
clear the interrupt flag
0 = No Interrupt detected (Default)
1 = Interrupt pending
Bit 3: FLT3_INT_PEND – FAULT[3] has caused an interrupt. Writing a 1 to a
bit will clear the interrupt flag
0 = No Interrupt detected (Default)
1 = Interrupt pending
Bit 2: FLT2_INT_PEND – FAULT[2] has caused an interrupt. Writing a 1 to a
bit will clear the interrupt flag
0 = No Interrupt detected (Default)
1 = Interrupt pending
Bit 1: FLT1_INT_PEND – FAULT[1] has caused an interrupt. Writing a 1 to a
bit will clear the interrupt flag
0 = No Interrupt detected (Default)
1 = Interrupt pending
Bit 0: FLT0_INT_PEND – FAULT[0] has caused an interrupt. Writing a 1 to a
bit will clear the interrupt flag
0 = No Interrupt detected (Default)
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1 = Interrupt pending
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4.12.7 External Interrupt Direction Register (EXTINTDIR)
Address FFF7FA20
Bit Number
Bit Name
Access
Default
0
EXT_INT_DIR
R/W
0
Bit 0: EXT_INT_DIR – EXT-INT Pin Configuration
0 = EXT-INT pin configured as an input pin (Default)
1 = EXT-INT pin configured as an output pin
4.12.8 External Interrupt Input Register (EXTINTIN)
Address FFF7FA24
Bit Number
Bit Name
Access
Default
0
EXT_INT_IN
R
-
Bit 0: EXT_INT_IN – Input Value of EXT-INT Pin
0 = EXT-INT pin driven low in GPIO mode
1 = EXT-INT pin driven high in GPIO mode
4.12.9 External Interrupt Output Register (EXTINTOUT)
Address FFF7FA28
Bit Number
Bit Name
Access
Default
0
EXT_INT_OUT
R/W
0
Bit 0: EXT_INT_OUT – EXT-INT Pin Output Value
0 = EXT-INT pin driven low (Default)
1 = EXT-INT pin driven high
4.12.10
External Interrupt Enable Register (EXTINTENA)
Address FFF7FA34
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Bit Number
Bit Name
Access
Default
0
EXT_INT_EN
R/W
0
Bit 0: EXT_INT_EN – EXT-INT Interrupt Enable
0 = Interrupt disabled for EXT-INT pin (Default)
1 = Interrupt enabled for EXT-INT pin
4.12.11
External Interrupt Polarity Register (EXTTINTPOL)
Address FFF7FA38
Bit Number
Bit Name
Access
Default
0
EXT_INT_POL
R/W
0
Bit 0: EXT_INT_POL – EXT-INT Interrupt Polarity Select
0 = Interrupt generated on falling edge (Default)
1 = Interrupt generated on rising edge
4.12.12
External Interrupt Pending Register (EXTINTPEND)
Address FFF7FA3C
Bit Number
Bit Name
Access
Default
0
EXT_INT_PEND
R/W
0
Bit 0: EXT_INT_PEND – EXT-INT has caused an interrupt. Writing a 1 to a bit
will clear the interrupt flag.
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4.13 Timer Module
Timer Registers have the following attributes:
- 32-bit wide
- Addresses placed on word boundaries
- Byte, Half-Word and word writes permitted
- All Registers can be read in any mode
- All Registers, except for the Timer Powerdown Control Register, are writeable
in any mode. The Timer Powerdown Control Register is writeable only in
privilege mode.
4.13.1 24-bit Counter Data Register (T24CNTDAT)
Address FFF7FD00
Bit Number
Bit Name
Access
Default
23:0
CNT_DAT
R
-
Bits 23-0: CNT_DAT: – Contains the 24-bit counter value
4.13.2 24-bit Counter Control Register (T24CNTCTRL)
Address FFF7FD04
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Bit Number
Bit Name
Access
Default
15:8
PRESCALE
R/W
0000_0000
7:3
RESERVED
00000
2
EXT_CLK_SEL
R/W
0
1
OV_INT_ENA
R/W
0
0
OV_FLAG
R
0
Bits 15-8: PRESCALE – Defines the prescaler value used to select the 24-bit
counter resolution. The minimum divider ratio is 4, prescaler value less than 3
defaults to 3.
Counter Resolution = (Prescaler Value+1)*1/ICLK
Bits 7-3: RESERVED – Unused bits
Bit 2: EXT_CLK_SEL – External Clock Select
0 = Selects ICLK as clock for 24-bit counter (Default)
1 = Selects External Clock on FAULT-0 as clock for 24-bit counter
Bit 1: OV_INT_ENA – Counter Overflow Interrupt Enable
0 = Disables 24-bit Counter Overflow Interrupt (Default)
1 = Enables 24-bit Counter Overflow Interrupt
Bit 0: OV_FLAG – Indicates a counter overflow. Overflow event is cleared by
writing a ‘1’ to this bit. If a clear and an overflow event occur at the same time,
the flag will remain high (set has priority versus clear).
0 = No counter overflow since last clear
1 = Counter overflow since last clear
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4.13.3 24-bit Capture Channel Data Register (T24CAPDAT)
Address FFF7FD08
Bit Number
Bit Name
Access
Default
23:0
CAP_DAT
R
-
Bits 23-0: CAP_DAT– Contains the 24-bit input capture value
4.13.4 24-bit Capture Channel Control Register (T24CAPCTRL)
Address FFF7FD14
Bit Number
Bit Name
Access
Default
5:4
CAP_SEL
R/W
00
3:2
EDGE
R/W
00
1
CAP_INT_ENA
R/W
0
0
CAP_INT_FLAG
R/W
0
Bits 5-4: CAP_SEL – Capture Pin Select
00 = TCAP pin (Default)
01 = SCI_RX[0] pin
10 = SCI_RX[1] pin
11 = SYNC pin
Bits 3-2: EDGE – Input Capture Edge Select
00 = No Capture (Default)
01 = Rising Edge
10 = Falling Edge
11 = Both Edges
Bit 1: CAP_INT_ENA – Input Capture Interrupt Enable
0 = Disables 24-bit input capture interrupt (Default)
1 = Enables 24-bit input capture interrupt
Bit 0: CAP_INT_FLAG – Flag which indicates a valid input capture event. This
bit is cleared by writing a ‘1’ to it or by reading the corresponding Capture
Channel Data Register. If a clear and a valid capture event occur at the same time,
the flag will remain high (set has priority versus clear).
0 = No valid capture event since last clear
1 = Valid capture event since last clear
4.13.5 24-bit Capture I/O Control and Data Register (T24CAPIO)
Address FFF7FD20
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Bit Number
Bit Name
Access
Default
2
TCAP_IN
R
-
1
TCAP_OUT
R/W
0
0
TCAP_DIR
R/W
0
Bit 2: TCAP_IN – Input data for pin TCAP pin, when connected to chip I/O
0 = Logic level low detected on TCAP pin
1 = Logic level high detected on TCAP pin
Bit 1: TCAP_OUT – Output data for pin TCAP pin, when connected to chip I/O
0 = Logic level low driven on TCAP pin in output mode (Default)
1 = Logic level high driven on TCAP pin in output mode
Bit 0: TCAP_DIR – Controls data direction for pin TCAP, when connected to
chip I/O
0 = TCAP pin configured as input (Default)
1 = TCAP pin configured as output
4.13.6 24-bit Output Compare Channel 0 Data Register (T24CMPDAT0)
Address FFF7FD24
Bit Number
Bit Name
Access
Default
23:0
CMP_DAT
R/W
0000_0000_0000_0000_0000_0000
Bits 23-0: CMP_DAT– Contains the 24-bit output comparison value
4.13.7 24-bit Output Compare Channel 1 Data Register (T24CMPDAT1)
Address FFF7FD28
Bit Number
Bit Name
Access
Default
23:0
CMP_DAT
R/W
0000_0000_0000_0000_0000_0000
Bits 23-0: CMP_DAT– Contains the 24-bit output comparison value
4.13.8 24-bit Output Compare Channel 0 Control Register (T24CMPCTRL0)
Address FFF7FD2C
Bit Number
Bit Name
Access
1
CMP_INT_ENA
R/W
0
CMP_INT_FLAG
R/W
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Default
0
0
Bit 1: CMP_INT_ENA– Output Compare Channel Interrupt
0 = Disables Output Compare Channel Interrupt (Default)
1 = Enables Output Compare Channel Interrupt
Bit 0: CMP_INT_FLAG – Indicates a valid output compare event. Bit can be
cleared by writing a ‘1’ to the bit or by rewriting the 24-bit Output Compare
Channel Data Register. If a clear and compare event occur at the same time, the
flag will remain high (set has priority versus clear).
0 = No compare event since last clear
1 = Compare event since last clear
4.13.9 24-bit Output Compare Channel 1 Control Register (T24CMPCTRL1)
Address FFF7FD30
Bit Number
Bit Name
Access
Default
1
CMP_INT_ENA
R/W
0
0
CMP_INT_FLAG
R/W
0
Bit 1: CMP_INT_ENA– Output Compare Channel Interrupt
0 = Disables Output Compare Channel Interrupt (Default)
1 = Enables Output Compare Channel Interrupt
Bit 0: CMP_INT_FLAG – Indicates a valid output compare event. Bit can be
cleared by writing a ‘1’ to the bit or by rewriting the 24-bit Output Compare
Channel Data Register. If a clear and compare event occur at the same time, the
flag will remain high (set has priority versus clear).
0 = No compare event since last clear
1 = Compare event since last clear
4.13.10
PWMx Counter Data Register (T16PWMxCNTDAT)
Address FFF7FD34 – 16-bit PWM0 Counter Data Register
Address FFF7FD58 – 16-bit PWM1 Counter Data Register
Address FFF7FD6C – 16-bit PWM2 Counter Data Register
Address FFF7FD80 – 16-bit PWM3 Counter Data Register
Bit Number
Bit Name
Access
Default
276
15:0
CNT_DAT
R
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Bits 15-0: CNT_DAT – Contains the 16-bit counter value. Read-only.
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4.13.11
PWMx Counter Control Register (T16PWMxCNTCTRL)
Address FFF7FD38 – 16-bit PWM0 Counter Control Register
Address FFF7FD5C – 16-bit PWM1 Counter Control Register
Address FFF7FD70 – 16-bit PWM2 Counter Control Register
Address FFF7FD84 – 16-bit PWM3 Counter Control Register
Bit Number
Bit Name
Access
Default
Bit Number
Bit Name
Access
Default
15:8
PRESCALE
R/W
0000_0000
3
SW_RESET
R/W
0
7
RESERVED
0
2
CMP_RESET_ENA
R/W
0
6:5
SYNC_SEL
R/W
00
1
OV_INT_ENA
R/W
0
4
SYNC_EN
R/W
0
0
OV_INT_FLAG
R/W
0
Bit 15-8: PRESCALE – Defines the prescaler value to select the PWM counter
resolution.
Counter Resolution = (Prescaler + 1) *1/ICLK
Bit 7: RESERVED – Unused bit
Bits 6:5: SYNC_SEL – Configures master PWM counter
0 = PWM0 Counter (Default)
1 = PWM1 Counter
2 = PWM2 Counter
3 = PWM3 Counter
Bit 4: SYNC_EN – PWM counter starts when master PWM counter is enabled
0 = PWM counter independent of other PWM counters (Default)
1 = PWM counter controlled by Master PWM counter
Bit 3: SW_RESET– PWM counter reset by software. This bit is cleared after
reset and has to be set to run the PWM counter.
0 = PWM counter reset and counter stop (Default)
1 = PWM counter is running
Bit 2: CMP_RESET_ENA – Enables PWM counter reset by compare action of
T16CMPxDR.
0 = Disable PWM counter reset by compare action (Default)
1 = Enable PWM counter reset by compare action
Bit 1: OV_INT_ENA– PWM Counter Overflow Interrupt Enable
0 = Disable PWM counter overflow interrupt (Default)
1 = Enable PWM counter overflow interrupt
Bit 0: OV_INT_FLAG – Flag which indicates a PWM counter overflow. This bit
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is cleared by writing ‘1’ to it. If a clear and an overflow event occur at the same
time, the flag will remain high (set has priority versus clear).
0 = No PWM counter overflow since last clear
1 = PWM counter overflow since last clear
4.13.12
PWMx 16-bit Compare Channel 0-1 Data Register
(T16PWMxCMPyDAT)
Address FFF7FD3C – 16-bit PWM0 Compare Channel 0 Data Register
Address FFF7FD40 – 16-bit PWM0 Compare Channel 1 Data Register
Address FFF7FD60 – 16-bit PWM1 Compare Channel 0 Data Register
Address FFF7FD64 – 16-bit PWM1 Compare Channel 1 Data Register
Address FFF7FD74 – 16-bit PWM2 Compare Channel 0 Data Register
Address FFF7FD78 – 16-bit PWM2 Compare Channel 1 Data Register
Address FFF7FD88 – 16-bit PWM3 Compare Channel 0 Data Register
Address FFF7FD8C – 16-bit PWM3 Compare Channel 1 Data Register
Bit Number
Bit Name
Access
Default
15:0
CMP_DAT
R/W
0000_0000_0000_0000
Bits 15-0: CMP_DAT – Contains the 16-bit compare value. When in PWM
mode, the value in the T16PWMxCMPyDAT is loaded after a match with the
PWMx Counter Data Register. When in OC mode, it has to be written by the
CPU. The mode is controlled by the bit SHADOW in the PWMx/Dual Compare
Control Register. If both Registers T16PWMxCMP0DAT and
T16PWMxCMP1DAT contain the same value, the interrupt and pin behavior is
controlled by output compare channel 0 (T16PWMxCMP0DAT has priority over
T16PWMxCMP1DAT).
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4.13.13
PWM Compare Control Register (T16PWMxCMPCTRL)
Address FFF7FD44 – 16-bit PWM0 Compare Control Register
Address FFF7FD68 – 16-bit PWM1 Compare Control Register
Bit Number
Bit Name
Access
Default
12
SHADOW
R/W
0
Bit Number
Bit Name
Access
Default
7:6
PWM_OUT_ACTION1
R/W
00
Bit Number
Bit Name
Access
Default
11
PWM_IN
R
-
2
CMP1_INT_FLAG
R/W
0
10
PWM_OUT
R/W
0
9
PWM_OUT_ENA
R/W
0
5:4
PWM_OUT_ACTION0
R/W
00
1
CMP0_INT_ENA
R/W
0
8
PWM_OUT_DRV
R/W
0
3
CMP1_INT_ENA
R/W
0
0
CMP0_INT_FLAG
R/W
0
Bit 12: SHADOW – Controls the update of the 16-bit output compare Registers.
0 = PWM output compare Registers immediately written (Default)
1 = PWM output compare Registers updated through the buffers
T16PWMxCMPyDAT after a match occurs in the corresponding
Register T16PWMxCMPyDAT.
Bit 11: PWM_IN – Input value of PWM pin when configured in PWM mode
0 = Logic level low detected on PWM pin
1 = Logic level high detected on PWM pin
Bit 10: PWM_OUT – Data to be written into the output latch when
PWM_OUT_DRV is high.
0 = Output latch is cleared when PWM_OUT_DRV=1 (Default)
1 = Output latch is set when PWM_OUT_DRV=1
Bit 9: PWM_OUT_ENA – FAN-PWM pin configuration
0 = FAN-PWM configured as an input pin (Default)
1 = FAN-PWM configured as an output pin
Bit 8: PWM_OUT_DRV – Causes the value of the bit PWM_OUT to be written
into the output latch. So it is possible to preload the output latch or to use the pin
as GPIO. The compare action has priority before the preload function. This bit is
always read as ‘0’.
0 = Output latch not affected by the value of PWM_OUT (Default)
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1 = Value of OUT written into the output latch
Bits 7-6: PWM_OUT_ACTION1 – These 2 bits select the output action when a
compare equal is detected on T16CMP1DAT
00 = No action (Default)
01 = Set pin
10 = Clear pin
11 = Toggle pin
Bits 5-4: PWM_OUT_ACTION0 – Selects the output action when a compare
equal is detected on T16CMP0DAT.
00 = No action (Default)
01 = Set pin
10 = Clear pin
11 = Toggle pin
Bit 3: CMP1_INT_ENA– Compare 1 Interrupt Enable
0 = Disables Compare 1 Interrupt (Default)
1 = Enables Compare 1 Interrupt
Bit 2: CMP1_INT_FLAG – Flag which indicates a valid output compare 1
event. This bit is cleared by writing ‘1’ to this bit or by rewriting
T16PWMxCMP1DAT. If a clear and a compare event occurs at the same time,
the flag will remain high (set has priority versus write clear).
0 = No compare event since last clear
1 = Compare event since last clear
Bit 1: CMP0_INT_ENA – Compare 0 Interrupt Enable
0 = Disables Compare 0 Interrupt (Default)
1 = Enables Compare 0 Interrupt
Bit 0: CMP0_INT_FLAG – Flag which indicates a valid output compare 1
event. This bit is cleared by writing ‘1’ to this bit or by rewriting
T16PWMxCMP0DAT. If a clear and a compare event occurs at the same time,
the flag will remain high (set has priority versus write clear).
0 = No compare event since last clear
1 = Compare event since last clear
4.13.14
PWMx Compare Control Register (T16PWMxCMPCTRL)
Address FFF7FD7C – 16-bit PWM2 Compare Control Register
Address FFF7FD90 – 16-bit PWM3 Compare Control Register
Bit Number
Bit Name
Access
Default
12
SHADOW
R/W
0
11:4
RESERVED
R/W
0000_0000
3
CMP1_INT_ENA
R/W
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Bit Number
Bit Name
Access
Default
2
CMP1_INT_FLAG
R/W
0
1
CMP0_INT_ENA
R/W
0
0
CMP0_INT_FLAG
R/W
0
Bit 12: SHADOW – Controls the update of the 16-bit output compare Registers.
0 = PWM output compare Registers immediately written (Default)
1 = PWM output compare Registers updated through the buffers
T16PWMxCMPyDAT after a match occurs in the corresponding
Register T16PWMxCMPyDAT.
Bits 11-4: RESERVED – Unused bits
Bit 3: CMP1_INT_ENA– Compare 1 Interrupt Enable
0 = Disables Compare 1 Interrupt (Default)
1 = Enables Compare 1 Interrupt
Bit 2: CMP1_INT_FLAG – Flag which indicates a valid output compare 1
event. This bit is cleared by writing ‘1’ to this bit or by rewriting
T16PWMxCMP1DAT. If a clear and a compare event occurs at the same time,
the flag will remain high (set has priority versus write clear).
0 = No compare event since last clear
1 = Compare event since last clear
Bit 1: CMP0_INT_ENA – Compare 0 Interrupt Enable
0 = Disables Compare 0 Interrupt (Default)
1 = Enables Compare 0 Interrupt
Bit 0: CMP0_INT_FLAG – Flag which indicates a valid output compare 1
event. This bit is cleared by writing ‘1’ to this bit or by rewriting
T16PWMxCMP0DAT. If a clear and a compare event occurs at the same time,
the flag will remain high (set has priority versus write clear).
0 = No compare event since last clear
1 = Compare event since last clear
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4.13.15
Watchdog Status (WDST)
Address FFF7FD94
Bit Number
Bit Name
Access
Default
3
WAKE_EV_RAW
R
-
2
WD_EV_RAW
R
-
1
WAKE_EV_INT
R
-
0
WD_EV_INT
R
-
Bit 3: WAKE_EV_RAW – Watchdog Wake Event Raw Status
0 = Watchdog Timer has not reached ½ of terminal count
1 = Watchdog Timer has reached ½ of terminal count
Bit 2: WD_EV_RAW – Watchdog Event Raw Status
0 = Watchdog Timer has not reached terminal count
1 = Watchdog Timer has reached terminal count
Bit 1: WAKE_EV_INT – Watchdog Wake Event Interrupt Status, cleared on
read of Watchdog Status Register
0 = Watchdog Timer has not reached ½ of terminal count
1 = Watchdog Timer has reached ½ of terminal count
Bit 0: WD_EV_INT – Watchdog Event Interrupt Status, cleared on read of
Watchdog Status Register
0 = Watchdog Timer has not reached terminal count
1 = Watchdog Timer has reached terminal count
4.13.16
Watchdog Control (WDCTRL)
Address FFF7FD98
Bit Number
Bit Name
Access
Default
14:8
PERIOD
R/W
111_1111
7
RESERVED
0
Bit Number
Bit Name
Access
Default
3
WKEV_INT_EN
R/W
0
6
PROTECT
R/W
1
2
WKEV_EN
R/W
0
5
CPU_RESET_EN
R/W
0
1
WDRST_EN
R/W
0
4
WDRST_INT_EN
R/W
0
0
CNT_RESET
R/W
1
Bits 14-8: PERIOD - Configures the time for the watchdog reset.
H’7F ~ 1.3s (minimum) (Default)
H’00 ~ 10ms (maximum)
Bit 7: RESERVED – Unused bits
Bit 6: PROTECT – Watchdog Protect Bit, Active Low
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0 = Watchdog enable bits are protected, only can be cleared by POR.
CPU_RESET_ENA (Bit 5), WDRST_ENA (Bit 2) and WKEV_ENA (Bit
1) are automatically set high when PROTECT is written low.
1 = Watchdog enable bits can be set by processor (Default)
Bit 5: CPU_RESET_EN – Enables Watchdog Reset Event to reset the CPU
0 = Watchdog Reset does not reset CPU (Default)
1 = Watchdog Reset does resets CPU
Bit 4: WDRST_INT_EN – Watchdog Reset Event Interrupt Enable
0 = Disables generation of Watchdog Reset Interrupt (Default)
1 = Enables generation of Watchdog Reset Interrupt
Bit 3: WKEN_INT_EN – Watchdog Wake Event Interrupt Enable
0 = Disables generation of Watchdog Wake Event Interrupt (Default)
1 = Enables generation of Watchdog Wake Event Interrupt
Bit 2: WKEV_EN – Watchdog Wake Event Comparator Enable
0 = Disables Watchdog Wake Event Comparator (Default)
1 = Enables Watchdog Wake Event Comparator
Bit 1: WDRST_EN – Watchdog Reset Event Comparator Enable
0 = Disables Watchdog Reset Event Comparator (Default)
1 = Enables Watchdog Reset Event Comparator
Bit 0: CNT_RESET – This bit resets the watchdog counters. This bit self clears
and if the enables are set, the counters restart counting.
0 = Watchdog counters enabled (Default)
1 = Watchdog counters reset
4.14 Memory Controller - MMC
All MMC control Registers have the following attributes:
- 16-bit wide
- Addresses placed on word boundaries
- 16-bit data is placed on the least significant data bus D[15:0]
- Only half-word writes are permitted
- Registers are readable in any mode, but writeable only in privilege mode
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4.14.1 Static Memory Control Register (SMCTRL)
Address FFFFFD00
Bit Number
Bit Name
Access
Default
13:12
LEAD
R/W
00
11:9
TRAIL
R/W
000
7:4
ACTIVE
R/W
0000
3
ENDIAN
R
-
1:0
WIDTH
R/W
00
Bits 13-12: LEAD – Address setup time cycles (write operations)
00 = No setup time required (Default)
01 = Write strobe is delayed one cycle
10 = Write strobe is delayed two cycles
11 = Write strobe is delayed three cycles
Bits 11-9: TRAIL – Number of Trailing wait states. Determine the trailing wait
states after read and write operations to the memory associated with the chip
select corresponding to the wait states.
Bit s 7-4: ACTIVE – Active Wait states (both read/write operations)
0000 = 0 Wait states (Default)
0001 = 1 Wait states
0010 = 2 Wait states
0011 = 3 Wait states
0100 = 4 Wait states
0101 = 5 Wait states
0110 = 6 Wait states
0111 = 7 Wait states
1000 = 8 Wait states
1001 = 9 Wait states
1010 = 10 Wait states
1011 = 11 Wait states
1100 = 12 Wait states
1101 = 13 Wait states
1110 = 14 Wait states
1111 = 15 Wait states
Bit 3: ENDIAN – Endian Mode Identification
0 = CPU configured in big endian mode
1 = CPU configured in little endian mode
Bits 1-0: WIDTH – Data Width for Memories
00 = 8 bits (Default)
01 = 16 bits
10 = 32 bits
11 = Reserved
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4.14.2 Write Control Register (WCTRL)
Address FFFFFD2C
Bit Number
Bit Name
Access
Default
1
TRAIL_OVR
R/W
0
0
WBUF_ENA
R/W
0
Bit 1: TRAIL_OVR – Write trailing wait state override.
0 = At least one trailing wait state (Default)
1 = TRAIL sets trailing wait states
Bit 0: WBUF_ENA – Write buffer enable. When this bit is 1, the memory
controller latches the data and control signals in the first cycle for write operations
to the memories and peripherals on the expansion bus and lets the CPU perform
other operations. However, the CPU starts a wait state if there is another request
before the memory controller finishes.
0 = Write buffer disabled (Disabled)
1 = Write buffer enabled
ii. Peripheral Control Register (PCTRL)
Address FFFFFD30
Bit Number
Bit Name
Access
Default
0
PBUF_ENA
R/W
0
Bit 0: PBUF_ENA – Write buffer enable. When this bit is set to 1, the memory
controller latches the data and control signals in the first cycle for write operations
to the memories and peripherals on the expansion bus and lets the CPU perform
other operations. However, the CPU starts a wait state if there is another request
before the memory controller finishes.
0 = Write buffer disabled (Default)
1 = Write buffer enabled
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4.14.3 Peripheral Location Register (PLOC)
Address FFFFFD34
Bit Number
Bit Name
Access
Default
15:0
LOC
R/W
0000_0000_0000_0000
Bits 15-0: LOC – These 16 bits represent the peripheral location bits, which
correspond to each of the 16 peripheral selects.
0 = Peripheral is internal (Default)
1 = Peripheral is external
4.14.4 Peripheral Protection Register (PPROT)
Address FFFFFD38
Bit Number
Bit Name
Access
Default
15:0
PROT
R/W
0000_0000_0000_0000
Bits 15-0: PROT – These 16 bits represent the peripheral protection bits, which
correspond to each of the 16 peripheral selects.
0 = Peripheral is accessible in all modes (Default)
1 = Peripheral is accessible in privilege mode only
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4.15 DEC – Address Manager
The DEC generates the memory selects and SAR peripheral select signals by
decoding the address and control signals from the ARM processor. In addition, the
DEC provides the control signals for the Program and Data Flash.
The assigned memory selects for Cyclone are as follows:
Memory Select 0 => Boot ROM (1Kx32)
Memory Select 1 => Program Flash 1(8Kx32)
Memory Select 2 => Data Flash (512x32)
Memory Select 3 => Data RAM (1Kx32)
Memory Select 4 => Loop Mux (1Kx32)
Memory Select 5 => Fault Mux (1Kx32)
Memory Select 6 => ADC12 Control (1Kx32)
Memory Select 7 => DPWM3 (1Kx32)
Memory Select 8 => Filter 2 (1Kx32)
Memory Select 9 => DPWM 2 (1Kx32)
Memory Select 10 => Front End Control 2 (1Kx32)
Memory Select 11 => Filter 1 (1Kx32)
Memory Select 12 => DPWM 1 (1Kx32)
Memory Select 13 => Front End Control 1 (1Kx32)
Memory Select 14 => Filter 0 (1Kx32)
Memory Select 15 => DPWM 0 (1Kx32)
Memory Select 16 => Front End Control 0 (1Kx32)
Memory Select 17 => Program Flash 2(8Kx32)
4.15.1 Memory Fine Base Address High Register 0 (MFBAHR0)
Address FFFFFE00
Bit Number
Bit Name
Access
Default
15:0
ADDRESS[31:16]
R/W
0000_0000_0000_0000
Bits 15-0: ADDRESS[31:16] – 16 Most Significant Bits of the Base Address.
The Base Address sets the 22 most significant bits of the memory address.
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4.15.2 Memory Fine Base Address Low Register 0 (MFBALR0)
Address FFFFFE04
Bit Number
Bit Name
Access
Default
15:10
ADDRESS[15:10]
R/W
000000
8
MS
R/W
0
7:4
BLOCK_SIZE
R/W
0000
1
RONLY
R/W
0
0
PRIV
R/W
0
Bits15-10: ADDRESS[15:10] – 6 Least Significant Bits of the Base Address. The
Base Address sets the 22 most significant bits of the memory address.
Bit 8: MS – Memory Map Select
0 = Memory Map configuration not updated (Default)
1 = Enables the fine and coarse memory selects and activates the memory
map
Bits 7-4: BLOCK_SIZE – Configures the size of the memory
0000 = Memory select is disabled (Default)
0001 = 1K Bytes
0010 = 2K Bytes
0011 = 4K Bytes
0100 = 8K Bytes
0101 = 16K Bytes
0110 = 32K Bytes
0111 = 64K Bytes
1000 = 128K Bytes
1001 = 256K Bytes
1010 = 512K Bytes
1011 = 1M Bytes
1100 = 2M Bytes
1101 = 4M Bytes
1110 = 8M Bytes
1111 = 16M Bytes
Bit 1: RONLY – Read-only protection. This bit sets read-only protection for the
memory selected by the memory select. An illegal access exception is generated
when a write is attempted to the memory.
0 = Read/write access to memory (Default)
1 = Read accesses to memory only
Bit 0: PRIV – Privilege mode protection. This bit sets privilege mode protection
for the memory Registration selected by the memory select. An illegal access
exception is generated on any access to memory protected by privilege mode.
0 = User/privilege mode accesses to memory (Default)
1 = Privilege mode accesses to memory only
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4.15.3 Memory Fine Base Address High Register 1-3,17 (MFBAHRx)
Address FFFFFE08 – Memory Fine Base Address High Register 1
Address FFFFFE10– Memory Fine Base Address High Register 2
Address FFFFFE18 – Memory Fine Base Address High Register 3
Address FFFFFE88 – Memory Fine Base Address High Register 17
Bit Number
Bit Name
Access
Default
15:0
ADDRESS[31:16]
R/W
0000_0000_0000_0000
Bits 15-0: ADDRESS[31:16] – 16 Most Significant Bits of the Base Address.
The Base Address sets the 22 most significant bits of the memory address.
4.15.4 Memory Fine Base Address Low Register 1-3,17(MFBALRx)
Address FFFFFE0C – Memory Fine Base Address Low Register 1
Address FFFFFE14 – Memory Fine Base Address Low Register 2
Address FFFFFE1C – Memory Fine Base Address Low Register 3
Address FFFFFE8C – Memory Fine Base Address Low Register 17
Bit Number
Bit Name
Access
Default
15:10
ADDRESS[15:10]
R/W
000000
9
AW
R/W
0
7:4
BLOCK_SIZE
R/W
0000
1
RONLY
R/W
0
0
PRIV
R/W
0
Bits 15-10: ADDRESS[15:10] – 6 Least Significant Bits of the Base Address.
The Base Address sets the 22 most significant bits of the memory address.
Bit 9: AW – Auto-wait-on-write. When this bit is set, any write operation on this
memory select takes two system cycles.
0 = Write operation is not supplemented with an additional cycle (Default)
1 = Write operation takes an additional cycle
Bits 7-4: BLOCK_SIZE – Configures the size of the memory
0000 = Memory select is disabled (Default)
0001 = 1K Bytes
0010 = 2K Bytes
0011 = 4K Bytes
0100 = 8K Bytes
0101 = 16K Bytes
0110 = 32K Bytes
0111 = 64K Bytes
1000 = 128K Bytes
1001 = 256K Bytes
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1010 = 512K Bytes
1011 = 1M Bytes
1100 = 2M Bytes
1101 = 4M Bytes
1110 = 8M Bytes
1111 = 16M Bytes
Bit 1: RONLY – Read-only protection. This bit sets read-only protection for the
memory selected by the memory select. An illegal access exception is generated
when a write is attempted to the memory.
0 = Read/write access to memory (Default)
1 = Read accesses to memory only
Bit 0: PRIV – Privilege mode protection. This bit sets privilege mode protection
for the memory Registration selected by the memory select. An illegal access
exception is generated on any access to memory protected by privilege mode.
0 = User/privilege mode accesses to memory (Default)
1 = Privilege mode accesses to memory only
4.15.5 Memory Fine Base Address High Register 4 (MFBAHR4)
Address FFFFFE20 – Memory Fine Base Address High Register 4
Bit Number
Bit Name
Access
Default
15:0
ADDRESS[31:16]
R/W
0000_0000_0001_0010
Bits 15-0: ADDRESS[31:16] – 16 Most Significant Bits of the Base Address.
The Base Address sets the 22 most significant bits of the memory address.
4.15.6 Memory Fine Base Address Low Register 4-16 (MFBALRx)
Address FFFFFE24 – Memory Fine Base Address Low Register 4
Address FFFFFE2C – Memory Fine Base Address Low Register 5
Address FFFFFE34 – Memory Fine Base Address Low Register 6
Address FFFFFE3C – Memory Fine Base Address Low Register 7
Address FFFFFE44 – Memory Fine Base Address Low Register 8
Address FFFFFE4C – Memory Fine Base Address Low Register 9
Address FFFFFE54 – Memory Fine Base Address Low Register 10
Address FFFFFE5C – Memory Fine Base Address Low Register 11
Address FFFFFE64 – Memory Fine Base Address Low Register 12
Address FFFFFE6C – Memory Fine Base Address Low Register 13
Address FFFFFE74 – Memory Fine Base Address Low Register 14
Address FFFFFE7C – Memory Fine Base Address Low Register 15
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Address FFFFFE84 – Memory Fine Base Address Low Register 16
Bit Number
Bit Name
Access
Default
15:10
ADDRESS[15:10]
R/W
000000
9
AW
R/W
0
8:2
RESERVED
0_0000_00
1
RONLY
R/W
0
0
PRIV
R/W
0
Bits 15-10: ADDRESS[15:10] – 6 Least Significant Bits of the Base Address.
The Base Address sets the 22 most significant bits of the memory address.
Bit 9: AW – Auto-wait-on-write. When this bit is set, any write operation on this
memory select takes two system cycles.
0 = Write operation is not supplemented with an additional cycle (Default)
1 = Write operation takes an additional cycle
Bits 8-2: RESERVED – Unused bits
Bit 1: RONLY – Read-only protection. This bit sets read-only protection for the
memory selected by the memory select. An illegal access exception is generated
when a write is attempted to the memory.
0 = Read/write access to memory (Default)
1 = Read accesses to memory only
Bit 0: PRIV – Privilege mode protection. This bit sets privilege mode protection
for the memory Registration selected by the memory select. An illegal access
exception is generated on any access to memory protected by privilege mode.
0 = User/privilege mode accesses to memory (Default)
1 = Privilege mode accesses to memory only
4.15.7 Memory Fine Base Address High Register 5 (MFBAHR5)
Address FFFFFE28 – Memory Fine Base Address High Register 5
Bit Number
Bit Name
Access
Default
15:0
ADDRESS[31:16]
R/W
0000_0000_0001_0011
Bits 15-0: ADDRESS[31:16] – 16 Most Significant Bits of the Base Address.
The Base Address sets the 22 most significant bits of the memory address.
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4.15.8 Memory Fine Base Address High Register 6 (MFBAHR6)
Address FFFFFE30 – Memory Fine Base Address High Register 6
Bit Number
Bit Name
Access
Default
15:0
ADDRESS[31:16]
R/W
0000_0000_0001_0100
Bits 15-0: ADDRESS[31:16] – 16 Most Significant Bits of the Base Address.
The Base Address sets the 22 most significant bits of the memory address.
4.15.9 Memory Fine Base Address High Register 7 (MFBAHR7)
Address FFFFFE38 – Memory Fine Base Address High Register 7
Bit Number
Bit Name
Access
Default
15:0
ADDRESS[31:16]
R/W
0000_0000_0001_0101
Bits 15-0: ADDRESS[31:16] – 16 Most Significant Bits of the Base Address.
The Base Address sets the 22 most significant bits of the memory address.
4.15.10
Memory Fine Base Address High Register 8 (MFBAHR8)
Address FFFFFE40 – Memory Fine Base Address High Register 8
Bit Number
Bit Name
Access
Default
15:0
ADDRESS[31:16]
R/W
0000_0000_0001_0110
Bits 15-0: ADDRESS[31:16] – 16 Most Significant Bits of the Base Address.
The Base Address sets the 22 most significant bits of the memory address.
4.15.11
Memory Fine Base Address High Register 9 (MFBAHR9)
Address FFFFFE48 – Memory Fine Base Address High Register 9
Bit Number
Bit Name
Access
Default
15:0
ADDRESS[31:16]
R/W
0000_0000_0001_0111
Bits 15-0: ADDRESS[31:16] – 16 Most Significant Bits of the Base Address.
The Base Address sets the 22 most significant bits of the memory address.
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4.15.12
Memory Fine Base Address High Register 10 (MFBAHR10)
Address FFFFFE50 – Memory Fine Base Address High Register 10
Bit Number
Bit Name
Access
Default
15:0
ADDRESS[31:16]
R/W
0000_0000_0001_1000
Bits 15-0: ADDRESS[31:16] – 16 Most Significant Bits of the Base Address.
The Base Address sets the 22 most significant bits of the memory address.
4.15.13
Memory Fine Base Address High Register 11 (MFBAHR11)
Address FFFFFE58 – Memory Fine Base Address High Register 11
Bit Number
Bit Name
Access
Default
15:0
ADDRESS[31:16]
R/W
0000_0000_0001_1001
Bits 15-0: ADDRESS[31:16] – 16 Most Significant Bits of the Base Address.
The Base Address sets the 22 most significant bits of the memory address.
4.15.14
Memory Fine Base Address High Register 12 (MFBAHR12)
Address FFFFFE60 – Memory Fine Base Address High Register 12
Bit Number
Bit Name
Access
Default
15:0
ADDRESS[31:16]
R/W
0000_0000_0001_1010
Bits 15-0: ADDRESS[31:16] – 16 Most Significant Bits of the Base Address.
The Base Address sets the 22 most significant bits of the memory address.
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4.15.15
Memory Fine Base Address High Register 13 (MFBAHR13)
Address FFFFFE68 – Memory Fine Base Address High Register 13
Bit Number
Bit Name
Access
Default
15:0
ADDRESS[31:16]
R/W
0000_0000_0001_1011
Bits 15-0: ADDRESS[31:16] – 16 Most Significant Bits of the Base Address.
The Base Address sets the 22 most significant bits of the memory address.
4.15.16
Memory Fine Base Address High Register 14 (MFBAHR14)
Address FFFFFE70 – Memory Fine Base Address High Register 14
Bit Number
Bit Name
Access
Default
15:0
ADDRESS[31:16]
R/W
0000_0000_0001_1100
Bits 15-0: ADDRESS[31:16] – 16 Most Significant Bits of the Base Address.
The Base Address sets the 22 most significant bits of the memory address.
4.15.17
Memory Fine Base Address High Register 15 (MFBAHR15)
Address FFFFFE78 – Memory Fine Base Address High Register 15
Bit Number
Bit Name
Access
Default
15:0
ADDRESS[31:16]
R/W
0000_0000_0001_1101
Bits 15-0: ADDRESS[31:16] – 16 Most Significant Bits of the Base Address.
The Base Address sets the 22 most significant bits of the memory address.
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4.15.18
Memory Fine Base Address High Register 16 (MFBAHR16)
Address FFFFFE80 – Memory Fine Base Address High Register 16
Bit Number
Bit Name
Access
Default
15:0
ADDRESS[31:16]
R/W
0000_0000_0001_1110
Bits 15-0: ADDRESS[31:16] – 16 Most Significant Bits of the Base Address.
The Base Address sets the 22 most significant bits of the memory address.
4.15.19
FFFFFE90
Bit
Number
Bit Name
Access
Default
Program Flash Block 1 Control Register (PFLASHCTRL1)
11
10
BUSY
R
-
RESERVED
0
9
8
7:5
PAGE_ERASE MASS_ERASE RESERVED PAGE_S
R/W
R/W
R/W
R/W
0
0
000
00000
Bit 11: BUSY – Program Flash Block 1Busy Indicator
0 = Program Flash available for read/write/erase access
1 = Program Flash unavailable for read/write/erase access
Bit 10: Reserved
Bit 9: PAGE_ERASE – Program Flash Block 1 Page Erase Enable
0 = No Page Erase initiated on Program Flash (Default)
1 = Page Erase on Program Flash enabled. Page erased is based on
PAGE_SEL (Bits 4-0). Interlock Key must be set in the Flash Interlock
Register (Section 4.15.21) before initiating a Page Erase cycle. This bit is
cleared upon completion of Page Erase cycle.
Bit 8: MASS_ERASE – Program Flash Block 1 Mass Erase Enable
0 = No Mass Erase initiated on Program Flash (Default)
1 = Mass Erase of Program Flash enabled. Interlock Key must be set in the
Flash Interlock Register (Section 4.15.21)before initiating a Mass Erase
cycle. This bit is cleared upon completion of Mass Erase cycle.
Bits 4-0: PAGE_SEL – Selects page to be erased during Page Erase Cycle
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4.15.20
Data Flash Control Register (DFLASHCTRL)
Address FFFFFE94
Bit
11
10
9
8
7:6
5:0
Number
RESERVED
PAGE_ERASE MASS_ERASE RESERVED PAGE_S
Bit Name BUSY
R
R/W
R/W
R/W
Access
0
0
0
00000
Default
Bit 11: BUSY – Data Flash Busy Indicator
0 = Data Flash available for read/write/erase access
1 = Data Flash unavailable for read/write/erase access
Bit 10: Reserved
Bit 9: PAGE_ERASE – Data Flash Page Erase Enable
0 = No Page Erase initiated on Data Flash (Default)
1 = Page Erase Cycle on Data Flash enabled. Page erased is based on
PAGE_SEL (Bits 4-0). These bits are cleared upon completion of Page
Erase cycle.
Bit 8: MASS_ERASE – Data Flash Mass Erase Enable
0 = No Mass Erase initiated on Data Flash (Default)
1 = Mass Erase of Data Flash enabled. Bit is cleared upon completion of
mass erase.
Bits 5-0: PAGE_SEL – Selects page to be erased during Page Erase Cycle
4.15.21
Flash Interlock Register (FLASHILOCK)
Address FFFFFE98
Bit Number
Bit Name
Access
Default
31:0
INTERLOCK_KEY
R/W
0000_0000_0000_0000_0000_0000_0000_0000
Bit 31-0: INTERLOCK_KEY – Flash Interlock Key. Register must be set to
0x42DC157E prior to every Program Flash#1 or Data Flash write, Mass Erase or
Page Erase or 0x6C97D0C5 prior to every Program Flash#2 write, Mass Erase or
Page Erase. If the Interlock Key is not set, the write/erase cycle to the Flash will
not initiate. This register will clear upon the completion of a write or erase cycle
to the Flash modules.
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4.15.22
Program Flash Block 2 Control Register (PFLASHCTRL2)
Address FFFFFE9C
Bit
11
10
9
8
7:5
4:0
Number
RESERVED
PAGE_ERASE MASS_ERASE RESERVED PAGE_S
Bit Name BUSY
R
R/W
R/W
R/W
R/W
Access
0
0
0
000
00000
Default
Bit 11: BUSY – Program Flash Block 2Busy Indicator
0 = Program Flash available for read/write/erase access
1 = Program Flash unavailable for read/write/erase access
Bit 10: Reserved
Bit 9: PAGE_ERASE – Program Flash Block 2 Page Erase Enable
0 = No Page Erase initiated on Program Flash (Default)
1 = Page Erase on Program Flash enabled. Page erased is based on
PAGE_SEL (Bits 4-0). Interlock Key must be set in the Flash Interlock
Register (Section 4.15.21) before initiating a Page Erase cycle. This bit is
cleared upon completion of Page Erase cycle.
Bit 8: MASS_ERASE – Program Flash Block 2 Mass Erase Enable
0 = No Mass Erase initiated on Program Flash (Default)
1 = Mass Erase of Program Flash enabled. Interlock Key must be set in the
Flash Interlock Register (Section 4.15.21) before initiating a Page Erase
cycle.. This bit is cleared upon completion of Mass Erase cycle.
Bits 4-0: PAGE_SEL – Selects page to be erased during Page Erase Cycle
4.16 CIM – Central Interrupt Module
CIM Registers have the following attributes:
- 32-bit wide
- Addresses placed on word boundaries
- Byte, half-word and word writes permitted
- All Registers have read/write access in any mode
- Interrupt Mask and FIQ/IRQ Program Control Registers are writeable in
privilege mode only. A write in user mode to these Registers causes a
peripheral illegal access exception.
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4.16.1 IRQ Index Offset Vector Register (IRQIVEC)
Address FFFFFF20
Bit Number
Bit Name
Access
Default
7:0
IRQIVEC
R
-
Bits 7-0: IRQIVEC – Index of the IRQ Pending Interrupt (Cleared upon read)
0 = No interrupt pending
1 = Pending interrupt on Channel 0
2 = Pending interrupt on Channel 1
N = Pending interrupt on Channel N-1, where N <= 31
4.16.2 FIQ Index Offset Vector Register (FIQIVEC)
Address FFFFFF24
Bit Number
Bit Name
Access
Default
7:0
FIQIVEC
R
-
Bits 7-0: FIQIVEC – Index of the FIQ pending interrupt (Cleared upon read)
0 = No interrupt pending
1 = Pending interrupt on Channel 0
2 = Pending interrupt on Channel 1
N = Pending interrupt on Channel N-1, where N <= 31.
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4.16.3 FIQ/IRQ Program Control Register (FIRQPR)
Address FFFFFF2C
A 32-bit FIQ/IRQ program control Register (FIRQPR) determines whether a given
interrupt request will be FIQ or IRQ type.
Bit
Number
Bit Name
Access
Default
Bit
Number
Bit Name
Access
Default
Bit
Number
Bit Name
Access
Default
Bit
Number
Bit Name
Access
Default
Bit
Number
Bit Name
Access
Default
Bit
Number
Bit Name
Access
Default
300
31
30
EXT_FAULT_INT
R/W
0
SYS_SSI_INT
R/W
0
29
28
27
26
25
DPWM0_INT
R/W
0
DPWM1_INT
R/W
0
DPWM2_INT
R/W
0
DPWM3_INT
R/W
0
FAULT_MUX_INT
R/W
0
24
23
22
21
20
ADC_INT
R/W
0
CPCC_INT
R/W
0
T24_OC0_INT
R/W
0
T24_CAP_INT
R/W
0
T24_OC1_INT
R/W
0
19
18
17
16
15
DTC_INT
R/W
0
T24_OVF
R/W
0
T16_PWM0_INT
R/W
0
T16_PWM1_INT
R/W
0
T16_PWM2_INT
R/W
0
14
13
12
11
10
T16_PWM3_INT
R/W
0
FE2_INT
R/W
0
FE1_INT
R/W
0
FE0_INT
R/W
0
DCOMP_I2C_SPI_INT
R/W
0
9
8
7
6
5
PMBUS_INT
R/W
0
UART1_TX_INT
R/W
0
UART1_RX_INT
R/W
0
UART0_TX_INT
R/W
0
UART0_RX_INT
R/W
0
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Bit
Number
Bit Name
Access
Default
4
3
2
1
0
UART_0_1_ERR_INT
R/W
0
WD_WAKE_INT
R/W
0
WD_FULL_INT
R/W
0
EXT_INT
R/W
0
BROWNOUT_INT
R/W
0
Bit 0: BROWMOUT_INT – Brownout Interrupt Request
0 = Interrupt request is of IRQ type (Default)
1 = Interrupt request is of FIQ type
Bit 1: EXT_INT – External Interrupt Request
0 = Interrupt request is of IRQ type (Default)
1 = Interrupt request is of FIQ type
Bit 2: WD_FULL_INT – Watchdog Max Count Reached Interrupt Request
0 = Interrupt request is of IRQ type (Default)
1 = Interrupt request is of FIQ type
Bit 3: WD_WAKE_INT – Watchdog Half Count Reached Interrupt Request
0 = Interrupt request is of IRQ type (Default)
1 = Interrupt request is of FIQ type
Bit 4: UART_0_1_ERR_INT – UART0/1 ERR Interrupt Request
0 = Interrupt request is of IRQ type (Default)
1 = Interrupt request is of FIQ type
Bit 5: UART0_RX_INT – UART0 RX Interrupt Request
0 = Interrupt request is of IRQ type (Default)
1 = Interrupt request is of FIQ type
Bit 6: UART0_TX_INT – UART0 TX Interrupt Request
0 = Interrupt request is of IRQ type (Default)
1 = Interrupt request is of FIQ type
Bit 7: UART1_RX_INT – UART1 RX Interrupt Request
0 = Interrupt request is of IRQ type (Default)
1 = Interrupt request is of FIQ type
Bit 8: UART1_TX_INT – UART1 TX Interrupt Request
0 = Interrupt request is of IRQ type (Default)
1 = Interrupt request is of FIQ type
Bit 9: PMBUS_INT – PMBus Interrupt Request
0 = Interrupt request is of IRQ type (Default)
1 = Interrupt request is of FIQ type
Bit 10: DCOMP_I2C_SPI_INT – Digital Comparator/I2C/SPI Interrupt Request
0 = Interrupt request is of IRQ type (Default)
1 = Interrupt request is of FIQ type
Bit 11: FE0_INT – Front End 0 Interrupt Request
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0 = Interrupt request is of IRQ type (Default)
1 = Interrupt request is of FIQ type
Bit 12: FE1_INT – Front End 1 Interrupt Request
0 = Interrupt request is of IRQ type (Default)
1 = Interrupt request is of FIQ type
Bit 13: FE2_INT – Front End 2 Interrupt Request
0 = Interrupt request is of IRQ type (Default)
1 = Interrupt request is of FIQ type
Bit 14: T16_PWM3_INT – 16-bit Timer 3 PWM Interrupt Request
0 = Interrupt request is of IRQ type (Default)
1 = Interrupt request is of FIQ type
Bit 15: T16_PWM2_INT – 16-bit Timer 2 PWM Interrupt Request
0 = Interrupt request is of IRQ type (Default)
1 = Interrupt request is of FIQ type
Bit 16: T16_PWM1_INT – 16-bit Timer 1 PWM Interrupt Request
0 = Interrupt request is of IRQ type (Default)
1 = Interrupt request is of FIQ type
Bit 17: T16_PWM0_INT – 16-bit Timer 0 PWM Interrupt Request
0 = Interrupt request is of IRQ type (Default)
1 = Interrupt request is of FIQ type
Bit 18: T24_OVF_INT – 24-bit Timer Overflow Interrupt Request
0 = Interrupt request is of IRQ type (Default)
1 = Interrupt request is of FIQ type
Bit 19: DTC_INT – DTC Interrupt Request
0 = Interrupt request is of IRQ type (Default)
1 = Interrupt request is of FIQ type
Bit 20: T24_OC1_INT – 24-bit Output Compare 1 Interrupt Request
0 = Interrupt request is of IRQ type (Default)
1 = Interrupt request is of FIQ type
Bit 21: T24_CAP_INT – 24-bit Timer Capture Interrupt Request
0 = Interrupt request is of IRQ type (Default)
1 = Interrupt request is of FIQ type
Bit 22: T24_OC0_INT – 24-bit Output Compare 0 Interrupt Request
0 = Interrupt request is of IRQ type (Default)
1 = Interrupt request is of FIQ type
Bit 23: CPCC_INT – CPCC Interrupt Request
0 = Interrupt request is of IRQ type (Default)
1 = Interrupt request is of FIQ type
Bit 24: ADC_INT – ADC12 Interrupt Request
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0 = Interrupt request is of IRQ type (Default)
1 = Interrupt request is of FIQ type
Bit 25: FAULT_MUX_INT – Fault Mux Interrupt Request
0 = Interrupt request is of IRQ type (Default)
1 = Interrupt request is of FIQ type
Bit 26: DPWM3_INT – DPWM3 Interrupt Request
0 = Interrupt request is of IRQ type (Default)
1 = Interrupt request is of FIQ type
Bit 27: DPWM2_INT – DPWM2 Interrupt Request
0 = Interrupt request is of IRQ type (Default)
1 = Interrupt request is of FIQ type
Bit 28: DPWM1_INT – DPWM1 Interrupt Request
0 = Interrupt request is of IRQ type (Default)
1 = Interrupt request is of FIQ type
Bit 29: DPWM0_INT – DPWM0 Interrupt Request
0 = Interrupt request is of IRQ type (Default)
1 = Interrupt request is of FIQ type
Bit 30: EXT_FAULT_INT – External Fault Interrupt Request
0 = Interrupt request is of IRQ type (Default)
1 = Interrupt request is of FIQ type
Bit 31: SYS_SSI_INT – SYS SSI Interrupt Request
0 = Interrupt request is of IRQ type (Default)
1 = Interrupt request is of FIQ type
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4.16.4 Pending Interrupt Read Location Register (INTREQ)
Address FFFFFF30
Bit
Number
Bit Name
Access
Default
Bit
Number
Bit Name
Access
Default
Bit
Number
Bit Name
Access
Default
Bit
Number
Bit Name
Access
Default
Bit
Number
Bit Name
Access
Default
Bit
Number
Bit Name
Access
Default
Bit
Number
304
31
30
EXT_FAULT_INT
R
-
SYS_SSI_INT
R
-
29
28
27
26
25
DPWM0_INT
R
-
DPWM1_INT
R
-
DPWM2_INT
R
-
DPWM3_INT
R
-
FAULT_MUX_INT
R
-
24
23
22
21
20
ADC_INT
R
-
CPCC_INT
R
-
T24_OC0_INT
R
-
T24_CAP_INT
R
-
T24_OC1_INT
R
-
19
18
17
16
15
DTC_INT
R
-
T24_OVF
R
-
T16_PWM0_INT
R
-
T16_PWM1_INT
R
-
T16_PWM2_INT
R
-
14
13
12
11
10
T16_PWM3_INT
R
-
FE2_INT
R
-
FE1_INT
R
-
FE0_INT
R
-
DCOMP_I2C_SPI_INT
R
-
9
8
7
6
5
PMBUS_INT
R
-
UART1_TX_INT
R
-
UART1_RX_INT
R
-
UART0_TX_INT
R
-
UART0_RX_INT
R
-
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2
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0
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Bit Name
Access
Default
UART_0_1_ERR_INT
R
-
WD_WAKE_INT
R
-
WD_FULL_INT
R
-
EXT_INT
R
-
BROWNOUT_INT
R
-
Bit 0: BROWMOUT_INT – Brownout Interrupt Request
0 = No interrupt has occurred
1 = Interrupt is pending
Bit 1: EXT_INT – External Interrupt Request
0 = No interrupt has occurred
1 = Interrupt is pending
Bit 2: WD_FULL_INT – Watchdog Max Count Reached Interrupt Request
0 = No interrupt has occurred
1 = Interrupt is pending
Bit 3: WD_WAKE_INT – Watchdog Half Count Reached Interrupt Request
0 = No interrupt has occurred
1 = Interrupt is pending
Bit 4: UART_0_1_ERR_INT – UART0/1 ERR Interrupt Request
0 = No interrupt has occurred
1 = Interrupt is pending
Bit 5: UART0_RX_INT – UART0 RX Interrupt Request
0 = No interrupt has occurred
1 = Interrupt is pending
Bit 6: UART0_TX_INT – UART0 TX Interrupt Request
0 = No interrupt has occurred
1 = Interrupt is pending
Bit 7: UART1_RX_INT – UART1 RX Interrupt Request
0 = No interrupt has occurred
1 = Interrupt is pending
Bit 8: UART1_TX_INT – UART1 TX Interrupt Request
0 = No interrupt has occurred
1 = Interrupt is pending
Bit 9: PMBUS_INT – PMBus Interrupt Request
0 = No interrupt has occurred
1 = Interrupt is pending
Bit 10: DCOMP_I2C_SPI_INT – Digital Comparator/I2C/SPI Interrupt Request
0 = No interrupt has occurred
1 = Interrupt is pending
Bit 11: FE0_INT – Front End 0 Interrupt Request
0 = No interrupt has occurred
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1 = Interrupt is pending
Bit 12: FE1_INT – Front End 1 Interrupt Request
0 = No interrupt has occurred
1 = Interrupt is pending
Bit 13: FE2_INT – Front End 2 Interrupt Request
0 = No interrupt has occurred
1 = Interrupt is pending
Bit 14: T16_PWM3_INT – 16-bit Timer 3 PWM Interrupt Request
0 = No interrupt has occurred
1 = Interrupt is pending
Bit 15: T16_PWM2_INT – 16-bit Timer 2 PWM Interrupt Request
0 = No interrupt has occurred
1 = Interrupt is pending
Bit 16: T16_PWM1_INT – 16-bit Timer 1 PWM Interrupt Request
0 = No interrupt has occurred
1 = Interrupt is pending
Bit 17: T16_PWM0_INT – 16-bit Timer 0 PWM Interrupt Request
0 = No interrupt has occurred
1 = Interrupt is pending
Bit 18: T24_OVF_INT – 24-bit Timer Overflow Interrupt Request
0 = No interrupt has occurred
1 = Interrupt is pending
Bit 19: DTC_INT – DTC Interrupt Request
0 = No interrupt has occurred
1 = Interrupt is pending
Bit 20: T24_OC1_INT – 24-bit Output Compare 1 Interrupt Request
0 = No interrupt has occurred
1 = Interrupt is pending
Bit 21: T24_CAP_INT – 24-bit Timer Capture Interrupt Request
0 = No interrupt has occurred
1 = Interrupt is pending
Bit 22: T24_OC0_INT – 24-bit Output Compare 0 Interrupt Request
0 = No interrupt has occurred
1 = Interrupt is pending
Bit 23: CPCC_INT – CPCC Interrupt Request
0 = No interrupt has occurred
1 = Interrupt is pending
Bit 24: ADC_INT – ADC12 Interrupt Request
0 = No interrupt has occurred
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1 = Interrupt is pending
Bit 25: FAULT_MUX_INT – Fault Mux Interrupt Request
0 = No interrupt has occurred
1 = Interrupt is pending
Bit 26: DPWM3_INT – DPWM3 Interrupt Request
0 = No interrupt has occurred
1 = Interrupt is pending
Bit 27: DPWM2_INT – DPWM2 Interrupt Request
0 = No interrupt has occurred
1 = Interrupt is pending
Bit 28: DPWM1_INT – DPWM1 Interrupt Request
0 = No interrupt has occurred
1 = Interrupt is pending
Bit 29: DPWM0_INT – DPWM0 Interrupt Request
0 = No interrupt has occurred
1 = Interrupt is pending
Bit 30: EXT_FAULT_INT – External Fault Interrupt Request
0 = No interrupt has occurred
1 = Interrupt is pending
Bit 31: SYS_SSI_INT – SYS SSI Interrupt Request
0 = No interrupt has occurred
1 = Interrupt is pending
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4.16.5 Interrupt Mask Register (REQMASK)
Address FFFFFF34
Bit
Number
Bit Name
Access
Default
Bit
Number
Bit Name
Access
Default
Bit
Number
Bit Name
Access
Default
Bit
Number
Bit Name
Access
Default
Bit
Number
Bit Name
Access
Default
Bit
Number
Bit Name
Access
Default
Bit
Number
308
31
30
EXT_FAULT_INT
R/W
0
SYS_SSI_INT
R/W
0
29
28
27
26
25
DPWM0_INT
R/W
0
DPWM1_INT
R/W
0
DPWM2_INT
R/W
0
DPWM3_INT
R/W
0
FAULT_MUX_INT
R/W
0
24
23
22
21
20
ADC_INT
R/W
0
CPCC_INT
R/W
0
T24_OC0_INT
R/W
0
T24_CAP_INT
R/W
0
T24_OC1_INT
R/W
0
19
18
17
16
15
DTC_INT
R/W
0
T24_OVF
R/W
0
T16_PWM0_INT
R/W
0
T16_PWM1_INT
R/W
0
T16_PWM2_INT
R/W
0
14
13
12
11
10
T16_PWM3_INT
R/W
0
FE2_INT
R/W
0
FE1_INT
R/W
0
FE0_INT
R/W
0
DCOMP_I2C_SPI_INT
R/W
0
9
8
7
6
5
PMBUS_INT
R/W
0
UART1_TX_INT
R/W
0
UART1_RX_INT
R/W
0
UART0_TX_INT
R/W
0
UART0_RX_INT
R/W
0
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2
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0
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Bit Name
Access
Default
UART_0_1_ERR_INT
R/W
0
WD_WAKE_INT
R/W
0
WD_FULL_INT
R/W
0
EXT_INT
R/W
0
BROWNOUT_INT
R/W
0
Bit 0: BROWMOUT_INT – Brownout Interrupt Mask Select
0 = Interrupt request channel is disabled (Default)
1 = Interrupt request channel is enabled
Bit 1: EXT_INT – External Interrupt Request
0 = Interrupt request channel is disabled (Default)
1 = Interrupt request channel is enabled
Bit 2: WD_FULL_INT – Watchdog Max Count Reached Interrupt Mask Select
0 = Interrupt request channel is disabled (Default)
1 = Interrupt request channel is enabled
Bit 3: WD_WAKE_INT – Watchdog Half Count Reached Interrupt Mask Select
0 = Interrupt request channel is disabled (Default)
1 = Interrupt request channel is enabled
Bit 4: UART_0_1_ERR_INT – UART0/1 ERR Interrupt Mask Select
0 = Interrupt request channel is disabled (Default)
1 = Interrupt request channel is enabled
Bit 5: UART0_RX_INT – UART0 RX Interrupt Mask Select
0 = Interrupt request channel is disabled (Default)
1 = Interrupt request channel is enabled
Bit 6: UART0_TX_INT – UART0 TX Interrupt Mask Select
0 = Interrupt request channel is disabled (Default)
1 = Interrupt request channel is enabled
Bit 7: UART1_RX_INT – UART1 RX Interrupt Mask Select
0 = Interrupt request channel is disabled (Default)
1 = Interrupt request channel is enabled
Bit 8: UART1_TX_INT – UART1 TX Interrupt Mask Select
0 = Interrupt request channel is disabled (Default)
1 = Interrupt request channel is enabled
Bit 9: PMBUS_INT – PMBus Interrupt Mask Select
0 = Interrupt request channel is disabled (Default)
1 = Interrupt request channel is enabled
Bit 10: DCOMP_I2C_SPI_INT – Digital Comparator/I2C/SPI Interrupt Mask
Select
0 = Interrupt request channel is disabled (Default)
1 = Interrupt request channel is enabled
Bit 11: FE0_INT – Front End 0 Interrupt Mask Select
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0 = Interrupt request channel is disabled (Default)
1 = Interrupt request channel is enabled
Bit 12: FE1_INT – Front End 1 Interrupt Mask Select
0 = Interrupt request channel is disabled (Default)
1 = Interrupt request channel is enabled
Bit 13: FE2_INT – Front End 2 Interrupt Mask Select
0 = Interrupt request channel is disabled (Default)
1 = Interrupt request channel is enabled
Bit 14: T16_PWM3_INT – 16-bit Timer 3 PWM Interrupt Mask Select
0 = Interrupt request channel is disabled (Default)
1 = Interrupt request channel is enabled
Bit 15: T16_PWM2_INT – 16-bit Timer 2 PWM Interrupt Mask Select
0 = Interrupt request channel is disabled (Default)
1 = Interrupt request channel is enabled
Bit 16: T16_PWM1_INT – 16-bit Timer 1 PWM Interrupt Mask Select
0 = Interrupt request channel is disabled (Default)
1 = Interrupt request channel is enabled
Bit 17: T16_PWM0_INT – 16-bit Timer 0 PWM Interrupt Mask Select
0 = Interrupt request channel is disabled (Default)
1 = Interrupt request channel is enabled
Bit 18: T24_OVF_INT – 24-bit Timer Overflow Interrupt Mask Select
0 = Interrupt request channel is disabled (Default)
1 = Interrupt request channel is enabled
Bit 19: DTC_INT – DTC Interrupt Mask Select
0 = Interrupt request channel is disabled (Default)
1 = Interrupt request channel is enabled
Bit 20: T24_OC1_INT – 24-bit Output Compare 1 Interrupt Mask Select
0 = Interrupt request channel is disabled (Default)
1 = Interrupt request channel is enabled
Bit 21: T24_CAP_INT – 24-bit Timer Capture Interrupt Mask Select
0 = Interrupt request channel is disabled (Default)
1 = Interrupt request channel is enabled
Bit 22: T24_OC0_INT – 24-bit Output Compare 0 Interrupt Mask Select
0 = Interrupt request channel is disabled (Default)
1 = Interrupt request channel is enabled
Bit 23: CPCC_INT – CPCC Interrupt Mask Select
0 = Interrupt request channel is disabled (Default)
1 = Interrupt request channel is enabled
Bit 24: ADC_INT – ADC12 Interrupt Mask Select
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0 = Interrupt request channel is disabled (Default)
1 = Interrupt request channel is enabled
Bit 25: FAULT_MUX_INT – Fault Mux Interrupt Mask Select
0 = Interrupt request channel is disabled (Default)
1 = Interrupt request channel is enabled
Bit 26: DPWM3_INT – DPWM3 Interrupt Mask Select
0 = Interrupt request channel is disabled (Default)
1 = Interrupt request channel is enabled
Bit 27: DPWM2_INT – DPWM2 Interrupt Mask Select
0 = Interrupt request channel is disabled (Default)
1 = Interrupt request channel is enabled
Bit 28: DPWM1_INT – DPWM1 Interrupt Mask Select
0 = Interrupt request channel is disabled (Default)
1 = Interrupt request channel is enabled
Bit 29: DPWM0_INT – DPWM0 Interrupt Mask Select
0 = Interrupt request channel is disabled (Default)
1 = Interrupt request channel is enabled
Bit 30: EXT_FAULT_INT – External Fault Interrupt Mask Select
0 = Interrupt request channel is disabled (Default)
1 = Interrupt request channel is enabled
Bit 31: SYS_SSI_INT – SYS SSI Interrupt Mask Select
0 = Interrupt request channel is disabled (Default)
1 = Interrupt request channel is enabled
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4.17 SYS – System Module
SYS Registers have the following attributes:
- Addresses placed on word boundaries
- Byte, half-word and word writes permitted
- All Registers can be read in any mode of operation.
- Global Control Register is writeable in privilege mode only. All other
Registers are writeable in any mode.
4.17.1 Clock Control Register (CLKCNTL)
Address FFFFFFD0
The clock control Register configures the MCLK divider for low power modes and the
clock multiplexer which drives the Sync pin when configured to output the CLKOUT
signal. CLKCNTRL is accessible in user and privilege mode and supports byte, halfword and word accesses. Any access to this Register takes two SYSCLK cycles.
Bit Number
Bit Name
Access
Default
9:8
M_DIV_RATIO
R/W
00
7
RESERVED
0
6:5
CLKSR
R/W
00
4
RESERVED
0
3
CLKDOUT
R/W
0
2:0
RESERVED
000
Bits 9-8: M_DIV_RATIO – MCLK (Processor Clock) Divide Ratio
00 = MCLK frequency equals High Frequency Oscillator divided by 8
(Default)
01 = MCLK frequency equals High Frequency Oscillator divided by 16
10 = MCLK frequency equals High Frequency Oscillator divided by 32
11 = MCLK frequency equals High Frequency Oscillator divided by 64
Bit 7: RESERVED
Bit 6-5: CLKSR – These bits control the source/function of CLKOUT
00 = Driven by value in CLKDOUT (Bit 3) (Default)
01 = Driven by the interface clock (ICLK)
10 = Driven by the CPU clock (MCLK)
11 = Driven by the system clock (SYSCLK)
Bit 4: RESERVED – Unused bit
Bit 3: CLKDOUT – This pin represents the output value of CLKOUT
0 = CLKOUT driven to logic low in output mode (Default)
1 = CLKOUT driven to logic high in output mode
Bits 2-0: RESERVED
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4.17.2 System Exception Control Register (SYSECR)
Address FFFFFFE0
The system exception control Register contains bits that allow the user to generate a
software reset. The OVR bits disable some reset/abort conditions when TRST is high.
Bit Number
Bit Name
Access
Default
15:14
RESET
R/W
01
13:3
RESERVED
-
2
PACCOVR
R/W
0
1
ACCOVR
R/W
0
0
ILLOVR
R/W
0
Bits 15-14: RESET – Software Reset Enable. These bits always read as 01
01 = No reset
1X = Global system reset (X = don’t care)
X0 = Global system reset (X = don’t care)
Bits 13-3: RESERVED
Bit 2: PACCOVR – Peripheral Access Violation Override
0 = Peripheral access violation error causes a reset or abort (Default)
1 = No action taken on a peripheral access violation
Bit 1: ACCOVR – Memory Access Reset Override
0 = Memory access violation error causes a reset or abort (Default)
.
1 = No action taken on an illegal address
Bit 0: ILLOVR – Illegal Address Reset Override
0 = Illegal address causes a reset or abort (Default)
1 = No action taken on an illegal address
4.17.3 System Exception Status Register (SYSESR)
Address FFFFFFE4
The System Exception Status Register contains flags for different reset/abort sources. On
power-up, all bits are cleared to 0. When a reset condition is recognized, the appropriate
bit in the Register is set and the value of the bit is maintained through the reset. When a
new reset condition occurs, the current contents of this Register are not cleared. The
contents of this Register are cleared on a power-on reset or by software.
Bit Number
Bit Name
Access
15
PORRST
R/W
14
CLKRST
R/W
13
WDRST
R/W
12
ILLMODE
R/W
11
ILLADR
R/W
10
ILLACC
R/W
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Default
Bit Number
Bit Name
Access
Default
0
9
PILLACC
R/W
0
0
8
ILLMAP
R/W
0
0
0
7
SWRST
R/W
0
0
0
6:0
RESERVED
000_0000
Bit 15: PORRST – Power-On reset flag. Set when power-on reset is asserted.
Reset is asserted as long as power-on-reset is active. Whenever a device is
powered, this bit is set.
User and privilege modes (read)
0 = Power-up reset has not occurred since the last clear
1 = Power-up reset has occurred since the last clear
User and privilege modes (write)
0 = Clears the corresponding bit to 0
1 = No effect
Bit 14: CLKRST – This bit represents the clock fail flag. This bit indicates a
clock fault condition has occurred. After power-on-reset, the CLKRST is reset to
0. Value remains unchanged during other resets.
User and privilege modes (read)
0 = Clock failure has not occurred since the last clear
1 = Clock failure has occurred since the last clear
User and privilege modes (write)
0 = Clears the corresponding bit to 0
1 = No effect
Bit 13: WDRST – This bit represents the watchdog reset flag. This bit indicates
that the last reset was caused by the watchdog.
User and privilege modes (read)
0 = Watchdog reset has not occurred since the last clear
1 = Watchdog reset has occurred since the last clear
User and privilege modes (write)
0 = Clears the corresponding bit to 0
1 = No effect
Bit 12: ILLMODE – This bit represents the illegal mode flag. This bit is set
when the mode bits in the program status Register are set to an illegal value.
User and privilege modes (read)
0 = Illegal mode has not occurred since the last clear
1 = Illegal mode has occurred since the last clear
User and privilege modes (write)
0 = Clears the corresponding bit to 0
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1 = No effect
Bit 11: ILLADR – This bit represents the illegal address access flag. This bit is
set when an access to an unimplemented location in the memory map is detected
in non-user mode.
User and privilege modes (read)
0 = Illegal address has not occurred since the last clear
1 = Illegal address has occurred since the last clear
User and privilege modes (write)
0 = Clears the corresponding bit to 0
1 = No effect
Bit 10: ILLACC – This bit represents the illegal memory access flag. This bit is
set when an access to a protected location without permission rights is detected in
non-user mode.
User and privilege modes (read)
0 = Illegal memory access has not occurred since the last clear
1 = Illegal memory access has occurred since the last clear
User and privilege modes (write)
0 = Clears the corresponding bit to 0
1 = No effect
Bit 9: PILLACC – This bit represents the peripheral illegal access flag. This bit
is set when a peripheral access violation is detected in user mode.
User and privilege modes (read)
0 = Illegal peripheral access has not occurred since the last clear
1 = Illegal peripheral access has occurred since the last clear
User and privilege modes (write)
0 = Clears the corresponding bit to 0
1 = No effect
Bit 8: ILLMAP – This bit represents the illegal address map flag. This bit is set
when the base addresses of one or more memories overlap. Reset occurs when the
overlapped registration is accessed.
User and privilege modes (read)
0 = Illegal address mapping has not occurred since the last clear
1 = Illegal address mapping has occurred since the last clear
User and privilege modes (write)
0 = Clears the corresponding bit to 0
1 = No effect
Bit 7: SWRST – This bit represents the software reset flag. This bit is set when
the last reset is caused by software writing the RESET bits.
User and privilege modes (read)
0 = Software reset has not occurred since the last clear
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1 = Software reset has occurred since the last clear
User and privilege modes (write)
0 = Clears the corresponding bit to 0
1 = No effect
Bit 6-0: RESERVED
4.17.4 Abort Exception Status Register (ABRTESR)
Address FFFFFFE8
The Abort Exception Status Register shows the abort cause.
Bit Number
Bit Name
Access
Default
15
ADRABT
R/W
0
14
MEMABT
R/W
0
13
PACCVIO
R/W
0
12:0
RESERVED
0_0000_0000_0000
Bit 15: ADRABT – This bit represents the illegal address abort. An illegal
address access was detected in user mode. An abort was generated due to an
illegal address access from either the MPU or system
User and privilege modes (read)
0 = No illegal address
1 = Abort caused by an illegal address
User and privilege modes (write)
0 = Clears bit to 0
1 = No effect
Bit 14: MEMABT – This bit represents the memory access abort. This bit
indicates an illegal memory access was detected in user mode. An abort was
generated due to the illegal memory access from either the MPU or system.
User and privilege modes (read)
0 = No illegal memory access
1 = Abort caused by an illegal memory access
User and privilege modes (write)
0 = Clears bit to 0
1 = No effect
Bit 13: PACCVIO – This bit represents the peripheral access violation error.
This bit indicates a peripheral access violation error was detected during a
peripheral Register access in user mode. An abort was generated due to a
peripheral access violation.
User and privilege modes (read)
0 = No peripheral access violation
1 = Abort caused by a peripheral access violation
User and privilege modes (write)
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0 = Clears bit to 0
1 = No effect
Bit 12-0: RESERVED – Unused bits
4.17.5 Global Status Register (GLBSTAT)
Address FFFFFFEC
The Global Status Register specifies the module that triggered the illegal address, illegal
access, abort or reset. When a new reset condition reset occurs, the current contents of
this Register are not cleared. The contents of this Register are cleared on a power-on reset
or by software.
Bit Number
Bit Name
Access
Default
7
SYSADDR
R/W
0
6
SYSACC
R/W
0
5:0
RESERVED
0000
Bit 7: SYSADDR – This bit represents the system illegal address flag. This bit is
set when the system detects an illegal address.
User and privilege modes (read)
0 = No system illegal address
1 = Abort or reset caused by a system illegal address
User and privilege modes (write)
0 = Clears bit to 0
1 = No effect
Bit 6: SYSACC – This bit represents the system illegal access flag. This bit is set
when the system detects an illegal access.
User and privilege modes (read)
0 = No system illegal access
1 = Abort or reset caused by a system illegal access
User and privilege modes (write)
0 = Clears bit to 0
1 = No effect
Bit 5-0: RESERVED
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4.17.6 Device Identification Register (DEV)
Address FFFFFFF0
The Device Identification Register contains device specification information that is hard
coded during device manufacturing. This register is read-only.
Bit Number
Bit Name
Access
Default
15:0
DEV
R
1001_0100_0111_1111
Bits 15-0: DEV – These bits represent the device identification code.
4.17.7 System Software Interrupt Flag Register (SSIF)
Address FFFFFFF8
The System Software Interrupt Flag Register is set when a software interrupt is triggered.
The flag allows the user to poll for a software interrupt.
Bit Number
Bit Name
Access
Default
0
SSIFLAG
R/W
0
Bit 0: SSIFLAG – This bit represents the system software interrupt flag. This bit
is set when a correct SSKEY is written to the System Software Interrupt Flag
Register. This bit is cleared only by software.
User and privilege modes (read)
0 = No IRQ/FIQ interrupt request has been generated since the last clear
1 = IRQ/FIQ interrupt request has been generated since the last clear
User and privilege modes (write)
0 = Clears bit to 0
1 = No effect
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4.17.8 System Software Interrupt Request Register (SSIR)
Address FFFFFFFC
The System Software Interrupt Request Register contains a key sequence that triggers a
software interrupt request to the CIM. Also, the Register contains an 8-bit data field.
Bit Number
Bit Name
Access
Default
15:8
SSKEY
R/W
0000_0000
7:0
SSDATA
R/W
0000_0000
Bits 15-8: SSKEY – These bits represent the system software interrupt request
key. These write-only bits are executable in both user and privilege modes. A
0x75 written to these bits initiates IRQ/FIQ interrupts. Data in this field is always
read as zero.
Bits 7-0: SSDATA – These bits represent the system software interrupt data. The
SSDATA bits provide an 8-bit field that can be used for passing messages into the
system software interrupt.
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