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Texas Instruments Inverted SEPIC Made SIMPLE Application notes
Application Report
SNVA743 – August 2015
Inverted SEPIC made SIMPLE
Akshay Mehta, Frank De Stasi
ABSTRACT
There can be quite a few applications that require a conversion from a negative input voltage to a negative
output voltage and there are a few ways to go about doing it. The telecom industry is one such example
where the rails are usually negative. This design space along with being limited is not well explored. In this
application note we will go over the use of an integrated boost regulator in the inverted SEPIC topology to
convert a negative input voltage to a negative output voltage.
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Contents
Introduction ...................................................................................................................
Application Details ...........................................................................................................
Test Results ..................................................................................................................
Conclusion ....................................................................................................................
References ...................................................................................................................
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2
5
8
8
List of Figures
1
-5VIN -12VOUT 300mA IOUT .................................................................................................... 2
2
Design Schematic
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4
5
6
7
8
...........................................................................................................
Line Regulation, IOUT = 400mA .............................................................................................
Efficiency Vs. IOUT, VOUT = -12V .............................................................................................
Load Regulation, VIN = -12V ................................................................................................
Maximum Output Current Vs. Input Voltage .............................................................................
Load Transient VIN = -12V, VOUT = -12V, IOUT = 200mA to 1A ..........................................................
Startup VIN = -12V, VOUT = -12V, IOUT = 500mA ...........................................................................
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5
5
6
6
7
7
List of Tables
1
1
Design BOM .................................................................................................................. 8
Introduction
The LM2586 is part of the LM258x family of SIMPLE SWITCHER® boost regulators from Texas
Instruments. The internal NPN is capable of handling a voltage of 65V and has a current limit of 4A. The
maximum input voltage that the device can handle is 40V. Thus this device makes a good candidate for
wide VIN solutions. The design shown here is created for a typical input of -5V and output of -12V at 1A
load current, with a common ground between input and output. But it can handle an input voltage range of
-5V to -24V. The following sections will talk about the operation.
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Application Details
2
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Application Details
The basic operation of this circuit is that of an inverted SEPIC topology. The inverted SEPIC is usually
used with devices that have a high side switch (e.g. a buck switcher) because it lets a user design for an
output voltage that can be higher or lower than the input voltage. The switching device in this topology
needs to be able to withstand a voltage of +VIN and –VOUT with respect to ground which limits the use of
most DC/DC integrated buck regulators. But since we are working with negative rails, we can use a device
with a low side switch such as the LM2586 in the inverted SEPIC topology and reference the device
ground to –VIN.
When the NPN is turned on, there are two current paths. One path is from ground, through primary
inductor L1, the internal NPN, -VIN rail and the input capacitor. The second current path is from ground, the
output capacitor, secondary inductor, the coupling capacitor, internal NPN, –VIN rail and the input
capacitor. During the on time the switch node is at a voltage of –VIN with respect to ground and the voltage
at the other end of the coupling capacitor is –VIN-VOUT with respect to ground. Therefore the coupling
capacitor is now charging up to VOUT. When the NPN is turned off, the voltages across the two inductors
are reversed and the current through them starts ramping down. During the off time the diode, D1, is
forward biased. There are two current paths during the off time as well. The first path is from -VOUT,
secondary inductor L2, diode D1, and output capacitor. The second current path is from ground, primary
inductor L1, coupling capacitor, diode D1 and output capacitor. The switch voltage during the off time is
+VOUT with respect to ground and the voltage on the other side of the coupling capacitor is a diode drop
above ground. Therefore the device chosen has to be able to sustain a total voltage of VIN+VOUT across it.
The distinct advantage of this topology is that the output sees constant current like that in the buck
topology. This makes the output ripple much cleaner and smaller. Figure 1 shows the steady state
waveform with the secondary inductor current, switch voltage and the output voltage ripple. While Figure 2
shows the design schematic. Reference 1 talks about the actual design equations and component
selection.
SW
20V/div
VOUT
50mV/div
IL2
500mA/div
IL1
500mA/div
2µs/div
Figure 1. -5VIN -12VOUT 300mA IOUT
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Application Details
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Figure 2. Design Schematic
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Application Details
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In this design, the ground of the IC is referenced to the negative input voltage. A current mirror is used to
set the feedback current and consequently the regulated output voltage. Use of an ordinary two transistor
current mirror would cause the output to have a dependency on the VBE of the transistor. In order to
remove that dependency a third transistor, Q3, and resistor RFBE2, are connected as shown in the design
schematic. From the schematic we can see that the voltage at the upper feedback resistor will be two
diode drops below ground, i.e. –2VBE. The lower feedback resistor is chosen such that there is 1mA of
current flowing through it. Therefore we get,
VREF
RFBB
0.001
(1)
The reference voltage VREF for the LM2586 is 1.2V. Therefore RFBB is set to be 1.2kΩ. An additional
resistor, RFBE2 is connected between ground and the common base of the two transistors. This resistor
helps pull more current from ground to FB and that current gets added to the current flowing through the
upper feedback resistor. This current can be realized as
VBE
IRBE 2
RBE 2
(2)
Without this resistor, RFBE2, the current flowing through the upper feedback resistor would be
VOUT 2 ˜ VBE
IRFBT
RFBT
(3)
With the addition of this resistor, this current is now re-written as
VOUT 2 ˜ VBE
V
IRFBT
BE
RFBT
RFBE2
(4)
From Equation 4 we can observe that the value of RFBE2 will affect the output voltage. If it is set to be
exactly half of the upper feedback resistor, RFBT, then we could get an output voltage that would not
depend on the transistor’s VBE. Therefore when RFBE2 is set to RFBT/2, we get
VOUT 2 ˜ VBE 2 ˜ VBE
IRFBT
RFBT
RFBT
(5)
This can be written as
VOUT
IRFBT
RFBT
(6)
We set the feedback current to be 1mA. Therefore setting IRFBT to 1mA, we can find the required value for
RFBT.
VOUT
RRFBT
IRFBT
(7)
The two PNPs forming the current mirror should have very close matching so as to get a well-matched
current and consequently lesser variation in VOUT. The best way to ensure that is to find a device that has
two PNPs packaged together. This way the two VBEs will change together with temperature. Another note
to keep in mind is that while laying out the board, the transistors should be kept away from the high
current paths.
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Test Results
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3 Test Results
The following scope plots and efficiency data were taken on the custom PCB. Figure 3 shows the line
regulation at IOUT of 400mA. Because of the modified current mirror, there is very little variation on the
output with input voltage.
12.1
12.08
12.06
12.04
12.02
Output Voltage (V)
12
11.98
11.96
11.94
11.92
11.9
11.88
11.86
11.84
11.82
11.8
0
5
10
15
20
25
30
Input Voltage (V)
Figure 3. Line Regulation, IOUT = 400mA
Figure 4 shows the efficiency of the design with respect to the load current and different VINs.
90
85
80
Efficiency (%)
75
5V
70
12V
65
24V
60
55
50
0
0.5
1
1.5
2
2.5
Output Current (A)
Figure 4. Efficiency Vs. IOUT, VOUT = -12V
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Test Results
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Figure 5 shows the load regulation of the design with the input voltage set to -12V.
12.15
12.125
Output Voltage (V)
12.1
12.075
12.05
12.025
12
11.975
11.95
0
200
400
600
800
1000
1200
Output Current (mA)
Figure 5. Load Regulation, VIN = -12V
Because of a relatively high switch current limit of 4A, the LM2586 can allow high output currents. Figure 6
shows the max load that the device can drive vs. the input voltage it is operating at.
2.5
Maximum Output Current (A)
2
1.5
1
0.5
0
0
5
10
15
20
25
30
Input Voltage (V)
Figure 6. Maximum Output Current Vs. Input Voltage
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Test Results
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As mentioned before, one advantage of the inverted SEPIC is that the output sees constant current. This
means that the RHP zero is eliminated in this topology. This makes the design a little easier to
compensate and the resulting load transient response would be faster. Figure 7 shows the result of a
200mA to 1A load transient at the output.
VOUT
500mV/div
1A
IOUT
200mA
20ms/div
Figure 7. Load Transient VIN = -12V, VOUT = -12V, IOUT = 200mA to 1A
Figure 8 shows the startup behavior of the design. In certain systems inrush currents shown aren't
tolerated. In order to reduce the inrush currents a longer softstart is desired. To add more softstart time an
external circuit can be added. Please refer to application note titled Soft-start Using Constant Current
Approach to learn more about this.
VOUT
5V/div
IL2
500mA/div
10ms/div
Figure 8. Startup VIN = -12V, VOUT = -12V, IOUT = 500mA
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Conclusion
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Table 1. Design BOM
4
DESIGNATOR
DESCRIPTION
PART NUMBER
CC
CAP, CERM, 0.22 µF, 16 V, +/- 5%, X7R, 0805
0805YC224JAT2A
CC2
CAP, CERM, 1000 pF, 100 V, +/- 5%, C0G/NP0, 0805
08051A102JAT2A
CIN1
CAP, AL, 56 µF, 50 V, +/- 20%, 0.34 ohm, SMD
UUD1H560MNL1GS
CIN2
CAP, CERM, 10 µF, 100 V, +/- 20%, X7R, 6x5x5mm
CKG57NX7R2A106M500JH
COUT1, COUT2
CAP, AL, 220 µF, 35 V, +/- 20%, 0.15 ohm, SMD
EEE-FC1V221P
CS2
CAP, CERM, 4.7 µF, 100 V, +/- 10%, X7S, 1210
C3225X7S2A475K200AE
COUT3
CAP, CERM, 10 µF, 50 V, +/- 10%, X5R, 1206_190
CGA5L3X5R1H106K160AB
D1
Diode, Schottky, 100 V, 2 A, PowerDI123
DFLS2100-7
D2
Diode, Schottky, 40 V, 1 A, SOD-123
1N5819HW-7-F
L1 , L2
Inductor, Shielded Drum Core, Ferrite, 47 µH, 2.7 A, 0.076 ohm,
SMD
744770147
Q1
Transistor, Dual PNP, 60 V, 0.6 A, SOT-363
MMDT2907A-7-F
Q3
Transistor, PNP, 150 V, 0.5 A, SOT-23
MMBT5401LT1G
RFBE2
RES, 6.04 k, 1%, 0.125 W, 0805
CRCW08056K04FKEA
RC
RES, 226, 1%, 0.125 W, 0805
CRCW0805226RFKEA
RFBB
RES, 1.21 k, 1%, 0.125 W, 0805
CRCW08051K21FKEA
RFBT
RES, 12.1 k, 1%, 0.125 W, 0805
CRCW080512K1FKEA
RSET
RES, 22.1 k, 1%, 0.125 W, 0805
CRCW080522K1FKEA
Conclusion
Thus we see that just by adding a few external components, a SIMPLE SWITCHER® boost regulator like
the LM2586 could be used in an inverted SEPIC topology to obtain a negative output from a negative
input. The showcased design has good line regulation and load transient response.
5
References
1. Designing DC/DC converters based on ZETA topology
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