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Texas Instruments Transient-testing platforms and automation techniques for LDOs and buck regulato Application notes
Analog Applications Journal
Industrial
Transient-testing platforms and automation
techniques for LDOs and buck regulators
By Kern Wong
Principal Design Application Engineer, Mobile Lighting and Power
Introduction
Figure 1. Antiquated setup for transient testing
With mobile processors in wireless devices operating in
the gigahertz range, there is increasing consumer demand
for higher performance, longer battery life, smaller size,
and lower cost. Therefore, the design of power management circuits is becoming an increasingly complex issue.
Low dropout regulators (LDOs) and switching regulators
are indispensable components in portable systems with
standalone regulators and power management units
(PMUs). As high-speed and portable communications
devices employ regulators that require faster response
time, it is necessary to rigorously validate regulator performance and merits in order to ensure reliable power
management products. Key performance parameters
include line transient, load transient, startup, load and line
regulation, and several others. To have a complete analysis
of these parameters, it is necessary to have state-of-theart tools for the hardware test platform and mature methodology. These tools allow accurate and high sample rates
for parameter characterization in addition to supporting
automation techniques that speeds up testing and ensures
repeatable results.
A
B
A. Emitter followers and pulse generator create VIN step
voltage during line transient tests.
B. Device under test (DUT) is an LDO evaluation board
(EVB).
C. PCB for NMOS transient load switch. A constant load
is applied during line transient tests.
Implementing high-edge-rate and reusable test
apparatus
circuit board (PCB). Also important is proper selection of
optimal ground and supply conduits, bypassing, charge
reservoirs, and external support components. After all, it
is the merits of the DUT that should be ascertained, not
the parasitic or the unwanted effects from improper
components and physical layout.
For an accurate assessment of the key parameters of a
regulator, it is necessary to generate steps in line voltage
and load current that are fast with respect to the regulator’s control-loop response time. Lab equipment and many
commercial instruments that use operational amplifiers
(op amps), passive components, and large driver chains
can limit the rise and fall times of the stimulus signals with
large excursions. To obtain high-speed edge rates for load
transients (>> 1 A/µs) and line transients (>> 0.1 V/µs,
with input caps), practically no off-the-shelf products are
available.
It is possible for a slow-transient stimulus to make a
poor regulator look good. In response, incremental
research and development (R&D) led to simpler designs
that are low in parasitic L and C, which can be readily
built and duplicated for use in design and application labs.
Setting up a respectable test jig is half the solution. To
achieve optimal response, the device under test (DUT)
must be properly wired or socketed onto the printed
Texas Instruments
C
Preamble on test hardware challenges and
limitations
In a load-transient test, the regulator’s input is powered by
a constant voltage source and the output is rapidly
switched to a greater resistive load or current sink. A linetransient test is similar in that a line-voltage step is rapidly
injected at the regulator input while its output is
supported with a constant load. Figure 1 shows a typical
test setup for transient testing. The setup is relatively
modularized for ease of assembly and the long cable
lengths were adequate for legacy technology. However,
this setup is not satisfactory for today’s requirement
because of parasitics, ground loops, and higher voltages
and currents.
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AAJ 3Q 2015
Analog Applications Journal
Industrial
Test-jig parasitics and automation
A transient-testing program for semi-automated testing
was initiated in January of 2013 for PMUs and regulators.
A universal regulator test bed was conceived and
constructed to verify its merits. Figures 2 and 3 show an
LDO regulator test jig that can accommodate an evaluation board (EVB) via machined socket pins for semi-­
automated testing. The schematic is shown in Figure 4.
Figure 3. Back side of LDO test jig
Figure 2. Transient test jig with
LDO EVB (blue PCB)
C
A
D
B
A. NFET load step switch (under resistors).
B. Relays to select load.
C. NPN follower.
D. 48-mA relay drivers.
Figure 4. Schematic for the LDO test jig
+6 V
200 µF
VIN
VOUT
VIN_LDO
9Ω
Line
Transient
VIN_LDO
(I-Loop, 0.2-inch
Spacing)
LP5907 EVB
LP5907 EVB
EN_LDO
EN
K1
Low-Inductance
Resistance
Load Box
K2
Socket R1
K3
Socket R2
Load
Transient
Socket R3
VOUT_LDO
(I-Loop, 0.2-inch
Pad Min Spacing)
Texas Instruments
GND
Socket R0
VOUT_LDO
+5 V
R1
R2
R3
GND
SN74AS1004A
+5 V
0.1 µF
Relay
Drivers
for K1
to K3
Relay Coils
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AAJ 3Q 2015
Analog Applications Journal
Industrial
Figures 5 through 7 show a similar transient test jig and
schematic for a buck regulator.
Figure 6. Back side of buck-regulator test jig
Figure 5. Transient test jig and
buck-regulator EVB (green PCB)
A
B
C
D
A. NFET load step switch (under resistors).
B. NPN follower for line step.
C. 48-mA relay drivers.
D. Relays to select load.
Figure 7. Schematic for the buck regulator test jig
+6 V
200 µF
10 Ω
50 Ω
SW
EN_Buck
9Ω
Line
Transient
VIN_Buck
(I-Loop,
0.2-inch
Spacing)
LM3671 EVB
VOUT_Buck
VIN_Buck
LP5907 EVB
+5 V (to logic
and relays)
K1
Low-Inductance
Resistance
Load Box
Socket R0
K2
GND
Socket R1
K3
Socket R2
VOUT
K4
Socket R3
Load
Transient
+5 V
K5
SN74AS1004A
Socket R4
VOUT_Buck
(I-Loop, 0.2-inch
Pad Min Spacing)
Texas Instruments
K6
Socket R5
R1
R2
R3
GND
9
+5 V
0.1 µF
Relay
Drivers
for K1
to K6
Relay Coils
AAJ 3Q 2015
Analog Applications Journal
Industrial
Further enhancements
Figure 9. Temperature-cycling test jig with
personality PCB for PMUs
The test jigs were successful in achieving the design goals
in that they significantly reduced parasitics and current
loops, thus enabling faster edge-rate stimulus for validating targeted products. In June of 2013, a follow-up
enhanced design for a higher-performance, integrated
transient test jig. This jig is capable of accommodating
today’s high-bandwidth and fast-edge-rate products and
future generations.
As shown in Figure 8, the enhanced jig was designed
with a circular PCB configuration and can either adapt an
EVB of a DUT for maximum flexibility. An alternate DUT
layout is to solder it on the PCB for optimal performance.
Radio frequency (RF) plumbing was used on the board
and PCB traces were matched and impedance controlled.
The jig also provides a rechargeable battery pack that
provides clean and quiet power to the DUT for low-noise
applications.
Figure 8. Enhanced test jig with
resistive loads on board
Architecture and automated test flow
A block diagram of the test environment for the automated test platform is shown in Figure 10.
The supply block provides all the voltage inputs and the
line-transient input to the DUT. The load block provides
multiple resistive loads that are controlled with relays. The
control block is responsible for interfacing with the DUT
and also for changing the supply and load settings. The
measurement block is responsible for measuring the input
and output voltages and currents.
Figure 10. Generic test environment
Control
Supply
Load
Measurement
For more extreme test requirements, the jig was redesigned to interface with temperature-cycling, air-stream
systems that can be sealed air tight with no leakage, which
will avoid icing at extreme temperatures. The result is the
castle-shaped metal housing structure shown in Figure 9
that supports a personality card PCB for the EVB. An
alternative could be a circular PCB with a direct on-board
DUT mount. Also, a high-temperature transparent plastic
adapter was included to interface to a temp-cycling
housing.
Texas Instruments
DUT
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Analog Applications Journal
Industrial
LDO test jig
Lab equipment deployed
Based on the jig schematic in Figure 4, the line-transient
input is connected to a function generator to provide the
line transient input to the LDO. Since the function generator cannot source a lot of current, an emitter follower is
used to increase the current being sourced to the input. A
9-W resistor is connected at the output of the emitter
follower circuit to provide fast discharge of the input
capacitor during the fall time of the input line transient.
For tests that do not require a line transient, a constant
DC voltage is provided through the line transient input,
which is connected to the input of the LDO. The enable
(EN) input is available to provide a pulse for the startup
test using a function generator. In other test cases, the
enable pin is supplied with a constant DC voltage for
regular enable operation. The load-transient input is also
controlled by a function generator that switches the
NMOSFET continuously for a load-transient test. There is
a base load (1-mA load for the LDO), which is always
connected to the output of the LDO. However, it can be
disconnected, if required. Three other resistive loads are
controlled by using three relays. In turn, these relays are
controlled via a computer through a USB relay controller.
For line/load-transient and startup testing, the test platform includes a programmable power supply, three function generators, one oscilloscope, and a test jig. The power
supply is used to provide power to the test circuitry
required to carry out line- and load-transient testing. The
power supply is also used to power the enable pin of the
DUT and the relay driver chip, which allows the user to
select different loads for a particular test. The function
generators are used for generating pulse waveforms (using
the arbitrary function waveform) for the line-transient
step, load-transient step, and to pulse the enable pin.
The oscilloscope measures the input and output voltages and currents. The test platform is also used to
observe the enable pin for the startup test. Designed as a
plug-and-play test platform where the DUT needs to be
installed on the test jig, this architecture methodology
allows the reuse of the platform for different DUTs. The
test setup relies on instruments that are controlled by a
laptop running LabVIEW® software and connected via a
general purpose interface bus (GPIB). All instruments,
except for the oscilloscope, are daisy chained using GPIB
cables that are connected to the laptop using a USB to
GPIB cable. The oscilloscope is directly connected to the
laptop with a USB cable. BNC to SMA cables are used to
measure or probe all the signals.
Buck test jig
The system architecture of the buck-regulator test jig
shown in Figure 7 is virtually the same as for the LDO jig.
The only major change is the addition of three new relays.
These were added because of the complicated nature of
the load-transient tests for a buck IC. Unlike a LDO, load
transients consist of different base current for load-­
transient testing. For example, for a LDO, the load transients required are 1 mA to 20 mA, 1 mA to 100 mA and 1
mA to 250 mA. However, for a buck, the various load-transient tests require 1 mA to 50 mA, 50 mA to 400 mA, 200
mA to 400 mA, and 0.6 A to 1 A. Hence, there are additional relays. The PCB design has some other changes.
The buck is a switching regulator, thus, there is an additional switching pin to probe. This pin is isolated from
other parts of the board by creating 20-mm segregation on
both sides of this trace and pin. The tests for the buck test
platform are exactly the same as for the LDO platform.
LabVIEW tool (LVT) for test automation
Visual basic routines for virtual instruments (VIs) are
written to automate the transient tests. These tests
consist of three blocks. The first block of the LVT test
selects the loads for the test. The second block includes
the feedback correction loop that continuously measures
the rise and fall times of the input-transient stimulus and
corrects for the output of the function generator until the
correct rise and fall times are measured by the oscilloscope. The third block of the LVT test captures a screenshot of the output and input voltage once the feedback is
completed. It also obtains the measured rise and fall times
and the maximum and minimum output voltages. The LVT
obtains the minimum, maximum and mean of all the
parameters directly from the scope. It also calculates the
average of the maximum and minimum value measured.
The LVT then populates a matrix of measurements and
graphs that are displayed on the front panel. These
measurements are also written to a text file in the Text
Files folder. The screen shots are saved to a pen drive
inserted into the oscilloscope. The name of these files are
decided based on the kind of load and edge-rate setting.
However, the names can be changed in the block diagram
of the LVT.
PCB design and issues
There are two major concerns on the layout of the redesigned automation test platform for high-performance validation. The first concern is maintaining high edge rates
and signal integrity of the stimuli. The test setup is
designed to produce fast line and load transients for the
DUT. However, impedance mismatches and cross-talk
between traces can significantly affect these high-speed
lines. The second concern is voltage drops in power lines
caused by attenuation from long traces. Hence, proper
PCB design following good RF techniques is required.
Also, it is necessary to measure a signal as close to its
origin as possible to mitigate voltage drop or parasitic
effects.
Texas Instruments
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AAJ 3Q 2015
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Industrial
Conclusion
References
The platform for automating high-speed transient testing
is very multi-disciplinary because it requires capabilities
beyond typical validation and test R&D. Included are a
wide range of disciplines such as basic knowledge of
startup-and-­transient behavior characteristics for linear
and switching regulators, best practices plus novel techniques for test and measurement, board-level system
design, and software development.
With the prototyping test jigs for both LDO and buck
ICs, the proposed test procedures can be validated and
automated for line-transient, load-transient and startup
tests. Stimulus edge rates can be achieved in the nanosecond range with proper drive, interfacing, and termination.
High-speed waveform-capture sampling can be done with
high-performance test equipment and probes. Serialinterface control of device modes, operation, and test
equipment can be programmed on the fly to automate
testing. Furthermore, closed-loop control and monitoring
facilitates programming the timed events and electrical
parametric stimuli in addition to accurately logging
response time delays.
1. Kern Wong, “High-Speed Load/Line Transient Jigs and
App Report for Testing Fast Response POL Regulators,”
Texas Instruments Application Report (SNOA895),
April 2013.
2. Kern Wong, “Myths surrounding PSRR specifications,”
TI E2E Power House blog, October 22, 2013.
3. Load Transient Testing Simplified, Texas Instruments
Application Report (SNOA507), November 2007.
Related Web sites
Product information:
LP5907
LM3671
LabVIEW tool information:
www.ni.com/labview
Subscribe to the AAJ:
www.ti.com/subscribe-aaj
Acknowledgments
The author thanks Sheng Jin, Applications Manager MLP
at Texas Instruments and Aditya Jain, our dedicated
intern. Thanks also to Hoang Duong, Robin Gupta, and
Hak-Leong Ng.
Texas Instruments
12
AAJ 3Q 2015
Analog Applications Journal
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