Texas Instruments | TPS65910x Power Sequencing Configurations | Application notes | Texas Instruments TPS65910x Power Sequencing Configurations Application notes

Texas Instruments TPS65910x Power Sequencing Configurations Application notes
Application Report
SWCA297 – July 2015
TPS65910x Sequencing Configurations
Rick Solarski
ABSTRACT
This document discusses the default voltages and boot orders of the TPS65910x power management
integrated circuits (PMICs).
1
Overview
Table 1 defines the default voltages and boot sequence of the TPS65910x power management integrated
circuits (PMICs). The values 1 through 7 in the top row represent the 2ms time slots, wherein, a regulator
will be enabled. Every TPS65910x device contains the two default configurations shown in the first two
rows of this table, selected with the associated logic levels on the BOOT pins.
The entries shown in Table 1 define the unique, factory pre-programmed EEPROM boot sequences for
each TPS65910x device, selected via the configuration BOOT 0 = 0, and BOOT 1 = 1. Regulators not
listed are off by default.
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SWCA297 – July 2015
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TPS65910x Sequencing Configurations
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1
Overview
www.ti.com
Table 1. Boot Sequences for Each TPS65910x Device
Sequence
TPS65910x
BOOT[0:1]=0/0
Processor
1
2
3
4
5
6
AM3517,
AM3505
1.8 (VIO),
1.8 (VAUX1)
3.3 (VDD2)
1.2 (VDD1)
1.8 (VPLL)
1.8 (VDAC),
1.8 (VAUX2)
3.3 (VMMC)
1.8 (VIO)
1.8 (VPLL)
1.2 (VDD1)
1.2 (VDD2)
1.8 (VAUX2)
3.3 (VAUX33)
1.2 (VDD2)
1.8 (VIO),
1.2 (VDIG2)
3.3 (VAUX33),
3.3 (VMMC)
1.8 (VAUX1),
3.3 (VAUX2)
1.8 (VPLL),
1.8 (VDAC)
TPS65910x
BOOT[0:1]=1/0
TPS65910
7
OMAPL-137/8,
C674x
1.2 (VDD1),
1.2 (VDIG1)
TPS65910A
AM335x
with DDR2
1.8 (VDAC)
1.8 (VDIG1),
1.8 (VDIG2)
1.8 (VPLL),
1.8 (VAUX1)
1.8 (VIO)
3.3 (VAUX2),
3.3 (VAUX33),
3.3 (VMMC)
1.1 (VDD1)
1.1 (VDD2)
TPS65910A3
AM335x
with DDR3
1.8 (VDAC)
1.8 (VDIG1),
1.8 (VDIG2)
1.8 (VPLL),
1.8 (VAUX1)
1.5 (VIO)
3.3 (VAUX2),
3.3 (VAUX33),
3.3 (VMMC)
1.1 (VDD1)
1.1 (VDD2)
TPS65910A31
AM335x
with DDR3
1.8 (VDAC)
1.8 (VDIG1),
1.8 (VDIG2)
1.8 (VPLL),
1.8 (VAUX1)
1.5 (VIO)
3.3 (VAUX2),
3.3 (VAUX33),
3.3 (VMMC)
1.1 (VDD1)
1.1 (VDD2)
TPS659101
Samsung:
S5PV210,
S5PC110
1.1 (VPLL)
1.2 (VDD1),
1.1 (VDD2),
1.1 (VDIG2)
1.8 (VIO)
2.8 (VAUX1),
3.3 (VAUX33),
3.3 (VMMC)
2.6 (VDAC)
TPS659102
Rockchip:
RK29xx,
RK30xx
3.3 (VIO)
1.2 (VDIG2),
2.5 (VPLL),
3.3 (VAUX33)
1.8 (VDAC),
3.3 (VAUX2)
1.8 (VDIG1),
2.8 (VAUX1),
3.0 (VMMC)
TPS659103
Samsung:
S5PC100
1.2 (VDIG1)
1.2 (VDD1),
1.2 (VDD2),
1.2 (VDIG2)
1.8 (VIO)
2.8 (VAUX1),
3.3 (VAUX33),
3.3 (VMMC)
3.3 (VAUX2)
1.8 (VPLL)
TPS659104
Samsung:
S5P6440
1.1 (VPLL)
1.1 (VDD1),
1.1 (VDD2),
1.1 (VDIG2)
1.8 (VIO),
1.8 (VDIG1)
3.3 (VAUX33),
3.3 (VMMC)
3.3 (VAUX2)
1.8 (VDAC)
TPS659105
DM643x,
DM644x
1.2 (VDD1)
3.3 (VAUX1),
3.3 (VAUX2),
3.3 (VAUX33)
1.8 (VIO)
1.2 (VDD2)
1.8 (VDIG1),
1.8 (VPLL)
1.8 (VDIG2),
3.3 (VMMC)
1.8 (VDAC)
TPS659106
Freescale:
i.MX53
1.8 (VDIG2)
1.275 (VDD2)
1.8 (VIO),
1.3 (VDD1),
2.5 (VAUX1)
1.8 (VDIG1),
2.6 (VDAC),
2.8 (VMMC)
3.3 (VAUX2),
2.8 (VAUX33)
TPS659107
Freescale:
i.MX27,
i.MX35
1.35 (VDD1),
3.3 (VAUX33)
3.0 (VMMC)
1.8 (VIO)
2.8 (VAUX1)
1.2 (VDD2),
5.0 (VDD3),
1.5 (VDIG1),
3.3 (VAUX2)
1.8 (VDIG2)
1.8 (VPLL),
2.6 (VDAC)
TPS659108
Freescale:
i.MX508
1.1 (VPLL)
1.1 (VDD2)
1.1 (VDD1),
1.2 (VDIG2),
3.3 (VAUX2)
2.5 (VAUX1)
1.8 (VIO)
1.8 (VDAC)
1.2 (VDIG1),
3.3 (VAUX33),
3.3 (VMMC)
TPS659109
Freescale:
i.MX51
1.2 (VDIG1)
1.2 (VDD2)
1.8 (VIO)
2.8 (VAUX1),
2.8 (VMMC)
1.1 (VDD1),
1.2 (VDIG2)
1.8 (VPLL)
2.6 (VDAC),
3.3 (VAUX2),
3.3 (VAUX33)
2
1.2 (VDD1),
1.2 (VDD2)
TPS65910x Sequencing Configurations
SWCA297 – July 2015
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References
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Current limitations for each regulator are further detailed in Table 2.
Table 2. Regulator Limitations
Number of power rails available
12
Input voltage range
2.7 V - 5.5 V
Sequencing(power-up/down)
Special features
Multi-Rail Configurations
Pre-Programmed *
Battery Backup, RTC, Digitally Set Output Voltage
Voltage Range*
Current limit
DCDC1 (VIO)
1.5 V - 3.3 V
1.0 A
DCDC2 (VDD1)
0.6 V - 3.3 V
1.5 A
DCDC3 (VDD2)
0.6 V - 3.3 V
1.5 A
DCDC4 (VDD3)
5V
100 mA
LDO1 (VDIG1)
1.2 V - 2.7 V
300 mA
LDO2 (VDIG2)
1 V - 1.8 V
300 mA
LDO3 (VPLL)
1.0 V - 2.5 V
50 mA
LDO4 (VDAC)
1.8 V - 2.85 V
150 mA
LDO5 (VAUX1)
1.8 V - 2.85 V
300 mA
LDO6 (VAUX2)
1.8 V - 3.3 V
150 mA
LDO7 (VAUX33)
1.8 V - 3.3 V
150 mA
LDO8 (VMMC)
1.8 V - 3.3 V
300 mA
Additional features such as clock source, VRTC regulator current limit in off state, reset polarities and
enable conditions are further detailed in the device-specific user’s guide’s listed in Section 2.
2
References
•
•
•
•
•
•
•
•
•
•
•
•
TPS65910 User Guide For OMAPL-137, OMAPL-138, and TMS320C674x Family of Processors
(SWCU071)
TPS65910 User Guide For AM3517/AM3505 Processor (SWCA089)
TPS65910Ax User's Guide For AM335x Processors (SWCU093)
TPS659101 User Guide for S5PV210 and S5PC110 (SWCU068)
TPS659102 User's Guide (SWCU137)
TPS659103 User Guide for S5PC100 (SWCU075)
TPS659104 User Guide for S5P6440x (SWCU072)
TPS659105 User Guide For DaVinci Family of Processors (SWCU074)
TPS659106 User's Guide For i.MX53 Processors (SWCU090)
TPS659107 User Guide For i.MX27 and i.MX35 Processors (SWCU073)
TPS659108 User Guide For i.MX508 (SWCU077)
TPS659109 User Guide For i.MX51 and i.MX37 Processors (SWCU070)
SWCA297 – July 2015
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TPS65910x Sequencing Configurations
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3
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