Texas Instruments | Rapid Transient Response With UCC28633 PSR-Flyback and UCC24650 Wake-Up Monitor | Application notes | Texas Instruments Rapid Transient Response With UCC28633 PSR-Flyback and UCC24650 Wake-Up Monitor Application notes

Texas Instruments Rapid Transient Response With UCC28633 PSR-Flyback and UCC24650 Wake-Up Monitor Application notes
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Application Report
SLUA735 – February 2015
Rapid Transient Response With UCC28633
Primary-Side-Regulation (PSR) Flyback and
UCC24650 Wake-Up Monitor
Bernard Keogh ............................................................................. Systems Solutions & Marketing, HVPS
ABSTRACT
PSR flyback controllers make use of primary-side information to indirectly sense the output voltage for
regulation. This capability allows elimination of the conventional secondary-side error amplifier (typically
TL431) and feedback opto-coupler – saving cost and standby power. However, because the output
voltage can only be sampled during a switching cycle, there is always a trade-off with PSR between verylow switching frequency to achieve low standby power and the need to keep switching frequency high to
maintain a fast transient response. This application note demonstrates how the UCC28633 PSR controller
can be combined with the UCC24650 secondary-side fast wake-up monitor to achieve low standby power
and fast transient response.
Topic
1
2
3
4
5
6
7
8
...........................................................................................................................
Page
Introduction ........................................................................................................ 2
Transient Response versus Standby Power ............................................................ 3
UCC28633 External Wake Input at VSENSE Pin ....................................................... 4
Practical Demonstration Using UCC28630-EVM572 .................................................. 6
Test Results ........................................................................................................ 8
Summary and Conclusions ................................................................................. 12
References ........................................................................................................ 12
Export Control Notice ......................................................................................... 12
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Rapid Transient Response With UCC28633 PSR-Flyback and UCC24650
Wake-Up Monitor
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Introduction
1
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Introduction
PSR is ideally suited to flyback converters, where secondary-side output voltage is readily available for
sensing across the transformer low-voltage bias winding, scaled by the bias-to-secondary turns ratio. Such
schemes require connection of the primary-referenced bias winding to a voltage-sense pin of the PWM
controller, for measurement of the reflected output voltage during the flyback interval, as shown in
Figure 1. Sampling of the reflected output voltage is synchronized to the flyback-interval portion of the
PWM switching cycle, as shown in Figure 2.
PRI
Np
VAC
SEC
Ns
VOUT
EMC
Filter
PWM Controller
Rt
1 VSENSE
HV 8
2 SD
BIAS
Nb
Rb
3 CS
VDD 6
4 GND
DRV 5
Figure 1. Typical PSR Flyback Power Stage and Controller
Bias winding
proportional to Vout
Gnd
Flyback output
sample window
Figure 2. Indirect Output Voltage Sense through Flyback Bias Winding
2
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Wake-Up Monitor
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Transient Response versus Standby Power
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2
Transient Response versus Standby Power
As shown in Figure 2, the sampling of the reflected output voltage on the bias or sense winding must be
synchronized to the Flyback interval of a PWM switching cycle. In between switching cycles, the primaryside controller is effectively “blind” to any deviations in the output voltage. This differs from conventional
secondary-side error-amplifier plus opto-feedback schemes, where the secondary-side error amplifier
continuously monitors the output voltage.
To achieve very low standby power targets, such as ≤30 mW, the PWM switching frequency of PSR
controllers is commonly decreased as load power decreases. As the load power approaches zero, the
PWM frequency can decrease well below 1 kHz; for example, the UCC28633 PSR controller has a
minimum switching frequency Fmin of just 200 Hz. This very-low minimum frequency allows for power
supply designs that can achieve very-low standby power.
However, as noted previously, in between switching cycles, the PSR controller is “blind” to any changes in
output voltage. So, if the power supply is running at or near zero-load standby level, and a large load
transient is applied, the response of the primary controller will be very dependent on the relative timing
between the application of the load step, and the next timed PWM cycle. If the primary controller is
operating at an Fmin of 200 Hz for example, then the worst-case delay is up to 5 ms before the next
switching cycle; during this interval, the drop in system output voltage is entirely a function of the load
current and the amount of output hold-up capacitance (see Figure 4).
IOUT
Heavy Load Step
VNOM
VOUT
PWM
Cycle
T = 1/(Fmin)
Figure 3. Output Transient Drop at Fmin – When Load Step Occurs just After PWM Cycle
By making use of the UCC28633 PSR controller and the UCC24650 secondary-side voltage monitor and
wake-up IC, the user can design a PSR flyback power supply that can achieve good transient response
and low standby power.
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UCC28633 External Wake Input at VSENSE Pin
3
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UCC28633 External Wake Input at VSENSE Pin
The UCC28633 controller supports fast PSR transient response through the VSENSE pin. When the
internal control loop drives the switching frequency low enough, the controller enters a low-power sleep
mode for a portion of the switching cycle. The sleep interval varies depending on the switching frequency
commanded; the sleep interval is longer for lower switching frequency.
The UCC28633 can respond to a fast transient “wake” signal coupled to the VSENSE pin. If the wake
signal exceeds an internal pin threshold of typically 0.8 V while the controller is in sleep mode, the sleep
interval is terminated and PWM activity commences within a typical delay time of 7 μs. This dramatically
improves the response to heavy load transients from zero load, or very-light load. The commencement of
any sleep interval in the controller is delayed until the resonant ringing on the VENSE pin has decreased
below the 0.8-V threshold for at least 2 μs. This prevents false wake-up events due to the resonant
ringing. After the ringing has decreased, the wake response is enabled and the sleep interval commences.
VOUT
VAC
EMC
Filter
UCC24650
5 WAKE VDD 1
GND
2
UCC28633
1 VSENSE
HV 8
2 SD
to
3 CS
VDD 6
4 GND
DRV 5
Figure 4. UCC24650 Secondary-Side Voltage Monitor and Wake-Up Circuit
The wake signal at the VSENSE pin can be generated using a secondary-side low-power voltage monitor
such as UCC24650, as shown in Figure 4. For more details, see the data sheet for UCC24650. This
secondary-side monitor uses the switching activity on the secondary winding to trigger refresh of an
internal sample-and-hold circuit to measure and record the system output voltage at its VDD pin.
Thereafter, if the actual system output voltage, as sensed at its VDD pin, drops by more than 3% of the
previously sampled value, the WAKE pin is internally pulled low through a current-limited open-drain
switch.
4
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UCC28633 External Wake Input at VSENSE Pin
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As shown in Figure 4, the main output rectifier diode must be positioned at the return side of the
secondary winding, so that the GND-referenced UCC24650 WAKE function can be deployed. In effect, the
WAKE pin shorts out the rectifier diode for a short interval to draw some current from the output capacitor
through the transformer secondary winding. This sets up a low-level pulse of current that then rings
resonantly in the power circuit, magnetizing inductance and parasitic capacitance. This causes a similar
ringing voltage waveform on all transformer windings, including the bias/sense winding, which interfaces to
the VSENSE pin. If the initial pulse of current drawn by the secondary WAKE pin is sufficient, then the
ringing voltage at the VSENSE pin is large enough to exceed the wake-up threshold.
The UCC28633 data sheet Typical Application section includes details of how to estimate the amplitude of
the wake pulse ringing at the WAKE pin. In some cases, especially at higher-rated output power, the
transformer magnetizing inductance is lower, while the total switch node capacitance tends to be higher.
This reduces the transformer impedance and can also result in reduced wake pulse amplitude. In these
cases, the UCC24650 WAKE pin output can be augmented with an external PNP circuit Q1, R1, and R2,
as shown in Figure 5. In this case, when the WAKE pin pulls low, Q1 turns on, and draws more current
through the secondary winding. TI recommends to have a current limiting resistor (R1) in series with either
the collector or emitter. Effectively, R1 swamps the UCC24650 internal WAKE pin resistance, RWAKE. The
setup requires a pullup resistor (R2) from base to emitter to ensure that the WAKE pin is adequately
pulled up or pulled down during normal switching activity to properly trigger the internal sample and hold
on the VDD pin. The external PNP device Q1 must have at least the same voltage rating as the main
rectifier diode.
VOUT
VAC
EMC
Filter
R1
Q1
R2
UCC24650
5 WAKE VDD 1
GND
2
UCC28633
1 VSENSE
HV 8
2 SD
to
3 CS
VDD 6
4 GND
DRV 5
Figure 5. Addition of UCC24650 Secondary-Side Voltage Monitor and Wake-Up Circuit
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Practical Demonstration Using UCC28630-EVM572
4
Practical Demonstration Using UCC28630-EVM572
4.1
EVM572 Modifications
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To demonstrate the UCC28633/UCC24650 capability, a standard 65-W average/130-W peak UCC28630
EVM module (UCC28630-EVM572) was modified to accommodate the secondary-side UCC24650.
The board was modified to accommodate the secondary side wake-up IC UCC24650. The following list
shows the required changes, and Figure 6 shows the modifications to the standard EVM572 schematic.
Required changes to EVM572 to support fast wake-up chipset:
• Replace the pre-inserted UCC28630D with UCC28633D.
• Remove output rectifier Diode D7 (and associated heatsink).
• Insert shorting wire links from the D7 anode terminals to the D7 cathode terminal.
• Cut the bottom-side trace going from transformer pins 10 and 11 to the output RET net.
• Connect diode D7 between transformer pins 10 and 11 and the output RET net. The cathode terminal
should connect to the transformer pins, and the anode terminals should connect to the RET net. See
Figure 6 mark-up for details.
• Connect UCC24650 device to RET and +VOUT nets as shown in the schematic mark-up.
• Connect PNP transistor (choose minimum 100-V rated Vce, suggest FMMTA92 or similar) plus
resistors as shown in schematic mark-up, between the WAKE pin of UCC24650, output RET, and D7
cathode.
6
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Wake-Up Monitor
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Practical Demonstration Using UCC28630-EVM572
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ACA
LINE
TP1
HV
TP6
VSEC
VDC
C10
DNP
2
BR1
800V
L2
47.7µH
2
~
F1
J1
1
0603
R17
DNP
1206
+VOUT
TP10
18.5V - 20.5V
0A - 7A
D8
1SMB5947BT3G
82V
R12
DNP
1206
~
C7
27µF
C5
100µF
DNPC8
0805
ACB
5
9
8
MAG
C16
10pF
D9
1SMB5949BT3G
100V
Connect 2 pins
of bobbin to
Vsec and Ret nets
6
1
LED1
Green
NTST30100CTG
100V
11
10
C11
680µF
2
D6
TP8
-VPRI
MURS160-13-F
R11
D10
MAG
MAG
R2
100k
Minimize copper area
TP2
VDD
TP11
MAG
D1
ES1D-13-F
200V
100k
VDD
of net
U1
8
HV
VSENSE
SD
R1
6
4.70
C2
22µF
C14
1000pF
R3
GND
TP3
C3
1µF
C4
0.1µF
DRV
5
VDD
CS
DRV
GND
R4
1
4
C6
120pF
C15
10pF
47.0
R10
3.90k
R7
22.6k
R15
100k
D4
BAV70-V
RT1
470k
R5
1.00k
R8
39k
100R
R16
0.2
R9
180k
STARPT
NT1
Net-Tie
-VPRI
GND
RET
2.2k
UCC24650
TP7
FMMTA92
-VPRI
UCC28633D
C9
2200pF
-VPRI
CS
0
3
UCC28630D
DRV
also High voltage Net
Q1
STF13NM60ND
600V
1
100
R6
2
t°
DNP
-VPRI
2
100V
OUTPUT R/A
SOCKET
of VSW net
R13
4.7
C13
1µF
copper area
+VSW
D5
DANGER HIGH VOLTAGE
TP9
1
2
3
D3
1N4007
1000V
J2
C12
680µF
R18
8.20k
D7
D2
1N4007
1000V
+VOUT
3
RLTI-1098
GND
TP5
D7
4
1
1
+
3
C1
0.33µF
V1
-
L1
RLTI-1099
4.5mH
4
1
NEUTRAL
TP4
4
2
3
39213150000
88VAC - 230VAC
0.5A - 1.5A
RLTI-1100
T1
Wake
Vdd
Gnd
STARPT
R20
-VPRI
0
Figure 6. Modification of Standard EVM572 Schematic to Add UCC28633 PSR Controller and UCC24650 Secondary-Side Voltage Monitor and
Wake-Up Circuit
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Test Results
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5
Test Results
5.1
Standard EVM572
Before making any modifications, the standard EVM572 was tested for standby power and for no-load to
full-load transients, with the results shown in Table 1 and Figure 7. The design is optimized for low
standby power (to meet a specification of <70 mW), but this comes at the expense of very poor transient
performance for heavy load steps that can occur from zero-load. Worst-case transient dips of 11.7 V were
measured out of a 19.5-V set-point (60% dip).
Table 1. Measured Standby Power
No Load Power
Vin (V)
F (Hz)
Pin (W)
Measured
Pin (W) Max
Specification
Vout (V)
Pass?
115
60
0.0524
0.070
19.65
PASS
230
50
0.0585
0.070
19.79
PASS
90 Vac, load step 0 to 3.4 A
Ch4: Vout; Ch3: Iload; Ch1: Gate drive
Figure 7. Zero-Load to Full-Load Transient Response on Standard EVM572
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5.2
Standard EVM572 With Added Pre-Load
The standard EVM572 was modified slightly to add more pre-load to the output. This addition was
achieved by adding some on-board load resistance across the output. To meet a similar timing response
as the UCC24650 secondary-side wake IC, the pre-load was calculated such that the average PWM
frequency in standby would be approximately 4 kHz; this gives the required time delay between PWM
cycles such that a drop in Vout for a full-load step would be approximately 3% in between switching
cycles—the same as the UCC24650 drop in Vout required to trigger a wake-up pulse. For the EVM572
power stage, the pre-load resistance required is approximately 1 kΩ.
The modified EVM was then tested for standby power and no-load to full-load transients, with the results
shown in Table 2 and Figure 8. The design now achieves significantly better transient response – worstcase 1.34-V drop out of 19.5 V (or 6.9%), but this comes at the expense of significantly higher standby
power.
Table 2. Measured Standby Power
No Load Power
Vin (V)
F (Hz)
Pin (W)
Measured
Pin (W) Max
Specification
Vout (V)
Pass?
115
60
0.452
0.070
19.65
FAIL
230
50
0.441
0.070
19.79
FAIL
90 Vac, load step 0 to 3.4 A
ChD: Vout; Ch3: Iload; Ch1: Gate drive
Figure 8. Zero-Load to Full-Load Transient Response on Modified EVM572 with 1-kΩ Pre-Load
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Test Results
5.3
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Modified EVM572 With UCC24650
Finally, the EVM572 was modified to remove the previous extra resistive pre-load, and further modified to
include the secondary-side monitor/wake-up IC UCC24650, as detailed in Section 4.1 and Figure 9. The
system no-load standby power and transient response were measured.
Table 3. Measured Standby Power
No Load Power
Vin (V)
F (Hz)
Pin (W)
Measured
Pin (W) Max
Specification
Vout (V)
Pass?
115
60
0.054
0.070
19.65
PASS
230
50
0.060
0.070
19.79
PASS
As can be seen, very low standby power performance was maintained (<2 mW increase from addition of
the UCC24650, which can be compensated for by a slight increase in R18 in Figure 6).
The design achieves 60-mW standby for a power supply that is rated to 130-W peak. The standby power
is <0.05% of peak power. Transient response is good, despite the low standby power; 1.3 V or 6.7% dip.
90 Vac, load step 0 to 3.4 A
Ch4: Vout; Ch3: Iload; Ch1: Gate drive
Figure 9. Zero-Load to Full-Load Transient Response on Modified EVM572 With UCC24650
Figure 10 and Figure 11 show detailed plots of the waveform at the bias/sense winding and show a zoomin of the ringing wake-up pulse waveform generated by the secondary-side wake-up IC, as measured on
the primary-side bias/sense winding.
10
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Wake-Up Monitor
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90 Vac, load step 0 to 3.4 A
Ch2: Iout; Ch3: Vout, Ch4: Bias wdg, ChD: Zoom C4
Figure 10. Detailed Waveforms during the Load Step Event
Wake-up Pulse
Wake-up Delay
~7 s
PWM Cycle
Zoom-in of wake pulse + response
ChA: Vout; ChB: Bias wdg
Figure 11. Zoom-In of the Wake-Up Pulse and Ringing as Measured on the Primary-Referenced
Bias/Sense Winding of the Transformer
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Summary and Conclusions
6
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Summary and Conclusions
Due to the trade-off between standby power and transient response for PSR, Section 5.1 and Section 5.2
show there is clear choice for most designs: optimize for low standby power or optimize for heavy-load
transients that can occur when the power supply is operating at or near zero-load.
If the end-system has a sufficient minimum load, or if the end-system characteristics are such that heavyload transients cannot occur when idling at or near zero-load, then the power supply can be designed for
low standby power, without the poor transient response issue.
For applications where the end-system can demand very-heavy load steps from zero-load conditions,
Section 5.3 shows that by adding the UCC24650 secondary-side monitor and wake-up IC, a dramatic
improvement in transient response can be achieved, while still achieving a very-low standby power design.
The addition of the UCC24650 IC only adds a further 1 to 2 mW of extra dissipation at 19.5-V output. This
extra dissipation could be subsumed into the regular PSR output pre-load to maintain the same standby
performance as the system without UCC24650.
Table 4 summarizes the relative performance of the EVM572 in terms of standby power and no-load to
full-load transient deviation, under the three configurations tested.
Table 4. Performance Comparison
7
Pstandby (mW)
Measured at 230 Vac
ΔVout (V/%) for
0-A to 3.4-A Step
Standard EVM572
58.5
–11.7 V (–60%)
EVM572 + pre-load
441
–1.34 V (–6.9%)
EVM572 + UCC24650
60
–1.30 V (–6.7%)
References
•
•
8
Configuration
UCC28630/1/2/3 High-Power Flyback Controller With Primary-Side-Regulation and Peak-Power Mode,
data sheet (SLUSBW3)
UCC24650 Voltage Droop Monitor With Wake-Up Output, data sheet (SLUSBL6)
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