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Texas Instruments Using the TPS62125 in an Inverting Buck-Boost Topology (Rev. B) Application notes
Application Report
SLVA514B – May 2012 – Revised July 2014
Using the TPS62125 in an Inverting Buck-Boost Topology
Chris Glaser and Sebastian Hares ............................................................. Low Power DC-DC Applications
ABSTRACT
The TPS62125 is a DCS-Control™ topology synchronous buck dc-to-dc converter designed for low-power
applications. It features a wide operating input voltage range from 3 V to 17 V, 300-mA output current, and
adjustable output voltage of 1.2 V to 10 V. This device is well-suited for applications such as ultra lowpower microprocessors, energy harvesting, and low-power RF applications. Moreover, the TPS62125 can
be configured in an inverting buck-boost topology, where the output voltage is inverted or negative with
respect to ground. This application note describes the TPS62125 in an inverting buck-boost topology for
use in low current negative rails for operational amplifier or optical module biasing and other low-power
applications.
1
2
3
4
5
6
7
Contents
Inverting Buck-Boost Topology ............................................................................................ 2
1.1
Concept .............................................................................................................. 2
1.2
Output Current Calculations ....................................................................................... 3
1.3
VIN and VOUT Range ................................................................................................. 4
Digital Pin Configurations ................................................................................................... 4
2.1
Enable Pin ........................................................................................................... 4
2.2
Enable Hysteresis Pin .............................................................................................. 6
2.3
Power Good Pin .................................................................................................... 7
2.4
Discharging the Output Voltage ................................................................................... 9
Startup Behavior and Switching Node Consideration ................................................................. 10
External Component Selection ........................................................................................... 11
4.1
Inductor Selection ................................................................................................. 11
4.2
Input Capacitor Selection......................................................................................... 11
4.3
Selecting L and COUT for Stability ................................................................................ 12
Typical Performance and Waveforms ................................................................................... 13
Conclusion .................................................................................................................. 17
References .................................................................................................................. 18
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1
Inverting Buck-Boost Topology
1.1
Concept
The inverting buck-boost topology is very similar to the buck topology. In the buck configuration shown in
Figure 1, the positive connection (VOUT) is connected to the inductor and the return connection is
connected to the integrated circuit (IC) ground. However, in the inverting buck-boost configuration shown
in Figure 2, the IC ground is used as the negative output voltage pin (labeled as –VOUT ). What used to be
the positive output in the buck configuration is used as the ground (GND). This inverting topology allows
the output voltage to be inverted and always lower than the ground.
L
TPS62125
2
VIN
3
CIN
4
1
VIN
SW
EN
FB
EN_HYS
VOS
GND
PG
7
VOUT
5
6
RFB1
8
COUT
RPG
ETPAD
9
RFB2
Figure 1. TPS62125 Buck Topology
CIN
L
TPS62125
VIN
2
3
4
1
VIN
SW
EN
FB
EN_HYS
GND
VOS
PG
ETPAD
9
7
5
6
RFB1
8
COUT
RPG
RFB2
-VOUT
Figure 2. TPS62125 Inverting Buck-Boost Topology
The circuit operation is different in the inverting buck-boost topology than in the buck topology. Figure 3
(a) illustrates that the output voltage terminals are reversed, though the components are wired the same
as a buck converter. During the on time of the control MOSFET, shown in Figure 3 (b), the inductor is
charged with current while the output capacitor supplies the load current. The inductor does not provide
current to the load during that time. During the off time of the control MOSFET and the on time of the
synchronous MOSFET, shown in Figure 3 (c), the inductor provides current to the load and the output
capacitor. These changes affect many parameters as described in the upcoming sections.
DCS-Control is a trademark of Texas Instruments.
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+
VIN
–
+
Q1
Control
VIN
VSW
–
VSW
iL
+
Q2
Sync
VO
–
+
Q1
Control
(a)
–
Q1
Control
VSW
iL
+
Q2
Sync
Load
VIN
VO
–
Load
(b)
iL
+
VO
–
Q2
Sync
Load
(c)
Figure 3. Inverting Buck-Boost Configuration
1.2
Output Current Calculations
The average inductor current is affected in this topology. In the buck configuration, the average inductor
current equals the average output current because the inductor always supplies current to the load during
both the on and off times of the control MOSFET. However, in the inverting buck-boost configuration, the
load is supplied with current only from the output capacitor and is completely disconnected from the
inductor during the on time of the control MOSFET. During the off time, the inductor connects to both the
output cap and the load (see Figure 3). Knowing that the off time is 1 – D of the switching period, then the
average inductor current is:
I
IL(Avg) = OUT
(1 - D)
(1)
The duty cycle for the typical buck converter is simply VOUT / VIN but the duty cycle for an inverting buckboost converter becomes:
VOUT
D=
(VOUT - VIN)
(2)
Finally, the maximum inductor current becomes:
DI
IL(Max) = IL(Avg) + L(Max)
2
(3)
Where,
D: Duty cycle
∆IL (A): Peak to peak inductor ripple current
VIN (V): Input voltage with respect to ground, instead of IC ground or –VOUT.
The TPS62125’s current limit technique allows a simple maximum output current calculation. If the current
exceeds ILIMF (the high-side MOSFET current limit), the high-side MOSFET switch turns off and the lowside MOSFET switch turns on until the inductor current ramps down to 0. If an overload is still present
after reaching 0 current, the low-side MOSFET switch turns off and the high-side MOSFET switch turns on
until current limit is reached again. In current limit, the inductor’s current goes from ILIMF to 0—its ripple
current becomes ILIMF. Operating the TPS62125 in this state (with IL(Max) equal to ∆IL(Max) equal to ILIMF)
reduces the average inductor current to ½ ILIMF (from Equation 3). With the TPS62125's minimum current
limit value of 600 mA, this gives an IL(Avg) of 300 mA when current limit is reached. With this, the maximum
allowable output current is calculated from Equation 1 and Equation 2, with a 5-V input voltage to –5-V
output voltage system as an example:
D = –5 / (–5 – 5) = 0.5
This result is then used in Equation 1:
IOUT = IL(Avg) × (1 – D) = 300 × (1 – 0.5) = 150 mA
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Inverting Buck-Boost Topology
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Due to increased duty cycles when operating at either lower input voltages (≤ 5 V) or with higher ambient
temperatures (for example, at 85 °C), the duty cycle used for the maximum output current calculation
above should be increased by 10% for these conditions. This provides a more accurate maximum output
current calculation. For the given example of a 5-V input and –5-V output, the maximum output current is
then 300 x (1 - 0.6) = 120 mA.
The maximum output current for –5-V, –3.3-V and –8-V output voltages at different input voltages is
displayed in Figure 4 and accounts for the above duty cycle increase for lower input voltages. Operation at
higher temperatures would decrease the maximum output current shown for input voltages above 6 V as
well.
300
250
Max IOUT (mA)
200
VOUT = ±3.3 V
VOUT = ±5 V
150
VOUT = ±8 V
100
50
0
3
4
5
6
7
8
9
10
11
12
13
14
VIN (V)
C001
Figure 4. Maximum Output Current versus Input Voltage
1.3
VIN and VOUT Range
The input voltage that can be applied to an IC operating in the inverting buck-boost topology is less than
the input voltage for the same IC operating in the buck topology. This is because the ground pin of the IC
is connected to the (negative) output voltage. Therefore, the input voltage across the device is VIN to VOUT,
not VIN to ground. Thus, the input voltage range of the TPS62125 is 3 V to 17 + VOUT, where VOUT is a
negative value.
The output voltage range is the same as when configured as a buck converter, but negative. The output
voltage for the inverting buck-boost topology should be set between –1.2 V and –10 V. It is set the same
way as in the buck configuration, with two resistors connected to the FB pin.
2
Digital Pin Configurations
2.1
Enable Pin
The device is enabled once the voltage at the EN pin trips its threshold and the input voltage is above the
UVLO threshold. The TPS62125 stops operation once the voltage on the EN pin falls below its threshold
or the input voltage falls below the UVLO threshold.
Because VOUT is the IC ground in this configuration, the EN pin must be referenced to VOUT instead of
ground. In the buck configuration, 1.2 V is considered a high and less than 1.15 V is considered a low. In
the inverting buck-boost configuration, however, the VOUT voltage is the reference; therefore, the high
threshold is 1.2 V + VOUT and the low threshold is 1.15 V + VOUT. For example, if VOUT = –5 V, then VEN is
considered at a high level for voltages above –3.8 V and a low level for voltages below –3.85 V.
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This behavior can cause difficulties enabling or disabling the part, since in some applications, the IC
providing the EN signal may not be able to produce negative voltages. The level shifter circuit shown in
Figure 5 alleviates any difficulties associated with the offset EN threshold voltages by eliminating the need
for negative EN signals. If disabling the TPS62125 is not desired, the EN pin may be directly connected to
VIN without this circuit.
Q2
PMOS
S
VIN
1 MΩ
D
EN
1 MΩ
G
–VOUT
D
SYS_EN
Q1
NMOS
G
S
NOTE: VOUT is the negative output voltage of the inverting buck-boost converter
Figure 5. EN Pin Level Shifter
The positive signal that originally drove EN is instead tied to the gate of Q1 (SYS_EN). When Q1 is off
(SYS_EN grounded), Q2 sees 0 V across its VGS and also remains off. In this state, the EN pin sees –5 V
which is below the low-level threshold and disables the device.
When SYS_EN provides enough positive voltage to turn Q1 on (VGS threshold as specified in the
MOSFET datasheet), the gate of Q2 sees ground through Q1. This drives the VGS of Q2 negative and
turns Q2 on. Now, VIN ties to EN through Q2 and the pin is above the high-level threshold, turning the
device on. Be careful to ensure that the VGD and VGS of Q2 remain within the MOSFET ratings during both
the enabled and disabled states. Failing to adhere to this constraint can result in damaged MOSFETs.
The enable and disable sequence is illustrated in Figure 6 and Figure 7. The SYS_EN signal activates the
enable circuit, and the G/D Node signal represents the shared node between Q1 and Q2. This circuit was
tested with a 5-V SYS_EN signal and dual N/PFET Si1029X. The EN signal is the output of the circuit and
goes from VIN to VOUT properly enabling and disabling the device. The PG pin was used as an output
discharge to accelerate VOUT's return to 0V, when the IC is disabled.
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SYS_EN 5 V/div
G/D Node 5 V/div
EN 5 V/div
VOUT 5 V/div
Time 100 μs/div
Figure 6. Enable Sequence
SYS_EN 5 V/div
G/D Node 5 V/div
EN 5 V/div
VOUT 5 V/div
Time 10 ms/div
Figure 7. Disable Sequence
2.2
Enable Hysteresis Pin
The enable comparator typically has a built-in hysteresis of 50 mV. This hysteresis can be increased with
an external resistor divider connected to the EN_hys pin. The equations to calculate the external resistor
values for a buck converter are located in the applications section of the data sheet (Equations 6–10).
Because the device is now an inverting buck-boost converter, the equations must be modified to account
for VOUT, which is the GND terminal of the device. The VEN_TH_ON variable remains the same since there is
usually no negative output voltage when the part is enabled. The equations for the inverting buck-boost
topology are:
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æ
ö
æ
ö
R
R
VIN _ startup = VEN _ TH _ ON ´ ç 1 + EN1 ÷ = 1.2 V ´ ç 1 + EN1 ÷
è REN2 ø
è REN2 ø
æ
REN1
VIN _ stop = VEN _ TH _ OFF ´ ç 1 +
ç REN2 + REN _ hys
è
(4)
ö
æ
REN1
÷ + VOUT = 1.15 V ´ ç 1 +
÷
ç REN2 + REN _ hys
ø
è
ö
÷ + VOUT
÷
ø
(5)
In order for the VIN_stop threshold to operate, VIN_startup must be greater than VIN_stop - VOUT, where VOUT is a
negative value.
If the EN_hys pin is not being used to adjust the hysteresis, it can instead be used to provide an output
discharge path (explained in Section 2.4).
2.3
Power Good Pin
The TPS62125 has a built-in power good (PG) function to indicate whether the output voltage has reached
its appropriate level or not. The PG pin is an open-drain output that requires a pullup resistor. Because
VOUT is the IC ground in this configuration, the PG pin is referenced to VOUT instead of ground, which
means that the TPS62125 pulls PG to VOUT when it is low.
This behavior can cause difficulties in reading the state of the PG pin, because in some applications the
IC detecting the polarity of the PG pin may not be able to withstand negative voltages. The level shifter
circuit shown in Figure 8 alleviates any difficulties associated with the offset PG pin voltages by eliminating
the negative output signals of the PG pin. If the PG pin functionality is not needed, it may be left floating or
connected to VOUT without this circuit. Note that to avoid violating its absolute maximum rating, the PG pin
should not be driven more than 6 V above the negative output voltage (IC ground).
VCC
100k
100k
SYS_PG
D
Q2
NMOS
G
100k
S
D
Q1
NMOS
G
S
D
PG
Q3
NMOS
G
–VOUT
S
–VOUT
Inside TPS62125
Figure 8. PG Pin Level Shifter
Inside the TPS62125, the PG pin is connected to an N-channel MOSFET (Q3). By tying the PG pin to the
gate of Q1, when the PG pin is pulled low, Q1 is off and Q2 is on because its VGS sees VCC. SYS_PG is
then pulled to ground.
When Q3 turns off, the gate of Q1 is pulled to ground potential turning it on. This pulls the gate of Q2
below ground, turning it off. SYS_PG is then pulled up to the VCC voltage. Note that the VCC voltage must
be at an appropriate logic level for the circuitry connected to the SYS_PG net.
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This PG pin level shifter sequence is illustrated in Figure 9 and Figure 10. The PG signal activates the PG
pin level shifter circuit, and the G/D Node signal represents the shared node between Q1 and Q2. This
circuit was tested with a VCC of 5 V and dual NFET Si1902DL. The SYS_PG net is the output of the circuit
and goes between ground and 5 V, and is easily read by a separate device. The EN_hys pin was used to
accelerate VOUT's return to 0V, when the IC is disabled.
SYS_PG 5 V/div
G/D Node 5 V/div
PG 5 V/div
VOUT 5 V/div
Time 200 μs/div
Figure 9. PG Pin Level Shifter on Startup
SYS_PG 5 V/div
G/D Node 5 V/div
PG 5 V/div
VOUT 5 V/div
Time 20 ms/div
Figure 10. PG Pin Level Shifter on Shutdown
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2.4
Discharging the Output Voltage
If the TPS62125 is disabled in a light-load or no-load condition, the PG or EN_hys pins can accelerate
VOUT's return to 0 V by providing an additional discharge path. When the IC is disabled via the EN pin, the
PG and EN_hys pins are connected to the device ground (VOUT) through an internal MOSFET. Placing a
resistor between ground and the PG or EN_hys pins creates a discharge path to ground. If the EN_hys
pin is already being used to adjust the enable thresholds, do not use this pin as a discharge path. If the
PG pin is already being used, do not use this pin as a discharge path.
The added resistor should be sized to limit the current into the PG or EN_hys pin to a safe level. The PG
output typically has an internal resistance of 600 Ω and a 400-Ω minimum. The maximum sink current into
the PG pin is 10 mA. In order to limit the discharge current to the maximum allowable sink current into the
PG pin, an external resistor is calculated using:
R = (-VOUT / IPG_MAX) – RPG_MIN = (-VOUT / 0.01 A) – 400 Ω
(6)
Use a 100-Ω resistor for a –5-V output. Figure 11 and Figure 12 illustrate the purpose of the PG/EN_hys
pin discharge path – the output voltage returns to 0 V quicker with the discharge circuit.
EN 5 V/div
SW 5 V/div
VOUT 5 V/div
Icoil 100 mA/div
Time 5 s/div
Figure 11. Shutdown at No Load and No PG Pin Discharge
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Startup Behavior and Switching Node Consideration
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EN 5 V/div
SW 5 V/div
VOUT 5 V/div
Icoil 100 mA/div
Time 50 ms/div
Figure 12. Shutdown at No Load and PG Pin Discharge of 100 Ohm
3
Startup Behavior and Switching Node Consideration
Figure 13 shows the startup behavior in the inverting configuration. After EN is taken high, the device
starts switching after about a 50-µs delay. Due to the higher peak currents in the inverting topology,
current limit is frequently reached during startup. This is acceptable as long as the saturation current of the
inductor is chosen appropriately.
EN 5 V/div
SW 5 V/div
VOUT 5 V/div
Icoil 500 mA/div
Time 200 μs/div
Figure 13. Startup Behavior in the Inverting Configuration with VIN = 5 V and 120-mA load
Figure 13 also shows the SW node voltage as the device starts up. The voltage on the SW pin switches
from VIN to VOUT. As the high-side MOSFET turns on, the SW node sees the input voltage and as the lowside MOSFET turns on, the SW node sees the IC ground, which is the output voltage. As VOUT continues
to ramp down, the SW node low level follows it down.
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External Component Selection
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4
External Component Selection
The inductor and output capacitor need to be selected based on the needs of the application and the
stability criteria of the device. The selection criterion for the inductor and output capacitor is different from
the buck converter. See Section 4.3 for a discussion of stability.
4.1
Inductor Selection
When selecting the inductor value for the inverting buck-boost topology, the equations provided in Output
Current Calculations should be used instead of the ones provided in the data sheet. (IL(max) should be kept
below the minimum current limit value of the device (0.6 A) for a reliable design.) It is recommended to
size the inductor for the current limit level of the TPS62125, as this level is sometimes reached during
startup (shown in Figure 13). See Section 4.3 for the stability impact of the inductor selection.
4.2
Input Capacitor Selection
An input capacitor, CIN, is required to provide a local bypass for the input voltage source. A low ESR, X5R
or X7R ceramic capacitor is best for input voltage filtering and minimizing interference with other circuits.
For most applications, a 10-µF ceramic capacitor is recommended from VIN to ground (system ground, not
–VOUT). The CIN capacitor value can be increased without any limit for better input voltage filtering.
For the inverting buck-boost configuration of the TPS62125, it is not recommended to install a capacitor
from VIN to VOUT. Such a capacitor, if installed, provides an AC path from VIN to VOUT. When VIN is applied
to the circuit, this dV/dt across a capacitor from VIN to VOUT creates a current that must return to ground
(the return of the input supply) to complete its loop. This current might flow through the internal low-side
MOSFET's body diode and the inductor to return to ground. Flowing through the body diode pulls the SW
pin and VOS pin more than 0.3 V below IC ground, violating their absolute maximum rating. Such a
condition might damage the TPS62125 and is not recommended. Therefore, a capacitor from VIN to VOUT
is not needed or recommended. If such a capacitor (CBP) is present, then a Schottky diode should be
installed on the output, per Figure 14. Startup testing should be conducted to ensure that the VOS pin is
not driven more than 0.3 V below IC ground when VIN is applied.
CIN
L
TPS62125
2
VIN
3
CBP
4
1
VIN
SW
EN
FB
EN_HYS
VOS
GND
PG
ETPAD
9
7
5
6
RFB1
8
COUT
RPG
D1
RFB2
-VOUT
Figure 14. If Installing CBP, Installing Schottky D1 is Required
The AC path through CBP might also worsen the line transient response. If strong line transients are
expected, the output capacitance should be increased to keep the output voltage within acceptable levels
during the line transient.
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External Component Selection
4.3
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Selecting L and COUT for Stability
The switch node, inductor current, and the output voltage ripple during steady state are signals that need
to be checked first for the stability of the system. Oscillations on the output voltage or the inductor current
as well as jitter on the switch node are good indicators of the instability of the system. Figure 22 shows
both the switch node and output voltage ripple of this topology. Load transient response is another good
test for stability, as described in the SLVA381 application report.
The recommended nominal inductor and output capacitor values to use for this topology are in the range
of 15 µH to 22 µH and from 22 µF to 100 µF, respectively. In this application report, a 22-µH inductor and
2 x 22-µF capacitors are used.
The inverting buck-boost topology contains a Right Half Plane (RHP) zero which significantly and
negatively impacts the control loop response by adding an increase in gain along with a decrease in
phase at a high frequency. This can cause instability. Equation 7 estimates the frequency of the RHP
zero.
f(RHP) =
-(1 - D)2 ´ VOUT
(D ´ L ´ IOUT ´ 2 ´ p)
(7)
It is recommended to keep the loop crossover frequency to, at most, 1/4th of the RHP zero frequency.
Doing this requires either decreasing the inductance to increase the RHP zero frequency or increasing the
output capacitance to decrease the crossover frequency. Note that the RHP zero frequency occurs at
lower frequencies with lower input voltages, which have a higher duty cycle. SLVA465 explains how to
measure the control loop of a DCS-Control™ device while Figure 15 shows the bode plot of Figure 16.
Figure 15. Bode Plot with VIN = 5 V and 120-mA Load
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5
Typical Performance and Waveforms
The application circuit shown in Figure 16 is used to generate the data presented in Figure 17 – Figure 22.
To reach the total effective capacitance of 22 µF, the design used 2 x 22-µF Murata
[GRM21BR61A226ME44L] capacitors, 2 × 22-µF Samsung [CL21A226MAQNNNE] capacitors, or 3 × 10µF TDK [C2012X7R0J106K125AB] capacitors. For a 5-V output, loss of capacitance from the DC bias
effect can be significant. Unless otherwise specified, VIN = 5 V and VOUT = –5 V. The inductor used in the
tested circuit is a 22-µH Coilcraft [LPS5030-223].
CIN
10uF
L
22uH
TPS62125
2
VIN
3
4
1
VIN
SW
EN
FB
EN_HYS
VOS
GND
PG
ETPAD
9
7
5
RFB1
2.00M
6
COUT
2x 22uF
8
100
RPG
RFB2
383k
-VOUT
Figure 16. Schematic of the Tested Circuit
100%
5 VIN, ±5 VOUT
95%
90%
Efficiency (%)
85%
80%
75%
70%
65%
60%
55%
50%
0.1
1
10
100
1000
IOUT (mA)
C003
Figure 17. Efficiency versus Load Current with VOUT = –5 V
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Typical Performance and Waveforms
-4.95
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IOUT = 80 mA
-4.96
-4.97
Output Voltage (V)
-4.98
-4.99
-5
-5.01
-5.02
-5.03
-5.04
-5.05
3
4
5
6
7
8
9
10
11
12
Input Voltage (V)
C001
Figure 18. Line Regulation
-4.95
5 VIN
-4.96
-4.97
Output Voltage (V)
-4.98
-4.99
-5
-5.01
-5.02
-5.03
-5.04
-5.05
0.1
1
10
100
IOUT (mA)
C002
Figure 19. Load Regulation
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VOUT 50 mV/div
Icoil 200 mA/div
0 to 120 mA Load Step
IOUT 100 mA/div
Time 10 μs/div
Figure 20. Load Transient Response with VIN = 5 V
SW 5 V/div
VIN 20 mV/div
Icoil 200 mA/div
Time 2 μs/div
Figure 21. Input Voltage Ripple with VIN = 5 V and 120-mA Load
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Using the TPS62125 in an Inverting Buck-Boost Topology
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15
Typical Performance and Waveforms
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SW 5 V/div
VOUT 20 mV/div
Icoil 200 mA/div
Time 2 μs/div
Figure 22. Output Voltage Ripple with VIN = 5 V and 120-mA Load
SW 5 V/div
VOUT 20 mV/div
Icoil 200 mA/div
Time 5 μs/div
Figure 23. Output Voltage Ripple with VIN = 5 V and 10-mA Load
16
Using the TPS62125 in an Inverting Buck-Boost Topology
Copyright © 2012–2014, Texas Instruments Incorporated
SLVA514B – May 2012 – Revised July 2014
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Conclusion
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VIN: 3–10 V
2 V/div
VOUT 20 mV/div
Icoil 200 mA/div
Time 100 μs/div
Figure 24. Line Transient Response with 120-mA Load
6
Conclusion
The TPS62125 can be configured as an inverting buck-boost converter to generate a negative output
voltage. The inverting buck-boost topology changes some system characteristics, such as input voltage
range and maximum output current. This application report explains the inverting buck-boost topology and
how to select the external components with the changed system characteristics. Measured data from the
example design are provided.
SLVA514B – May 2012 – Revised July 2014
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Using the TPS62125 in an Inverting Buck-Boost Topology
Copyright © 2012–2014, Texas Instruments Incorporated
17
References
7
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References
1.
2.
3.
4.
5.
6.
7.
8.
9.
Creating an Inverting Power Supply From a Step-Down Regulator (SLVA317)
TPS62125 Datasheet (SLVSAG7)
Using a Buck Converter in an Inverting Buck-Boost Topology (SLYT286)
Using the TPS5430 in an Inverting Buck-Boost Topology (SLVA257)
Using the TPS6215x in an Inverting Buck Boost Topology (SLVA469)
Simplifying Stability Checks (SLVA381)
Robert W. Erickson: Fundamentals of Power Electronics, Kluwer Academic Publishers, 1997
How to Measure the Control Loop of DCS-Control™ Devices (SLVA465)
DCS-Control™ Landing Page: www.ti.com/dcs-control
Revision History
Changes from A Revision (September 2013) to B Revision .......................................................................................... Page
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18
Changed abstract, reworded. ............................................................................................................ 1
Changed Figure 1 and 2, changed descriptions of both figures in the first paragraph of the Concept section. .............. 2
Changed Figure 3. ........................................................................................................................ 3
Changed equations in Output Current Calculations section. ........................................................................ 3
Changed Figure 4, Maximum Output Current versus VIN ........................................................................... 4
Changed entire Digital Pin Configurations section; headings, text, equations, and images. .................................... 4
Changed entire External Component Selection section; headings, text, equations, and images. ............................ 11
Changed entire Typical Performance and Waveforms section; headings, text, equations, and images. .................... 13
Added Output Voltage Ripple VIN = 5 V and 10-mA Load image. ................................................................. 16
Added references to the References section......................................................................................... 18
Revision History
SLVA514B – May 2012 – Revised July 2014
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