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Texas Instruments An Accurate Thermal-Evaluation Method for the TLV62065 Application notes
Application Report
SLVA658 – June 2014
An Accurate Thermal-Evaluation Method for the TLV62065
Yangwei Yu
............................................................................... Boost and Cost Effective Buck Solutions
ABSTRACT
The increase of power density has resulted in the need for accurate measurement of die junction
temperature. This application report is a basic overview of thermal evaluation and provides an accurate
evaluation method of junction temperature in a real application. The evaluation method described in this
application is confirmed with bench measurements. This method is proven to be easy to use and have
good accuracy and relevance to real applications.
Contents
Introduction ................................................................................................................... 2
Thermal Metrics in the Data Sheet ........................................................................................ 2
2.1
JEDEC PCB Specifications ........................................................................................ 2
2.2
Estimating the Junction Temperature by Thermal Metric ..................................................... 2
2.3
Accurate Thermal Measurement of the Die Level .............................................................. 5
3
Conclusion .................................................................................................................. 10
4
About the Author ........................................................................................................... 10
5
References .................................................................................................................. 11
Appendix A
PCB Overview ..................................................................................................... 12
1
2
List of Figures
1
Measurement of ΨJx and RθJx ............................................................................................... 3
2
TLV62065 Thermal Measurement ......................................................................................... 4
3
Thermal Calculation with RθJx and ψJx ..................................................................................... 5
4
P-N Junction Forward-Voltage Linearity of Temperature ............................................................... 6
5
TLV62065 Mode Pin P-N Junction Measurement ....................................................................... 6
6
TLV62065 Mode-Pin Diode Voltage Versus Temperature ............................................................. 7
7
TLV62065 Mode Pin and Thermal Sense Location ..................................................................... 8
8
TLV62065 Die Thermal Simulation 1-W Power Loss ................................................................... 9
9
TLV62065 Die Thermal Simulation 0.5-W Power Loss ................................................................. 9
10
TLV62065 FET and Mode Pin Temperature............................................................................ 10
11
TLV62065EVM
.............................................................................................................
12
List of Tables
1
Critical PCB Design Factors for JEDEC 1s and 2s2p Test Boards ................................................... 2
2
TLV62065 Thermal Metrics ................................................................................................. 2
3
TLV62065 Specifications
4
5
...................................................................................................
Power Loss Versus Load ...................................................................................................
TLV62065 Temperature Measurement (1-W Loss) .....................................................................
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5
9
1
Introduction
1
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Introduction
As power densities increase, the amount of heat generated on the silicon imposes significant challenges
to thermal management. Temperature becomes a more dominant factor in device performance and
reliability. Therefore, the meticulously assessment of the thermal-management design of each device is
important of the device to perform safely under the intended operating conditions and environments.
However, thermal evaluation in the system-level of an electronic circuit board is generally a difficult task.
This type of evaluation requires knowledge of the major heat dissipaters in the system, the environmental
conditions, some theoretical calculations, and some amount of guesswork. Because of this guesswork and
uncertainty, the tolerance on accurate junction-temperature measurement and prediction is typically poor.
The purpose of this application report is to minimize the guesswork required and deliver a more accurate
method of thermal evaluation.
2
Thermal Metrics in the Data Sheet
2.1
JEDEC PCB Specifications
Many thermal metrics exist for semiconductor and integrated circuit (IC) packages. These thermal metrics
are often misapplied by users who try to use the metrics to estimate junction temperatures in their
systems. The thermal resistance (RθJA which is from junction to ambient and RθJC which is from junction to
case) in a data sheet is a measurement of the thermal performance of an IC package mounted on a
specific test board as listed in Table 1. Sometimes, however, the conditions outlined in the JEDEC
documentation are not followed and the deviations from the standards are not documented. These test
board variations can have an effect on the measured values of thermal resistance. Therefore, unless test
conditions are reported with the RθJA and RθJC value, these conditions should be used of thermal
evaluation or calculation. Ideally, the thermal performance of a TI device can be compared to a device
from another company which is true when both companies use a standardized test to measure RθJA, such
as that specified by JEDEC in the EIA/JESD 51 series of documents. The TLV62065 device used in this
application report follows the high-K standard.
Table 1. Critical PCB Design Factors for JEDEC 1s and 2s2p Test Boards
TEST BOARD DESIGN
Trace thickness
JEDEC HIGH-K 2s2p (inch)
0.0028
0.0028
Trace length
0.98
0.98
PCB thickness
0.062
0.062
4
4
PCB width
PCB length
Power-plane and ground-plane thickness
2.2
JEDEC LOW-K 1s (inch)
4.5
4.5
No internal copper planes
0.0014 (2 planes)
Estimating the Junction Temperature by Thermal Metric
This section defines specific thermal metrics. Table 2 lists the TLV62065 thermal metrics.
Table 2. TLV62065 Thermal Metrics
THERMAL METRIC
2
TLV62065
RθJA
Junction-to-ambient thermal resistance
65.3
RθJC(top)
Junction-to-case (top) thermal resistance
74.2
RθJB
Junction-to-board thermal resistance
35.4
ψJT
Junction-to-top characterization parameter
12.8
ψJB
Junction-to-board characterization parameter
2.2
RθJC(bot)
Junction-to-case (bottom) thermal resistance
36
An Accurate Thermal-Evaluation Method for the TLV62065
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UNIT
°C/W
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Thermal Metrics in the Data Sheet
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Thermal Resistance — is the temperature drop from the packaged device to the primary heat-sink per
watt of power dissipated in the package. The primary heat sink may be the ambient air, the PCB
itself, or a heat sink that is mounted on the package. Thermal resistance is denoted by the symbol
RθJx (or ThetaJx) where x denotes the external reference point where the temperature is measured.
Characterization Parameter — is different from thermal resistance because the referenced external
temperature is not the ultimate heat sink for the package. A thermal characterization parameter can
be used to estimate junction temperatures for a device in the end-use environment. A thermal
parameter is denoted by the symbol ψJx (or PsiJx) where x denotes the referenced point where the
temperature is measured.
Figure 1 shows the measurement of ψJT and RθJC.
Power dissipation = 2 W
Cu-plate at constant temperature = 25°C
0.5 W
Case temperature
monitor
Junction temperature
monitor
0.25 W
Device
Pad
PWB
2W
Device
Pad
PWB
1.25 W
RJC
JT
Power is dissipated in all directions
All of the power is forced to dissipate
only in one direction ² UPWARD
JT
TJ ± TT
TJ TC
P
T
J
P
B
RTJC
TJ ± TC
TJ TC
P
C
A
J
B
A
NOTE: A = Ambient, B = Board, C = Case, J = Junction, P = Pin
Figure 1. Measurement of ΨJx and RθJx
RθJx is a variable function of the package and many other system-level factors such as the design and
layout of the printed circuit board (PCB) on which the device is mounted. In effect, the test board is a heat
sink that is soldered to the leads of the device. Changing the design or configuration of the test board also
changes the heat flow and therefore the measured value of RθJx.
The use of Equation 1 to calculate RθJx results in highly inaccurate values.
TJ = Tx + RθJx × P
where
•
•
•
TJ = junction temperature
TX = the point of the temperature to be calculation
P = power
(1)
RθJx is not a characteristic of only the package but of the package, PCB, and other environmental factors.
Best practice is to use RθJx as a comparison of the thermal performance of a package between different
companies. For example, if TI reports a RθJx of 100°C/W for a similar package for which a competitor
reports 125°C/W, the TI device will likely run 20% cooler in an application than the device of the
competitor.
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Thermal Metrics in the Data Sheet
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In an attempt to provide a more practical thermal metric to estimate junction temperatures in real
application from measured case and board temperatures, a new thermal metric, ΨJx, has been adopted by
the industry (EIA/JESD 51-2). ΨJx is defined as dividing the thermal gradient between the junction
temperature and surface temperature by the dissipated power. The heat energy generated by the test die
is allowed to flow normally along preferential thermal conduction paths. The quantity of heat flowing from
the die to the surface temperature is actually unknown in the measurement, but is assumed to be the total
power of the device for the purposes of ΨJx calculation. However, this assumption is invalid and when
calculated with Equation 2, ΨJx becomes a very useful number because the experimental configuration is
much like the application environment of the IC package. As such, the amount of energy flowing from the
die to the top of the package during test is similar to the partitioning of the energy flow in an application
environment.
TJ = Tx + ΨJx × P
(2)
As previously mentioned, ΨJx is used to accurately estimate the junction temperature of the semiconductor
device. If the top case temperature and component power dissipation can be estimated, the junction
temperature can be calculated using Equation 2.
The TLV62065 device was selected as for verification. Table 3 lists the TLV62065 specifications based on
the standard evaluation module (EVM). See Appendix A for an overview of the TLV62065EVM.
Table 3. TLV62065 Specifications
PARAMETER
VALUE
VI
Input voltage
3.3 V
VO
Output voltage
1V
IO
Output current
1 A to 2 A
NOTE: The junction-temperature measurement is based on the ratio of the P-N junction forward
voltage as described in the following paragraph.
102
100
Temperature (qC)
98
96
94
92
90
88
TA 85qC TDIE_Mode Pin (qC)
TA 85qC TC(top) (qC)
86
84
1
1.1
1.2
1.3
1.4 1.5 1.6 1.7
Output Current (A)
1.8
1.9
2
D001
Figure 2. TLV62065 Thermal Measurement
The power loss of the TLV62065 device is obtained from the overall efficiency performance and because
the assumed power loss is only generated by the device. Table 4 lists the tested results of the power loss
for the specification of VI = 3.3 V and VO = 1 V.
4
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Thermal Metrics in the Data Sheet
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Table 4. Power Loss Versus Load
POWER LOSS (W)
LOAD (A)
0.429
1
0.591
1.2
0.808
1.5
1.151
1.8
1.390
2
Table 2 lists the thermal resistance and characterization parameters. Based on these parameters,
Figure 3 shows the various calculations based on the measured ambient and top case temperatures. The
calculation using ψJT is much closer to the real measured data.
180
TA 85°C T(DIE) (°C)
TA 85°C TC (°C)
TJ(1) (°C)
TJ(2) (°C)
TJ(3) (°C)
Temperature (qC)
160
140
TJ(1) = TA + θJAx × Ptot
TJ(2) = TC + θJCx × Ptot
120
100
TJ(3) = TC + ΨJTx × Ptot
80
60
1
1.1
1.2
1.3
1.4 1.5 1.6 1.7
Output Current (A)
ΨJT provides
the most
accuracy.
1.8
1.9
2
D002
Figure 3. Thermal Calculation with RθJx and ψJx
2.3
2.3.1
Accurate Thermal Measurement of the Die Level
P-N Junction Versus Temperature
The ideal measurement method of junction temperature is to monitor the device temperature as close as
possible to the heat source. One method is to place a temperature sensor very close to the semiconductor
junction and measure the sensor output signal. This method is straightforward, but there are physical
limitations to this technique because of the size of the sensor inside the die.
A better method is to use the junction as a temperature sensor. With most materials, a strong correlation
exists between the forward voltage drop and the temperature of that junction. This relationship is nearly
linear for most devices. Equation 3 is the mathematical expression.
TJ = T(O) + m × VF
where
•
•
•
•
TJ = junction temperature (°C)
m = slope (°C/V)
VF = forward voltage drop
T(O) = Temperature at 0°C
(3)
NOTE: The slope, m, is a device-specific parameter.
At a given temperature, TJ(x), the semiconductor junction will have a specific forward voltage drop, VF(x). If
VF is measured at two different temperatures, the slope, m, and the intercept for a particular junction can
be measured as shown in Figure 4.
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Thermal Metrics in the Data Sheet
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Internal Sense
+
±
Voltage of P-N (V)
+ V(P-N) -
V(P-N) vs
Temperature
VF(1)
VF(2)
VF(3)
TJ(1) = ambient
TJ(2)
TJ(3)
Junction Temperature (°C)
Figure 4. P-N Junction Forward-Voltage Linearity of Temperature
2.3.2
TLV62065 Mode-Pin P-N Junction Voltage Versus Temperature
For the TLV62065 device, the body diode (or ESD diode) of the MODE pin (from the PGND pin to the
MODE pin) can be used to measure the die temperature. The pins for measurement should not affect the
normal application.
L1
1 µH
TLV62065
VI
C1
10 µF
PVIN
SW
AVIN
FB
VO
R1
VF
EN
C2
10 µF
MODE
AGND
R2
PGND
R(V)
30 k
0.1 mA
Figure 5. TLV62065 Mode Pin P-N Junction Measurement
6
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Thermal Metrics in the Data Sheet
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For this test, the device-under-test (DUT) is placed in a temperature chamber and connected to the power
supply and measurement equipment. Place the DUT into an environmental chamber and set the chamber
to an initial temperature (typically at room temperature, such as 25°C). After the junction reaches the
thermal equilibrium (monitor the temperature and voltage until the temperature is stable), a very low
current is sourced into the DUT and the voltage drop of the P-N junction (from the PGND pin to the MODE
pin) is measured.
NOTE: The amplitude of the current that sinks into P-N junction is very important. Delivering a larger
amount of power (too much current) may skew the results by heating the junction.
For this setup, use a 100-µA input current (typical), for which the resulting additional temperature could be
negligible. The temperature is then increased to a higher value (50°C for example) and the DUT is allowed
to reach thermal equilibrium. Then the current is delivered. Voltages recorded at this temperature are
labeled the VF(1) at TJ(1) (40°C for this example). These steps can be repeated for a number of values and
then plotted as voltage versus junction temperature as shown in Figure 6.
Mode Pin Diode Voltage (V)
0.6
VF PG (V)
Interpolation (V)
0.55
0.5
0.45
0.4
0.35
0.3
-50
0
50
100
Temperature (qC)
150
200
D003
Figure 6. TLV62065 Mode-Pin Diode Voltage Versus Temperature
Equation 4 is a linearized equation for the junction temperature versus forward voltage of the TLV62065
device based on the measured data and curve.
TJ (°C) = –0.8493 × VF (mV) + 397.78 (mV)
(4)
To evaluate other scenarios, such as variations in PCB layout or environment temperature, measure VF
and use Equation 4 to calculate the actual junction temperature.
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Thermal Metrics in the Data Sheet
2.3.3
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Temperature Gradient in the Die
Typically, the temperature is considered to be constant throughout the entire die. However, distinct
temperature gradients inside the die have been discovered, specifically in devices with increasing power
density.
In the die level, the hottest spot is near the power FET which contributes the highest percentage of the
heat. The thermal sensor is also located directly next to the power FET to detect the hottest spot in the
application. The most direct method to detect this hot spot is to measure the FET temperature; however,
this method has a practical measurement limitation. In real practice, the pin that does not impact normal
operation is typically used to monitor the die temperature (such as the MODE pin of the TLV62065
device). Then, temperature gradients between the measured pin and the hottest spot (or thermal sensor)
should be considered in order to minimize the tolerance of the real FET temperature. Figure 7 shows the
measured pin and thermal sensor (reflecting the FET temperature) location inside the die. A thermal
resistance causes the temperature gap.
Power FET
Control Circuitry
Thermal
Sense
Mode
Distance: around 1.1 mm
Figure 7. TLV62065 Mode Pin and Thermal Sense Location
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2.3.3.1
Thermal Simulation Verification
For a 1-W power loss in the die, the FET temperature (thermal sensor) of the TLV62065 device is 89.29°C
and the temperature of the MODE pin is 78.32°C (see Figure 8).
For a 0.5-W power loss, the FET temperature (thermal sensor) is 58.25°C and the temperature of the
MODE pin is 52.75°C (see Figure 9).
TLV62065
FET (thermal sensor)
MODE pin
FET (thermal sensor)
MODE pin
TLV62065
Temperature (°C)
90
Temperature
(°C)
Temperature (°C)
90
90
87
87
87
84
84
84
81
81
81
78
78
78
75
75
Figure 8. TLV62065 Die Thermal Simulation
1-W Power Loss
Figure 9. TLV62065 Die Thermal Simulation
0.5-W Power Loss
75
2.3.3.2
Bench Measurement Verification
At a no-load condition, no power loss is generated in the die and therefore the temperature gap between
the FET and MODE pin is almost zero. Heat up the board until thermal protection is triggered (suddenly
decreasing the input current) and record the temperature using the symbols T(MODE1) and T(FET1).
For the given power loss, the thermal-sense trip temperature is assumed to be of less variation. The
temperature of the MODE pin can be read by measuring the P-N junction voltage. Record the temperature
as T(MODE2) and T(FET2) (equal with T(FET1)) when thermal protection is triggered. Table 5 lists the
measurement of the TLV62065EVM as a result of no load and 1-W power loss.
Table 5. TLV62065 Temperature Measurement (1-W Loss)
NO POWER LOSS
1-W POWER LOSS
T(FET1/FET2) (°C)
T(MODE1) (°C)
T(MODE2) (°C)
147
147
137.5
Based on the simulation result and bench verification, the temperature gradient is approximately 9°C/W
between the MODE pin and the thermal sensor (hottest spot in die).
With the given power loss, use Equation 5 to calculate the thermal sensor temperature.
T(FETx) = T(MODEx) + 9°C/W × Ptot
where
•
Ptot = total power loss
(5)
The power loss can be available based on the overall efficiency of the DC-DC converter. The thermal
evaluation would then have less tolerance.
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Conclusion
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120
Temperature (qC)
110
100
90
80
70
TA 85qC TDIE_FET (qC)
TA 85qC TDIE_Mode Pin (qC)
60
1
1.1
1.2
1.3
1.4 1.5 1.6 1.7
Output Current (A)
1.8
1.9
2
D004
Figure 10. TLV62065 FET and Mode Pin Temperature
With this method, the FET junction temperature of the TLV62065 device is predicted again using the
power loss listed in Table 4. The FET temperature is selected based on Figure 10 and the tolerance is
lowered further.
3
Conclusion
The thermal metric listed in the device data sheet can be used to estimate the junction temperature while
suffering from a large tolerance. To validate the thermal evaluation with less tolerance, the operating
junction temperature can be measured directly using the P-N junction linearity with forward voltage.
Additionally, the temperature gradient inside the die should be considered. With the method described in
this application report, the hot spot across the entire die can be predicted more accurately. The method
described in this document was evaluated for accuracy, ease of use, and relevance to a real application.
The simulation and bench verification is available using the TLV62065 as an example.
4
About the Author
The author would like to thank Paulo Martin, Oliver Nachbaur, and Gavin Jin for their support on this
document.
10
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References
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5
References
1.
2.
3.
4.
PowerPAD™ Thermally Enhanced Package, SLMA002
Semiconductor and IC Package Thermal Metrics, SPRA953
Using Forward Voltage to Measure Semiconductor Junction Temperature (Chonko 2006)
Validation and Application of Different Experimental Techniques to Measure Electronic Component
Operating Junction Temperature by Ohan, Rodgers, Fager, Lehtiniemi, Eveloy, Tiilikka, and Rantala in
IEEE Transactions on Components and Packaging Technology, Vol 22, No. 2, June 1999
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Appendix A PCB Overview
All of the measurements in this application report are based on the standard evaluation module, EVM, for
the TLV62065 device. The printed circuit board (PCB) is made up of four layers with a 2-oz copper top
layer and a 2-oz copper bottom layer. The two inner layers are 1-oz copper each.
38,10 mm
(1.50 inches)
45,72 mm
(1.80 inches)
Figure 11. TLV62065EVM
12
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