Texas Instruments | 5-W USB Flyback Design Example Using the UCC28722 | Application notes | Texas Instruments 5-W USB Flyback Design Example Using the UCC28722 Application notes

Texas Instruments 5-W USB Flyback Design Example Using the UCC28722 Application notes
Application Report
SLUA700 –January 2014
UCC28722/UCC28720 5W USB BJT Flyback Design
Example
Michael O’Loughlin
Senior System Solutions Engineer
Introduction:
In USB and isolated low power converter designs-quasi resonant and discontinuous conduction mode
flyback converter topologies are a popular choice, due to their low parts count and relatively low cost.
To reduce the cost even further, TI has developed a quasi-resonant/discontinuous current mode flyback
controller with primary-side control. This removes the need for optocoupler and TL431 feedback
circuitry reducing the cost of these low power designs even more. The control methodology uses a
combination of primary peak current amplitude modulation (AM) and frequency modulation (FM) to
regulate the output current and voltage please refer to data sheet [1] for controller details. This design
example is a theoretical design that shows how to use the UCC28722 in a 5W USB application. The
calculations were used to design the UCC28720EVM-212 reference design [2]. Note the UCC28722 is
cost reduced version of the UC28720. To reduce the cost of the UCC28722 the internal startup circuit
was removed. This device requires a trickle charge resistor from the bulk input voltage during power
up.
Design Specifications:
Description
RMS Input Voltage
Minimum
90 (VINMIN)
Typical
115/230
4.75
5 (VOUT)
No Load Input Power
Output Voltage
Output Voltage Ripple
Output Load Step
(0.1 to 0.6A), (0.6 to 0.1A)
Output Current
Switching Frequency
Full Load Efficiency
Maximum
265 (VINMAX)
50 (PINL)
5.25
100 (VRIPPLE)
6.0
4.1 (VOTRM)
1(IOUT)
74 kHz (fMAX)
73(η)
74
Units
V
mW
V
mVpp
V
A
kHz
%
Table 1, Design Specifications
1
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Functional Schematic:
DG
T1
RL
DA
470uH
DC
CA
VIN
NP
CB
DZ
DD
DB
RS
VOUT+
NS
DF
COUT
RZ
10.0k
RT
CS
1nF
DE
RS1
T1
RF1
22.5
CDD
4.7uF
VOUTRG1
QA
10
DF
30V
RG2
10k
UCC28722
2
VDD
DRV
3
6
VS
CS
4
5
GND
CBC
1
RCS
RLC
NA
RS2
RCBC
Note RT is not required on UCC28720
Figure 1, UCC28722 5W Offline Flyback Functional Schematic
Selecting RCBC Resistor:
In this design cable compensation was not used and resistor R8 was not populated.
Please refer to the data sheet on how to setup cable compensation [1].
Initial Power Budget:
To meet the efficiency (η) goal an initial power loss budget (PBUDGET) needs to be set.
POUT  VOUT  I OUT  5V 1A  5W
P 
PBUDGET   OUT   POUT  1.849W
  
Bridge Rectifier Selection (DA ..DD):
For this design a 600V, 0.8A, bridge rectifier from Diodes Incorporated was chosen for the bridge
rectifier diode (DA.. DD), part number HD06.
VFDA  1V , forward voltage drop of bridge rectifier diode (VFDA)
2
UCC28722/UCC28720 5W USB BJT Flyback Design Example
SLUA700
I DA
POUT


5W



  0.75  85mA , bridge rectifier average diode current (IDA)



2
2
 VINMIN  2  90V  2


PDA  VFDA  I DA  85mW , estimate power dissipated in bridge rectifier diode (PDA)
Estimate remaining power budget based on bridge rectifier loss.
PBUDGET  PBUDGET  2  PDA  1.68W
Transformer Calculations (T1):
Transformer demagnetizing duty cycle (DMAG) is fixed to 42.5% based on the UCC28720/2 control law
methodology [1].
DMAG  0.425
TR is the estimated period of the LC resonant frequency at the switch node.
TR  2us
Calculate maximum duty cycle (DMAX):
DMAX  1  DMAG  f MAX
TR
2s
 1  0.425  74kHz
 0.501
2
2
Calculate transformer primary peak current (IPPK) based on a minimum flyback input voltage. This
calculation includes a factor of 0.6 to account for the reduction in flyback input voltage caused by the
ripple voltage across the input capacitors (CA and CB).
I PPK 
2  POUT
2  5W

 358mA
 VINMIN 2  0.6  DMAX 0.75  90V 2  0.6  0.47
Selected primary magnetizing inductance (LPM) based on minimum flyback input voltage, transformer,
primary peak current, efficiency and maximum switching frequency (fMAX).
2  POUT
LPM 

I
2
PPK
 f MAX
2  5W
0.75

 1.44mH
350mA2  74kHz
UCC28722/UCC28720 5W USB BJT Flyback Design Example
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VQA _ CE( SAT )  1V , estimated voltage drop across transistor during conduction
VRCS  0.78V , voltage drop across current sense resistor
VDG  0.6V , estimated forward voltage drop across output diode
Calculate transformer turns ratio primary to secondary (a1) based on volt-second balance.
Note in the following equation LSM is secondary magnetizing inductance.
a1 
NP

NS


DMAX  VINMIN 2  0.6  VQA _ CE ( SAT )  VRCS
LPM

 15.7
LSM
DMAG  VOUT  VDG 
VDDMIN ( on)  8.15V , UCC28722 minimum VDD voltage before UVLO turnoff.
VDE  0.6V , estimated auxiliary diode forward voltage drop
VOUT _ INIT  2V , Minimum voltage on the output when adapter is connected to a device
with a depleted battery.
Calculate transformer auxiliary to secondary turns ratio (a2)
a2 
V
 VDE
NA
 DDMIN
 3.37
N S VOUT _ INIT  VDG
Transformer primary RMS current (IPRMS)
I PRMS  I PPK
DMAX
 146mA
3
Transformer secondary peak current RMS current (ISPK)
I SPK 
4
POUT  2
 4.71A
VOUT  DMAG
UCC28722/UCC28720 5W USB BJT Flyback Design Example
SLUA700
Transformer secondary RMS current (ISRMS)
I SRMS  I SPK
DMAG
 1.77 A , transformer secondary RMS current
3
Estimate power dissipated by the UCC28722 IC (PIC)
VDD  VOUT  a2  16.83V , Estimated VDD
I RUN  2mA , Typical IC run current
I DRS ( MAX )  37mA , Average Maximum Drive Current
I DRS ( MIN )  19mA , Average Minimum Drive Current
I DRS ( AVG ) 
I DRS ( MAX )  I DRS ( MIN )
2
 DMAX  14mA , Average Base Drive Current
PIC  VDD I RUN  I DRS ( AVG )   270mW
Calculate auxiliary winding peak current (IAPK)
I APK 
(VOUT
PIC  2
 67mA
 VDE )  a2  DMAG
Calculate auxiliary winding RMS current (IARMS)
I ARMS  I APK
DMAG
 25mA
3
For this transformer we allow for 3% efficiency loss from the transformer (PT1)
PT 1  POUT  0.03  150mW
Recalculate remaining power budget
PBUDGET  PBUDGET  PT 1  1.26W
A Wurth Electronik transformer was designed for this application, part number 7508110151, which has
the following specifications:
UCC28722/UCC28720 5W USB BJT Flyback Design Example
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a1 = 15.42
a2 = 3.2
LPM  1.5mH
LLK  20uH , primary leakage inductance
Input Capacitor Selection (CIN = CA + CB):
Calculate input capacitor charge time (tCH) based on 40% input capacitor ripple voltage.
tCH
V
2  VINMIN 2  0.6 

1  sin 1  INMIN

V
2
INMIN

  3.4ms

4  47 Hz
Calculate flyback average primary current (IPT1) during input capacitor discharge.
I PT 1
POUT
POUT

  VINMIN 2   VINMIN 2  0.6

 72mA
2
Calculate total input capacitance (CIN) based on minimum flyback input voltage and 40% ripple voltage
across the input capacitor.
TRL 
1
 11ms , longest period of the rectified line voltage
2  47 Hz
VINRIPPLE  VINMIN  2  0.4  50.9V , input ripple to the flyback converter
C IN 
I PT 1 TRL  t CH 
 10uF
VINRIPPLE
C A  CB 
6
CIN
 5uF
2
UCC28722/UCC28720 5W USB BJT Flyback Design Example
SLUA700
Calculate input capacitor (CA) RMS current (IC_ARMS) based on 40% input capacitor ripple voltage.
I CINP 
2  (C A  C B )  VINMIN 2  0.4
 311mA , peak input capacitor charge current (ICINP)
tCH
I CA _ RMS
I
  CINP
 2
2
tCH
3  TRL
  I CINP
 
  2
 
TRL  tCH
3  TRL
2
  I PT 1  2
 
  2   82mA

Estimate of capacitor CB‘s low frequency (1/TRL) RMS current ( I CB _ LFRMS )
I CB _ LFRMS  I CA _ RMS
Estimate of CB‘s high frequency RMS current (ICB_HFRMS)
I CB _ HFRMS

  I PPK

2
DMAX
3
2
 
DMAX 
   I PPK
  116mA
 
2


Estimate of CB’s total RMS current (ICB_RMS)
I CB _ RMS 
I
  I
2
CB _ LFRMS

2
CB _ HFRMS
 142mA
For this design 4.7uF, 400V electrolytic capacitors, from Nichicon part number UVR2G4R7MPD were
chosen for the design.
CA  CB  4.7uF
These capacitors had a measured ESR of 5 ohms at 74 kHz
ESRCA = ESRCB = 5Ω
Recalculate remaining power budget based on power dissipation by the ESRs in the input capacitors.
PBUDGET  PBUDGET  I CA _ RMS   ESRCA  I CB _ RMS   ESRCB  1.126W
2
2
UCC28722/UCC28720 5W USB BJT Flyback Design Example
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Filter Inductor (LA):
Filter inductor (LA) is used for EMI filtering. In this design it is just a place holder and the design has
not been optimized for EMI. 470uH inductor from Bourns was chosen, part number RLB0608-471KL.
This inductor has a DCR of 6.5 ohms.
DCR  6.5
Recalculate power budget based on DCR losses
PBUDGET  PBUDGET  I PRMS   DCR  0.987W
2
Fusible Resistor (RL):
To limit the inrush current during power and for safety a 10 ohm, 3W fusible resistor from Bourn, part
number PWR4522AS10R0JA was placed at the input of this design.
RL  10
Recalculate power budget based on estimated RL losses
2
PBUDGET  PBUDGET
 POUT 
  RL  0.929W
 
 VINMIN  
Current Sense Resistor (RCS):
For this design 2.15 ohm resistor was selected based on a nominal maximum current sense signal of
0.78V.
RCS 
0.78V
 2.2  2.15ohm
I PPK
PRCS  I PRMS   RCS  46mW , nominal current sense resistor power dissipation
2
Recalculate power budget
PBUDGET  PBUDGET  PRCS  0.883W
Select Output Diode (DG):
Calculate diode reverse voltage (VRDG)
VRDG  VOUT  VINMAX 2
8
1
 29.3V
a1
UCC28722/UCC28720 5W USB BJT Flyback Design Example
SLUA700
Calculate peak output diode (IDGPK)
I DGPK  I SPK  4.7 A
For this design we selected a 3A, 40V schottky rectifier with a forward voltage drop (VFDG) of 0.31V.
VFDG  0.31V
Estimated diode power loss (PDG)
PDG 
POUT  VFDG
 310mW
VOUT
Recalculate power budget
PBUDGET  PBUDGET  PDG  573mW
Select Output Capacitors (COUT):
Select output ESR based on 90% of the allowable output ripple voltage
ESRCOUT 
VRIPPLE  0.9 100mV  0.9

 19m
I SPK
4.7 A
For this design the output capacitor (COUT) was selected to prevent VOUT from dropping below the
minimum output voltage during transients (VOTRM).
VOTRM  4.1V
2ms 
COUT 
VOUT
POUT
VOUT  2
 1.1mF
 VOTRM
For this design example two 680uF capacitors were selected in parallel on the output, with an ESR of 7
mΩ each.
COUT  2  680uF  1.36mF
ESRCOUT 
7m
 3.5m
2
UCC28722/UCC28720 5W USB BJT Flyback Design Example
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Estimate total output capacitor RMS current (ICOUT_RMS)
I COUT _ RMS
 I  DMAG
  SPK
3

2
  POUT
  
  VOUT
2

  1.46 A

Estimate total output capacitor loss (PCOUT)
PCOUT  I COUT _ RMS   ESRCOUT  7.5mW
2
Recalculate power budget
PBUDGET  PBUDGET  PCOUT  565mW
Select BJT QA:
For this design we had chosen 800V 1A transistor with the following characteristics:
VCE( sat)  0.6V , Transistor Collector Emitter Saturation
VBE ( sat)  0.6V , Base Emitter Saturation
t r  140ns , Estimated collector rise time
Estimate transistor losses (PQA):
VFLY  VINMIN  2 
I DRS ( AVG ) 
VINRIPPLE
 2  VFDA  99.8V , Average Minimum Input Voltage
2
DMAX ( I DRS ( MIN )  I DRS ( MAX ) )
2
 14mA , Average Base Drive Current
I PPK  DMAX
 90mA , Average Collector Emitter Current
2
V  (VOUT  VDG )a1
PQA  I DRS ( AVG ) VBE ( SAT )  I CE ( AVG ) VCE ( SAT )  I PPK  FLY
 t r  f MAX  373mW
2
I CE ( AVG ) 
Recalculate the power budget
PBUDGET  PBUDGET  PQA  192mW
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UCC28722/UCC28720 5W USB BJT Flyback Design Example
SLUA700
Setup Zener Clamp to Protect FET QA:
VZ  82V , Zener Clamp Voltage (DZ)
VCE _ MAX  800V , FET maximum drain to source voltage
VCLAMP  VCE _ MAX  0.9  VINMAX 2  345.2V , Available Clamp Voltage to Protect FET QA
RS 
VCLAMP  0.6  VZ
 734
I PPK
Select a standard resistor for the design.
RS  750
Estimate Zener Clamp/LLK power dissipation (PLK)
LLPK  I PPK   f MAX
 95mW
2
2
PLLK 
Recalculate power budget
PBUDGET  PBUDGET  PLLK  97mW
Trickle Charge Resistor (RT):
To reduce no load power losses RT and to keep no load power to a minimum, three 1.47MΩ are used in
series for RT
RT  1.47M  3  4.41M
PRT
V

INMAX
RT
2

2
 32mW , Total trickle charge resistor power dissipation
Recalculate power budget
PBUDGET  PBUDGET  PRT  65mW
UCC28722/UCC28720 5W USB BJT Flyback Design Example
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SLUA700
VDD Capacitor Selection (CDD):
VVDD (ON )  21V , Typical VDD turn-on threshold
VVDD (OFF )  7.7V , Typical VDD turnoff threshold
C DD 
I
DRS ( AVG )
 I RUN  COUT  VOUT _ INIT
(VVDD (ON )  VVDD (OFF ) )  I OUT
 3.3uF
Select standard capacitor value for the design
CDD  4.7uF
Note after CDD has been charged up to the device turn on threshold (VVDD(on)), the UCC28722 will
initiate three small gate drive pulses (DRV) and start sensing current and voltage. (Please refer to figure
2) If a fault is detected such as an input under voltage or any other fault, the UCC28722 will terminate
the gate drive pulses and discharge CDD to initiate an under voltage lockout. This capacitor will be
discharged with the run current of the UCC28722 (IRUN) until the VDD turnoff (VVDD(off)) threshold is
reached. Note the CDD discharge time (tCDDD) from this forced soft start can be calculated knowing the
controller run current (IRUN) without out gate driver switching and the controller’s VDD turnoff
threshold (VVDD(off)) and the following equations. If no fault is detected, the UCC28722 will continue
driving QA and controlling the input and output currents and a soft start will not be initiated.
tCDDD  C DD
VVDD ( on)  VVDD ( off )
 VINMAX 2




I
RUN


R
T


 33ms , Discharge for soft start Reset
VVDD(on) =21V
VDD
3 Initial DRV Pulses After VDD(ON)
DRV
0V
Figure 2, VDD and DRV at Startup with Fault
12
VVDD(off) =7.7V
UCC28722/UCC28720 5W USB BJT Flyback Design Example
SLUA700
Select VS voltage divider (RS1, RS2):
IVSL( run)  225uA VS Line-sense run current
Note RS1 so the converter will go into under voltage lockout when the input is below 80% of the
minimum specified input voltage.
a2
VINMIN 2  0.8
a1
RS1 
 93.9k
IVSL( run)
Select a standard resistor for the design
RS1  82.5k
Calculate RS2
RS 2 
4V
VOUT  VDG  a2  4V
 23.7k
RS1
Select a standard resistor for the design
RS 2  27.4k
Calculate VS divider power dissipation (PVS)
PVS


DMAX VOUT  VDG a2
RS1  RS 2 

2
 1.2mW
Select auxiliary diode (DE) for this design that had a forward voltage drop (VDE) of 0.6V.
VDE  0.6V
VDD  VOUT  VDG  a2  VDE  17.3V , UCC28700 supply voltage at VDD
VRDE  VDD  VINMAX 2 
a2
 95V , maximum reverse voltage across VDE
a1
UCC28722/UCC28720 5W USB BJT Flyback Design Example
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SLUA700
Calculate DE power dissipation (PDE)
PDE  ( I RUN  I DRS ( AVG ) ) VDE  9.6mW
Recalculated power budget
PBUDGET  PBUDGET  PVS  PDE  54mW
Preload Resistor Selection (RZ):
To keep the output voltage from climbing at no load a pre-load resistor is required. This is generally a
trial an error process. For this design the preload resistor that kept the output regulated under no load
conditions was 10 kΩ.
RZ  10.0K
Calculate RZ power dissipation (PRZ)
PRZ 
VOUT 2
RZ
 2.5mW
Recalculated power budget and there is 52 mW of margin left in the power budget to meet the efficiency
requirements of the design. Note in production designs, more margin might be required. Also note
these calculations are estimations and the final design may need to be adjusted to hit efficiency
requirements and regulation requirements.
PBUDGET  PBUDGET  PRZ  52mW
Internal Blanking
The UCC28722 controller regulates the output voltage by sensing the auxiliary (Aux) winding. This
removes the need for opto isolator feedback scheme reducing the cost of the design. However, this
voltage control feedback scheme is susceptible to leakage spikes at the switch node that occur in most
flyback converters. This signal is coupled through the turns ratio of the transformer (T1) and shows up
on the Aux winding during tLK_RESET , please refer to figure 3 for details.
To help insure the leakage spike on the Aux winding does not cause a control issue the UCC28720/22
blanks (tB) the Aux signal to the controller for 600 ns to 2.2 us depending on loading. Please see the
data sheet details [1]. Note the ringing on the auxiliary winding needs to be less than 100mV peak
to peak after tB. Snubbing circuitry on the secondary and/or auxiliary winding may be required to
reduce ringing.
14
UCC28722/UCC28720 5W USB BJT Flyback Design Example
SLUA700
Aux Ringing after tB < 100mV
tLK_RESET
VS Samples Aux Voltage for Control
Aux/
DE Cathode
0V
RCS
0V
QA on
DRV
QA off
tB
Figure 3, Auxiliary Winding VS Blanking
To ensure the leakage spike does not cause control issues it needs to be dissipated before the Aux
blanking (tB) has terminated. The tank frequency (fLC) between the switch node capacitance (CSWN) and
the transformer leakage inductance (LLK) should be greater than 1MHz.
f LC 
1
2    LLK  CSWN
f LC 
1
 1MHz
2  500ns
UCC28722/UCC28720 5W USB BJT Flyback Design Example
15
SLUA700
Select line compensation resistor RLC:
Resistor RLC provides offset to the peak current comparator input (CS). RLC is adjusted to terminate the
gate drive signal (B) early to prevent primary current (A) from over shooting [1]. Please refer to figures
4 and 5 for details.
Figure 4, Peak Current Limit Comparator
Figure 5, CS(A), QAg(B), VQADS Signals
K LC  25 , Line Compensating Ratio [1]
Calculate RLC initial resistor setting based on QADS rise and fall time (tr)
RLC 
K LC  RS1  RCS  t r  a1
 6.3k , Starting Point for RLC
LPM
In circuit adjust RLC so the maximum output current is (IOUT). For this design RLC was set to 1 kΩ.
RLC  1k
16
UCC28722/UCC28720 5W USB BJT Flyback Design Example
SLUA700
Estimate no load input power (PNL):
f MIN  650Hz , Minimum operating frequency
IWAIT  95uA , VDD input current at 1 kHz operating frequency [1]
PVDD  IWAIT  VDD 
I
DRS (max)
 I DRS (min)  VDD
2

f MIN
 5.9mW , Estimated UCC28722 power dissipation
f MAX
Estimate switching losses (PSWFM) at high line at fMIN
PSWFM  VINMAX  VOUT
I PPK
 t r  f MIN
 VVDG  a1 3
 1.6mW
2
2
PLLK
I

LLPK   PPK   f MIN
 3 

 92uW , estimate of leakage power dissipation at no load
2
The estimated no load input power (PNL) is roughly 42 mW.
PNL  PVDD  PSWFM  PRZ  PRT  PLLK  42mW
5W EVM Schematic:
Figure 6, UCC28720EVM-212 Schematic
UCC28722/UCC28720 5W USB BJT Flyback Design Example
17
SLUA700
Efficiency
78%
76%
% Efficiency
74%
72%
70%
Efficiency @ 115V RMS
68%
Efficiency @ 230V RMS
66%
64%
10%
20%
30%
40%
50%
60%
70%
80%
90% 100%
Output Power
Figure 7, Efficiency
REFERENCES
[1] UCC28722 Data Sheet, Constant-Voltage, Constant-Current Controller with Primary Side
Regulation, SLUSBL7, December 2013, http://www.ti.com/lit/gpn/ucc28722
[2] Using the UCC28722EVM-212, UCC28700EVM-212 5W USB Adapter, SLUU968, July 2012,
http://www.ti.com/litv/pdf/sluua92
18
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