Texas Instruments | Design Checklist TPS65310A-Q1 | Application notes | Texas Instruments Design Checklist TPS65310A-Q1 Application notes

Texas Instruments Design Checklist TPS65310A-Q1 Application notes
TPS65310A-Design-Checklist
This tool is designed as an aid for customers of Texas Instruments related to their use of the TPS65381. This tool is provided “as is” and Texas Instruments makes no warranties, either express or implied, with regard to the tool or its
output, and assumes no liability for applications assistance of the design of the user’s products. User assumes all risk in the use of this tool.
(applies to TPS65310A-Q1)
Pin Name
Pin #
Type
Signal
VSSENSE
1 Analog
I
VIN
2 Power
PWR
GPFET
VINPROT
3 Digital
4 Power
HSCTRL
HSSENSE
WAKE
EXTSUP
VREG
5
6
7
8
9
Description
external circuit
if not used
Typical resistor to input(Battery) voltage
n/a
Blocking cap to gnd min. 100nF
n/a
O
PWR
Input to monitor the battery line for under-voltage conditions. UV
will be indicated by the IRQ pin.
Unprotected supply input for the base functionality and band gap 1.
Supplied blocks are: RESET, WD, Wake, SPI, Temp Sensing, Voltage
Monitoring and the Logic block.
Gate Driver external protection PMOS FET.
Main input supply pin (Gate Drivers & Bandgap2)
Gate of external protection Ptype-FET
Blocking cap to gnd min. 100nF at pin + 2.2uF + 47uF closed to the HS MOS transistor of BUCK1
open
n/a
Analog
Analog
Digital
Power
Power
O
I
I
PWR
PWR
High Side Gate driver output
Sense Input High Side / LED
Wake Up Input ( Pull down )
Optional LV input for gate driver supply
Internal regulator for gate driver supply (decoupling) and VREF.
Gate of an external PMOS for LED
shutn resistor to measure LED current
VIN
VIN
leave open
n/a
n/a
BOOT1
10 Power
PWR
n/a
GU
PH1
11 Power
12 Power
PWR
PWR
The capacitor on these pins act as the voltage supply for the high side min. 100nF cap to PH1 as closed as possible to device
MOSFET gate drive circuitry.
Gate Driver – high side FET
Gate HS transistor(Ntype) BUCK1, short connection
Switching Node - BUCK1 (floating ground for high side FET driver)
HS/LS Transistor(Ntype) and cap of Buck1 converter
GL
PGND1
S1
S2
VMON1
COMP1
13
14
15
16
17
18
PWR
GND
I
I
I
O
Current sense resistor for BUCK1
Current sense resistor for BUCK1
Monitoring voltage divider BUCK1
compensation network BUCK1
n/a
n/a
n/a
n/a
n/a
n/a
VSENSE1
19 Analog
I
Gate Driver – low side FET
Ground for low side FET driver
Differential current sense inputs for BUCK1, S2 pull-down only active
in RAMP and ACTIVE state
Input pin for the independent voltage monitor at BUCK1
Error Amplifier output for the switching controller. External
compensation network is connected to this node
Input for externally sensed voltage of the output using a resistor
divider network from their respective output line to ground.
Control voltage divider BUCK1
n/a
COMP5
20 Analog
O
VSENSE5
21 Analog
I
PGND5
PH5
VBOOST
VT_REF
22
23
24
25
PRESN
RESN
IRQ
26 Digital
27 Digital
28 Digital
O
O
O
BOOT2
29 Power
PWR
Power
GND
Analog
Analog
Analog
Analog
GND
Power
Power
Analog
GND
PWR
I
O
min. 100nF blocking cap. to GND as closed as possible to pin
min. 2.2uF blocking cap to gnd + 100nF cap to gnd as closed as possible to pin
Gate LS transistor(Ntype) BUCK1, short connection
n/a
n/a
Error Amplifier output for the Boost switching controller. External
compensation network BOOST
compensation network is connected to this node
Input for externally sensed voltage of the Boost output using a
Control voltage divider BOOST
resistor divider network from their respective output line to ground.
GND
Power Ground Boost Converter
Switching Node Boost
Booster Output Voltage
Shutdown comparator reference output. Internally connected to
DVDD, current-limited. When not in use can be connected to DVDD
or left open.
Peripherals Reset ( Open Drain )
System Reset ( Open Drain )
Low Battery Interrupt Output in Operating Mode ( Open Drain )
GND
open
open
DVDD or leave open
The capacitor on these pins act as the voltage supply for the HighSide MOSFET gate drive circuitry.
Coil and diode of BOOST converter
min 50uF cap. to GND
VSENSE1
n/a
n/a
n/a
min. 100nF cap. to PH2 as closed as possible to device
leave open
VSUP2
PH2
PGND2
VMON2
COMP2
VSENSE2
30
31
32
33
34
35
VSENSE3
36 Analog
COMP3
VMON3
PGND3
PH3
VSUP3
BOOT3
37
38
39
40
41
42
WD
43 Digital
CSN
SDI
SCK
SDO
VIO
44
45
46
47
48
Digital
Digital
Digital
Digital
Power
I
I
I
O
PWR
HSPWM
VSUP4
LDO
49 Digital
50 Power
51 Power
I
PWR
PWR
VSENSE4
52 Analog
I
VREF
53 Analog
O
VT
54 Analog
I
DVDD
GND
55 Power
56 GND
PWR
GND
SLVA609
Power
Power
GND
Analog
Digital
Analog
Digital
Analog
GND
Power
Power
Power
PWR
PWR
GND
I
I
I
Input Voltage Supply for Switch mode Regulator BUCK2
Switching Node BUCK2
Power ground of synchronous converter BUCK2.
Input pin for the independent voltage monitor at BUCK2
Compensation selection for the BUCK2 switching converter.
Input for externally sensed voltage of the output using a resistor
divider network from their respective output line to ground.
min. 10uF + 1uF blocking cap. to GND
Coil and cap of Buck2 converter
Monitoring voltage divider BUCK2
low, open or high digital signal to define internal compenmsation of buck2
Control voltage divider BUCK2
leave open
leave open
leave open
VMON1
GND
leave open
I
Input for externally sensed voltage of the output using a resistor
divider network from their respective output line to ground.
Control voltage divider BUCK3
leave open
Compensation selection for the BUCK3 switching converter.
Input pin for the independent voltage monitor at BUCK3
Power ground of synchronous converter BUCK3
Switching Node BUCK3
Input Voltage Supply for Switch mode Regulator BUCK3
The capacitor on these pins act as the voltage supply for the BUCK3
High-Side MOSFET gate drive circuitry.
Watchdog input pin. WD is the trigger input coming from the MCU. (
Pull down )
SPI – Chip select ( Pull up )
SPI – Master Out Slave In ( Pull down )
SPI – Clock ( Pull down )
SPI – Master In Slave Out - Push Pull Output supplied by VIO
Supply Input for the Digital Interface to the MCU. Voltage on this
input will be monitored. If VIO falls below UV threshold a reset will
be generated and the part enters Error Mode.
High side / LED PWM Input ( Pull down )
Input Voltage Supply for Linear Regulator LDO
Linear regulated output (connect a low ESR ceramic output capacitor
to this terminal)
Input for externally sensed voltage of the output using a resistor
divider network from their respective output line to ground.
low, open or high digital signal to define internal compenmsation of buck3
Monitoring voltage divider BUCK3
GND
VMON1
n/a
leave open
leave open
leave open
I
I
GND
PWR
PWR
PWR
I
Coil and cap of Buck3 converter
min. 10uF + 1uF blocking cap. to GND
min. 100nF cap. to PH3 as closed as possible to device
n/a
min. 100nF cap. as closed as possible to GND
leave open
leave open
leave open
n/a
n/a
min. 1uF cap. as closed as possible to GND
10uF cap. as closed as possible to GND
leave open
leave open
leave open
Control voltage divider LDO
VMON1
Accurate reference voltage output for peripherals on the system (e.g. 1uF cap. as closed as possible to GND
ADC)
Input pin for the comparator with shutdown functionality. This input
can be used to sense an external NTC resistor to shut down the IC in
case of TA too high / TA too low. Tie to GND if not in use.
n/a
Internal DVDD output for decoupling
Analog GND, digital GND and substrate connection
n/a
n/a
100nF + 1uF cap. as closed as possible to GND
GND
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