Texas Instruments | AN-1028 Maximum Power Enhancement Techniques for Power Packages (Rev. B) | Application notes | Texas Instruments AN-1028 Maximum Power Enhancement Techniques for Power Packages (Rev. B) Application notes

Texas Instruments AN-1028 Maximum Power Enhancement Techniques for Power Packages (Rev. B) Application notes
Application Report
SNVA036B – June 2001 – Revised May 2013
AN-1028 Maximum Power Enhancement Techniques for
Power Packages
.....................................................................................................................................................
ABSTRACT
The purpose of this application report is to aid the user in maximizing the power handling capability of
Texas Instruments power packages by using the SOT-223 as an example.
Contents
1
Introduction .................................................................................................................. 2
2
Theory ........................................................................................................................ 2
3
Result ......................................................................................................................... 3
4
Conclusion ................................................................................................................... 4
5
References ................................................................................................................... 5
Appendix A
Heat Flow Theory Applied to Power Devices .................................................................. 6
Appendix B
Thermal Measurement ............................................................................................ 8
Appendix C Package Dimension .............................................................................................. 10
Appendix D Thermal Board Views ............................................................................................ 11
List of Figures
.................................
1
SOT-223 Package achieves junction-to-case thermal resistance RθJC of 12°C/W
2
Both Sides of the 4.5″ x 5″ SOT-223 Thermal Board (complete scale drawings is shown in ) ................... 3
3
SOT-223 Junction-to-Ambient Thermal Resistance versus Copper Mounting Pad Area and Its Surface
Placement .................................................................................................................... 3
4
Maximum Power Dissipation Curves for SOT-223. 0.066 in.2 2 oz. Copper Mounting Pad Area, Layout 2,
is Recommended to Achieve Approximately 1.3W ..................................................................... 4
5
Cross-Sectional View of a Power MOSFET Mounted on a Printed Circuit Board
6
7
8
9
10
11
.................................
K Factors, Slopes of a VSD vs Temperature Curves, of a Typical Power MOSFET ................................
Normalized Transient Thermal Resistance Curves.....................................................................
Junction-to-Case Thermal Resistance RθJC of Various Surface Mount Packages ..................................
SOT-223 ....................................................................................................................
SOT-223 Thermal Board Top View in Actual Scale ..................................................................
SOT-223 Thermal Board Bottom View in Actual Scale...............................................................
2
6
8
9
9
10
11
12
List of Tables
1
Thermal Board Configurations
............................................................................................
3
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Introduction
1
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Introduction
In natural cooling, the method of improving power performance should be focused on the optimum design
of copper mounting pads. The design should take into consideration the size of the copper and its
placement on either or both of the board surfaces. A copper mounting pad is important because the
substrate of the integrated circuit is mounted directly onto the pad. The pad acts as a heatsink to reduce
thermal resistance and leads to improved power performance.
Figure 1. SOT-223 Package achieves junction-to-case thermal resistance RθJC of 12°C/W
2
Theory
When a device operates in a system under the steady-state condition, the maximum power dissipation is
determined by the maximum junction temperature rating, the ambient temperature, and junction-toambient thermal resistance.
PDMAX = (TJMAX − TA) / RθJA
(1)
The term junction refers to the point of thermal reference of the semiconductor. Equation 1 can also be
applied to the transient-state:
PDMAX(t) = [TJMAX − TA] / RθJA(t)
(2)
where PDMAX(t) and RθJA(t) are time dependent. By using the transient thermal resistance curves shown in
the data sheet, a transient temperature change can be calculated. The transient thermal behavior is a
complicated subject because RθJA(t) increases non-linearly with time and the conditions of the power
pulse. A more thorough treatment of transient power analysis is beyond the scope of this document; for
more details, see [13].
RθJA has two distinct elements, RθJC junction-to-case and RCA case-to-ambient thermal resistance.
RθJA = RθJC + RθCA
(3)
The case thermal reference of the SOT-223 Power Package is defined as the point of contact between the
lead of the package and the mounting surface.
RθCA is influenced by many variables such as ambient temperature, board layout, and cooling method. Due
to the lack of an industry standard, the value of RθCA is not easily defined and can affect RθJA significantly.
In addition, the case reference can be defined differently by various manufacturers. Under such
conditions, it becomes difficult to define RθCA from the component manufacturer standpoint.
On the other hand, RθJC is independent of the users' conditions and can be accurately measured by the
component manufacturer.
Therefore, in this application report an effort has been made to define a procedure that can be used to
quantify the junction-to-ambient thermal resistance RθJA, which is more useful to the circuit board designer.
2
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Result
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3
Result
The scope of the investigation has been limited to the size of copper mounting pad and its relative surface
placement on the board. In still air with no heatsink, the application of these heat dissipation methods is
the most cost effective thermal solution. A total of sixteen different combinations of 2 oz. copper pad sizes
and their placement were designed to study their influence on RθJA thermal resistance. The configurations
of the board layout are shown in Figure 2 and Table 1. Layouts 1 to 6 have the copper pad sizes from
0.0123 to 1 square inches on the top side of the board (top side is defined as the component side of the
board). Layouts 7 to 11 have copper pad sizes from 0.2 to 1 square inches on the bottom side of the
board. Layouts 12 to 16 have copper pad sizes from 0.132 to 1 square inches divided equally on both
sides of the board.
Figure 2. Both Sides of the 4.5″ x 5″ SOT-223 Thermal Board (complete scale drawings is shown in
Appendix D)
Table 1. Thermal Board Configurations
Layout
2 oz. Copper Mounting Pad Area (in2)
Relative Placement on Board
1–6
0.0123, 0.066, 0.3, 0.53. 0.76, 1
Top
7–11
0.2, 0.4, 0.6, 0.8, 1
Bottom
12–16
0.132, 0.35, 0.568, 0.784, 1
1/2 Top and 1/2 Bottom
RθJA was calculated from the relationship between power and the change of junction temperature. For
more details, test conditions and method, see Appendix B.
Figure 3. SOT-223 Junction-to-Ambient Thermal Resistance versus Copper Mounting Pad Area and Its
Surface Placement
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Conclusion
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Plots in Figure 3 show the relationship of RθJA versus the copper mounting pad area and its surface
placement on the board. It is apparent that increasing copper mounting pad area considerably lowers RθJA
from approximately 110°C/W to 40°C/W in the range from 0.0123 to 1 square inches. In addition, placing
all the copper on the top side of the board further reduces RθJA by 10°C/W to 15°C/W when compared with
the other two placements.
By substituting the thermal resistance, ambient temperature, and the maximum junction temperature rating
into Equation 1, the steady-state maximum power dissipation curves can be obtained and are shown in
Figure 4.
A 18% increase in the power handling can be achieved by increasing the copper pad area on top of the
board from 0.0123 to 0.066 in.2, layout 2. This thermal pad fits directly under the package, so that no
additional board space is required. For maximum performance, it is recommended to put extra copper on
the bottom of the board connected to the top pad by through-hole thermal vias.
Figure 4. Maximum Power Dissipation Curves for SOT-223. 0.066 in.2 2 oz. Copper Mounting Pad Area,
Layout 2, is Recommended to Achieve Approximately 1.3W
4
Conclusion
Texas Instruments has attempted to define the thermal performance of the SOT-223 Power Package, from
a systems point of view. It has been demonstrated that significant thermal improvement can be achieved
in the maximum power dissipation through the proper design of copper mounting pads on the circuit
board. The results can be summarized as follows:
• Enlarged copper mounting pads, on either one or both sides of the board, are effective in reducing the
case-to-ambient thermal resistance RθCA.
• Placement of the copper pads on the top side of the board gives the best thermal performance.
• The most cost effective approach of designing layout 2: 0.066 square inches copper pad directly under
the package, without occupying additional board space, can increase the maximum power from
approximately 1.1W to 1.3W.
4
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References
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5
References
1. K. Azar, S.S. Pan, J. Parry, H. Rosten, “Effect of Circuit Board Parameters on Thermal Performance of
Electronic Components in Natural Convection Cooling,” IEEE 10th Annual Semi-Therm Conference,
Feb. 1994.
2. A. Bar-Cohen, & A.D. Krauss, “Advances in Thermal Modeling of Electronic Components & Systems,”
Vol 1, Hemisphere Publishing, Washington, D.C., 1988.
3. R.T. Bilson, M.R. Hepher, J.P. McCarthy, “The Impact of Surface Mounted Chip Carrier Packaging on
Thermal Management in Hybrid Microcircuit,” Thermal Management Concepts in Microelectronics
Packaging, International Society for Hybrid Microelectronics, 1984.
4. R.A. Brewster, R.A. Sherif, “Thermal Analysis of A Substrate with Power Dissipation in the Vias,” IEEE
8th Annual Semi-Therm Conf., Austin, TX, Feb. 1992.
5. D. Edwards, “Thermal Enhancement of IC Packages,” IEEE 10th Annual Semi-Therm Conf., San Jose,
CA, Feb. 1994.
6. S.S. Furkay, “Convective Heat Transfer in Electronic Equipment: An Overview,” Thermal Management
Concepts, 1984.
7. C. Harper, Electronic Packaging & Interconnection Handbook, McGraw-Hill, NY, 1991, Ch. 2.
8. Y.M. Kasem, R.K. Williams, “Thermal Design Principles and Characterization of Miniaturized SurfaceMount Packages for Power Electronics,” IEEE 10th Annual Semi-Therm Conf., San Jose, CA, Feb.
1994.
9. V. Manno, N.R. Kurita, K. Azar, “Experimental Characterization of Board Conduction Effect,” IEEE 9th
Annual Semi-Therm Conf., 1993.
10. J.W. Sofia, “Analysis of Thermal Transient Data with Synthesized Dynamic Models for Semiconductor
Devices,” IEEE 10th Annual Semi-Therm Conf., San Jose, CA, Feb. 1994.
11. G.R. Wagner, “Circuit Board Material/Construction and its Effect on Thermal Management,” Thermal
Management Concepts, 1984.
12. M. Wills, “Thermal Analysis of Air-Cooled Cbs,” Electron Prod., pp. 11-18, May 1983.
13. Motorola Application Note AN-569.
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Appendix A Heat Flow Theory Applied to Power Devices
When a power device operates with an appreciable current, its junction temperature is elevated. It is
important to quantify its thermal limits in order to achieve acceptable performance and reliability. This limit
is determined by summing the individual parts consisting of a series of temperature rises from the
semiconductor junction to the operating environment. A one dimensional steady-state model of conduction
heat transfer is demonstrated in Figure 5. The heat generated at the device junction flows through the die
to the die attach pad, through the lead frame to the surrounding case material, to the printed circuit board,
and eventually to the ambient environment. There are also secondary heat paths. One is from the
package to the ambient air. Using a MOSFET device as an example, the other is from the drain lead
frame to the detached source and gate leads then to the printed circuit board. These secondary heat
paths are assumed to be negligible contributors to the heat flow in this analysis.
Figure 5. Cross-Sectional View of a Power MOSFET Mounted on a Printed Circuit Board
NOTE: Note that the case temperature is measured at the point where the drain lead(s) contact with
the mounting pad surface.
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Appendix A
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The increase of junction temperature above the surrounding environment is directly proportional to
dissipated power and the thermal resistance.
The steady-state junction-to-ambient thermal resistance, RθJA, is defined as:
RθJA = (TJ − TA)/P
(4)
where TJ is the average temperature of the device junction. The term junction refers to the point of thermal
reference of the semiconductor device. TA is the average temperature of the ambient environment. P is the
power applied to the device which changes the junction temperature.
RθJA is a function of the junction-to-case RθJC and case-to-ambient RθCA thermal resistance.
RθJA = RθJC + RθCA
(5)
where the case of a power MOSFET is defined at the point of contact between the drain lead(s) and the
mounting pad surface. RθJC can be controlled and measured by the component manufacturer independent
of the application and mounting method and is therefore the best means of comparing various suppliers
component specifications for thermal performance. On the other hand, it is difficult to quantify RθCA due to
heavy dependence on the application. Before using the data sheet thermal data, the user should always
be aware of the test conditions and justify the compatibility in the application.
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Appendix B Thermal Measurement
B.1
Prior to any thermal measurement, a K factor must be determined. It is a linear factor related to the
change of intrinsic diode voltage with respect to the change of junction temperature. From the slope of the
curve shown in Figure 6, K factor can be determined. It is approximately 2.2 mV/°C for most Power
MOSFET devices.
Figure 6. K Factors, Slopes of a VSD vs Temperature Curves, of a Typical Power MOSFET
After the K factor calibration, the drain-source diode voltage of the device is measured prior to any
heating. A pulse is then applied to the device and the drain-source diode voltage is measured 30 µs
following the end of the power pulse. From the change of the drain-source diode voltage, the K factor,
input power, and the reference temperature, the time dependent single pulsed junction-to-reference
thermal resistance can be calculated. From the single pulse curve on Figure 7, duty cycle curves can be
determined.
NOTE: A curve set in which RθJA is specified indicates that the part was characterized using the
ambient as the thermal reference. The board layout specified in the device-specific data
sheet will help determine the applicability of the curve set.
B.2
Junction-to-Ambient Thermal Resistance Measurement
Equipment and Setup:
• Tesec DV240 Thermal Tester
• 1 cubic foot still air environment
• Thermal Test Board with 16 layouts defined by the size of the copper mounting pad and their relative
surface placement. For layouts with copper on the top and bottom planes, there are 0.02 inch copper
plated vias (heat pipes) connecting the two planes. For board layout and description, see Figure 2 and
Table 1 on the thermal application report. The conductivity of the FR-4 PCB used is 0.29 W/m-C. The
length is 5.00 inches ± 0.005; width 4.50 inches ± 0.005; and thickness 0.062 inches ± 0.005. 2 oz.
copper clad PCB.
The junction-to-ambient thermal measurement was conducted in accordance with the requirements of
MIL-STD-883 and MIL-STD-750 with the exception of using 2 oz. copper and measuring diode current at
10 mA.
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Junction-to-Case Thermal Resistance Measurement
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A test device is soldered on the thermal test board with minimum soldering. The copper mounting pad
reaches the remote connection points through fine traces. Jumpers are used to bridge to the edge card
connector. The fine traces and jumpers do not contribute significant thermal dissipation but serve the
purpose of electrical connections. Using the intrinsic diode voltage measurement described above, the
junction-to-ambient thermal resistance can be calculated.
Figure 7. Normalized Transient Thermal Resistance Curves
B.3
Junction-to-Case Thermal Resistance Measurement
Equipment and Setup:
• Tesec DV240 Thermal Tester
• large aluminum heat sink
• type-K thermocouple with FLUKE 52 K/J Thermometer
The drain lead(s) is soldered on a 0.5 x 1.5 x 0.05 copper plate. The plate is mechanically clamped to a
heat sink which is large enough to be considered ideal. Thermal grease is applied in-between the two
planes to provide good thermal contact. Theoretically the case temperature should be held constant
regardless of the conditions. Thus a thermocouple is used and fixed at the point of contact between the
drain lead(s) and the copper plate surface, to account for any heatsink temperature change. Using the
intrinsic diode voltage measurement described earlier, the junction-to-case thermal resistance can be
obtained. A plot of junction-to-case thermal resistance for various packages is shown in Figure 8. Note
RθJC can vary with die size and the effect is more prominent as RθJC decreases.
Figure 8. Junction-to-Case Thermal Resistance RθJC of Various Surface Mount Packages
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Appendix C Package Dimension
Figure 9. SOT-223
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Appendix D Thermal Board Views
Figure 10. SOT-223 Thermal Board Top View in Actual Scale
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Appendix D
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Figure 11. SOT-223 Thermal Board Bottom View in Actual Scale
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