Texas Instruments | DRA80xM Infotainment Applications Processor Silicon Revision 1.0 (Rev. E) | Datasheet | Texas Instruments DRA80xM Infotainment Applications Processor Silicon Revision 1.0 (Rev. E) Datasheet

Texas Instruments DRA80xM Infotainment Applications Processor Silicon Revision 1.0 (Rev. E) Datasheet
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DRA80M
SPRSP31E – APRIL 2018 – REVISED JUNE 2019
DRA80xM Infotainment Applications Processor
Silicon Revision 1.0
1 Device Overview
1.1
Features
Processor cores:
• Dual- or quad-core Arm® Cortex®-A53
microprocessor subsystem at up to 1.1 GHz
– Up to two dual-core or two single-core Arm®
Cortex®-A53 clusters with 512KB L2 cache
including SECDED
– Each A53 core has 32KB L1 ICache and 32K L1
DCache
• Dual-core Arm® Cortex®-R5F at up to 400 MHz
– Supports lockstep mode
– 16KB ICache, 16KB DCache, and 64KB RAM
per R5F core
Ethernet subsystem:
• Three industrial subsystem with Ethernet support:
– Up to two 10/100/1000 Ethernet ports per
subsystem
– Supports two 10/100/1000 SGMII ports (1)
– Compatibility with 10/100Mb
Memory subsystem:
• Up to 2MB of on-chip L3 RAM with SECDED
• Multi-core Shared Memory Controller (MSMC)
– Up to 2MB (2 banks × 1MB) SRAM with
SECDED
– Shared coherent Level 2 or Level 3 memorymapped SRAM
– Shared coherent Level 3 Cache
– 256-bit processor port bus and 40-bit physical
address bus
– Coherent unified bi-directional interfaces to
connect to processors or device masters
– L2, L3 Cache pre-warming and post flushing
– Bandwidth management with starvation bound
– One infrastructure master interface
– Single external memory master interface
– Supports distributed virtual system
– Supports internal DMA engine – Data Routing
Unit (DRU)
– ECC error protection
• DDR Subsystem (DDRSS)
– Supports DDR3L/DDR4 memory types up to
DDR-1600
– Supports LPDDR4 memory type up to DDR1333
– 32-bit data bus and 7-bit SECDED bus
– 32GB of total addressable space
• General-Purpose Memory Controller (GPMC)
SafeTI™ semiconductor component:
• Designed for functional safety applications
• Developed according to the requirements of ISO
26262
• Achieves systematic integrity of ASIL-D
• For the MCU safety island, sufficient diagnostics
are included to achieve random fault integrity
requirements of ASIL-B
• For the rest of the SoC, sufficient diagnostics are
included to achieve random fault integrity
requirements of ASIL-B
• In addition, sufficient architectural support is in
place to achieve execution of ASIL-D applications
given a proper safety concept (for example
reciprocal comparison by software)
• Functional safety manual available
• Safety-related certification
– Component level functional safety certification
by TÜV SÜD [certification in progress]
• Functional safety features:
– ECC or parity on calculation-critical memories
and internal bus interconnect
– Firewalls to help provide Freedom From
Interference (FFI)
– Built-In Self-Test (BIST) for CPU, high-end
timers, and on-chip RAM
– Hardware error injection support for test-fordiagnostics
– Error Signaling Modules (ESM) for capture of
functional safety related errors
– Voltage, temperature, and clock monitoring
– Windowed and non-windowed watchdog timers
in multiple clock domains
• MCU island
– Isolation of the dual-core Arm® Cortex®-R5F
microprocessor subsystem
– Separate voltage, clocks, resets, and dedicated
peripherals
– Internal MCSPI connection to the rest of SoC
Security:
• Secure boot supported
– Hardware-enforced root-of-trust
– Support to switch root-of-trust via backup key
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. ADVANCE INFORMATION for pre-production products; subject to
change without notice.
ADVANCE INFORMATION
1
DRA80M
SPRSP31E – APRIL 2018 – REVISED JUNE 2019
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ADVANCE INFORMATION
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www.ti.com
– Support for takeover protection, IP protection,
and anti-roll back protection
Cryptographic acceleration supported
– Session-aware cryptographic engine with ability
to auto-switch key-material based on incoming
data stream
– Supports cryptographic cores
– AES – 128/192/256 bits key sizes
– 3DES – 56/112/168 bits key sizes
– MD5, SHA1
– SHA2 – 224/256/384/512
– DRBG with true random number generator
– PKA (public key accelerator) to assist in
RSA/ECC processing
– DMA support
Debugging security
– Secure software controlled debug access
– Security aware debugging
Trusted Execution Environment (TEE) supported
– Arm® TrustZone® based TEE
– Extensive firewall support for isolation
– Secure DMA path and interconnect
– Secure watchdog/timer/IPC
Secure storage support
On-the-fly encryption and authentication support
for OSPI™ interface
Networking security support for data (payload)
encryption/authentication via packet based
hardware cryptographic engine
Security co-processor (DMSC) for key and security
management, with dedicated device level
interconnect for security
SoC services:
Device Management Security Controller (DMSC)
– Centralized SoC system controller
– Manages system services including initial boot,
security, functional safety and clock/reset/power
management
– Power management controller for active and low
power modes
– Communication with various processing units
over message manager
– Simplified interface for optimizing unused
peripherals
– Tracing and debugging capability
Sixteen 32-bit general-purpose timers
Two data movement and control Navigator
Subsystems (NAVSS)
– Ring Accelerator (RA)
– Unified DMA (UDMA)
– Up to 2 Timer Managers (TM) (1024 timers
each)
Multimedia:
One Camera Serial Interface-2 ( MIPI® CSI-2)
High-speed interfaces:
• One Gigabit Ethernet (CPSW) interface supporting
– RMII (10/100) or RGMII (10/100/1000)
– IEEE1588 (2008 Annex D, Annex E, Annex F)
with 802.1AS PTP
– Audio/video bridging (P802.1Qav/D6.0)
– Energy-efficient Ethernet (802.3az)
– Jumbo frames (2024 bytes)
– Clause 45 MDIO PHY management
• Two PCI-Express® ( PCIe®) revision 3.1
subsystems (1)
– Supports Gen3 (8.0GT/s) operation
– Two independent 1-lane, or a single 2-lane port
– Support for concurrent root-complex and/or endpoint operation
• USB 3.1 Dual-Role Device (DRD) subsystem (1)
– One enhanced SuperSpeed Gen1 Port
– One USB 2.0 port
– Each port independently configurable as USB
host, USB peripheral, or USB dual-role device
General connectivity:
• 6× Inter-Integrated Circuit ( I2C™) ports
• 5× configurable UART/IrDA/CIR modules
• Two simultaneous flash interfaces configured as
– Two OSPI flash interfaces
– or HyperBus™ and OSPI1 flash interface
• 2× 12-bit Analog-to-Digital Converters (ADC)
– Up to 4 Msamples/s
– Eight multiplexed analog inputs
• 8× Multichannel Serial Peripheral Interfaces
(MCSPI) controllers
– Two with internal connections
– Six with external interfaces
• General-Purpose I/O (GPIO) pins
Control interfaces:
• 6× Enhanced High Resolution Pulse-Width
Modulator (EHRPWM) modules
• One Enhanced Capture (ECAP) module
• 3× Enhanced Quadrature Encoder Pulse (EQEP)
modules
Automotive interfaces:
• 2× Modular Controller Area Network (MCAN)
modules with full CAN-FD support
Audio interfaces:
• 3× Multichannel Audio Serial Port (MCASP)
modules
Media and data storage:
• 2× MultiMedia Card/ Secure Digital® ( MMC™/
SD®) interfaces
Simplified power management:
• Simplified power sequence with full support for
dual voltage I/O
• Integrated LDOs reduces power solution
Device Overview
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SPRSP31E – APRIL 2018 – REVISED JUNE 2019
complexity
• Integrated SDIO LDO for handling automatic
voltage transition for SD interface
• Integrated Power On Reset (POR) generation
reducing power solution complexity
• Integrated voltage supervisor for functional safety
monitoring
• Integrated power supply glitch detector for
detecting fast power supply transients
Analog/system integration:
• Integrated USB VBUS detection
• Fail safe I/O for DDR RESET
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Applications
Automotive gateway
Automotive telematics
Automotive V2X
1.3
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Vehicle computing
Other general use
Description
Automobiles are becoming more and more connected - both inside the car, within the various
subsystems/domains as well as with the outside world, with connectivity via Bluetooth, LTE, WiFi etc.
Much more information and data are being shared or transferred between the various domains; for
example, video from rear and surround view cameras for displayed in the head unit; data from the chassis
is sent to the on-board diagnostic unit, etc. As the amount of data that has to be integrated and
transported between the various domains in a time sensitive manner has increased, car manufacturers are
looking to include a network gateway, based on Ethernet protocols, in cars. Such gateways should be able
to handle multiple connectivity protocols such as CAN, CAN-FD, TCP/IP to name a few. TI’s DRA80x
family of products enable automotive manufacturers to build scalable and cost optimized network gateway
features in cars, thanks to its high level of integration and purpose built peripherals, such as Gigabit
Ethernet MACs.
DRA80x Automotive Gateway processors are built to meet the intense processing needs of automotive
gateway. The DRA80x family of devices combines four or two Arm® Cortex®-A53 cores with an ASIL-C
capable dual Arm® Cortex®-R5 MCU subsystem and six Gigabit Ethernet MACs in the MAIN domain and
one Gigabit Ethernet MAC in the MCU domain to create an SoC capable of implementing an Automotive
Gateway system with plenty of automotive connectivity and functional safety processing.
The four Courtex-A53 cores in the DRA804M are arranged in two dual-core clusters with shared L2
memory to create two processing channels to address additional safety concepts. The two Arm® Cortex®A53 cores in the DRA802M are available in a single dual-core cluster and two single-core cluster options.
Extensive ECC is included for on-chip memory and interconnects for reliability. Cryptographic acceleration
and secure boot are available on some DRA80x devices, in addition to granular whitelist firewalls
managed by a security controller core.
Programmability is provided by the Arm® Cortex®-A53 RISC CPUs with Arm® Neon™ extension, and the
dual Arm® Cortex®-R5 MCU subsystem is available for general purpose use. The Ethernet subsystem can
be used to provide up to six ports of Ethernets, including TSN and Ethernet/IP, for standard Ethernet
connectivity. Additionally, TI provides a complete set of development tools for the Arm® cores including C
compilers and a debugging interface for visibility into source code execution. Safety documentation is
available for applications needing to meet functional safety standards.
Device Overview
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ADVANCE INFORMATION
1.2
• All I/O pins drivers disabled during reset to avoid
bus conflicts
• Default I/O pulls disabled during reset to avoid
system conflicts
• Support dynamic I/O pinmux configuration change
System-on-Chip (SoC) architecture:
• Supports primary boot from UART, I2C, OSPI,
HyperBus, parallel NOR Flash, SD or eMMC™,
USB, PCIe, and Ethernet interfaces
• 28-nm CMOS technology
• 23 mm × 23 mm, 0.8-mm pitch, 784-pin FCBGA
(ACD)
DRA80M
SPRSP31E – APRIL 2018 – REVISED JUNE 2019
www.ti.com
Device Information (1)
(1)
PART NUMBER
PACKAGE
BODY SIZE
DRA804MACD
FCBGA (784)
23.0 mm × 23.0 mm
DRA802MACD
FCBGA (784)
23.0 mm × 23.0 mm
For more information, see Section 9, Mechanical, Packaging, and Orderable Information
ADVANCE INFORMATION
4
Device Overview
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1.4
SPRSP31E – APRIL 2018 – REVISED JUNE 2019
Functional Block Diagram
Figure 1-1 is functional block diagram for the device.
DRA80x
Navigator Subsystem
Industrial Subsystem
2x
2xArm
Arm®®
Cortex
Cortex®®-A53
-A53
2x Arm ®
Cortex ®-A53
DMSC
Proxy
2x PVU
CPTS
RA
MCRC
INTR
12x Mailbox
Spinlock
3x INTA
(3)
3x PRU_ICSSG
(up to 6x Ethernet Ports)
512KB
512KBL2
L2
with
withECC
ECC
UDMA
512KB L2
with ECC
2x TIMER-MGR
Channelized FW
System Services
Memory Subsystem
Camera Adaptation
Layer
12x GP Timers
MSMC
2MB SRAM with ECC
MIPI CSI-2
PDMA
GPMC
ELM
AES
DRBG
SHA
MD5
MCU Island
Navigator Subsystem
PKA
3DES
Debug
EMIF with ECC
Security Accelerators
ADVANCE INFORMATION
4x RTI/WWDT
RA
UDMA
Proxy
MCRC
INTR
INTA
Channelized FW
2x Arm ®
Cortex ®-R5F
PDMA
4x GP Timers
(with optional Lockstep)
ESM
2x RTI/WWDT
Scratchpad RAM 512B
MCU-MSRAM 512KB
ESM
Interconnect
Automotive Interfaces
Control Interfaces
2x MCAN-FD (1)
6x EHRPWM
1x ECAP
3x EQEP
Media and Data Storage
Audio Peripherals
2x MMC/SD
3x MCASP
General Connectivity
GPIO
2x OSPI
or 1xQSPI +
1x Hyperbus (1)
5x MCSPI (2)
3x MCSPI (1)(2)
2x ADC (1)
5x I2C
4x UART
1x I2C (1)
1x UART (1)
High-Speed Serial Interfaces
PCIe ®
2x Single/1x Dual lane
Gen 3(3)
1x USB 2.0 DRD
1x USB 3.1 DRD (3)
10/100/1000 Ethernet (1)
intro_001
(1)
(2)
(3)
This interface is located on the MCU Island but is available for the full system to access.
One port is internally connected only; not connected to any pins.
SGMII, USB3.1 and PCIe share a total of two SerDes lanes.
Figure 1-1. DRA80x Block Diagram
Device Overview
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SPRSP31E – APRIL 2018 – REVISED JUNE 2019
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Table of Contents
1
Device Overview ......................................... 1
1.1
Features .............................................. 1
1.2
Applications ........................................... 3
1.3
Description ............................................ 3
........................... 5
Revision History ......................................... 7
Device Comparison ..................................... 8
3.1
Related Products ..................................... 9
Terminal Configuration and Functions ............ 10
4.1
Pin Diagram ......................................... 10
4.2
Pin Attributes ........................................ 10
4.3
Signal Descriptions .................................. 59
4.4
Pin Multiplexing .................................... 107
4.5
Connections for Unused Pins ...................... 118
Specifications ......................................... 120
5.1
Absolute Maximum Ratings........................ 120
5.2
ESD Ratings ....................................... 122
5.3
Power-On-Hour (POH) Limits(1)(2)(3) ............... 123
5.4
Recommended Operating Conditions ............. 123
5.5
Operating Performance Points ..................... 126
5.6
Electrical Characteristics ........................... 127
1.4
2
3
4
5
ADVANCE INFORMATION
6
Functional Block Diagram
7
8
............................
...................
6.4
Other Subsystems .................................
6.5
Identification........................................
6.6
Boot Modes ........................................
Applications, Implementation, and Layout ......
7.1
DDR Board Design and Layout Guidelines ........
7.2
OSPI Board Design and Layout Guidelines .......
7.3
High Speed Differential Signal Routing Guidance .
7.4
USB Design Guidelines ............................
6.2
Processor Subsystems
238
6.3
Accelerators and Coprocessors
243
281
281
286
286
286
288
288
7.5
System Power Supply Monitor Design Guidelines
7.6
7.7
MMC Design Guidelines ........................... 290
Power Distribution Network Implementation
Guidance ........................................... 290
289
7.8
External Capacitors ................................ 290
7.9
Thermal Solution Guidance ........................ 297
Device and Documentation Support .............. 298
8.1
Device Nomenclature .............................. 298
8.2
Tools and Software ................................ 300
8.3
Documentation Support ............................ 301
8.4
Related Links
......................................
301
5.7
VPP Specifications for One-Time Programmable
(OTP) eFuses ...................................... 135
8.5
Community Resources............................. 301
8.6
Trademarks ........................................ 301
5.8
Thermal Resistance Characteristics ............... 136
8.7
Electrostatic Discharge Caution
5.9
Timing and Switching Characteristics.............. 137
8.8
Glossary............................................ 302
Detailed Description.................................. 237
6.1
Overview ........................................... 237
9
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302
Mechanical, Packaging, and Orderable
Information ............................................. 303
9.1
6
246
Packaging Information ............................. 303
Table of Contents
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SPRSP31E – APRIL 2018 – REVISED JUNE 2019
2 Revision History
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Added clarification for PRU_ICSSG MII support in Table 3-1, Device Comparison ......................................... 8
Added Note for ICSSG Features Related to RGMII/SGMII/MII in Table 3-1, Device Comparison ........................ 8
Updated type, I/O Voltage Value, Power, Buffer Type and IO Daisy Chain of MON pins in Table 4-1, Pin Attributes 10
Updated MMC SDCD and SDWP Power Connection .......................................................................... 10
Updated footnotes under MMC Signal Description Tables ................................................................... 82
Added Notes for ICSSG Features Related to RGMII/SGMII/MII in Section 4.3.21, PRU_ICSSG ........................ 85
Updated note (6) regarding VDDA_VSYS_MON .............................................................................. 106
Added Table 4-77, Reserved Balls to Reserved Balls Specific Connection Requirements and Updated Table 476, Unused Balls Specific Connection Requirements ........................................................................ 118
Added electrical characteristics for monitor pins in Section 5.1, Absolute Maximum Ratings and Section 5.4,
Recommended Operating Conditions ........................................................................................... 120
Updated Transient Overshoot and Undershoot specification at IO pin parameter ........................................ 122
Updated JEDEC specification for CDM method in Section 5.2, ESD Ratings ............................................ 122
Removed Power Consumption Summary section ............................................................................. 126
Updated Impact to Your Hardware Warranty section ......................................................................... 135
Updated the default state of WKUP_LFOSC0 and HFOSC1 in Section 5.9.2, Power Supply Sequencing and
Section 5.9.4.1, Input Clocks / Oscillators ...................................................................................... 138
Removed table PLL Power Supply Requirements and the information is moved in Section 5.4, Recommended
Operating Conditions .............................................................................................................. 155
Updated MDIO Timing Diagram and MDIO7 parameter values ............................................................ 157
Updated delay time in Table 5-42, Timing Requirements for eHRPWM ................................................... 165
Added Table 5-76, MMC DLL Delay Mapping for all Timing Modes ....................................................... 211
Updated timing specification values in Section 5.9.5.19, OLDI .............................................................. 219
Updated all sections in Section 6, Detailed Description and aligned with the device TRM .............................. 237
Added Note for ICSSG Features Related to RGMII/SGMII/MII in Section 6.3.1, PRU_ICSSG ......................... 243
Added Section 6.5, Identification and Section 6.6, Boot Modes ............................................................ 281
Added VDDA_VSYS_MON voltage divider details in Section 7.5, System Power Supply Design Guidelines ....... 289
Updated Figures in Section 7.8.1, LVCMOS External Capacitor Connections ............................................ 292
Revision History
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ADVANCE INFORMATION
Changes from March 23, 2019 to June 21, 2019 (from D Revision (March 2019) to E Revision)
DRA80M
SPRSP31E – APRIL 2018 – REVISED JUNE 2019
www.ti.com
3 Device Comparison
Table 3-1 shows a comparison between devices, highlighting the differences.
Table 3-1. Device Comparison
FEATURES
REFERENCE NAME
DRA804M
DRA802M
DRA804M: 0x161FC
DRA802M: 0x161BC
Features
CTRLMMR_WKUP_JTAG_DEVICE_ID[31:11] DEVICE_ID
register bitfield value (5)
PROCESSORS AND ACCELERATORS
Speed Grades
See Table 5-1
Arm Cortex-A53 Microprocessor Subsystem
Arm A53
Dual-Core Arm Cortex-R5F
Arm R5F
Quad Core
Dual Core
Device Management Security Controller
DMSC
Yes
Safety Features
Safety
Optional(4)
Yes (optional lockstep(4))
PROGRAM AND DATA STORAGE
ADVANCE INFORMATION
On-Chip Shared Memory (RAM)
MCU_MSRAM
Multicore Shared Memory Controller
MSMC
2MB (On-Chip Shared SRAM with ECC)
512KB
DDR3L/DDR4/LPDDR4 DDR Subsystem
DDRSS
Up to 32GB (32-Bit data)
SECDED
7-Bit
General-Purpose Memory Controller
GPMC
Up to 1GB with ECC
Error Location Module
ELM
Yes
Display Subsystem
DSS
No(1)
Modular Controller Area Network Interface
MCAN
2
Peripheral Direct Memory Access
PDMA
Yes
Navigator Subsystem
NAVSS
General-Purpose I/O
GPIO
Inter-Integrated Circuit Interface
I2C
Analog-to-Digital Converter
ADC
2
Camera Adaptation Layer (CAL) with Camera Serial Interface
(CSI2) and Video Input Port (VIN)
CSI2
Yes
VIN0
No(1)
Multichannel Serial Peripheral Interface
MCSPI
PERIPHERALS
Multichannel Audio Serial Port
MultiMedia Card/ Secure Digital Interface
2
Up to 242
6
8
MCASP0
16 Serializers
MCASP1
10 Serializers
MCASP2
4 Serializers
MMCSD0
8-bits
MMCSD1
4-bits
8-bits (3)
OSPI0
Flash Subsystem (FSS)
OSPI1
4-bits
HyperBus
Yes
Security Accelerator
SA
Error Signalling Module
ESM
2x PCI Express 3.1 Port with Integrated PHY
PCIE0
Yes
Yes
Up to Two Lanes (2)
Single Lane (2)
PCIE1
3x Programmable Real-Time Unit Subsystem and Industrial
Communication Subsystem (Ethernet Subsystem)
(3)
PRU_ICSSG0
(6)
PRU_ICSSG1
(6)
PRU_ICSSG2
(6)
Yes (2× RGMII, 2× MII)
Yes (2× RGMII, 2× MII)
Yes (2× RGMII, 2× MII, 2× SGMII
Gigabit Ethernet Interface
CPSW
RMII or RGMII
General-Purpose Timers
TIMER
16
8
Device Comparison
(2)
)
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Table 3-1. Device Comparison (continued)
FEATURES
REFERENCE NAME
DRA804M
DRA802M
Features
Enhanced High Resolution Pulse-Width Modulator Module
EHRPWM
Yes
Enhanced Capture Module
ECAP
Yes
Enhanced Quadrature Encoder Pulse Module
EQEP
Yes
Universal Asynchronous Receiver and Transmitter
UART
5
Universal Serial Bus (USB3.1) SuperSpeed Dual-Role-Device
(DRD) Ports with SS PHY
USB0
Yes(2)
Universal Serial Bus (USB2.0) HighSpeed Dual-Role-Device
(DRD) Ports with HS/FS PHY
USB1
Yes
(1) VIN0 and VOUT0 are not available on this device, but signal names are retained for consistency with the pin compatible family of
devices.
(2) SGMII0, SGMII1, USB3.1, PCIE0, and PCIE1 share total of two SerDes lanes.
(3) Two simultaneous flash interfaces configured as OSPI0 and OSPI1, or HyperBus and OSPI1.
(5) For more details about the CTRLMMR_WKUP_JTAG_DEVICE_ID register and DEVICE_ID bitfield, see the device TRM.
(6) ICSS features not related to RGMII, MII, and SGMII are not supported on this SoC. Signal names for other functions are retained for
consistency with the pin compatible family of devices
3.1
Related Products
Companion Products for DRA80x Review products that are frequently purchased or used in conjunction
with this product.
Reference Designs for DRA80x TI Designs Reference Design Library as a robust reference design
library spanning analog, embedded processor and connectivity. Created by TI experts to
help you jump-start your system design, all TI Designs include schematic or block diagrams,
BOMs and design files to speed your time to market.
Device Comparison
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ADVANCE INFORMATION
(4) Device supports features to aid in functional safety system designs such as lockstep Arm R5F if the part number is designated with the
F option.
DRA80M
SPRSP31E – APRIL 2018 – REVISED JUNE 2019
www.ti.com
4 Terminal Configuration and Functions
4.1
Pin Diagram
NOTE
The terms "ball", "pin", and "terminal" are used interchangeably throughout the document. An
attempt is made to use "ball" only when referring to the physical package.
Figure 4-1 shows the ball locations for the 784 plastic ball grid array (FCBGA) package that are used in
conjunction with Table 4-1 through to locate signal names and ball grid numbers.
ADVANCE INFORMATION
AH
AG
AF
AE
AD
AC
AB
AA
Y
W
V
U
T
R
P
N
M
L
K
J
H
G
F
E
D
C
B
A
3
1
2
7
5
4
6
9
8
11 13 15 17 19 21 23 25 27
10 12 14 16 18 20 22 24 26 28
Figure 4-1. ACD FCBGA-N784 Package (Bottom View)
4.2
Pin Attributes
Table 4-1 describes the terminal characteristics and the signals multiplexed on each ball.
10
Terminal Configuration and Functions
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Table 4-1. Pin Attributes
BALL NAME [2]
SIGNAL NAME [3]
MUXMODE
[4]
TYPE [5]
BALL
BALL
RESET
I/O
RESET
REL.
VOLTAGE
STATE [6] MUXMODE VALUE [8]
[7]
POWER [9]
HYS [10]
BUFFER
TYPE [11]
PULL
UP/DOWN
TYPE [12]
DSIS [13]
RXACTIVE/
IO Daisy
TXDISABL
Chain [15]
E [14]
P17
CAP_VDDAR_CORE0
CAP_VDDAR_CORE0
CAP
V17
CAP_VDDAR_CORE1
CAP_VDDAR_CORE1
CAP
W16
CAP_VDDAR_CORE2
CAP_VDDAR_CORE2
CAP
M14
CAP_VDDAR_CORE3
CAP_VDDAR_CORE3
CAP
L15
CAP_VDDAR_CORE4
CAP_VDDAR_CORE4
CAP
U10
CAP_VDDAR_MCU
CAP_VDDAR_MCU
CAP
M12
CAP_VDDAR_MPU0_0
CAP_VDDAR_MPU0_0
CAP
N12
CAP_VDDAR_MPU0_1
CAP_VDDAR_MPU0_1
CAP
N18
CAP_VDDAR_MPU1_0
CAP_VDDAR_MPU1_0
CAP
N15
CAP_VDDAR_MPU1_1
CAP_VDDAR_MPU1_1
CAP
Y10
CAP_VDDAR_WKUP
CAP_VDDAR_WKUP
CAP
AA8
CAP_VDDA_1P8_IOLDO_WKU CAP_VDDA_1P8_IOLDO_WKUP
P
CAP
J17
CAP_VDDA_1P8_SDIO
CAP_VDDA_1P8_SDIO
CAP
G19
CAP_VDDA_1P8_IOLDO0
CAP_VDDA_1P8_IOLDO0
CAP
Y19
CAP_VDDA_1P8_IOLDO1
CAP_VDDA_1P8_IOLDO1
CAP
H18
CAP_VDDSHV_SDIO
CAP_VDDSHV_SDIO
CAP
V9
CAP_VDD_WKUP
CAP_VDD_WKUP
CAP
G28
CSI0_RXN0
CSI0_RXN0
I
PD
1.8 V
VDDA_1P8_CSI
0
DPHY
PU/PD
No
H27
CSI0_RXN1
CSI0_RXN1
I
PD
1.8 V
VDDA_1P8_CSI
0
DPHY
PU/PD
No
F26
CSI0_RXN2
CSI0_RXN2
I
PD
1.8 V
VDDA_1P8_CSI
0
DPHY
PU/PD
No
H25
CSI0_RXN3
CSI0_RXN3
I
PD
1.8 V
VDDA_1P8_CSI
0
DPHY
PU/PD
No
G24
CSI0_RXN4
CSI0_RXN4
I
PD
1.8 V
VDDA_1P8_CSI
0
DPHY
PU/PD
No
F28
CSI0_RXP0
CSI0_RXP0
I
PD
1.8 V
VDDA_1P8_CSI
0
DPHY
PU/PD
No
G27
CSI0_RXP1
CSI0_RXP1
I
PD
1.8 V
VDDA_1P8_CSI
0
DPHY
PU/PD
No
G26
CSI0_RXP2
CSI0_RXP2
I
PD
1.8 V
VDDA_1P8_CSI
0
DPHY
PU/PD
No
G25
CSI0_RXP3
CSI0_RXP3
I
PD
1.8 V
VDDA_1P8_CSI
0
DPHY
PU/PD
No
F24
CSI0_RXP4
CSI0_RXP4
I
PD
1.8 V
VDDA_1P8_CSI
0
DPHY
PU/PD
No
A10
DDR_AC0
DDR_AC0
IO
OFF
1.1 V/1.2
V/1.35 V
VDDS_DDR
DDR
PU/PD
No
Terminal Configuration and Functions
Copyright © 2018–2019, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: DRA80M
ADVANCE INFORMATION
BALL NUMBER
[1]
11
DRA80M
SPRSP31E – APRIL 2018 – REVISED JUNE 2019
www.ti.com
Table 4-1. Pin Attributes (continued)
BALL NUMBER
[1]
BALL NAME [2]
SIGNAL NAME [3]
MUXMODE
[4]
TYPE [5]
BALL
BALL
RESET
I/O
RESET
REL.
VOLTAGE
STATE [6] MUXMODE VALUE [8]
[7]
POWER [9]
HYS [10]
BUFFER
TYPE [11]
PULL
UP/DOWN
TYPE [12]
DSIS [13]
RXACTIVE/
IO Daisy
TXDISABL
Chain [15]
E [14]
ADVANCE INFORMATION
D9
DDR_AC1
DDR_AC1
IO
OFF
1.1 V/1.2
V/1.35 V
VDDS_DDR
DDR
PU/PD
No
C9
DDR_AC2
DDR_AC2
IO
OFF
1.1 V/1.2
V/1.35 V
VDDS_DDR
DDR
PU/PD
No
E9
DDR_AC3
DDR_AC3
IO
OFF
1.1 V/1.2
V/1.35 V
VDDS_DDR
DDR
PU/PD
No
A9
DDR_AC4
DDR_AC4
IO
OFF
1.1 V/1.2
V/1.35 V
VDDS_DDR
DDR
PU/PD
No
E8
DDR_AC5
DDR_AC5
IO
OFF
1.1 V/1.2
V/1.35 V
VDDS_DDR
DDR
PU/PD
No
F8
DDR_AC6
DDR_AC6
IO
OFF
1.1 V/1.2
V/1.35 V
VDDS_DDR
DDR
PU/PD
No
C7
DDR_AC7
DDR_AC7
IO
OFF
1.1 V/1.2
V/1.35 V
VDDS_DDR
DDR
PU/PD
No
C8
DDR_AC8
DDR_AC8
IO
OFF
1.1 V/1.2
V/1.35 V
VDDS_DDR
DDR
PU/PD
No
D7
DDR_AC9
DDR_AC9
IO
OFF
1.1 V/1.2
V/1.35 V
VDDS_DDR
DDR
PU/PD
No
E7
DDR_AC10
DDR_AC10
IO
OFF
1.1 V/1.2
V/1.35 V
VDDS_DDR
DDR
PU/PD
No
A6
DDR_AC11
DDR_AC11
IO
OFF
1.1 V/1.2
V/1.35 V
VDDS_DDR
DDR
PU/PD
No
F7
DDR_AC12
DDR_AC12
IO
OFF
1.1 V/1.2
V/1.35 V
VDDS_DDR
DDR
PU/PD
No
D6
DDR_AC13
DDR_AC13
IO
OFF
1.1 V/1.2
V/1.35 V
VDDS_DDR
DDR
PU/PD
No
C6
DDR_AC14
DDR_AC14
IO
OFF
1.1 V/1.2
V/1.35 V
VDDS_DDR
DDR
PU/PD
No
F6
DDR_AC15
DDR_AC15
IO
OFF
1.1 V/1.2
V/1.35 V
VDDS_DDR
DDR
PU/PD
No
E6
DDR_AC16
DDR_AC16
IO
OFF
1.1 V/1.2
V/1.35 V
VDDS_DDR
DDR
PU/PD
No
E5
DDR_AC17
DDR_AC17
IO
OFF
1.1 V/1.2
V/1.35 V
VDDS_DDR
DDR
PU/PD
No
D8
DDR_AC18
DDR_AC18
IO
OFF
1.1 V/1.2
V/1.35 V
VDDS_DDR
DDR
PU/PD
No
D10
DDR_AC19
DDR_AC19
IO
OFF
1.1 V/1.2
V/1.35 V
VDDS_DDR
DDR
PU/PD
No
E10
DDR_AC20
DDR_AC20
IO
OFF
1.1 V/1.2
V/1.35 V
VDDS_DDR
DDR
PU/PD
No
C10
DDR_AC21
DDR_AC21
IO
OFF
1.1 V/1.2
V/1.35 V
VDDS_DDR
DDR
PU/PD
No
F11
DDR_AC22
DDR_AC22
IO
OFF
1.1 V/1.2
V/1.35 V
VDDS_DDR
DDR
PU/PD
No
B10
DDR_AC23
DDR_AC23
IO
OFF
1.1 V/1.2
V/1.35 V
VDDS_DDR
DDR
PU/PD
No
12
Terminal Configuration and Functions
Copyright © 2018–2019, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: DRA80M
DRA80M
www.ti.com
SPRSP31E – APRIL 2018 – REVISED JUNE 2019
Table 4-1. Pin Attributes (continued)
BALL NAME [2]
SIGNAL NAME [3]
MUXMODE
[4]
TYPE [5]
BALL
BALL
RESET
I/O
RESET
REL.
VOLTAGE
STATE [6] MUXMODE VALUE [8]
[7]
POWER [9]
HYS [10]
BUFFER
TYPE [11]
PULL
UP/DOWN
TYPE [12]
DSIS [13]
RXACTIVE/
IO Daisy
TXDISABL
Chain [15]
E [14]
D11
DDR_AC24
DDR_AC24
IO
OFF
1.1 V/1.2
V/1.35 V
VDDS_DDR
DDR
PU/PD
No
B11
DDR_AC25
DDR_AC25
IO
OFF
1.1 V/1.2
V/1.35 V
VDDS_DDR
DDR
PU/PD
No
C11
DDR_AC26
DDR_AC26
IO
OFF
1.1 V/1.2
V/1.35 V
VDDS_DDR
DDR
PU/PD
No
E11
DDR_AC27
DDR_AC27
IO
OFF
1.1 V/1.2
V/1.35 V
VDDS_DDR
DDR
PU/PD
No
E12
DDR_AC28
DDR_AC28
IO
OFF
1.1 V/1.2
V/1.35 V
VDDS_DDR
DDR
PU/PD
No
D12
DDR_AC29
DDR_AC29
IO
OFF
1.1 V/1.2
V/1.35 V
VDDS_DDR
DDR
PU/PD
No
D5
DDR_ALERTn
DDR_ALERTn
IO
OFF
1.1 V/1.2
V/1.35 V
VDDS_DDR
DDR
PU/PD
No
B8
DDR_CK0N
DDR_CK0N
IO
drive 1
(OFF)
1.1 V/1.2
V/1.35 V
VDDS_DDR
DDR
PU/PD
No
A8
DDR_CK0P
DDR_CK0P
IO
drive 0
(OFF)
1.1 V/1.2
V/1.35 V
VDDS_DDR
DDR
PU/PD
No
B7
DDR_CK1N
DDR_CK1N
IO
drive 1
(OFF)
1.1 V/1.2
V/1.35 V
VDDS_DDR
DDR
PU/PD
No
A7
DDR_CK1P
DDR_CK1P
IO
drive 0
(OFF)
1.1 V/1.2
V/1.35 V
VDDS_DDR
DDR
PU/PD
No
E1
DDR_DM0
DDR_DM0
IO
OFF
1.1 V/1.2
V/1.35 V
VDDS_DDR
DDR
PU/PD
No
C5
DDR_DM1
DDR_DM1
IO
OFF
1.1 V/1.2
V/1.35 V
VDDS_DDR
DDR
PU/PD
No
D14
DDR_DM2
DDR_DM2
IO
OFF
1.1 V/1.2
V/1.35 V
VDDS_DDR
DDR
PU/PD
No
B17
DDR_DM3
DDR_DM3
IO
OFF
1.1 V/1.2
V/1.35 V
VDDS_DDR
DDR
PU/PD
No
A3
DDR_DQ0
DDR_DQ0
IO
OFF
1.1 V/1.2
V/1.35 V
VDDS_DDR
DDR
PU/PD
No
B2
DDR_DQ1
DDR_DQ1
IO
OFF
1.1 V/1.2
V/1.35 V
VDDS_DDR
DDR
PU/PD
No
C2
DDR_DQ2
DDR_DQ2
IO
OFF
1.1 V/1.2
V/1.35 V
VDDS_DDR
DDR
PU/PD
No
D2
DDR_DQ3
DDR_DQ3
IO
OFF
1.1 V/1.2
V/1.35 V
VDDS_DDR
DDR
PU/PD
No
E2
DDR_DQ4
DDR_DQ4
IO
OFF
1.1 V/1.2
V/1.35 V
VDDS_DDR
DDR
PU/PD
No
G1
DDR_DQ5
DDR_DQ5
IO
OFF
1.1 V/1.2
V/1.35 V
VDDS_DDR
DDR
PU/PD
No
F2
DDR_DQ6
DDR_DQ6
IO
OFF
1.1 V/1.2
V/1.35 V
VDDS_DDR
DDR
PU/PD
No
F1
DDR_DQ7
DDR_DQ7
IO
OFF
1.1 V/1.2
V/1.35 V
VDDS_DDR
DDR
PU/PD
No
Terminal Configuration and Functions
Copyright © 2018–2019, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: DRA80M
ADVANCE INFORMATION
BALL NUMBER
[1]
13
DRA80M
SPRSP31E – APRIL 2018 – REVISED JUNE 2019
www.ti.com
Table 4-1. Pin Attributes (continued)
BALL NUMBER
[1]
BALL NAME [2]
SIGNAL NAME [3]
MUXMODE
[4]
TYPE [5]
BALL
BALL
RESET
I/O
RESET
REL.
VOLTAGE
STATE [6] MUXMODE VALUE [8]
[7]
POWER [9]
HYS [10]
BUFFER
TYPE [11]
PULL
UP/DOWN
TYPE [12]
DSIS [13]
RXACTIVE/
IO Daisy
TXDISABL
Chain [15]
E [14]
ADVANCE INFORMATION
E3
DDR_DQ8
DDR_DQ8
IO
OFF
1.1 V/1.2
V/1.35 V
VDDS_DDR
DDR
PU/PD
No
C3
DDR_DQ9
DDR_DQ9
IO
OFF
1.1 V/1.2
V/1.35 V
VDDS_DDR
DDR
PU/PD
No
D3
DDR_DQ10
DDR_DQ10
IO
OFF
1.1 V/1.2
V/1.35 V
VDDS_DDR
DDR
PU/PD
No
B3
DDR_DQ11
DDR_DQ11
IO
OFF
1.1 V/1.2
V/1.35 V
VDDS_DDR
DDR
PU/PD
No
D4
DDR_DQ12
DDR_DQ12
IO
OFF
1.1 V/1.2
V/1.35 V
VDDS_DDR
DDR
PU/PD
No
C4
DDR_DQ13
DDR_DQ13
IO
OFF
1.1 V/1.2
V/1.35 V
VDDS_DDR
DDR
PU/PD
No
B4
DDR_DQ14
DDR_DQ14
IO
OFF
1.1 V/1.2
V/1.35 V
VDDS_DDR
DDR
PU/PD
No
B5
DDR_DQ15
DDR_DQ15
IO
OFF
1.1 V/1.2
V/1.35 V
VDDS_DDR
DDR
PU/PD
No
E13
DDR_DQ16
DDR_DQ16
IO
OFF
1.1 V/1.2
V/1.35 V
VDDS_DDR
DDR
PU/PD
No
C14
DDR_DQ17
DDR_DQ17
IO
OFF
1.1 V/1.2
V/1.35 V
VDDS_DDR
DDR
PU/PD
No
B14
DDR_DQ18
DDR_DQ18
IO
OFF
1.1 V/1.2
V/1.35 V
VDDS_DDR
DDR
PU/PD
No
A14
DDR_DQ19
DDR_DQ19
IO
OFF
1.1 V/1.2
V/1.35 V
VDDS_DDR
DDR
PU/PD
No
E14
DDR_DQ20
DDR_DQ20
IO
OFF
1.1 V/1.2
V/1.35 V
VDDS_DDR
DDR
PU/PD
No
B13
DDR_DQ21
DDR_DQ21
IO
OFF
1.1 V/1.2
V/1.35 V
VDDS_DDR
DDR
PU/PD
No
C13
DDR_DQ22
DDR_DQ22
IO
OFF
1.1 V/1.2
V/1.35 V
VDDS_DDR
DDR
PU/PD
No
D13
DDR_DQ23
DDR_DQ23
IO
OFF
1.1 V/1.2
V/1.35 V
VDDS_DDR
DDR
PU/PD
No
D15
DDR_DQ24
DDR_DQ24
IO
OFF
1.1 V/1.2
V/1.35 V
VDDS_DDR
DDR
PU/PD
No
C15
DDR_DQ25
DDR_DQ25
IO
OFF
1.1 V/1.2
V/1.35 V
VDDS_DDR
DDR
PU/PD
No
E16
DDR_DQ26
DDR_DQ26
IO
OFF
1.1 V/1.2
V/1.35 V
VDDS_DDR
DDR
PU/PD
No
E15
DDR_DQ27
DDR_DQ27
IO
OFF
1.1 V/1.2
V/1.35 V
VDDS_DDR
DDR
PU/PD
No
D16
DDR_DQ28
DDR_DQ28
IO
OFF
1.1 V/1.2
V/1.35 V
VDDS_DDR
DDR
PU/PD
No
B16
DDR_DQ29
DDR_DQ29
IO
OFF
1.1 V/1.2
V/1.35 V
VDDS_DDR
DDR
PU/PD
No
C16
DDR_DQ30
DDR_DQ30
IO
OFF
1.1 V/1.2
V/1.35 V
VDDS_DDR
DDR
PU/PD
No
14
Terminal Configuration and Functions
Copyright © 2018–2019, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: DRA80M
DRA80M
www.ti.com
SPRSP31E – APRIL 2018 – REVISED JUNE 2019
Table 4-1. Pin Attributes (continued)
BALL NAME [2]
SIGNAL NAME [3]
MUXMODE
[4]
TYPE [5]
BALL
BALL
RESET
I/O
RESET
REL.
VOLTAGE
STATE [6] MUXMODE VALUE [8]
[7]
POWER [9]
HYS [10]
BUFFER
TYPE [11]
PULL
UP/DOWN
TYPE [12]
DSIS [13]
RXACTIVE/
IO Daisy
TXDISABL
Chain [15]
E [14]
A17
DDR_DQ31
DDR_DQ31
IO
OFF
1.1 V/1.2
V/1.35 V
VDDS_DDR
DDR
PU/PD
No
C1
DDR_DQS0N
DDR_DQS0N
IO
OFF
1.1 V/1.2
V/1.35 V
VDDS_DDR
DDR
PU/PD
No
D1
DDR_DQS0P
DDR_DQS0P
IO
OFF
1.1 V/1.2
V/1.35 V
VDDS_DDR
DDR
PU/PD
No
A4
DDR_DQS1N
DDR_DQS1N
IO
OFF
1.1 V/1.2
V/1.35 V
VDDS_DDR
DDR
PU/PD
No
A5
DDR_DQS1P
DDR_DQS1P
IO
OFF
1.1 V/1.2
V/1.35 V
VDDS_DDR
DDR
PU/PD
No
A12
DDR_DQS2N
DDR_DQS2N
IO
OFF
1.1 V/1.2
V/1.35 V
VDDS_DDR
DDR
PU/PD
No
A13
DDR_DQS2P
DDR_DQS2P
IO
OFF
1.1 V/1.2
V/1.35 V
VDDS_DDR
DDR
PU/PD
No
A16
DDR_DQS3N
DDR_DQS3N
IO
OFF
1.1 V/1.2
V/1.35 V
VDDS_DDR
DDR
PU/PD
No
A15
DDR_DQS3P
DDR_DQS3P
IO
OFF
1.1 V/1.2
V/1.35 V
VDDS_DDR
DDR
PU/PD
No
B19
DDR_ECC_D0
DDR_ECC_D0
IO
OFF
1.1 V/1.2
V/1.35 V
VDDS_DDR
DDR
PU/PD
No
B18
DDR_ECC_D1
DDR_ECC_D1
IO
OFF
1.1 V/1.2
V/1.35 V
VDDS_DDR
DDR
PU/PD
No
C18
DDR_ECC_D2
DDR_ECC_D2
IO
OFF
1.1 V/1.2
V/1.35 V
VDDS_DDR
DDR
PU/PD
No
D18
DDR_ECC_D3
DDR_ECC_D3
IO
OFF
1.1 V/1.2
V/1.35 V
VDDS_DDR
DDR
PU/PD
No
E18
DDR_ECC_D4
DDR_ECC_D4
IO
OFF
1.1 V/1.2
V/1.35 V
VDDS_DDR
DDR
PU/PD
No
E17
DDR_ECC_D5
DDR_ECC_D5
IO
OFF
1.1 V/1.2
V/1.35 V
VDDS_DDR
DDR
PU/PD
No
D17
DDR_ECC_D6
DDR_ECC_D6
IO
OFF
1.1 V/1.2
V/1.35 V
VDDS_DDR
DDR
PU/PD
No
C17
DDR_ECC_DM
DDR_ECC_DM
IO
OFF
1.1 V/1.2
V/1.35 V
VDDS_DDR
DDR
PU/PD
No
A18
DDR_ECC_DQSN
DDR_ECC_DQSN
IO
OFF
1.1 V/1.2
V/1.35 V
VDDS_DDR
DDR
PU/PD
No
A19
DDR_ECC_DQSP
DDR_ECC_DQSP
IO
OFF
1.1 V/1.2
V/1.35 V
VDDS_DDR
DDR
PU/PD
No
F16
DDR_FS_RESETn
DDR_FS_RESETn
IO
drive 0
(OFF)
1.1 V/1.2
V/1.35 V
VDDS_DDR
LVCMOS
PD
No
A11
DDR_RESETn
DDR_RESETn
IO
drive 0
(OFF)
1.1 V/1.2
V/1.35 V
VDDS_DDR
DDR
PU/PD
No
F12
DDR_VREF0
DDR_VREF0
A
0.5*VDDS_ VDDS_DDR
DDR
DDR
No
F15
DDR_VREF_ZQ
DDR_VREF_ZQ
A
VDDS_DDR
DDR
No
Terminal Configuration and Functions
Copyright © 2018–2019, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: DRA80M
ADVANCE INFORMATION
BALL NUMBER
[1]
15
DRA80M
SPRSP31E – APRIL 2018 – REVISED JUNE 2019
www.ti.com
Table 4-1. Pin Attributes (continued)
BALL NUMBER
[1]
BALL NAME [2]
SIGNAL NAME [3]
MUXMODE
[4]
TYPE [5]
F13
DDR_VTP
DDR_VTP
D21
ECAP0_IN_APWM_OUT
ECAP0_IN_APWM_OUT
0
IO
SYNC0_OUT
1
O
CPTS0_RFT_CLK
2
I
GPIO1_86
7
IO
BALL
BALL
RESET
I/O
RESET
REL.
VOLTAGE
STATE [6] MUXMODE VALUE [8]
[7]
A
1.1 V/1.2
V/1.35 V
OFF
7
POWER [9]
HYS [10]
VDDS_DDR
1.8 V/3.3 V VDDSHV0
BUFFER
TYPE [11]
PULL
UP/DOWN
TYPE [12]
DSIS [13]
RXACTIVE/
IO Daisy
TXDISABL
Chain [15]
E [14]
DDR
Yes
LVCMOS
No
PU/PD
0
0/1
Yes
0
0
ADVANCE INFORMATION
AA2
EMU0
EMU0
0
IO
PU
0
1.8 V/3.3 V VDDSHV0_WKU Yes
P
LVCMOS
PU/PD
1/1
Yes
AA1
EMU1
EMU1
0
IO
PU
0
1.8 V/3.3 V VDDSHV0_WKU Yes
P
LVCMOS
PU/PD
1/1
Yes
A22
EXT_REFCLK1
EXT_REFCLK1
0
I
OFF
7
1.8 V/3.3 V VDDSHV0
Yes
LVCMOS
PU/PD
0/1
Yes
SYNC1_OUT
1
O
GPIO1_87
7
IO
GPMC0_ADVn_ALE
0
O
OFF
7
1.8 V/3.3 V VDDSHV2
Yes
LVCMOS
PU/PD
1/1
Yes
VOUT1_DATA17
1
O
GPIO0_17
7
IO
BOOTMODE16
Bootstrap
I
GPMC0_CLK
0
IO
0/1
Yes
VOUT1_DATA16
1
O
VIN0_PCLK
2
I
GPIO0_16
7
IO
GPMC0_DIR
0
O
0/1
Yes
VOUT1_HSYNC
1
O
VIN0_DATA8
2
I
0
PRG2_PWM1_B0
3
IO
1
PRG2_IEP1_EDC_SYNC_OUT0
4
O
TIMER_IO6
5
IO
0
PRG2_IEP0_EDIO_DATA_IN_OUT29
6
IO
0
GPIO0_25
7
IO
GPMC0_OEn_REn
0
O
1/1
Yes
VOUT1_DATA18
1
O
GPIO0_18
7
IO
BOOTMODE17
Bootstrap
I
GPMC0_WEn
0
O
1/1
Yes
VOUT1_DATA19
1
O
GPIO0_19
7
IO
0
BOOTMODE18
Bootstrap
I
0
P25
R28
T24
P26
U28
16
GPMC0_ADVn_ALE
GPMC0_CLK
GPMC0_DIR
GPMC0_OEn_REn
GPMC0_WEn
0
0
0
0
OFF
7
1.8 V/3.3 V VDDSHV2
Yes
LVCMOS
PU/PD
0
0
0
OFF
7
1.8 V/3.3 V VDDSHV2
Yes
LVCMOS
PU/PD
0
OFF
7
1.8 V/3.3 V VDDSHV2
Yes
LVCMOS
PU/PD
0
0
OFF
7
1.8 V/3.3 V VDDSHV2
Terminal Configuration and Functions
Yes
LVCMOS
PU/PD
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Table 4-1. Pin Attributes (continued)
T25
M27
M23
M28
M24
N24
N27
N28
BALL NAME [2]
GPMC0_WPn
GPMC0_AD0
GPMC0_AD1
GPMC0_AD2
GPMC0_AD3
GPMC0_AD4
GPMC0_AD5
GPMC0_AD6
SIGNAL NAME [3]
MUXMODE
[4]
TYPE [5]
BALL
BALL
RESET
I/O
RESET
REL.
VOLTAGE
STATE [6] MUXMODE VALUE [8]
[7]
POWER [9]
HYS [10]
BUFFER
TYPE [11]
PULL
UP/DOWN
TYPE [12]
OFF
7
1.8 V/3.3 V VDDSHV2
Yes
LVCMOS
PU/PD
OFF
7
1.8 V/3.3 V VDDSHV2
Yes
LVCMOS
PU/PD
DSIS [13]
GPMC0_WPn
0
O
VOUT1_VSYNC
1
O
GPIO0_24
7
IO
GPMC0_AD0
0
IO
VOUT1_DATA0
1
O
VIN0_DATA12
2
I
0
GPIO0_0
7
IO
0
BOOTMODE00
Bootstrap
I
GPMC0_AD1
0
IO
VOUT1_DATA1
1
O
VIN0_DATA13
2
I
0
GPIO0_1
7
IO
0
BOOTMODE01
Bootstrap
I
GPMC0_AD2
0
IO
VOUT1_DATA2
1
O
VIN0_DATA14
2
I
0
GPIO0_2
7
IO
0
BOOTMODE02
Bootstrap
I
GPMC0_AD3
0
IO
VOUT1_DATA3
1
O
VIN0_DATA15
2
I
0
GPIO0_3
7
IO
0
BOOTMODE03
Bootstrap
I
GPMC0_AD4
0
IO
VOUT1_DATA4
1
O
GPIO0_4
7
IO
BOOTMODE04
Bootstrap
I
GPMC0_AD5
0
IO
VOUT1_DATA5
1
O
GPIO0_5
7
IO
BOOTMODE05
Bootstrap
I
GPMC0_AD6
0
IO
VOUT1_DATA6
1
O
GPIO0_6
7
IO
0
BOOTMODE06
Bootstrap
I
0
RXACTIVE/
IO Daisy
TXDISABL
Chain [15]
E [14]
0/1
Yes
1/1
Yes
1/1
Yes
1/1
Yes
1/1
Yes
1/1
Yes
1/1
Yes
1/1
Yes
0
0
ADVANCE INFORMATION
BALL NUMBER
[1]
0
OFF
7
1.8 V/3.3 V VDDSHV2
Yes
LVCMOS
PU/PD
0
0
OFF
7
1.8 V/3.3 V VDDSHV2
Yes
LVCMOS
PU/PD
0
0
OFF
7
1.8 V/3.3 V VDDSHV2
Yes
LVCMOS
PU/PD
0
0
OFF
7
1.8 V/3.3 V VDDSHV2
Yes
LVCMOS
PU/PD
0
0
0
OFF
7
1.8 V/3.3 V VDDSHV2
Yes
LVCMOS
PU/PD
0
0
0
OFF
7
1.8 V/3.3 V VDDSHV2
Yes
LVCMOS
PU/PD
0
Terminal Configuration and Functions
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Table 4-1. Pin Attributes (continued)
BALL NUMBER
[1]
M25
N23
ADVANCE INFORMATION
M26
P28
P27
18
BALL NAME [2]
GPMC0_AD7
GPMC0_AD8
GPMC0_AD9
GPMC0_AD10
GPMC0_AD11
SIGNAL NAME [3]
MUXMODE
[4]
TYPE [5]
BALL
BALL
RESET
I/O
RESET
REL.
VOLTAGE
STATE [6] MUXMODE VALUE [8]
[7]
OFF
7
POWER [9]
1.8 V/3.3 V VDDSHV2
HYS [10]
Yes
BUFFER
TYPE [11]
LVCMOS
PULL
UP/DOWN
TYPE [12]
PU/PD
DSIS [13]
GPMC0_AD7
0
IO
VOUT1_DATA7
1
O
0
GPIO0_7
7
IO
BOOTMODE07
Bootstrap
I
GPMC0_AD8
0
IO
VOUT1_DATA8
1
O
VIN0_DATA0
2
I
0
PRG2_PRU0_GPO12
3
IO
0
PRG2_PRU0_GPI12
4
I
0
PRG2_PWM2_A0
5
IO
0
GPIO0_8
7
IO
0
BOOTMODE08
Bootstrap
I
GPMC0_AD9
0
IO
VOUT1_DATA9
1
O
VIN0_DATA1
2
I
0
PRG2_PRU0_GPO13
3
IO
0
PRG2_PRU0_GPI13
4
I
0
PRG2_PWM2_B0
5
IO
1
GPIO0_9
7
IO
0
BOOTMODE09
Bootstrap
I
GPMC0_AD10
0
IO
VOUT1_DATA10
1
O
VIN0_DATA2
2
I
0
PRG2_PRU0_GPO14
3
IO
0
PRG2_PRU0_GPI14
4
I
0
PRG2_PWM0_TZ_IN
6
I
0
GPIO0_10
7
IO
0
BOOTMODE10
Bootstrap
I
GPMC0_AD11
0
IO
VOUT1_DATA11
1
O
VIN0_DATA3
2
I
0
PRG2_PRU0_GPO15
3
IO
0
PRG2_PRU0_GPI15
4
I
0
PRG2_PWM2_A1
5
IO
0
GPIO0_11
7
IO
0
BOOTMODE11
Bootstrap
I
0
RXACTIVE/
IO Daisy
TXDISABL
Chain [15]
E [14]
1/1
Yes
1/1
Yes
1/1
Yes
1/1
Yes
1/1
Yes
0
0
OFF
7
1.8 V/3.3 V VDDSHV2
Yes
LVCMOS
PU/PD
0
0
OFF
7
1.8 V/3.3 V VDDSHV2
Yes
LVCMOS
PU/PD
0
0
OFF
7
1.8 V/3.3 V VDDSHV2
Yes
LVCMOS
PU/PD
0
0
OFF
7
1.8 V/3.3 V VDDSHV2
Terminal Configuration and Functions
Yes
LVCMOS
PU/PD
0
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SPRSP31E – APRIL 2018 – REVISED JUNE 2019
Table 4-1. Pin Attributes (continued)
N26
N25
P24
R27
T28
BALL NAME [2]
GPMC0_AD12
GPMC0_AD13
GPMC0_AD14
GPMC0_AD15
GPMC0_BE0n_CLE
SIGNAL NAME [3]
MUXMODE
[4]
TYPE [5]
BALL
BALL
RESET
I/O
RESET
REL.
VOLTAGE
STATE [6] MUXMODE VALUE [8]
[7]
OFF
7
POWER [9]
1.8 V/3.3 V VDDSHV2
HYS [10]
Yes
BUFFER
TYPE [11]
LVCMOS
PULL
UP/DOWN
TYPE [12]
PU/PD
DSIS [13]
GPMC0_AD12
0
IO
VOUT1_DATA12
1
O
0
VIN0_DATA4
2
I
0
PRG2_PRU1_GPO12
3
IO
0
PRG2_PRU1_GPI12
4
I
0
PRG2_PWM2_B1
5
IO
1
GPIO0_12
7
IO
0
BOOTMODE12
Bootstrap
I
GPMC0_AD13
0
IO
VOUT1_DATA13
1
O
VIN0_DATA5
2
I
0
PRG2_PRU1_GPO13
3
IO
0
PRG2_PRU1_GPI13
4
I
0
PRG2_PWM2_A2
5
IO
0
GPIO0_13
7
IO
0
BOOTMODE13
Bootstrap
I
GPMC0_AD14
0
IO
VOUT1_DATA14
1
O
VIN0_DATA6
2
I
0
PRG2_PRU1_GPO14
3
IO
0
PRG2_PRU1_GPI14
4
I
0
PRG2_PWM0_TZ_OUT
6
O
GPIO0_14
7
IO
BOOTMODE14
Bootstrap
I
GPMC0_AD15
0
IO
VOUT1_DATA15
1
O
VIN0_DATA7
2
I
0
PRG2_PRU1_GPO15
3
IO
0
PRG2_PRU1_GPI15
4
I
0
PRG2_PWM2_B2
5
IO
1
GPIO0_15
7
IO
0
BOOTMODE15
Bootstrap
I
GPMC0_BE0n_CLE
0
O
VOUT1_DATA20
1
O
GPIO0_20
7
IO
RXACTIVE/
IO Daisy
TXDISABL
Chain [15]
E [14]
1/1
Yes
1/1
Yes
1/1
Yes
1/1
Yes
0/1
Yes
ADVANCE INFORMATION
BALL NUMBER
[1]
0
OFF
7
1.8 V/3.3 V VDDSHV2
Yes
LVCMOS
PU/PD
0
0
OFF
7
1.8 V/3.3 V VDDSHV2
Yes
LVCMOS
PU/PD
0
0
0
OFF
7
1.8 V/3.3 V VDDSHV2
Yes
LVCMOS
PU/PD
0
0
OFF
7
1.8 V/3.3 V VDDSHV2
Yes
LVCMOS
PU/PD
0
Terminal Configuration and Functions
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Table 4-1. Pin Attributes (continued)
BALL NUMBER
[1]
P23
ADVANCE INFORMATION
R24
T23
R25
T27
R26
20
BALL NAME [2]
GPMC0_BE1n
GPMC0_CSn0
GPMC0_CSn1
GPMC0_CSn2
GPMC0_CSn3
GPMC0_WAIT0
SIGNAL NAME [3]
MUXMODE
[4]
TYPE [5]
BALL
BALL
RESET
I/O
RESET
REL.
VOLTAGE
STATE [6] MUXMODE VALUE [8]
[7]
OFF
7
POWER [9]
1.8 V/3.3 V VDDSHV2
HYS [10]
Yes
BUFFER
TYPE [11]
LVCMOS
PULL
UP/DOWN
TYPE [12]
DSIS [13]
GPMC0_BE1n
0
O
VOUT1_DATA21
1
O
PU/PD
VIN0_HD
2
I
0
PRG2_PRU0_GPO17
3
IO
0
PRG2_PRU0_GPI17
4
I
0
TIMER_IO2
5
IO
0
PRG2_PWM2_TZ_IN
6
I
0
GPIO0_21
7
IO
GPMC0_CSn0
0
O
VOUT1_PCLK
1
O
GPIO0_26
7
IO
GPMC0_CSn1
0
O
VOUT1_DE
1
O
VIN0_DATA9
2
I
0
PRG2_PRU1_GPO17
3
IO
0
PRG2_PRU1_GPI17
4
I
0
TIMER_IO7
5
IO
0
PRG2_PWM2_TZ_OUT
6
O
GPIO0_27
7
IO
GPMC0_CSn2
0
O
VOUT1_EXTPCLKIN
1
I
0
VIN0_DATA10
2
I
0
GPMC0_A27
3
OZ
PRG2_IEP1_EDC_LATCH_IN1
4
I
0
I2C2_SDA
5
IOD
1
PRG2_IEP0_EDIO_DATA_IN_OUT30
6
IO
0
GPIO0_28
7
IO
GPMC0_CSn3
0
O
VIN0_DATA11
2
I
GPMC0_A26
3
OZ
PRG2_IEP1_EDC_SYNC_OUT1
4
O
I2C2_SCL
5
IOD
1
PRG2_IEP0_EDIO_DATA_IN_OUT31
6
IO
0
GPIO0_29
7
IO
GPMC0_WAIT0
0
I
VOUT1_DATA22
1
O
GPIO0_22
7
IO
RXACTIVE/
IO Daisy
TXDISABL
Chain [15]
E [14]
0/1
Yes
0/1
Yes
0/1
Yes
0/1
Yes
0/1
Yes
0/1
Yes
0
OFF
7
1.8 V/3.3 V VDDSHV2
Yes
LVCMOS
PU/PD
OFF
7
1.8 V/3.3 V VDDSHV2
Yes
LVCMOS
PU/PD
0
0
OFF
7
1.8 V/3.3 V VDDSHV2
Yes
LVCMOS
PU/PD
0
OFF
7
1.8 V/3.3 V VDDSHV2
Yes
LVCMOS
PU/PD
0
0
OFF
7
1.8 V/3.3 V VDDSHV2
Terminal Configuration and Functions
Yes
LVCMOS
PU/PD
1
0
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SPRSP31E – APRIL 2018 – REVISED JUNE 2019
Table 4-1. Pin Attributes (continued)
R23
BALL NAME [2]
GPMC0_WAIT1
SIGNAL NAME [3]
MUXMODE
[4]
TYPE [5]
BALL
BALL
RESET
I/O
RESET
REL.
VOLTAGE
STATE [6] MUXMODE VALUE [8]
[7]
OFF
7
POWER [9]
1.8 V/3.3 V VDDSHV2
HYS [10]
Yes
BUFFER
TYPE [11]
LVCMOS
PULL
UP/DOWN
TYPE [12]
PU/PD
DSIS [13]
GPMC0_WAIT1
0
I
VOUT1_DATA23
1
O
1
VIN0_VD
2
I
0
PRG2_PWM1_A0
3
IO
0
PRG2_IEP1_EDC_LATCH_IN0
4
I
0
TIMER_IO3
5
IO
0
PRG2_IEP0_EDIO_DATA_IN_OUT28
6
IO
0
GPIO0_23
7
IO
RXACTIVE/
IO Daisy
TXDISABL
Chain [15]
E [14]
0/1
Yes
0
D20
I2C0_SCL
I2C0_SCL
0
IOD
OFF
7
1.8 V/3.3 V VDDSHV0
Yes
LVCMOSFS
PU/PD
1
1/1
Yes
C21
I2C0_SDA
I2C0_SDA
0
IOD
OFF
7
1.8 V/3.3 V VDDSHV0
Yes
LVCMOSFS
PU/PD
1
1/1
Yes
B21
I2C1_SCL
I2C1_SCL
0
IOD
OFF
7
1.8 V/3.3 V VDDSHV0
Yes
1
1/1
Yes
1
I
LVCMOSFS
PU/PD
CPTS0_HW1TSPUSH
I2C1_SDA
0
IOD
1/1
Yes
1
I
LVCMOSFS
PU/PD
CPTS0_HW2TSPUSH
E21
I2C1_SDA
ADVANCE INFORMATION
BALL NUMBER
[1]
OFF
7
1.8 V/3.3 V VDDSHV0
Yes
0
1
0
K2
MCU_ADC0_REFN
MCU_ADC0_REFN
A
1.8 V
VDDA_ADC_MC
U
Analog
No
K3
MCU_ADC0_REFP
MCU_ADC0_REFP
A
1.8 V
VDDA_ADC_MC
U
Analog
No
H3
MCU_ADC1_REFN
MCU_ADC1_REFN
A
1.8 V
VDDA_ADC_MC
U
Analog
No
H2
MCU_ADC1_REFP
MCU_ADC1_REFP
A
1.8 V
VDDA_ADC_MC
U
Analog
No
K5
MCU_ADC0_AIN0
MCU_ADC0_AIN0
A
1.8 V
VDDA_ADC_MC
U
Analog
No
J3
MCU_ADC0_AIN1
MCU_ADC0_AIN1
A
1.8 V
VDDA_ADC_MC
U
Analog
No
J1
MCU_ADC0_AIN2
MCU_ADC0_AIN2
A
1.8 V
VDDA_ADC_MC
U
Analog
No
J5
MCU_ADC0_AIN3
MCU_ADC0_AIN3
A
1.8 V
VDDA_ADC_MC
U
Analog
No
K4
MCU_ADC0_AIN4
MCU_ADC0_AIN4
A
1.8 V
VDDA_ADC_MC
U
Analog
No
J4
MCU_ADC0_AIN5
MCU_ADC0_AIN5
A
1.8 V
VDDA_ADC_MC
U
Analog
No
J2
MCU_ADC0_AIN6
MCU_ADC0_AIN6
A
1.8 V
VDDA_ADC_MC
U
Analog
No
J6
MCU_ADC0_AIN7
MCU_ADC0_AIN7
A
1.8 V
VDDA_ADC_MC
U
Analog
No
F4
MCU_ADC1_AIN0
MCU_ADC1_AIN0
A
1.8 V
VDDA_ADC_MC
U
Analog
No
Terminal Configuration and Functions
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Table 4-1. Pin Attributes (continued)
BALL NUMBER
[1]
BALL NAME [2]
SIGNAL NAME [3]
MUXMODE
[4]
TYPE [5]
BALL
BALL
RESET
I/O
RESET
REL.
VOLTAGE
STATE [6] MUXMODE VALUE [8]
[7]
POWER [9]
HYS [10]
BUFFER
TYPE [11]
PULL
UP/DOWN
TYPE [12]
DSIS [13]
RXACTIVE/
IO Daisy
TXDISABL
Chain [15]
E [14]
ADVANCE INFORMATION
G6
MCU_ADC1_AIN1
MCU_ADC1_AIN1
A
1.8 V
VDDA_ADC_MC
U
Analog
No
G4
MCU_ADC1_AIN2
MCU_ADC1_AIN2
A
1.8 V
VDDA_ADC_MC
U
Analog
No
H5
MCU_ADC1_AIN3
MCU_ADC1_AIN3
A
1.8 V
VDDA_ADC_MC
U
Analog
No
F5
MCU_ADC1_AIN4
MCU_ADC1_AIN4
A
1.8 V
VDDA_ADC_MC
U
Analog
No
G5
MCU_ADC1_AIN5
MCU_ADC1_AIN5
A
1.8 V
VDDA_ADC_MC
U
Analog
No
G3
MCU_ADC1_AIN6
MCU_ADC1_AIN6
A
1.8 V
VDDA_ADC_MC
U
Analog
No
H4
MCU_ADC1_AIN7
MCU_ADC1_AIN7
A
1.8 V
VDDA_ADC_MC
U
Analog
No
V5
MCU_BYP_POR
MCU_BYP_POR
I
OFF
1.8 V/3.3 V VDDSHV0_WKU Yes
P
LVCMOS
No
AD8
MCU_I2C0_SCL
MCU_I2C0_SCL
0
IOD
OFF
0
1.8 V/3.3 V VDDSHV0_WKU Yes
P
I2C OPEN
DRAIN
1
1/0
Yes
AD7
MCU_I2C0_SDA
MCU_I2C0_SDA
0
IOD
OFF
0
1.8 V/3.3 V VDDSHV0_WKU Yes
P
I2C OPEN
DRAIN
1
1/0
Yes
W2
MCU_MCAN0_RX
MCU_MCAN0_RX
0
I
OFF
7
0
0/1
Yes
7
IO
1.8 V/3.3 V VDDSHV0_WKU Yes
P
LVCMOS
WKUP_GPIO0_55
MCU_MCAN0_TX
0
O
0/1
Yes
7
IO
1.8 V/3.3 V VDDSHV0_WKU Yes
P
LVCMOS
WKUP_GPIO0_54
MCU_MDIO0_MDC
0
O
0/1
Yes
7
IO
1.8 V/3.3 V VDDSHV2_WKU Yes
P
LVCMOS
WKUP_GPIO0_47
MCU_MDIO0_MDIO
0
IO
0/1
Yes
7
IO
1.8 V/3.3 V VDDSHV2_WKU Yes
P
LVCMOS
WKUP_GPIO0_46
MCU_OSPI0_CLK
0
O
0/1
Yes
MCU_HYPERBUS0_CK
1
O
WKUP_GPIO0_12
7
IO
MCU_OSPI0_DQS
0
I
0/1
Yes
MCU_HYPERBUS0_RWDS
1
IO
WKUP_GPIO0_14
7
IO
MCU_OSPI0_LBCLKO
0
IO
0/1
Yes
MCU_HYPERBUS0_CKn
1
O
WKUP_GPIO0_13
7
IO
MCU_OSPI1_CLK
0
O
0/1
Yes
WKUP_GPIO0_25
7
IO
W1
L1
L4
V1
U2
U1
T1
22
MCU_MCAN0_TX
MCU_MDIO0_MDC
MCU_MDIO0_MDIO
MCU_OSPI0_CLK
MCU_OSPI0_DQS
MCU_OSPI0_LBCLKO
MCU_OSPI1_CLK
OFF
OFF
OFF
7
7
7
PU/PD
0
PU/PD
0
0
PU/PD
0
PU/PD
0
0
OFF
7
1.8 V/3.3 V VDDSHV1_WKU Yes
P
LVCMOS
PU/PD
OFF
7
1.8 V/3.3 V VDDSHV1_WKU Yes
P
LVCMOS
PU/PD
0
0
0
0
OFF
7
1.8 V/3.3 V VDDSHV1_WKU Yes
P
LVCMOS
PU/PD
OFF
7
1.8 V/3.3 V VDDSHV1_WKU Yes
P
LVCMOS
PU/PD
0
Terminal Configuration and Functions
0
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SPRSP31E – APRIL 2018 – REVISED JUNE 2019
Table 4-1. Pin Attributes (continued)
P2
R1
R4
R5
U4
U5
T2
T3
T4
T5
R2
BALL NAME [2]
MCU_OSPI1_DQS
MCU_OSPI1_LBCLKO
MCU_OSPI0_CSn0
MCU_OSPI0_CSn1
MCU_OSPI0_D0
MCU_OSPI0_D1
MCU_OSPI0_D2
MCU_OSPI0_D3
MCU_OSPI0_D4
MCU_OSPI0_D5
MCU_OSPI0_D6
SIGNAL NAME [3]
MUXMODE
[4]
TYPE [5]
MCU_OSPI1_DQS
0
I
MCU_OSPI0_CSn3
1
O
MCU_HYPERBUS0_INTn
2
I
WKUP_GPIO0_27
7
IO
MCU_OSPI1_LBCLKO
0
IO
MCU_OSPI0_CSn2
1
O
MCU_HYPERBUS0_RESETOn
2
I
WKUP_GPIO0_26
7
IO
MCU_OSPI0_CSn0
0
O
MCU_HYPERBUS0_CSn0
1
O
WKUP_GPIO0_23
7
IO
MCU_OSPI0_CSn1
0
O
MCU_HYPERBUS0_RESETn
1
O
WKUP_GPIO0_24
7
IO
MCU_OSPI0_D0
0
IO
MCU_HYPERBUS0_DQ0
1
IO
WKUP_GPIO0_15
7
IO
MCU_OSPI0_D1
0
IO
MCU_HYPERBUS0_DQ1
1
IO
WKUP_GPIO0_16
7
IO
MCU_OSPI0_D2
0
IO
MCU_HYPERBUS0_DQ2
1
IO
WKUP_GPIO0_17
7
IO
MCU_OSPI0_D3
0
IO
MCU_HYPERBUS0_DQ3
1
IO
WKUP_GPIO0_18
7
IO
MCU_OSPI0_D4
0
IO
MCU_HYPERBUS0_DQ4
1
IO
WKUP_GPIO0_19
7
IO
MCU_OSPI0_D5
0
IO
MCU_HYPERBUS0_DQ5
1
IO
WKUP_GPIO0_20
7
IO
MCU_OSPI0_D6
0
IO
MCU_HYPERBUS0_DQ6
1
IO
WKUP_GPIO0_21
7
IO
BALL
BALL
RESET
I/O
RESET
REL.
VOLTAGE
STATE [6] MUXMODE VALUE [8]
[7]
OFF
7
POWER [9]
HYS [10]
1.8 V/3.3 V VDDSHV1_WKU Yes
P
BUFFER
TYPE [11]
LVCMOS
PULL
UP/DOWN
TYPE [12]
PU/PD
DSIS [13]
0
RXACTIVE/
IO Daisy
TXDISABL
Chain [15]
E [14]
0/1
Yes
0/1
Yes
0/1
Yes
0/1
Yes
0/1
Yes
0/1
Yes
0/1
Yes
0/1
Yes
0/1
Yes
0/1
Yes
0/1
Yes
1
0
OFF
7
1.8 V/3.3 V VDDSHV1_WKU Yes
P
LVCMOS
PU/PD
0
1
ADVANCE INFORMATION
BALL NUMBER
[1]
0
OFF
7
1.8 V/3.3 V VDDSHV1_WKU Yes
P
LVCMOS
PU/PD
OFF
7
1.8 V/3.3 V VDDSHV1_WKU Yes
P
LVCMOS
PU/PD
OFF
7
1.8 V/3.3 V VDDSHV1_WKU Yes
P
LVCMOS
PU/PD
1.8 V/3.3 V VDDSHV1_WKU Yes
P
LVCMOS
1.8 V/3.3 V VDDSHV1_WKU Yes
P
LVCMOS
1.8 V/3.3 V VDDSHV1_WKU Yes
P
LVCMOS
1.8 V/3.3 V VDDSHV1_WKU Yes
P
LVCMOS
1.8 V/3.3 V VDDSHV1_WKU Yes
P
LVCMOS
1.8 V/3.3 V VDDSHV1_WKU Yes
P
LVCMOS
0
0
0
0
0
OFF
7
PU/PD
0
0
0
OFF
7
PU/PD
0
0
0
OFF
7
PU/PD
0
0
0
OFF
7
PU/PD
0
0
0
OFF
7
PU/PD
0
0
0
OFF
7
PU/PD
0
0
0
Terminal Configuration and Functions
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DRA80M
SPRSP31E – APRIL 2018 – REVISED JUNE 2019
www.ti.com
Table 4-1. Pin Attributes (continued)
BALL NUMBER
[1]
R3
N2
N3
ADVANCE INFORMATION
P3
P4
P5
P1
BALL NAME [2]
MCU_OSPI0_D7
MCU_OSPI1_CSn0
MCU_OSPI1_CSn1
MCU_OSPI1_D0
MCU_OSPI1_D1
MCU_OSPI1_D2
MCU_OSPI1_D3
SIGNAL NAME [3]
TYPE [5]
MCU_OSPI0_D7
0
IO
MCU_HYPERBUS0_DQ7
1
IO
WKUP_GPIO0_22
7
IO
MCU_OSPI1_CSn0
0
O
WKUP_GPIO0_32
7
IO
MCU_OSPI1_CSn1
0
O
MCU_HYPERBUS0_WPn
1
O
MCU_TIMER_IO0
2
IO
MCU_HYPERBUS0_CSn1
3
O
MCU_UART0_RTSn
4
O
MCU_SPI0_CS2
5
IO
WKUP_GPIO0_33
7
IO
MCU_OSPI1_D0
0
IO
WKUP_GPIO0_28
7
IO
MCU_OSPI1_D1
0
IO
MCU_UART0_RXD
4
I
MCU_SPI1_CS1
5
IO
WKUP_GPIO0_29
7
IO
MCU_OSPI1_D2
0
IO
MCU_UART0_TXD
4
O
MCU_SPI1_CS2
5
IO
WKUP_GPIO0_30
7
IO
MCU_OSPI1_D3
0
IO
MCU_UART0_CTSn
4
I
MCU_SPI0_CS1
5
IO
WKUP_GPIO0_31
7
IO
W5
MCU_PORz
MCU_PORz
V2
MCU_PORz_OUT
MCU_PORz_OUT
V3
MCU_RESETSTATz
W4
M1
24
MUXMODE
[4]
BALL
BALL
RESET
I/O
RESET
REL.
VOLTAGE
STATE [6] MUXMODE VALUE [8]
[7]
OFF
7
POWER [9]
HYS [10]
BUFFER
TYPE [11]
1.8 V/3.3 V VDDSHV1_WKU Yes
P
LVCMOS
1.8 V/3.3 V VDDSHV1_WKU Yes
P
LVCMOS
1.8 V/3.3 V VDDSHV1_WKU Yes
P
LVCMOS
PULL
UP/DOWN
TYPE [12]
PU/PD
DSIS [13]
0
RXACTIVE/
IO Daisy
TXDISABL
Chain [15]
E [14]
0/1
Yes
0/1
Yes
0/1
Yes
0/1
Yes
0/1
Yes
0/1
Yes
0/1
Yes
0
0
OFF
OFF
7
7
PU/PD
0
PU/PD
0
1
0
OFF
OFF
7
7
1.8 V/3.3 V VDDSHV1_WKU Yes
P
LVCMOS
1.8 V/3.3 V VDDSHV1_WKU Yes
P
LVCMOS
PU/PD
0
0
PU/PD
0
1
1
0
OFF
7
1.8 V/3.3 V VDDSHV1_WKU Yes
P
LVCMOS
PU/PD
0
1
0
OFF
7
1.8 V/3.3 V VDDSHV1_WKU Yes
P
LVCMOS
PU/PD
0
1
1
0
I
OFF
1.8 V/3.3 V VDDSHV0_WKU Yes
P
LVCMOS
0
O
OFF
MCU_RESETSTATz
0
O
MCU_RESETz
MCU_RESETz
0
MCU_RGMII1_RXC
MCU_RGMII1_RXC
MCU_RMII1_REF_CLK
WKUP_GPIO0_41
0
1.8 V/3.3 V VDDSHV0_WKU Yes
P
LVCMOS
PU/PD
0/0
No
OFF
0
1.8 V/3.3 V VDDSHV0_WKU Yes
P
LVCMOS
PU/PD
0/0
No
I
PU
0
1.8 V/3.3 V VDDSHV0_WKU Yes
P
LVCMOS
PU/PD
1/1
No
0
I
OFF
7
PU/PD
0/1
Yes
I
1.8 V/3.3 V VDDSHV2_WKU Yes
P
LVCMOS
1
7
IO
Terminal Configuration and Functions
No
0
0
0
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SPRSP31E – APRIL 2018 – REVISED JUNE 2019
Table 4-1. Pin Attributes (continued)
N5
N1
N4
L6
M6
L5
L2
M5
M4
M3
M2
BALL NAME [2]
MCU_RGMII1_RX_CTL
MCU_RGMII1_TXC
MCU_RGMII1_TX_CTL
MCU_RGMII1_RD0
MCU_RGMII1_RD1
MCU_RGMII1_RD2
MCU_RGMII1_RD3
MCU_RGMII1_TD0
MCU_RGMII1_TD1
MCU_RGMII1_TD2
MCU_RGMII1_TD3
SIGNAL NAME [3]
MUXMODE
[4]
TYPE [5]
MCU_RGMII1_RX_CTL
0
I
MCU_RMII1_RX_ER
1
I
WKUP_GPIO0_35
7
IO
MCU_RGMII1_TXC
0
IO
MCU_RMII1_TX_EN
1
O
WKUP_GPIO0_40
7
IO
MCU_RGMII1_TX_CTL
0
O
MCU_RMII1_CRS_DV
1
I
WKUP_GPIO0_34
7
IO
MCU_RGMII1_RD0
0
I
MCU_RMII1_RXD0
1
I
WKUP_GPIO0_45
7
IO
MCU_RGMII1_RD1
0
I
MCU_RMII1_RXD1
1
I
WKUP_GPIO0_44
7
IO
MCU_RGMII1_RD2
0
I
WKUP_GPIO0_43
7
IO
MCU_RGMII1_RD3
0
I
WKUP_GPIO0_42
7
IO
MCU_RGMII1_TD0
0
O
MCU_RMII1_TXD0
1
O
WKUP_GPIO0_39
7
IO
MCU_RGMII1_TD1
0
O
MCU_RMII1_TXD1
1
O
WKUP_GPIO0_38
7
IO
MCU_RGMII1_TD2
0
O
WKUP_GPIO0_37
7
IO
MCU_RGMII1_TD3
0
O
WKUP_GPIO0_36
7
IO
BALL
BALL
RESET
I/O
RESET
REL.
VOLTAGE
STATE [6] MUXMODE VALUE [8]
[7]
OFF
7
POWER [9]
HYS [10]
BUFFER
TYPE [11]
1.8 V/3.3 V VDDSHV2_WKU Yes
P
LVCMOS
PULL
UP/DOWN
TYPE [12]
PU/PD
0/1
Yes
0/1
Yes
0/1
Yes
0/1
Yes
0/1
Yes
0/1
Yes
0/1
Yes
0/1
Yes
0/1
Yes
0/1
Yes
0/1
Yes
1/0
No
1/1
Yes
0/1
Yes
0
OFF
7
1.8 V/3.3 V VDDSHV2_WKU Yes
P
LVCMOS
PU/PD
OFF
7
1.8 V/3.3 V VDDSHV2_WKU Yes
P
LVCMOS
PU/PD
1.8 V/3.3 V VDDSHV2_WKU Yes
P
LVCMOS
1.8 V/3.3 V VDDSHV2_WKU Yes
P
LVCMOS
1.8 V/3.3 V VDDSHV2_WKU Yes
P
LVCMOS
1.8 V/3.3 V VDDSHV2_WKU Yes
P
LVCMOS
0
0
0
0
OFF
7
PU/PD
0
0
0
OFF
7
PU/PD
0
0
0
OFF
OFF
7
7
PU/PD
0
0
PU/PD
0
0
OFF
7
1.8 V/3.3 V VDDSHV2_WKU Yes
P
LVCMOS
PU/PD
OFF
7
1.8 V/3.3 V VDDSHV2_WKU Yes
P
LVCMOS
PU/PD
OFF
7
1.8 V/3.3 V VDDSHV2_WKU Yes
P
LVCMOS
PU/PD
1.8 V/3.3 V VDDSHV2_WKU Yes
P
LVCMOS
0
0
OFF
7
0
PU/PD
0
MCU_SAFETY_ERRORn
MCU_SAFETY_ERRORn
0
IO
PD
0
1.8 V/3.3 V VDDSHV0_WKU Yes
P
LVCMOS
PU/PD
Y1
MCU_SPI0_CLK
MCU_SPI0_CLK
0
IO
OFF
7
PU/PD
7
IO
1.8 V/3.3 V VDDSHV0_WKU Yes
P
LVCMOS
WKUP_GPIO0_48
MCU_BOOTMODE06
Bootstrap
I
MCU_SPI0_CS0
0
IO
LVCMOS
WKUP_GPIO0_51
7
IO
1.8 V/3.3 V VDDSHV0_WKU Yes
P
MCU_SPI0_CS0
0
RXACTIVE/
IO Daisy
TXDISABL
Chain [15]
E [14]
0
W3
Y4
DSIS [13]
ADVANCE INFORMATION
BALL NUMBER
[1]
0
0
0
OFF
7
PU/PD
1
0
Terminal Configuration and Functions
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DRA80M
SPRSP31E – APRIL 2018 – REVISED JUNE 2019
www.ti.com
Table 4-1. Pin Attributes (continued)
BALL NUMBER
[1]
Y3
Y2
BALL NAME [2]
MCU_SPI0_D0
MCU_SPI0_D1
SIGNAL NAME [3]
MUXMODE
[4]
TYPE [5]
MCU_SPI0_D0
0
IO
WKUP_GPIO0_49
7
IO
MCU_BOOTMODE07
Bootstrap
I
MCU_SPI0_D1
0
IO
WKUP_GPIO0_50
7
IO
MCU_BOOTMODE05
Bootstrap
I
ADVANCE INFORMATION
D24
MMC0_CALPAD
MMC0_CALPAD
B25
MMC0_CLK
MMC0_CLK
0
O
GPIO1_10
7
O
MMC0_CMD
0
IO
GPIO1_11
7
IO
MMC0_DS
0
I
GPIO1_12
7
I
MMC0_SDCD
0
I
PRG2_IEP0_EDIO_OUTVALID
6
O
GPIO1_13
7
IO
MMC0_SDWP
0
I
GPIO1_14
7
IO
B27
C25
A23
B23
MMC0_CMD
MMC0_DS
MMC0_SDCD
MMC0_SDWP
MMC1_CALPAD
MMC1_CALPAD
C27
MMC1_CLK
MMC1_CLK
0
O
GPIO1_77
7
O
MMC1_CMD
0
IO
GPIO1_78
7
IO
MMC1_SDCD
0
I
GPIO1_79
7
IO
MMC1_SDWP
0
I
GPIO1_80
7
IO
MMC0_DAT0
0
IO
GPIO1_9
7
IO
MMC0_DAT1
0
IO
GPIO1_8
7
IO
MMC0_DAT2
0
IO
GPIO1_7
7
IO
MMC0_DAT3
0
IO
GPIO1_6
7
IO
B24
C24
A26
E25
C26
A25
26
MMC1_CMD
MMC1_SDCD
MMC1_SDWP
MMC0_DAT0
MMC0_DAT1
MMC0_DAT2
MMC0_DAT3
OFF
7
POWER [9]
HYS [10]
BUFFER
TYPE [11]
PULL
UP/DOWN
TYPE [12]
PU/PD
DSIS [13]
1.8 V/3.3 V VDDSHV0_WKU Yes
P
LVCMOS
0
1.8 V/3.3 V VDDSHV0_WKU Yes
P
LVCMOS
1.8 V/3.3 V VDDSHV6
UHS-I (8bit
PHY)
1.8 V/3.3 V VDDSHV6
UHS-I (8bit PU/PD
PHY)
1
UHS-I (8bit PU/PD
PHY)
1
UHS-I (8bit PU/PD
PHY)
1
1
RXACTIVE/
IO Daisy
TXDISABL
Chain [15]
E [14]
1/1
Yes
1/1
Yes
0
0
OFF
7
PU/PD
0
0
0
A
F23
C28
BALL
BALL
RESET
I/O
RESET
REL.
VOLTAGE
STATE [6] MUXMODE VALUE [8]
[7]
PD
PU
PD
7
7
7
1.8 V/3.3 V VDDSHV6
1.8 V/3.3 V VDDSHV6
No
OFF
7
1.8 V
VDDS_OSC1
Yes
LVCMOS
PU/PD
OFF
7
1.8 V
VDDS_OSC1
Yes
LVCMOS
PU/PD
No
0
No
0
No
0
0/1
Yes
0/1
Yes
0
1
0
A
PD
PU
OFF
7
7
7
1.8 V/3.3 V VDDSHV7
UHS-I (4bit
PHY)
1.8 V/3.3 V VDDSHV7
UHS-I (4bit PU/PD
PHY)
1
UHS-I (4bit PU/PD
PHY)
1
LVCMOS
1
1.8 V/3.3 V VDDSHV7
1.8 V
VDDS_OSC1
Yes
No
PU/PD
No
0
No
0
0/1
Yes
0/1
Yes
0
OFF
7
1.8 V
VDDS_OSC1
Yes
LVCMOS
PU/PD
1
0
PU
PU
PU
PU
7
7
7
7
1.8 V/3.3 V VDDSHV6
1.8 V/3.3 V VDDSHV6
1.8 V/3.3 V VDDSHV6
1.8 V/3.3 V VDDSHV6
Terminal Configuration and Functions
UHS-I (8bit PU/PD
PHY)
1
UHS-I (8bit PU/PD
PHY)
1
UHS-I (8bit PU/PD
PHY)
1
UHS-I (8bit PU/PD
PHY)
1
No
0
No
0
No
0
No
0
Copyright © 2018–2019, Texas Instruments Incorporated
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SPRSP31E – APRIL 2018 – REVISED JUNE 2019
Table 4-1. Pin Attributes (continued)
E24
A24
B26
D25
D28
E27
D26
D27
F18
BALL NAME [2]
MMC0_DAT4
MMC0_DAT5
MMC0_DAT6
MMC0_DAT7
MMC1_DAT0
MMC1_DAT1
MMC1_DAT2
MMC1_DAT3
NMIn
SIGNAL NAME [3]
MUXMODE
[4]
TYPE [5]
MMC0_DAT4
0
IO
UART0_RIN
1
I
EQEP2_S
5
IO
GPIO1_5
7
IO
MMC0_DAT5
0
IO
UART0_DTRn
1
O
EQEP2_I
5
IO
GPIO1_4
7
IO
MMC0_DAT6
0
IO
UART0_DSRn
1
I
EQEP2_B
5
I
GPIO1_3
7
IO
MMC0_DAT7
0
IO
UART0_DCDn
1
I
EQEP2_A
5
I
GPIO1_2
7
IO
MMC1_DAT0
0
IO
GPIO1_76
7
IO
MMC1_DAT1
0
IO
GPIO1_75
7
IO
MMC1_DAT2
0
IO
GPIO1_74
7
IO
MMC1_DAT3
0
IO
GPIO1_73
7
IO
NMIn
0
I
PRG2_PWM1_TZ_IN
6
I
BALL
BALL
RESET
I/O
RESET
REL.
VOLTAGE
STATE [6] MUXMODE VALUE [8]
[7]
PU
7
POWER [9]
HYS [10]
1.8 V/3.3 V VDDSHV6
BUFFER
TYPE [11]
PULL
UP/DOWN
TYPE [12]
UHS-I (8bit PU/PD
PHY)
DSIS [13]
RXACTIVE/
IO Daisy
TXDISABL
Chain [15]
E [14]
1
No
1
0
0
PU
7
1.8 V/3.3 V VDDSHV6
UHS-I (8bit PU/PD
PHY)
1
No
0
ADVANCE INFORMATION
BALL NUMBER
[1]
0
PU
7
1.8 V/3.3 V VDDSHV6
UHS-I (8bit PU/PD
PHY)
1
No
1
0
0
PU
7
1.8 V/3.3 V VDDSHV6
UHS-I (8bit PU/PD
PHY)
1
No
1
0
0
PU
PU
PU
PU
PU
7
7
7
7
0
1.8 V/3.3 V VDDSHV7
1.8 V/3.3 V VDDSHV7
1.8 V/3.3 V VDDSHV7
1.8 V/3.3 V VDDSHV7
1.8 V/3.3 V VDDSHV0
Yes
UHS-I (4bit PU/PD
PHY)
1
UHS-I (4bit PU/PD
PHY)
1
UHS-I (4bit PU/PD
PHY)
1
UHS-I (4bit PU/PD
PHY)
1
LVCMOSFS
1
PU/PD
No
0
No
0
No
0
No
0
1/1
Yes
0
L25
OLDI0_CLKN
OLDI0_CLKN
IO
OFF
1.8 V
VDDA_1P8_OL
DI0
OLDI_LVD
S
No
K25
OLDI0_CLKP
OLDI0_CLKP
IO
OFF
1.8 V
VDDA_1P8_OL
DI0
OLDI_LVD
S
No
J28
OLDI0_A0N
OLDI0_A0N
IO
OFF
1.8 V
VDDA_1P8_OL
DI0
OLDI_LVD
S
No
K28
OLDI0_A0P
OLDI0_A0P
IO
OFF
1.8 V
VDDA_1P8_OL
DI0
OLDI_LVD
S
No
L27
OLDI0_A1N
OLDI0_A1N
IO
OFF
1.8 V
VDDA_1P8_OL
DI0
OLDI_LVD
S
No
K27
OLDI0_A1P
OLDI0_A1P
IO
OFF
1.8 V
VDDA_1P8_OL
DI0
OLDI_LVD
S
No
K24
OLDI0_A2N
OLDI0_A2N
IO
OFF
1.8 V
VDDA_1P8_OL
DI0
OLDI_LVD
S
No
Terminal Configuration and Functions
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Table 4-1. Pin Attributes (continued)
BALL NUMBER
[1]
BALL NAME [2]
SIGNAL NAME [3]
MUXMODE
[4]
TYPE [5]
BALL
BALL
RESET
I/O
RESET
REL.
VOLTAGE
STATE [6] MUXMODE VALUE [8]
[7]
POWER [9]
HYS [10]
BUFFER
TYPE [11]
PULL
UP/DOWN
TYPE [12]
DSIS [13]
RXACTIVE/
IO Daisy
TXDISABL
Chain [15]
E [14]
ADVANCE INFORMATION
J24
OLDI0_A2P
OLDI0_A2P
IO
OFF
1.8 V
VDDA_1P8_OL
DI0
OLDI_LVD
S
No
J26
OLDI0_A3N
OLDI0_A3N
IO
OFF
1.8 V
VDDA_1P8_OL
DI0
OLDI_LVD
S
No
K26
OLDI0_A3P
OLDI0_A3P
IO
OFF
1.8 V
VDDA_1P8_OL
DI0
OLDI_LVD
S
No
C22
OSC1_XI
OSC1_XI
I
OFF
1.8 V
VDDS_OSC1
Analog
No
E22
OSC1_XO
OSC1_XO
O
OFF
1.8 V
VDDS_OSC1
Analog
Y5
PMIC_POWER_EN0
PMIC_POWER_EN0
0
O
OFF
0
1.8 V/3.3 V VDDSHV0_WKU Yes
P
LVCMOS
PU/PD
0/0
No
AA5
PMIC_POWER_EN1
PMIC_POWER_EN1
0
O
OFF
0
1.8 V/3.3 V VDDSHV0_WKU Yes
P
LVCMOS
PU/PD
0/0
No
E19
PORz
PORz
0
I
OFF
0
1.8 V/3.3 V VDDSHV0
Yes
LVCMOS
C19
PORz_OUT
PORz_OUT
0
O
OFF
0
1.8 V/3.3 V VDDSHV0
Yes
LVCMOS
PU/PD
0/0
Yes
AE28
PRG0_MDIO0_MDC
PRG0_MDIO0_MDC
0
O
OFF
7
1.8 V/3.3 V VDDSHV3
Yes
LVCMOS
PU/PD
0/1
Yes
PRG2_PWM1_B2
3
IO
1
MCASP2_AXR3
5
IO
0
GPIO1_70
7
IO
PRG0_MDIO0_MDIO
0
IO
0/1
Yes
PRG2_PWM1_A2
3
IO
0
MCASP2_AXR2
5
IO
0
GPIO1_69
7
IO
PRG0_PRU0_GPO0
0
IO
0/1
Yes
PRG0_PRU0_GPI0
1
I
0
PRG0_RGMII1_RD0
2
I
0
PRG0_PWM3_A0
3
IO
0
MCASP0_ACLKX
5
IO
0
GPIO1_29
7
IO
PRG0_PRU0_GPO1
0
IO
0/1
Yes
PRG0_PRU0_GPI1
1
I
0
PRG0_RGMII1_RD1
2
I
0
PRG0_PWM3_B0
3
IO
1
MCASP0_AFSX
5
IO
0
GPIO1_30
7
IO
0
AE26
V24
W25
28
PRG0_MDIO0_MDIO
PRG0_PRU0_GPO0
PRG0_PRU0_GPO1
No
Yes
0
OFF
7
1.8 V/3.3 V VDDSHV3
Yes
LVCMOS
PU/PD
0
0
OFF
7
1.8 V/3.3 V VDDSHV3
Yes
LVCMOS
PU/PD
0
0
OFF
7
1.8 V/3.3 V VDDSHV3
Terminal Configuration and Functions
Yes
LVCMOS
PU/PD
0
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SPRSP31E – APRIL 2018 – REVISED JUNE 2019
Table 4-1. Pin Attributes (continued)
W24
AA27
Y24
V28
Y25
U27
BALL NAME [2]
PRG0_PRU0_GPO2
PRG0_PRU0_GPO3
PRG0_PRU0_GPO4
PRG0_PRU0_GPO5
PRG0_PRU0_GPO6
PRG0_PRU0_GPO7
SIGNAL NAME [3]
MUXMODE
[4]
TYPE [5]
BALL
BALL
RESET
I/O
RESET
REL.
VOLTAGE
STATE [6] MUXMODE VALUE [8]
[7]
OFF
7
POWER [9]
1.8 V/3.3 V VDDSHV3
HYS [10]
Yes
BUFFER
TYPE [11]
LVCMOS
PULL
UP/DOWN
TYPE [12]
PU/PD
DSIS [13]
PRG0_PRU0_GPO2
0
IO
PRG0_PRU0_GPI2
1
I
0
0
PRG0_RGMII1_RD2
2
I
0
PRG0_PWM2_A0
3
IO
0
MCASP0_ACLKR
5
IO
0
GPIO1_31
7
IO
PRG0_PRU0_GPO3
0
IO
PRG0_PRU0_GPI3
1
I
0
PRG0_RGMII1_RD3
2
I
0
PRG0_PWM3_A2
3
IO
0
MCASP0_AFSR
5
IO
0
GPIO1_32
7
IO
PRG0_PRU0_GPO4
0
IO
PRG0_PRU0_GPI4
1
I
0
PRG0_RGMII1_RX_CTL
2
I
0
PRG0_PWM2_B0
3
IO
1
MCASP0_AXR0
5
IO
0
GPIO1_33
7
IO
PRG0_PRU0_GPO5
0
IO
PRG0_PRU0_GPI5
1
I
0
PRG0_PWM3_B2
3
IO
1
MCASP0_AXR1
5
IO
0
GPIO1_34
7
IO
PRG0_PRU0_GPO6
0
IO
PRG0_PRU0_GPI6
1
I
0
PRG0_RGMII1_RXC
2
I
0
PRG0_PWM3_A1
3
IO
0
MCASP0_AXR2
5
IO
0
GPIO1_35
7
IO
PRG0_PRU0_GPO7
0
IO
PRG0_PRU0_GPI7
1
I
0
PRG0_IEP0_EDC_LATCH_IN1
2
I
0
PRG0_PWM3_B1
3
IO
1
PRG0_ECAP0_SYNC_IN
4
I
0
MCASP0_AXR3
5
IO
0
GPIO1_36
7
IO
0
RXACTIVE/
IO Daisy
TXDISABL
Chain [15]
E [14]
0/1
Yes
0/1
Yes
0/1
Yes
0/1
Yes
0/1
Yes
0/1
Yes
0
OFF
7
1.8 V/3.3 V VDDSHV3
Yes
LVCMOS
PU/PD
0
ADVANCE INFORMATION
BALL NUMBER
[1]
0
OFF
7
1.8 V/3.3 V VDDSHV3
Yes
LVCMOS
PU/PD
0
0
OFF
7
1.8 V/3.3 V VDDSHV3
Yes
LVCMOS
PU/PD
0
0
OFF
7
1.8 V/3.3 V VDDSHV3
Yes
LVCMOS
PU/PD
0
0
OFF
7
1.8 V/3.3 V VDDSHV3
Yes
LVCMOS
PU/PD
0
Terminal Configuration and Functions
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SPRSP31E – APRIL 2018 – REVISED JUNE 2019
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Table 4-1. Pin Attributes (continued)
BALL NUMBER
[1]
V27
V26
ADVANCE INFORMATION
U25
AB25
AD27
30
BALL NAME [2]
PRG0_PRU0_GPO8
PRG0_PRU0_GPO9
PRG0_PRU0_GPO10
PRG0_PRU0_GPO11
PRG0_PRU0_GPO12
SIGNAL NAME [3]
MUXMODE
[4]
TYPE [5]
BALL
BALL
RESET
I/O
RESET
REL.
VOLTAGE
STATE [6] MUXMODE VALUE [8]
[7]
OFF
7
POWER [9]
1.8 V/3.3 V VDDSHV3
HYS [10]
Yes
BUFFER
TYPE [11]
LVCMOS
PULL
UP/DOWN
TYPE [12]
PU/PD
DSIS [13]
PRG0_PRU0_GPO8
0
IO
PRG0_PRU0_GPI8
1
I
0
0
PRG0_PWM2_A1
3
IO
0
MCASP0_AXR4
5
IO
0
GPIO1_37
7
IO
PRG0_PRU0_GPO9
0
IO
PRG0_PRU0_GPI9
1
I
0
PRG0_UART0_CTSn
2
I
1
PRG0_PWM3_TZ_IN
3
I
0
SPI3_CS1
4
IO
1
MCASP0_AXR5
5
IO
0
PRG0_IEP0_EDIO_DATA_IN_OUT28
6
IO
0
GPIO1_38
7
IO
PRG0_PRU0_GPO10
0
IO
PRG0_PRU0_GPI10
1
I
PRG0_UART0_RTSn
2
O
PRG0_PWM2_B1
3
IO
1
SPI3_CS2
4
IO
1
MCASP0_AXR6
5
IO
0
PRG0_IEP0_EDIO_DATA_IN_OUT29
6
IO
0
GPIO1_39
7
IO
PRG0_PRU0_GPO11
0
IO
PRG0_PRU0_GPI11
1
I
PRG0_RGMII1_TX_CTL
2
O
PRG0_PWM3_TZ_OUT
3
O
MCASP0_AXR7
5
IO
GPIO1_40
7
IO
PRG0_PRU0_GPO12
0
IO
PRG0_PRU0_GPI12
1
I
PRG0_RGMII1_TD0
2
O
PRG0_PWM0_A0
3
IO
0
MCASP0_AXR8
5
IO
0
GPIO1_41
7
IO
0
RXACTIVE/
IO Daisy
TXDISABL
Chain [15]
E [14]
0/1
Yes
0/1
Yes
0/1
Yes
0/1
Yes
0/1
Yes
0
OFF
7
1.8 V/3.3 V VDDSHV3
Yes
LVCMOS
PU/PD
0
0
OFF
7
1.8 V/3.3 V VDDSHV3
Yes
LVCMOS
PU/PD
0
0
0
OFF
7
1.8 V/3.3 V VDDSHV3
Yes
LVCMOS
PU/PD
0
0
0
0
OFF
7
1.8 V/3.3 V VDDSHV3
Terminal Configuration and Functions
Yes
LVCMOS
PU/PD
0
0
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SPRSP31E – APRIL 2018 – REVISED JUNE 2019
Table 4-1. Pin Attributes (continued)
AC26
AD26
AA24
AD28
U26
BALL NAME [2]
PRG0_PRU0_GPO13
PRG0_PRU0_GPO14
PRG0_PRU0_GPO15
PRG0_PRU0_GPO16
PRG0_PRU0_GPO17
SIGNAL NAME [3]
MUXMODE
[4]
TYPE [5]
BALL
BALL
RESET
I/O
RESET
REL.
VOLTAGE
STATE [6] MUXMODE VALUE [8]
[7]
OFF
7
POWER [9]
1.8 V/3.3 V VDDSHV3
HYS [10]
Yes
BUFFER
TYPE [11]
LVCMOS
PULL
UP/DOWN
TYPE [12]
PU/PD
DSIS [13]
PRG0_PRU0_GPO13
0
IO
PRG0_PRU0_GPI13
1
I
0
PRG0_RGMII1_TD1
2
O
PRG0_PWM0_B0
3
IO
1
MCASP0_AXR9
5
IO
0
GPIO1_42
7
IO
PRG0_PRU0_GPO14
0
IO
PRG0_PRU0_GPI14
1
I
PRG0_RGMII1_TD2
2
O
PRG0_PWM0_A1
3
IO
0
MCASP0_AXR10
5
IO
0
GPIO1_43
7
IO
PRG0_PRU0_GPO15
0
IO
PRG0_PRU0_GPI15
1
I
PRG0_RGMII1_TD3
2
O
PRG0_PWM0_B1
3
IO
1
MCASP0_AXR11
5
IO
0
GPIO1_44
7
IO
PRG0_PRU0_GPO16
0
IO
PRG0_PRU0_GPI16
1
I
0
PRG0_RGMII1_TXC
2
IO
0
PRG0_PWM0_A2
3
IO
0
MCASP0_AXR12
5
IO
0
MCASP1_AHCLKR
6
IO
0
GPIO1_45
7
IO
PRG0_PRU0_GPO17
0
IO
PRG0_PRU0_GPI17
1
I
PRG0_IEP0_EDC_SYNC_OUT1
2
O
PRG0_PWM0_B2
3
IO
PRG0_ECAP0_SYNC_OUT
4
O
MCASP0_AXR13
5
IO
0
MCASP1_AHCLKX
6
IO
0
GPIO1_46
7
IO
0
RXACTIVE/
IO Daisy
TXDISABL
Chain [15]
E [14]
0/1
Yes
0/1
Yes
0/1
Yes
0/1
Yes
0/1
Yes
0
0
OFF
7
1.8 V/3.3 V VDDSHV3
Yes
LVCMOS
PU/PD
0
ADVANCE INFORMATION
BALL NUMBER
[1]
0
0
OFF
7
1.8 V/3.3 V VDDSHV3
Yes
LVCMOS
PU/PD
0
0
0
OFF
7
1.8 V/3.3 V VDDSHV3
Yes
LVCMOS
PU/PD
0
0
OFF
7
1.8 V/3.3 V VDDSHV3
Yes
LVCMOS
PU/PD
0
0
1
Terminal Configuration and Functions
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Table 4-1. Pin Attributes (continued)
BALL NUMBER
[1]
V25
ADVANCE INFORMATION
U24
AB28
AC28
AC27
AB26
32
BALL NAME [2]
PRG0_PRU0_GPO18
PRG0_PRU0_GPO19
PRG0_PRU1_GPO0
PRG0_PRU1_GPO1
PRG0_PRU1_GPO2
PRG0_PRU1_GPO3
SIGNAL NAME [3]
MUXMODE
[4]
TYPE [5]
BALL
BALL
RESET
I/O
RESET
REL.
VOLTAGE
STATE [6] MUXMODE VALUE [8]
[7]
OFF
7
POWER [9]
1.8 V/3.3 V VDDSHV3
HYS [10]
Yes
BUFFER
TYPE [11]
LVCMOS
PULL
UP/DOWN
TYPE [12]
PU/PD
DSIS [13]
PRG0_PRU0_GPO18
0
IO
PRG0_PRU0_GPI18
1
I
0
0
PRG0_IEP0_EDC_LATCH_IN0
2
I
0
PRG0_PWM0_TZ_IN
3
I
0
PRG0_ECAP0_IN_APWM_OUT
4
IO
0
MCASP0_AXR14
5
IO
0
MCASP2_AHCLKR
6
IO
0
GPIO1_47
7
IO
PRG0_PRU0_GPO19
0
IO
PRG0_PRU0_GPI19
1
I
PRG0_IEP0_EDC_SYNC_OUT0
2
O
PRG0_PWM0_TZ_OUT
3
O
MCASP0_AXR15
5
IO
0
MCASP2_AHCLKX
6
IO
0
GPIO1_48
7
IO
PRG0_PRU1_GPO0
0
IO
PRG0_PRU1_GPI0
1
I
0
PRG0_RGMII2_RD0
2
I
0
MCASP1_ACLKX
5
IO
0
GPIO1_49
7
IO
PRG0_PRU1_GPO1
0
IO
PRG0_PRU1_GPI1
1
I
0
PRG0_RGMII2_RD1
2
I
0
MCASP1_AFSX
5
IO
0
GPIO1_50
7
IO
PRG0_PRU1_GPO2
0
IO
PRG0_PRU1_GPI2
1
I
0
PRG0_RGMII2_RD2
2
I
0
PRG0_PWM2_A2
3
IO
0
MCASP1_ACLKR
5
IO
0
GPIO1_51
7
IO
PRG0_PRU1_GPO3
0
IO
PRG0_PRU1_GPI3
1
I
0
PRG0_RGMII2_RD3
2
I
0
EQEP0_A
4
I
0
MCASP1_AFSR
5
IO
0
GPIO1_52
7
IO
0
RXACTIVE/
IO Daisy
TXDISABL
Chain [15]
E [14]
0/1
Yes
0/1
Yes
0/1
Yes
0/1
Yes
0/1
Yes
0/1
Yes
0
OFF
7
1.8 V/3.3 V VDDSHV3
Yes
LVCMOS
PU/PD
0
0
0
OFF
7
1.8 V/3.3 V VDDSHV3
Yes
LVCMOS
PU/PD
0
0
OFF
7
1.8 V/3.3 V VDDSHV3
Yes
LVCMOS
PU/PD
0
0
OFF
7
1.8 V/3.3 V VDDSHV3
Yes
LVCMOS
PU/PD
0
0
OFF
7
1.8 V/3.3 V VDDSHV3
Terminal Configuration and Functions
Yes
LVCMOS
PU/PD
0
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SPRSP31E – APRIL 2018 – REVISED JUNE 2019
Table 4-1. Pin Attributes (continued)
AA25
U23
AB27
W28
W27
BALL NAME [2]
PRG0_PRU1_GPO4
PRG0_PRU1_GPO5
PRG0_PRU1_GPO6
PRG0_PRU1_GPO7
PRG0_PRU1_GPO8
SIGNAL NAME [3]
MUXMODE
[4]
TYPE [5]
BALL
BALL
RESET
I/O
RESET
REL.
VOLTAGE
STATE [6] MUXMODE VALUE [8]
[7]
OFF
7
POWER [9]
1.8 V/3.3 V VDDSHV3
HYS [10]
Yes
BUFFER
TYPE [11]
LVCMOS
PULL
UP/DOWN
TYPE [12]
PU/PD
DSIS [13]
PRG0_PRU1_GPO4
0
IO
PRG0_PRU1_GPI4
1
I
0
0
PRG0_RGMII2_RX_CTL
2
I
0
PRG0_PWM2_B2
3
IO
1
EQEP0_B
4
I
0
MCASP1_AXR0
5
IO
0
MCASP0_AHCLKR
6
IO
0
GPIO1_53
7
IO
PRG0_PRU1_GPO5
0
IO
PRG0_PRU1_GPI5
1
I
0
EQEP0_S
4
IO
0
MCASP1_AXR1
5
IO
0
MCASP0_AHCLKX
6
IO
0
GPIO1_54
7
IO
PRG0_PRU1_GPO6
0
IO
PRG0_PRU1_GPI6
1
I
0
PRG0_RGMII2_RXC
2
I
0
MCASP1_AXR2
5
IO
0
GPIO1_55
7
IO
PRG0_PRU1_GPO7
0
IO
PRG0_PRU1_GPI7
1
I
0
PRG0_IEP1_EDC_LATCH_IN1
2
I
0
SPI3_CS0
4
IO
1
MCASP1_AXR3
5
IO
0
UART2_TXD
6
O
GPIO1_56
7
IO
PRG0_PRU1_GPO8
0
IO
PRG0_PRU1_GPI8
1
I
PRG0_PWM2_TZ_OUT
3
O
MCASP1_AXR4
5
IO
0
GPIO1_57
7
IO
0
RXACTIVE/
IO Daisy
TXDISABL
Chain [15]
E [14]
0/1
Yes
0/1
Yes
0/1
Yes
0/1
Yes
0/1
Yes
ADVANCE INFORMATION
BALL NUMBER
[1]
0
OFF
7
1.8 V/3.3 V VDDSHV3
Yes
LVCMOS
PU/PD
0
0
OFF
7
1.8 V/3.3 V VDDSHV3
Yes
LVCMOS
PU/PD
0
0
OFF
7
1.8 V/3.3 V VDDSHV3
Yes
LVCMOS
PU/PD
0
0
OFF
7
1.8 V/3.3 V VDDSHV3
Yes
LVCMOS
PU/PD
0
0
Terminal Configuration and Functions
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Table 4-1. Pin Attributes (continued)
BALL NUMBER
[1]
Y28
ADVANCE INFORMATION
AA28
AB24
AC25
AD25
34
BALL NAME [2]
PRG0_PRU1_GPO9
PRG0_PRU1_GPO10
PRG0_PRU1_GPO11
PRG0_PRU1_GPO12
PRG0_PRU1_GPO13
SIGNAL NAME [3]
MUXMODE
[4]
TYPE [5]
BALL
BALL
RESET
I/O
RESET
REL.
VOLTAGE
STATE [6] MUXMODE VALUE [8]
[7]
OFF
7
POWER [9]
1.8 V/3.3 V VDDSHV3
HYS [10]
Yes
BUFFER
TYPE [11]
LVCMOS
PULL
UP/DOWN
TYPE [12]
PU/PD
DSIS [13]
PRG0_PRU1_GPO9
0
IO
PRG0_PRU1_GPI9
1
I
0
0
PRG0_UART0_RXD
2
I
1
SPI3_CS3
4
IO
1
MCASP1_AXR5
5
IO
0
PRG0_IEP0_EDIO_DATA_IN_OUT30
6
IO
0
GPIO1_58
7
IO
PRG0_PRU1_GPO10
0
IO
PRG0_PRU1_GPI10
1
I
PRG0_UART0_TXD
2
O
PRG0_PWM2_TZ_IN
3
I
0
EQEP0_I
4
IO
0
MCASP1_AXR6
5
IO
0
PRG0_IEP0_EDIO_DATA_IN_OUT31
6
IO
0
GPIO1_59
7
IO
PRG0_PRU1_GPO11
0
IO
PRG0_PRU1_GPI11
1
I
PRG0_RGMII2_TX_CTL
2
O
MCASP1_AXR7
5
IO
GPIO1_60
7
IO
PRG0_PRU1_GPO12
0
IO
PRG0_PRU1_GPI12
1
I
PRG0_RGMII2_TD0
2
O
PRG0_PWM1_A0
3
IO
0
MCASP1_AXR8
5
IO
0
GPIO1_61
7
IO
PRG0_PRU1_GPO13
0
IO
PRG0_PRU1_GPI13
1
I
PRG0_RGMII2_TD1
2
O
PRG0_PWM1_B0
3
IO
1
MCASP1_AXR9
5
IO
0
GPIO1_62
7
IO
0
RXACTIVE/
IO Daisy
TXDISABL
Chain [15]
E [14]
0/1
Yes
0/1
Yes
0/1
Yes
0/1
Yes
0/1
Yes
0
OFF
7
1.8 V/3.3 V VDDSHV3
Yes
LVCMOS
PU/PD
0
0
0
OFF
7
1.8 V/3.3 V VDDSHV3
Yes
LVCMOS
PU/PD
0
0
0
0
OFF
7
1.8 V/3.3 V VDDSHV3
Yes
LVCMOS
PU/PD
0
0
0
OFF
7
1.8 V/3.3 V VDDSHV3
Terminal Configuration and Functions
Yes
LVCMOS
PU/PD
0
0
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SPRSP31E – APRIL 2018 – REVISED JUNE 2019
Table 4-1. Pin Attributes (continued)
AD24
AE27
AC24
Y27
Y26
BALL NAME [2]
PRG0_PRU1_GPO14
PRG0_PRU1_GPO15
PRG0_PRU1_GPO16
PRG0_PRU1_GPO17
PRG0_PRU1_GPO18
SIGNAL NAME [3]
MUXMODE
[4]
TYPE [5]
BALL
BALL
RESET
I/O
RESET
REL.
VOLTAGE
STATE [6] MUXMODE VALUE [8]
[7]
OFF
7
POWER [9]
1.8 V/3.3 V VDDSHV3
HYS [10]
Yes
BUFFER
TYPE [11]
LVCMOS
PULL
UP/DOWN
TYPE [12]
PU/PD
DSIS [13]
PRG0_PRU1_GPO14
0
IO
PRG0_PRU1_GPI14
1
I
0
PRG0_RGMII2_TD2
2
O
PRG0_PWM1_A1
3
IO
0
MCASP2_AFSR
5
IO
0
GPIO1_63
7
IO
PRG0_PRU1_GPO15
0
IO
PRG0_PRU1_GPI15
1
I
PRG0_RGMII2_TD3
2
O
PRG0_PWM1_B1
3
IO
1
MCASP2_ACLKR
5
IO
0
GPIO1_64
7
IO
PRG0_PRU1_GPO16
0
IO
PRG0_PRU1_GPI16
1
I
0
PRG0_RGMII2_TXC
2
IO
0
PRG0_PWM1_A2
3
IO
0
MCASP2_AXR0
5
IO
0
GPIO1_65
7
IO
PRG0_PRU1_GPO17
0
IO
PRG0_PRU1_GPI17
1
I
PRG0_IEP1_EDC_SYNC_OUT1
2
O
PRG0_PWM1_B2
3
IO
1
SPI3_CLK
4
IO
0
MCASP2_AXR1
5
IO
0
UART2_RXD
6
I
1
GPIO1_66
7
IO
PRG0_PRU1_GPO18
0
IO
PRG0_PRU1_GPI18
1
I
0
PRG0_IEP1_EDC_LATCH_IN0
2
I
0
PRG0_PWM1_TZ_IN
3
I
0
SPI3_D0
4
IO
0
MCASP2_AFSX
5
IO
0
UART2_CTSn
6
I
1
GPIO1_67
7
IO
0
RXACTIVE/
IO Daisy
TXDISABL
Chain [15]
E [14]
0/1
Yes
0/1
Yes
0/1
Yes
0/1
Yes
0/1
Yes
0
0
OFF
7
1.8 V/3.3 V VDDSHV3
Yes
LVCMOS
PU/PD
0
ADVANCE INFORMATION
BALL NUMBER
[1]
0
0
OFF
7
1.8 V/3.3 V VDDSHV3
Yes
LVCMOS
PU/PD
0
0
OFF
7
1.8 V/3.3 V VDDSHV3
Yes
LVCMOS
PU/PD
0
0
0
OFF
7
1.8 V/3.3 V VDDSHV3
Yes
LVCMOS
PU/PD
0
Terminal Configuration and Functions
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Table 4-1. Pin Attributes (continued)
BALL NUMBER
[1]
W26
ADVANCE INFORMATION
AH18
AD18
AE22
AG24
AF23
AD21
36
BALL NAME [2]
PRG0_PRU1_GPO19
PRG1_MDIO0_MDC
PRG1_MDIO0_MDIO
PRG1_PRU0_GPO0
PRG1_PRU0_GPO1
PRG1_PRU0_GPO2
PRG1_PRU0_GPO3
SIGNAL NAME [3]
MUXMODE
[4]
TYPE [5]
BALL
BALL
RESET
I/O
RESET
REL.
VOLTAGE
STATE [6] MUXMODE VALUE [8]
[7]
OFF
7
POWER [9]
1.8 V/3.3 V VDDSHV3
HYS [10]
Yes
BUFFER
TYPE [11]
LVCMOS
PULL
UP/DOWN
TYPE [12]
PU/PD
DSIS [13]
PRG0_PRU1_GPO19
0
IO
PRG0_PRU1_GPI19
1
I
0
PRG0_IEP1_EDC_SYNC_OUT0
2
O
PRG0_PWM1_TZ_OUT
3
O
SPI3_D1
4
IO
0
MCASP2_ACLKX
5
IO
0
UART2_RTSn
6
O
GPIO1_68
7
IO
PRG1_MDIO0_MDC
0
O
SPI1_CS3
1
IO
1
PRG2_PWM1_B1
3
IO
1
GPIO1_1
7
IO
PRG1_MDIO0_MDIO
0
IO
SPI1_CS2
1
IO
1
PRG2_PWM1_A1
3
IO
0
GPIO1_0
7
IO
PRG1_PRU0_GPO0
0
IO
PRG1_PRU0_GPI0
1
I
0
PRG1_RGMII1_RD0
2
I
0
PRG1_PWM3_A0
3
IO
0
GPIO0_56
7
IO
PRG1_PRU0_GPO1
0
IO
PRG1_PRU0_GPI1
1
I
0
PRG1_RGMII1_RD1
2
I
0
PRG1_PWM3_B0
3
IO
1
GPIO0_57
7
IO
PRG1_PRU0_GPO2
0
IO
PRG1_PRU0_GPI2
1
I
0
PRG1_RGMII1_RD2
2
I
0
PRG1_PWM2_A0
3
IO
0
GPIO0_58
7
IO
PRG1_PRU0_GPO3
0
IO
PRG1_PRU0_GPI3
1
I
0
PRG1_RGMII1_RD3
2
I
0
PRG1_PWM3_A2
3
IO
0
GPIO0_59
7
IO
0
RXACTIVE/
IO Daisy
TXDISABL
Chain [15]
E [14]
0/1
Yes
0/1
Yes
0/1
Yes
0/1
Yes
0/1
Yes
0/1
Yes
0/1
Yes
0
0
OFF
7
1.8 V/3.3 V VDDSHV4
Yes
LVCMOS
PU/PD
0
OFF
7
1.8 V/3.3 V VDDSHV4
Yes
LVCMOS
PU/PD
0
0
OFF
7
1.8 V/3.3 V VDDSHV4
Yes
LVCMOS
PU/PD
0
0
OFF
7
1.8 V/3.3 V VDDSHV4
Yes
LVCMOS
PU/PD
0
0
OFF
7
1.8 V/3.3 V VDDSHV4
Yes
LVCMOS
PU/PD
0
0
OFF
7
1.8 V/3.3 V VDDSHV4
Terminal Configuration and Functions
Yes
LVCMOS
PU/PD
0
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SPRSP31E – APRIL 2018 – REVISED JUNE 2019
Table 4-1. Pin Attributes (continued)
AG23
AF27
AF22
AG27
AF28
AF26
AH25
BALL NAME [2]
PRG1_PRU0_GPO4
PRG1_PRU0_GPO5
PRG1_PRU0_GPO6
PRG1_PRU0_GPO7
PRG1_PRU0_GPO8
PRG1_PRU0_GPO9
PRG1_PRU0_GPO10
SIGNAL NAME [3]
MUXMODE
[4]
TYPE [5]
BALL
BALL
RESET
I/O
RESET
REL.
VOLTAGE
STATE [6] MUXMODE VALUE [8]
[7]
OFF
7
POWER [9]
1.8 V/3.3 V VDDSHV4
HYS [10]
Yes
BUFFER
TYPE [11]
LVCMOS
PULL
UP/DOWN
TYPE [12]
PU/PD
DSIS [13]
PRG1_PRU0_GPO4
0
IO
PRG1_PRU0_GPI4
1
I
0
0
PRG1_RGMII1_RX_CTL
2
I
0
PRG1_PWM2_B0
3
IO
1
GPIO0_60
7
IO
PRG1_PRU0_GPO5
0
IO
PRG1_PRU0_GPI5
1
I
0
PRG1_PWM3_B2
3
IO
1
GPIO0_61
7
IO
PRG1_PRU0_GPO6
0
IO
PRG1_PRU0_GPI6
1
I
0
PRG1_RGMII1_RXC
2
I
0
PRG1_PWM3_A1
3
IO
0
GPIO0_62
7
IO
PRG1_PRU0_GPO7
0
IO
PRG1_PRU0_GPI7
1
I
0
PRG1_IEP0_EDC_LATCH_IN1
2
I
0
PRG1_PWM3_B1
3
IO
1
GPIO0_63
7
IO
PRG1_PRU0_GPO8
0
IO
PRG1_PRU0_GPI8
1
I
0
PRG1_PWM2_A1
3
IO
0
GPIO0_64
7
IO
PRG1_PRU0_GPO9
0
IO
PRG1_PRU0_GPI9
1
I
0
PRG1_UART0_CTSn
2
I
1
PRG1_PWM3_TZ_IN
3
I
0
SPI2_CS1
4
IO
1
PRG1_IEP0_EDIO_DATA_IN_OUT28
6
IO
0
GPIO0_65
7
IO
PRG1_PRU0_GPO10
0
IO
PRG1_PRU0_GPI10
1
I
PRG1_UART0_RTSn
2
O
PRG1_PWM2_B1
3
IO
1
SPI2_CS2
4
IO
1
PRG1_IEP0_EDIO_DATA_IN_OUT29
6
IO
0
GPIO0_66
7
IO
0
RXACTIVE/
IO Daisy
TXDISABL
Chain [15]
E [14]
0/1
Yes
0/1
Yes
0/1
Yes
0/1
Yes
0/1
Yes
0/1
Yes
0/1
Yes
0
OFF
7
1.8 V/3.3 V VDDSHV4
Yes
LVCMOS
PU/PD
0
ADVANCE INFORMATION
BALL NUMBER
[1]
0
OFF
7
1.8 V/3.3 V VDDSHV4
Yes
LVCMOS
PU/PD
0
0
OFF
7
1.8 V/3.3 V VDDSHV4
Yes
LVCMOS
PU/PD
0
0
OFF
7
1.8 V/3.3 V VDDSHV4
Yes
LVCMOS
PU/PD
0
0
OFF
7
1.8 V/3.3 V VDDSHV4
Yes
LVCMOS
PU/PD
0
0
OFF
7
1.8 V/3.3 V VDDSHV4
Yes
LVCMOS
PU/PD
0
0
Terminal Configuration and Functions
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Table 4-1. Pin Attributes (continued)
BALL NUMBER
[1]
AF21
AH20
ADVANCE INFORMATION
AH21
AG20
AD19
AD20
AH26
38
BALL NAME [2]
PRG1_PRU0_GPO11
PRG1_PRU0_GPO12
PRG1_PRU0_GPO13
PRG1_PRU0_GPO14
PRG1_PRU0_GPO15
PRG1_PRU0_GPO16
PRG1_PRU0_GPO17
SIGNAL NAME [3]
MUXMODE
[4]
TYPE [5]
BALL
BALL
RESET
I/O
RESET
REL.
VOLTAGE
STATE [6] MUXMODE VALUE [8]
[7]
OFF
7
POWER [9]
1.8 V/3.3 V VDDSHV4
HYS [10]
Yes
BUFFER
TYPE [11]
LVCMOS
PULL
UP/DOWN
TYPE [12]
PU/PD
DSIS [13]
PRG1_PRU0_GPO11
0
IO
PRG1_PRU0_GPI11
1
I
0
PRG1_RGMII1_TX_CTL
2
O
PRG1_PWM3_TZ_OUT
3
O
GPIO0_67
7
IO
PRG1_PRU0_GPO12
0
IO
PRG1_PRU0_GPI12
1
I
PRG1_RGMII1_TD0
2
O
PRG1_PWM0_A0
3
IO
GPIO0_68
7
IO
PRG1_PRU0_GPO13
0
IO
PRG1_PRU0_GPI13
1
I
PRG1_RGMII1_TD1
2
O
PRG1_PWM0_B0
3
IO
GPIO0_69
7
IO
PRG1_PRU0_GPO14
0
IO
PRG1_PRU0_GPI14
1
I
PRG1_RGMII1_TD2
2
O
PRG1_PWM0_A1
3
IO
GPIO0_70
7
IO
PRG1_PRU0_GPO15
0
IO
PRG1_PRU0_GPI15
1
I
PRG1_RGMII1_TD3
2
O
PRG1_PWM0_B1
3
IO
GPIO0_71
7
IO
PRG1_PRU0_GPO16
0
IO
PRG1_PRU0_GPI16
1
I
0
PRG1_RGMII1_TXC
2
IO
0
PRG1_PWM0_A2
3
IO
0
GPIO0_72
7
IO
PRG1_PRU0_GPO17
0
IO
PRG1_PRU0_GPI17
1
I
PRG1_IEP0_EDC_SYNC_OUT1
2
O
PRG1_PWM0_B2
3
IO
1
GPIO0_73
7
IO
0
RXACTIVE/
IO Daisy
TXDISABL
Chain [15]
E [14]
0/1
Yes
0/1
Yes
0/1
Yes
0/1
Yes
0/1
Yes
0/1
Yes
0/1
Yes
0
0
OFF
7
1.8 V/3.3 V VDDSHV4
Yes
LVCMOS
PU/PD
0
0
0
0
OFF
7
1.8 V/3.3 V VDDSHV4
Yes
LVCMOS
PU/PD
0
0
1
0
OFF
7
1.8 V/3.3 V VDDSHV4
Yes
LVCMOS
PU/PD
0
0
0
0
OFF
7
1.8 V/3.3 V VDDSHV4
Yes
LVCMOS
PU/PD
0
0
1
0
OFF
7
1.8 V/3.3 V VDDSHV4
Yes
LVCMOS
PU/PD
0
0
OFF
7
1.8 V/3.3 V VDDSHV4
Terminal Configuration and Functions
Yes
LVCMOS
PU/PD
0
0
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SPRSP31E – APRIL 2018 – REVISED JUNE 2019
Table 4-1. Pin Attributes (continued)
AG25
AG26
AH24
AH23
AG21
AH22
AE21
BALL NAME [2]
PRG1_PRU0_GPO18
PRG1_PRU0_GPO19
PRG1_PRU1_GPO0
PRG1_PRU1_GPO1
PRG1_PRU1_GPO2
PRG1_PRU1_GPO3
PRG1_PRU1_GPO4
SIGNAL NAME [3]
MUXMODE
[4]
TYPE [5]
BALL
BALL
RESET
I/O
RESET
REL.
VOLTAGE
STATE [6] MUXMODE VALUE [8]
[7]
OFF
7
POWER [9]
1.8 V/3.3 V VDDSHV4
HYS [10]
Yes
BUFFER
TYPE [11]
LVCMOS
PULL
UP/DOWN
TYPE [12]
PU/PD
DSIS [13]
PRG1_PRU0_GPO18
0
IO
PRG1_PRU0_GPI18
1
I
0
0
PRG1_IEP0_EDC_LATCH_IN0
2
I
0
PRG1_PWM0_TZ_IN
3
I
0
GPIO0_74
7
IO
PRG1_PRU0_GPO19
0
IO
PRG1_PRU0_GPI19
1
I
PRG1_IEP0_EDC_SYNC_OUT0
2
O
PRG1_PWM0_TZ_OUT
3
O
GPIO0_75
7
IO
PRG1_PRU1_GPO0
0
IO
PRG1_PRU1_GPI0
1
I
0
PRG1_RGMII2_RD0
2
I
0
GPIO0_76
7
IO
PRG1_PRU1_GPO1
0
IO
PRG1_PRU1_GPI1
1
I
0
PRG1_RGMII2_RD1
2
I
0
GPIO0_77
7
IO
PRG1_PRU1_GPO2
0
IO
PRG1_PRU1_GPI2
1
I
0
PRG1_RGMII2_RD2
2
I
0
PRG1_PWM2_A2
3
IO
0
GPIO0_78
7
IO
PRG1_PRU1_GPO3
0
IO
PRG1_PRU1_GPI3
1
I
0
PRG1_RGMII2_RD3
2
I
0
EQEP1_A
4
I
0
GPIO0_79
7
IO
PRG1_PRU1_GPO4
0
IO
PRG1_PRU1_GPI4
1
I
0
PRG1_RGMII2_RX_CTL
2
I
0
PRG1_PWM2_B2
3
IO
1
EQEP1_B
4
I
0
GPIO0_80
7
IO
0
RXACTIVE/
IO Daisy
TXDISABL
Chain [15]
E [14]
0/1
Yes
0/1
Yes
0/1
Yes
0/1
Yes
0/1
Yes
0/1
Yes
0/1
Yes
0
OFF
7
1.8 V/3.3 V VDDSHV4
Yes
LVCMOS
PU/PD
0
0
ADVANCE INFORMATION
BALL NUMBER
[1]
0
OFF
7
1.8 V/3.3 V VDDSHV4
Yes
LVCMOS
PU/PD
0
0
OFF
7
1.8 V/3.3 V VDDSHV4
Yes
LVCMOS
PU/PD
0
0
OFF
7
1.8 V/3.3 V VDDSHV4
Yes
LVCMOS
PU/PD
0
0
OFF
7
1.8 V/3.3 V VDDSHV4
Yes
LVCMOS
PU/PD
0
0
OFF
7
1.8 V/3.3 V VDDSHV4
Yes
LVCMOS
PU/PD
0
Terminal Configuration and Functions
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Table 4-1. Pin Attributes (continued)
BALL NUMBER
[1]
AC22
AG22
ADVANCE INFORMATION
AD23
AE24
AF25
AF24
AC20
40
BALL NAME [2]
PRG1_PRU1_GPO5
PRG1_PRU1_GPO6
PRG1_PRU1_GPO7
PRG1_PRU1_GPO8
PRG1_PRU1_GPO9
PRG1_PRU1_GPO10
PRG1_PRU1_GPO11
SIGNAL NAME [3]
MUXMODE
[4]
TYPE [5]
BALL
BALL
RESET
I/O
RESET
REL.
VOLTAGE
STATE [6] MUXMODE VALUE [8]
[7]
OFF
7
POWER [9]
1.8 V/3.3 V VDDSHV4
HYS [10]
Yes
BUFFER
TYPE [11]
LVCMOS
PULL
UP/DOWN
TYPE [12]
PU/PD
DSIS [13]
PRG1_PRU1_GPO5
0
IO
PRG1_PRU1_GPI5
1
I
0
0
EQEP1_S
4
IO
0
GPIO0_81
7
IO
PRG1_PRU1_GPO6
0
IO
PRG1_PRU1_GPI6
1
I
0
PRG1_RGMII2_RXC
2
I
0
GPIO0_82
7
IO
PRG1_PRU1_GPO7
0
IO
PRG1_PRU1_GPI7
1
I
0
PRG1_IEP1_EDC_LATCH_IN1
2
I
0
SPI2_CS0
4
IO
1
UART1_TXD
6
O
GPIO0_83
7
IO
PRG1_PRU1_GPO8
0
IO
PRG1_PRU1_GPI8
1
I
PRG1_PWM2_TZ_OUT
3
O
GPIO0_84
7
IO
PRG1_PRU1_GPO9
0
IO
PRG1_PRU1_GPI9
1
I
0
PRG1_UART0_RXD
2
I
1
PRG1_IEP0_EDIO_DATA_IN_OUT30
6
IO
0
GPIO0_85
7
IO
PRG1_PRU1_GPO10
0
IO
PRG1_PRU1_GPI10
1
I
PRG1_UART0_TXD
2
O
PRG1_PWM2_TZ_IN
3
I
0
SPI2_CS3
4
IO
1
PRG1_IEP0_EDIO_DATA_IN_OUT31
6
IO
0
GPIO0_86
7
IO
PRG1_PRU1_GPO11
0
IO
PRG1_PRU1_GPI11
1
I
PRG1_RGMII2_TX_CTL
2
O
EQEP1_I
4
IO
0
GPIO0_87
7
IO
0
RXACTIVE/
IO Daisy
TXDISABL
Chain [15]
E [14]
0/1
Yes
0/1
Yes
0/1
Yes
0/1
Yes
0/1
Yes
0/1
Yes
0/1
Yes
0
OFF
7
1.8 V/3.3 V VDDSHV4
Yes
LVCMOS
PU/PD
0
0
OFF
7
1.8 V/3.3 V VDDSHV4
Yes
LVCMOS
PU/PD
0
0
OFF
7
1.8 V/3.3 V VDDSHV4
Yes
LVCMOS
PU/PD
0
0
0
OFF
7
1.8 V/3.3 V VDDSHV4
Yes
LVCMOS
PU/PD
0
0
OFF
7
1.8 V/3.3 V VDDSHV4
Yes
LVCMOS
PU/PD
0
0
0
OFF
7
1.8 V/3.3 V VDDSHV4
Terminal Configuration and Functions
Yes
LVCMOS
PU/PD
0
0
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SPRSP31E – APRIL 2018 – REVISED JUNE 2019
Table 4-1. Pin Attributes (continued)
AE20
AF19
AH19
AG19
AE19
AE23
BALL NAME [2]
PRG1_PRU1_GPO12
PRG1_PRU1_GPO13
PRG1_PRU1_GPO14
PRG1_PRU1_GPO15
PRG1_PRU1_GPO16
PRG1_PRU1_GPO17
SIGNAL NAME [3]
MUXMODE
[4]
TYPE [5]
BALL
BALL
RESET
I/O
RESET
REL.
VOLTAGE
STATE [6] MUXMODE VALUE [8]
[7]
OFF
7
POWER [9]
1.8 V/3.3 V VDDSHV4
HYS [10]
Yes
BUFFER
TYPE [11]
LVCMOS
PULL
UP/DOWN
TYPE [12]
PU/PD
DSIS [13]
PRG1_PRU1_GPO12
0
IO
PRG1_PRU1_GPI12
1
I
0
PRG1_RGMII2_TD0
2
O
PRG1_PWM1_A0
3
IO
GPIO0_88
7
IO
PRG1_PRU1_GPO13
0
IO
PRG1_PRU1_GPI13
1
I
PRG1_RGMII2_TD1
2
O
PRG1_PWM1_B0
3
IO
GPIO0_89
7
IO
PRG1_PRU1_GPO14
0
IO
PRG1_PRU1_GPI14
1
I
PRG1_RGMII2_TD2
2
O
PRG1_PWM1_A1
3
IO
GPIO0_90
7
IO
PRG1_PRU1_GPO15
0
IO
PRG1_PRU1_GPI15
1
I
PRG1_RGMII2_TD3
2
O
PRG1_PWM1_B1
3
IO
GPIO0_91
7
IO
PRG1_PRU1_GPO16
0
IO
PRG1_PRU1_GPI16
1
I
0
PRG1_RGMII2_TXC
2
IO
0
PRG1_PWM1_A2
3
IO
0
GPIO0_92
7
IO
PRG1_PRU1_GPO17
0
IO
PRG1_PRU1_GPI17
1
I
PRG1_IEP1_EDC_SYNC_OUT1
2
O
PRG1_PWM1_B2
3
IO
1
SPI2_CLK
4
IO
0
PRG1_ECAP0_SYNC_OUT
5
O
UART1_RXD
6
I
1
GPIO0_93
7
IO
0
RXACTIVE/
IO Daisy
TXDISABL
Chain [15]
E [14]
0/1
Yes
0/1
Yes
0/1
Yes
0/1
Yes
0/1
Yes
0/1
Yes
0
0
0
OFF
7
1.8 V/3.3 V VDDSHV4
Yes
LVCMOS
PU/PD
0
0
ADVANCE INFORMATION
BALL NUMBER
[1]
1
0
OFF
7
1.8 V/3.3 V VDDSHV4
Yes
LVCMOS
PU/PD
0
0
0
0
OFF
7
1.8 V/3.3 V VDDSHV4
Yes
LVCMOS
PU/PD
0
0
1
0
OFF
7
1.8 V/3.3 V VDDSHV4
Yes
LVCMOS
PU/PD
0
0
OFF
7
1.8 V/3.3 V VDDSHV4
Yes
LVCMOS
PU/PD
0
0
Terminal Configuration and Functions
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Table 4-1. Pin Attributes (continued)
BALL NUMBER
[1]
AD22
ADVANCE INFORMATION
AC21
AF18
AE18
42
BALL NAME [2]
PRG1_PRU1_GPO18
PRG1_PRU1_GPO19
PRG2_PRU0_GPO0
PRG2_PRU0_GPO1
SIGNAL NAME [3]
MUXMODE
[4]
TYPE [5]
BALL
BALL
RESET
I/O
RESET
REL.
VOLTAGE
STATE [6] MUXMODE VALUE [8]
[7]
OFF
7
POWER [9]
1.8 V/3.3 V VDDSHV4
HYS [10]
Yes
BUFFER
TYPE [11]
LVCMOS
PULL
UP/DOWN
TYPE [12]
PU/PD
DSIS [13]
PRG1_PRU1_GPO18
0
IO
PRG1_PRU1_GPI18
1
I
0
0
PRG1_IEP1_EDC_LATCH_IN0
2
I
0
PRG1_PWM1_TZ_IN
3
I
0
SPI2_D0
4
IO
0
PRG1_ECAP0_SYNC_IN
5
I
0
UART1_CTSn
6
I
1
GPIO0_94
7
IO
PRG1_PRU1_GPO19
0
IO
PRG1_PRU1_GPI19
1
I
PRG1_IEP1_EDC_SYNC_OUT0
2
O
PRG1_PWM1_TZ_OUT
3
O
SPI2_D1
4
IO
0
PRG1_ECAP0_IN_APWM_OUT
5
IO
0
UART1_RTSn
6
O
GPIO0_95
7
IO
PRG2_PRU0_GPO0
0
IO
PRG2_PRU0_GPI0
1
I
0
PRG2_RGMII1_RD0
2
I
0
GPMC0_A25
3
OZ
TRC_CLK
4
O
EHRPWM0_SYNCI
5
I
0
PRG2_PWM3_A0
6
IO
0
GPIO0_30
7
IO
PRG2_PRU0_GPO1
0
IO
PRG2_PRU0_GPI1
1
I
0
PRG2_RGMII1_RD1
2
I
0
GPMC0_A24
3
OZ
TRC_CTL
4
O
EHRPWM0_SYNCO
5
O
SYNC2_OUT
6
O
GPIO0_31
7
IO
RXACTIVE/
IO Daisy
TXDISABL
Chain [15]
E [14]
0/1
Yes
0/1
Yes
0/1
Yes
0/1
Yes
0
OFF
7
1.8 V/3.3 V VDDSHV4
Yes
LVCMOS
PU/PD
0
0
0
OFF
7
1.8 V/3.3 V VDDSHV5
Yes
LVCMOS
PU/PD
0
0
OFF
7
1.8 V/3.3 V VDDSHV5
Terminal Configuration and Functions
Yes
LVCMOS
PU/PD
0
0
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SPRSP31E – APRIL 2018 – REVISED JUNE 2019
Table 4-1. Pin Attributes (continued)
AH17
AG18
AG17
AF17
BALL NAME [2]
PRG2_PRU0_GPO2
PRG2_PRU0_GPO3
PRG2_PRU0_GPO4
PRG2_PRU0_GPO5
SIGNAL NAME [3]
MUXMODE
[4]
TYPE [5]
BALL
BALL
RESET
I/O
RESET
REL.
VOLTAGE
STATE [6] MUXMODE VALUE [8]
[7]
OFF
7
POWER [9]
1.8 V/3.3 V VDDSHV5
HYS [10]
Yes
BUFFER
TYPE [11]
LVCMOS
PULL
UP/DOWN
TYPE [12]
PU/PD
DSIS [13]
PRG2_PRU0_GPO2
0
IO
PRG2_PRU0_GPI2
1
I
0
0
PRG2_RGMII1_RD2
2
I
0
GPMC0_A23
3
OZ
TRC_DATA0
4
O
EHRPWM_TZn_IN0
5
I
SYNC3_OUT
6
O
GPIO0_32
7
IO
PRG2_PRU0_GPO3
0
IO
PRG2_PRU0_GPI3
1
I
0
PRG2_RGMII1_RD3
2
I
0
GPMC0_A22
3
OZ
TRC_DATA1
4
O
EHRPWM0_A
5
IO
0
PRG2_PWM3_B0
6
IO
1
GPIO0_33
7
IO
PRG2_PRU0_GPO4
0
IO
PRG2_PRU0_GPI4
1
I
0
PRG2_RGMII1_RX_CTL
2
I
0
GPMC0_A21
3
OZ
TRC_DATA2
4
O
EHRPWM0_B
5
IO
0
PRG2_PWM0_A0
6
IO
0
GPIO0_34
7
IO
PRG2_PRU0_GPO5
0
IO
PRG2_PRU0_GPI5
1
I
0
PRG2_RGMII1_RXC
2
I
0
GPMC0_A20
3
OZ
TRC_DATA3
4
O
EHRPWM1_A
5
IO
0
PRG2_PWM3_A1
6
IO
0
GPIO0_35
7
IO
0
RXACTIVE/
IO Daisy
TXDISABL
Chain [15]
E [14]
0/1
Yes
0/1
Yes
0/1
Yes
0/1
Yes
0
ADVANCE INFORMATION
BALL NUMBER
[1]
0
OFF
7
1.8 V/3.3 V VDDSHV5
Yes
LVCMOS
PU/PD
0
0
OFF
7
1.8 V/3.3 V VDDSHV5
Yes
LVCMOS
PU/PD
0
0
OFF
7
1.8 V/3.3 V VDDSHV5
Yes
LVCMOS
PU/PD
0
Terminal Configuration and Functions
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Table 4-1. Pin Attributes (continued)
BALL NUMBER
[1]
AE17
ADVANCE INFORMATION
AC19
AH16
AG16
44
BALL NAME [2]
PRG2_PRU0_GPO6
PRG2_PRU0_GPO7
PRG2_PRU0_GPO8
PRG2_PRU0_GPO9
SIGNAL NAME [3]
MUXMODE
[4]
TYPE [5]
BALL
BALL
RESET
I/O
RESET
REL.
VOLTAGE
STATE [6] MUXMODE VALUE [8]
[7]
OFF
7
POWER [9]
1.8 V/3.3 V VDDSHV5
HYS [10]
Yes
BUFFER
TYPE [11]
LVCMOS
PULL
UP/DOWN
TYPE [12]
PU/PD
DSIS [13]
PRG2_PRU0_GPO6
0
IO
PRG2_PRU0_GPI6
1
I
0
PRG2_RGMII1_TX_CTL
2
O
GPMC0_A19
3
OZ
TRC_DATA4
4
O
EHRPWM1_B
5
IO
0
PRG2_PWM3_B1
6
IO
1
GPIO0_36
7
IO
PRG2_PRU0_GPO7
0
IO
PRG2_PRU0_GPI7
1
I
0
PRG2_MDIO0_MDIO
2
IO
0
GPMC0_A18
3
OZ
TRC_DATA5
4
O
EHRPWM_TZn_IN1
5
I
EHRPWM_SOCA
6
O
GPIO0_37
7
IO
PRG2_PRU0_GPO8
0
IO
PRG2_PRU0_GPI8
1
I
PRG2_RGMII1_TD0
2
O
GPMC0_A17
3
OZ
TRC_DATA6
4
O
EHRPWM2_A
5
IO
0
PRG2_PWM0_B0
6
IO
1
GPIO0_38
7
IO
PRG2_PRU0_GPO9
0
IO
PRG2_PRU0_GPI9
1
I
PRG2_RGMII1_TD1
2
O
GPMC0_A16
3
OZ
TRC_DATA7
4
O
EHRPWM2_B
5
IO
0
GPIO0_39
7
IO
0
RXACTIVE/
IO Daisy
TXDISABL
Chain [15]
E [14]
0/1
Yes
0/1
Yes
0/1
Yes
0/1
Yes
0
0
OFF
7
1.8 V/3.3 V VDDSHV5
Yes
LVCMOS
PU/PD
0
0
0
OFF
7
1.8 V/3.3 V VDDSHV5
Yes
LVCMOS
PU/PD
0
0
0
OFF
7
1.8 V/3.3 V VDDSHV5
Terminal Configuration and Functions
Yes
LVCMOS
PU/PD
0
0
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SPRSP31E – APRIL 2018 – REVISED JUNE 2019
Table 4-1. Pin Attributes (continued)
AF16
AE16
AD16
AH15
BALL NAME [2]
PRG2_PRU0_GPO10
PRG2_PRU0_GPO11
PRG2_PRU0_GPO16
PRG2_PRU1_GPO0
SIGNAL NAME [3]
MUXMODE
[4]
TYPE [5]
BALL
BALL
RESET
I/O
RESET
REL.
VOLTAGE
STATE [6] MUXMODE VALUE [8]
[7]
OFF
7
POWER [9]
1.8 V/3.3 V VDDSHV5
HYS [10]
Yes
BUFFER
TYPE [11]
LVCMOS
PULL
UP/DOWN
TYPE [12]
PU/PD
DSIS [13]
PRG2_PRU0_GPO10
0
IO
PRG2_PRU0_GPI10
1
I
0
PRG2_RGMII1_TD2
2
O
GPMC0_A15
3
OZ
TRC_DATA8
4
O
EHRPWM_TZn_IN2
5
I
EHRPWM_SOCB
6
O
GPIO0_40
7
IO
PRG2_PRU0_GPO11
0
IO
PRG2_PRU0_GPI11
1
I
PRG2_RGMII1_TD3
2
O
GPMC0_A14
3
OZ
TRC_DATA9
4
O
PRG2_ECAP0_IN_APWM_OUT
6
IO
GPIO0_41
7
IO
PRG2_PRU0_GPO16
0
IO
PRG2_PRU0_GPI16
1
I
0
PRG2_RGMII1_TXC
2
IO
0
GPMC0_A13
3
OZ
TRC_DATA10
4
O
PRG2_PWM0_A1
6
IO
GPIO0_42
7
IO
PRG2_PRU1_GPO0
0
IO
PRG2_PRU1_GPI0
1
I
0
PRG2_RGMII2_RD0
2
I
0
GPMC0_A12
3
OZ
TRC_DATA11
4
O
EHRPWM3_A
5
IO
0
PRG2_PWM3_A2
6
IO
0
GPIO0_43
7
IO
0
RXACTIVE/
IO Daisy
TXDISABL
Chain [15]
E [14]
0/1
Yes
0/1
Yes
0/1
Yes
0/1
Yes
0
0
ADVANCE INFORMATION
BALL NUMBER
[1]
0
OFF
7
1.8 V/3.3 V VDDSHV5
Yes
LVCMOS
PU/PD
0
0
0
0
OFF
7
1.8 V/3.3 V VDDSHV5
Yes
LVCMOS
PU/PD
0
0
0
OFF
7
1.8 V/3.3 V VDDSHV5
Yes
LVCMOS
PU/PD
0
Terminal Configuration and Functions
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Table 4-1. Pin Attributes (continued)
BALL NUMBER
[1]
AC16
ADVANCE INFORMATION
AD17
AH14
AG14
46
BALL NAME [2]
PRG2_PRU1_GPO1
PRG2_PRU1_GPO2
PRG2_PRU1_GPO3
PRG2_PRU1_GPO4
SIGNAL NAME [3]
MUXMODE
[4]
TYPE [5]
BALL
BALL
RESET
I/O
RESET
REL.
VOLTAGE
STATE [6] MUXMODE VALUE [8]
[7]
OFF
7
POWER [9]
1.8 V/3.3 V VDDSHV5
HYS [10]
Yes
BUFFER
TYPE [11]
LVCMOS
PULL
UP/DOWN
TYPE [12]
PU/PD
DSIS [13]
PRG2_PRU1_GPO1
0
IO
PRG2_PRU1_GPI1
1
I
0
0
PRG2_RGMII2_RD1
2
I
0
GPMC0_A11
3
OZ
TRC_DATA12
4
O
EHRPWM3_B
5
IO
0
PRG2_PWM3_B2
6
IO
1
GPIO0_44
7
IO
PRG2_PRU1_GPO2
0
IO
PRG2_PRU1_GPI2
1
I
0
PRG2_RGMII2_RD2
2
I
0
GPMC0_A10
3
OZ
TRC_DATA13
4
O
EHRPWM3_SYNCI
5
I
0
PRG2_PWM0_B1
6
IO
1
GPIO0_45
7
IO
PRG2_PRU1_GPO3
0
IO
PRG2_PRU1_GPI3
1
I
0
PRG2_RGMII2_RD3
2
I
0
GPMC0_A9
3
OZ
TRC_DATA14
4
O
EHRPWM3_SYNCO
5
O
GPIO0_46
7
IO
PRG2_PRU1_GPO4
0
IO
PRG2_PRU1_GPI4
1
I
0
PRG2_RGMII2_RX_CTL
2
I
0
GPMC0_A8
3
OZ
TRC_DATA15
4
O
EHRPWM_TZn_IN3
5
I
PRG2_ECAP0_SYNC_OUT
6
O
GPIO0_47
7
IO
RXACTIVE/
IO Daisy
TXDISABL
Chain [15]
E [14]
0/1
Yes
0/1
Yes
0/1
Yes
0/1
Yes
0
OFF
7
1.8 V/3.3 V VDDSHV5
Yes
LVCMOS
PU/PD
0
0
OFF
7
1.8 V/3.3 V VDDSHV5
Yes
LVCMOS
PU/PD
0
0
OFF
7
1.8 V/3.3 V VDDSHV5
Terminal Configuration and Functions
Yes
LVCMOS
PU/PD
0
0
0
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SPRSP31E – APRIL 2018 – REVISED JUNE 2019
Table 4-1. Pin Attributes (continued)
AG15
AC17
AE15
AD15
BALL NAME [2]
PRG2_PRU1_GPO5
PRG2_PRU1_GPO6
PRG2_PRU1_GPO7
PRG2_PRU1_GPO8
SIGNAL NAME [3]
MUXMODE
[4]
TYPE [5]
BALL
BALL
RESET
I/O
RESET
REL.
VOLTAGE
STATE [6] MUXMODE VALUE [8]
[7]
OFF
7
POWER [9]
1.8 V/3.3 V VDDSHV5
HYS [10]
Yes
BUFFER
TYPE [11]
LVCMOS
PULL
UP/DOWN
TYPE [12]
PU/PD
DSIS [13]
PRG2_PRU1_GPO5
0
IO
PRG2_PRU1_GPI5
1
I
0
0
PRG2_RGMII2_RXC
2
I
0
GPMC0_A7
3
OZ
TRC_DATA16
4
O
EHRPWM4_A
5
IO
GPIO0_48
7
IO
PRG2_PRU1_GPO6
0
IO
PRG2_PRU1_GPI6
1
I
PRG2_RGMII2_TX_CTL
2
O
GPMC0_A6
3
OZ
TRC_DATA17
4
O
EHRPWM4_B
5
IO
GPIO0_49
7
IO
PRG2_PRU1_GPO7
0
IO
PRG2_PRU1_GPI7
1
I
PRG2_MDIO0_MDC
2
O
GPMC0_A5
3
OZ
TRC_DATA18
4
O
EHRPWM_TZn_IN4
5
I
0
PRG2_PWM3_TZ_IN
6
I
0
GPIO0_50
7
IO
PRG2_PRU1_GPO8
0
IO
PRG2_PRU1_GPI8
1
I
PRG2_RGMII2_TD0
2
O
GPMC0_A4
3
OZ
TRC_DATA19
4
O
EHRPWM5_A
5
IO
0
PRG2_PWM0_A2
6
IO
0
GPIO0_51
7
IO
0
RXACTIVE/
IO Daisy
TXDISABL
Chain [15]
E [14]
0/1
Yes
0/1
Yes
0/1
Yes
0/1
Yes
0
0
OFF
7
1.8 V/3.3 V VDDSHV5
Yes
LVCMOS
PU/PD
0
ADVANCE INFORMATION
BALL NUMBER
[1]
0
0
0
OFF
7
1.8 V/3.3 V VDDSHV5
Yes
LVCMOS
PU/PD
0
0
0
OFF
7
1.8 V/3.3 V VDDSHV5
Yes
LVCMOS
PU/PD
0
0
Terminal Configuration and Functions
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DRA80M
SPRSP31E – APRIL 2018 – REVISED JUNE 2019
www.ti.com
Table 4-1. Pin Attributes (continued)
BALL NUMBER
[1]
AF14
ADVANCE INFORMATION
AC15
AD14
AE14
BALL NAME [2]
PRG2_PRU1_GPO9
PRG2_PRU1_GPO10
PRG2_PRU1_GPO11
PRG2_PRU1_GPO16
SIGNAL NAME [3]
MUXMODE
[4]
TYPE [5]
BALL
BALL
RESET
I/O
RESET
REL.
VOLTAGE
STATE [6] MUXMODE VALUE [8]
[7]
OFF
7
POWER [9]
1.8 V/3.3 V VDDSHV5
HYS [10]
Yes
BUFFER
TYPE [11]
LVCMOS
PULL
UP/DOWN
TYPE [12]
PU/PD
DSIS [13]
PRG2_PRU1_GPO9
0
IO
PRG2_PRU1_GPI9
1
I
0
PRG2_RGMII2_TD1
2
O
GPMC0_A3
3
OZ
TRC_DATA20
4
O
EHRPWM5_B
5
IO
PRG2_PWM3_TZ_OUT
6
O
GPIO0_52
7
IO
PRG2_PRU1_GPO10
0
IO
PRG2_PRU1_GPI10
1
I
PRG2_RGMII2_TD2
2
O
GPMC0_A2
3
OZ
TRC_DATA21
4
O
EHRPWM_TZn_IN5
5
I
0
PRG2_PWM0_B2
6
IO
1
GPIO0_53
7
IO
PRG2_PRU1_GPO11
0
IO
PRG2_PRU1_GPI11
1
I
PRG2_RGMII2_TD3
2
O
GPMC0_A1
3
OZ
TRC_DATA22
4
O
PRG2_ECAP0_SYNC_IN
6
I
GPIO0_54
7
IO
PRG2_PRU1_GPO16
0
IO
PRG2_PRU1_GPI16
1
I
0
PRG2_RGMII2_TXC
2
IO
0
GPMC0_A0
3
OZ
TRC_DATA23
4
O
PRG2_PWM1_TZ_OUT
6
O
GPIO0_55
7
IO
RXACTIVE/
IO Daisy
TXDISABL
Chain [15]
E [14]
0/1
Yes
0/1
Yes
0/1
Yes
0/1
Yes
0
0
0
OFF
7
1.8 V/3.3 V VDDSHV5
Yes
LVCMOS
PU/PD
0
0
0
OFF
7
1.8 V/3.3 V VDDSHV5
Yes
LVCMOS
PU/PD
0
0
0
0
OFF
7
1.8 V/3.3 V VDDSHV5
Yes
LVCMOS
PU/PD
0
0
AF9
REFCLK0N
REFCLK0N
O
OFF
1.8 V
VDDA_1P8_SE
RDES0
LJCB CLK
No
AF10
REFCLK0P
REFCLK0P
O
OFF
1.8 V
VDDA_1P8_SE
RDES0
LJCB CLK
No
AE8
REFCLK1N
REFCLK1N
O
OFF
1.8 V
VDDA_1P8_SE
RDES0
LJCB CLK
No
AE9
REFCLK1P
REFCLK1P
O
OFF
1.8 V
VDDA_1P8_SE
RDES0
LJCB CLK
No
D19
RESETSTATz
RESETSTATz
O
OFF
48
0
0
1.8 V/3.3 V VDDSHV0
Terminal Configuration and Functions
Yes
LVCMOS
PU/PD
0/0
Yes
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SPRSP31E – APRIL 2018 – REVISED JUNE 2019
Table 4-1. Pin Attributes (continued)
BALL NAME [2]
SIGNAL NAME [3]
MUXMODE
[4]
BALL
BALL
RESET
I/O
RESET
REL.
VOLTAGE
STATE [6] MUXMODE VALUE [8]
[7]
POWER [9]
HYS [10]
DSIS [13]
RESETz
I
PU
0
1.8 V/3.3 V VDDSHV0
SERDES0_REFCLKN
SERDES0_REFCLKN
I
OFF
0
1.8 V
VDDA_1P8_SE
RDES0
SERDES0
No
AG6
SERDES0_REFCLKP
SERDES0_REFCLKP
I
OFF
0
1.8 V
VDDA_1P8_SE
RDES0
SERDES0
No
AC9
SERDES0_REFRES
SERDES0_REFRES
A
0
1.8 V
VDDA_1P8_SE
RDES0
SERDES0
No
AH3
SERDES0_RXN
SERDES0_RXN
I
OFF
0
1.8 V
VDDA_1P8_SE
RDES0
SERDES0
No
AG2
SERDES0_RXP
SERDES0_RXP
I
OFF
0
1.8 V
VDDA_1P8_SE
RDES0
SERDES0
No
AH4
SERDES0_TXN
SERDES0_TXN
O
OFF
0
1.8 V
VDDA_1P8_SE
RDES0
SERDES0
No
AG3
SERDES0_TXP
SERDES0_TXP
O
OFF
0
1.8 V
VDDA_1P8_SE
RDES0
SERDES0
No
AH6
SERDES1_REFCLKN
SERDES1_REFCLKN
I
OFF
0
1.8 V
VDDA_1P8_SE
RDES0
SERDES1
No
AH7
SERDES1_REFCLKP
SERDES1_REFCLKP
I
OFF
0
1.8 V
VDDA_1P8_SE
RDES0
SERDES1
No
AC14
SERDES1_REFRES
SERDES1_REFRES
A
0
1.8 V
VDDA_1P8_SE
RDES0
SERDES1
No
AG9
SERDES1_RXN
SERDES1_RXN
I
OFF
0
1.8 V
VDDA_1P8_SE
RDES0
SERDES1
No
AH10
SERDES1_RXP
SERDES1_RXP
I
OFF
0
1.8 V
VDDA_1P8_SE
RDES0
SERDES1
No
AH9
SERDES1_TXN
SERDES1_TXN
O
OFF
0
1.8 V
VDDA_1P8_SE
RDES0
SERDES1
No
AG8
SERDES1_TXP
SERDES1_TXP
O
OFF
0
1.8 V
VDDA_1P8_SE
RDES0
SERDES1
No
E20
SOC_SAFETY_ERRORn
SOC_SAFETY_ERRORn
0
IO
PD
0
1.8 V/3.3 V VDDSHV0
Yes
LVCMOS
PU/PD
AH13
SPI0_CLK
SPI0_CLK
0
IO
OFF
7
1.8 V/3.3 V VDDSHV1
Yes
LVCMOS
PU/PD
GPIO1_17
7
IO
SPI1_CLK
0
IO
PRG2_IEP0_EDC_SYNC_OUT0
3
O
PRG2_UART0_RTSn
4
O
GPIO1_22
7
IO
SPI0_CS0
0
IO
GPIO1_15
7
IO
SPI0_CS0
PU/PD
RXACTIVE/
IO Daisy
TXDISABL
Chain [15]
E [14]
RESETz
AG13
LVCMOS
PULL
UP/DOWN
TYPE [12]
AG5
SPI1_CLK
Yes
BUFFER
TYPE [11]
F17
AH12
0
TYPE [5]
1/1
0
Yes
1/0
Yes
0/1
Yes
0/1
Yes
0/1
Yes
ADVANCE INFORMATION
BALL NUMBER
[1]
0
OFF
7
1.8 V/3.3 V VDDSHV1
Yes
LVCMOS
PU/PD
OFF
7
1.8 V/3.3 V VDDSHV1
Yes
LVCMOS
PU/PD
0
0
1
0
Terminal Configuration and Functions
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SPRSP31E – APRIL 2018 – REVISED JUNE 2019
www.ti.com
Table 4-1. Pin Attributes (continued)
BALL NUMBER
[1]
AF13
AE13
ADVANCE INFORMATION
AD13
AD12
AG12
AE12
AF12
BALL NAME [2]
SPI0_CS1
SPI0_D0
SPI0_D1
SPI1_CS0
SPI1_CS1
SPI1_D0
SPI1_D1
SIGNAL NAME [3]
MUXMODE
[4]
TYPE [5]
BALL
BALL
RESET
I/O
RESET
REL.
VOLTAGE
STATE [6] MUXMODE VALUE [8]
[7]
OFF
7
POWER [9]
1.8 V/3.3 V VDDSHV1
HYS [10]
Yes
BUFFER
TYPE [11]
LVCMOS
PULL
UP/DOWN
TYPE [12]
PU/PD
DSIS [13]
SPI0_CS1
0
IO
CPTS0_TS_COMP
1
O
1
I2C3_SCL
2
IOD
PRG1_IEP0_EDIO_OUTVALID
6
O
GPIO1_16
7
IO
SPI0_D0
0
IO
GPIO1_18
7
IO
SPI0_D1
0
IO
GPIO1_19
7
IO
SPI1_CS0
0
IO
PRG2_IEP0_EDC_LATCH_IN0
3
I
0
PRG2_UART0_CTSn
4
I
1
PRG0_IEP0_EDIO_OUTVALID
6
O
GPIO1_20
7
IO
SPI1_CS1
0
IO
CPTS0_TS_SYNC
1
O
I2C3_SDA
2
IOD
GPIO1_21
7
IO
SPI1_D0
0
IO
PRG2_IEP0_EDC_LATCH_IN1
3
I
0
PRG2_UART0_RXD
4
I
1
GPIO1_23
7
IO
SPI1_D1
0
IO
PRG2_IEP0_EDC_SYNC_OUT1
3
O
PRG2_UART0_TXD
4
O
GPIO1_24
7
IO
RXACTIVE/
IO Daisy
TXDISABL
Chain [15]
E [14]
0/1
Yes
0/1
Yes
0/1
Yes
0/1
Yes
0/1
Yes
0/1
Yes
0/1
Yes
1
0
OFF
7
1.8 V/3.3 V VDDSHV1
Yes
LVCMOS
PU/PD
0
0
OFF
7
1.8 V/3.3 V VDDSHV1
Yes
LVCMOS
PU/PD
0
0
OFF
7
1.8 V/3.3 V VDDSHV1
Yes
LVCMOS
PU/PD
1
0
OFF
7
1.8 V/3.3 V VDDSHV1
Yes
LVCMOS
PU/PD
1
1
0
OFF
7
1.8 V/3.3 V VDDSHV1
Yes
LVCMOS
PU/PD
0
0
OFF
7
1.8 V/3.3 V VDDSHV1
Yes
LVCMOS
PU/PD
0
0
AA4
TCK
TCK
0
I
PU
0
1.8 V/3.3 V VDDSHV0_WKU Yes
P
LVCMOS
PU/PD
1/1
Yes
C20
TDI
TDI
0
I
PU
0
1.8 V/3.3 V VDDSHV0
LVCMOS
PU/PD
1/1
Yes
A20
TDO
TDO
0
OZ
PU
0
1.8 V/3.3 V VDDSHV0
LVCMOS
PU/PD
0/0
Yes
W6
TEMP_DIODE_P
TEMP_DIODE_P
1.8 V
Power
B22
TIMER_IO0
TIMER_IO0
0
IO
SYSCLKOUT0
2
O
GPIO1_88
7
IO
TIMER_IO1
0
IO
OBSCLK0
2
O
GPIO1_89
7
IO
C23
50
TIMER_IO1
A
Yes
No
OFF
7
1.8 V/3.3 V VDDSHV0
Yes
LVCMOS
PU/PD
OFF
7
1.8 V/3.3 V VDDSHV0
Yes
LVCMOS
PU/PD
0
0/1
Yes
0/1
Yes
0
Terminal Configuration and Functions
0
0
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SPRSP31E – APRIL 2018 – REVISED JUNE 2019
Table 4-1. Pin Attributes (continued)
BALL NAME [2]
SIGNAL NAME [3]
MUXMODE
[4]
TYPE [5]
BALL
BALL
RESET
I/O
RESET
REL.
VOLTAGE
STATE [6] MUXMODE VALUE [8]
[7]
POWER [9]
HYS [10]
BUFFER
TYPE [11]
PULL
UP/DOWN
TYPE [12]
DSIS [13]
RXACTIVE/
IO Daisy
TXDISABL
Chain [15]
E [14]
A21
TMS
TMS
0
I
PU
0
1.8 V/3.3 V VDDSHV0
Yes
LVCMOS
PU/PD
1/1
Yes
AA3
TRSTn
TRSTn
0
I
PD
0
1.8 V/3.3 V VDDSHV0_WKU Yes
P
LVCMOS
PU/PD
1/1
Yes
AG11
UART0_CTSn
UART0_CTSn
0
I
OFF
7
1.8 V/3.3 V VDDSHV1
LVCMOS
PU/PD
0/1
Yes
TIMER_IO4
1
IO
0
SPI0_CS2
2
IO
1
GPIO1_27
7
IO
UART0_RTSn
0
O
0/1
Yes
TIMER_IO5
1
IO
0
SPI0_CS3
2
IO
1
GPIO1_28
7
IO
UART0_RXD
0
I
0/1
Yes
GPIO1_25
7
IO
UART0_TXD
0
O
0/1
Yes
GPIO1_26
7
IO
AD11
AF11
AE11
UART0_RTSn
UART0_RXD
UART0_TXD
Yes
1
0
OFF
7
1.8 V/3.3 V VDDSHV1
Yes
LVCMOS
PU/PD
0
OFF
7
1.8 V/3.3 V VDDSHV1
Yes
LVCMOS
PU/PD
1
0
OFF
7
1.8 V/3.3 V VDDSHV1
Yes
LVCMOS
PU/PD
0
AE2
USB0_DM
USB0_DM
IO
OFF
3.3 V
VDDA_3P3_US
B
USBHS
No
AF1
USB0_DP
USB0_DP
IO
OFF
3.3 V
VDDA_3P3_US
B
USBHS
No
AD9
USB0_DRVVBUS
USB0_DRVVBUS
0
O
PD
GPIO1_71
7
IO
USB0_ID
USB0_ID
A
AE7
USB0_VBUS
USB0_VBUS
A
AD2
USB1_DM
USB1_DM
IO
OFF
AE1
USB1_DP
USB1_DP
IO
OFF
AC8
USB1_DRVVBUS
USB1_DRVVBUS
0
O
PD
GPIO1_72
7
IO
USB1_ID
USB1_ID
A
AF6
USB1_VBUS
USB1_VBUS
A
AB6
VDDA_1P8_MON_WKUP
VDDA_1P8_MON_WKUP
A
G17
VDDA_1P8_SDIO
VDDA_1P8_SDIO
PWR
L20, M21
VDDA_1P8_CSI0
VDDA_1P8_CSI0
PWR
AC6
VDDA_1P8_MON0
VDDA_1P8_MON0
A
0
1.8 V/3.3 V VDDSHV8
Yes
LVCMOS
PU/PD
0/0
Yes
0
AF7
AF5
ADVANCE INFORMATION
BALL NUMBER
[1]
3.3 V
0
VDDA_3P3_US
B
USBHS
No
VDDA_3P3_US
B
USBHS
No
3.3 V
VDDA_3P3_US
B
USBHS
No
3.3 V
VDDA_3P3_US
B
USBHS
No
1.8 V/3.3 V VDDSHV8
Yes
LVCMOS
PU/PD
0/0
Yes
0
3.3 V
VDDA_3P3_US
B
USBHS
No
VDDA_3P3_US
B
USBHS
No
1.8 V
VDDA_POR_W
KUP
Analog
No
1.8 V
VDDA_POR_W
KUP
Analog
No
Terminal Configuration and Functions
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www.ti.com
Table 4-1. Pin Attributes (continued)
BALL NUMBER
[1]
L22
BALL NAME [2]
MUXMODE
[4]
TYPE [5]
ADVANCE INFORMATION
VDDA_1P8_OLDI0
PWR
AA14, AB13, AB15 VDDA_1P8_SERDES0
VDDA_1P8_SERDES0
PWR
AB9
VDDA_3P3_IOLDO_WKUP
VDDA_3P3_IOLDO_WKUP
PWR
U6
VDDA_3P3_MON_WKUP
VDDA_3P3_MON_WKUP
A
H17
VDDA_3P3_SDIO
VDDA_3P3_SDIO
PWR
AC12
VDDA_3P3_USB
VDDA_3P3_USB
PWR
G18
VDDA_3P3_IOLDO0
VDDA_3P3_IOLDO0
PWR
AA21
VDDA_3P3_IOLDO1
VDDA_3P3_IOLDO1
PWR
AC10
VDDA_3P3_MON0
VDDA_3P3_MON0
A
M7, M9
VDDA_ADC_MCU
VDDA_ADC_MCU
PWR
AB8
VDDA_LDO_WKUP
VDDA_LDO_WKUP
PWR
U12
VDDA_MCU
VDDA_MCU
PWR
H15
VDDA_PLL0_DDR
VDDA_PLL0_DDR
PWR
H11
VDDA_PLL1_DDR
VDDA_PLL1_DDR
PWR
Y17
VDDA_PLL_CORE
VDDA_PLL_CORE
PWR
L21
VDDA_PLL_DSS
VDDA_PLL_DSS
PWR
L12
VDDA_PLL_MPU0
VDDA_PLL_MPU0
PWR
K15
VDDA_PLL_MPU1
VDDA_PLL_MPU1
PWR
AB7
VDDA_PLL_PER0
VDDA_PLL_PER0
PWR
Y9
VDDA_POR_WKUP
VDDA_POR_WKUP
PWR
M19
VDDA_SRAM_CORE0
VDDA_SRAM_CORE0
PWR
V16
VDDA_SRAM_CORE1
VDDA_SRAM_CORE1
PWR
K7
VDDA_SRAM_MPU0
VDDA_SRAM_MPU0
PWR
L18
VDDA_SRAM_MPU1
VDDA_SRAM_MPU1
PWR
AC11
VDDA_VSYS_MON
VDDA_VSYS_MON
A
AA9
VDDA_WKUP
VDDA_WKUP
PWR
G12
VDDS0
VDDS0
PWR
V8
VDDS0_WKUP
VDDS0_WKUP
PWR
AA16
VDDS1
VDDS1
PWR
T9
VDDS1_WKUP
VDDS1_WKUP
PWR
P20
VDDS2
VDDS2
PWR
N8
VDDS2_WKUP
VDDS2_WKUP
PWR
T20
VDDS3
VDDS3
PWR
Y20
VDDS4
VDDS4
PWR
AC18
VDDS5
VDDS5
PWR
52
VDDA_1P8_OLDI0
SIGNAL NAME [3]
BALL
BALL
RESET
I/O
RESET
REL.
VOLTAGE
STATE [6] MUXMODE VALUE [8]
[7]
POWER [9]
HYS [10]
BUFFER
TYPE [11]
PULL
UP/DOWN
TYPE [12]
DSIS [13]
RXACTIVE/
IO Daisy
TXDISABL
Chain [15]
E [14]
1.8 V
VDDA_POR_W
KUP
Analog
No
1.8 V
VDDA_POR_W
KUP
Analog
No
1.8 V
VDDA_POR_W
KUP
Analog
No
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Table 4-1. Pin Attributes (continued)
BALL NAME [2]
SIGNAL NAME [3]
MUXMODE
[4]
TYPE [5]
F20
VDDS6
VDDS6
PWR
K20
VDDS7
VDDS7
PWR
AA10
VDDS8
VDDS8
PWR
G15, H16
VDDSHV0
VDDSHV0
PWR
U8, V7, W8, Y7
VDDSHV0_WKUP
VDDSHV0_WKUP
PWR
AA18, AB17
VDDSHV1
VDDSHV1
PWR
R6, R8, T7
VDDSHV1_WKUP
VDDSHV1_WKUP
PWR
N20, N22, P21,
R20, R22
VDDSHV2
VDDSHV2
PWR
N6, P7, P9
VDDSHV2_WKUP
VDDSHV2_WKUP
PWR
T21, U20, U22,
V21, V23
VDDSHV3
VDDSHV3
PWR
AA22, W20, W22,
Y21, Y23
VDDSHV4
VDDSHV4
PWR
AA20, AB19, AB21, VDDSHV5
AB23
VDDSHV5
PWR
G20, H19, H21
VDDSHV6
VDDSHV6
PWR
J20, J22, K21
VDDSHV7
VDDSHV7
PWR
AB11
VDDSHV8
VDDSHV8
PWR
G10, G14, G8,
H13, H7, H9
VDDS_DDR
VDDS_DDR
PWR
J16
VDDS_OSC1
VDDS_OSC1
PWR
AA12, J10, J12,
J14, J19, J8, K13,
L14, L19, M13,
N14, P13, P15,
P19, R14, R16,
R18, T13, T15,
T17, T19, U14,
U16, U18, V13,
V15, V19, W14,
W18, Y11, Y13,
Y15
VDD_CORE
VDD_CORE
PWR
G22
VDD_DLL_MMC0
VDD_DLL_MMC0
PWR
H23
VDD_DLL_MMC1
VDD_DLL_MMC1
PWR
N10, P11, R10,
R12, T11
VDD_MCU
VDD_MCU
PWR
K11, K9, L10, L8,
M11
VDD_MPU0
VDD_MPU0
PWR
K16, K18, L17,
M16, M18, N17
VDD_MPU1
VDD_MPU1
PWR
V11, W10, W12
VDD_WKUP0
VDD_WKUP0
PWR
M22
VDD_WKUP1
VDD_WKUP1
PWR
F21
VPP_CORE
VPP_CORE
PWR
BALL
BALL
RESET
I/O
RESET
REL.
VOLTAGE
STATE [6] MUXMODE VALUE [8]
[7]
POWER [9]
HYS [10]
BUFFER
TYPE [11]
PULL
UP/DOWN
TYPE [12]
DSIS [13]
RXACTIVE/
IO Daisy
TXDISABL
Chain [15]
E [14]
ADVANCE INFORMATION
BALL NUMBER
[1]
OFF
1.8 V
Power
No
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Table 4-1. Pin Attributes (continued)
BALL NUMBER
[1]
T6
BALL NAME [2]
MUXMODE
[4]
TYPE [5]
BALL
BALL
RESET
I/O
RESET
REL.
VOLTAGE
STATE [6] MUXMODE VALUE [8]
[7]
HYS [10]
BUFFER
TYPE [11]
ADVANCE INFORMATION
PWR
GND
AF4
WKUP_GPIO0_0
0
IO
MCU_SPI1_CLK
1
IO
WKUP_GPIO0_0
7
IO
0
MCU_BOOTMODE00
Bootstrap
I
0
7
Power
1.8 V/3.3 V VDDSHV0_WKU Yes
P
LVCMOS
DSIS [13]
VSS
OFF
1.8 V
PULL
UP/DOWN
TYPE [12]
VPP_MCU
WKUP_GPIO0_0
OFF
POWER [9]
A1, A2, A28, AA11, VSS
AA13, AA15, AA17,
AA19, AA23, AA26,
AA7, AB10, AB12,
AB14, AB16, AB18,
AB20, AB22, AD4,
AE10, AE25, AE5,
AF15, AF2, AF20,
AF8, AG1, AG10,
AG28, AG4, AG7,
AH1, AH11, AH2,
AH27, AH28, AH5,
AH8, B12, B15,
B20, B6, B9, D22,
E26, E28, E4, F14,
F19, F22, F25,
F27, F3, G11, G13,
G16, G2, G21,
G23, G7, G9, H1,
H10, H12, H14,
H20, H22, H24,
H26, H28, H6, H8,
J11, J13, J15, J18,
J21, J23, J25, J27,
J7, J9, K1, K10,
K12, K14, K17,
K19, K22, K23, K6,
K8, L11, L13, L16,
L23, L24, L26, L28,
L3, L7, L9, M10,
M15, M17, M20,
M8, N11, N13,
N16, N19, N21, N7,
N9, P10, P12, P14,
P16, P18, P22, P6,
P8, R11, R13, R15,
R17, R19, R21, R7,
R9, T10, T12, T14,
T16, T18, T22,
T26, T8, U11, U13,
U15, U17, U19,
U21, U3, U7, U9,
V10, V12, V14,
V18, V20, V22, V6,
W11, W13, W15,
W17, W19, W21,
W23, W7, W9,
Y12, Y14, Y16,
Y18, Y22, Y6, Y8
54
VPP_MCU
SIGNAL NAME [3]
Terminal Configuration and Functions
RXACTIVE/
IO Daisy
TXDISABL
Chain [15]
E [14]
No
PU/PD
0
1/1
Yes
0
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Table 4-1. Pin Attributes (continued)
AF3
AE3
AD1
AC3
AD3
AC2
AC1
AC5
BALL NAME [2]
WKUP_GPIO0_1
WKUP_GPIO0_2
WKUP_GPIO0_3
WKUP_GPIO0_4
WKUP_GPIO0_5
WKUP_GPIO0_6
WKUP_GPIO0_7
WKUP_GPIO0_8
SIGNAL NAME [3]
MUXMODE
[4]
TYPE [5]
BALL
BALL
RESET
I/O
RESET
REL.
VOLTAGE
STATE [6] MUXMODE VALUE [8]
[7]
OFF
7
POWER [9]
HYS [10]
1.8 V/3.3 V VDDSHV0_WKU Yes
P
BUFFER
TYPE [11]
LVCMOS
PULL
UP/DOWN
TYPE [12]
PU/PD
DSIS [13]
WKUP_GPIO0_1
0
IO
MCU_SPI1_D0
1
IO
0
WKUP_GPIO0_1
7
IO
MCU_BOOTMODE01
Bootstrap
I
WKUP_GPIO0_2
0
IO
MCU_SPI1_D1
1
IO
WKUP_GPIO0_2
7
IO
MCU_BOOTMODE02
Bootstrap
I
WKUP_GPIO0_3
0
IO
MCU_SPI1_CS0
1
IO
WKUP_GPIO0_3
7
IO
MCU_BOOTMODE03
Bootstrap
I
WKUP_GPIO0_4
0
IO
MCU_MCAN1_TX
1
O
MCU_SPI0_CS3
2
IO
1
MCU_ADC_EXT_TRIGGER0
3
I
0
WKUP_GPIO0_4
7
IO
0
MCU_BOOTMODE04
Bootstrap
I
WKUP_GPIO0_5
0
IO
MCU_MCAN1_RX
1
I
MCU_SPI1_CS3
2
IO
1
MCU_ADC_EXT_TRIGGER1
3
I
0
WKUP_GPIO0_5
7
IO
WKUP_GPIO0_6
0
IO
WKUP_UART0_CTSn
1
I
MCU_CPTS0_HW1TSPUSH
2
I
WKUP_GPIO0_6
7
IO
WKUP_GPIO0_7
0
IO
WKUP_UART0_RTSn
1
O
MCU_CPTS0_HW2TSPUSH
2
I
WKUP_GPIO0_7
7
IO
WKUP_GPIO0_8
0
IO
MCU_CPTS0_TS_SYNC
2
O
WKUP_GPIO0_8
7
IO
0
MCU_BOOTMODE08
Bootstrap
I
0
RXACTIVE/
IO Daisy
TXDISABL
Chain [15]
E [14]
1/1
Yes
1/1
Yes
1/1
Yes
1/1
Yes
0/1
Yes
0/1
Yes
0/1
Yes
1/1
Yes
0
0
0
OFF
7
1.8 V/3.3 V VDDSHV0_WKU Yes
P
LVCMOS
PU/PD
0
0
0
ADVANCE INFORMATION
BALL NUMBER
[1]
0
OFF
7
1.8 V/3.3 V VDDSHV0_WKU Yes
P
LVCMOS
PU/PD
0
1
0
0
OFF
7
1.8 V/3.3 V VDDSHV0_WKU Yes
P
LVCMOS
PU/PD
0
0
OFF
7
1.8 V/3.3 V VDDSHV0_WKU Yes
P
LVCMOS
PU/PD
0
1
0
OFF
7
1.8 V/3.3 V VDDSHV0_WKU Yes
P
LVCMOS
PU/PD
0
1
0
0
OFF
7
1.8 V/3.3 V VDDSHV0_WKU Yes
P
LVCMOS
PU/PD
0
0
0
OFF
7
1.8 V/3.3 V VDDSHV0_WKU Yes
P
LVCMOS
PU/PD
0
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Table 4-1. Pin Attributes (continued)
BALL NUMBER
[1]
AB4
AB3
ADVANCE INFORMATION
AB2
BALL NAME [2]
WKUP_GPIO0_9
WKUP_GPIO0_10
WKUP_GPIO0_11
SIGNAL NAME [3]
MUXMODE
[4]
TYPE [5]
WKUP_GPIO0_9
0
IO
MCU_CPTS0_TS_COMP
2
O
WKUP_GPIO0_9
7
IO
MCU_BOOTMODE09
Bootstrap
I
WKUP_GPIO0_10
0
IO
MCU_EXT_REFCLK0
1
I
MCU_CPTS0_RFT_CLK
4
I
MCU_SYSCLKOUT0
5
O
WKUP_GPIO0_10
7
IO
WKUP_GPIO0_11
0
IO
MCU_OBSCLK0
1
O
MCU_TIMER_IO1
4
IO
MCU_CLKOUT0
6
O
BALL
BALL
RESET
I/O
RESET
REL.
VOLTAGE
STATE [6] MUXMODE VALUE [8]
[7]
OFF
7
POWER [9]
HYS [10]
1.8 V/3.3 V VDDSHV0_WKU Yes
P
BUFFER
TYPE [11]
LVCMOS
PULL
UP/DOWN
TYPE [12]
PU/PD
DSIS [13]
0
RXACTIVE/
IO Daisy
TXDISABL
Chain [15]
E [14]
1/1
Yes
0/1
Yes
0/1
Yes
0
0
OFF
7
1.8 V/3.3 V VDDSHV0_WKU Yes
P
LVCMOS
PU/PD
0
0
0
0
OFF
7
1.8 V/3.3 V VDDSHV0_WKU Yes
P
LVCMOS
PU/PD
0
0
WKUP_GPIO0_11
7
IO
AC7
WKUP_I2C0_SCL
WKUP_I2C0_SCL
0
IOD
OFF
0
1.8 V/3.3 V VDDSHV0_WKU Yes
P
I2C OPEN
DRAIN
1
1/0
Yes
AD6
WKUP_I2C0_SDA
WKUP_I2C0_SDA
0
IOD
OFF
0
1.8 V/3.3 V VDDSHV0_WKU Yes
P
I2C OPEN
DRAIN
1
1/0
Yes
AE4
WKUP_LFOSC0_XI
WKUP_LFOSC0_XI
I
OFF
1.8 V
VDDA_WKUP
Analog
No
AC4
WKUP_LFOSC0_XO
WKUP_LFOSC0_XO
O
OFF
1.8 V
VDDA_WKUP
Analog
No
AD5
WKUP_OSC0_XI
WKUP_OSC0_XI
I
OFF
1.8 V
VDDA_WKUP
Analog
No
AE6
WKUP_OSC0_XO
WKUP_OSC0_XO
O
OFF
1.8 V
VDDA_WKUP
Analog
AB1
WKUP_UART0_RXD
WKUP_UART0_RXD
0
I
OFF
WKUP_GPIO0_52
7
IO
WKUP_UART0_TXD
0
O
WKUP_GPIO0_53
7
IO
AB5
56
WKUP_UART0_TXD
0
OFF
7
7
1.8 V/3.3 V VDDSHV0_WKU Yes
P
LVCMOS
1.8 V/3.3 V VDDSHV0_WKU Yes
P
LVCMOS
Terminal Configuration and Functions
No
PU/PD
1
0/1
Yes
0/1
Yes
0
PU/PD
1
0
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The following list describes the table column headers:
1. BALL NUMBER: Ball numbers on the bottom side associated with each signal on the bottom.
2. BALL NAME: Mechanical name from package device (name is taken from muxmode 0).
3. SIGNAL NAME: Names of signals multiplexed on each ball (also notice that the name of the ball is the
signal name in muxmode 0).
NOTE
Table 4-1, Pin Attributes, does not take into account the subsystem multiplexing signals.
Subsystem multiplexing signals are described in Section 4.3, Signal Descriptions.
4. MUXMODE: Multiplexing mode number:
a. MUXMODE 0 is the primary muxmode. The primary muxmode is not necessarily the default
muxmode.
b. MUXMODE 1 through 7 are possible muxmodes for alternate functions. On each pin, some
muxmodes are effectively used for alternate functions, while some muxmodes are not used. Only
MUXMODE values which correspond to defined functions should be used.
c. Bootstrap are Special Configuration Pins, latched on rising edge of PORn / RESETFULLn. These
are not programable MUXMODE.
d. An empty box means Not Applicable.
5. TYPE: This column describes functionality of the pin when configured for the given mux mode. It does
not represent all capabilities of the pin, and as such, there may be other mux mode configurations
where these pins operate as a push-pull driver:
– I = Input
– O = Output
– IO = Input or Output
– IOD = Open drain terminal - Input or Output
– IOZ = Input, Output or Three-state terminal
– OZ = Output or Three-state terminal
– A = Analog
– PWR = Power
– GND = Ground
– CAP = LDO Capacitor.
6. BALL RESET STATE: The state of the terminal at power-on reset:
– DRIVE 0 (OFF): The buffer drives VOL (pulldown or pullup resistor not activated).
– DRIVE 1 (OFF): The buffer drives VOH (pulldown or pullup resistor not activated).
– OFF: High-impedance
– PD: High-impedance with an active pulldown resistor
– PU: High-impedance with an active pullup resistor
– An empty box means Not Applicable.
For more information on the CORE_PWRON_RET_RST reset signal and its reset sources, see
chapter Device Configuration in the device TRM.
7. BALL RESET REL. MUXMODE: This muxmode is automatically configured at the release of the
rstoutn signal.
An empty box means Not Applicable.
8. I/O VOLTAGE VALUE: This column describes the IO voltage value (the corresponding power supply).
An empty box means Not Applicable.
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NOTE
The default muxmode is the mode at the release of the reset; also see the BALL RESET
REL. MUXMODE column.
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9. POWER: The voltage supply that powers the terminal IO buffers.
An empty box means Not Applicable.
10. HYS: Indicates if the input buffer has hysteresis:
– Yes: With hysteresis
– No: Without hysteresis
An empty box means No.
For more information, see the hysteresis values in Section 5.6, Electrical Characteristics.
11. BUFFER TYPE: This column describes the associated output buffer type
An empty box means Not Applicable.
ADVANCE INFORMATION
For drive strength of the associated output buffer, refer to Section 5.6, Electrical Characteristics.
12. PULL UP/DOWN TYPE: indicates the presence of an internal pullup or pulldown resistor. Pullup and
pulldown resistors can be enabled or disabled via software.
– PU: Internal pullup
– PD: Internal pulldown
– PU/PD: Internal pullup and pulldown
– An empty box means No pull.
13. DSIS: The deselected input state (DSIS) indicates the state driven on the peripheral input (logic "0",
logic "1", or "PIN" level) when the peripheral pin function is not selected by any of the PINCNTLx
registers.
– 0: Logic 0 driven on the input signal port of the peripheral.
– 1: Logic 1 driven on the input signal port of the peripheral.
– An empty box means Not Applicable.
14. RXACTIVE / TXDISABLE:This column indicates the default value of the RXACTIVE / TXDISABLE
bits in the PADCONFIG register.
– RXACTIVE: 0 = receiver disabled, 1 = receiver enabled.
– TXDISABLE: 0 = driver enabled, 1 = driver disabled.
– An empty box means Not Applicable.
15. IO Daisy Chain:This column indicates which pins can be included in the daisy chain during low power
modes.
NOTE
Configuring two pins to the same input signal is not supported as it can yield unexpected
results. This can be easily prevented with the proper software configuration (HiZ mode is not
an input signal).
NOTE
When a pad is set into a multiplexing mode which is not defined by pin multiplexing, that
pad’s behavior is undefined. This should be avoided.
58
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4.3
SPRSP31E – APRIL 2018 – REVISED JUNE 2019
Signal Descriptions
Many signals are available on multiple pins, according to the software configuration of the pin multiplexing
options.
The following list describes the column headers:
(1) SIGNAL NAME: The name of the signal passing through the pin.
NOTE
In Table 4-1 and Table 4-75 are not described the subsystem multiplexing signals.
(3) PIN TYPE: This column describes functionality of the pin when configured for the given mux mode. It does not represent all capabilities
of the pin, and as such, there may be other mux mode configurations where these pins operate as a push-pull driver:
– I = Input
– O = Output
– IO = Input or Output
– IOD = Open drain terminal - Input or Output
– IOZ = Input, Output or Three-state terminal
– OZ = Output or Three-state terminal
– A = Analog
– PWR = Power
– GND = Ground
– CAP = LDO Capacitor
(4) BALL: Associated balls bottom
For more information on the I/O cell configurations, see section Pad Configuration Registers in the device TRM.
4.3.1
4.3.1.1
ADC
MCU Domain
Table 4-2. ADC Signal Descriptions
SIGNAL NAME [1]
DESCRIPTION [2]
PIN
TYPE [3]
BALL [4]
MCU_ADC_EXT_TRIGGER0
ADC Trigger Input
I
AC3
MCU_ADC_EXT_TRIGGER1
ADC Trigger Input
I
AD3
PIN
TYPE [3]
BALL [4]
Table 4-3. ADC0 Signal Descriptions
SIGNAL NAME [1]
DESCRIPTION [2]
MCU_ADC0_REFN
ADC Reference Input (negative)
A
K2
MCU_ADC0_REFP
ADC Reference Input (positive)
A
K3
MCU_ADC0_AIN0
ADC Analog Input 0
A
K5
MCU_ADC0_AIN1
ADC Analog Input 1
A
J3
MCU_ADC0_AIN2
ADC Analog Input 2
A
J1
MCU_ADC0_AIN3
ADC Analog Input 3
A
J5
MCU_ADC0_AIN4
ADC Analog Input 4
A
K4
MCU_ADC0_AIN5
ADC Analog Input 5
A
J4
MCU_ADC0_AIN6
ADC Analog Input 6
A
J2
MCU_ADC0_AIN7
ADC Analog Input 7
A
J6
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(2) DESCRIPTION: Description of the signal
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Table 4-4. ADC1 Signal Descriptions
SIGNAL NAME [1]
DESCRIPTION [2]
PIN
TYPE [3]
BALL [4]
MCU_ADC1_REFN
ADC Reference Input (negative)
A
H3
MCU_ADC1_REFP
ADC Reference Input (positive)
A
H2
MCU_ADC1_AIN0
ADC Analog Input 0
A
F4
MCU_ADC1_AIN1
ADC Analog Input 1
A
G6
MCU_ADC1_AIN2
ADC Analog Input 2
A
G4
MCU_ADC1_AIN3
ADC Analog Input 3
A
H5
MCU_ADC1_AIN4
ADC Analog Input 4
A
F5
MCU_ADC1_AIN5
ADC Analog Input 5
A
G5
MCU_ADC1_AIN6
ADC Analog Input 6
A
G3
MCU_ADC1_AIN7
ADC Analog Input 7
A
H4
PIN
TYPE [3]
BALL [4]
4.3.2
CAL
4.3.2.1
MAIN Domain
ADVANCE INFORMATION
Table 4-5. CSI0 Signal Descriptions
SIGNAL NAME [1]
DESCRIPTION [2]
CSI0_RXN0
CSI Differential Receive Input (negative)
I
G28
CSI0_RXN1
CSI Differential Receive Input (negative)
I
H27
CSI0_RXN2
CSI Differential Receive Input (negative)
I
F26
CSI0_RXN3
CSI Differential Receive Input (negative)
I
H25
CSI0_RXN4(1)
CSI Differential Receive Input (negative)
I
G24
CSI0_RXP0
CSI Differential Receive Input (positive)
I
F28
CSI0_RXP1
CSI Differential Receive Input (positive)
I
G27
CSI0_RXP2
CSI Differential Receive Input (positive)
I
G26
CSI0_RXP3
CSI Differential Receive Input (positive)
I
G25
CSI0_RXP4(1)
CSI Differential Receive Input (positive)
I
F24
(1) Line 4 (position 5) supports only data. For more information, see section Camera Adapter Layer (CAL) Subsystem in the device TRM.
NOTE
Video Input Port (VIN) interface is not included on this variant of a pin compatible family of
devices. Refer to Table 3-1, Device Comparison to determine which devices support this
interface.
Table 4-6. VIN0 Signal Descriptions
SIGNAL NAME [1]
DESCRIPTION [2]
PIN
TYPE [3]
BALL [4]
VIN0_HD(1)
Video Input Horizontal Sync
I
P23
VIN0_PCLK(1)
Video Input Pixel Clock
I
R28
VIN0_VD(1)
R23
Video Input Vertical Sync
I
(1)
Video Input Data 0
I
N23
VIN0_DATA1(1)
Video Input Data 1
I
M26
VIN0_DATA2(1)
Video Input Data 2
I
P28
(1)
Video Input Data 3
I
P27
VIN0_DATA4(1)
Video Input Data 4
I
N26
VIN0_DATA5(1)
Video Input Data 5
I
N25
VIN0_DATA0
VIN0_DATA3
60
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Table 4-6. VIN0 Signal Descriptions (continued)
SIGNAL NAME [1]
PIN
TYPE [3]
DESCRIPTION [2]
BALL [4]
VIN0_DATA6(1)
Video Input Data 6
I
P24
VIN0_DATA7(1)
Video Input Data 7
I
R27
VIN0_DATA8(1)
Video Input Data 8
I
T24
(1)
VIN0_DATA9
Video Input Data 9
I
T23
VIN0_DATA10(1)
Video Input Data 10
I
R25
VIN0_DATA11(1)
Video Input Data 11
I
T27
VIN0_DATA12(1)
Video Input Data 12
I
M27
VIN0_DATA13(1)
Video Input Data 13
I
M23
VIN0_DATA14(1)
Video Input Data 14
I
M28
VIN0_DATA15(1)
Video Input Data 15
I
M24
(1) Video Input Port (VIN) interface is not included on this variant of a pin compatible family of devices. Refer to Table 3-1, Device
Comparison to determine which devices support this interface.
4.3.3.1
CPSW2G
ADVANCE INFORMATION
4.3.3
MCU Domain
Table 4-7. CPSW2G0 Signal Descriptions
SIGNAL NAME [1]
DESCRIPTION [2]
PIN
TYPE [3]
BALL [4]
AB3
MCU_CPTS0_RFT_CLK
CPTS Reference Clock
I
MCU_CPTS0_TS_COMP
CPTS Time Stamp Counter Compare
O
AB4
MCU_CPTS0_TS_SYNC
CPTS Time Stamp Counter Bit
O
AC5
MCU_CPTS0_HW1TSPUSH
CPTS Hardware Time Stamp Push 1
I
AC2
MCU_CPTS0_HW2TSPUSH
CPTS Hardware Time Stamp Push 2
I
AC1
MCU_MDIO0_MDC
MDIO Clock
O
L1
MCU_MDIO0_MDIO
MDIO Data
IO
L4
MCU_RGMII1_RXC
RGMII Receive Clock
I
M1
MCU_RGMII1_RX_CTL
RGMII Receive Control
I
N5
MCU_RGMII1_TXC
RGMII Transmit Clock
IO
N1
MCU_RGMII1_TX_CTL
RGMII Transmit Control
O
N4
MCU_RGMII1_RD0
RGMII Receive Data 0
I
L6
MCU_RGMII1_RD1
RGMII Receive Data 1
I
M6
MCU_RGMII1_RD2
RGMII Receive Data 2
I
L5
MCU_RGMII1_RD3
RGMII Receive Data 3
I
L2
MCU_RGMII1_TD0
RGMII Transmit Data 0
O
M5
MCU_RGMII1_TD1
RGMII Transmit Data 1
O
M4
MCU_RGMII1_TD2
RGMII Transmit Data 2
O
M3
MCU_RGMII1_TD3
RGMII Transmit Data 3
O
M2
MCU_RMII1_CRS_DV
RMII Carrier Sense / Data Valid
I
N4
MCU_RMII1_REF_CLK
RMII Reference Clock
I
M1
MCU_RMII1_RX_ER
RMII Receive Data Error
I
N5
MCU_RMII1_TX_EN
RMII Transmit Enable
O
N1
MCU_RMII1_RXD0
RMII Receive Data 0
I
L6
MCU_RMII1_RXD1
RMII Receive Data 1
I
M6
MCU_RMII1_TXD0
RMII Transmit Data 0
O
M5
MCU_RMII1_TXD1
RMII Transmit Data 1
O
M4
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4.3.4
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DDRSS
4.3.4.1
MAIN Domain
Table 4-8. DDRSS0 Signal Descriptions
SIGNAL NAME [1]
DESCRIPTION [2]
PIN
TYPE [3]
BALL [4]
ADVANCE INFORMATION
DDR_AC0
DDRSS Address and Command Bus
IO
A10
DDR_AC1
DDRSS Address and Command Bus
IO
D9
DDR_AC2
DDRSS Address and Command Bus
IO
C9
DDR_AC3
DDRSS Address and Command Bus
IO
E9
DDR_AC4
DDRSS Address and Command Bus
IO
A9
DDR_AC5
DDRSS Address and Command Bus
IO
E8
DDR_AC6
DDRSS Address and Command Bus
IO
F8
DDR_AC7
DDRSS Address and Command Bus
IO
C7
DDR_AC8
DDRSS Address and Command Bus
IO
C8
DDR_AC9
DDRSS Address and Command Bus
IO
D7
DDR_AC10
DDRSS Address and Command Bus
IO
E7
DDR_AC11
DDRSS Address and Command Bus
IO
A6
DDR_AC12
DDRSS Address and Command Bus
IO
F7
DDR_AC13
DDRSS Address and Command Bus
IO
D6
DDR_AC14
DDRSS Address and Command Bus
IO
C6
DDR_AC15
DDRSS Address and Command Bus
IO
F6
DDR_AC16
DDRSS Address and Command Bus
IO
E6
DDR_AC17
DDRSS Address and Command Bus
IO
E5
DDR_AC18
DDRSS Address and Command Bus
IO
D8
DDR_AC19
DDRSS Address and Command Bus
IO
D10
DDR_AC20
DDRSS Address and Command Bus
IO
E10
DDR_AC21
DDRSS Address and Command Bus
IO
C10
DDR_AC22
DDRSS Address and Command Bus
IO
F11
DDR_AC23
DDRSS Address and Command Bus
IO
B10
DDR_AC24
DDRSS Address and Command Bus
IO
D11
DDR_AC25
DDRSS Address and Command Bus
IO
B11
DDR_AC26
DDRSS Address and Command Bus
IO
C11
DDR_AC27
DDRSS Address and Command Bus
IO
E11
DDR_AC28
DDRSS Address and Command Bus
IO
E12
DDR_AC29
DDRSS Address and Command Bus
IO
D12
DDR_ALERTn
DDRSS Parity Error
IO
D5
DDR_CK0N
DDRSS Differential Clock (negative)
IO
B8
DDR_CK0P
DDRSS Differential Clock (positive)
IO
A8
DDR_CK1N
DDRSS Differential Clock (negative)
IO
B7
DDR_CK1P
DDRSS Differential Clock (positive)
IO
A7
DDR_DM0
DDRSS Data Mask
IO
E1
DDR_DM1
DDRSS Data Mask
IO
C5
DDR_DM2
DDRSS Data Mask
IO
D14
DDR_DM3
DDRSS Data Mask
IO
B17
DDR_DQ0
DDRSS Data
IO
A3
DDR_DQ1
DDRSS Data
IO
B2
DDR_DQ2
DDRSS Data
IO
C2
DDR_DQ3
DDRSS Data
IO
D2
62
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Table 4-8. DDRSS0 Signal Descriptions (continued)
DESCRIPTION [2]
PIN
TYPE [3]
BALL [4]
DDR_DQ4
DDRSS Data
IO
E2
DDR_DQ5
DDRSS Data
IO
G1
DDR_DQ6
DDRSS Data
IO
F2
DDR_DQ7
DDRSS Data
IO
F1
DDR_DQ8
DDRSS Data
IO
E3
DDR_DQ9
DDRSS Data
IO
C3
DDR_DQ10
DDRSS Data
IO
D3
DDR_DQ11
DDRSS Data
IO
B3
DDR_DQ12
DDRSS Data
IO
D4
DDR_DQ13
DDRSS Data
IO
C4
DDR_DQ14
DDRSS Data
IO
B4
DDR_DQ15
DDRSS Data
IO
B5
DDR_DQ16
DDRSS Data
IO
E13
DDR_DQ17
DDRSS Data
IO
C14
DDR_DQ18
DDRSS Data
IO
B14
DDR_DQ19
DDRSS Data
IO
A14
DDR_DQ20
DDRSS Data
IO
E14
DDR_DQ21
DDRSS Data
IO
B13
DDR_DQ22
DDRSS Data
IO
C13
DDR_DQ23
DDRSS Data
IO
D13
DDR_DQ24
DDRSS Data
IO
D15
DDR_DQ25
DDRSS Data
IO
C15
DDR_DQ26
DDRSS Data
IO
E16
DDR_DQ27
DDRSS Data
IO
E15
DDR_DQ28
DDRSS Data
IO
D16
DDR_DQ29
DDRSS Data
IO
B16
DDR_DQ30
DDRSS Data
IO
C16
DDR_DQ31
DDRSS Data
IO
A17
DDR_DQS0N
DDRSS Complimentary Data Strobe
IO
C1
DDR_DQS0P
DDRSS Data Strobe
IO
D1
DDR_DQS1N
DDRSS Complimentary Data Strobe
IO
A4
DDR_DQS1P
DDRSS Data Strobe
IO
A5
DDR_DQS2N
DDRSS Complimentary Data Strobe
IO
A12
DDR_DQS2P
DDRSS Data Strobe
IO
A13
DDR_DQS3N
DDRSS Complimentary Data Strobe
IO
A16
DDR_DQS3P
DDRSS Data Strobe
IO
A15
DDR_ECC_D0
DDRSS ECC Data
IO
B19
DDR_ECC_D1
DDRSS ECC Data
IO
B18
DDR_ECC_D2
DDRSS ECC Data
IO
C18
DDR_ECC_D3
DDRSS ECC Data
IO
D18
DDR_ECC_D4
DDRSS ECC Data
IO
E18
DDR_ECC_D5
DDRSS ECC Data
IO
E17
DDR_ECC_D6
DDRSS ECC Data
IO
D17
DDR_ECC_DM
DDRSS ECC Data Mask
IO
C17
DDR_ECC_DQSN
DDRSS ECC Complimentary Data Strobe
IO
A18
DDR_ECC_DQSP
DDRSS ECC Data Strobe
IO
A19
DDR_FS_RESETn
DDRSS Fail-safe Reset
IO
F16
Terminal Configuration and Functions
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Table 4-8. DDRSS0 Signal Descriptions (continued)
SIGNAL NAME [1]
DESCRIPTION [2]
DDR_RESETn
DDRSS Reset
DDR_VREF0
DDRSS I/O Voltage Reference
DDR_VREF_ZQ
DDRSS I/O Voltage Reference for ZQ calibration
DDR_VTP
DDRSS Calibration Resistor
(1)
(2)
PIN
TYPE [3]
BALL [4]
IO
A11
A
F12
A
F15
A
F13
(1) This pin is intended for observation purpose only. No external voltage should be applied to this pin.
(2) An external 240Ω ±1% resistor must be connected between this pin and VSS. No external voltage should be applied to this pin.
4.3.4.2
DDRSS Mapping
Table 4-9 presents DDRSS interface signal mapping per device memory type.
Table 4-9. DDRSS Signal Mapping
SIGNAL NAME [1]
MEMORY TYPE
ADVANCE INFORMATION
PIN TYPE
[3]
BALL [4]
CA0_A
IO
A10
A1
CA1_A
IO
D9
A2
CA2_A
IO
C9
A3
A3
CA3_A
IO
E9
DDR_AC4
A4
A4
CA4_A
IO
A9
DDR_AC5
A5
A5
CA5_A
IO
E8
DDR_AC6
A6
A6
CA0_B
IO
F8
DDR_AC7
A7
A7
CA1_B
IO
C7
DDR_AC8
A8
A8
CA2_B
IO
C8
DDR_AC9
A9
A9
CA3_B
IO
D7
DDR_AC10
A10
A10
CA4_B
IO
E7
DDR_AC11
A11
A11
CA5_B
IO
A6
DDR_AC12
A12
A12
CS0_B
IO
F7
DDR_AC13
A13
A13
CKE0_B
IO
D6
DDR_AC14
A14
A14/WE_n
CS1_B
IO
C6
DDR_AC15
A15
A15/CAS_n
CKE1_B
IO
F6
DDR_AC16
WE_n
A16/RAS_n
IO
E6
DDR_AC17
CAS_n
A17
IO
E5
DDR_AC18
RAS_n
ACT_n
IO
D8
DDR_AC19
BA0
BA0
IO
D10
DDR_AC20
BA1
BA1
IO
E10
DDR_AC21
BA2
C10
DDR3L(2)
DDR4(2)
LPDDR4(1)
DDR_AC0
A0
A0
DDR_AC1
A1
DDR_AC2
A2
DDR_AC3
BG0
IO
DDR_AC22
BG1
IO
F11
DDR_AC23
PAR
IO
B10
IO
D11
DDR_AC24
CS0_n
CS0_n
DDR_AC25
ODT0
ODT0
DDR_AC26
CKE0
CKE0
DDR_AC27
CS1_n
CS1_n
DDR_AC28
ODT1
ODT1
DDR_AC29
CKE1
CKE1
DDR_ALERTn
CS0_A
IO
B11
CKE0_A
IO
C11
CS1_A
IO
E11
CKE1_A
ALERT_n
IO
E12
IO
D12
IO
D5
DDR_CK0P
CK0
CK0_t
CK_t_A
IO
A8
DDR_CK0N
CK0_n
CK0_c
CK_c_A
IO
B8
64
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Table 4-9. DDRSS Signal Mapping (continued)
MEMORY TYPE
PIN TYPE
[3]
BALL [4]
CK_t_B
IO
A7
CK_c_B
IO
B7
DQ0
DQ0
IO
A3
DQ1
DQ1
DQ1
IO
B2
DQ2
DQ2
DQ2
IO
C2
DDR_DQ3
DQ3
DQ3
DQ3
IO
D2
DDR_DQ4
DQ4
DQ4
DQ4
IO
E2
DDR_DQ5
DQ5
DQ5
DQ5
IO
G1
DDR_DQ6
DQ6
DQ6
DQ6
IO
F2
DDR_DQ7
DQ7
DQ7
DQ7
IO
F1
DDR_DM0
DM0
DM0_n
DMI0
IO
E1
DDR_DQ8
DQ8
DQ8
DQ8
IO
E3
DDR_DQ9
DQ9
DQ9
DQ9
IO
C3
DDR_DQ10
DQ10
DQ10
DQ10
IO
D3
DDR_DQ11
DQ11
DQ11
DQ11
IO
B3
DDR_DQ12
DQ12
DQ12
DQ12
IO
D4
DDR_DQ13
DQ13
DQ13
DQ13
IO
C4
DDR_DQ14
DQ14
DQ14
DQ14
IO
B4
DDR_DQ15
DQ15
DQ15
DQ15
IO
B5
DDR_DM1
DM1
DM1_n
DMI1
IO
C5
DDR_DQ16
DQ16
DQ16
DQ16
IO
E13
DDR_DQ17
DQ17
DQ17
DQ17
IO
C14
DDR_DQ18
DQ18
DQ18
DQ18
IO
B14
DDR_DQ19
DQ19
DQ19
DQ19
IO
A14
DDR_DQ20
DQ20
DQ20
DQ20
IO
E14
DDR_DQ21
DQ21
DQ21
DQ21
IO
B13
DDR_DQ22
DQ22
DQ22
DQ22
IO
C13
DDR_DQ23
DQ23
DQ23
DQ23
IO
D13
DDR_DM2
DM2
DM2_n
DMI2
IO
D14
DDR_DQ24
DQ24
DQ24
DQ24
IO
D15
DDR_DQ25
DQ25
DQ25
DQ25
IO
C15
DDR_DQ26
DQ26
DQ26
DQ26
IO
E16
DDR_DQ27
DQ27
DQ27
DQ27
IO
E15
DDR_DQ28
DQ28
DQ28
DQ28
IO
D16
DDR_DQ29
DQ29
DQ29
DQ29
IO
B16
DDR_DQ30
DQ30
DQ30
DQ30
IO
C16
DDR_DQ31
DQ31
DQ31
DQ31
IO
A17
DDR_DM3
DM3
DM3_n
DMI3
IO
B17
DDR_ECC_D0
DQ32
DQ32
DQ32
IO
B19
DDR_ECC_D1
DQ33
DQ33
DQ33
IO
B18
DDR_ECC_D2
DQ34
DQ34
DQ34
IO
C18
DDR_ECC_D3
DQ35
DQ35
DQ35
IO
D18
DDR_ECC_D4
DQ36
DQ36
DQ36
IO
E18
DDR_ECC_D5
DQ37
DQ37
DQ37
IO
E17
DDR_ECC_D6
DQ38
DQ38
DQ38
IO
D17
DDR_ECC_DM
DM4
DM4_n
DM4
IO
C17
DDR3L(2)
DDR4(2)
LPDDR4(1)
DDR_CK1P
CK1
CK1_t
DDR_CK1N
CK1_n
CK1_c
DDR_DQ0
DQ0
DDR_DQ1
DDR_DQ2
Terminal Configuration and Functions
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Table 4-9. DDRSS Signal Mapping (continued)
SIGNAL NAME [1]
MEMORY TYPE
ADVANCE INFORMATION
PIN TYPE
[3]
BALL [4]
DQS0
IO
D1
DQS0_n
IO
C1
DQS1_t
DQS1
IO
A5
DQS1_n
DQS1_c
DQS1_n
IO
A4
DQS2
DQS2_t
DQS2
IO
A13
DDR_DQS2N
DQS2_n
DQS2_c
DQS2_n
IO
A12
DDR_DQS3P
DQS3
DQS3_t
DQS3
IO
A15
DDR_DQS3N
DQS3_n
DQS3_c
DQS3_n
IO
A16
DDR_ECC_DQSP
DQS4
DQS4_t
DQS4
IO
A19
DDR_ECC_DQSN
DQS4_n
DQS4_c
DQS4_n
IO
A18
DDR_FS_RESETn
FS_RESET_n
FS_RESET_n
FS_RESET_n
IO
F16
DDR_RESETn
RESET_n
RESET_n
RESET_n
IO
A11
DDR_VREF0
VREF0
VREF0
VREF0
A
F12
DDR_VREF_ZQ
VREF_ZQ
VREF_ZQ
VREF_ZQ
A
F15
DDR_VTP
VTP
VTP
VTP
A
F13
DDR3L(2)
DDR4(2)
LPDDR4(1)
DDR_DQS0P
DQS0
DQS0_t
DDR_DQS0N
DQS0_n
DQS0_c
DDR_DQS1P
DQS1
DDR_DQS1N
DDR_DQS2P
(1) This device cannot support two independent channels.
(2) Only single rank is supported for DDR3L and DDR4.
4.3.5
DMTIMER
4.3.5.1
MAIN Domain
Table 4-10. DMTIMER Signal Descriptions
SIGNAL NAME [1]
DESCRIPTION [2]
PIN
TYPE [3]
BALL [4]
TIMER_IO0
Timer Inputs and Outputs (not tied to single timer
instance)
IO
B22
TIMER_IO1
Timer Inputs and Outputs (not tied to single timer
instance)
IO
C23
TIMER_IO2
Timer Inputs and Outputs (not tied to single timer
instance)
IO
P23
TIMER_IO3
Timer Inputs and Outputs (not tied to single timer
instance)
IO
R23
TIMER_IO4
Timer Inputs and Outputs (not tied to single timer
instance)
IO
AG11
TIMER_IO5
Timer Inputs and Outputs (not tied to single timer
instance)
IO
AD11
TIMER_IO6
Timer Inputs and Outputs (not tied to single timer
instance)
IO
T24
TIMER_IO7
Timer Inputs and Outputs (not tied to single timer
instance)
IO
T23
PIN
TYPE [3]
BALL [4]
4.3.5.2
MCU Domain
Table 4-11. DMTIMER Signal Descriptions
SIGNAL NAME [1]
DESCRIPTION [2]
MCU_TIMER_IO0
Timer Inputs and Outputs (not tied to single timer
instance)
IO
N3
MCU_TIMER_IO1
Timer Inputs and Outputs (not tied to single timer
instance)
IO
AB2
66
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4.3.6
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DSS
NOTE
Display Subsystem (DSS) interface is not included on this variant of a pin compatible family
of devices. Refer to Table 3-1, Device Comparison to determine which devices support this
interface.
4.3.6.1
MAIN Domain
Table 4-12. DSS0 Signal Descriptions
(1)
DESCRIPTION [2]
PIN
TYPE [3]
BALL [4]
VOUT1_DE
Video Output Data Enable
O
T23
VOUT1_EXTPCLKIN(1)
Video Output External Pixel Clock Input
I
R25
VOUT1_HSYNC(1)
Video Output Horizontal Sync
O
T24
VOUT1_PCLK(1)
Video Output Pixel Clock Output
O
R24
VOUT1_VSYNC(1)
Video Output Vertical Sync
O
T25
(1)
Video Output Data 0
O
M27
VOUT1_DATA1(1)
Video Output Data 1
O
M23
VOUT1_DATA2(1)
Video Output Data 2
O
M28
VOUT1_DATA3(1)
Video Output Data 3
O
M24
(1)
Video Output Data 4
O
N24
VOUT1_DATA5(1)
Video Output Data 5
O
N27
VOUT1_DATA6(1)
Video Output Data 6
O
N28
(1)
Video Output Data 7
O
M25
VOUT1_DATA8(1)
Video Output Data 8
O
N23
VOUT1_DATA9(1)
Video Output Data 9
O
M26
VOUT1_DATA10(1)
Video Output Data 10
O
P28
VOUT1_DATA11(1)
Video Output Data 11
O
P27
VOUT1_DATA12(1)
Video Output Data 12
O
N26
VOUT1_DATA13(1)
Video Output Data 13
O
N25
(1)
VOUT1_DATA14
Video Output Data 14
O
P24
VOUT1_DATA15(1)
Video Output Data 15
O
R27
VOUT1_DATA16(1)
Video Output Data 16
O
R28
(1)
VOUT1_DATA17
Video Output Data 17
O
P25
VOUT1_DATA18(1)
Video Output Data 18
O
P26
VOUT1_DATA19(1)
Video Output Data 19
O
U28
VOUT1_DATA20(1)
Video Output Data 20
O
T28
VOUT1_DATA21(1)
Video Output Data 21
O
P23
VOUT1_DATA22(1)
Video Output Data 22
O
R26
VOUT1_DATA23(1)
Video Output Data 23
O
R23
VOUT1_DATA0
VOUT1_DATA4
VOUT1_DATA7
Terminal Configuration and Functions
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SIGNAL NAME [1]
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(1) Display Subsystem (DSS) interface is not included on this variant of a pin compatible family of devices. Refer to Table 3-1, Device
Comparison to determine which devices support this interface.
4.3.7
ECAP
4.3.7.1
MAIN Domain
Table 4-13. ECAP0 Signal Descriptions
SIGNAL NAME [1]
DESCRIPTION [2]
Enhanced Capture (ECAP) Input or Auxiliary PWM
(APWM) Ouput
ECAP0_IN_APWM_OUT
4.3.8
PIN
TYPE [3]
BALL [4]
IO
D21
PIN
TYPE [3]
BALL [4]
EHRPWM
4.3.8.1
MAIN Domain
Table 4-14. EHRPWM Signal Descriptions
ADVANCE INFORMATION
SIGNAL NAME [1]
DESCRIPTION [2]
EHRPWM_SOCA
EHRPWM Start of Conversion A
O
AC19
EHRPWM_SOCB
EHRPWM Start of Conversion B
O
AF16
EHRPWM_TZn_IN0
EHRPWM Trip Zone Input 0 (active low)
I
AH17
EHRPWM_TZn_IN1
EHRPWM Trip Zone Input 1 (active low)
I
AC19
EHRPWM_TZn_IN2
EHRPWM Trip Zone Input 2 (active low)
I
AF16
EHRPWM_TZn_IN3
EHRPWM Trip Zone Input 3 (active low)
I
AG14
EHRPWM_TZn_IN4
EHRPWM Trip Zone Input 4 (active low)
I
AE15
EHRPWM_TZn_IN5
EHRPWM Trip Zone Input 5 (active low)
I
AC15
PIN
TYPE [3]
BALL [4]
Table 4-15. EHRPWM0 Signal Descriptions
SIGNAL NAME [1]
DESCRIPTION [2]
EHRPWM0_A
EHRPWM Output A
IO
AG18
EHRPWM0_B
EHRPWM Output B
IO
AG17
EHRPWM0_SYNCI
Sync Input to EHRPWM module from an external pin
I
AF18
EHRPWM0_SYNCO
Sync Output to EHRPWM module to an external pin
O
AE18
PIN
TYPE [3]
BALL [4]
Table 4-16. EHRPWM1 Signal Descriptions
SIGNAL NAME [1]
DESCRIPTION [2]
EHRPWM1_A
EHRPWM Output A
IO
AF17
EHRPWM1_B
EHRPWM Output B
IO
AE17
PIN
TYPE [3]
BALL [4]
Table 4-17. EHRPWM2 Signal Descriptions
SIGNAL NAME [1]
DESCRIPTION [2]
EHRPWM2_A
EHRPWM Output A
IO
AH16
EHRPWM2_B
EHRPWM Output B
IO
AG16
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Table 4-18. EHRPWM3 Signal Descriptions
SIGNAL NAME [1]
DESCRIPTION [2]
PIN
TYPE [3]
BALL [4]
EHRPWM3_A
EHRPWM Output A
IO
AH15
EHRPWM3_B
EHRPWM Output B
IO
AC16
EHRPWM3_SYNCI
Sync Input to EHRPWM module from an external pin
I
AD17
EHRPWM3_SYNCO
Sync Output to EHRPWM module to an external pin
O
AH14
PIN
TYPE [3]
BALL [4]
Table 4-19. EHRPWM4 Signal Descriptions
SIGNAL NAME [1]
DESCRIPTION [2]
EHRPWM4_A
EHRPWM Output A
IO
AG15
EHRPWM4_B
EHRPWM Output B
IO
AC17
PIN
TYPE [3]
BALL [4]
SIGNAL NAME [1]
DESCRIPTION [2]
EHRPWM5_A
EHRPWM Output A
IO
AD15
EHRPWM5_B
EHRPWM Output B
IO
AF14
PIN
TYPE [3]
BALL [4]
4.3.9
ADVANCE INFORMATION
Table 4-20. EHRPWM5 Signal Descriptions
EQEP
4.3.9.1
MAIN Domain
Table 4-21. EQEP0 Signal Descriptions
SIGNAL NAME [1]
DESCRIPTION [2]
EQEP0_A
EQEP Quadrature Input A
I
AB26
EQEP0_B
EQEP Quadrature Input B
I
AA25
EQEP0_I
EQEP Index
IO
AA28
EQEP0_S
EQEP Strobe
IO
U23
PIN
TYPE [3]
BALL [4]
I
AH22
Table 4-22. EQEP1 Signal Descriptions
SIGNAL NAME [1]
DESCRIPTION [2]
EQEP1_A
EQEP Quadrature Input A
EQEP1_B
EQEP Quadrature Input B
I
AE21
EQEP1_I
EQEP Index
IO
AC20
EQEP1_S
EQEP Strobe
IO
AC22
PIN
TYPE [3]
BALL [4]
Table 4-23. EQEP2 Signal Descriptions
SIGNAL NAME [1]
DESCRIPTION [2]
EQEP2_A
EQEP Quadrature Input A
I
D25
EQEP2_B
EQEP Quadrature Input B
I
B26
EQEP2_I
EQEP Index
IO
A24
EQEP2_S
EQEP Strobe
IO
E24
Terminal Configuration and Functions
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4.3.10 GPIO
4.3.10.1 MAIN Domain
Table 4-24. GPIO0 Signal Descriptions
SIGNAL NAME [1]
DESCRIPTION [2]
PIN
TYPE [3]
BALL [4]
ADVANCE INFORMATION
GPIO0_0
General Purpose Input/Output
IO
M27
GPIO0_1
General Purpose Input/Output
IO
M23
GPIO0_2
General Purpose Input/Output
IO
M28
GPIO0_3
General Purpose Input/Output
IO
M24
GPIO0_4
General Purpose Input/Output
IO
N24
GPIO0_5
General Purpose Input/Output
IO
N27
GPIO0_6
General Purpose Input/Output
IO
N28
GPIO0_7
General Purpose Input/Output
IO
M25
GPIO0_8
General Purpose Input/Output
IO
N23
GPIO0_9
General Purpose Input/Output
IO
M26
GPIO0_10
General Purpose Input/Output
IO
P28
GPIO0_11
General Purpose Input/Output
IO
P27
GPIO0_12
General Purpose Input/Output
IO
N26
GPIO0_13
General Purpose Input/Output
IO
N25
GPIO0_14
General Purpose Input/Output
IO
P24
GPIO0_15
General Purpose Input/Output
IO
R27
GPIO0_16
General Purpose Input/Output
IO
R28
GPIO0_17
General Purpose Input/Output
IO
P25
GPIO0_18
General Purpose Input/Output
IO
P26
GPIO0_19
General Purpose Input/Output
IO
U28
GPIO0_20
General Purpose Input/Output
IO
T28
GPIO0_21
General Purpose Input/Output
IO
P23
GPIO0_22
General Purpose Input/Output
IO
R26
GPIO0_23
General Purpose Input/Output
IO
R23
GPIO0_24
General Purpose Input/Output
IO
T25
GPIO0_25
General Purpose Input/Output
IO
T24
GPIO0_26
General Purpose Input/Output
IO
R24
GPIO0_27
General Purpose Input/Output
IO
T23
GPIO0_28
General Purpose Input/Output
IO
R25
GPIO0_29
General Purpose Input/Output
IO
T27
GPIO0_30
General Purpose Input/Output
IO
AF18
GPIO0_31
General Purpose Input/Output
IO
AE18
GPIO0_32
General Purpose Input/Output
IO
AH17
GPIO0_33
General Purpose Input/Output
IO
AG18
GPIO0_34
General Purpose Input/Output
IO
AG17
GPIO0_35
General Purpose Input/Output
IO
AF17
GPIO0_36
General Purpose Input/Output
IO
AE17
GPIO0_37
General Purpose Input/Output
IO
AC19
GPIO0_38
General Purpose Input/Output
IO
AH16
GPIO0_39
General Purpose Input/Output
IO
AG16
GPIO0_40
General Purpose Input/Output
IO
AF16
GPIO0_41
General Purpose Input/Output
IO
AE16
GPIO0_42
General Purpose Input/Output
IO
AD16
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SIGNAL NAME [1]
DESCRIPTION [2]
PIN
TYPE [3]
BALL [4]
GPIO0_43
General Purpose Input/Output
IO
AH15
GPIO0_44
General Purpose Input/Output
IO
AC16
GPIO0_45
General Purpose Input/Output
IO
AD17
GPIO0_46
General Purpose Input/Output
IO
AH14
GPIO0_47
General Purpose Input/Output
IO
AG14
GPIO0_48
General Purpose Input/Output
IO
AG15
GPIO0_49
General Purpose Input/Output
IO
AC17
GPIO0_50
General Purpose Input/Output
IO
AE15
GPIO0_51
General Purpose Input/Output
IO
AD15
GPIO0_52
General Purpose Input/Output
IO
AF14
GPIO0_53
General Purpose Input/Output
IO
AC15
GPIO0_54
General Purpose Input/Output
IO
AD14
GPIO0_55
General Purpose Input/Output
IO
AE14
GPIO0_56
General Purpose Input/Output
IO
AE22
GPIO0_57
General Purpose Input/Output
IO
AG24
GPIO0_58
General Purpose Input/Output
IO
AF23
GPIO0_59
General Purpose Input/Output
IO
AD21
GPIO0_60
General Purpose Input/Output
IO
AG23
GPIO0_61
General Purpose Input/Output
IO
AF27
GPIO0_62
General Purpose Input/Output
IO
AF22
GPIO0_63
General Purpose Input/Output
IO
AG27
GPIO0_64
General Purpose Input/Output
IO
AF28
GPIO0_65
General Purpose Input/Output
IO
AF26
GPIO0_66
General Purpose Input/Output
IO
AH25
GPIO0_67
General Purpose Input/Output
IO
AF21
GPIO0_68
General Purpose Input/Output
IO
AH20
GPIO0_69
General Purpose Input/Output
IO
AH21
GPIO0_70
General Purpose Input/Output
IO
AG20
GPIO0_71
General Purpose Input/Output
IO
AD19
GPIO0_72
General Purpose Input/Output
IO
AD20
GPIO0_73
General Purpose Input/Output
IO
AH26
GPIO0_74
General Purpose Input/Output
IO
AG25
GPIO0_75
General Purpose Input/Output
IO
AG26
GPIO0_76
General Purpose Input/Output
IO
AH24
GPIO0_77
General Purpose Input/Output
IO
AH23
GPIO0_78
General Purpose Input/Output
IO
AG21
GPIO0_79
General Purpose Input/Output
IO
AH22
GPIO0_80
General Purpose Input/Output
IO
AE21
GPIO0_81
General Purpose Input/Output
IO
AC22
GPIO0_82
General Purpose Input/Output
IO
AG22
GPIO0_83
General Purpose Input/Output
IO
AD23
GPIO0_84
General Purpose Input/Output
IO
AE24
GPIO0_85
General Purpose Input/Output
IO
AF25
GPIO0_86
General Purpose Input/Output
IO
AF24
GPIO0_87
General Purpose Input/Output
IO
AC20
GPIO0_88
General Purpose Input/Output
IO
AE20
GPIO0_89
General Purpose Input/Output
IO
AF19
Terminal Configuration and Functions
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Table 4-24. GPIO0 Signal Descriptions (continued)
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Table 4-24. GPIO0 Signal Descriptions (continued)
SIGNAL NAME [1]
PIN
TYPE [3]
DESCRIPTION [2]
BALL [4]
GPIO0_90
General Purpose Input/Output
IO
AH19
GPIO0_91
General Purpose Input/Output
IO
AG19
GPIO0_92
General Purpose Input/Output
IO
AE19
GPIO0_93
General Purpose Input/Output
IO
AE23
GPIO0_94
General Purpose Input/Output
IO
AD22
GPIO0_95
General Purpose Input/Output
IO
AC21
PIN
TYPE [3]
ACD [4]
Table 4-25. GPIO1 Signal Descriptions
SIGNAL NAME [1]
DESCRIPTION [2]
ADVANCE INFORMATION
GPIO1_0
General Purpose Input/Output
IO
AD18
GPIO1_1
General Purpose Input/Output
IO
AH18
GPIO1_2
General Purpose Input/Output
IO
D25
GPIO1_3
General Purpose Input/Output
IO
B26
GPIO1_4
General Purpose Input/Output
IO
A24
GPIO1_5
General Purpose Input/Output
IO
E24
GPIO1_6
General Purpose Input/Output
IO
A25
GPIO1_7
General Purpose Input/Output
IO
C26
GPIO1_8
General Purpose Input/Output
IO
E25
GPIO1_9
General Purpose Input/Output
IO
A26
GPIO1_10
General Purpose Input/Output
O
B25
GPIO1_11
General Purpose Input/Output
IO
B27
GPIO1_12
General Purpose Input/Output
I
C25
GPIO1_13
General Purpose Input/Output
IO(1)
A23
GPIO1_14
General Purpose Input/Output
IO(1)
B23
GPIO1_15
General Purpose Input/Output
IO
AG13
GPIO1_16
General Purpose Input/Output
IO
AF13
GPIO1_17
General Purpose Input/Output
IO
AH13
GPIO1_18
General Purpose Input/Output
IO
AE13
GPIO1_19
General Purpose Input/Output
IO
AD13
GPIO1_20
General Purpose Input/Output
IO
AD12
GPIO1_21
General Purpose Input/Output
IO
AG12
GPIO1_22
General Purpose Input/Output
IO
AH12
GPIO1_23
General Purpose Input/Output
IO
AE12
GPIO1_24
General Purpose Input/Output
IO
AF12
GPIO1_25
General Purpose Input/Output
IO
AF11
GPIO1_26
General Purpose Input/Output
IO
AE11
GPIO1_27
General Purpose Input/Output
IO
AG11
GPIO1_28
General Purpose Input/Output
IO
AD11
GPIO1_29
General Purpose Input/Output
IO
V24
GPIO1_30
General Purpose Input/Output
IO
W25
GPIO1_31
General Purpose Input/Output
IO
W24
GPIO1_32
General Purpose Input/Output
IO
AA27
GPIO1_33
General Purpose Input/Output
IO
Y24
GPIO1_34
General Purpose Input/Output
IO
V28
GPIO1_35
General Purpose Input/Output
IO
Y25
GPIO1_36
General Purpose Input/Output
IO
U27
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SIGNAL NAME [1]
DESCRIPTION [2]
PIN
TYPE [3]
ACD [4]
V27
GPIO1_37
General Purpose Input/Output
IO
GPIO1_38
General Purpose Input/Output
IO
V26
GPIO1_39
General Purpose Input/Output
IO
U25
GPIO1_40
General Purpose Input/Output
IO
AB25
GPIO1_41
General Purpose Input/Output
IO
AD27
GPIO1_42
General Purpose Input/Output
IO
AC26
GPIO1_43
General Purpose Input/Output
IO
AD26
GPIO1_44
General Purpose Input/Output
IO
AA24
GPIO1_45
General Purpose Input/Output
IO
AD28
GPIO1_46
General Purpose Input/Output
IO
U26
GPIO1_47
General Purpose Input/Output
IO
V25
GPIO1_48
General Purpose Input/Output
IO
U24
GPIO1_49
General Purpose Input/Output
IO
AB28
GPIO1_50
General Purpose Input/Output
IO
AC28
GPIO1_51
General Purpose Input/Output
IO
AC27
GPIO1_52
General Purpose Input/Output
IO
AB26
GPIO1_53
General Purpose Input/Output
IO
AA25
GPIO1_54
General Purpose Input/Output
IO
U23
GPIO1_55
General Purpose Input/Output
IO
AB27
GPIO1_56
General Purpose Input/Output
IO
W28
GPIO1_57
General Purpose Input/Output
IO
W27
GPIO1_58
General Purpose Input/Output
IO
Y28
GPIO1_59
General Purpose Input/Output
IO
AA28
GPIO1_60
General Purpose Input/Output
IO
AB24
GPIO1_61
General Purpose Input/Output
IO
AC25
GPIO1_62
General Purpose Input/Output
IO
AD25
GPIO1_63
General Purpose Input/Output
IO
AD24
GPIO1_64
General Purpose Input/Output
IO
AE27
GPIO1_65
General Purpose Input/Output
IO
AC24
GPIO1_66
General Purpose Input/Output
IO
Y27
GPIO1_67
General Purpose Input/Output
IO
Y26
GPIO1_68
General Purpose Input/Output
IO
W26
GPIO1_69
General Purpose Input/Output
IO
AE26
GPIO1_70
General Purpose Input/Output
IO
AE28
GPIO1_71
General Purpose Input/Output
IO
AD9
GPIO1_72
General Purpose Input/Output
IO
AC8
GPIO1_73
General Purpose Input/Output
IO
D27
GPIO1_74
General Purpose Input/Output
IO
D26
GPIO1_75
General Purpose Input/Output
IO
E27
GPIO1_76
General Purpose Input/Output
IO
D28
GPIO1_77
General Purpose Input/Output
O
C27
GPIO1_78
General Purpose Input/Output
IO
C28
GPIO1_79
General Purpose Input/Output
IO(1)
B24
GPIO1_80
General Purpose Input/Output
(1)
C24
GPIO1_86
General Purpose Input/Output
IO
D21
GPIO1_87
General Purpose Input/Output
IO
A22
GPIO1_88
General Purpose Input/Output
IO
B22
IO
Terminal Configuration and Functions
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Table 4-25. GPIO1 Signal Descriptions (continued)
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Table 4-25. GPIO1 Signal Descriptions (continued)
SIGNAL NAME [1]
DESCRIPTION [2]
GPIO1_89
General Purpose Input/Output
PIN
TYPE [3]
ACD [4]
IO
C23
(1) When OSC1 is being used with an external crystal, this pin must only be used as an input. The output functionality must be disabled.
4.3.10.2 WKUP Domain
Table 4-26. GPIO0 Signal Descriptions
SIGNAL NAME [1]
DESCRIPTION [2]
PIN
TYPE [3]
BALL [4]
ADVANCE INFORMATION
WKUP_GPIO0_0
General Purpose Input/Output
IO
AF4
WKUP_GPIO0_1
General Purpose Input/Output
IO
AF3
WKUP_GPIO0_2
General Purpose Input/Output
IO
AE3
WKUP_GPIO0_3
General Purpose Input/Output
IO
AD1
WKUP_GPIO0_4
General Purpose Input/Output
IO
AC3
WKUP_GPIO0_5
General Purpose Input/Output
IO
AD3
WKUP_GPIO0_6
General Purpose Input/Output
IO
AC2
WKUP_GPIO0_7
General Purpose Input/Output
IO
AC1
WKUP_GPIO0_8
General Purpose Input/Output
IO
AC5
WKUP_GPIO0_9
General Purpose Input/Output
IO
AB4
WKUP_GPIO0_10
General Purpose Input/Output
IO
AB3
WKUP_GPIO0_11
General Purpose Input/Output
IO
AB2
WKUP_GPIO0_12
General Purpose Input/Output
IO
V1
WKUP_GPIO0_13
General Purpose Input/Output
IO
U1
WKUP_GPIO0_14
General Purpose Input/Output
IO
U2
WKUP_GPIO0_15
General Purpose Input/Output
IO
U4
WKUP_GPIO0_16
General Purpose Input/Output
IO
U5
WKUP_GPIO0_17
General Purpose Input/Output
IO
T2
WKUP_GPIO0_18
General Purpose Input/Output
IO
T3
WKUP_GPIO0_19
General Purpose Input/Output
IO
T4
WKUP_GPIO0_20
General Purpose Input/Output
IO
T5
WKUP_GPIO0_21
General Purpose Input/Output
IO
R2
WKUP_GPIO0_22
General Purpose Input/Output
IO
R3
WKUP_GPIO0_23
General Purpose Input/Output
IO
R4
WKUP_GPIO0_24
General Purpose Input/Output
IO
R5
WKUP_GPIO0_25
General Purpose Input/Output
IO
T1
WKUP_GPIO0_26
General Purpose Input/Output
IO
R1
WKUP_GPIO0_27
General Purpose Input/Output
IO
P2
WKUP_GPIO0_28
General Purpose Input/Output
IO
P3
WKUP_GPIO0_29
General Purpose Input/Output
IO
P4
WKUP_GPIO0_30
General Purpose Input/Output
IO
P5
WKUP_GPIO0_31
General Purpose Input/Output
IO
P1
WKUP_GPIO0_32
General Purpose Input/Output
IO
N2
WKUP_GPIO0_33
General Purpose Input/Output
IO
N3
WKUP_GPIO0_34
General Purpose Input/Output
IO
N4
WKUP_GPIO0_35
General Purpose Input/Output
IO
N5
WKUP_GPIO0_36
General Purpose Input/Output
IO
M2
WKUP_GPIO0_37
General Purpose Input/Output
IO
M3
WKUP_GPIO0_38
General Purpose Input/Output
IO
M4
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SIGNAL NAME [1]
DESCRIPTION [2]
PIN
TYPE [3]
BALL [4]
M5
WKUP_GPIO0_39
General Purpose Input/Output
IO
WKUP_GPIO0_40
General Purpose Input/Output
IO
N1
WKUP_GPIO0_41
General Purpose Input/Output
IO
M1
WKUP_GPIO0_42
General Purpose Input/Output
IO
L2
WKUP_GPIO0_43
General Purpose Input/Output
IO
L5
WKUP_GPIO0_44
General Purpose Input/Output
IO
M6
WKUP_GPIO0_45
General Purpose Input/Output
IO
L6
WKUP_GPIO0_46
General Purpose Input/Output
IO
L4
WKUP_GPIO0_47
General Purpose Input/Output
IO
L1
WKUP_GPIO0_48
General Purpose Input/Output
IO
Y1
WKUP_GPIO0_49
General Purpose Input/Output
IO
Y3
WKUP_GPIO0_50
General Purpose Input/Output
IO
Y2
WKUP_GPIO0_51
General Purpose Input/Output
IO
Y4
WKUP_GPIO0_52
General Purpose Input/Output
IO
AB1
WKUP_GPIO0_53
General Purpose Input/Output
IO
AB5
WKUP_GPIO0_54
General Purpose Input/Output
IO
W1
WKUP_GPIO0_55
General Purpose Input/Output
IO
W2
PIN
TYPE [3]
BALL [4]
ADVANCE INFORMATION
Table 4-26. GPIO0 Signal Descriptions (continued)
4.3.11 GPMC
4.3.11.1 MAIN Domain
Table 4-27. GPMC0 Signal Descriptions
SIGNAL NAME [1]
DESCRIPTION [2]
GPMC0_ADVn_ALE
GPMC Address Valid (active low) or Address Latch
Enable
O
P25
GPMC0_CLK
GPMC Clock Output
IO
R28
GPMC0_DIR
GPMC Data Bus Signal Direction Control
O
T24
GPMC0_OEn_REn
GPMC Output Enable (active low) or Read Enable (active
low)
O
P26
GPMC0_WEn
GPMC Write Enable (active low)
O
U28
GPMC0_WPn
GPMC Flash Write Protect (active low)
O
T25
GPMC0_A0
GPMC Address 0 Output. Only used to effectively
address 8-bit data non-multiplexed memories
OZ
AE14
GPMC0_A1
GPMC address 1 Output in A/D non-multiplexed mode
and Address 17 in A/D multiplexed mode
OZ
AD14
GPMC0_A2
GPMC address 2 Output in A/D non-multiplexed mode
and Address 18 in A/D multiplexed mode
OZ
AC15
GPMC0_A3
GPMC address 3 Output in A/D non-multiplexed mode
and Address 19 in A/D multiplexed mode
OZ
AF14
GPMC0_A4
GPMC address 4 Output in A/D non-multiplexed mode
and Address 20 in A/D multiplexed mode
OZ
AD15
GPMC0_A5
GPMC address 5 Output in A/D non-multiplexed mode
and Address 21 in A/D multiplexed mode
OZ
AE15
GPMC0_A6
GPMC address 6 Output in A/D non-multiplexed mode
and Address 22 in A/D multiplexed mode
OZ
AC17
GPMC0_A7
GPMC address 7 Output in A/D non-multiplexed mode
and Address 23 in A/D multiplexed mode
OZ
AG15
GPMC0_A8
GPMC address 8 Output in A/D non-multiplexed mode
and Address 24 in A/D multiplexed mode
OZ
AG14
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Table 4-27. GPMC0 Signal Descriptions (continued)
SIGNAL NAME [1]
DESCRIPTION [2]
PIN
TYPE [3]
BALL [4]
ADVANCE INFORMATION
GPMC0_A9
GPMC address 9 Output in A/D non-multiplexed mode
and Address 25 in A/D multiplexed mode
OZ
AH14
GPMC0_A10
GPMC address 10 Output in A/D non-multiplexed mode
and Address 26 in A/D multiplexed mode
OZ
AD17
GPMC0_A11
GPMC address 11 Output in A/D non-multiplexed mode
and unused in A/D multiplexed mode
OZ
AC16
GPMC0_A12
GPMC address 12 Output in A/D non-multiplexed mode
and unused in A/D multiplexed mode
OZ
AH15
GPMC0_A13
GPMC address 13 Output in A/D non-multiplexed mode
and unused in A/D multiplexed mode
OZ
AD16
GPMC0_A14
GPMC address 14 Output in A/D non-multiplexed mode
and unused in A/D multiplexed mode
OZ
AE16
GPMC0_A15
GPMC address 15 Output in A/D non-multiplexed mode
and unused in A/D multiplexed mode
OZ
AF16
GPMC0_A16
GPMC address 16 Output in A/D non-multiplexed mode
and unused in A/D multiplexed mode
OZ
AG16
GPMC0_A17
GPMC address 17 Output in A/D non-multiplexed mode
and unused in A/D multiplexed mode
OZ
AH16
GPMC0_A18
GPMC address 18 Output in A/D non-multiplexed mode
and unused in A/D multiplexed mode
OZ
AC19
GPMC0_A19
GPMC address 19 Output in A/D non-multiplexed mode
and unused in A/D multiplexed mode
OZ
AE17
GPMC0_A20
GPMC address 20 Output in A/D non-multiplexed mode
and unused in A/D multiplexed mode
OZ
AF17
GPMC0_A21
GPMC address 21 Output in A/D non-multiplexed mode
and unused in A/D multiplexed mode
OZ
AG17
GPMC0_A22
GPMC address 22 Output in A/D non-multiplexed mode
and unused in A/D multiplexed mode
OZ
AG18
GPMC0_A23
GPMC address 23 Output in A/D non-multiplexed mode
and unused in A/D multiplexed mode
OZ
AH17
GPMC0_A24
GPMC address 24 Output in A/D non-multiplexed mode
and unused in A/D multiplexed mode
OZ
AE18
GPMC0_A25
GPMC address 25 Output in A/D non-multiplexed mode
and unused in A/D multiplexed mode
OZ
AF18
GPMC0_A26
GPMC address 26 Output in A/D non-multiplexed mode
and unused in A/D multiplexed mode
OZ
T27
GPMC0_A27
GPMC address 27 in A/D non-multiplexed mode and
Address 27 in A/D multiplexed mode
OZ
R25
GPMC0_AD0
GPMC Data 0 Input/Output in A/D non-multiplexed mode
and additionally Address 1 Output in A/D multiplexed
mode
IO
M27
GPMC0_AD1
GPMC Data 1 Input/Output in A/D non-multiplexed mode
and additionally Address 2 Output in A/D multiplexed
mode
IO
M23
GPMC0_AD2
GPMC Data 2 Input/Output in A/D non-multiplexed mode
and additionally Address 3 Output in A/D multiplexed
mode
IO
M28
GPMC0_AD3
GPMC Data 3 Input/Output in A/D non-multiplexed mode
and additionally Address 4 Output in A/D multiplexed
mode
IO
M24
GPMC0_AD4
GPMC Data 4 Input/Output in A/D non-multiplexed mode
and additionally Address 5 Output in A/D multiplexed
mode
IO
N24
GPMC0_AD5
GPMC Data 5 Input/Output in A/D non-multiplexed mode
and additionally Address 6 Output in A/D multiplexed
mode
IO
N27
76
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DESCRIPTION [2]
PIN
TYPE [3]
BALL [4]
GPMC0_AD6
GPMC Data 6 Input/Output in A/D non-multiplexed mode
and additionally Address 7 Output in A/D multiplexed
mode
IO
N28
GPMC0_AD7
GPMC Data 7 Input/Output in A/D non-multiplexed mode
and additionally Address 8 Output in A/D multiplexed
mode
IO
M25
GPMC0_AD8
GPMC Data 8 Input/Output in A/D non-multiplexed mode
and additionally Address 9 Output in A/D multiplexed
mode
IO
N23
GPMC0_AD9
GPMC Data 9 Input/Output in A/D non-multiplexed mode
and additionally Address 10 Output in A/D multiplexed
mode
IO
M26
GPMC0_AD10
GPMC Data 10 Input/Output in A/D non-multiplexed
mode and additionally Address 11 Output in A/D
multiplexed mode
IO
P28
GPMC0_AD11
GPMC Data 11 Input/Output in A/D non-multiplexed
mode and additionally Address 12 Output in A/D
multiplexed mode
IO
P27
GPMC0_AD12
GPMC Data 12 Input/Output in A/D non-multiplexed
mode and additionally Address 13 Output in A/D
multiplexed mode
IO
N26
GPMC0_AD13
GPMC Data 13 Input/Output in A/D non-multiplexed
mode and additionally Address 14 Output in A/D
multiplexed mode
IO
N25
GPMC0_AD14
GPMC Data 14 Input/Output in A/D non-multiplexed
mode and additionally Address 15 Output in A/D
multiplexed mode
IO
P24
GPMC0_AD15
GPMC Data 15 Input/Output in A/D non-multiplexed
mode and additionally Address 16 Output in A/D
multiplexed mode
IO
R27
GPMC0_BE0n_CLE
GPMC Lower-Byte Enable (active low) or Command
Latch Enable
O
T28
GPMC0_BE1n
GPMC Upper-Byte Enable (active low)
O
P23
GPMC0_CSn0
GPMC Chip Select 0 (active low)
O
R24
GPMC0_CSn1
GPMC Chip Select 1 (active low)
O
T23
GPMC0_CSn2
GPMC Chip Select 2 (active low)
O
R25
GPMC0_CSn3
GPMC Chip Select 3 (active low)
O
T27
GPMC0_WAIT0
GPMC External Indication of Wait
I
R26
GPMC0_WAIT1
GPMC External Indication of Wait
I
R23
PIN
TYPE [3]
BALL [4]
SIGNAL NAME [1]
ADVANCE INFORMATION
Table 4-27. GPMC0 Signal Descriptions (continued)
4.3.12 HYPERBUS
4.3.12.1 MCU Domain
Table 4-28. HYPERBUS0 Signal Descriptions
SIGNAL NAME [1]
DESCRIPTION [2]
MCU_HYPERBUS0_CK
Hyperbus Differential Clock (positive)
O
V1
MCU_HYPERBUS0_CKn
Hyperbus Differential Clock (negative)
O
U1
MCU_HYPERBUS0_INTn
Hyperbus Interrupt (active low)
I
P2
MCU_HYPERBUS0_RESETn
Hyperbus Reset (active low) Output
O
R5
MCU_HYPERBUS0_RESETOn
Hyperbus Reset Status Indicator (active low) from
Hyperbus Memory
I
R1
MCU_HYPERBUS0_RWDS
Hyperbus Read-Write Data Strobe
IO
U2
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Table 4-28. HYPERBUS0 Signal Descriptions (continued)
SIGNAL NAME [1]
DESCRIPTION [2]
PIN
TYPE [3]
BALL [4]
MCU_HYPERBUS0_WPn
Hyperbus Write Protect (Not in use)
O
N3
MCU_HYPERBUS0_CSn0
Hyperbus Chip Select 0
O
R4
MCU_HYPERBUS0_CSn1
Hyperbus Chip Select 1
O
N3
MCU_HYPERBUS0_DQ0
Hyperbus Data 0
IO
U4
MCU_HYPERBUS0_DQ1
Hyperbus Data 1
IO
U5
MCU_HYPERBUS0_DQ2
Hyperbus Data 2
IO
T2
MCU_HYPERBUS0_DQ3
Hyperbus Data 3
IO
T3
MCU_HYPERBUS0_DQ4
Hyperbus Data 4
IO
T4
MCU_HYPERBUS0_DQ5
Hyperbus Data 5
IO
T5
MCU_HYPERBUS0_DQ6
Hyperbus Data 6
IO
R2
MCU_HYPERBUS0_DQ7
Hyperbus Data 7
IO
R3
PIN
TYPE [3]
BALL [4]
4.3.13 I2C
ADVANCE INFORMATION
4.3.13.1 MAIN Domain
Table 4-29. I2C0 Signal Descriptions
SIGNAL NAME [1]
DESCRIPTION [2]
I2C0_SCL
I2C Clock
IOD
D20
I2C0_SDA
I2C Data
IOD
C21
PIN
TYPE [3]
BALL [4]
Table 4-30. I2C1 Signal Descriptions
SIGNAL NAME [1]
DESCRIPTION [2]
I2C1_SCL
I2C Clock
IOD
B21
I2C1_SDA
I2C Data
IOD
E21
PIN
TYPE [3]
BALL [4]
Table 4-31. I2C2 Signal Descriptions
SIGNAL NAME [1]
DESCRIPTION [2]
I2C2_SCL
I2C Clock
IOD
T27
I2C2_SDA
I2C Data
IOD
R25
PIN
TYPE [3]
BALL [4]
Table 4-32. I2C3 Signal Descriptions
SIGNAL NAME [1]
DESCRIPTION [2]
I2C3_SCL
I2C Clock
IOD
AF13
I2C3_SDA
I2C Data
IOD
AG12
PIN
TYPE [3]
BALL [4]
4.3.13.2 MCU Domain
Table 4-33. I2C0 Signal Descriptions
SIGNAL NAME [1]
DESCRIPTION [2]
MCU_I2C0_SCL
I2C Clock
IOD
AD8
MCU_I2C0_SDA
I2C Data
IOD
AD7
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4.3.13.3 WKUP Domain
Table 4-34. I2C0 Signal Descriptions
SIGNAL NAME [1]
DESCRIPTION [2]
PIN
TYPE [3]
BALL [4]
WKUP_I2C0_SCL
I2C Clock
IOD
AC7
WKUP_I2C0_SDA
I2C Data
IOD
AD6
PIN
TYPE [3]
BALL [4]
4.3.14 MCAN
4.3.14.1 MCU Domain
SIGNAL NAME [1]
DESCRIPTION [2]
MCU_MCAN0_RX
MCAN Receive Data
I
W2
MCU_MCAN0_TX
MCAN Transmit Data
O
W1
PIN
TYPE [3]
BALL [4]
ADVANCE INFORMATION
Table 4-35. MCAN0 Signal Descriptions
Table 4-36. MCAN1 Signal Descriptions
SIGNAL NAME [1]
DESCRIPTION [2]
MCU_MCAN1_RX
MCAN Receive Data
I
AD3
MCU_MCAN1_TX
MCAN Transmit Data
O
AC3
PIN
TYPE [3]
BALL [4]
W24
4.3.15 MCASP
4.3.15.1 MAIN Domain
Table 4-37. MCASP0 Signal Descriptions
SIGNAL NAME [1]
DESCRIPTION [2]
MCASP0_ACLKR
MCASP Receive Bit Clock
IO
MCASP0_ACLKX
MCASP Transmit Bit Clock
IO
V24
MCASP0_AFSR
MCASP Receive Frame Sync
IO
AA27
MCASP0_AFSX
MCASP Transmit Frame Sync
IO
W25
MCASP0_AHCLKR
MCASP Receive Master Clock
IO
AA25
MCASP0_AHCLKX
MCASP Transmit Master Clock
IO
U23
MCASP0_AXR0
MCASP Serial Data (Input/Output)
IO
Y24
MCASP0_AXR1
MCASP Serial Data (Input/Output)
IO
V28
MCASP0_AXR2
MCASP Serial Data (Input/Output)
IO
Y25
MCASP0_AXR3
MCASP Serial Data (Input/Output)
IO
U27
MCASP0_AXR4
MCASP Serial Data (Input/Output)
IO
V27
MCASP0_AXR5
MCASP Serial Data (Input/Output)
IO
V26
MCASP0_AXR6
MCASP Serial Data (Input/Output)
IO
U25
MCASP0_AXR7
MCASP Serial Data (Input/Output)
IO
AB25
MCASP0_AXR8
MCASP Serial Data (Input/Output)
IO
AD27
MCASP0_AXR9
MCASP Serial Data (Input/Output)
IO
AC26
MCASP0_AXR10
MCASP Serial Data (Input/Output)
IO
AD26
MCASP0_AXR11
MCASP Serial Data (Input/Output)
IO
AA24
MCASP0_AXR12
MCASP Serial Data (Input/Output)
IO
AD28
MCASP0_AXR13
MCASP Serial Data (Input/Output)
IO
U26
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Table 4-37. MCASP0 Signal Descriptions (continued)
SIGNAL NAME [1]
PIN
TYPE [3]
DESCRIPTION [2]
BALL [4]
MCASP0_AXR14
MCASP Serial Data (Input/Output)
IO
V25
MCASP0_AXR15
MCASP Serial Data (Input/Output)
IO
U24
PIN
TYPE [3]
BALL [4]
Table 4-38. MCASP1 Signal Descriptions
SIGNAL NAME [1]
DESCRIPTION [2]
ADVANCE INFORMATION
MCASP1_ACLKR
MCASP Receive Bit Clock
IO
AC27
MCASP1_ACLKX
MCASP Transmit Bit Clock
IO
AB28
MCASP1_AFSR
MCASP Receive Frame Sync
IO
AB26
MCASP1_AFSX
MCASP Transmit Frame Sync
IO
AC28
MCASP1_AHCLKR
MCASP Receive Master Clock
IO
AD28
MCASP1_AHCLKX
MCASP Transmit Master Clock
IO
U26
MCASP1_AXR0
MCASP Serial Data (Input/Output)
IO
AA25
MCASP1_AXR1
MCASP Serial Data (Input/Output)
IO
U23
MCASP1_AXR2
MCASP Serial Data (Input/Output)
IO
AB27
MCASP1_AXR3
MCASP Serial Data (Input/Output)
IO
W28
MCASP1_AXR4
MCASP Serial Data (Input/Output)
IO
W27
MCASP1_AXR5
MCASP Serial Data (Input/Output)
IO
Y28
MCASP1_AXR6
MCASP Serial Data (Input/Output)
IO
AA28
MCASP1_AXR7
MCASP Serial Data (Input/Output)
IO
AB24
MCASP1_AXR8
MCASP Serial Data (Input/Output)
IO
AC25
MCASP1_AXR9
MCASP Serial Data (Input/Output)
IO
AD25
PIN
TYPE [3]
BALL [4]
AE27
Table 4-39. MCASP2 Signal Descriptions
SIGNAL NAME [1]
DESCRIPTION [2]
MCASP2_ACLKR
MCASP Receive Bit Clock
IO
MCASP2_ACLKX
MCASP Transmit Bit Clock
IO
W26
MCASP2_AFSR
MCASP Receive Frame Sync
IO
AD24
MCASP2_AFSX
MCASP Transmit Frame Sync
IO
Y26
MCASP2_AHCLKR
MCASP Receive Master Clock
IO
V25
MCASP2_AHCLKX
MCASP Transmit Master Clock
IO
U24
MCASP2_AXR0
MCASP Serial Data (Input/Output)
IO
AC24
MCASP2_AXR1
MCASP Serial Data (Input/Output)
IO
Y27
MCASP2_AXR2
MCASP Serial Data (Input/Output)
IO
AE26
MCASP2_AXR3
MCASP Serial Data (Input/Output)
IO
AE28
PIN
TYPE [3]
BALL [4]
4.3.16 MCSPI
4.3.16.1 MAIN Domain
Table 4-40. MCSPI0 Signal Descriptions
SIGNAL NAME [1]
DESCRIPTION [2]
SPI0_CLK
SPI Clock
IO
AH13
SPI0_CS0
SPI Chip Select 0
IO
AG13
SPI0_CS1
SPI Chip Select 1
IO
AF13
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Table 4-40. MCSPI0 Signal Descriptions (continued)
SIGNAL NAME [1]
DESCRIPTION [2]
PIN
TYPE [3]
BALL [4]
SPI0_CS2
SPI Chip Select 2
IO
AG11
SPI0_CS3
SPI Chip Select 3
IO
AD11
SPI0_D0
SPI Data 0
IO
AE13
SPI0_D1
SPI Data 1
IO
AD13
PIN
TYPE [3]
BALL [4]
SIGNAL NAME [1]
DESCRIPTION [2]
SPI1_CLK
SPI Clock
IO
AH12
SPI1_CS0
SPI Chip Select 0
IO
AD12
SPI1_CS1
SPI Chip Select 1
IO
AG12
SPI1_CS2
SPI Chip Select 2
IO
AD18
SPI1_CS3
SPI Chip Select 3
IO
AH18
SPI1_D0
SPI Data 0
IO
AE12
SPI1_D1
SPI Data 1
IO
AF12
PIN
TYPE [3]
BALL [4]
ADVANCE INFORMATION
Table 4-41. MCSPI1 Signal Descriptions
Table 4-42. MCSPI2 Signal Descriptions
SIGNAL NAME [1]
DESCRIPTION [2]
SPI2_CLK
SPI Clock
IO
AE23
SPI2_CS0
SPI Chip Select 0
IO
AD23
SPI2_CS1
SPI Chip Select 1
IO
AF26
SPI2_CS2
SPI Chip Select 2
IO
AH25
SPI2_CS3
SPI Chip Select 3
IO
AF24
SPI2_D0
SPI Data 0
IO
AD22
SPI2_D1
SPI Data 1
IO
AC21
PIN
TYPE [3]
BALL [4]
Table 4-43. MCSPI3 Signal Descriptions
SIGNAL NAME [1]
DESCRIPTION [2]
SPI3_CLK
SPI Clock
IO
Y27
SPI3_CS0
SPI Chip Select 0
IO
W28
SPI3_CS1
SPI Chip Select 1
IO
V26
SPI3_CS2
SPI Chip Select 2
IO
U25
SPI3_CS3
SPI Chip Select 3
IO
Y28
SPI3_D0
SPI Data 0
IO
Y26
SPI3_D1
SPI Data 1
IO
W26
PIN
TYPE [3]
BALL [4]
4.3.16.2 MCU Domain
Table 4-44. MCSPI0 Signal Descriptions
SIGNAL NAME [1]
DESCRIPTION [2]
MCU_SPI0_CLK
SPI Clock
IO
Y1
MCU_SPI0_CS0
SPI Chip Select 0
IO
Y4
MCU_SPI0_CS1
SPI Chip Select 1
IO
P1
MCU_SPI0_CS2
SPI Chip Select 2
IO
N3
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Table 4-44. MCSPI0 Signal Descriptions (continued)
SIGNAL NAME [1]
DESCRIPTION [2]
PIN
TYPE [3]
BALL [4]
MCU_SPI0_CS3
SPI Chip Select 3
IO
AC3
MCU_SPI0_D0
SPI Data 0
IO
Y3
MCU_SPI0_D1
SPI Data 1
IO
Y2
PIN
TYPE [3]
BALL [4]
Table 4-45. MCSPI1 Signal Descriptions
SIGNAL NAME [1]
DESCRIPTION [2]
ADVANCE INFORMATION
MCU_SPI1_CLK
SPI Clock
IO
AF4
MCU_SPI1_CS0
SPI Chip Select 0
IO
AD1
MCU_SPI1_CS1
SPI Chip Select 1
IO
P4
MCU_SPI1_CS2
SPI Chip Select 2
IO
P5
MCU_SPI1_CS3
SPI Chip Select 3
IO
AD3
MCU_SPI1_D0
SPI Data 0
IO
AF3
MCU_SPI1_D1
SPI Data 1
IO
AE3
PIN
TYPE [3]
BALL [4]
4.3.17 MMC
4.3.17.1 MAIN Domain
Table 4-46. MMC0 Signal Descriptions
SIGNAL NAME [1]
(1)
DESCRIPTION [2]
MMC0_CALPAD
MMC/SD Calibration Resistor
A
D24
MMC0_CLK(2)(3)
MMC/SD Clock
O
B25
MMC/SD Command
MMC0_CMD
(2)
IO
B27
MMC0_DS
MMC Data Strobe
I
C25
MMC0_SDCD
SD Card Detect
I
A23
MMC0_SDWP
SD Write Protect
I
B23
MMC0_DAT0(2)
MMC/SD Data
IO
A26
MMC0_DAT1(2)
MMC/SD Data
IO
E25
(2)
MMC0_DAT2
MMC/SD Data
IO
C26
MMC0_DAT3(2)
MMC/SD Data
IO
A25
MMC0_DAT4(2)
MMC/SD Data
IO
E24
MMC0_DAT5(2)
MMC/SD Data
IO
A24
(2)
MMC0_DAT6
MMC/SD Data
IO
B26
MMC0_DAT7(2)
MMC/SD Data
IO
D25
(1) An external 10kΩ ±1% resistor must be connected between this pin and VSS. No external voltage should be applied to this pin.
(2) When MMCSD0 or MMCSD1 is used, any non-MMC signal function multiplexed with the respective pins are not available. This is due to
the MMC having an internal IO multiplexer which is controlled by MMCSD0/1_SS_PHY_CTRL_1_REG[31] IOMUX_ENABLE. This
internal IO multiplexer is primary for the signal functions associated with MMCSD pins, and the PADCONFIG’s MUXMODE is
secondary. Additionally, the internal IO multiplexer affects all of the MMCSD0 or MMCSD1 pins, regardless of configured data bus width.
Therefore, when MMCSD0/1_SS_PHY_CTRL_1_REG[31] IOMUX_ENABLE = 0, the respective MMCSD pins are configured for
eMMC/SD functionality, regardless of the PADCONFIG [MUXMODE] setting.
(3) This output signal is also used as a retiming input. It is also recommended to place a 33 Ω resistor in series (close to the processor) to
avoid signal reflections.
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Table 4-47. MMC1 Signal Descriptions
SIGNAL NAME [1]
(1)
PIN
TYPE [3]
DESCRIPTION [2]
BALL [4]
MMC1_CALPAD
MMC/SD Calibration Resistor
A
F23
MMC1_CLK(2)(3)
MMC/SD Clock
O
C27
MMC1_CMD(2)
MMC/SD Command
IO
C28
MMC1_SDCD
SD Card Detect
I
B24
MMC1_SDWP
SD Write Protect
I
C24
MMC1_DAT0(2)
MMC/SD Data
IO
D28
MMC1_DAT1(2)
MMC/SD Data
IO
E27
MMC1_DAT2(2)
MMC/SD Data
IO
D26
MMC1_DAT3(2)
MMC/SD Data
IO
D27
(2) When MMCSD0 or MMCSD1 is used, any non-MMC signal function multiplexed with the respective pins are not available. This is due to
the MMC having an internal IO multiplexer which is controlled by MMCSD0/1_SS_PHY_CTRL_1_REG[31] IOMUX_ENABLE. This
internal IO multiplexer is primary for the signal functions associated with MMCSD pins, and the PADCONFIG’s MUXMODE is
secondary. Additionally, the internal IO multiplexer affects all of the MMCSD0 or MMCSD1 pins, regardless of configured data bus width.
Therefore, when MMCSD0/1_SS_PHY_CTRL_1_REG[31] IOMUX_ENABLE = 0, the respective MMCSD pins are configured for
eMMC/SD functionality, regardless of the PADCONFIG [MUXMODE] setting.
(3) This output signal is also used as a retiming input. It is also recommended to place a 33 Ω resistor in series (close to the processor) to
avoid signal reflections.
4.3.18 CPTS
4.3.18.1 MAIN Domain
Table 4-48. CPTS0 Signal Descriptions
SIGNAL NAME [1]
PIN
TYPE [3]
DESCRIPTION [2]
BALL [4]
CPTS0_RFT_CLK
CPTS Reference Clock
I
D21
CPTS0_TS_COMP
CPTS Time Stamp Counter Compare
O
AF13
CPTS0_TS_SYNC
CPTS Time Stamp Counter Bit
O
AG12
CPTS0_HW1TSPUSH
CPTS Hardware Time Stamp Push 1
I
B21
CPTS0_HW2TSPUSH
CPTS Hardware Time Stamp Push 2
I
E21
PIN
TYPE [3]
BALL [4]
4.3.19 OLDI
4.3.19.1 MAIN Domain
Table 4-49. OLDI0 Signal Descriptions
SIGNAL NAME [1]
DESCRIPTION [2]
OLDI0_CLKN
OLDI Differential Clock (negative)
IO
L25
OLDI0_CLKP
OLDI Differential Clock (positive)
IO
K25
OLDI0_A0N
OLDI Differential Data (negative)
IO
J28
OLDI0_A0P
OLDI Differential Data (positive)
IO
K28
OLDI0_A1N
OLDI Differential Data (negative)
IO
L27
OLDI0_A1P
OLDI Differential Data (positive)
IO
K27
OLDI0_A2N
OLDI Differential Data (negative)
IO
K24
OLDI0_A2P
OLDI Differential Data (positive)
IO
J24
OLDI0_A3N
OLDI Differential Data (negative)
IO
J26
OLDI0_A3P
OLDI Differential Data (positive)
IO
K26
Terminal Configuration and Functions
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83
ADVANCE INFORMATION
(1) An external 10kΩ ±1% resistor must be connected between this pin and VSS. No external voltage should be applied to this pin.
DRA80M
SPRSP31E – APRIL 2018 – REVISED JUNE 2019
www.ti.com
4.3.20 OSPI
4.3.20.1 MCU Domain
Table 4-50. OSPI0 Signal Descriptions
SIGNAL NAME [1]
DESCRIPTION [2]
PIN
TYPE [3]
BALL [4]
O
V1
ADVANCE INFORMATION
MCU_OSPI0_CLK
OSPI Clock
MCU_OSPI0_DQS
OSPI Data Strobe (DQS) or Loopback Clock Input
I
U2
MCU_OSPI0_LBCLKO
OSPI Loopback Clock Output
IO
U1
MCU_OSPI0_CSn0
OSPI Chip Select 0 (active low)
O
R4
MCU_OSPI0_CSn1
OSPI Chip Select 1 (active low)
O
R5
MCU_OSPI0_CSn2
OSPI Chip Select 2 (active low)
O
R1
MCU_OSPI0_CSn3
OSPI Chip Select 3 (active low)
O
P2
MCU_OSPI0_D0
OSPI Data 0
IO
U4
MCU_OSPI0_D1
OSPI Data 1
IO
U5
MCU_OSPI0_D2
OSPI Data 2
IO
T2
MCU_OSPI0_D3
OSPI Data 3
IO
T3
MCU_OSPI0_D4
OSPI Data 4
IO
T4
MCU_OSPI0_D5
OSPI Data 5
IO
T5
MCU_OSPI0_D6
OSPI Data 6
IO
R2
MCU_OSPI0_D7
OSPI Data 7
IO
R3
PIN
TYPE [3]
BALL [4]
Table 4-51. OSPI1 Signal Descriptions
SIGNAL NAME [1]
DESCRIPTION [2]
MCU_OSPI1_CLK
OSPI Clock
O
T1
MCU_OSPI1_DQS
OSPI Data Strobe (DQS) or Loopback Clock Input
I
P2
MCU_OSPI1_LBCLKO
OSPI Loopback Clock Output
IO
R1
MCU_OSPI1_CSn0
OSPI Chip Select 0 (active low)
O
N2
MCU_OSPI1_CSn1
OSPI Chip Select 1 (active low)
O
N3
MCU_OSPI1_D0
OSPI Data 0
IO
P3
MCU_OSPI1_D1
OSPI Data 1
IO
P4
MCU_OSPI1_D2
OSPI Data 2
IO
P5
MCU_OSPI1_D3
OSPI Data 3
IO
P1
84
Terminal Configuration and Functions
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SPRSP31E – APRIL 2018 – REVISED JUNE 2019
4.3.21 PRU_ICSSG
4.3.21.1 MAIN Domain
NOTE
The PRU_ICSSG contains a second layer of multiplexing to enable additional functionality on
the PRU GPO and GPI signals. This internal wrapper multiplexing is described in the
PRU_ICSSG chapter in the device TRM.
SIGNAL NAME [1]
DESCRIPTION [2]
PRG0_ECAP0_IN_APWM_OUT
PRU_ICSSG Enhanced Capture (ECAP) Input or
Auxiliary PWM (APWM) Ouput
(1)
PIN
TYPE [3]
BALL [4]
IO
V25
U27
PRG0_ECAP0_SYNC_IN (1)
PRU_ICSSG ECAP Sync Input
I
PRG0_ECAP0_SYNC_OUT (1)
PRU_ICSSG ECAP Sync Output
O
U26
PRG0_IEP0_EDIO_OUTVALID
(1)
PRU_ICSSG Industrial Ethernet Digital I/O Outvalid
O
AD12
PRG0_IEP0_EDC_LATCH_IN0
(1)
PRU_ICSSG Industrial Ethernet Distributed Clock Latch
Input
I
V25
PRG0_IEP0_EDC_LATCH_IN1
(1)
PRU_ICSSG Industrial Ethernet Distributed Clock Latch
Input
I
U27
PRG0_IEP0_EDC_SYNC_OUT0
(1)
PRU_ICSSG Industrial Ethernet Distributed Clock Sync
Output
O
U24
PRG0_IEP0_EDC_SYNC_OUT1
(1)
PRU_ICSSG Industrial Ethernet Distributed Clock Sync
Output
O
U26
PRG0_IEP0_EDIO_DATA_IN_OUT28
(1)
PRU_ICSSG Industrial Ethernet Digital I/O Data
Input/Output
IO
V26
PRG0_IEP0_EDIO_DATA_IN_OUT29
(1)
PRU_ICSSG Industrial Ethernet Digital I/O Data
Input/Output
IO
U25
PRG0_IEP0_EDIO_DATA_IN_OUT30
(1)
PRU_ICSSG Industrial Ethernet Digital I/O Data
Input/Output
IO
Y28
PRG0_IEP0_EDIO_DATA_IN_OUT31
(1)
PRU_ICSSG Industrial Ethernet Digital I/O Data
Input/Output
IO
AA28
PRG0_IEP1_EDC_LATCH_IN0
(1)
PRU_ICSSG Industrial Ethernet Distributed Clock Latch
Input
I
Y26
PRG0_IEP1_EDC_LATCH_IN1
(1)
PRU_ICSSG Industrial Ethernet Distributed Clock Latch
Input
I
W28
PRG0_IEP1_EDC_SYNC_OUT0
(1)
PRU_ICSSG Industrial Ethernet Distributed Clock Sync
Output
O
W26
PRG0_IEP1_EDC_SYNC_OUT1
(1)
PRU_ICSSG Industrial Ethernet Distributed Clock Sync
Output
O
Y27
PRG0_MDIO0_MDC
PRU_ICSSG MDIO Clock
O
AE28
PRG0_MDIO0_MDIO
PRU_ICSSG MDIO Data
IO
AE26
PRG0_PRU0_GPI0 (1)
PRU_ICSSG PRU Data Input
I
V24
PRG0_PRU0_GPI1 (1)
PRU_ICSSG PRU Data Input
I
W25
PRG0_PRU0_GPI2 (1)
PRU_ICSSG PRU Data Input
I
W24
PRG0_PRU0_GPI3 (1)
PRU_ICSSG PRU Data Input
I
AA27
PRG0_PRU0_GPI4 (1)
PRU_ICSSG PRU Data Input
I
Y24
PRG0_PRU0_GPI5 (1)
PRU_ICSSG PRU Data Input
I
V28
(1)
PRU_ICSSG PRU Data Input
I
Y25
PRG0_PRU0_GPI7 (1)
PRU_ICSSG PRU Data Input
I
U27
PRG0_PRU0_GPI8 (1)
PRU_ICSSG PRU Data Input
I
V27
(1)
PRU_ICSSG PRU Data Input
I
V26
PRG0_PRU0_GPI6
PRG0_PRU0_GPI9
Terminal Configuration and Functions
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Table 4-52. PRU_ICSSG0 Signal Descriptions
85
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SPRSP31E – APRIL 2018 – REVISED JUNE 2019
www.ti.com
Table 4-52. PRU_ICSSG0 Signal Descriptions (continued)
SIGNAL NAME [1]
DESCRIPTION [2]
PIN
TYPE [3]
BALL [4]
PRG0_PRU0_GPI10
(1)
PRU_ICSSG PRU Data Input
I
U25
PRG0_PRU0_GPI11
(1)
PRU_ICSSG PRU Data Input
I
AB25
PRG0_PRU0_GPI12
(1)
PRU_ICSSG PRU Data Input
I
AD27
PRG0_PRU0_GPI13
(1)
PRU_ICSSG PRU Data Input
I
AC26
PRG0_PRU0_GPI14
(1)
PRU_ICSSG PRU Data Input
I
AD26
PRG0_PRU0_GPI15
(1)
PRU_ICSSG PRU Data Input
I
AA24
PRG0_PRU0_GPI16
(1)
PRU_ICSSG PRU Data Input
I
AD28
PRG0_PRU0_GPI17
(1)
PRU_ICSSG PRU Data Input
I
U26
PRG0_PRU0_GPI18
(1)
PRU_ICSSG PRU Data Input
I
V25
PRG0_PRU0_GPI19
(1)
PRU_ICSSG PRU Data Input
I
U24
ADVANCE INFORMATION
PRG0_PRU0_GPO0 (1)
PRU_ICSSG PRU Data Output
IO
V24
PRG0_PRU0_GPO1 (1)
PRU_ICSSG PRU Data Output
IO
W25
PRG0_PRU0_GPO2 (1)
PRU_ICSSG PRU Data Output
IO
W24
(1)
PRU_ICSSG PRU Data Output
IO
AA27
PRG0_PRU0_GPO4 (1)
PRU_ICSSG PRU Data Output
IO
Y24
PRG0_PRU0_GPO5 (1)
PRU_ICSSG PRU Data Output
IO
V28
PRG0_PRU0_GPO6 (1)
PRU_ICSSG PRU Data Output
IO
Y25
(1)
PRU_ICSSG PRU Data Output
IO
U27
PRG0_PRU0_GPO8 (1)
PRU_ICSSG PRU Data Output
IO
V27
PRG0_PRU0_GPO9 (1)
PRU_ICSSG PRU Data Output
IO
V26
PRG0_PRU0_GPO10
(1)
PRU_ICSSG PRU Data Output
IO
U25
PRG0_PRU0_GPO11
(1)
PRU_ICSSG PRU Data Output
IO
AB25
PRG0_PRU0_GPO12
(1)
PRU_ICSSG PRU Data Output
IO
AD27
PRG0_PRU0_GPO13
(1)
PRU_ICSSG PRU Data Output
IO
AC26
PRG0_PRU0_GPO14
(1)
PRU_ICSSG PRU Data Output
IO
AD26
PRG0_PRU0_GPO15
(1)
PRU_ICSSG PRU Data Output
IO
AA24
PRG0_PRU0_GPO16
(1)
PRU_ICSSG PRU Data Output
IO
AD28
PRG0_PRU0_GPO17
(1)
PRU_ICSSG PRU Data Output
IO
U26
PRG0_PRU0_GPO18
(1)
PRU_ICSSG PRU Data Output
IO
V25
PRG0_PRU0_GPO19
(1)
PRU_ICSSG PRU Data Output
IO
U24
PRG0_PRU0_GPO3
PRG0_PRU0_GPO7
PRG0_PRU1_GPI0 (1)
PRU_ICSSG PRU Data Input
I
AB28
PRG0_PRU1_GPI1 (1)
PRU_ICSSG PRU Data Input
I
AC28
PRG0_PRU1_GPI2 (1)
PRU_ICSSG PRU Data Input
I
AC27
(1)
PRU_ICSSG PRU Data Input
I
AB26
PRG0_PRU1_GPI4 (1)
PRU_ICSSG PRU Data Input
I
AA25
PRG0_PRU1_GPI5 (1)
PRU_ICSSG PRU Data Input
I
U23
PRG0_PRU1_GPI6 (1)
PRU_ICSSG PRU Data Input
I
AB27
PRG0_PRU1_GPI7 (1)
PRU_ICSSG PRU Data Input
I
W28
PRG0_PRU1_GPI8 (1)
PRU_ICSSG PRU Data Input
I
W27
PRG0_PRU1_GPI9 (1)
PRU_ICSSG PRU Data Input
I
Y28
PRG0_PRU1_GPI10
(1)
PRU_ICSSG PRU Data Input
I
AA28
PRG0_PRU1_GPI11
(1)
PRU_ICSSG PRU Data Input
I
AB24
PRG0_PRU1_GPI12
(1)
PRU_ICSSG PRU Data Input
I
AC25
PRG0_PRU1_GPI13
(1)
PRU_ICSSG PRU Data Input
I
AD25
PRG0_PRU1_GPI14
(1)
PRU_ICSSG PRU Data Input
I
AD24
PRG0_PRU1_GPI15
(1)
PRU_ICSSG PRU Data Input
I
AE27
PRG0_PRU1_GPI16
(1)
PRU_ICSSG PRU Data Input
I
AC24
PRG0_PRU1_GPI3
86
Terminal Configuration and Functions
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SPRSP31E – APRIL 2018 – REVISED JUNE 2019
SIGNAL NAME [1]
DESCRIPTION [2]
PIN
TYPE [3]
BALL [4]
Y27
PRG0_PRU1_GPI17
(1)
PRU_ICSSG PRU Data Input
I
PRG0_PRU1_GPI18
(1)
PRU_ICSSG PRU Data Input
I
Y26
PRG0_PRU1_GPI19
(1)
PRU_ICSSG PRU Data Input
I
W26
PRG0_PRU1_GPO0 (1)
PRU_ICSSG PRU Data Output
IO
AB28
PRG0_PRU1_GPO1 (1)
PRU_ICSSG PRU Data Output
IO
AC28
PRG0_PRU1_GPO2 (1)
PRU_ICSSG PRU Data Output
IO
AC27
PRG0_PRU1_GPO3 (1)
PRU_ICSSG PRU Data Output
IO
AB26
(1)
PRU_ICSSG PRU Data Output
IO
AA25
PRG0_PRU1_GPO5 (1)
PRU_ICSSG PRU Data Output
IO
U23
PRG0_PRU1_GPO6 (1)
PRU_ICSSG PRU Data Output
IO
AB27
PRG0_PRU1_GPO7 (1)
PRU_ICSSG PRU Data Output
IO
W28
PRG0_PRU1_GPO8 (1)
PRU_ICSSG PRU Data Output
IO
W27
PRG0_PRU1_GPO9 (1)
PRU_ICSSG PRU Data Output
IO
Y28
PRG0_PRU1_GPO10
(1)
PRU_ICSSG PRU Data Output
IO
AA28
PRG0_PRU1_GPO11
(1)
PRU_ICSSG PRU Data Output
IO
AB24
PRG0_PRU1_GPO12
(1)
PRU_ICSSG PRU Data Output
IO
AC25
PRG0_PRU1_GPO13
(1)
PRU_ICSSG PRU Data Output
IO
AD25
PRG0_PRU1_GPO14
(1)
PRU_ICSSG PRU Data Output
IO
AD24
PRG0_PRU1_GPO15
(1)
PRU_ICSSG PRU Data Output
IO
AE27
PRG0_PRU1_GPO16
(1)
PRU_ICSSG PRU Data Output
IO
AC24
PRG0_PRU1_GPO17
(1)
PRU_ICSSG PRU Data Output
IO
Y27
PRG0_PRU1_GPO18
(1)
PRU_ICSSG PRU Data Output
IO
Y26
PRG0_PRU1_GPO19
(1)
PRU_ICSSG PRU Data Output
IO
W26
PRG0_PRU1_GPO4
PRG0_PWM0_TZ_IN
(1)
PRG0_PWM0_TZ_OUT
PRG0_PWM1_TZ_IN
(1)
PRG0_PWM1_TZ_OUT
PRG0_PWM2_TZ_IN
(1)
(1)
PRG0_PWM2_TZ_OUT
PRG0_PWM3_TZ_IN
(1)
(1)
(1)
PRG0_PWM3_TZ_OUT
(1)
PRU_ICSSG PWM Trip Zone Input
I
V25
PRU_ICSSG PWM Trip Zone Output
O
U24
PRU_ICSSG PWM Trip Zone Input
I
Y26
PRU_ICSSG PWM Trip Zone Output
O
W26
PRU_ICSSG PWM Trip Zone Input
I
AA28
PRU_ICSSG PWM Trip Zone Output
O
W27
PRU_ICSSG PWM Trip Zone Input
I
V26
PRU_ICSSG PWM Trip Zone Output
O
AB25
PRG0_PWM0_A0 (1)
PRU_ICSSG PWM Output A
IO
AD27
PRG0_PWM0_A1 (1)
PRU_ICSSG PWM Output A
IO
AD26
(1)
PRU_ICSSG PWM Output A
IO
AD28
PRG0_PWM0_B0 (1)
PRU_ICSSG PWM Output B
IO
AC26
PRG0_PWM0_B1 (1)
PRU_ICSSG PWM Output B
IO
AA24
PRG0_PWM0_B2 (1)
PRU_ICSSG PWM Output B
IO
U26
(1)
PRU_ICSSG PWM Output A
IO
AC25
PRG0_PWM1_A1 (1)
PRU_ICSSG PWM Output A
IO
AD24
PRG0_PWM1_A2 (1)
PRU_ICSSG PWM Output A
IO
AC24
(1)
PRU_ICSSG PWM Output B
IO
AD25
PRG0_PWM1_B1 (1)
PRU_ICSSG PWM Output B
IO
AE27
PRG0_PWM1_B2 (1)
PRU_ICSSG PWM Output B
IO
Y27
(1)
PRU_ICSSG PWM Output A
IO
W24
PRG0_PWM2_A1 (1)
PRU_ICSSG PWM Output A
IO
V27
PRG0_PWM2_A2 (1)
PRU_ICSSG PWM Output A
IO
AC27
PRG0_PWM2_B0 (1)
PRU_ICSSG PWM Output B
IO
Y24
PRG0_PWM0_A2
PRG0_PWM1_A0
PRG0_PWM1_B0
PRG0_PWM2_A0
Terminal Configuration and Functions
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ADVANCE INFORMATION
Table 4-52. PRU_ICSSG0 Signal Descriptions (continued)
87
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SPRSP31E – APRIL 2018 – REVISED JUNE 2019
www.ti.com
Table 4-52. PRU_ICSSG0 Signal Descriptions (continued)
SIGNAL NAME [1]
PIN
TYPE [3]
DESCRIPTION [2]
BALL [4]
PRG0_PWM2_B1 (1)
PRU_ICSSG PWM Output B
IO
U25
PRG0_PWM2_B2 (1)
PRU_ICSSG PWM Output B
IO
AA25
PRG0_PWM3_A0 (1)
PRU_ICSSG PWM Output A
IO
V24
(1)
PRU_ICSSG PWM Output A
IO
Y25
PRG0_PWM3_A2 (1)
PRU_ICSSG PWM Output A
IO
AA27
PRG0_PWM3_B0 (1)
PRU_ICSSG PWM Output B
IO
W25
PRG0_PWM3_B1 (1)
PRU_ICSSG PWM Output B
IO
U27
(1)
PRU_ICSSG PWM Output B
PRG0_PWM3_A1
PRG0_PWM3_B2
ADVANCE INFORMATION
IO
V28
PRG0_RGMII1_RXC
PRU_ICSSG RGMII Receive Clock
I
Y25
PRG0_RGMII1_RX_CTL
PRU_ICSSG RGMII Receive Control
I
Y24
PRG0_RGMII1_TXC
PRU_ICSSG RGMII Transmit Clock
IO
AD28
PRG0_RGMII1_TX_CTL
PRU_ICSSG RGMII Transmit Control
O
AB25
PRG0_RGMII2_RXC
PRU_ICSSG RGMII Receive Clock
I
AB27
PRG0_RGMII2_RX_CTL
PRU_ICSSG RGMII Receive Control
I
AA25
PRG0_RGMII2_TXC
PRU_ICSSG RGMII Transmit Clock
IO
AC24
PRG0_RGMII2_TX_CTL
PRU_ICSSG RGMII Transmit Control
O
AB24
PRG0_RGMII1_RD0
PRU_ICSSG RGMII Receive Data
I
V24
PRG0_RGMII1_RD1
PRU_ICSSG RGMII Receive Data
I
W25
PRG0_RGMII1_RD2
PRU_ICSSG RGMII Receive Data
I
W24
PRG0_RGMII1_RD3
PRU_ICSSG RGMII Receive Data
I
AA27
PRG0_RGMII1_TD0
PRU_ICSSG RGMII Transmit Data
O
AD27
PRG0_RGMII1_TD1
PRU_ICSSG RGMII Transmit Data
O
AC26
PRG0_RGMII1_TD2
PRU_ICSSG RGMII Transmit Data
O
AD26
PRG0_RGMII1_TD3
PRU_ICSSG RGMII Transmit Data
O
AA24
PRG0_RGMII2_RD0
PRU_ICSSG RGMII Receive Data
I
AB28
PRG0_RGMII2_RD1
PRU_ICSSG RGMII Receive Data
I
AC28
PRG0_RGMII2_RD2
PRU_ICSSG RGMII Receive Data
I
AC27
PRG0_RGMII2_RD3
PRU_ICSSG RGMII Receive Data
I
AB26
PRG0_RGMII2_TD0
PRU_ICSSG RGMII Transmit Data
O
AC25
PRG0_RGMII2_TD1
PRU_ICSSG RGMII Transmit Data
O
AD25
PRG0_RGMII2_TD2
PRU_ICSSG RGMII Transmit Data
O
AD24
PRG0_RGMII2_TD3
PRU_ICSSG RGMII Transmit Data
O
AE27
PRG0_UART0_CTSn (1)
PRU_ICSSG UART Clear to Send (active low)
I
V26
PRU_ICSSG UART Request to Send (active low)
O
U25
PRU_ICSSG UART Receive Data
I
Y28
PRU_ICSSG UART Transmit Data
O
AA28
PRG0_UART0_RTSn
(1)
PRG0_UART0_RXD (1)
PRG0_UART0_TXD
(1)
(1) ICSS does not support these signals on this SoC. Signals are retained for consistency with the pin compatible family of devices.
Table 4-53. PRU_ICSSG1 Signal Descriptions
SIGNAL NAME [1]
DESCRIPTION [2]
PRG1_ECAP0_IN_APWM_OUT
(1)
PRU_ICSSG Enhanced Capture (ECAP) Input or
Auxiliary PWM (APWM) Ouput
PIN
TYPE [3]
BALL [4]
IO
AC21
PRG1_ECAP0_SYNC_IN (1)
PRU_ICSSG ECAP Sync Input
I
AD22
PRG1_ECAP0_SYNC_OUT (1)
PRU_ICSSG ECAP Sync Output
O
AE23
PRU_ICSSG Industrial Ethernet Digital I/O Outvalid
O
AF13
PRG1_IEP0_EDIO_OUTVALID
88
(1)
Terminal Configuration and Functions
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SPRSP31E – APRIL 2018 – REVISED JUNE 2019
SIGNAL NAME [1]
DESCRIPTION [2]
PIN
TYPE [3]
BALL [4]
PRG1_IEP0_EDC_LATCH_IN0
(1)
PRU_ICSSG Industrial Ethernet Distributed Clock Latch
Input
I
AG25
PRG1_IEP0_EDC_LATCH_IN1
(1)
PRU_ICSSG Industrial Ethernet Distributed Clock Latch
Input
I
AG27
PRG1_IEP0_EDC_SYNC_OUT0
(1)
PRU_ICSSG Industrial Ethernet Distributed Clock Sync
Output
O
AG26
PRG1_IEP0_EDC_SYNC_OUT1
(1)
PRU_ICSSG Industrial Ethernet Distributed Clock Sync
Output
O
AH26
PRG1_IEP0_EDIO_DATA_IN_OUT28
(1)
PRU_ICSSG Industrial Ethernet Digital I/O Data
Input/Output
IO
AF26
PRG1_IEP0_EDIO_DATA_IN_OUT29
(1)
PRU_ICSSG Industrial Ethernet Digital I/O Data
Input/Output
IO
AH25
PRG1_IEP0_EDIO_DATA_IN_OUT30
(1)
PRU_ICSSG Industrial Ethernet Digital I/O Data
Input/Output
IO
AF25
PRG1_IEP0_EDIO_DATA_IN_OUT31
(1)
PRU_ICSSG Industrial Ethernet Digital I/O Data
Input/Output
IO
AF24
PRG1_IEP1_EDC_LATCH_IN0
(1)
PRU_ICSSG Industrial Ethernet Distributed Clock Latch
Input
I
AD22
PRG1_IEP1_EDC_LATCH_IN1
(1)
PRU_ICSSG Industrial Ethernet Distributed Clock Latch
Input
I
AD23
PRG1_IEP1_EDC_SYNC_OUT0
(1)
PRU_ICSSG Industrial Ethernet Distributed Clock Sync
Output
O
AC21
PRG1_IEP1_EDC_SYNC_OUT1
(1)
PRU_ICSSG Industrial Ethernet Distributed Clock Sync
Output
O
AE23
PRG1_MDIO0_MDC
PRU_ICSSG MDIO Clock
O
AH18
PRG1_MDIO0_MDIO
PRU_ICSSG MDIO Data
IO
AD18
PRG1_PRU0_GPI0 (1)
PRU_ICSSG PRU Data Input
I
AE22
PRG1_PRU0_GPI1 (1)
PRU_ICSSG PRU Data Input
I
AG24
PRG1_PRU0_GPI2 (1)
PRU_ICSSG PRU Data Input
I
AF23
(1)
PRU_ICSSG PRU Data Input
I
AD21
PRG1_PRU0_GPI4 (1)
PRU_ICSSG PRU Data Input
I
AG23
PRG1_PRU0_GPI5 (1)
PRU_ICSSG PRU Data Input
I
AF27
(1)
PRU_ICSSG PRU Data Input
I
AF22
PRG1_PRU0_GPI7 (1)
PRU_ICSSG PRU Data Input
I
AG27
PRG1_PRU0_GPI8 (1)
PRU_ICSSG PRU Data Input
I
AF28
(1)
PRG1_PRU0_GPI3
PRG1_PRU0_GPI6
PRG1_PRU0_GPI9
PRU_ICSSG PRU Data Input
I
AF26
PRG1_PRU0_GPI10
(1)
PRU_ICSSG PRU Data Input
I
AH25
PRG1_PRU0_GPI11
(1)
PRU_ICSSG PRU Data Input
I
AF21
PRG1_PRU0_GPI12
(1)
PRU_ICSSG PRU Data Input
I
AH20
PRG1_PRU0_GPI13
(1)
PRU_ICSSG PRU Data Input
I
AH21
PRG1_PRU0_GPI14
(1)
PRU_ICSSG PRU Data Input
I
AG20
PRG1_PRU0_GPI15
(1)
PRU_ICSSG PRU Data Input
I
AD19
PRG1_PRU0_GPI16
(1)
PRU_ICSSG PRU Data Input
I
AD20
PRG1_PRU0_GPI17
(1)
PRU_ICSSG PRU Data Input
I
AH26
PRG1_PRU0_GPI18
(1)
PRU_ICSSG PRU Data Input
I
AG25
PRG1_PRU0_GPI19
(1)
PRU_ICSSG PRU Data Input
I
AG26
PRG1_PRU0_GPO0
(1)
PRU_ICSSG PRU Data Output
IO
AE22
PRG1_PRU0_GPO1 (1)
PRU_ICSSG PRU Data Output
IO
AG24
PRG1_PRU0_GPO2 (1)
PRU_ICSSG PRU Data Output
IO
AF23
(1)
PRU_ICSSG PRU Data Output
IO
AD21
PRG1_PRU0_GPO3
Terminal Configuration and Functions
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Table 4-53. PRU_ICSSG1 Signal Descriptions (continued)
89
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SPRSP31E – APRIL 2018 – REVISED JUNE 2019
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Table 4-53. PRU_ICSSG1 Signal Descriptions (continued)
SIGNAL NAME [1]
DESCRIPTION [2]
PIN
TYPE [3]
BALL [4]
PRG1_PRU0_GPO4 (1)
PRU_ICSSG PRU Data Output
IO
AG23
PRG1_PRU0_GPO5 (1)
PRU_ICSSG PRU Data Output
IO
AF27
PRG1_PRU0_GPO6 (1)
PRU_ICSSG PRU Data Output
IO
AF22
(1)
PRU_ICSSG PRU Data Output
IO
AG27
PRG1_PRU0_GPO8 (1)
PRU_ICSSG PRU Data Output
IO
AF28
PRG1_PRU0_GPO9 (1)
PRU_ICSSG PRU Data Output
IO
AF26
AH25
PRG1_PRU0_GPO7
ADVANCE INFORMATION
PRG1_PRU0_GPO10
(1)
PRU_ICSSG PRU Data Output
IO
PRG1_PRU0_GPO11
(1)
PRU_ICSSG PRU Data Output
IO
AF21
PRG1_PRU0_GPO12
(1)
PRU_ICSSG PRU Data Output
IO
AH20
PRG1_PRU0_GPO13
(1)
PRU_ICSSG PRU Data Output
IO
AH21
PRG1_PRU0_GPO14
(1)
PRU_ICSSG PRU Data Output
IO
AG20
PRG1_PRU0_GPO15
(1)
PRU_ICSSG PRU Data Output
IO
AD19
PRG1_PRU0_GPO16
(1)
PRU_ICSSG PRU Data Output
IO
AD20
PRG1_PRU0_GPO17
(1)
PRU_ICSSG PRU Data Output
IO
AH26
PRG1_PRU0_GPO18
(1)
PRU_ICSSG PRU Data Output
IO
AG25
PRG1_PRU0_GPO19
(1)
PRU_ICSSG PRU Data Output
IO
AG26
PRG1_PRU1_GPI0 (1)
PRU_ICSSG PRU Data Input
I
AH24
(1)
PRU_ICSSG PRU Data Input
I
AH23
PRG1_PRU1_GPI2 (1)
PRU_ICSSG PRU Data Input
I
AG21
PRG1_PRU1_GPI3 (1)
PRU_ICSSG PRU Data Input
I
AH22
(1)
PRU_ICSSG PRU Data Input
I
AE21
PRG1_PRU1_GPI5 (1)
PRU_ICSSG PRU Data Input
I
AC22
PRG1_PRU1_GPI6 (1)
PRU_ICSSG PRU Data Input
I
AG22
(1)
PRU_ICSSG PRU Data Input
I
AD23
PRG1_PRU1_GPI8 (1)
PRU_ICSSG PRU Data Input
I
AE24
PRG1_PRU1_GPI9 (1)
PRU_ICSSG PRU Data Input
I
AF25
PRG1_PRU1_GPI1
PRG1_PRU1_GPI4
PRG1_PRU1_GPI7
PRG1_PRU1_GPI10
(1)
PRU_ICSSG PRU Data Input
I
AF24
PRG1_PRU1_GPI11
(1)
PRU_ICSSG PRU Data Input
I
AC20
PRG1_PRU1_GPI12
(1)
PRU_ICSSG PRU Data Input
I
AE20
PRG1_PRU1_GPI13
(1)
PRU_ICSSG PRU Data Input
I
AF19
PRG1_PRU1_GPI14
(1)
PRU_ICSSG PRU Data Input
I
AH19
PRG1_PRU1_GPI15
(1)
PRU_ICSSG PRU Data Input
I
AG19
PRG1_PRU1_GPI16
(1)
PRU_ICSSG PRU Data Input
I
AE19
PRG1_PRU1_GPI17
(1)
PRU_ICSSG PRU Data Input
I
AE23
PRG1_PRU1_GPI18
(1)
PRU_ICSSG PRU Data Input
I
AD22
PRG1_PRU1_GPI19
(1)
PRU_ICSSG PRU Data Input
I
AC21
PRG1_PRU1_GPO0 (1)
PRU_ICSSG PRU Data Output
IO
AH24
(1)
PRU_ICSSG PRU Data Output
IO
AH23
PRG1_PRU1_GPO2 (1)
PRU_ICSSG PRU Data Output
IO
AG21
PRG1_PRU1_GPO3 (1)
PRU_ICSSG PRU Data Output
IO
AH22
(1)
PRU_ICSSG PRU Data Output
IO
AE21
PRG1_PRU1_GPO5 (1)
PRU_ICSSG PRU Data Output
IO
AC22
PRG1_PRU1_GPO6 (1)
PRU_ICSSG PRU Data Output
IO
AG22
(1)
PRU_ICSSG PRU Data Output
IO
AD23
PRG1_PRU1_GPO8 (1)
PRU_ICSSG PRU Data Output
IO
AE24
PRG1_PRU1_GPO9 (1)
PRU_ICSSG PRU Data Output
IO
AF25
PRU_ICSSG PRU Data Output
IO
AF24
PRG1_PRU1_GPO1
PRG1_PRU1_GPO4
PRG1_PRU1_GPO7
PRG1_PRU1_GPO10
90
(1)
Terminal Configuration and Functions
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DRA80M
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SPRSP31E – APRIL 2018 – REVISED JUNE 2019
SIGNAL NAME [1]
DESCRIPTION [2]
PIN
TYPE [3]
BALL [4]
PRG1_PRU1_GPO11
(1)
PRU_ICSSG PRU Data Output
IO
AC20
PRG1_PRU1_GPO12
(1)
PRU_ICSSG PRU Data Output
IO
AE20
PRG1_PRU1_GPO13
(1)
PRU_ICSSG PRU Data Output
IO
AF19
PRG1_PRU1_GPO14
(1)
PRU_ICSSG PRU Data Output
IO
AH19
PRG1_PRU1_GPO15
(1)
PRU_ICSSG PRU Data Output
IO
AG19
PRG1_PRU1_GPO16
(1)
PRU_ICSSG PRU Data Output
IO
AE19
PRG1_PRU1_GPO17
(1)
PRU_ICSSG PRU Data Output
IO
AE23
PRG1_PRU1_GPO18
(1)
PRU_ICSSG PRU Data Output
IO
AD22
PRG1_PRU1_GPO19
(1)
PRU_ICSSG PRU Data Output
IO
AC21
PRU_ICSSG PWM Trip Zone Input
I
AG25
PRU_ICSSG PWM Trip Zone Output
O
AG26
PRU_ICSSG PWM Trip Zone Input
I
AD22
PRU_ICSSG PWM Trip Zone Output
O
AC21
PRG1_PWM0_TZ_IN
(1)
PRG1_PWM0_TZ_OUT
PRG1_PWM1_TZ_IN
PRG1_PWM1_TZ_OUT
PRG1_PWM2_TZ_IN
(1)
(1)
(1)
(1)
PRU_ICSSG PWM Trip Zone Input
I
AF24
PRU_ICSSG PWM Trip Zone Output
O
AE24
PRU_ICSSG PWM Trip Zone Input
I
AF26
PRU_ICSSG PWM Trip Zone Output
O
AF21
(1)
PRU_ICSSG PWM Output A
IO
AH20
PRG1_PWM0_A1 (1)
PRU_ICSSG PWM Output A
IO
AG20
PRG1_PWM0_A2 (1)
PRU_ICSSG PWM Output A
IO
AD20
(1)
PRU_ICSSG PWM Output B
IO
AH21
PRG1_PWM0_B1 (1)
PRU_ICSSG PWM Output B
IO
AD19
PRG1_PWM0_B2 (1)
PRU_ICSSG PWM Output B
IO
AH26
(1)
PRU_ICSSG PWM Output A
IO
AE20
PRG1_PWM1_A1 (1)
PRU_ICSSG PWM Output A
IO
AH19
PRG1_PWM1_A2 (1)
PRU_ICSSG PWM Output A
IO
AE19
PRG1_PWM1_B0 (1)
PRU_ICSSG PWM Output B
IO
AF19
(1)
PRU_ICSSG PWM Output B
IO
AG19
PRG1_PWM1_B2 (1)
PRU_ICSSG PWM Output B
IO
AE23
PRG1_PWM2_A0 (1)
PRU_ICSSG PWM Output A
IO
AF23
(1)
PRU_ICSSG PWM Output A
IO
AF28
PRG1_PWM2_A2 (1)
PRU_ICSSG PWM Output A
IO
AG21
PRG1_PWM2_B0 (1)
PRU_ICSSG PWM Output B
IO
AG23
(1)
PRU_ICSSG PWM Output B
IO
AH25
PRG1_PWM2_B2 (1)
PRU_ICSSG PWM Output B
IO
AE21
PRG1_PWM3_A0 (1)
PRU_ICSSG PWM Output A
IO
AE22
PRG1_PWM3_A1 (1)
PRU_ICSSG PWM Output A
IO
AF22
(1)
PRU_ICSSG PWM Output A
IO
AD21
PRG1_PWM3_B0 (1)
PRU_ICSSG PWM Output B
IO
AG24
PRG1_PWM3_B1 (1)
PRU_ICSSG PWM Output B
IO
AG27
(1)
PRU_ICSSG PWM Output B
IO
AF27
PRG1_PWM2_TZ_OUT
PRG1_PWM3_TZ_IN
(1)
PRG1_PWM3_TZ_OUT
PRG1_PWM0_A0
PRG1_PWM0_B0
PRG1_PWM1_A0
PRG1_PWM1_B1
PRG1_PWM2_A1
PRG1_PWM2_B1
PRG1_PWM3_A2
PRG1_PWM3_B2
(1)
(1)
PRG1_RGMII1_RXC
PRU_ICSSG RGMII Receive Clock
I
AF22
PRG1_RGMII1_RX_CTL
PRU_ICSSG RGMII Receive Control
I
AG23
PRG1_RGMII1_TXC
PRU_ICSSG RGMII Transmit Clock
IO
AD20
PRG1_RGMII1_TX_CTL
PRU_ICSSG RGMII Transmit Control
O
AF21
PRG1_RGMII2_RXC
PRU_ICSSG RGMII Receive Clock
I
AG22
PRG1_RGMII2_RX_CTL
PRU_ICSSG RGMII Receive Control
I
AE21
Terminal Configuration and Functions
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ADVANCE INFORMATION
Table 4-53. PRU_ICSSG1 Signal Descriptions (continued)
91
DRA80M
SPRSP31E – APRIL 2018 – REVISED JUNE 2019
www.ti.com
Table 4-53. PRU_ICSSG1 Signal Descriptions (continued)
SIGNAL NAME [1]
PIN
TYPE [3]
DESCRIPTION [2]
BALL [4]
ADVANCE INFORMATION
PRG1_RGMII2_TXC
PRU_ICSSG RGMII Transmit Clock
IO
AE19
PRG1_RGMII2_TX_CTL
PRU_ICSSG RGMII Transmit Control
O
AC20
PRG1_RGMII1_RD0
PRU_ICSSG RGMII Receive Data
I
AE22
PRG1_RGMII1_RD1
PRU_ICSSG RGMII Receive Data
I
AG24
PRG1_RGMII1_RD2
PRU_ICSSG RGMII Receive Data
I
AF23
PRG1_RGMII1_RD3
PRU_ICSSG RGMII Receive Data
I
AD21
PRG1_RGMII1_TD0
PRU_ICSSG RGMII Transmit Data
O
AH20
PRG1_RGMII1_TD1
PRU_ICSSG RGMII Transmit Data
O
AH21
PRG1_RGMII1_TD2
PRU_ICSSG RGMII Transmit Data
O
AG20
PRG1_RGMII1_TD3
PRU_ICSSG RGMII Transmit Data
O
AD19
PRG1_RGMII2_RD0
PRU_ICSSG RGMII Receive Data
I
AH24
PRG1_RGMII2_RD1
PRU_ICSSG RGMII Receive Data
I
AH23
PRG1_RGMII2_RD2
PRU_ICSSG RGMII Receive Data
I
AG21
PRG1_RGMII2_RD3
PRU_ICSSG RGMII Receive Data
I
AH22
PRG1_RGMII2_TD0
PRU_ICSSG RGMII Transmit Data
O
AE20
PRG1_RGMII2_TD1
PRU_ICSSG RGMII Transmit Data
O
AF19
PRG1_RGMII2_TD2
PRU_ICSSG RGMII Transmit Data
O
AH19
PRG1_RGMII2_TD3
PRU_ICSSG RGMII Transmit Data
O
AG19
PRG1_UART0_CTSn (1)
PRU_ICSSG UART Clear to Send (active low)
I
AF26
PRG1_UART0_RTSn (1)
PRU_ICSSG UART Request to Send (active low)
O
AH25
PRG1_UART0_RXD (1)
PRU_ICSSG UART Receive Data
I
AF25
PRU_ICSSG UART Transmit Data
O
AF24
PRG1_UART0_TXD
(1)
(1) ICSS does not support these signals on this SoC. Signals are retained for consistency with the pin compatible family of devices.
Table 4-54. PRU_ICSSG2 Signal Descriptions
SIGNAL NAME [1]
DESCRIPTION [2]
PRG2_ECAP0_IN_APWM_OUT
PRU_ICSSG Enhanced Capture (ECAP) Input or
Auxiliary PWM (APWM) Ouput
(2)
PRG2_ECAP0_SYNC_IN (2)
PRG2_ECAP0_SYNC_OUT
PRU_ICSSG ECAP Sync Input
(2)
PRU_ICSSG ECAP Sync Output
BALL [4]
IO
AE16
I
AD14
O
AG14
O(1)
A23
(2)
PRU_ICSSG Industrial Ethernet Distributed Clock Latch
Input
I
AD12
(2)
PRU_ICSSG Industrial Ethernet Distributed Clock Latch
Input
I
AE12
(2)
PRU_ICSSG Industrial Ethernet Digital I/O Outvalid
PRG2_IEP0_EDC_LATCH_IN0
PRG2_IEP0_EDC_LATCH_IN1
PRG2_IEP0_EDIO_OUTVALID
PIN
TYPE [3]
PRG2_IEP0_EDC_SYNC_OUT0
(2)
PRU_ICSSG Industrial Ethernet Distributed Clock Sync
Output
O
AH12
PRG2_IEP0_EDC_SYNC_OUT1
(2)
PRU_ICSSG Industrial Ethernet Distributed Clock Sync
Output
O
AF12
PRG2_IEP0_EDIO_DATA_IN_OUT28
(2)
PRU_ICSSG Industrial Ethernet Digital I/O Data
Input/Output
IO
R23
PRG2_IEP0_EDIO_DATA_IN_OUT29
(2)
PRU_ICSSG Industrial Ethernet Digital I/O Data
Input/Output
IO
T24
PRG2_IEP0_EDIO_DATA_IN_OUT30
(2)
PRU_ICSSG Industrial Ethernet Digital I/O Data
Input/Output
IO
R25
PRG2_IEP0_EDIO_DATA_IN_OUT31
(2)
PRU_ICSSG Industrial Ethernet Digital I/O Data
Input/Output
IO
T27
I
R23
PRG2_IEP1_EDC_LATCH_IN0
92
(2)
PRU_ICSSG Industrial Ethernet Distributed Clock Latch
Input
Terminal Configuration and Functions
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PIN
TYPE [3]
BALL [4]
PRU_ICSSG Industrial Ethernet Distributed Clock Latch
Input
I
R25
SIGNAL NAME [1]
PRG2_IEP1_EDC_LATCH_IN1
DESCRIPTION [2]
(2)
PRG2_IEP1_EDC_SYNC_OUT0
(2)
PRU_ICSSG Industrial Ethernet Distributed Clock Sync
Output
O
T24
PRG2_IEP1_EDC_SYNC_OUT1
(2)
PRU_ICSSG Industrial Ethernet Distributed Clock Sync
Output
O
T27
PRG2_MDIO0_MDC
PRU_ICSSG MDIO Clock
O
AE15
PRG2_MDIO0_MDIO
PRU_ICSSG MDIO Data
IO
AC19
PRG2_PRU0_GPI0 (2)
PRU_ICSSG PRU Data Input
I
AF18
PRG2_PRU0_GPI1 (2)
PRU_ICSSG PRU Data Input
I
AE18
PRG2_PRU0_GPI2 (2)
PRU_ICSSG PRU Data Input
I
AH17
PRG2_PRU0_GPI3 (2)
PRU_ICSSG PRU Data Input
I
AG18
PRG2_PRU0_GPI4 (2)
PRU_ICSSG PRU Data Input
I
AG17
PRG2_PRU0_GPI5 (2)
PRU_ICSSG PRU Data Input
I
AF17
(2)
PRU_ICSSG PRU Data Input
I
AE17
PRG2_PRU0_GPI7 (2)
PRU_ICSSG PRU Data Input
I
AC19
PRG2_PRU0_GPI8 (2)
PRU_ICSSG PRU Data Input
I
AH16
(2)
AG16
PRG2_PRU0_GPI6
PRG2_PRU0_GPI9
PRU_ICSSG PRU Data Input
I
PRG2_PRU0_GPI10
(2)
PRU_ICSSG PRU Data Input
I
AF16
PRG2_PRU0_GPI11
(2)
PRU_ICSSG PRU Data Input
I
AE16
PRG2_PRU0_GPI12
(2)
PRU_ICSSG PRU Data Input
I
N23
PRG2_PRU0_GPI13
(2)
PRU_ICSSG PRU Data Input
I
M26
PRG2_PRU0_GPI14
(2)
PRU_ICSSG PRU Data Input
I
P28
PRG2_PRU0_GPI15
(2)
PRU_ICSSG PRU Data Input
I
P27
PRG2_PRU0_GPI16
(2)
PRU_ICSSG PRU Data Input
I
AD16
PRG2_PRU0_GPI17
(2)
PRU_ICSSG PRU Data Input
I
P23
AF18
PRG2_PRU0_GPO0 (2)
PRU_ICSSG PRU Data Output
IO
PRG2_PRU0_GPO1 (2)
PRU_ICSSG PRU Data Output
IO
AE18
PRG2_PRU0_GPO2 (2)
PRU_ICSSG PRU Data Output
IO
AH17
PRG2_PRU0_GPO3 (2)
PRU_ICSSG PRU Data Output
IO
AG18
(2)
PRU_ICSSG PRU Data Output
IO
AG17
PRG2_PRU0_GPO5 (2)
PRU_ICSSG PRU Data Output
IO
AF17
PRG2_PRU0_GPO6 (2)
PRU_ICSSG PRU Data Output
IO
AE17
PRG2_PRU0_GPO7 (2)
PRU_ICSSG PRU Data Output
IO
AC19
(2)
PRU_ICSSG PRU Data Output
IO
AH16
PRG2_PRU0_GPO9 (2)
PRU_ICSSG PRU Data Output
IO
AG16
PRG2_PRU0_GPO4
PRG2_PRU0_GPO8
PRG2_PRU0_GPO10
(2)
PRU_ICSSG PRU Data Output
IO
AF16
PRG2_PRU0_GPO11
(2)
PRU_ICSSG PRU Data Output
IO
AE16
PRG2_PRU0_GPO12
(2)
PRU_ICSSG PRU Data Output
IO
N23
PRG2_PRU0_GPO13
(2)
PRU_ICSSG PRU Data Output
IO
M26
PRG2_PRU0_GPO14
(2)
PRU_ICSSG PRU Data Output
IO
P28
PRG2_PRU0_GPO15
(2)
PRU_ICSSG PRU Data Output
IO
P27
PRG2_PRU0_GPO16
(2)
PRU_ICSSG PRU Data Output
IO
AD16
PRG2_PRU0_GPO17
(2)
PRU_ICSSG PRU Data Output
IO
P23
(2)
PRU_ICSSG PRU Data Input
I
AH15
PRG2_PRU1_GPI1 (2)
PRU_ICSSG PRU Data Input
I
AC16
PRG2_PRU1_GPI2 (2)
PRU_ICSSG PRU Data Input
I
AD17
PRG2_PRU1_GPI0
Terminal Configuration and Functions
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Table 4-54. PRU_ICSSG2 Signal Descriptions (continued)
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Table 4-54. PRU_ICSSG2 Signal Descriptions (continued)
SIGNAL NAME [1]
DESCRIPTION [2]
PIN
TYPE [3]
BALL [4]
PRG2_PRU1_GPI3 (2)
PRU_ICSSG PRU Data Input
I
AH14
PRG2_PRU1_GPI4 (2)
PRU_ICSSG PRU Data Input
I
AG14
PRG2_PRU1_GPI5 (2)
PRU_ICSSG PRU Data Input
I
AG15
(2)
PRU_ICSSG PRU Data Input
I
AC17
PRG2_PRU1_GPI7 (2)
PRU_ICSSG PRU Data Input
I
AE15
PRG2_PRU1_GPI8 (2)
PRU_ICSSG PRU Data Input
I
AD15
PRG2_PRU1_GPI9 (2)
PRG2_PRU1_GPI6
ADVANCE INFORMATION
PRU_ICSSG PRU Data Input
I
AF14
PRG2_PRU1_GPI10
(2)
PRU_ICSSG PRU Data Input
I
AC15
PRG2_PRU1_GPI11
(2)
PRU_ICSSG PRU Data Input
I
AD14
PRG2_PRU1_GPI12
(2)
PRU_ICSSG PRU Data Input
I
N26
PRG2_PRU1_GPI13
(2)
PRU_ICSSG PRU Data Input
I
N25
PRG2_PRU1_GPI14
(2)
PRU_ICSSG PRU Data Input
I
P24
PRG2_PRU1_GPI15
(2)
PRU_ICSSG PRU Data Input
I
R27
PRG2_PRU1_GPI16
(2)
PRU_ICSSG PRU Data Input
I
AE14
PRG2_PRU1_GPI17
(2)
PRU_ICSSG PRU Data Input
I
T23
PRG2_PRU1_GPO0 (2)
PRU_ICSSG PRU Data Output
IO
AH15
PRG2_PRU1_GPO1 (2)
PRU_ICSSG PRU Data Output
IO
AC16
(2)
PRU_ICSSG PRU Data Output
IO
AD17
PRG2_PRU1_GPO3 (2)
PRU_ICSSG PRU Data Output
IO
AH14
PRG2_PRU1_GPO4 (2)
PRU_ICSSG PRU Data Output
IO
AG14
PRG2_PRU1_GPO5 (2)
PRU_ICSSG PRU Data Output
IO
AG15
PRG2_PRU1_GPO6 (2)
PRU_ICSSG PRU Data Output
IO
AC17
PRG2_PRU1_GPO7 (2)
PRU_ICSSG PRU Data Output
IO
AE15
(2)
PRU_ICSSG PRU Data Output
IO
AD15
PRG2_PRU1_GPO9 (2)
PRU_ICSSG PRU Data Output
IO
AF14
PRG2_PRU1_GPO2
PRG2_PRU1_GPO8
PRG2_PRU1_GPO10
(2)
PRU_ICSSG PRU Data Output
IO
AC15
PRG2_PRU1_GPO11
(2)
PRU_ICSSG PRU Data Output
IO
AD14
PRG2_PRU1_GPO12
(2)
PRU_ICSSG PRU Data Output
IO
N26
PRG2_PRU1_GPO13
(2)
PRU_ICSSG PRU Data Output
IO
N25
PRG2_PRU1_GPO14
(2)
PRU_ICSSG PRU Data Output
IO
P24
PRG2_PRU1_GPO15
(2)
PRU_ICSSG PRU Data Output
IO
R27
PRG2_PRU1_GPO16
(2)
PRU_ICSSG PRU Data Output
IO
AE14
PRG2_PRU1_GPO17
(2)
PRU_ICSSG PRU Data Output
IO
T23
PRU_ICSSG PWM Trip Zone Input
I
P28
PRU_ICSSG PWM Trip Zone Output
O
P24
PRU_ICSSG PWM Trip Zone Input
I
F18
PRU_ICSSG PWM Trip Zone Output
O
AE14
PRU_ICSSG PWM Trip Zone Input
I
P23
PRU_ICSSG PWM Trip Zone Output
O
T23
PRU_ICSSG PWM Trip Zone Input
I
AE15
PRG2_PWM0_TZ_IN
(2)
PRG2_PWM0_TZ_OUT
PRG2_PWM1_TZ_IN
(2)
PRG2_PWM1_TZ_OUT
PRG2_PWM2_TZ_IN
(2)
(2)
PRG2_PWM2_TZ_OUT
PRG2_PWM3_TZ_IN
(2)
(2)
(2)
PRG2_PWM3_TZ_OUT
(2)
PRU_ICSSG PWM Trip Zone Output
O
AF14
(2)
PRU_ICSSG PWM Output A
IO
AG17
PRG2_PWM0_A1 (2)
PRU_ICSSG PWM Output A
IO
AD16
(2)
PRU_ICSSG PWM Output A
IO
AD15
PRG2_PWM0_B0 (2)
PRU_ICSSG PWM Output B
IO
AH16
PRG2_PWM0_B1 (2)
PRU_ICSSG PWM Output B
IO
AD17
PRG2_PWM0_B2 (2)
PRU_ICSSG PWM Output B
IO
AC15
PRG2_PWM0_A0
PRG2_PWM0_A2
94
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Table 4-54. PRU_ICSSG2 Signal Descriptions (continued)
PIN
TYPE [3]
DESCRIPTION [2]
BALL [4]
PRG2_PWM1_A0 (2)
PRU_ICSSG PWM Output A
IO
R23
PRG2_PWM1_A1 (2)
PRU_ICSSG PWM Output A
IO
AD18
PRG2_PWM1_A2 (2)
PRU_ICSSG PWM Output A
IO
AE26
(2)
PRU_ICSSG PWM Output B
IO
T24
PRG2_PWM1_B1 (2)
PRU_ICSSG PWM Output B
IO
AH18
PRG2_PWM1_B2 (2)
PRU_ICSSG PWM Output B
IO
AE28
PRG2_PWM2_A0 (2)
PRU_ICSSG PWM Output A
IO
N23
(2)
PRU_ICSSG PWM Output A
IO
P27
PRG2_PWM2_A2 (2)
PRU_ICSSG PWM Output A
IO
N25
PRG2_PWM2_B0 (2)
PRU_ICSSG PWM Output B
IO
M26
(2)
PRU_ICSSG PWM Output B
IO
N26
PRG2_PWM2_B2 (2)
PRU_ICSSG PWM Output B
IO
R27
PRG2_PWM3_A0 (2)
PRU_ICSSG PWM Output A
IO
AF18
PRG2_PWM3_A1 (2)
PRU_ICSSG PWM Output A
IO
AF17
PRG2_PWM3_A2 (2)
PRU_ICSSG PWM Output A
IO
AH15
PRG2_PWM3_B0 (2)
PRU_ICSSG PWM Output B
IO
AG18
PRG2_PWM3_B1 (2)
PRU_ICSSG PWM Output B
IO
AE17
(2)
PRU_ICSSG PWM Output B
IO
AC16
PRG2_PWM1_B0
PRG2_PWM2_A1
PRG2_PWM2_B1
PRG2_PWM3_B2
PRG2_RGMII1_RXC
PRU_ICSSG RGMII Receive Clock
I
AF17
PRG2_RGMII1_RX_CTL
PRU_ICSSG RGMII Receive Control
I
AG17
PRG2_RGMII1_TXC
PRU_ICSSG RGMII Transmit Clock
IO
AD16
PRG2_RGMII1_TX_CTL
PRU_ICSSG RGMII Transmit Control
O
AE17
PRG2_RGMII2_RXC
PRU_ICSSG RGMII Receive Clock
I
AG15
PRG2_RGMII2_RX_CTL
PRU_ICSSG RGMII Receive Control
I
AG14
PRG2_RGMII2_TXC
PRU_ICSSG RGMII Transmit Clock
IO
AE14
PRG2_RGMII2_TX_CTL
PRU_ICSSG RGMII Transmit Control
O
AC17
PRG2_RGMII1_RD0
PRU_ICSSG RGMII Receive Data
I
AF18
PRG2_RGMII1_RD1
PRU_ICSSG RGMII Receive Data
I
AE18
PRG2_RGMII1_RD2
PRU_ICSSG RGMII Receive Data
I
AH17
PRG2_RGMII1_RD3
PRU_ICSSG RGMII Receive Data
I
AG18
PRG2_RGMII1_TD0
PRU_ICSSG RGMII Transmit Data
O
AH16
PRG2_RGMII1_TD1
PRU_ICSSG RGMII Transmit Data
O
AG16
PRG2_RGMII1_TD2
PRU_ICSSG RGMII Transmit Data
O
AF16
PRG2_RGMII1_TD3
PRU_ICSSG RGMII Transmit Data
O
AE16
PRG2_RGMII2_RD0
PRU_ICSSG RGMII Receive Data
I
AH15
PRG2_RGMII2_RD1
PRU_ICSSG RGMII Receive Data
I
AC16
PRG2_RGMII2_RD2
PRU_ICSSG RGMII Receive Data
I
AD17
PRG2_RGMII2_RD3
PRU_ICSSG RGMII Receive Data
I
AH14
PRG2_RGMII2_TD0
PRU_ICSSG RGMII Transmit Data
O
AD15
PRG2_RGMII2_TD1
PRU_ICSSG RGMII Transmit Data
O
AF14
PRG2_RGMII2_TD2
PRU_ICSSG RGMII Transmit Data
O
AC15
PRG2_RGMII2_TD3
PRU_ICSSG RGMII Transmit Data
O
AD14
PRG2_UART0_CTSn (2)
PRU_ICSSG UART Clear to Send (active low)
I
AD12
PRU_ICSSG UART Request to Send (active low)
O
AH12
PRU_ICSSG UART Receive Data
I
AE12
PRU_ICSSG UART Transmit Data
O
AF12
PRG2_UART0_RTSn
(2)
PRG2_UART0_RXD (2)
PRG2_UART0_TXD
(2)
Terminal Configuration and Functions
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SIGNAL NAME [1]
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(1) When OSC1 is being used with an external crystal, this signal is unavailable. The output functionality must be disabled.
(2) ICSS does not support these signals on this SoC. Signals are retained for consistency with the pin compatible family of devices.
4.3.22 SERDES
4.3.22.1 MAIN Domain
Table 4-55. SERDES0 Signal Descriptions(1)
SIGNAL NAME [1]
DESCRIPTION [2]
PIN
TYPE [3]
BALL [4]
SERDES0_REFCLKN
SERDES Clock Input (negative)
I
AG5
SERDES0_REFCLKP
SERDES Clock Input (positive)
I
AG6
(2)
A
AC9
SERDES0_REFRES
SERDES Reference Resistor
SERDES0_RXN
SERDES Differential Receive Data (negative)
I
AH3
SERDES0_RXP
SERDES Differential Receive Data (positive)
I
AG2
SERDES0_TXN
SERDES Differential Transmit Data (negative)
O
AH4
SERDES0_TXP
SERDES Differential Transmit Data (positive)
O
AG3
ADVANCE INFORMATION
(1) The functionality of these pins is controlled by CTRLMMR_SERDES0_CTRL[1:0] LANE_FUNC_SEL. 0x0 = USB3, 0x1 = PCIe0 Lane0,
0x2 = ICSS2 SGMII Lane0.
(2) The required resistor value is 3kΩ ±1%.
Table 4-56. SERDES1 Signal Descriptions(1)
SIGNAL NAME [1]
DESCRIPTION [2]
PIN
TYPE [3]
BALL [4]
AH6
SERDES1_REFCLKN
SERDES Clock Input (negative)
I
SERDES1_REFCLKP
SERDES Clock Input (positive)
I
AH7
SERDES1_REFRES
SERDES Reference Resistor(2)
A
AC14
SERDES1_RXN
SERDES Differential Receive Data (negative)
I
AG9
SERDES1_RXP
SERDES Differential Receive Data (positive)
I
AH10
SERDES1_TXN
SERDES Differential Transmit Data (negative)
O
AH9
SERDES1_TXP
SERDES Differential Transmit Data (positive)
O
AG8
(1) The functionality of these pins is controlled by CTRLMMR_SERDES1_CTRL[1:0] LANE_FUNC_SEL. 0x0 = PCIe1 Lane0, 0x1 = PCIe0
Lane1, 0x2 = ICSS2 SGMII Lane1.
(2) The required resistor value is 3kΩ ±1%.
4.3.23 UART
4.3.23.1 MAIN Domain
Table 4-57. UART0 Signal Descriptions
SIGNAL NAME [1]
DESCRIPTION [2]
PIN
TYPE [3]
BALL [4]
UART0_CTSn
UART Clear to Send (active low)
I
AG11
UART0_DCDn
UART Data Carrier Detect (active low)
I
D25
UART0_DSRn
UART Data Set Ready (active low)
I
B26
UART0_DTRn
UART Data Terminal Ready (active low)
O
A24
UART0_RIN
UART Ring Indicator
I
E24
UART0_RTSn
UART Request to Send (active low)
O
AD11
UART0_RXD
UART Receive Data
I
AF11
UART0_TXD
UART Transmit Data
O
AE11
96
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Table 4-58. UART1 Signal Descriptions
SIGNAL NAME [1]
DESCRIPTION [2]
PIN
TYPE [3]
BALL [4]
UART1_CTSn
UART Clear to Send (active low)
I
AD22
UART1_RTSn
UART Request to Send (active low)
O
AC21
UART1_RXD
UART Receive Data
I
AE23
UART1_TXD
UART Transmit Data
O
AD23
PIN
TYPE [3]
BALL [4]
Table 4-59. UART2 Signal Descriptions
SIGNAL NAME [1]
DESCRIPTION [2]
UART2_CTSn
UART Clear to Send (active low)
I
Y26
UART2_RTSn
UART Request to Send (active low)
O
W26
UART2_RXD
UART Receive Data
I
Y27
UART2_TXD
UART Transmit Data
O
W28
PIN
TYPE [3]
BALL [4]
ADVANCE INFORMATION
4.3.23.2 MCU Domain
Table 4-60. UART0 Signal Descriptions
SIGNAL NAME [1]
DESCRIPTION [2]
MCU_UART0_CTSn
UART Clear to Send (active low)
I
P1
MCU_UART0_RTSn
UART Request to Send (active low)
O
N3
MCU_UART0_RXD
UART Receive Data
I
P4
MCU_UART0_TXD
UART Transmit Data
O
P5
PIN
TYPE [3]
BALL [4]
4.3.23.3 WKUP Domain
Table 4-61. UART0 Signal Descriptions
SIGNAL NAME [1]
DESCRIPTION [2]
WKUP_UART0_CTSn
UART Clear to Send (active low)
I
AC2
WKUP_UART0_RTSn
UART Request to Send (active low)
O
AC1
WKUP_UART0_RXD
UART Receive Data
I
AB1
WKUP_UART0_TXD
UART Transmit Data
O
AB5
PIN
TYPE [3]
BALL [4]
4.3.24 USB
4.3.24.1 MAIN Domain
Table 4-62. USB0 Signal Descriptions
SIGNAL NAME [1]
DESCRIPTION [2]
USB0_DM
USB 2.0 Differential Data (negative)
IO
AE2
USB0_DP
USB 2.0 Differential Data (positive)
IO
AF1
USB0_DRVVBUS
USB VBUS control output (active high)
O
AD9
USB0_ID
USB 2.0 Dual-Role Device Role Select
A
AF7
USB Level-shifted VBUS Input
A
AE7
USB0_VBUS
(1)
Terminal Configuration and Functions
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(1) An external resistor divider is required to limit the voltage applied to the device pin. For more information, see Section 7.4.
Table 4-63. USB1 Signal Descriptions
SIGNAL NAME [1]
DESCRIPTION [2]
PIN
TYPE [3]
BALL [4]
AD2
USB1_DM
USB 2.0 Differential Data (negative)
IO
USB1_DP
USB 2.0 Differential Data (positive)
IO
AE1
USB1_DRVVBUS
USB VBUS control output (active high)
O
AC8
USB1_ID
USB 2.0 Dual-Role Device Role Select
A
AF5
USB Level-shifted VBUS Input
A
AF6
USB1_VBUS
(1)
(1) An external resistor divider is required to limit the voltage applied to the device pin. For more information, see Section 7.4.
4.3.25 Emulation and Debug
4.3.25.1 MAIN Domain
Table 4-64. Emulation and Debug 0 Signal Descriptions
ADVANCE INFORMATION
SIGNAL NAME [1]
DESCRIPTION [2]
PIN
TYPE [3]
BALL [4]
EMU0
Emulation Control 0
IO
AA2
EMU1
Emulation Control 1
IO
AA1
TCK
JTAG Test Clock Input
I
AA4
TDI
JTAG Test Data Input
I
C20
TDO
JTAG Test Data Output
OZ
A20
TMS
JTAG Test Mode Select Input
I
A21
TRSTn
JTAG Reset
I
AA3
TRC_CLK
Trace Clock
O
AF18
TRC_CTL
Trace Control
O
AE18
TRC_DATA0
Trace Data 0
O
AH17
TRC_DATA1
Trace Data 1
O
AG18
TRC_DATA2
Trace Data 2
O
AG17
TRC_DATA3
Trace Data 3
O
AF17
TRC_DATA4
Trace Data 4
O
AE17
TRC_DATA5
Trace Data 5
O
AC19
TRC_DATA6
Trace Data 6
O
AH16
TRC_DATA7
Trace Data 7
O
AG16
TRC_DATA8
Trace Data 8
O
AF16
TRC_DATA9
Trace Data 9
O
AE16
TRC_DATA10
Trace Data 10
O
AD16
TRC_DATA11
Trace Data 11
O
AH15
TRC_DATA12
Trace Data 12
O
AC16
TRC_DATA13
Trace Data 13
O
AD17
TRC_DATA14
Trace Data 14
O
AH14
TRC_DATA15
Trace Data 15
O
AG14
TRC_DATA16
Trace Data 16
O
AG15
TRC_DATA17
Trace Data 17
O
AC17
TRC_DATA18
Trace Data 18
O
AE15
TRC_DATA19
Trace Data 19
O
AD15
TRC_DATA20
Trace Data 20
O
AF14
TRC_DATA21
Trace Data 21
O
AC15
TRC_DATA22
Trace Data 22
O
AD14
98
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Table 4-64. Emulation and Debug 0 Signal Descriptions (continued)
SIGNAL NAME [1]
Trace Data 23
PIN
TYPE [3]
BALL [4]
O
AE14
ADVANCE INFORMATION
TRC_DATA23
DESCRIPTION [2]
Terminal Configuration and Functions
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4.3.26 System and Miscellaneous
4.3.26.1 Boot Mode Configuration
4.3.26.1.1 MAIN Domain
Table 4-65. Sysboot Signal Descriptions
SIGNAL NAME [1]
DESCRIPTION [2]
PIN
TYPE [3]
BALL [4]
ADVANCE INFORMATION
BOOTMODE00
Bootmode pin 00
I
M27
BOOTMODE01
Bootmode pin 01
I
M23
BOOTMODE02
Bootmode pin 02
I
M28
BOOTMODE03
Bootmode pin 03
I
M24
BOOTMODE04
Bootmode pin 04
I
N24
BOOTMODE05
Bootmode pin 05
I
N27
BOOTMODE06
Bootmode pin 06
I
N28
BOOTMODE07
Bootmode pin 07
I
M25
BOOTMODE08
Bootmode pin 08
I
N23
BOOTMODE09
Bootmode pin 09
I
M26
BOOTMODE10
Bootmode pin 10
I
P28
BOOTMODE11
Bootmode pin 11
I
P27
BOOTMODE12
Bootmode pin 12
I
N26
BOOTMODE13
Bootmode pin 13
I
N25
BOOTMODE14
Bootmode pin 14
I
P24
BOOTMODE15
Bootmode pin 15
I
R27
BOOTMODE16
Bootmode pin 16
I
P25
BOOTMODE17
Bootmode pin 17
I
P26
BOOTMODE18
Bootmode pin 18
I
U28
PIN
TYPE [3]
BALL [4]
AF4
4.3.26.1.2 MCU Domain
Table 4-66. Sysboot Signal Descriptions
SIGNAL NAME [1]
DESCRIPTION [2]
MCU_BOOTMODE00
Bootmode pin 00
I
MCU_BOOTMODE01
Bootmode pin 01
I
AF3
MCU_BOOTMODE02
Bootmode pin 02
I
AE3
MCU_BOOTMODE03(1)
Bootmode pin 03
I
AD1
MCU_BOOTMODE04(1)
Bootmode pin 04
I
AC3
MCU_BOOTMODE05(1)
Bootmode pin 05
I
Y2
MCU_BOOTMODE06(1)
Bootmode pin 06
I
Y1
(1)
MCU_BOOTMODE07
Bootmode pin 07
I
Y3
MCU_BOOTMODE08(1)
Bootmode pin 08
I
AC5
MCU_BOOTMODE09
Bootmode pin 09
I
AB4
100
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(1) These signals must be connected to VSS through a separate external pull resistor to ensure these balls are held to a valid logic low
level.
4.3.26.2 Clock
4.3.26.2.1 MAIN Domain
Table 4-67. Clock1 Signal Descriptions
SIGNAL NAME [1]
DESCRIPTION [2]
PIN
TYPE [3]
BALL [4]
OSC1_XI
High frequency oscillator input
I
C22
OSC1_XO
High frequency oscillator output
O
E22
PIN
TYPE [3]
BALL [4]
4.3.26.2.2 WKUP Domain
SIGNAL NAME [1]
DESCRIPTION [2]
WKUP_LFOSC0_XI
Low frequency (32.768 KHz) oscillator input
I
AE4
WKUP_LFOSC0_XO
Low frequency (32.768 KHz) oscillator output
O
AC4
WKUP_OSC0_XI
High frequency oscillator input
I
AD5
WKUP_OSC0_XO
High frequency oscillator output
O
AE6
DESCRIPTION [2]
PIN
TYPE [3]
BALL [4]
EXT_REFCLK1
External clock input to Main Domain, routed to Timer
clock muxes as one of the selectable input clock sources
for Timer/WDT modules, or as reference clock to
MAIN_PLL2 (PER1 PLL)
I
A22
NMIn
External Interrupt
I
F18
OBSCLK0
Observation clock output for test and debug purposes
only
O
C23
PORz
Main Domain cold reset
I
E19
PORz_OUT
Main Domain POR status output
O
C19
REFCLK0N
SERDES Differential Clock Output (negative)
O
AF9
REFCLK0P
SERDES Differential Clock Output (positive)
O
AF10
REFCLK1N
SERDES Differential Clock Output (negative)
O
AE8
REFCLK1P
SERDES Differential Clock Output (positive)
O
AE9
RESETSTATz
Main Domain warm reset status output
O
D19
RESETz
Main Domain warm reset
I
F17
SOC_SAFETY_ERRORn
Error signal output from Main Domain ESM
IO
E20
SYNC0_OUT
CPTS Time Stamp Generator Bit 0
O
D21
SYNC1_OUT
CPTS Time Stamp Generator Bit 1
O
A22
SYNC2_OUT
CPTS Time Stamp Generator Bit 2
O
AE18
SYNC3_OUT
CPTS Time Stamp Generator Bit 3
O
AH17
SYSCLKOUT0
SYSCLK0 output from Main PLL controller (divided by 4)
for test and debug purposes only
O
B22
ADVANCE INFORMATION
Table 4-68. Clock0 Signal Descriptions
4.3.26.3 System
4.3.26.3.1 MAIN Domain
Table 4-69. System0 Signal Descriptions
SIGNAL NAME [1]
Terminal Configuration and Functions
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4.3.26.3.2 WKUP Domain
Table 4-70. System0 Signal Descriptions
SIGNAL NAME [1]
DESCRIPTION [2]
PIN
TYPE [3]
BALL [4]
ADVANCE INFORMATION
MCU_BYP_POR
MCU Bypass reset circuitry input. 0 = Internal POR is
used, 1 = External MCU_PORz signal is used.
I
V5
MCU_CLKOUT0
Reference clock output for Ethernet PHYs (50MHz or
25MHz)
O
AB2
MCU_EXT_REFCLK0
External system clock input
I
AB3
MCU_OBSCLK0
Observation clock output for test and debug purposes
only
O
AB2
MCU_PORz
MCU Domain cold reset
I
W5
MCU_PORz_OUT
MCU Domain POR status output
O
V2
MCU_RESETSTATz
MCU Domain warm reset status output
O
V3
MCU_RESETz
MCU Domain warm reset
I
W4
MCU_SAFETY_ERRORn
Error signal output from MCU Domain ESM
IO
W3
MCU_SYSCLKOUT0
MCU Domain system clock output (divided by 4) for test
and debug purposes only
O
AB3
PMIC_POWER_EN0
Power enable output for MAIN Domain supplies
O
Y5
PMIC_POWER_EN1
Power enable output for MAIN Domain supplies
O
AA5
PIN
TYPE [3]
BALL [4]
A
W6
PIN
TYPE [3]
BALL [4]
PWR
F21
4.3.26.4 Miscellaneous
4.3.26.4.1 WKUP Domain
Table 4-71. Miscellaneous0 Signal Descriptions
SIGNAL NAME [1]
DESCRIPTION [2]
TEMP_DIODE_P
Temperature Sensor Diode
4.3.26.5 EFUSE
4.3.26.5.1 MAIN Domain
Table 4-72. EFUSE0 Signal Descriptions
SIGNAL NAME [1]
VPP_CORE
(1)
DESCRIPTION [2]
Programming voltage for MAIN Domain efuses
(1) This signal is valid only for High-Security devices. For more details, see Section 5.7, VPP Specification for One-Time Programmable
(OTP) eFUSEs. For General Purpose devices do not connect any signal, test point, or board trace to this signal.
102
Terminal Configuration and Functions
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4.3.26.5.2 MCU Domain
Table 4-73. EFUSE0 Signal Descriptions
SIGNAL NAME [1]
VPP_MCU
(1)
DESCRIPTION [2]
Programming voltage for MCU Domain efuses
PIN
TYPE [3]
BALL [4]
PWR
T6
(1) This signal is valid only for High-Security devices. For more details, see Section 5.7, VPP Specification for One-Time Programmable
(OTP) eFUSEs. For General Purpose devices do not connect any signal, test point, or board trace to this signal.
4.3.27 Power Supply
SIGNAL NAME [1]
DESCRIPTION [2]
PIN
TYPE [3]
BALL [4]
(1)
External capacitor connection for CORE SRAM LDOs
CAP
P17
CAP_VDDAR_CORE1(1)
External capacitor connection for CORE SRAM LDOs
CAP
V17
(1)
External capacitor connection for CORE SRAM LDOs
CAP
W16
CAP_VDDAR_CORE3(1)
External capacitor connection for MSMC SRAM LDOs
CAP
M14
CAP_VDDAR_CORE4(1)
External capacitor connection for MSMC SRAM LDOs
CAP
L15
CAP_VDDAR_MCU(1)
External capacitor connection for MCU SRAM LDO
CAP
U10
CAP_VDDAR_MPU0_0(1)
External capacitor connection for MPU SRAM LDOs
CAP
M12
CAP_VDDAR_MPU0_1(1)
External capacitor connection for MPU SRAM LDOs
CAP
N12
CAP_VDDAR_MPU1_0(1)
External capacitor connection for MPU SRAM LDOs
CAP
N18
(1)
CAP_VDDAR_MPU1_1
External capacitor connection for MPU SRAM LDOs
CAP
N15
CAP_VDDAR_WKUP(1)
External capacitor connection for WKUP SRAM LDO
CAP
Y10
CAP_VDDA_1P8_IOLDO_WKUP(1)
External capacitor connection for IO Bias LDO in WKUP
domain
CAP
AA8
CAP_VDDA_1P8_SDIO(2)
External capacitor connection for SDIO LDO
CAP
J17
CAP_VDDA_1P8_IOLDO0(1)
External capacitor connection for IO Bias LDO
CAP
G19
CAP_VDDA_1P8_IOLDO1(1)
External capacitor connection for IO Bias LDO
CAP
Y19
H18
CAP_VDDAR_CORE0
CAP_VDDAR_CORE2
CAP_VDDSHV_SDIO
(3)
ADVANCE INFORMATION
Table 4-74. Power Supply Signal Description
External capacitor connection for SDIO LDO
CAP
CAP_VDD_WKUP(1)
External capacitor connection for WKUP LDO
CAP
V9
VDDA_1P8_MON_WKUP
Supply monitor in WKUP domain
A
AB6
VDDA_1P8_SDIO
SDIO LDO analog power supply
PWR
G17
VDDA_1P8_CSI0
CSI PHY analog power supply
PWR
L20, M21
VDDA_1P8_MON0
Supply monitor in MAIN domain
A
AC6
VDDA_1P8_OLDI0
OLDI analog power supply
PWR
L22
VDDA_1P8_SERDES0
SERDES0/1 (USB, PCIE) analog power supply
PWR
AA14, AB13, AB15
VDDA_3P3_IOLDO_WKUP
WKUP IO Bias LDO analog power supply
PWR
AB9
VDDA_3P3_MON_WKUP
Supply monitor in WKUP domain
A
U6
VDDA_3P3_SDIO
SDIO LDO analog power supply
PWR
H17
VDDA_3P3_USB
USB analog power supply
PWR
AC12
VDDA_3P3_IOLDO0
IO Bias LDO analog power supply
PWR
G18
VDDA_3P3_IOLDO1
IO Bias LDO analog power supply
PWR
AA21
VDDA_3P3_MON0
Supply monitor in MAIN domain
A
AC10
VDDA_ADC_MCU
ADC0, ADC1 analog power supply
PWR
M7, M9
VDDA_LDO_WKUP
WKUP LDO analog power supply
PWR
AB8
VDDA_MCU
MCU SRAM LDO, MCU DPLL, CPSW DPLL analog
power supply
PWR
U12
VDDA_PLL0_DDR
DDR DPLL analog power supply
PWR
H15
VDDA_PLL1_DDR
DDR De-skew DPLL analog power supply
PWR
H11
Terminal Configuration and Functions
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Table 4-74. Power Supply Signal Description (continued)
SIGNAL NAME [1]
DESCRIPTION [2]
PIN
TYPE [3]
BALL [4]
ADVANCE INFORMATION
VDDA_PLL_CORE
CORE DPLL, PER1 DPLL analog power supply
PWR
Y17
VDDA_PLL_DSS
DSS DPLL analog power supply
PWR
L21
VDDA_PLL_MPU0
MPU0 DPLL analog power supply
PWR
L12
VDDA_PLL_MPU1
MPU1 DPLL analog power supply
PWR
K15
VDDA_PLL_PER0
PER0 DPLL analog power supply
PWR
AB7
VDDA_POR_WKUP(5)
WKUP POR/POK analog power supply
PWR
Y9
VDDA_SRAM_CORE0
CORE SRAM LDOs analog power supply
PWR
M19
VDDA_SRAM_CORE1
CORE SRAM LDOs analog power supply
PWR
V16
VDDA_SRAM_MPU0
MPU SRAM LDOs analog power supply
PWR
K7
VDDA_SRAM_MPU1
MPU SRAM LDOs analog power supply
PWR
L18
VDDA_VSYS_MON(6)
Supply monitor for system
A
AC11
VDDA_WKUP
WKUP High/Low Frequency Oscillator (WKUP_LFOSC0 /
WKUP_OSC0), SRAM LDO analog power supply
PWR
AA9
VDDS0
IO bias supply for VDDSHV0
PWR
G12
VDDS0_WKUP
IO bias supply for VDDSHV0_WKUP
PWR
V8
VDDS1
IO bias supply for VDDSHV1
PWR
AA16
VDDS1_WKUP
IO bias supply for VDDSHV1_WKUP
PWR
T9
VDDS2
IO bias supply for VDDSHV2
PWR
P20
VDDS2_WKUP
IO bias supply for VDDSHV2_WKUP
PWR
N8
VDDS3
IO bias supply for VDDSHV3
PWR
T20
VDDS4
IO bias supply for VDDSHV4
PWR
Y20
VDDS5
IO bias supply for VDDSHV5
PWR
AC18
VDDS6
IO bias supply for VDDSHV6
PWR
F20
VDDS7
IO bias supply for VDDSHV7
PWR
K20
VDDS8
IO bias supply for VDDSHV8
PWR
AA10
VDDSHV0
Dual-voltage IO domain power supply
PWR
G15, H16
VDDSHV0_WKUP
Dual-voltage IO domain power supply
PWR
U8, V7, W8, Y7
VDDSHV1
Dual-voltage IO domain power supply
PWR
AA18, AB17
VDDSHV1_WKUP
Dual-voltage IO domain power supply
PWR
R6, R8, T7
N20, N22, P21, R20,
R22
VDDSHV2
Dual-voltage IO domain power supply
PWR
VDDSHV2_WKUP
Dual-voltage IO domain power supply
PWR
N6, P7, P9
VDDSHV3
Dual-voltage IO domain power supply
PWR
T21, U20, U22, V21,
V23
VDDSHV4
Dual-voltage IO domain power supply
PWR
AA22, W20, W22,
Y21, Y23
VDDSHV5
Dual-voltage IO domain power supply
PWR
AA20, AB19, AB21,
AB23
VDDSHV6
Dual-voltage IO domain power supply
PWR
G20, H19, H21
VDDSHV7
Dual-voltage IO domain power supply
PWR
J20, J22, K21
VDDSHV8
Dual-voltage IO domain power supply
PWR
AB11
VDDS_DDR
DDR IO domain power supply
PWR
G10, G14, G8, H13,
H7, H9
VDDS_OSC1
MAIN High Frequency Oscillator (OSC1) analog power
supply
PWR
J16
104
Terminal Configuration and Functions
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SIGNAL NAME [1]
DESCRIPTION [2]
PIN
TYPE [3]
BALL [4]
VDD_CORE
CORE voltage domain supply
PWR
AA12, J10, J12, J14,
J19, J8, K13, L14,
L19, M13, N14, P13,
P15, P19, R14, R16,
R18, T13, T15, T17,
T19, U14, U16, U18,
V13, V15, V19, W14,
W18, Y11, Y13, Y15
VDD_DLL_MMC0
MMC0 PHY DLL voltage supply
PWR
G22
VDD_DLL_MMC1
MMC1 PHY DLL voltage supply
PWR
H23
VDD_MCU
MCU voltage domain supply
PWR
N10, P11, R10, R12,
T11
VDD_MPU0
MPU0 voltage domain supply
PWR
K11, K9, L10, L8,
M11
VDD_MPU1
MPU1 voltage domain supply
PWR
K16, K18, L17, M16,
M18, N17
VDD_WKUP0(4)
WKUP voltage domain supply
PWR
V11, W10, W12
VDD_WKUP1(4)
WKUP voltage domain supply
PWR
M22
GND
A1, A2, A28, AA11,
AA13, AA15, AA17,
AA19, AA23, AA26,
AA7, AB10, AB12,
AB14, AB16, AB18,
AB20, AB22, AD4,
AE10, AE25, AE5,
AF15, AF2, AF20,
AF8, AG1, AG10,
AG28, AG4, AG7,
AH1, AH11, AH2,
AH27, AH28, AH5,
AH8, B12, B15, B20,
B6, B9, D22, E26,
E28, E4, F14, F19,
F22, F25, F27, F3,
G11, G13, G16, G2,
G21, G23, G7, G9,
H1, H10, H12, H14,
H20, H22, H24, H26,
H28, H6, H8, J11,
J13, J15, J18, J21,
J23, J25, J27, J7, J9,
K1, K10, K12, K14,
K17, K19, K22, K23,
K6, K8, L11, L13,
L16, L23, L24, L26,
L28, L3, L7, L9, M10,
M15, M17, M20, M8,
N11, N13, N16, N19,
N21, N7, N9, P10,
P12, P14, P16, P18,
P22, P6, P8, R11,
R13, R15, R17, R19,
R21, R7, R9, T10,
T12, T14, T16, T18,
T22, T26, T8, U11,
U13, U15, U17, U19,
U21, U3, U7, U9,
V10, V12, V14, V18,
V20, V22, V6, W11,
W13, W15, W17,
W19, W21, W23, W7,
W9, Y12, Y14, Y16,
Y18, Y22, Y6, Y8
VSS
Ground
Terminal Configuration and Functions
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ADVANCE INFORMATION
Table 4-74. Power Supply Signal Description (continued)
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(1) This pin must always be connected via a 1-uF capacitor to VSS.
(2) The net connecting CAP_VDDA_1P8_SDIO and VDDA_1P8_SDIO to VDDS6 or VDDS7 must be connected to a 3.3-uF decoupling
capacitor. VDDA_1P8_SDIO, CAP_VDDA_1P8_SDIO, CAP_VDDSHV_SDIO, and VDDA_3P3_SDIO must be connected to VSS, when
SDIO_LDO is not used with either MMC0 or MMC1.
(3) When CAP_VDDSHV_SDIO is connected to VDDSHV6 or VDDSHV7, the entire net which connects these pins should not exceed TBDuF of decoupling capacitance. When SDIO LDO is not used, this pin should be left unconnected.
(4) These power rails should be connected together on the board level.
(5) VDDA_POR_WKUP is preferred to be connected to CAP_VDDA_1P8_IOLDO_WKUP when using internal POR feature.
(6) The VDDA_VSYS_MON pin provides a way to monitor the system power supply and is not fail-safe, unless implemented with the
appropriate resistor voltage divider source. For more information, see Section 7.5, System Power Supply Monitor Design Guidelines.
ADVANCE INFORMATION
106
Terminal Configuration and Functions
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4.4
SPRSP31E – APRIL 2018 – REVISED JUNE 2019
Pin Multiplexing
Table 4-75 describes the device pin multiplexing associated with pins.
NOTE
Many device pins support multiple signal functions. Some signal functions are selected via a single layer of multiplexers associated with
pins. Other signal functions are selected via two or more layers of multiplexers, where one layer is associated with the pins and other
layers are associated with peripheral logic functions.
ADVANCE INFORMATION
Table 4-75, Pin Multiplexing only describes signal multiplexing at the pins. For more information, related to signal multiplexing at the pins,
see section Pad Configuration Registers in the device TRM. Refer to the respective peripheral chapter in the device TRM for information
associated with peripheral signal multiplexing.
NOTE
When a pad is set into a pin multiplexing mode which is not defined, that pad’s behavior is undefined. This should be avoided.
NOTE
Table 4-75, Pin Multiplexing does not include SerDes signal functions. For more information, refer to the Serializer/Deserializer (SerDes)
section in the device TRM.
NOTE
The PRU_ICSSG contains a second layer of multiplexing to enable additional functionality on the PRU GPO and GPI signals. This
internal wrapper multiplexing is described in the PRU_ICSSG chapter in the device TRM.
For more information on the I/O cell configurations, see section Pad Configuration Registers in the device TRM.
Table 4-75. Pin Multiplexing
ADDRESS
REGISTER NAME
BALL
NUMBER
MUXMODE[7:0] SETTINGS
0
1
2
3
4
5
6
7
Bootstrap
0x0011C000
SOC_PADCONFIG_0
M27
GPMC0_AD0
VOUT1_DATA0
VIN0_DATA12
GPIO0_0
BOOTMODE00
0x0011C004
SOC_PADCONFIG_1
M23
GPMC0_AD1
VOUT1_DATA1
VIN0_DATA13
GPIO0_1
BOOTMODE01
0x0011C008
SOC_PADCONFIG_2
M28
GPMC0_AD2
VOUT1_DATA2
VIN0_DATA14
GPIO0_2
BOOTMODE02
0x0011C00C
SOC_PADCONFIG_3
M24
GPMC0_AD3
VOUT1_DATA3
VIN0_DATA15
GPIO0_3
BOOTMODE03
0x0011C010
SOC_PADCONFIG_4
N24
GPMC0_AD4
VOUT1_DATA4
GPIO0_4
BOOTMODE04
0x0011C014
SOC_PADCONFIG_5
N27
GPMC0_AD5
VOUT1_DATA5
GPIO0_5
BOOTMODE05
0x0011C018
SOC_PADCONFIG_6
N28
GPMC0_AD6
VOUT1_DATA6
GPIO0_6
BOOTMODE06
Terminal Configuration and Functions
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Table 4-75. Pin Multiplexing (continued)
ADDRESS
REGISTER NAME
BALL
NUMBER
MUXMODE[7:0] SETTINGS
0
1
2
ADVANCE INFORMATION
0x0011C01C
SOC_PADCONFIG_7
M25
GPMC0_AD7
VOUT1_DATA7
0x0011C020
SOC_PADCONFIG_8
N23
GPMC0_AD8
VOUT1_DATA8
VIN0_DATA0
0x0011C024
SOC_PADCONFIG_9
M26
GPMC0_AD9
VOUT1_DATA9
0x0011C028
SOC_PADCONFIG_10
P28
GPMC0_AD10
0x0011C02C
SOC_PADCONFIG_11
P27
0x0011C030
SOC_PADCONFIG_12
0x0011C034
3
4
5
6
7
Bootstrap
GPIO0_7
BOOTMODE07
PRG2_PRU0_GPO PRG2_PRU0_GPI1 PRG2_PWM2_A0
12
2
GPIO0_8
BOOTMODE08
VIN0_DATA1
PRG2_PRU0_GPO PRG2_PRU0_GPI1 PRG2_PWM2_B0
13
3
GPIO0_9
BOOTMODE09
VOUT1_DATA10
VIN0_DATA2
PRG2_PRU0_GPO PRG2_PRU0_GPI1
14
4
GPMC0_AD11
VOUT1_DATA11
VIN0_DATA3
N26
GPMC0_AD12
VOUT1_DATA12
SOC_PADCONFIG_13
N25
GPMC0_AD13
0x0011C038
SOC_PADCONFIG_14
P24
0x0011C03C
SOC_PADCONFIG_15
0x0011C040
0x0011C044
PRG2_PWM0_TZ_I GPIO0_10
N
BOOTMODE10
PRG2_PRU0_GPO PRG2_PRU0_GPI1 PRG2_PWM2_A1
15
5
GPIO0_11
BOOTMODE11
VIN0_DATA4
PRG2_PRU1_GPO PRG2_PRU1_GPI1 PRG2_PWM2_B1
12
2
GPIO0_12
BOOTMODE12
VOUT1_DATA13
VIN0_DATA5
PRG2_PRU1_GPO PRG2_PRU1_GPI1 PRG2_PWM2_A2
13
3
GPIO0_13
BOOTMODE13
GPMC0_AD14
VOUT1_DATA14
VIN0_DATA6
PRG2_PRU1_GPO PRG2_PRU1_GPI1
14
4
PRG2_PWM0_TZ_ GPIO0_14
OUT
BOOTMODE14
R27
GPMC0_AD15
VOUT1_DATA15
VIN0_DATA7
PRG2_PRU1_GPO PRG2_PRU1_GPI1 PRG2_PWM2_B2
15
5
GPIO0_15
BOOTMODE15
SOC_PADCONFIG_16
R28
GPMC0_CLK
VOUT1_DATA16
VIN0_PCLK
SOC_PADCONFIG_17
P25
GPMC0_ADVn_AL VOUT1_DATA17
E
GPIO0_17
BOOTMODE16
0x0011C048
SOC_PADCONFIG_18
P26
GPMC0_OEn_REn VOUT1_DATA18
GPIO0_18
BOOTMODE17
0x0011C04C
SOC_PADCONFIG_19
U28
GPMC0_WEn
VOUT1_DATA19
GPIO0_19
BOOTMODE18
0x0011C050
SOC_PADCONFIG_20
T28
GPMC0_BE0n_CL
E
VOUT1_DATA20
GPIO0_20
0x0011C054
SOC_PADCONFIG_21
P23
GPMC0_BE1n
VOUT1_DATA21
0x0011C058
SOC_PADCONFIG_22
R26
GPMC0_WAIT0
VOUT1_DATA22
0x0011C05C
SOC_PADCONFIG_23
R23
GPMC0_WAIT1
VOUT1_DATA23
0x0011C060
SOC_PADCONFIG_24
T25
GPMC0_WPn
VOUT1_VSYNC
0x0011C064
SOC_PADCONFIG_25
T24
GPMC0_DIR
VOUT1_HSYNC
0x0011C068
SOC_PADCONFIG_26
R24
GPMC0_CSn0
VOUT1_PCLK
0x0011C06C
SOC_PADCONFIG_27
T23
GPMC0_CSn1
VOUT1_DE
0x0011C070
SOC_PADCONFIG_28
R25
GPMC0_CSn2
0x0011C074
SOC_PADCONFIG_29
T27
GPMC0_CSn3
0x0011C078
SOC_PADCONFIG_30
AF18
PRG2_PRU0_GPO PRG2_PRU0_GPI0 PRG2_RGMII1_RD GPMC0_A25
0
0
TRC_CLK
EHRPWM0_SYNCI PRG2_PWM3_A0
GPIO0_30
0x0011C07C
SOC_PADCONFIG_31
AE18
PRG2_PRU0_GPO PRG2_PRU0_GPI1 PRG2_RGMII1_RD GPMC0_A24
1
1
TRC_CTL
EHRPWM0_SYNC SYNC2_OUT
O
GPIO0_31
0x0011C080
SOC_PADCONFIG_32
AH17
PRG2_PRU0_GPO PRG2_PRU0_GPI2 PRG2_RGMII1_RD GPMC0_A23
2
2
TRC_DATA0
EHRPWM_TZn_IN0 SYNC3_OUT
GPIO0_32
108
GPIO0_16
VIN0_HD
PRG2_PRU0_GPO PRG2_PRU0_GPI1 TIMER_IO2
17
7
PRG2_PWM2_TZ_I GPIO0_21
N
VIN0_VD
PRG2_PWM1_A0
PRG2_IEP1_EDC_ TIMER_IO3
LATCH_IN0
PRG2_IEP0_EDIO GPIO0_23
_DATA_IN_OUT28
VIN0_DATA8
PRG2_PWM1_B0
PRG2_IEP1_EDC_ TIMER_IO6
SYNC_OUT0
PRG2_IEP0_EDIO GPIO0_25
_DATA_IN_OUT29
VIN0_DATA9
PRG2_PRU1_GPO PRG2_PRU1_GPI1 TIMER_IO7
17
7
PRG2_PWM2_TZ_ GPIO0_27
OUT
VOUT1_EXTPCLKI VIN0_DATA10
N
GPMC0_A27
PRG2_IEP1_EDC_ I2C2_SDA
LATCH_IN1
PRG2_IEP0_EDIO GPIO0_28
_DATA_IN_OUT30
VIN0_DATA11
GPMC0_A26
PRG2_IEP1_EDC_ I2C2_SCL
SYNC_OUT1
PRG2_IEP0_EDIO GPIO0_29
_DATA_IN_OUT31
GPIO0_22
GPIO0_24
GPIO0_26
Terminal Configuration and Functions
Copyright © 2018–2019, Texas Instruments Incorporated
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Product Folder Links: DRA80M
DRA80M
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SPRSP31E – APRIL 2018 – REVISED JUNE 2019
Table 4-75. Pin Multiplexing (continued)
REGISTER NAME
MUXMODE[7:0] SETTINGS
0
1
2
3
4
5
6
7
0x0011C084
SOC_PADCONFIG_33
AG18
PRG2_PRU0_GPO PRG2_PRU0_GPI3 PRG2_RGMII1_RD GPMC0_A22
3
3
TRC_DATA1
EHRPWM0_A
PRG2_PWM3_B0
GPIO0_33
0x0011C088
SOC_PADCONFIG_34
AG17
PRG2_PRU0_GPO PRG2_PRU0_GPI4 PRG2_RGMII1_RX GPMC0_A21
4
_CTL
TRC_DATA2
EHRPWM0_B
PRG2_PWM0_A0
GPIO0_34
0x0011C08C
SOC_PADCONFIG_35
AF17
PRG2_PRU0_GPO PRG2_PRU0_GPI5 PRG2_RGMII1_RX GPMC0_A20
5
C
TRC_DATA3
EHRPWM1_A
PRG2_PWM3_A1
GPIO0_35
0x0011C090
SOC_PADCONFIG_36
AE17
PRG2_PRU0_GPO PRG2_PRU0_GPI6 PRG2_RGMII1_TX GPMC0_A19
6
_CTL
TRC_DATA4
EHRPWM1_B
PRG2_PWM3_B1
GPIO0_36
0x0011C094
SOC_PADCONFIG_37
AC19
PRG2_PRU0_GPO PRG2_PRU0_GPI7 PRG2_MDIO0_MDI GPMC0_A18
7
O
TRC_DATA5
EHRPWM_TZn_IN1 EHRPWM_SOCA
GPIO0_37
0x0011C098
SOC_PADCONFIG_38
AH16
PRG2_PRU0_GPO PRG2_PRU0_GPI8 PRG2_RGMII1_TD GPMC0_A17
8
0
TRC_DATA6
EHRPWM2_A
GPIO0_38
0x0011C09C
SOC_PADCONFIG_39
AG16
PRG2_PRU0_GPO PRG2_PRU0_GPI9 PRG2_RGMII1_TD GPMC0_A16
9
1
TRC_DATA7
EHRPWM2_B
GPIO0_39
0x0011C0A0
SOC_PADCONFIG_40
AF16
PRG2_PRU0_GPO PRG2_PRU0_GPI1 PRG2_RGMII1_TD GPMC0_A15
10
0
2
TRC_DATA8
EHRPWM_TZn_IN2 EHRPWM_SOCB
GPIO0_40
0x0011C0A4
SOC_PADCONFIG_41
AE16
PRG2_PRU0_GPO PRG2_PRU0_GPI1 PRG2_RGMII1_TD GPMC0_A14
11
1
3
TRC_DATA9
PRG2_ECAP0_IN_ GPIO0_41
APWM_OUT
0x0011C0A8
SOC_PADCONFIG_42
AD16
PRG2_PRU0_GPO PRG2_PRU0_GPI1 PRG2_RGMII1_TX GPMC0_A13
16
6
C
TRC_DATA10
PRG2_PWM0_A1
GPIO0_42
0x0011C0AC
SOC_PADCONFIG_43
AH15
PRG2_PRU1_GPO PRG2_PRU1_GPI0 PRG2_RGMII2_RD GPMC0_A12
0
0
TRC_DATA11
EHRPWM3_A
PRG2_PWM3_A2
GPIO0_43
0x0011C0B0
SOC_PADCONFIG_44
AC16
PRG2_PRU1_GPO PRG2_PRU1_GPI1 PRG2_RGMII2_RD GPMC0_A11
1
1
TRC_DATA12
EHRPWM3_B
PRG2_PWM3_B2
GPIO0_44
0x0011C0B4
SOC_PADCONFIG_45
AD17
PRG2_PRU1_GPO PRG2_PRU1_GPI2 PRG2_RGMII2_RD GPMC0_A10
2
2
TRC_DATA13
EHRPWM3_SYNCI PRG2_PWM0_B1
GPIO0_45
0x0011C0B8
SOC_PADCONFIG_46
AH14
PRG2_PRU1_GPO PRG2_PRU1_GPI3 PRG2_RGMII2_RD GPMC0_A9
3
3
TRC_DATA14
EHRPWM3_SYNC
O
GPIO0_46
0x0011C0BC
SOC_PADCONFIG_47
AG14
PRG2_PRU1_GPO PRG2_PRU1_GPI4 PRG2_RGMII2_RX GPMC0_A8
4
_CTL
TRC_DATA15
EHRPWM_TZn_IN3 PRG2_ECAP0_SY GPIO0_47
NC_OUT
0x0011C0C0
SOC_PADCONFIG_48
AG15
PRG2_PRU1_GPO PRG2_PRU1_GPI5 PRG2_RGMII2_RX GPMC0_A7
5
C
TRC_DATA16
EHRPWM4_A
GPIO0_48
0x0011C0C4
SOC_PADCONFIG_49
AC17
PRG2_PRU1_GPO PRG2_PRU1_GPI6 PRG2_RGMII2_TX GPMC0_A6
6
_CTL
TRC_DATA17
EHRPWM4_B
GPIO0_49
0x0011C0C8
SOC_PADCONFIG_50
AE15
PRG2_PRU1_GPO PRG2_PRU1_GPI7 PRG2_MDIO0_MD GPMC0_A5
7
C
TRC_DATA18
EHRPWM_TZn_IN4 PRG2_PWM3_TZ_I GPIO0_50
N
0x0011C0CC
SOC_PADCONFIG_51
AD15
PRG2_PRU1_GPO PRG2_PRU1_GPI8 PRG2_RGMII2_TD GPMC0_A4
8
0
TRC_DATA19
EHRPWM5_A
PRG2_PWM0_A2
0x0011C0D0
SOC_PADCONFIG_52
AF14
PRG2_PRU1_GPO PRG2_PRU1_GPI9 PRG2_RGMII2_TD GPMC0_A3
9
1
TRC_DATA20
EHRPWM5_B
PRG2_PWM3_TZ_ GPIO0_52
OUT
0x0011C0D4
SOC_PADCONFIG_53
AC15
PRG2_PRU1_GPO PRG2_PRU1_GPI1 PRG2_RGMII2_TD GPMC0_A2
10
0
2
TRC_DATA21
EHRPWM_TZn_IN5 PRG2_PWM0_B2
0x0011C0D8
SOC_PADCONFIG_54
AD14
PRG2_PRU1_GPO PRG2_PRU1_GPI1 PRG2_RGMII2_TD GPMC0_A1
11
1
3
TRC_DATA22
PRG2_ECAP0_SY GPIO0_54
NC_IN
0x0011C0DC
SOC_PADCONFIG_55
AE14
PRG2_PRU1_GPO PRG2_PRU1_GPI1 PRG2_RGMII2_TX GPMC0_A0
16
6
C
TRC_DATA23
PRG2_PWM1_TZ_ GPIO0_55
OUT
0x0011C0E0
SOC_PADCONFIG_56
AE22
PRG1_PRU0_GPO PRG1_PRU0_GPI0 PRG1_RGMII1_RD PRG1_PWM3_A0
0
0
PRG2_PWM0_B0
Bootstrap
GPIO0_51
GPIO0_53
GPIO0_56
Terminal Configuration and Functions
Copyright © 2018–2019, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: DRA80M
ADVANCE INFORMATION
ADDRESS
BALL
NUMBER
109
DRA80M
SPRSP31E – APRIL 2018 – REVISED JUNE 2019
www.ti.com
Table 4-75. Pin Multiplexing (continued)
ADDRESS
REGISTER NAME
BALL
NUMBER
MUXMODE[7:0] SETTINGS
0
1
2
3
4
5
6
7
ADVANCE INFORMATION
0x0011C0E4
SOC_PADCONFIG_57
AG24
PRG1_PRU0_GPO PRG1_PRU0_GPI1 PRG1_RGMII1_RD PRG1_PWM3_B0
1
1
GPIO0_57
0x0011C0E8
SOC_PADCONFIG_58
AF23
PRG1_PRU0_GPO PRG1_PRU0_GPI2 PRG1_RGMII1_RD PRG1_PWM2_A0
2
2
GPIO0_58
0x0011C0EC
SOC_PADCONFIG_59
AD21
PRG1_PRU0_GPO PRG1_PRU0_GPI3 PRG1_RGMII1_RD PRG1_PWM3_A2
3
3
GPIO0_59
0x0011C0F0
SOC_PADCONFIG_60
AG23
PRG1_PRU0_GPO PRG1_PRU0_GPI4 PRG1_RGMII1_RX PRG1_PWM2_B0
4
_CTL
GPIO0_60
0x0011C0F4
SOC_PADCONFIG_61
AF27
PRG1_PRU0_GPO PRG1_PRU0_GPI5
5
PRG1_PWM3_B2
GPIO0_61
0x0011C0F8
SOC_PADCONFIG_62
AF22
PRG1_PRU0_GPO PRG1_PRU0_GPI6 PRG1_RGMII1_RX PRG1_PWM3_A1
6
C
GPIO0_62
0x0011C0FC
SOC_PADCONFIG_63
AG27
PRG1_PRU0_GPO PRG1_PRU0_GPI7 PRG1_IEP0_EDC_ PRG1_PWM3_B1
7
LATCH_IN1
GPIO0_63
0x0011C100
SOC_PADCONFIG_64
AF28
PRG1_PRU0_GPO PRG1_PRU0_GPI8
8
GPIO0_64
0x0011C104
SOC_PADCONFIG_65
AF26
PRG1_PRU0_GPO PRG1_PRU0_GPI9 PRG1_UART0_CT PRG1_PWM3_TZ_I SPI2_CS1
9
Sn
N
PRG1_IEP0_EDIO GPIO0_65
_DATA_IN_OUT28
0x0011C108
SOC_PADCONFIG_66
AH25
PRG1_PRU0_GPO PRG1_PRU0_GPI1 PRG1_UART0_RT PRG1_PWM2_B1
10
0
Sn
PRG1_IEP0_EDIO GPIO0_66
_DATA_IN_OUT29
0x0011C10C
SOC_PADCONFIG_67
AF21
PRG1_PRU0_GPO PRG1_PRU0_GPI1 PRG1_RGMII1_TX PRG1_PWM3_TZ_
11
1
_CTL
OUT
GPIO0_67
0x0011C110
SOC_PADCONFIG_68
AH20
PRG1_PRU0_GPO PRG1_PRU0_GPI1 PRG1_RGMII1_TD PRG1_PWM0_A0
12
2
0
GPIO0_68
0x0011C114
SOC_PADCONFIG_69
AH21
PRG1_PRU0_GPO PRG1_PRU0_GPI1 PRG1_RGMII1_TD PRG1_PWM0_B0
13
3
1
GPIO0_69
0x0011C118
SOC_PADCONFIG_70
AG20
PRG1_PRU0_GPO PRG1_PRU0_GPI1 PRG1_RGMII1_TD PRG1_PWM0_A1
14
4
2
GPIO0_70
0x0011C11C
SOC_PADCONFIG_71
AD19
PRG1_PRU0_GPO PRG1_PRU0_GPI1 PRG1_RGMII1_TD PRG1_PWM0_B1
15
5
3
GPIO0_71
0x0011C120
SOC_PADCONFIG_72
AD20
PRG1_PRU0_GPO PRG1_PRU0_GPI1 PRG1_RGMII1_TX PRG1_PWM0_A2
16
6
C
GPIO0_72
0x0011C124
SOC_PADCONFIG_73
AH26
PRG1_PRU0_GPO PRG1_PRU0_GPI1 PRG1_IEP0_EDC_ PRG1_PWM0_B2
17
7
SYNC_OUT1
GPIO0_73
0x0011C128
SOC_PADCONFIG_74
AG25
PRG1_PRU0_GPO PRG1_PRU0_GPI1 PRG1_IEP0_EDC_ PRG1_PWM0_TZ_I
18
8
LATCH_IN0
N
GPIO0_74
0x0011C12C
SOC_PADCONFIG_75
AG26
PRG1_PRU0_GPO PRG1_PRU0_GPI1 PRG1_IEP0_EDC_ PRG1_PWM0_TZ_
19
9
SYNC_OUT0
OUT
GPIO0_75
0x0011C130
SOC_PADCONFIG_76
AH24
PRG1_PRU1_GPO PRG1_PRU1_GPI0 PRG1_RGMII2_RD
0
0
GPIO0_76
0x0011C134
SOC_PADCONFIG_77
AH23
PRG1_PRU1_GPO PRG1_PRU1_GPI1 PRG1_RGMII2_RD
1
1
GPIO0_77
0x0011C138
SOC_PADCONFIG_78
AG21
PRG1_PRU1_GPO PRG1_PRU1_GPI2 PRG1_RGMII2_RD PRG1_PWM2_A2
2
2
GPIO0_78
0x0011C13C
SOC_PADCONFIG_79
AH22
PRG1_PRU1_GPO PRG1_PRU1_GPI3 PRG1_RGMII2_RD
3
3
EQEP1_A
GPIO0_79
0x0011C140
SOC_PADCONFIG_80
AE21
PRG1_PRU1_GPO PRG1_PRU1_GPI4 PRG1_RGMII2_RX PRG1_PWM2_B2
4
_CTL
EQEP1_B
GPIO0_80
110
PRG1_PWM2_A1
Terminal Configuration and Functions
SPI2_CS2
Bootstrap
Copyright © 2018–2019, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: DRA80M
DRA80M
www.ti.com
SPRSP31E – APRIL 2018 – REVISED JUNE 2019
Table 4-75. Pin Multiplexing (continued)
REGISTER NAME
MUXMODE[7:0] SETTINGS
0
1
2
3
4
5
6
EQEP1_S
7
0x0011C144
SOC_PADCONFIG_81
AC22
PRG1_PRU1_GPO PRG1_PRU1_GPI5
5
0x0011C148
SOC_PADCONFIG_82
AG22
PRG1_PRU1_GPO PRG1_PRU1_GPI6 PRG1_RGMII2_RX
6
C
0x0011C14C
SOC_PADCONFIG_83
AD23
PRG1_PRU1_GPO PRG1_PRU1_GPI7 PRG1_IEP1_EDC_
7
LATCH_IN1
0x0011C150
SOC_PADCONFIG_84
AE24
PRG1_PRU1_GPO PRG1_PRU1_GPI8
8
0x0011C154
SOC_PADCONFIG_85
AF25
PRG1_PRU1_GPO PRG1_PRU1_GPI9 PRG1_UART0_RX
9
D
0x0011C158
SOC_PADCONFIG_86
AF24
PRG1_PRU1_GPO PRG1_PRU1_GPI1 PRG1_UART0_TX
10
0
D
0x0011C15C
SOC_PADCONFIG_87
AC20
PRG1_PRU1_GPO PRG1_PRU1_GPI1 PRG1_RGMII2_TX
11
1
_CTL
0x0011C160
SOC_PADCONFIG_88
AE20
PRG1_PRU1_GPO PRG1_PRU1_GPI1 PRG1_RGMII2_TD PRG1_PWM1_A0
12
2
0
GPIO0_88
0x0011C164
SOC_PADCONFIG_89
AF19
PRG1_PRU1_GPO PRG1_PRU1_GPI1 PRG1_RGMII2_TD PRG1_PWM1_B0
13
3
1
GPIO0_89
0x0011C168
SOC_PADCONFIG_90
AH19
PRG1_PRU1_GPO PRG1_PRU1_GPI1 PRG1_RGMII2_TD PRG1_PWM1_A1
14
4
2
GPIO0_90
0x0011C16C
SOC_PADCONFIG_91
AG19
PRG1_PRU1_GPO PRG1_PRU1_GPI1 PRG1_RGMII2_TD PRG1_PWM1_B1
15
5
3
GPIO0_91
0x0011C170
SOC_PADCONFIG_92
AE19
PRG1_PRU1_GPO PRG1_PRU1_GPI1 PRG1_RGMII2_TX PRG1_PWM1_A2
16
6
C
GPIO0_92
0x0011C174
SOC_PADCONFIG_93
AE23
PRG1_PRU1_GPO PRG1_PRU1_GPI1 PRG1_IEP1_EDC_ PRG1_PWM1_B2
17
7
SYNC_OUT1
0x0011C178
SOC_PADCONFIG_94
AD22
0x0011C17C
SOC_PADCONFIG_95
0x0011C180
Bootstrap
GPIO0_81
GPIO0_82
SPI2_CS0
UART1_TXD
PRG1_PWM2_TZ_
OUT
GPIO0_83
GPIO0_84
PRG1_IEP0_EDIO GPIO0_85
_DATA_IN_OUT30
PRG1_PWM2_TZ_I SPI2_CS3
N
PRG1_IEP0_EDIO GPIO0_86
_DATA_IN_OUT31
EQEP1_I
SPI2_CLK
GPIO0_87
PRG1_ECAP0_SY UART1_RXD
NC_OUT
GPIO0_93
PRG1_PRU1_GPO PRG1_PRU1_GPI1 PRG1_IEP1_EDC_ PRG1_PWM1_TZ_I SPI2_D0
18
8
LATCH_IN0
N
PRG1_ECAP0_SY UART1_CTSn
NC_IN
GPIO0_94
AC21
PRG1_PRU1_GPO PRG1_PRU1_GPI1 PRG1_IEP1_EDC_ PRG1_PWM1_TZ_ SPI2_D1
19
9
SYNC_OUT0
OUT
PRG1_ECAP0_IN_ UART1_RTSn
APWM_OUT
GPIO0_95
SOC_PADCONFIG_96
AD18
PRG1_MDIO0_MDI SPI1_CS2
O
PRG2_PWM1_A1
GPIO1_0
0x0011C184
SOC_PADCONFIG_97
AH18
PRG1_MDIO0_MD SPI1_CS3
C
PRG2_PWM1_B1
GPIO1_1
0x0011C188
SOC_PADCONFIG_98
D25
MMC0_DAT7
UART0_DCDn
EQEP2_A
GPIO1_2
0x0011C18C
SOC_PADCONFIG_99
B26
MMC0_DAT6
UART0_DSRn
EQEP2_B
GPIO1_3
0x0011C190
SOC_PADCONFIG_100
A24
MMC0_DAT5
UART0_DTRn
EQEP2_I
GPIO1_4
0x0011C194
SOC_PADCONFIG_101
E24
MMC0_DAT4
UART0_RIN
EQEP2_S
GPIO1_5
0x0011C198
SOC_PADCONFIG_102
A25
MMC0_DAT3
GPIO1_6
0x0011C19C
SOC_PADCONFIG_103
C26
MMC0_DAT2
GPIO1_7
0x0011C1A0
SOC_PADCONFIG_104
E25
MMC0_DAT1
GPIO1_8
0x0011C1A4
SOC_PADCONFIG_105
A26
MMC0_DAT0
GPIO1_9
0x0011C1A8
SOC_PADCONFIG_106
B25
MMC0_CLK
GPIO1_10
0x0011C1AC
SOC_PADCONFIG_107
B27
MMC0_CMD
GPIO1_11
0x0011C1B0
SOC_PADCONFIG_108
C25
MMC0_DS
GPIO1_12
Terminal Configuration and Functions
Copyright © 2018–2019, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: DRA80M
ADVANCE INFORMATION
ADDRESS
BALL
NUMBER
111
DRA80M
SPRSP31E – APRIL 2018 – REVISED JUNE 2019
www.ti.com
Table 4-75. Pin Multiplexing (continued)
ADDRESS
REGISTER NAME
MUXMODE[7:0] SETTINGS
BALL
NUMBER
0
1
2
3
4
5
6
7
ADVANCE INFORMATION
0x0011C1B4
SOC_PADCONFIG_109
A23
MMC0_SDCD
PRG2_IEP0_EDIO GPIO1_13
_OUTVALID
0x0011C1B8
SOC_PADCONFIG_110
B23
MMC0_SDWP
GPIO1_14
0x0011C1BC
SOC_PADCONFIG_111
AG13
SPI0_CS0
0x0011C1C0
SOC_PADCONFIG_112
AF13
SPI0_CS1
0x0011C1C4
SOC_PADCONFIG_113
AH13
SPI0_CLK
GPIO1_17
0x0011C1C8
SOC_PADCONFIG_114
AE13
SPI0_D0
GPIO1_18
0x0011C1CC
SOC_PADCONFIG_115
AD13
SPI0_D1
0x0011C1D0
SOC_PADCONFIG_116
AD12
SPI1_CS0
0x0011C1D4
SOC_PADCONFIG_117
AG12
SPI1_CS1
0x0011C1D8
SOC_PADCONFIG_118
AH12
SPI1_CLK
PRG2_IEP0_EDC_ PRG2_UART0_RT
SYNC_OUT0
Sn
GPIO1_22
0x0011C1DC
SOC_PADCONFIG_119
AE12
SPI1_D0
PRG2_IEP0_EDC_ PRG2_UART0_RX
LATCH_IN1
D
GPIO1_23
0x0011C1E0
SOC_PADCONFIG_120
AF12
SPI1_D1
PRG2_IEP0_EDC_ PRG2_UART0_TX
SYNC_OUT1
D
GPIO1_24
0x0011C1E4
SOC_PADCONFIG_121
AF11
UART0_RXD
0x0011C1E8
SOC_PADCONFIG_122
AE11
UART0_TXD
0x0011C1EC
SOC_PADCONFIG_123
AG11
UART0_CTSn
TIMER_IO4
SPI0_CS2
0x0011C1F0
SOC_PADCONFIG_124
AD11
UART0_RTSn
TIMER_IO5
SPI0_CS3
0x0011C1F4
SOC_PADCONFIG_125
V24
PRG0_PRU0_GPO PRG0_PRU0_GPI0 PRG0_RGMII1_RD PRG0_PWM3_A0
0
0
MCASP0_ACLKX
GPIO1_29
0x0011C1F8
SOC_PADCONFIG_126
W25
PRG0_PRU0_GPO PRG0_PRU0_GPI1 PRG0_RGMII1_RD PRG0_PWM3_B0
1
1
MCASP0_AFSX
GPIO1_30
0x0011C1FC
SOC_PADCONFIG_127
W24
PRG0_PRU0_GPO PRG0_PRU0_GPI2 PRG0_RGMII1_RD PRG0_PWM2_A0
2
2
MCASP0_ACLKR
GPIO1_31
0x0011C200
SOC_PADCONFIG_128
AA27
PRG0_PRU0_GPO PRG0_PRU0_GPI3 PRG0_RGMII1_RD PRG0_PWM3_A2
3
3
MCASP0_AFSR
GPIO1_32
0x0011C204
SOC_PADCONFIG_129
Y24
PRG0_PRU0_GPO PRG0_PRU0_GPI4 PRG0_RGMII1_RX PRG0_PWM2_B0
4
_CTL
MCASP0_AXR0
GPIO1_33
0x0011C208
SOC_PADCONFIG_130
V28
PRG0_PRU0_GPO PRG0_PRU0_GPI5
5
PRG0_PWM3_B2
MCASP0_AXR1
GPIO1_34
0x0011C20C
SOC_PADCONFIG_131
Y25
PRG0_PRU0_GPO PRG0_PRU0_GPI6 PRG0_RGMII1_RX PRG0_PWM3_A1
6
C
MCASP0_AXR2
GPIO1_35
0x0011C210
SOC_PADCONFIG_132
U27
PRG0_PRU0_GPO PRG0_PRU0_GPI7 PRG0_IEP0_EDC_ PRG0_PWM3_B1
7
LATCH_IN1
PRG0_ECAP0_SY MCASP0_AXR3
NC_IN
GPIO1_36
0x0011C214
SOC_PADCONFIG_133
V27
PRG0_PRU0_GPO PRG0_PRU0_GPI8
8
MCASP0_AXR4
GPIO1_37
0x0011C218
SOC_PADCONFIG_134
V26
PRG0_PRU0_GPO PRG0_PRU0_GPI9 PRG0_UART0_CT PRG0_PWM3_TZ_I SPI3_CS1
9
Sn
N
MCASP0_AXR5
PRG0_IEP0_EDIO GPIO1_38
_DATA_IN_OUT28
0x0011C21C
SOC_PADCONFIG_135
U25
PRG0_PRU0_GPO PRG0_PRU0_GPI1 PRG0_UART0_RT PRG0_PWM2_B1
10
0
Sn
MCASP0_AXR6
PRG0_IEP0_EDIO GPIO1_39
_DATA_IN_OUT29
112
Bootstrap
GPIO1_15
CPTS0_TS_COMP I2C3_SCL
PRG1_IEP0_EDIO GPIO1_16
_OUTVALID
GPIO1_19
PRG2_IEP0_EDC_ PRG2_UART0_CT
LATCH_IN0
Sn
CPTS0_TS_SYNC
PRG0_IEP0_EDIO GPIO1_20
_OUTVALID
I2C3_SDA
GPIO1_21
GPIO1_25
GPIO1_26
GPIO1_27
GPIO1_28
PRG0_PWM2_A1
Terminal Configuration and Functions
SPI3_CS2
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DRA80M
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SPRSP31E – APRIL 2018 – REVISED JUNE 2019
Table 4-75. Pin Multiplexing (continued)
REGISTER NAME
MUXMODE[7:0] SETTINGS
0
1
2
3
4
5
6
7
0x0011C220
SOC_PADCONFIG_136
AB25
PRG0_PRU0_GPO PRG0_PRU0_GPI1 PRG0_RGMII1_TX PRG0_PWM3_TZ_
11
1
_CTL
OUT
MCASP0_AXR7
GPIO1_40
0x0011C224
SOC_PADCONFIG_137
AD27
PRG0_PRU0_GPO PRG0_PRU0_GPI1 PRG0_RGMII1_TD PRG0_PWM0_A0
12
2
0
MCASP0_AXR8
GPIO1_41
0x0011C228
SOC_PADCONFIG_138
AC26
PRG0_PRU0_GPO PRG0_PRU0_GPI1 PRG0_RGMII1_TD PRG0_PWM0_B0
13
3
1
MCASP0_AXR9
GPIO1_42
0x0011C22C
SOC_PADCONFIG_139
AD26
PRG0_PRU0_GPO PRG0_PRU0_GPI1 PRG0_RGMII1_TD PRG0_PWM0_A1
14
4
2
MCASP0_AXR10
GPIO1_43
0x0011C230
SOC_PADCONFIG_140
AA24
PRG0_PRU0_GPO PRG0_PRU0_GPI1 PRG0_RGMII1_TD PRG0_PWM0_B1
15
5
3
MCASP0_AXR11
GPIO1_44
0x0011C234
SOC_PADCONFIG_141
AD28
PRG0_PRU0_GPO PRG0_PRU0_GPI1 PRG0_RGMII1_TX PRG0_PWM0_A2
16
6
C
MCASP0_AXR12
MCASP1_AHCLKR GPIO1_45
0x0011C238
SOC_PADCONFIG_142
U26
PRG0_PRU0_GPO PRG0_PRU0_GPI1 PRG0_IEP0_EDC_ PRG0_PWM0_B2
17
7
SYNC_OUT1
PRG0_ECAP0_SY MCASP0_AXR13
NC_OUT
MCASP1_AHCLKX GPIO1_46
0x0011C23C
SOC_PADCONFIG_143
V25
PRG0_PRU0_GPO PRG0_PRU0_GPI1 PRG0_IEP0_EDC_ PRG0_PWM0_TZ_I PRG0_ECAP0_IN_ MCASP0_AXR14
18
8
LATCH_IN0
N
APWM_OUT
MCASP2_AHCLKR GPIO1_47
0x0011C240
SOC_PADCONFIG_144
U24
PRG0_PRU0_GPO PRG0_PRU0_GPI1 PRG0_IEP0_EDC_ PRG0_PWM0_TZ_
19
9
SYNC_OUT0
OUT
MCASP0_AXR15
MCASP2_AHCLKX GPIO1_48
0x0011C244
SOC_PADCONFIG_145
AB28
PRG0_PRU1_GPO PRG0_PRU1_GPI0 PRG0_RGMII2_RD
0
0
MCASP1_ACLKX
GPIO1_49
0x0011C248
SOC_PADCONFIG_146
AC28
PRG0_PRU1_GPO PRG0_PRU1_GPI1 PRG0_RGMII2_RD
1
1
MCASP1_AFSX
GPIO1_50
0x0011C24C
SOC_PADCONFIG_147
AC27
PRG0_PRU1_GPO PRG0_PRU1_GPI2 PRG0_RGMII2_RD PRG0_PWM2_A2
2
2
MCASP1_ACLKR
GPIO1_51
0x0011C250
SOC_PADCONFIG_148
AB26
PRG0_PRU1_GPO PRG0_PRU1_GPI3 PRG0_RGMII2_RD
3
3
EQEP0_A
MCASP1_AFSR
GPIO1_52
0x0011C254
SOC_PADCONFIG_149
AA25
PRG0_PRU1_GPO PRG0_PRU1_GPI4 PRG0_RGMII2_RX PRG0_PWM2_B2
4
_CTL
EQEP0_B
MCASP1_AXR0
MCASP0_AHCLKR GPIO1_53
0x0011C258
SOC_PADCONFIG_150
U23
PRG0_PRU1_GPO PRG0_PRU1_GPI5
5
EQEP0_S
MCASP1_AXR1
MCASP0_AHCLKX GPIO1_54
0x0011C25C
SOC_PADCONFIG_151
AB27
PRG0_PRU1_GPO PRG0_PRU1_GPI6 PRG0_RGMII2_RX
6
C
MCASP1_AXR2
GPIO1_55
0x0011C260
SOC_PADCONFIG_152
W28
PRG0_PRU1_GPO PRG0_PRU1_GPI7 PRG0_IEP1_EDC_
7
LATCH_IN1
0x0011C264
SOC_PADCONFIG_153
W27
PRG0_PRU1_GPO PRG0_PRU1_GPI8
8
0x0011C268
SOC_PADCONFIG_154
Y28
PRG0_PRU1_GPO PRG0_PRU1_GPI9 PRG0_UART0_RX
9
D
0x0011C26C
SOC_PADCONFIG_155
AA28
PRG0_PRU1_GPO PRG0_PRU1_GPI1 PRG0_UART0_TX
10
0
D
0x0011C270
SOC_PADCONFIG_156
AB24
0x0011C274
SOC_PADCONFIG_157
0x0011C278
0x0011C27C
SPI3_CS0
PRG0_PWM2_TZ_
OUT
MCASP1_AXR3
UART2_TXD
GPIO1_56
MCASP1_AXR4
GPIO1_57
MCASP1_AXR5
PRG0_IEP0_EDIO GPIO1_58
_DATA_IN_OUT30
MCASP1_AXR6
PRG0_IEP0_EDIO GPIO1_59
_DATA_IN_OUT31
PRG0_PRU1_GPO PRG0_PRU1_GPI1 PRG0_RGMII2_TX
11
1
_CTL
MCASP1_AXR7
GPIO1_60
AC25
PRG0_PRU1_GPO PRG0_PRU1_GPI1 PRG0_RGMII2_TD PRG0_PWM1_A0
12
2
0
MCASP1_AXR8
GPIO1_61
SOC_PADCONFIG_158
AD25
PRG0_PRU1_GPO PRG0_PRU1_GPI1 PRG0_RGMII2_TD PRG0_PWM1_B0
13
3
1
MCASP1_AXR9
GPIO1_62
SOC_PADCONFIG_159
AD24
PRG0_PRU1_GPO PRG0_PRU1_GPI1 PRG0_RGMII2_TD PRG0_PWM1_A1
14
4
2
MCASP2_AFSR
GPIO1_63
SPI3_CS3
PRG0_PWM2_TZ_I EQEP0_I
N
Bootstrap
Terminal Configuration and Functions
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ADVANCE INFORMATION
ADDRESS
BALL
NUMBER
113
DRA80M
SPRSP31E – APRIL 2018 – REVISED JUNE 2019
www.ti.com
Table 4-75. Pin Multiplexing (continued)
ADDRESS
REGISTER NAME
MUXMODE[7:0] SETTINGS
BALL
NUMBER
0
1
2
3
4
5
6
7
ADVANCE INFORMATION
0x0011C280
SOC_PADCONFIG_160
AE27
PRG0_PRU1_GPO PRG0_PRU1_GPI1 PRG0_RGMII2_TD PRG0_PWM1_B1
15
5
3
MCASP2_ACLKR
GPIO1_64
0x0011C284
SOC_PADCONFIG_161
AC24
PRG0_PRU1_GPO PRG0_PRU1_GPI1 PRG0_RGMII2_TX PRG0_PWM1_A2
16
6
C
MCASP2_AXR0
GPIO1_65
0x0011C288
SOC_PADCONFIG_162
Y27
PRG0_PRU1_GPO PRG0_PRU1_GPI1 PRG0_IEP1_EDC_ PRG0_PWM1_B2
17
7
SYNC_OUT1
0x0011C28C
SOC_PADCONFIG_163
Y26
0x0011C290
SOC_PADCONFIG_164
0x0011C294
MCASP2_AXR1
UART2_RXD
GPIO1_66
PRG0_PRU1_GPO PRG0_PRU1_GPI1 PRG0_IEP1_EDC_ PRG0_PWM1_TZ_I SPI3_D0
18
8
LATCH_IN0
N
MCASP2_AFSX
UART2_CTSn
GPIO1_67
W26
PRG0_PRU1_GPO PRG0_PRU1_GPI1 PRG0_IEP1_EDC_ PRG0_PWM1_TZ_ SPI3_D1
19
9
SYNC_OUT0
OUT
MCASP2_ACLKX
UART2_RTSn
GPIO1_68
SOC_PADCONFIG_165
AE26
PRG0_MDIO0_MDI
O
PRG2_PWM1_A2
MCASP2_AXR2
GPIO1_69
0x0011C298
SOC_PADCONFIG_166
AE28
PRG0_MDIO0_MD
C
PRG2_PWM1_B2
MCASP2_AXR3
GPIO1_70
0x0011C29C
SOC_PADCONFIG_167
F18
NMIn
0x0011C2A0
SOC_PADCONFIG_168
F17
RESETz
0x0011C2A4
SOC_PADCONFIG_169
D19
RESETSTATz
0x0011C2A8
SOC_PADCONFIG_170
C19
PORz_OUT
0x0011C2AC
SOC_PADCONFIG_171
E20
SOC_SAFETY_ER
RORn
0x0011C2B0
SOC_PADCONFIG_172
C20
TDI
0x0011C2B4
SOC_PADCONFIG_173
A20
TDO
0x0011C2B8
SOC_PADCONFIG_174
A21
TMS
0x0011C2BC
SOC_PADCONFIG_175
AD9
USB0_DRVVBUS
GPIO1_71
0x0011C2C0
SOC_PADCONFIG_176
AC8
USB1_DRVVBUS
GPIO1_72
0x0011C2C4
SOC_PADCONFIG_177
D27
MMC1_DAT3
GPIO1_73
0x0011C2C8
SOC_PADCONFIG_178
D26
MMC1_DAT2
GPIO1_74
0x0011C2CC
SOC_PADCONFIG_179
E27
MMC1_DAT1
GPIO1_75
0x0011C2D0
SOC_PADCONFIG_180
D28
MMC1_DAT0
GPIO1_76
0x0011C2D4
SOC_PADCONFIG_181
C27
MMC1_CLK
GPIO1_77
0x0011C2D8
SOC_PADCONFIG_182
C28
MMC1_CMD
GPIO1_78
0x0011C2DC
SOC_PADCONFIG_183
B24
MMC1_SDCD
GPIO1_79
0x0011C2E0
SOC_PADCONFIG_184
C24
MMC1_SDWP
GPIO1_80
0x0011C2E8
SOC_PADCONFIG_186
D20
I2C0_SCL
0x0011C2EC
SOC_PADCONFIG_187
C21
I2C0_SDA
0x0011C2F0
SOC_PADCONFIG_188
B21
I2C1_SCL
CPTS0_HW1TSPU
SH
0x0011C2F4
SOC_PADCONFIG_189
E21
I2C1_SDA
CPTS0_HW2TSPU
SH
0x0011C2F8
SOC_PADCONFIG_190
D21
ECAP0_IN_APWM SYNC0_OUT
_OUT
0x0011C2FC
SOC_PADCONFIG_191
A22
EXT_REFCLK1
114
SPI3_CLK
Bootstrap
PRG2_PWM1_TZ_I
N
CPTS0_RFT_CLK
SYNC1_OUT
GPIO1_86
GPIO1_87
Terminal Configuration and Functions
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SPRSP31E – APRIL 2018 – REVISED JUNE 2019
Table 4-75. Pin Multiplexing (continued)
REGISTER NAME
MUXMODE[7:0] SETTINGS
0
1
2
3
4
5
6
7
0x0011C300
SOC_PADCONFIG_192
B22
TIMER_IO0
SYSCLKOUT0
GPIO1_88
0x0011C304
SOC_PADCONFIG_193
C23
TIMER_IO1
OBSCLK0
GPIO1_89
0x0011C308
SOC_PADCONFIG_194
E19
PORz
0x4301C000
WKUP_PADCONFIG_0
V1
MCU_OSPI0_CLK
MCU_HYPERBUS0
_CK
WKUP_GPIO0_12
0x4301C004
WKUP_PADCONFIG_1
U1
MCU_OSPI0_LBCL MCU_HYPERBUS0
KO
_CKn
WKUP_GPIO0_13
0x4301C008
WKUP_PADCONFIG_2
U2
MCU_OSPI0_DQS MCU_HYPERBUS0
_RWDS
WKUP_GPIO0_14
0x4301C00C
WKUP_PADCONFIG_3
U4
MCU_OSPI0_D0
MCU_HYPERBUS0
_DQ0
WKUP_GPIO0_15
0x4301C010
WKUP_PADCONFIG_4
U5
MCU_OSPI0_D1
MCU_HYPERBUS0
_DQ1
WKUP_GPIO0_16
0x4301C014
WKUP_PADCONFIG_5
T2
MCU_OSPI0_D2
MCU_HYPERBUS0
_DQ2
WKUP_GPIO0_17
0x4301C018
WKUP_PADCONFIG_6
T3
MCU_OSPI0_D3
MCU_HYPERBUS0
_DQ3
WKUP_GPIO0_18
0x4301C01C
WKUP_PADCONFIG_7
T4
MCU_OSPI0_D4
MCU_HYPERBUS0
_DQ4
WKUP_GPIO0_19
0x4301C020
WKUP_PADCONFIG_8
T5
MCU_OSPI0_D5
MCU_HYPERBUS0
_DQ5
WKUP_GPIO0_20
0x4301C024
WKUP_PADCONFIG_9
R2
MCU_OSPI0_D6
MCU_HYPERBUS0
_DQ6
WKUP_GPIO0_21
0x4301C028
WKUP_PADCONFIG_10
R3
MCU_OSPI0_D7
MCU_HYPERBUS0
_DQ7
WKUP_GPIO0_22
0x4301C02C
WKUP_PADCONFIG_11
R4
MCU_OSPI0_CSn0 MCU_HYPERBUS0
_CSn0
WKUP_GPIO0_23
0x4301C030
WKUP_PADCONFIG_12
R5
MCU_OSPI0_CSn1 MCU_HYPERBUS0
_RESETn
WKUP_GPIO0_24
0x4301C034
WKUP_PADCONFIG_13
T1
MCU_OSPI1_CLK
WKUP_GPIO0_25
0x4301C038
WKUP_PADCONFIG_14
R1
MCU_OSPI1_LBCL MCU_OSPI0_CSn2 MCU_HYPERBUS0
KO
_RESETOn
WKUP_GPIO0_26
0x4301C03C
WKUP_PADCONFIG_15
P2
MCU_OSPI1_DQS MCU_OSPI0_CSn3 MCU_HYPERBUS0
_INTn
WKUP_GPIO0_27
0x4301C040
WKUP_PADCONFIG_16
P3
MCU_OSPI1_D0
0x4301C044
WKUP_PADCONFIG_17
P4
MCU_OSPI1_D1
MCU_UART0_RXD MCU_SPI1_CS1
WKUP_GPIO0_29
0x4301C048
WKUP_PADCONFIG_18
P5
MCU_OSPI1_D2
MCU_UART0_TXD MCU_SPI1_CS2
WKUP_GPIO0_30
0x4301C04C
WKUP_PADCONFIG_19
P1
MCU_OSPI1_D3
MCU_UART0_CTS MCU_SPI0_CS1
n
WKUP_GPIO0_31
0x4301C050
WKUP_PADCONFIG_20
N2
MCU_OSPI1_CSn0
0x4301C054
WKUP_PADCONFIG_21
N3
MCU_OSPI1_CSn1 MCU_HYPERBUS0 MCU_TIMER_IO0
_WPn
0x4301C058
WKUP_PADCONFIG_22
N4
MCU_RGMII1_TX_ MCU_RMII1_CRS_
CTL
DV
WKUP_GPIO0_34
0x4301C05C
WKUP_PADCONFIG_23
N5
MCU_RGMII1_RX_ MCU_RMII1_RX_E
CTL
R
WKUP_GPIO0_35
Bootstrap
ADVANCE INFORMATION
ADDRESS
BALL
NUMBER
WKUP_GPIO0_28
WKUP_GPIO0_32
MCU_HYPERBUS0 MCU_UART0_RTS MCU_SPI0_CS2
_CSn1
n
WKUP_GPIO0_33
Terminal Configuration and Functions
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Table 4-75. Pin Multiplexing (continued)
ADDRESS
BALL
NUMBER
REGISTER NAME
MUXMODE[7:0] SETTINGS
0
1
2
3
4
5
6
7
Bootstrap
ADVANCE INFORMATION
0x4301C060
WKUP_PADCONFIG_24
M2
MCU_RGMII1_TD3
WKUP_GPIO0_36
0x4301C064
WKUP_PADCONFIG_25
M3
MCU_RGMII1_TD2
WKUP_GPIO0_37
0x4301C068
WKUP_PADCONFIG_26
M4
MCU_RGMII1_TD1 MCU_RMII1_TXD1
WKUP_GPIO0_38
0x4301C06C
WKUP_PADCONFIG_27
M5
MCU_RGMII1_TD0 MCU_RMII1_TXD0
WKUP_GPIO0_39
0x4301C070
WKUP_PADCONFIG_28
N1
MCU_RGMII1_TXC MCU_RMII1_TX_E
N
WKUP_GPIO0_40
0x4301C074
WKUP_PADCONFIG_29
M1
MCU_RGMII1_RXC MCU_RMII1_REF_
CLK
WKUP_GPIO0_41
0x4301C078
WKUP_PADCONFIG_30
L2
MCU_RGMII1_RD3
WKUP_GPIO0_42
0x4301C07C
WKUP_PADCONFIG_31
L5
MCU_RGMII1_RD2
WKUP_GPIO0_43
0x4301C080
WKUP_PADCONFIG_32
M6
MCU_RGMII1_RD1 MCU_RMII1_RXD1
WKUP_GPIO0_44
0x4301C084
WKUP_PADCONFIG_33
L6
MCU_RGMII1_RD0 MCU_RMII1_RXD0
WKUP_GPIO0_45
0x4301C088
WKUP_PADCONFIG_34
L4
MCU_MDIO0_MDI
O
WKUP_GPIO0_46
0x4301C08C
WKUP_PADCONFIG_35
L1
MCU_MDIO0_MDC
WKUP_GPIO0_47
0x4301C090
WKUP_PADCONFIG_36
Y1
MCU_SPI0_CLK
WKUP_GPIO0_48
MCU_BOOTMODE
06
0x4301C094
WKUP_PADCONFIG_37
Y3
MCU_SPI0_D0
WKUP_GPIO0_49
MCU_BOOTMODE
07
0x4301C098
WKUP_PADCONFIG_38
Y2
MCU_SPI0_D1
WKUP_GPIO0_50
MCU_BOOTMODE
05
0x4301C09C
WKUP_PADCONFIG_39
Y4
MCU_SPI0_CS0
WKUP_GPIO0_51
0x4301C0A0
WKUP_PADCONFIG_40
AB1
WKUP_UART0_RX
D
WKUP_GPIO0_52
0x4301C0A4
WKUP_PADCONFIG_41
AB5
WKUP_UART0_TX
D
WKUP_GPIO0_53
0x4301C0A8
WKUP_PADCONFIG_42
W1
MCU_MCAN0_TX
WKUP_GPIO0_54
0x4301C0AC
WKUP_PADCONFIG_43
W2
MCU_MCAN0_RX
0x4301C0B0
WKUP_PADCONFIG_44
AF4
WKUP_GPIO0_0
MCU_SPI1_CLK
WKUP_GPIO0_0
MCU_BOOTMODE
00
0x4301C0B4
WKUP_PADCONFIG_45
AF3
WKUP_GPIO0_1
MCU_SPI1_D0
WKUP_GPIO0_1
MCU_BOOTMODE
01
0x4301C0B8
WKUP_PADCONFIG_46
AE3
WKUP_GPIO0_2
MCU_SPI1_D1
WKUP_GPIO0_2
MCU_BOOTMODE
02
0x4301C0BC
WKUP_PADCONFIG_47
AD1
WKUP_GPIO0_3
MCU_SPI1_CS0
WKUP_GPIO0_3
MCU_BOOTMODE
03
0x4301C0C0
WKUP_PADCONFIG_48
AC3
WKUP_GPIO0_4
MCU_MCAN1_TX
MCU_SPI0_CS3
MCU_ADC_EXT_T
RIGGER0
WKUP_GPIO0_4
MCU_BOOTMODE
04
0x4301C0C4
WKUP_PADCONFIG_49
AD3
WKUP_GPIO0_5
MCU_MCAN1_RX
MCU_SPI1_CS3
MCU_ADC_EXT_T
RIGGER1
WKUP_GPIO0_5
0x4301C0C8
WKUP_PADCONFIG_50
AC2
WKUP_GPIO0_6
WKUP_UART0_CT MCU_CPTS0_HW1
Sn
TSPUSH
WKUP_GPIO0_6
0x4301C0CC
WKUP_PADCONFIG_51
AC1
WKUP_GPIO0_7
WKUP_UART0_RT MCU_CPTS0_HW2
Sn
TSPUSH
WKUP_GPIO0_7
116
WKUP_GPIO0_55
Terminal Configuration and Functions
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SPRSP31E – APRIL 2018 – REVISED JUNE 2019
Table 4-75. Pin Multiplexing (continued)
ADDRESS
REGISTER NAME
MUXMODE[7:0] SETTINGS
BALL
NUMBER
0
1
2
3
4
5
6
7
Bootstrap
0x4301C0D0
WKUP_PADCONFIG_52
AC5
WKUP_GPIO0_8
MCU_CPTS0_TS_
SYNC
WKUP_GPIO0_8
MCU_BOOTMODE
08
0x4301C0D4
WKUP_PADCONFIG_53
AB4
WKUP_GPIO0_9
MCU_CPTS0_TS_
COMP
WKUP_GPIO0_9
MCU_BOOTMODE
09
0x4301C0D8
WKUP_PADCONFIG_54
AB3
WKUP_GPIO0_10
MCU_EXT_REFCL
K0
MCU_CPTS0_RFT MCU_SYSCLKOUT
_CLK
0
0x4301C0DC
WKUP_PADCONFIG_55
AB2
WKUP_GPIO0_11
MCU_OBSCLK0
MCU_TIMER_IO1
0x4301C0E0
WKUP_PADCONFIG_56
AC7
WKUP_I2C0_SCL
0x4301C0E4
WKUP_PADCONFIG_57
AD6
WKUP_I2C0_SDA
0x4301C0E8
WKUP_PADCONFIG_58
AD8
MCU_I2C0_SCL
0x4301C0EC
WKUP_PADCONFIG_59
AD7
MCU_I2C0_SDA
0x4301C0F0
WKUP_PADCONFIG_60
AA5
PMIC_POWER_EN
1
0x4301C0F4
WKUP_PADCONFIG_61
W3
MCU_SAFETY_ER
RORn
0x4301C0F8
WKUP_PADCONFIG_62
W4
MCU_RESETz
0x4301C0FC
WKUP_PADCONFIG_63
V3
MCU_RESETSTAT
z
0x4301C100
WKUP_PADCONFIG_64
V2
MCU_PORz_OUT
0x4301C104
WKUP_PADCONFIG_65
AA4
TCK
0x4301C108
WKUP_PADCONFIG_66
AA3
TRSTn
0x4301C10C
WKUP_PADCONFIG_67
AA2
EMU0
0x4301C110
WKUP_PADCONFIG_68
AA1
EMU1
0x4301C114
WKUP_PADCONFIG_69
Y5
PMIC_POWER_EN
0
WKUP_GPIO0_10
WKUP_GPIO0_11
ADVANCE INFORMATION
MCU_CLKOUT0
Terminal Configuration and Functions
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DRA80M
SPRSP31E – APRIL 2018 – REVISED JUNE 2019
4.5
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Connections for Unused Pins
This section describes the Unused/Reserved balls connection requirements.
NOTE
All power balls must be supplied with the voltages specified in Section 5.4, Recommended
Operating Conditions, unless otherwise specified in Section 4.3, Signal Descriptions.
Table 4-76. Unused Balls Specific Connection Requirements
BALL NUMBER
BALL NAME
ADVANCE INFORMATION
C22
OSC1_XI
AE4
WKUP_LFOSC0_XI
AA3
TRSTn
K2
MCU_ADC0_REFN
K3
MCU_ADC0_REFP
V5
MCU_BYP_POR
H2
MCU_ADC1_REFP
H3
MCU_ADC1_REFN
K5
MCU_ADC0_AIN0
J3
MCU_ADC0_AIN1
J1
MCU_ADC0_AIN2
J5
MCU_ADC0_AIN3
K4
MCU_ADC0_AIN4
J4
MCU_ADC0_AIN5
J2
MCU_ADC0_AIN6
J6
MCU_ADC0_AIN7
F4
MCU_ADC1_AIN0
G6
MCU_ADC1_AIN1
G4
MCU_ADC1_AIN2
H5
MCU_ADC1_AIN3
F5
MCU_ADC1_AIN4
G5
MCU_ADC1_AIN5
G3
MCU_ADC1_AIN6
H4
MCU_ADC1_AIN7
F17
RESETz
W4
MCU_RESETz
W5
MCU_PORz
E19
PORz
AA4
TCK
A21
TMS
AC7
WKUP_I2C0_SCL
AD6
WKUP_I2C0_SDA
AD7
MCU_I2C0_SDA
AD8
MCU_I2C0_SCL
F18
NMIn
C20
TDI
A20
TDO
AA1
EMU1
AA2
EMU0
118
CONNECTION REQUIREMENTS
Each of these balls must be connected to VSS through a separate
external pull resistor to ensure these balls are held to a valid logic
low level if unused.
Each of these balls must be connected to the corresponding power
supply through a separate external pull resistor to ensure these balls
are held to a valid logic high level if unused.(1)
Terminal Configuration and Functions
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SPRSP31E – APRIL 2018 – REVISED JUNE 2019
Table 4-76. Unused Balls Specific Connection Requirements (continued)
BALL NUMBER
BALL NAME
F21
VPP_CORE
T6
VPP_MCU
F23
MMC1_CALPAD
D24
MMC0_CALPAD
CONNECTION REQUIREMENTS
This ball must be left unconnected if unused.
(1) To determine which power supply is associated with any IO refer to Table 4-1, Pin Attributes.
Table 4-77. Reserved Balls Specific Connection Requirements
BALLS
CONNECTION REQUIREMENTS
These balls must be left unconnected.
V4 (RSV1)
These balls must be connected to VSS through a separate external
pull resistor to ensure these balls are held to a valid logic low level.
ADVANCE INFORMATION
AA6 (RSV2), B1 (RSV3), AC23 (RSV4), C12 (RSV5), F9 (RSV6),
F10 (RSV7), AD10 (RSV8), AC13 (RSV9), B28 (RSV10), A27
(RSV11), D23 (RSV12), E23 (RSV13)
NOTE
All other unused signal balls with a Pad Configuration Register can be left unconnected with
their multiplexing mode set to GPIO input and internal pulldown resistor enabled.
Unused balls are defined as those which only connect to a PCB solder pad. This is the only
use case where internal pull resistors are allowed as the only source/sink to hold a valid logic
level.
Any balls connected to a via, test point, or PCB trace are considered used and must not
depend on the internal pull resistor to hold a valid logic level.
Internal pull resistors are weak and may not source enough current to maintain a valid logic
level for some operating conditions. This may be the case when connected to components
with leakage to the opposite logic level, or when external noise sources couple to signal
traces attached to balls which are only pulled to a valid logic level by the internal resistor.
Therefore, external pull resistors may be required to hold a valid logic level on balls with
external connections.
If balls are allowed to float between valid logic levels, the input buffer may enter a highcurrent state which could damage the IO cell.
Terminal Configuration and Functions
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5 Specifications
5.1
Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)
(1)(2)
PARAMETERS
MIN
MAX UNIT
ADVANCE INFORMATION
VDD_CORE
Supply voltage range for CORE domain
-0.3
1.5
V
VDD_MCU
Supply voltage range for R5F MCU domain
-0.3
1.5
V
VDD_MPU0
Supply voltage range for A53 MPU0 domain
-0.3
1.5
V
VDD_MPU1
Supply voltage range for A53 MPU1 domain
-0.3
1.5
V
VDD_WKUP0
Supply voltage range for WKUP domain
-0.3
1.5
V
VDD_WKUP1
Supply voltage range for WKUP domain
-0.3
1.5
V
VDD_DLL_MMC0
Supply voltage range for MMC0 DLL
-0.3
1.5
V
VDD_DLL_MMC1
Supply voltage range for MMC1 DLL
-0.3
1.5
V
VDDA_1P8_CSI0
Supply voltage range for CSI PHY, Analog, 1.8 V
-0.3
2
V
VDDA_1P8_OLDI0
Supply voltage range for OLDI, Analog, 1.8 V
-0.3
2
V
VDDA_1P8_SDIO
Supply voltage range for SDIO LDO, Analog, 1.8 V
-0.3
2
V
VDDA_1P8_SERDES0
Supply voltage range for USB, PCIE, Analog, 1.8 V
-0.3
2
V
VDDA_3P3_IOLDO_WKUP
Supply voltage range for WKUP IO Bias LDO, Analog,
3.3 V
-0.3
3.8
V
VDDA_3P3_IOLDO0
Supply voltage range for IO Bias LDO, Analog 3.3 V
-0.3
3.8
V
VDDA_3P3_IOLDO1
Supply voltage range for IO Bias LDO, Analog 3.3 V
-0.3
3.8
V
VDDA_3P3_SDIO
Supply voltage range for SDIO LDO, Analog, 3.3 V
-0.3
3.8
V
VDDA_3P3_USB
Supply voltage range for USBPHY, Analog, 3.3 V
-0.3
3.8
V
VDDA_ADC_MCU
Supply voltage range for ADC0, ADC1, Analog
-0.3
2
V
VDDA_PLL0_DDR
Supply voltage range for DDR DPLL, Analog
-0.3
2
V
VDDA_PLL1_DDR
Supply voltage range for DDR De-skew DPLL, Analog
-0.3
2
V
VDDA_LDO_WKUP
Supply voltage range for WKUP LDO, Analog
-0.3
2
V
VDDA_MCU
Supply voltage range for MCU SRAM LDO, MCU
DPLL, CPSW DPLL, Analog
-0.3
2
V
VDDA_PLL_CORE
Supply voltage range for CORE DPLL, PER1 DPLL,
Analog
-0.3
2
V
VDDA_PLL_DSS
Supply voltage range for DSS DPLL, Analog
-0.3
2
V
VDDA_PLL_MPU0
Supply voltage range for MPU0 DPLL, Analog
-0.3
2
V
VDDA_PLL_MPU1
Supply voltage range for MPU1 DPLL, Analog
-0.3
2
V
VDDA_PLL_PER0
Supply voltage range for PER0 DPLL, Analog
-0.3
2
V
VDDA_POR_WKUP
Supply voltage range for WKUP POR, Analog
-0.3
2
V
VDDA_SRAM_CORE0
Supply voltage range for CORE SRAM LDOs, Analog
-0.3
2
V
VDDA_SRAM_CORE1
Supply voltage range for CORE SRAM LDOs, Analog
-0.3
2
V
VDDA_SRAM_MPU0
Supply voltage range for MPU SRAM LDOs, Analog
-0.3
2
V
VDDA_SRAM_MPU1
Supply voltage range for MPU SRAM LDOs, Analog
-0.3
2
V
VDDA_WKUP
Supply voltage range for WKUP OSC, SRAM LDO,
Analog
-0.3
2
V
VDDS_DDR
Supply voltage range for DDR IO domain
-0.3
2
V
VDDS_OSC1
Supply voltage range for CORE HFOSC, Analog
-0.3
2
V
VDDS0
Supply voltage range for VDDSHV0 IO bias
-0.3
2
V
VDDS0_WKUP
Supply voltage range for VDDSHV0_WKUP IO bias
-0.3
2
V
VDDS1
Supply voltage range for VDDSHV1 IO bias
-0.3
2
V
VDDS1_WKUP
Supply voltage range for VDDSHV1_WKUP IO bias
-0.3
2
V
VDDS2
Supply voltage range for VDDSHV2 IO bias
-0.3
2
V
VDDS2_WKUP
Supply voltage range for VDDSHV2_WKUP IO bias
-0.3
2
V
120
Specifications
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Absolute Maximum Ratings (continued)
(1)(2)
PARAMETERS
MIN
MAX UNIT
VDDS3
Supply voltage range for VDDSHV3 IO bias
-0.3
2
V
VDDS4
Supply voltage range for VDDSHV4 IO bias
-0.3
2
V
VDDS5
Supply voltage range for VDDSHV5 IO bias
-0.3
2
V
VDDS6
Supply voltage range for VDDSHV6 IO bias
-0.3
2
V
VDDS7
Supply voltage range for VDDSHV7 IO bias
-0.3
2
V
VDDS8
Supply voltage range for VDDSHV8 IO bias
-0.3
2
V
VDDSHV0
Supply voltage range for dual-voltage IO
domain
1.8 V
-0.3
2
V
3.3 V
-0.3
3.8
V
VDDSHV0_WKUP
Supply voltage range for dual-voltage IO
domain
1.8 V
-0.3
2
V
3.3 V
-0.3
3.8
V
VDDSHV1
Supply voltage range for dual-voltage IO
domain
1.8 V
-0.3
2
V
3.3 V
-0.3
3.8
V
VDDSHV1_WKUP
Supply voltage range for dual-voltage IO
domain
1.8 V
-0.3
2
V
3.3 V
-0.3
3.8
V
VDDSHV2
Supply voltage range for dual-voltage IO
domain
1.8 V
-0.3
2
V
3.3 V
-0.3
3.8
V
VDDSHV2_WKUP
Supply voltage range for dual-voltage IO
domain
1.8 V
-0.3
2
V
3.3 V
-0.3
3.8
V
VDDSHV3
Supply voltage range for dual-voltage IO
domain
1.8 V
-0.3
2
V
3.3 V
-0.3
3.8
V
VDDSHV4
Supply voltage range for dual-voltage IO
domain
1.8 V
-0.3
2
V
3.3 V
-0.3
3.8
V
VDDSHV5
Supply voltage range for dual-voltage IO
domain
1.8 V
-0.3
2
V
3.3 V
-0.3
3.8
V
VDDSHV6
Supply voltage range for dual-voltage IO
domain
1.8 V
-0.3
2
V
3.3 V
-0.3
3.8
V
VDDSHV7
Supply voltage range for dual-voltage IO
domain
1.8 V
-0.3
2
V
3.3 V
-0.3
3.8
V
VDDSHV8
Supply voltage range for dual-voltage IO
domain
1.8 V
-0.3
2
V
3.3 V
-0.3
3.8
V
VDDA_VSYS_MON
Supply monitor for system
-0.3
2
V
VPP_CORE
Supply voltage range for CORE EFUSE domain
TBD
TBD
V
VPP_MCU
Supply voltage range for MCU EFUSE domain
TBD
TBD
V
USB0_VBUS
Voltage range for USB VBUS comparator input
TBD
TBD
V
USB1_VBUS
Voltage range for USB VBUS comparator input
TBD
TBD
V
I2C0_SCL, I2C0_SDA, I2C1_SCL, I2C1_SDA, NMIn,
VDDA_3P3_MON_WKUP, VDDA_3P3_MON0
–0.3
3.8
V
Steady State Max. Voltage at all
fail-safe IO pins
Steady State Max. Voltage at all
other IO pins(3)
Transient Overshoot and
Undershoot specification at IO
pin
Latch-up Performance(5)
TSTG
(7)
VDDA_1P8_MON_WKUP, VDDA_1P8_MON0
-0.3
2
V
DDR_FS_RESETn
TBD
TBD
V
-0.3 VDDA_POR_WKUP + 0.3
V
-0.3
IO supply voltage + 0.3
V
0.2 × VDD(6)
V
VDDA_VSYS_MON
(4)
All other IO pins
20% of IO supply voltage for up to 20% of signal period
(see Figure 5-1, IO Transient Voltage Ranges)
Class II (105°C)
TBD
TBD
mA
Class II (125°C)
TBD
TBD
mA
-55
+150
°C
Storage temperature
Specifications
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ADVANCE INFORMATION
over operating free-air temperature range (unless otherwise noted)
DRA80M
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Absolute Maximum Ratings (continued)
over operating free-air temperature range (unless otherwise noted)
(1)(2)
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under Section 5.4, Recommended
Operating Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) All voltage values are with respect to their associated VSS or VSSA_x, unless otherwise noted.
(3) This parameter applies to all IO pins which are not fail-safe and the requirement applies to all values of IO supply voltage. For example,
if the voltage applied to a specific IO supply is 0 volts the valid input voltage range for any IO powered by that supply will be –0.3 to +0.3
volts. Special attention should be applied anytime peripheral devices are not powered from the same power sources used to power the
respective IO supply. It is important the attached peripheral never sources a voltage outside the valid input voltage range, including
power supply ramp-up and ramp-down sequences.
(4) The VDDA_VSYS_MON pin provides a way to monitor the system power supply and is not fail-safe, unless implemented with the
appropriate resistor voltage divider source. For more information, see Section 7.5, System Power Supply Monitor Design Guidelines.
(5) For current pulse injection:
Pins stressed per JEDEC JESD78D (Class II) and passed with specified I/O pin injection current and clamp voltage of 1.5 times
maximum recommended I/O voltage and negative 0.5 times maximum recommended I/O voltage.
For overvoltage performance:
Supplies stressed per JEDEC JESD78D (Class II) and passed specified voltage injection.
(6) VDD is the voltage on the corresponding power-supply pin(s) for the IO.
ADVANCE INFORMATION
(7) For tape and reel the storage temperature range is [–10°C; +50°C] with a maximum relative humidity of 70%. TI recommends returning
to ambient room temperature before usage.
Fail-safe IO terminals are designed such they do not have dependencies on the respective IO power
supply voltage. This allows external voltage sources to be connected to these IO terminals when the
respective IO power supplies are turned off. The I2C0_SCL, I2C0_SDA, I2C1_SCL, I2C1_SDA,
DDR_FS_RESETn, NMIn, VDDA_1P8_MON_WKUP, VDDA_1P8_MON0, VDDA_3P3_MON_WKUP, and
VDDA_3P3_MON0 are the only fail-safe IO terminals. All other IO terminals are not fail-safe and the
voltage applied to them should be limited to the value defined by the Steady State Max. Voltage at all IO
pins parameter in Section 5.1, Absolute Maximum Ratings.
Overshoot = 20% of nominal
IO supply voltage
Tovershoot
Tperiod
Tundershoot
Undershoot = 20% of nominal
IO supply voltage
(1)
Tovershoot + Tundershoot < 20% of Tperiod
Figure 5-1. IO Transient Voltage Ranges
5.2
ESD Ratings
VALUE
V(ESD)
Electrostatic discharge
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1)
TBD
Charged-device model (CDM), per JEDEC specification AEC Q100011(2)
TBD
UNIT
V
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
122
Specifications
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5.3
SPRSP31E – APRIL 2018 – REVISED JUNE 2019
Power-On-Hour (POH) Limits(1)(2)(3)
OPERATING
CONDITION
OPP
OPP_NOM
COMMERCIAL TEMPERATURE
RANGE
EXTENDED TEMPERATURE
RANGE
AUTOMOTIVE TEMPERATURE
RANGE
JUNCTION
TEMP (Tj)
LIFETIME (POH)
JUNCTION
TEMP (Tj)
LIFETIME (POH)
0°C to 90°C
100k
-40°C to 105°C
100k
OPP_OD
100k
100k
OPP_TURBO
TBD
TBD
JUNCTION
TEMP (Tj)
LIFETIME (POH)
Automotive
Profile(4)
TBD
TBD
TBD
(1) This information is provided solely for your convenience and does not extend or modify the warranty provided under TI's standard terms
and conditions for TI semiconductor products.
(2) Unless specified in the table above, all voltage domains and operating conditions are supported in the device at the noted temperatures.
(3) POH is a function of voltage, temperature and time. Usage at higher voltages and temperatures will result in a reduction in POH.
(4) Automotive profile is defined as 20000 power on hours with a junction temperature as follows: 5%@-40°C, 65%@70°C, 20%@110°C,
and 10%@125°C.
5.4
Recommended Operating Conditions
SUPPLY NAME
(3)
DESCRIPTION
MIN(1)
NOM
MAX(1)
UNIT
VDD_CORE
CORE voltage domain supply
0.95
1
1.05
V
VDD_MCU(3)
MCU voltage domain supply
0.95
1
1.05
V
(3)
VDD_MPU0
(3)
VDD_MPU1
MPU0 voltage domain supply
MPU1 voltage domain supply
OPP_NOM
0.95
1
1.05
V
OPP_OD
1.05
1.1
1.15
V
OPP_TURBO
1.16
1.22
1.28
V
OPP_NOM
0.95
1
1.05
V
OPP_OD
1.05
1.1
1.15
V
OPP_TURBO
1.16
1.22
1.28
V
VDD_WKUP0
WKUP voltage domain supply
0.95
1
1.05
V
VDD_WKUP1
WKUP voltage domain supply
0.95
1
1.05
V
VDD_DLL_MMC0
MMC0 PHY DLL voltage supply
0.95
1
1.05
V
TBD
mVPPmax
Maximum peak-to-peak supply noise
VDD_DLL_MMC1
MMC1 PHY DLL voltage supply
0.95
1
Maximum peak-to-peak supply noise
1.05
V
TBD
mVPPmax
VDDA_1P8_CSI0
CSI PHY analog power supply
1.71
1.8
1.89
V
VDDA_1P8_SDIO
SDIO LDO analog power supply
1.71
1.8
1.89
V
VDDA_1P8_OLDI0
OLDI analog power supply
1.71
1.8
1.89
V
VDDA_1P8_SERDES0
SERDES0/1 (USB, PCIE, SGMII) analog power supply
1.71
1.8
1.89
V
VDDA_3P3_IOLDO_WKUP WKUP IO Bias LDO analog power supply
3.14
3.3
3.46
V
VDDA_3P3_IOLDO0
IO Bias LDO analog power supply
3.14
3.3
3.46
V
VDDA_3P3_IOLDO1
IO Bias LDO analog power supply
3.14
3.3
3.46
V
VDDA_3P3_SDIO
SDIO LDO analog power supply
3.14
3.3
3.46
V
VDDA_3P3_USB
USB analog power supply
3.14
3.3
3.46
V
VDDA_1P8_MON_WKUP
1.8V supply monitor in WKUP domain
1.71
1.8
1.89
V
VDDA_1P8_MON0
1.8V supply monitor in MAIN domain
1.71
1.8
1.89
V
VDDA_3P3_MON_WKUP
3.3V supply monitor in WKUP domain
3.14
3.3
3.46
V
VDDA_3P3_MON0
3.3V supply monitor in MAIN domain
3.14
3.3
3.46
V
VDDA_VSYS_MON
Supply monitor for system
(6)
1
V
VDDA_ADC_MCU
ADC0, ADC1 analog power supply
1.71
1.8
1.89
V
VDDA_LDO_WKUP
WKUP LDO analog power supply
1.71
1.8
1.89
V
VDDA_MCU
MCU SRAM LDO, MCU DPLL, CPSW DPLL analog power
supply
1.71
1.8
1.89
V
0
see
Specifications
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over operating free-air temperature range (unless otherwise noted)
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Recommended Operating Conditions (continued)
over operating free-air temperature range (unless otherwise noted)
SUPPLY NAME
VDDA_PLL_CORE
DESCRIPTION
CORE DPLL, PER1 DPLL analog power supply
MIN(1)
NOM
MAX(1)
1.71
1.8
1.89
Maximum peak-to-peak supply noise
VDDA_PLL0_DDR
50
DDR DPLL analog power supply
1.71
1.8
Maximum peak-to-peak supply noise
VDDA_PLL1_DDR
50
DDR De-skew DPLL analog power supply
1.71
1.8
1.89
1.71
1.8
1.89
Maximum peak-to-peak supply noise
VDDA_PLL_DSS
50
DSS DPLL analog power supply
Maximum peak-to-peak supply noise
VDDA_PLL_MPU0
50
MPU0 DPLL analog power supply
1.71
1.8
1.89
1.71
1.8
1.89
Maximum peak-to-peak supply noise
VDDA_PLL_MPU1
50
MPU1 DPLL analog power supply
Maximum peak-to-peak supply noise
VDDA_PLL_PER0
1.89
50
PER0 DPLL analog power supply
1.71
1.8
ADVANCE INFORMATION
Maximum peak-to-peak supply noise
1.89
50
UNIT
V
mVPPmax
V
mVPPmax
V
mVPPmax
V
mVPPmax
V
mVPPmax
V
mVPPmax
V
mVPPmax
VDDA_POR_WKUP
WKUP POR/POK analog power supply
1.71
1.8
1.89
V
VDDA_SRAM_CORE0
CORE SRAM LDOs analog power supply
1.71
1.8
1.89
V
VDDA_SRAM_CORE1
CORE SRAM LDOs analog power supply
1.71
1.8
1.89
V
VDDA_SRAM_MPU0
MPU SRAM LDOs analog power supply
1.71
1.8
1.89
V
VDDA_SRAM_MPU1
MPU SRAM LDOs analog power supply
1.71
1.8
1.89
V
VDDA_WKUP
WKUP High/Low Frequency Oscillator (WKUP_LFOSC0 /
WKUP_OSC0), SRAM LDO analog power supply
1.71
1.8
1.89
V
VDDS_DDR(4)
DDR IO domain power supply (DDR3L)
1.28
1.35
1.42
V
DDR IO domain power supply (DDR4)
1.14
1.2
1.26
V
DDR IO domain power supply (LPDDR4)
1.05
1.1
1.15
V
VDDS_OSC1
MAIN High Frequency Oscillator (OSC1) analog power supply
1.71
1.8
1.89
V
VDDS0
IO bias supply for VDDSHV0
1.71
1.8
1.89
V
VDDS0_WKUP
IO bias supply for VDDSHV0_WKUP
1.71
1.8
1.89
V
VDDS1
IO bias supply for VDDSHV1
1.71
1.8
1.89
V
VDDS1_WKUP
IO bias supply for VDDSHV1_WKUP
1.71
1.8
1.89
V
VDDS2
IO bias supply for VDDSHV2
1.71
1.8
1.89
V
VDDS2_WKUP
IO bias supply for VDDSHV2_WKUP
1.71
1.8
1.89
V
VDDS3
IO bias supply for VDDSHV3
1.71
1.8
1.89
V
VDDS4
IO bias supply for VDDSHV4
1.71
1.8
1.89
V
VDDS5
IO bias supply for VDDSHV5
1.71
1.8
1.89
V
VDDS6
IO bias supply for VDDSHV6
1.71
1.8
1.89
V
VDDS7
IO bias supply for VDDSHV7
1.71
1.8
1.89
V
VDDS8
IO bias supply for VDDSHV8
1.71
1.8
1.89
V
VDDSHV0
Dual-voltage IO domain power supply 1.8-V operation
1.71
1.8
1.89
V
3.3-V operation
3.14
3.3
3.46
V
Dual-voltage IO domain power supply 1.8-V operation
1.71
1.8
1.89
V
3.3-V operation
3.14
3.3
3.46
V
VDDSHV1
Dual-voltage IO domain power supply 1.8-V operation
1.71
1.8
1.89
V
3.3-V operation
3.14
3.3
3.46
V
VDDSHV1_WKUP
Dual-voltage IO domain power supply 1.8-V operation
1.71
1.8
1.89
V
3.3-V operation
3.14
3.3
3.46
V
VDDSHV0_WKUP
124
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Recommended Operating Conditions (continued)
over operating free-air temperature range (unless otherwise noted)
MIN(1)
NOM
MAX(1)
Dual-voltage IO domain power supply 1.8-V operation
1.71
1.8
1.89
V
3.3-V operation
3.14
3.3
3.46
V
Dual-voltage IO domain power supply 1.8-V operation
1.71
1.8
1.89
V
3.3-V operation
3.14
3.3
3.46
V
VDDSHV3
Dual-voltage IO domain power supply 1.8-V operation
1.71
1.8
1.89
V
3.3-V operation
3.14
3.3
3.46
V
VDDSHV4
Dual-voltage IO domain power supply 1.8-V operation
1.71
1.8
1.89
V
3.3-V operation
3.14
3.3
3.46
V
VDDSHV5
Dual-voltage IO domain power supply 1.8-V operation
1.71
1.8
1.89
V
3.3-V operation
3.14
3.3
3.46
V
VDDSHV6
Dual-voltage IO domain power supply 1.8-V operation
1.71
1.8
1.89
V
3.3-V operation
3.14
3.3
3.46
V
Dual-voltage IO domain power supply 1.8-V operation
1.71
1.8
1.89
V
3.3-V operation
3.14
3.3
3.46
V
VDDSHV8
Dual-voltage IO domain power supply 1.8-V operation
1.71
1.8
1.89
V
3.3-V operation
3.14
3.3
3.46
V
USB0_VBUS
Voltage range for USB VBUS comparator input
0
TBD
TBD
V
USB1_VBUS
Voltage range for USB VBUS comparator input
0
TBD
TBD
V
USB0_ID
Voltage range for the USB ID input
VDDSHV2
VDDSHV2_WKUP
VDDSHV7
DESCRIPTION
USB1_ID
Voltage range for the USB ID input
VSS
Ground
TJ
Operating junction temperature range Automotive
UNIT
see
(5)
V
see
(5)
V
0
Extended
Commercial
V
-40
125
°C
-40
105
°C
0
90
°C
(1) The voltage at the device ball must never be below the MIN voltage or above the MAX voltage for any amount of time. This requirement
includes dynamic voltage events such as AC ripple, voltage transients, voltage dips, and so forth.
(2) Refer to Section 5.3, Power-On-Hour (POH) Limits for limitations.
(3) This value is without AVS. The AVS Voltages are device-dependent, voltage domain-dependent, and OPP-dependent. They must be
read from the VTM_DEVINFO_VDn. For information about VTM_DEVINFO_VDn Registers address, please refer to section Voltage and
Thermal Manager (VTM) in the device TRM. The power supply should be adjustable over the following ranges for each required OPP:
– OPP_NOM: TBD
– OPP_OD: TBD
– OPP_TURBO: TBD
The AVS Voltages will be within the above specified ranges.
(4) VDDS_DDR is required to still be powered with either DDR3L, DDR4, or LPDDR4 voltage ranges, even If DDR interface is unused.
(5) This terminal is connected to analog circuits in the respective USB PHY. The circuit sources a known current while measuring the
voltage to determine if the terminal is connected to VSS with a resistance less than 10 Ω or greater than 100 kΩ. The terminal should be
connected to ground for USB host operation or open-circuit for USB peripheral operation, and should never be connected to any
external voltage source.
(6) The VDDA_VSYS_MON pin provides a way to monitor the system power supply and is not fail-safe, unless implemented with the
appropriate resistor voltage divider source. For more information, see Section 7.5, System Power Supply Monitor Design Guidelines.
Specifications
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5.5
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Operating Performance Points
This section describes the operating conditions of the device. This section also contains the description of
each operating performance point for processor clocks and device core clocks.
NOTE
The OPP voltage and frequency values may change following the silicon characterization
result.
Table 5-1 describes the maximum supported frequency per speed grade for the device.
Table 5-1. Speed Grade Maximum Frequency(1)
DEVICE SPEED
DRA80xM X
MAXIMUM FREQUENCY (MHz)
MPU
MCU
DMSC
GPU
CBASS0
ICSSG
DDR3L/DDR4
LPDDR4
1100
400
200
N/A
250
250
800 (DDR-1600)
667 (DDR-1333)
(1) N/A stands for Not Applicable.
ADVANCE INFORMATION
5.5.1
Core Clock Specifications
Table 5-2 describes the standard processor clocks speed characteristics vs OPP of the device.
Table 5-2. Supported OPP vs Max Frequency (1)(2)
OPP_NOM
OPP_OD
OPP_TURBO
MAXIMUM FREQUENCY (MHz)
MAXIMUM FREQUENCY (MHz)
MAXIMUM FREQUENCY (MHz)
DDR3L/DDR4
800 (DDR-1600)
N/A
N/A
LPDDR4
667 (DDR-1333)
N/A
N/A
CBASS0
250
N/A
N/A
ICSSG
250
N/A
N/A
800
1000
1100
800
1000
1100
400
N/A
N/A
200
N/A
N/A
DESCRIPTION
VD_CORE
VD_MPU0
MPU0
VD_MPU1
MPU1
VD_MCU
MCU
VD_WKUP
DMSC
(1) N/A stands for Not Applicable.
(2) Maximum supported frequency is limited according to the Table 5-1, Speed Grade Maximum Frequency.
126
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5.6
SPRSP31E – APRIL 2018 – REVISED JUNE 2019
Electrical Characteristics
NOTE
The interfaces or signals described in Table 5-3 through Table 5-9 correspond to the
interfaces or signals available in multiplexing mode 0 (Primary Function).
All interfaces or signals multiplexed on the balls described in these tables have the same DC
electrical characteristics, unless multiplexing involves a PHY and GPIO combination, in
which case different DC electrical characteristics are specified for the different multiplexing
modes (Functions).
Table 5-3. I2C OPEN DRAIN DC Electrical Characteristics
over recommended operating conditions (unless otherwise noted)
PARAMETER
MIN
TYP
MAX
UNIT
BALL NAMES in Mode 0: WKUP_I2C0_SCL / WKUP_I2C0_SDA / MCU_I2C0_SCL / MCU_I2C0_SDA
BALL NUMBERS: AC7 / AD6 / AD7 / AD8
VIH
High-level input threshold
0.7 ×
VDDSHV0_WKUP
VIL
Low-level input threshold
VHYS
Hysteresis
IIN
Input leakage current. This value represents the
maximum current flowing in or out of the pin while the
output driver is disabled and the input is swept from VSS
to VDD.
12
µA
IOZ
Total leakage current through the driver/receiver
combination, which may include an internal pull-up or
pull-down. This value represents the maximum current
flowing in or out of the pin while the output driver is
disabled, the pull-up or pull-down is inhibited, and the
input is swept from VSS to VDD.
12
µA
VOL
Low-level output voltage at 3-mA sink current
0.2 ×
VDDSHV0_WKUP
V
ADVANCE INFORMATION
I2C STANDARD MODE / FAST MODE - VDDSHV0_WKUP = 1.8 V
V
0.3 ×
VDDSHV0_WKUP
V
0.1 ×
VDDSHV0_WKUP
V
I2C STANDARD MODE / FAST MODE - VDDSHV0_WKUP = 3.3 V
VIH
High-level input voltage
0.7 ×
VDDSHV0_WKUP
V
VIL
Low-level input voltage
VHYS
Hysteresis
IIN
Input leakage current. This value represents the
maximum current flowing in or out of the pin while the
output driver is disabled and the input is swept from VSS
to VDD.
80
µA
IOZ
Total leakage current through the driver/receiver
combination, which may include an internal pull-up or
pull-down. This value represents the maximum current
flowing in or out of the pin while the output driver is
disabled, the pull-up or pull-down is inhibited, and the
input is swept from VSS to VDD.
80
µA
VOL
Low-level output voltage at 3-mA sink current
0.4
V
0.3 ×
VDDSHV0_WKUP
V
0.05 ×
VDDSHV0_WKUP
V
Specifications
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Table 5-4. Analog OSC Buffers DC Electrical Characteristics
over recommended operating conditions (unless otherwise noted)
PARAMETER
MIN
TYP
MAX
UNIT
BALL NAMES: OSC1_XI / WKUP_OSC0_XI
BALL NUMBERS: C22 / AD5
HIGH FREQUENCY OSCILLATOR
VIH
High-level input voltage
VIL
Low-level input voltage
0.65 * VDDS(1)
V
0.35 * VDDS(1)
V
BALL NAMES: WKUP_LFOSC0_XI
BALL NUMBERS: AE4
LOW FREQUENCY OSCILLATOR
VIH
High-level input voltage
VIL
Low-level input voltage
0.65 *
VDDA_WKUP
V
0.35 *
VDDA_WKUP
V
(1) VDDS stands for corresponding power supply. For WKUP_OSC0_XI, the corresponding power supply is VDDA_WKUP. For OSC1_XI,
the corresponding power supply is VDDS_OSC1.
ADVANCE INFORMATION
Table 5-5. UHS-I MMC (8-bit PHY) Buffers DC Electrical Characteristics
over operating free-air temperature range (unless otherwise noted)
PARAMETER
MIN
NOM
MAX
UNIT
BALL NAMES in Mode 0: MMC0_CLK / MMC0_CMD / MMC0_DS / MMC0_DAT[7:0] / MMC1_CLK / MMC1_CMD / MMC1_DAT[3:0] /
MMC0_CALPAD / MMC1_CALPAD
BALL NUMBERS: A24 / A25 / A26 / B25 / B26 / B27 / C25 / C26 / C27 / C28 / D24 / D25 / D26 / D27 / D28 / E24 / E25 / E27 / F23
VIH
Input High-Level Voltage
0.65 ×
VDDS(1)
VIL
Input Low-Level Voltage
VOH
Output High-Level Threshold
VOL
Output Low-Level Threshold
IIN
Input Leakage Current
V
0.35 ×
VDDS(1)
0.75 ×
VDDS(1)
V
V
0.125 ×
VDDS(1)
10
V
µA
(1) VDDS stands for corresponding power supply (that is, VDDSHV6 or VDDSHV7). For more information on the power supply name and
the corresponding ball, see Table 4-1, POWER [9] column.
128
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Table 5-6. Analog ADC DC Electrical Characteristics
over recommended operating conditions (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
BALL NAMES in Mode 0: MCU_ADC0_AIN[7:0] / MCU_ADC0_REFP/N / MCU_ADC1_AIN[7:0] / MCU_ADC1_REFP/N
BALL NUMBERS: F4 / F5 / G3 / G4 / G5 / G6 / H2 / H3 / H4 / H5 / J1 / J2 / J3 / J4 / J5 / J6 / K2 / K3 / K4 / K5
VMCU_ADC0/1_REFP
MCU_ADC0/1_REFP
(0.5 x
VDDA_ADC_MCU) +
0.25
VDDA_ADC_MCU
V
VMCU_ADC0/1_REFN
MCU_ADC0/1_REFN
0
(0.5 x
VDDA_ADC_MCU) 0.25
V
VMCU_ADC0/1_REFP +
MCU_ADC0/1_REFN
MCU_ADC0/1_REFP
+MCU_ADC0/1_REFN
VMCU_ADC0/1_AIN[7:0]
Full-scale Input Range
DNL
Differential Non-Linearity
MCU_ADC0/1_REFP =
VDDA_MCU_ADC0/1,
MCU_ADC0/1_REFN = VSS
INL
Integral Non-Linearity
LSBGAIN-ERROR
VDDA_ADC_MCU
MCU_ADC0/1_REFN
-1
V
MCU_ADC0/1_REFP
V
0.5
TBD
LSB
MCU_ADC0/1_REFP =
VDDA_MCU_ADC0/1,
MCU_ADC0/1_REFN = VSS
±1
±2
LSB
Gain Error
MCU_ADC0/1_REFP =
VDDA_MCU_ADC0/1,
MCU_ADC0/1_REFN = VSS
±2
LSB
LSBOFFSET-ERROR
Offset Error
MCU_ADC0/1_REFP =
VDDA_MCU_ADC0/1,
MCU_ADC0/1_REFN = VSS
±2
LSB
CIN
Input Sampling Capacitance
5.5
pF
SNR
Signal-to-Noise Ratio
Input Signal: 200 kHz sine wave
at -0.5 dB Full Scale,
MCU_ADC0/1_REFP =
VDDA_MCU_ADC0/1,
MCU_ADC0/1_REFN = VSS
70
dB
THD
Total Harmonic Distortion
Input Signal: 200 kHz sine wave
at -0.5 dB Full Scale,
MCU_ADC0/1_REFP =
VDDA_MCU_ADC0/1,
MCU_ADC0/1_REFN = VSS
75
dB
SFDR
Spurious Free Dynamic Range
Input Signal: 200 kHz sine wave
at -0.5 dB Full Scale,
MCU_ADC0/1_REFP =
VDDA_MCU_ADC0/1,
MCU_ADC0/1_REFN = VSS
80
dB
Specifications
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Table 5-6. Analog ADC DC Electrical Characteristics (continued)
over recommended operating conditions (unless otherwise noted)
PARAMETER
SNR(PLUS)
Signal-to-Noise Plus Distortion
Rstatic(MCU_ADC0/1_REFP,
MCU_ADC0/1_REFN)
ADVANCE INFORMATION
Rdynamic(MCU_ADC0/1_REFP,
MCU_ADC0/1_REFN)
TEST CONDITIONS
MIN
TYP
Input Signal: 200 kHz sine wave
at -0.5 dB Full Scale,
MCU_ADC0/1_REFP =
VDDA_MCU_ADC0/1,
MCU_ADC0/1_REFN = VSS
MAX
UNIT
69
dB
Static Input Impedance of
MCU_ADC0/1_REFP relative to
MCU_ADC0/1_REFN
2.2
kΩ
Dynamic Input Impedance of
MCU_ADC0/1_REFP relative to
MCU_ADC0/1_REFN
[1/((65.97 × 10–-12)×
fSMPL_CLK)](1)
Ω
[1/((65.97 × 10–-12) ×
fSMPL_CLK)]
Ω
RMCU_ADC0/1_AIN[0:7]
Input Impedance of
MCU_ADC0/1_AIN[7:0]
f = input frequency
IIN
Input Leakage
MCU_ADC0/1_AIN[7:0] = VSS
MCU_ADC0/1_AIN[7:0] =
VDDA_MCU_ADC0/1
-126
μA
572
μA
Sampling Dynamics
FSMPL_CLK
SMPL_CLK Frequency
tC
Conversion Time
tACQ
Acquisition time
TR
Sampling Rate
CCISO
Channel to Channel Isolation
TBD
2
4
100
Specifications
MCU_ADC0/1_REFN)).
MHz
ADC0/1 SMPL_CLK
Cycles
257
ADC0/1 SMPL_CLK = 60 MHz
(1) The MCU_ADC0/1_REFP and MCU_ADC0/1_REFN source impedance should be ≤ to 1/10 × (Rdynamic(MCU_ADC0/1_REFP,
should be ≤ to 25 Ω on each reference input.
130
60
13
ADC0/1 SMPL_CLK
Cycles
MSPS
dB
For example, for a 60 MHz clock, this source
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Table 5-7. DPHY CSI2 Buffers DC Electrical Characteristics
over operating free-air temperature range (unless otherwise noted)
PARAMETER
MIN
NOM
MAX
UNIT
BALL NAMES in Mode 0: CSI0_RXN0 / CSI0_RXN3 / CSI0_RXN4 / CSI0_RXP0 / CSI0_RXP3 / CSI0_RXP4 / CSI0_RXN1 / CSI0_RXN2
/ CSI0_RXP1 / CSI0_RXP2
BALL NUMBERS: F24 / F26 / F28 / G24 / G25 / G26 / G27 / G28 / H25 / H27
Low-Power Receiver (LP-RX)
VIH
High-level input voltage
VIL
Low-level input voltage
VHYS
Hysteresis
880
mV
550
25
mV
mV
Ultra-Low Power Receiver (ULP-RX)
VITH
High-level input voltage
VITL-ULPM
Low-level input voltage
VHYS
Hysteresis
880
mV
300
25
mV
mV
High Speed Receiver (HS-RX)
Differential input high threshold
VIDTL
Differential input low threshold
70
-70
mV
mV
VIDMAX
Maximum differential input voltage
270
mV
VILHS
Single-ended input low voltage
VIHHS
Single-ended input high voltage
VCMRXDC
Common-mode voltage
-40
mV
460
mV
330
mV
TYP
MAX
UNIT
1.3
1.6
70
Table 5-8. OLDI LVDS Buffers DC Electrical Characteristics
over recommended operating conditions (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
1.8-V MODE
BALL NAMES in Mode 0: OLDI0_A0P/N / OLDI0_A1P/N / OLDI0_A2P/N / OLDI0_A3P/N / OLDI0_CLKP/N
BALL NUMBERS: J24 / J26 / J28 / K24 / K25 / K26 / K27 / K28 / L25 / L27
OLDI LVDS TRANSMITTER
VOH
High Level Output Voltage
VOL
Low Level Output Voltage
VCM
Common Mode Voltage (OLDI)
Differential Load =100Ω
0.9
1.01
1.125
1.25
Common Mode Voltage (sub-LVDS)
V
1.375
0.9
ΔVCM
Difference in Common Mode Output
Voltage, between high/low steady-states
VOD
Differential Output Voltage
250
Reduced Differential Output Voltage
100
ΔVOD
Difference in Differential Output Voltage,
between high/low steady states
IOS
Output Short Circuit Current
PAD/PADN=0,
Differential Load =100Ω
IOZ
Output Tri-State Current
PAD/PADN = 0/VDDS
V
V
V
35
mV
380
450
mV
200
300
mV
50
mV
-5
mA
40
µA
-10
4
(1) VDDS stands for corresponding power supply. For more information on the power supply name and the corresponding ball, see Table 41, POWER [9] column.
Table 5-9. LVCMOS Buffers DC Electrical Characteristics
over recommended operating conditions (unless otherwise noted)
PARAMETER
SPECIFIC BALL
MIN
TYP
MAX
UNIT
BALL NAMES: ALL LVCMOS IOs as defined in Table 4-1, Pin Attributes
BALL NUMBERS: ALL LVCMOS IOs as defined in Table 4-1, Pin Attributes
Specifications
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Table 5-9. LVCMOS Buffers DC Electrical Characteristics (continued)
over recommended operating conditions (unless otherwise noted)
PARAMETER
SPECIFIC BALL
MIN
TYP
MAX
UNIT
1.8-V MODE
VIH
VIL
VHYS
Input high-level threshold
Input low-level threshold
Input hysteresis voltage
TCK ( AA4)
0.60 *
VDDS(1)
All other IOs
0.65 *
VDDS(1)
TCK ( AA4)
0.30 *
VDDS(1)
All other IOs
0.35 *
VDDS(1)
TCK ( AA4)
400
PORz ( E19),
MCU_PORz ( W5),
MCU_BYP_POR ( V5)
ADVANCE INFORMATION
VOL
Output high-level threshold
Output low-level threshold
mV
100
IOH = 100µA
VDDS(1)-0.1
IOH = 2mA
VDDS(1)-0.2
IOH = 4mA
VDDS(1)-0.3
IOH = 6mA
VDDS(1)-0.4
V
IOL = 100µA
0.1
IOL = 2mA
0.2
IOL = 4mA
0.3
IOL = 6mA
IIN
IOZ
V
50
All other IOs
VOH
V
V
0.4
Input leakage current, pull-up or pull-down
inhibited
11.5
Input leakage current, pull-down enabled, VI =
VDDS(1)
65
96
153
Input leakage current, pull-up enabled, VI =
VSS
64
97
154
Total leakage current through the
driver/receiver combination, which may include
an internal pull-up or pull-down. This value
represents the maximum current flowing in or
out of the pin while the output driver is
disabled, the pull-up or pull-down is inhibited,
and the input is swept from VSS to VDD.
11.5
µA
µA
3.3-V MODE
VIH
VIL
VHYS
Input high-level threshold
Input low-level threshold
Input hysteresis voltage
TCK ( AA4)
2
All other IOs
2
TCK ( AA4)
0.8
All other IOs
0.8
TCK ( AA4)
400
PORz ( E19),
MCU_PORz ( W5),
MCU_BYP_POR ( V5)
132
Output high-level threshold
V
mV
50
All other IOs
VOH
V
100
(1)
IOH = 100µA
VDDS -0.1
IOH = 2mA
VDDS(1)-0.2
IOH = 4mA
VDDS(1)-0.3
IOH = 6mA
VDDS(1)-0.45
Specifications
V
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Table 5-9. LVCMOS Buffers DC Electrical Characteristics (continued)
over recommended operating conditions (unless otherwise noted)
IIN
IOZ
Output low-level threshold
SPECIFIC BALL
MIN
TYP
MAX
IOL = 100µA
0.1
IOL = 2mA
0.2
IOL = 4mA
0.3
IOL = 6mA
0.45
Input leakage current, pull-up or pull-down
inhibited
UNIT
V
64
Input leakage current, pull-down enabled, VI =
VDDS(1)
67
100.7
198
Input leakage current, pull-up enabled, VI =
VSS
63
100.3
160
Total leakage current through the
driver/receiver combination, which may include
an internal pull-up or pull-down. This value
represents the maximum current flowing in or
out of the pin while the output driver is
disabled, the pull-up or pull-down is inhibited,
and the input is swept from VSS to VDD.
µA
64
µA
(1) VDDS stands for corresponding power supply. For more information on the power supply name and the corresponding ball, see Table 41, POWER [9] column.
Table 5-10. LVCMOS-FS Buffers DC Electrical Characteristics
over recommended operating conditions (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
BALL NAMES in Mode 0: I2C0_SCL / I2C0_SDA / I2C1_SCL / I2C1_SDA / NMIn
BALL NUMBERS: D20 / C21 / B21 / E21 / F18
1.8-V MODE
VIH
High-level input threshold
VIL
Low-level input threshold
VOH
High-level output threshold
IOH = 1 mA
VOL
Low-level output threshold
IOL = 1 mA
IIN
Input leakage current. This value represents
the maximum current flowing in or out of the
pin while the output driver is disabled and the
input is swept from VSS to VDD.
VI = VDDSHV0
IOZ
1.21
V
0.55
VDDSHV0
- 0.45
VI = VSS
Total leakage current through the
driver/receiver combination, which may
include an internal pull-up or pull-down. This
value represents the maximum current
flowing in or out of the pin while the output
driver is disabled, the pull-up or pull-down is
inhibited, and the input is swept from VSS to
VDD.
V
V
0.45
V
6
µA
2.6
µA
6
µA
3.3-V MODE
VIH
High-level input threshold
VIL
Low-level input threshold
1.21
V
VOH
High-level output threshold
IOH = 100 µA
VOL
Low-level output threshold
IOL = 100 µA
0.2
V
IIN
Input leakage current. This value represents
the maximum current flowing in or out of the
pin while the output driver is disabled and the
input is swept from VSS to VDD.
VI = VDDSHV0
45
µA
1
µA
0.55
VI = VSS
VDDSHV0
- 0.2
V
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PARAMETER
VOL
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Table 5-10. LVCMOS-FS Buffers DC Electrical Characteristics (continued)
over recommended operating conditions (unless otherwise noted)
PARAMETER
IOZ
5.6.1
TEST CONDITIONS
Total leakage current through the
driver/receiver combination, which may
include an internal pull-up or pull-down. This
value represents the maximum current
flowing in or out of the pin while the output
driver is disabled, the pull-up or pull-down is
inhibited, and the input is swept from VSS to
VDD.
MIN
TYP
MAX
45
UNIT
µA
USBHS Buffers DC Electrical Characteristics
NOTE
USB0 and USB1 Electrical Characteristics are compliant with Universal Serial Bus Revision
2.0 Specification dated April 27, 2000 including ECNs and Errata as applicable.
ADVANCE INFORMATION
5.6.2
SERDES Buffers DC Electrical Characteristics
NOTE
The PCIe interfaces are compliant with the electrical parameters specified in PCI Express®
Base Specification Revision 3.1.
NOTE
USB0 instance is compliant with the USB3.1 SuperSpeed Transmitter and Receiver
Normative Electrical Parameters as defined in the Universal Serial Bus 3.1 Specification,
Revision 1.0, July 26, 2013.
134
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5.7
SPRSP31E – APRIL 2018 – REVISED JUNE 2019
VPP Specifications for One-Time Programmable (OTP) eFuses
This section specifies the operating conditions required for programming the OTP eFuses and is
applicable only for High-Security Devices.
Table 5-11. Recommended Operating Conditions for OTP eFuse Programming
over operating free-air temperature range (unless otherwise noted)
DESCRIPTION
MIN
NOM
MAX
UNIT
Supply voltage range for the core domain
during OTP operation; OPP NOM (BOOT)
VPP_CORE
Supply voltage range for the eFuse ROM
domain during normal operation
NC(2)
V
Supply voltage range for the eFuse ROM
domain during OTP programming (1)
NC(2)
V
Supply voltage range for the eFuse ROM
domain during normal operation
NC(2)
V
VPP_MCU
Supply voltage range for the eFuse ROM
domain during OTP programming (1)
See Section 5.4
1.71
1.8
0
25
I(VPP_MCU)
Tj
Temperature (junction)
V
1.89
V
100
mA
85
ºC
(1) Supply voltage range includes DC errors and peak-to-peak noise. TI power management solutions TLV70718 from the TLV707x family
meet the supply voltage range needed for VPP_MCU.
(2) NC stands for No Connect.
5.7.1
Hardware Requirements
The following hardware requirements must be met when programming keys in the OTP eFuses:
• The VPP_MCU power supply must be disabled when not programming OTP registers.
• The VPP_MCU power supply must be ramped up after the proper device power-up sequence (for
more details, see Section 5.9.2).
5.7.2
Programming Sequence
Programming sequence for OTP eFuses:
• Power on the board per the power-up sequencing. No voltage should be applied on the VPP_MCU
terminal during power up and normal operation.
• Load the OTP write software required to program the eFuse (contact your local TI representative for
the OTP software package).
• Apply the voltage on the VPP_MCU terminal according to the specification in Table 5-11.
• Run the software that programs the OTP registers.
• After validating the content of the OTP registers, remove the voltage from the VPP_MCU terminal.
5.7.3
Impact to Your Hardware Warranty
You accept that e-Fusing the TI Devices with security keys permanently alters them. You acknowledge
that the e-Fuse can fail, for example, due to incorrect or aborted program sequence or if you omit a
sequence step. Further the TI Device may fail to secure boot if the error code correction check fails for the
Production Keys or if the image is not signed and optionally encrypted with the current active Production
Keys. These types of situations will render the TI Device inoperable and TI will be unable to confirm
whether the TI Devices conformed to their specifications prior to the attempted e-Fuse.
CONSEQUENTLY, TI WILL HAVE NO LIABILITY (WARRANTY OR OTHERWISE) FOR ANY TI
DEVICES THAT HAVE BEEN e-FUSED WITH SECURITY KEYS.
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PARAMETER
VDD_MCU
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5.8
www.ti.com
Thermal Resistance Characteristics
This section provides the thermal resistance characteristics used on this device.
For reliability and operability concerns, the maximum junction temperature of the Device has to be at or
below the TJ value identified in Section 5.4, Recommended Operating Conditions.
Table 5-12. Thermal Resistance Characteristics
It is recommended to perform thermal simulations at the system level with the worst case device power consumption.
NO.
NAME
DESCRIPTION
ACD
°C/W
AIR FLOW
(m/s)
0.2
N/A
T1
RΘJC
Junction-to-case
T2
RΘJB
Junction-to-board
3.1
N/A
Junction-to-free air
12.8
0
7.4
1
6.5
2
T6
6
3
T7
0.1
0
T8
0.1
1
T3
T4
T5
ADVANCE INFORMATION
T9
RΘJA
ΨJT
Junction-to-moving air
Junction-to-package top
0.1
2
T10
0.1
3
T11
2.9
0
2.4
1
2.3
2
2.3
3
T12
T13
ΨJB
Junction-to-board
T14
(1) These values are based on a JEDEC defined 2S2P system (with the exception of the Theta JC [RΘJC] value, which is based on a
JEDEC defined 1S0P system) and will change based on environment as well as application. For more information, see these
EIA/JEDEC standards:
– JESD51-2, Integrated Circuits Thermal Test Method Environment Conditions - Natural Convection (Still Air)
– JESD51-3, Low Effective Thermal Conductivity Test Board for Leaded Surface Mount Packages
– JESD51-6, Integrated Circuit Thermal Test Method Environmental Conditions - Forced Convection (Moving Air)
– JESD51-7, High Effective Thermal Conductivity Test Board for Leaded Surface Mount Packages
– JESD51-9, Test Boards for Area Array Surface Mount Packages
(2) m/s = meters per second.
(3) °C/W = degrees Celsius per watt.
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5.9
SPRSP31E – APRIL 2018 – REVISED JUNE 2019
Timing and Switching Characteristics
NOTE
The Timing Requirements and Switching Characteristics values may change following the
silicon characterization result.
NOTE
The default SLEWRATE settings in each pad configuration register must be used to ensure
timings, unless specific instructions are given otherwise.
5.9.1
Timing Parameters and Information
ADVANCE INFORMATION
The timing parameter symbols used in Section 5.9 are created in accordance with JEDEC Standard 100.
To shorten the symbols, some pin names and other related terminologies have been abbreviated in
Table 5-13:
Table 5-13. Timing Parameters Subscripts
SYMBOL
PARAMETER
c
Cycle time (period)
d
Delay time
dis
Disable time
en
Enable time
h
Hold time
su
Setup time
START
Start bit
t
Transition time
v
Valid time
w
Pulse duration (width)
X
Unknown, changing, or don't care level
F
Fall time
H
High
L
Low
R
Rise time
V
Valid
IV
Invalid
AE
Active Edge
FE
First Edge
LE
Last Edge
Z
High impedance
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5.9.2
www.ti.com
Power Supply Sequencing
This section describes the power-up sequence required to ensure proper device operation. The power
supply names described in this section comprise a superset of a family of compatible devices. Some
members of this family will not include a subset of these power supplies and their associated device
modules.
NOTE
All timing requirements and switching characteristics in Section 5.9.3 should be strictly
followed unless otherwise specified.
5.9.2.1
Power Supply Slew Rate Requirement
To maintain the safe operating range of the internal ESD protection devices, TI recommends limiting the
maximum slew rate of supplies to be less than 1.0E + 5 V/s. For instance, as shown in Figure 5-2, TI
recommends having the supply ramp slew for a 1.8-V supply of more than 18 μs.
Figure 5-2 describes the Power Supply Slew Rate Requirement of the device.
ADVANCE INFORMATION
Supply value
t
slew rate < 1E + 5 V/s
slew > (supply value) / (1E + 5V/s)
supply value x 10 µs
SPRSP08_ELCH_06
Figure 5-2. Power Supply Slew and Slew Rate
5.9.2.2
Power-Up Sequencing
Figure 5-3 describes the Power-Up Sequencing using On Chip Power-on-reset (POR) of the device.
138
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VDDA_3P3_IOLDO_WKUP,
VDDA_3P3_IOLDO0, VDDA_3P3_IOLDO1,
VDDA_3P3_SDIO, VDDA_3P3_USB
(2)
(2)
(2)
(2)
VDDS0_WKUP , VDDS1_WKUP , VDDS2_WKUP , VDDS0 ,
(2)
(2)
(2)
(2)
(2)
(2)
VDDS1 ,VDDS2 , VDDS3 , VDDS4 , VDDS5 , VDDS6 ,
(2)
(2)
VDDS7 , VDDS8 , VDDA_1P8_CSI0, VDDA_1P8_OLDI0,
VDDA_1P8_SERDES0, VDDA_MCU, VDDA_PLL_CORE,
VDDA_PLL0_DDR, VDDA_PLL1_DDR, VDDA_PLL_DSS,
VDDA_PLL_MPU0, VDDA_PLL_MPU1, VDDA_PLL_PER0,
VDDA_ADC_MCU, VDDA_LDO_WKUP, VDDA_POR_WKUP,
VDDA_SRAM_CORE0, VDDA_SRAM_CORE1, VDDA_SRAM_MPU0,
VDDA_SRAM_MPU1, VDDA_WKUP, VDDS_OSC1
VDDSHV0_WKUP,VDDSHV1_WKUP, VDDSHV2_WKUP,
VDDSHV0, VDDSHV1, VDDSHV2, VDDSHV3, VDDSHV4,
VDDSHV5, VDDSHV6, VDDSHV7, VDDSHV8
Note 6
VDDS_DDR
Note 10
VDD_WKUP0, VDD_WKUP1
ADVANCE INFORMATION
VDD_MCU
VDD_CORE, VDD_DLL_MMC0, VDD_DLL_MMC1
VDD_MPU0, VDD_MPU1
WKUP_OSC0_XI, WKUP_OSC0_XO
(12)
(3)(12)
WKUP_LFOSC0_XI, WKUP_LFOSC0_XO
(optional)
(9)(12)
OSC1_XI, OSC1_XO
(optional)
Note 7
PORz, MCU_PORz
PORz_OUT, MCU_PORz_OUT
(4)
(11)
MCU_BYP_POR
Note 8
RESETz, MCU_RESETz
RESETSTATz, MCU_RESETSTATz
SPRSP08_ELCH_03
Figure 5-3. Power-Up Sequencing using On Chip Power-on-reset (POR)
(1) Grey shaded areas are windows where it is valid to ramp the voltage rail.
(2) The VDDS[2:0]_WKUP, VDDS[8:0] are sourced from the same 1.8 V VDDSHV[2:0]_WKUP, VDDSHV[8:0] supply. If
VDDSHV[2:0]_WKUP, VDDSHV[8:0] is configured as 3.3 V, VDDS[2:0]_WKUP, VDDS[8:0] should be sourced from the internal IO bias
LDO.
(3) WKUP_LFOSC0 crystal clock source is enabled by default. For the oscillator start-up time, see Table 5-18, WKUP_OSC0 Switching
Characteristics – Crystal Mode. For more information about WKUP_LFOSC0 clock source configuration, refer to device TRM.
(4) PORz should be pulled to VDDSHV0. MCU_PORz should be pulled to VDDSHV0_WKUP.
(5) Blue dashed lines are not valid windows but show alternate ramp possibilities based on the associated note.
(6) If any of the VDDSHV[0-8], VDDSHV[2:0]_WKUP rails are used as 3.3 V only, then these rails must be ramped-up with the 3.3 V power
supplies.
(7) If any of the PORz, MCU_PORz signals are configured at 3.3 V only, then these signals must be ramped-up at the same time with the
3.3 V power supplies.
(8) If any of the RESETz, MCU_RESETz signals are configured at 3.3 V only, then these signals must be ramped-up at the same time with
the 3.3 V power supplies.
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(9) OSC1 crystal clock sources is enabled by default. For the oscillator start-up time, see Table 5-22, OSC1 Switching Characteristics –
Crystal Mode. For more information about OSC1 clock source configuration, refer to device TRM.
(10) If WKUP LDO is used to power the WKUP domain, connect CAP_VDD_WKUP pin to VDD_WKUP0/1 pin. VDD_WKUP0/1 will start
ramping after VDDA_LDO_WKUP reaches a certain threshold. If WKUP LDO is bypassed, connect VDD_WKUP0/1 with VDD_MCU.
(11) PORz_OUT and MCU_PORz_OUT should be pulled down.
(12) Refer to the Clock Specifications section for the oscillator start-up time.
Figure 5-4 describes the Power-Up Sequencing using External Power-on-reset (POR), bypassing on-chip
POR circuit of the device.
VDDA_3P3_IOLDO_WKUP,
VDDA_3P3_IOLDO0, VDDA_3P3_IOLDO1,
VDDA_3P3_SDIO, VDDA_3P3_USB
(2)
(2)
(2)
(2)
VDDS0_WKUP , VDDS1_WKUP , VDDS2_WKUP , VDDS0 ,
VDDS1(2),VDDS2(2), VDDS3(2), VDDS4(2), VDDS5(2), VDDS6(2),
(2)
(2)
VDDS7 , VDDS8 , VDDA_1P8_CSI0, VDDA_1P8_OLDI0,
VDDA_1P8_SERDES0, VDDA_MCU, VDDA_PLL_CORE,
VDDA_PLL0_DDR, VDDA_PLL1_DDR, VDDA_PLL_DSS,
VDDA_PLL_MPU0, VDDA_PLL_MPU1, VDDA_PLL_PER0,
VDDA_ADC_MCU, VDDA_LDO_WKUP, VDDA_POR_WKUP,
VDDA_SRAM_CORE0, VDDA_SRAM_CORE1, VDDA_SRAM_MPU0,
VDDA_SRAM_MPU1, VDDA_WKUP, VDDS_OSC1
ADVANCE INFORMATION
VDDSHV0_WKUP,VDDSHV1_WKUP, VDDSHV2_WKUP,
VDDSHV0, VDDSHV1, VDDSHV2, VDDSHV3, VDDSHV4,
VDDSHV5, VDDSHV6, VDDSHV7, VDDSHV8
Note 6
VDDS_DDR
Note 11
VDD_WKUP0, VDD_WKUP1
VDD_MCU
VDD_CORE, VDD_DLL_MMC0, VDD_DLL_MMC1
VDD_MPU0, VDD_MPU1
WKUP_OSC0_XI, WKUP_OSC0_XO
(13)
WKUP_LFOSC0_XI, WKUP_LFOSC0_XO(3)(13)
(optional)
OSC1_XI, OSC1_XO(9)(13)
(optional)
PORz, MCU_PORz
PORz_OUT, MCU_PORz_OUT
(4)
(12)
Note 7
MCU_BYP_POR
(5)
Note 8
RESETz, MCU_RESETz
RESETSTATz, MCU_RESETSTATz
SPRSP08_ELCH_04
Figure 5-4. Power-Up Sequencing using External Power-on-reset (POR), bypassing on-chip POR circuit
(1) Grey shaded areas are windows where it is valid to ramp the voltage rail.
(2) The VDDS[2:0]_WKUP, VDDS[8:0] are sourced from the same 1.8 V VDDSHV[2:0]_WKUP, VDDSHV[8:0] supply. If
VDDSHV[2:0]_WKUP, VDDSHV[8:0] is configured as 3.3 V, VDDS[2:0]_WKUP, VDDS[8:0] should be sourced from the internal IO bias
LDO.
(3) WKUP_LFOSC0 crystal clock source is enabled by default. For the oscillator start-up time, see Table 5-18, WKUP_OSC0 Switching
140
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Characteristics – Crystal Mode. For more information about WKUP_LFOSC0 clock source configuration, refer to device TRM.
(4) PORz should be pulled to VDDSHV0. MCU_PORz should be pulled to VDDSHV0_WKUP.
(5) MCU_BYP_POR should be pulled to VDDSHV0_WKUP.
(6) If any of the VDDSHV[0-8] rails are used as 3.3 V only, then these rails must be ramped-up with the 3.3 V power supplies.
(7) If MCU_BYP_POR is configured at 3.3 V only, then this signal must be ramped-up at the same time with the 3.3 V power supplies.
(8) If any of the RESETz, MCU_RESETz signals are configured at 3.3 V only, then these signals must be ramped-up at the same time with
the 3.3 V power supplies.
(9) OSC1 crystal clock sources is enabled by default. For the oscillator start-up time, see Table 5-22, OSC1 Switching Characteristics –
Crystal Mode. For more information about OSC1 clock source configuration, refer to device TRM.
(10) Blue dashed lines are not valid windows but show alternate ramp possibilities based on the associated note.
(11) If WKUP LDO is used to power the WKUP domain, connect CAP_VDD_WKUP pin to VDD_WKUP0/1 pin. VDD_WKUP0/1 will start
ramping after VDDA_LDO_WKUP reaches a certain threshold. If WKUP LDO is bypassed, connect VDD_WKUP0/1 with VDD_MCU.
(12) PORz_OUT and MCU_PORz_OUT should be pulled down.
(13) Refer to the Clock Specifications section for the oscillator start-up time.
Power-Down Sequencing
A typical power down sequence is to have the Power-on-Reset asserted, clock shut down, and ramp down
all the power supplies sequentially in the exact reverse order of the power-up sequencing. In other words,
the power supply that has been ramped up first should be the last one that is ramped down.
For DRA80x, there are no specific power-down sequencing requirements, except for asserting Power-onReset before ramping down the rails while bypassing internal POR.
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5.9.2.3
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5.9.3
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Reset Timing
5.9.3.1
Reset Electrical Data/Timing
For more details about features and additional description information on the subsystem multiplexing
signals, see the corresponding sections within Section 4.3, Signal Descriptions and Section 6, Detailed
Description.
Table 5-14, Table 5-15, Figure 5-5, and Figure 5-6 present the reset timing requirements and switching
characteristics.
Table 5-14. Reset Timing Requirements
NO.
PARAMETER
DESCRIPTION
MIN
RST1
tw(PORzL)
Pulse Width minimum, PORz low
RST2
th(SUPPLIES VALID - PORz)
Hold time, PORz active (low) after all supplies valid
MAX
UNIT
PORz Pin
2000
ns
2000000
ns
400
ns
2000
ns
2000000
ns
400
ns
1000000
ns
RESETz Pin
RST5
tw(RESETzL)
Pulse Width minimum, RESETz low
ADVANCE INFORMATION
MCU_PORz Pin
RST13
tw(MCU_PORzL)
Pulse Width minimum, MCU_PORz
RST8
th(SUPPLIES VALID -
Hold time, MCU_PORz active (low) after all supplies valid
MCU_PORz)
MCU_RESETz Pin
RST9
tw(MCU_RESETzL)
Pulse Width minimum, MCU_RESETz
MCU_BYP_POR Pin
RST12
tsu(MCU_BYP_POR-MCU_PORz) Setup time, MCU_BYP_POR active (high) before all supplies are
valid
Table 5-15. Reset Switching Characteristics
NO.
PARAMETER
DESCRIPTION
MIN
MAX
UNIT
RST3
td(PORz-PORz_OUT low)
Delay time, PORz active (low) to PORz_OUT active (low)
0
ns
RST4
td(PORz-PORz_OUT high)
Delay time, PORz inactive (high) to PORz_OUT inactive (high)
0
ns
PORz Pin
RESETz Pin
RST6
td(RESETz-RESETSTATz low)
Delay time, RESETz active (low) to RESETSTATz active (low)
RST7
td(RESETz-RESETSTATz high)
Delay time, RESETz inactive (high) to RESETSTATz inactive
(high)
4106
ns
380000
ns
RST10
td(MCU_RESETz-
Delay time, MCU_RESETz active (low) to MCU_RESETSTATz
active (low)
4106
ns
289000
ns
Delay time, MCU_PORz active (low) to MCU_PORz_OUT active
(low)
0
ns
Delay time, MCU_PORz inactive (high) to MCU_PORz_OUT
inactive (high)
0
ns
MCU_RESETSTATz Pin
MCU_RESETSTATz low)
RST11
td(MCU_RESETzMCU_RESETSTATz high)
Delay time, MCU_RESETz inactive (high) to MCU_RESETSTATz
inactive (high)
MCU_PORz Pin
RST14
td(MCU_PORz-MCU_PORz_OUT
low)
RST15
td(MCU_PORz-MCU_PORz_OUT
high)
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RST1
PORz
RST4
RST3
PORz_OUT
All Supplies Valid
RST2
RST13
RST8
MCU_PORz
RST14
RST15
MCU_PORz_OUT
ADVANCE INFORMATION
RST12
MCU_BYP_POR
SPRSP08_PORz_Reset_Timing
Figure 5-5. PORz Reset Timing
RST5
RESETz
RST6
RESETSTATz
RST7
SPRSP08_RESETz_Timing
Figure 5-6. RESETz and RESETSTATz Timing
RST9
MCU_RESETz
RST10
MCU_RESETSTATz
RST11
SPRSP08__MCU_RESETz_Timing
Figure 5-7. MCU_RESETz and MCU_RESETSTATz Timing
Table 5-16 and Figure 5-8 present the boot configuration timing requirements.
Table 5-16. Boot Configuration Timing Requirements
NO.
PARAMETER
BC1
tsu(BOOTMODE-PORz)
Setup time, All Bootmode pins active to PORz inactive (high)
BC2
th(PORz - BOOTMODE)
Hold time, All Bootmode pins active after PORz inactive (high)
BC3
tsu(MCU_BOOTMODE-MCU_PORz) Setup time, All Bootmode pins active to MCU_PORz inactive
(high)
MIN
MAX
2000
ns
0
ns
2000
ns
Specifications
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Table 5-16. Boot Configuration Timing Requirements (continued)
NO.
PARAMETER
BC4
th(MCU_PORz MCU_BOOTMODE)
MIN
Hold time, All Bootmode pins active after MCU_PORz inactive
(high)
0
MAX
UNIT
ns
BC1
PORz
BOOTMODE[18:00]
BC2
BC3
MCU_PORz
ADVANCE INFORMATION
MCU_BOOTMODE[09:00]
BC 4
Figure 5-8. Boot Configuration Timing
5.9.4
Clock Specifications
5.9.4.1
Input Clocks / Oscillators
Various external clock inputs are needed to drive the device. Summary of these input clock signals are:
• OSC1_XO/OSC1_XI — Еxternal main crystal interface pins connected to internal oscillator which
sources reference clock and provides reference clock to PLLs within MAIN domain. Also, for audio
applications, high-frequency oscillator 0 is used to provide audio clock frequencies to MCASPs.
• WKUP_OSC0_XO/WKUP_OSC0_XI — Еxternal main crystal interface pins connected to internal
oscillator which sources reference clock and provides reference clock to PLLs within MCU domain and
MAIN domain.
• WKUP_LFOSC_XO/WKUP_LFOSC_XI — External main crystal interface pins connected to internal
oscillator which sources reference clock provides a clock for low power operation in deeper sleep
modes.
• MCU_EXT_REFCLK0 — Optional external system clock input (MCU domain).
• EXT_REFCLK1— Optional external System clock input (MAIN domain). Optionally PLL2 (PER1) and
MCASP can be sourced by EXT_REFCLK1 (sourced externally).
• SERDES0_REFCLK P/N and SERDES1_REFCLK P/N — SerDes reference clock for PCIe or Optional
USB3.0 PHY.
• MCU_CPTS0_RFT_CLK — CPTS reference clock inputs for MCU_CPTS0_RFT_CLK.
• CPTS_RFT0_CLK — CPTS reference clock inputs for CPTS0_RFT_CLK.
• VOUT1_EXTPCLKIN — Optional for the DPI1 Port of DSS.
• REFCLK0 P/N and REFCLK1 P/N — There are 2 differential clock output pins to support 2 PCIe
devices.
Figure 5-9 shows the external input clock sources to peripherals.
144
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DEVICE
Selects Main PLL output divide-by-4
SYSCLK0
Optional pins to provide reference clock input to the PLLs.
MCU_SYSCLKOUT0
MCU_OBSCLK0
Observation clock output for MCU Domain clocks
WKUP_OSC0_XI
Еxternal main crystal interface pins connected to
internal oscillator whichsources reference clock.
Provides reference clock to PLLs within WKUP and MAIN domain.
WKUP_OSC0_XO
WKUP_LFOSC0_XI
Optional external low frequency crystal interface pins connected
to internal oscillator which provides a 32.768 KHz clock for
low power operation in deeper sleep modes.
WKUP_LFOSC0_XO
OSC1_XO
ADVANCE INFORMATION
Optional external crystal interface pins connected to internal
oscillator which sources reference clock. Provides reference clock to
PLLs within MCU domain and MAIN domain. This high-frequency oscillator
is used to provide audio clock frequencies to MCASPs.
OSC1_XI
JTAG Clock Input
TCK
EXT_REFCLK1
Optional external System clock input (MAIN domain)
MCU Warm Reset Input / Device Warm Reset Input
MCU_RESETz/ RESETz
MCU_PORz / PORz
MCU Power ON Reset / Device Power ON Reset
BOOTMODE[18:00]
Boot Mode Configuration / devices select
MCU_BOOTMODE[09:00]
MCU Boot Mode system clock speed and fail-safe boot device
DDR_CK0P/DDR_CK0N
DDR Differential Clock outputs
DDR_CK1P/DDR_CK1N
REFCLK0 P/N
There are 2 differential clock output pins to support 2 PCIe
devices
REFCLK1 P/N
Observation clock output for MAIN and MCU Domain clocks
OBSCLK0
SERDES0_REFCLK P/N
SerDes reference clock input for PCIe or Optional USB3SS0 PHY
SERDES1_REFCLK P/N
MCU_CPTS0_RFT_CLK
CPTS reference clock input for MCU_CPTS_RFT_CLK
Optional external system clock input (MCU domain)
MCU_EXT_REFCLK0
Optional for the DPI1 Port of DSS
VOUT1_EXTPCLKIN
CPTS reference clock input for CPTS_RFT_CLK
CPTS0_RFT_CLK
SPRSP08_CLOCK_01
Figure 5-9. Input Clocks Interface
For more information about Input clock interfaces, see section Clocking in the device TRM.
Specifications
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5.9.4.1.1 WKUP_OSC0 Internal Oscillator Clock Source
Figure 5-10 shows the recommended crystal circuit. It is recommended that preproduction printed-circuit
board (PCB) designs include the two optional resistors Rbias and Rd in case they are required for proper
oscillator operation when combined with production crystal circuit components. In most cases, Rbias is not
required and Rd is a 0-Ω resistor. These resistors may be removed from production PCB designs after
evaluating oscillator performance with production crystal circuit components installed on preproduction
PCBs.
Device
WKUP_OSC0_XO
WKUP_OSC0_XI
Rd
(Optional)
Crystal
ADVANCE INFORMATION
(Optional) Rbias
Cf2
Cf1
PCB Ground
SPRSP08_PCB_CLK_OSC_2
Figure 5-10. WKUP_OSC0 Crystal Implementation
NOTE
The load capacitors, Cf1 and Cf2 in Figure 5-11, should be chosen such that the below
equation is satisfied. CL in the equation is the load specified by the crystal manufacturer. All
discrete components used to implement the oscillator circuit should be placed as close as
possible to the associated oscillator WKUP_OSC0_XI, WKUP_OSC0_XO, and VSS pins.
CL=
Cf1Cf2
(Cf1+Cf2)
SPRS932_CLOCK_03
Figure 5-11. Load Capacitance Equation
The crystal must be in the fundamental mode of operation and parallel resonant. Table 5-17 summarizes
the required electrical constraints.
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Table 5-17. WKUP_OSC0 Crystal Electrical Characteristics
DESCRIPTION
MIN
TYP
MAX
UNIT
Parallel resonance crystal frequency
19.2, 20, 24, 25, 26, 27
Cf1
Cf1 load capacitance for crystal parallel resonance with Cf1 = Cf2
12
24
pF
Cf2
Cf2 load capacitance for crystal parallel resonance with Cf1 = Cf2
12
24
pF
ESR(Cf1,Cf2)
Crystal ESR
ESR = 30 Ω
ESR = 40 Ω
ESR = 50 Ω
CO
ESR = 60 Ω
Crystal shunt capacitance
100
Ω
19.2 MHz, 20 MHz, 24
MHz, 25 MHz, 26 MHz, 27
MHz
7
pF
19.2 MHz, 20 MHz
7
pF
24 MHz, 25 MHz, 26 MHz,
27 MHz
5
pF
19.2 MHz, 20 MHz
7
pF
24 MHz, 25 MHz, 26 MHz,
27 MHz
Not Supported
19.2 MHz, 20 MHz
ESR = 80 Ω
LM
Crystal motional inductance for fp = 20 MHz
CM
Crystal motional capacitance
fj(WKUP_OSC0_XI)
Frequency accuracy, WKUP_OSC0_XI
5
24 MHz, 25 MHz, 26 MHz,
27 MHz
pF
Not Supported
19.2 MHz, 20 MHz
ESR = 100 Ω
MHz
3
24 MHz, 25 MHz, 26 MHz,
27 MHz
pF
Not Supported
-
10.16
mH
3.42
fF
Ethernet RGMII and RMII
not used
±100
Ethernet RGMII and RMII
using derived clock
±50
ppm
When selecting a crystal, the system design must consider the temperature and aging characteristics of a
based on the worst case environment and expected life expectancy of the system.
Table 5-18 details the switching characteristics of the oscillator and the requirements of the input clock.
Table 5-18. WKUP_OSC0 Switching Characteristics – Crystal Mode
NAME
DESCRIPTION
fp
Oscillation frequency
tsX
Start-up time
MIN
TYP
MAX
19.2, 20, 24, 25, 26, 27
UNIT
MHz
2(1)
ms
Specifications
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NAME
fp
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(1) In order to meet the start-up time defined in this table, the crystal needs to be selected according to the following equation:
Tsu = K*Lm/ (Ro-ESR) + Δt
where Lm is crystal motional inductance, RO is the negative resistance of amplifier, ESR is the crystal Effective series resistance and K
is a constant which represents the initial conditions. Δt is the time amplifier takes to reach its bias point after power down is released.
VDD_WKUP (min.)
VDD_WKUP
Voltage
VSS
VDDA_WKUP (min.)
VDDA_WKUP
WKUP_OSC0_XO
VSS
tsX
ADVANCE INFORMATION
Time
Figure 5-12. WKUP_OSC0 Start-up Time
5.9.4.1.2 WKUP_OSC0 LVCMOS Digital Clock Source
Figure 5-13 shows the recommended oscillator connections when WKUP_OSC0 is connected to an
LVCMOS square-wave digital clock source The 1.8-V LVCMOS-Compatible clock source is connected to
the WKUP_OSC0_XI pin. In this mode of operation, the WKUP_OSC0_XO pin is left unconnected and
should not be used to source any external components.
Device
WKUP_OSC0_XI
WKUP_OSC0_XO
VSS
NC
PCB Ground
SPRSP08_CLK_02
Figure 5-13. 1.8-V LVCMOS-Compatible Clock Input
Table 5-19 summarizes the WKUP_OSC0 input clock electrical characteristics
Table 5-19. WKUP_OSC0 Switching Characteristics – Crystal Mode
NAME
f
148
DESCRIPTION
MIN
Frequency
CIN
Input capacitance
IIN
Input current (3.3V mode)
TYP
MAX
19.2, 20, 24, 25, 26, 27
UNIT
MHz
2.184
2.384
2.584
pF
4
6
10
µA
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Table 5-20 details the WKUP_OSC0 input clock timing requirements.
Table 5-20. WKUP_OSC0 Input Clock Timing Requirements
DESCRIPTION
MIN
CK0
1/
tc(WKUP_OSC0_XI)
Frequency, WKUP_OSC0_XI
CK1
tw(WKUP_OSC0_XI)
Pulse duration, WKUP_OSC0_XI low or high
tj(WKUP_OSC0_XI)
Period jitter, WKUP_OSC0_XI
tR(WKUP_OSC0_XI)
tF(WKUP_OSC0_XI)
tj(WKUP_OSC0_XI)
TYP
MAX
UNIT
19.2, 20, 24, 25, 26, 27
0.55 ×
tc(WKUP_OSC0_XI)
ns
0.01 ×
tc(WKUP_OSC0_XI)
ns
Rise time, WKUP_OSC0_XI
5
ns
Fall time, WKUP_OSC0_XI
5
ns
Frequency accuracy,
WKUP_OSC0_XI
0.45 ×
tc(WKUP_OSC0_XI)
MHz
Ethernet RGMII and RMII
not used
±100
Ethernet RGMII and RMII
using derived clock
±50
ppm
CK0
CK1
CK1
WKUP_OSC0_XI
Figure 5-14. WKUP_OSC0_XI Input Clock
5.9.4.1.3 Auxiliary OSC1 Internal Oscillator Clock Source
Figure 5-15 shows the recommended crystal circuit. It is recommended that preproduction printed-circuit
board (PCB) designs include the two optional resistors Rbias and Rd in case they are required for proper
oscillator operation when combined with production crystal circuit components. In most cases, Rbias is not
required and Rd is a 0-Ω resistor. These resistors may be removed from production PCB designs after
evaluating oscillator performance with production crystal circuit components installed on preproduction
PCBs.
Device
OSC1_XO
OSC1_XI
Rd
(Optional)
Crystal
(Optional) Rbias
Cf1
Cf2
PCB Ground
SPRSP08_PCB_CLK_OSC_1
Figure 5-15. OSC1 Crystal Implementation
Specifications
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NAME
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NOTE
The load capacitors, Cf1 and Cf2 in Figure 5-16, should be chosen such that the below
equation is satisfied. CL in the equation is the load specified by the crystal manufacturer. All
discrete components used to implement the oscillator circuit should be placed as close as
possible to the associated oscillator OSC1_XI, OSC1_XO, and VSS pins.
CL=
Cf1Cf2
(Cf1+Cf2)
SPRS932_CLOCK_03
Figure 5-16. Load Capacitance Equation
The crystal must be in the fundamental mode of operation and parallel resonant. Table 5-21 summarizes
the required electrical constraints.
Table 5-21. OSC1 Crystal Electrical Characteristics
ADVANCE INFORMATION
NAME
DESCRIPTION
MIN
TYP
MAX
19.2, 20, 24, 25, 26, 27
UNIT
fp
Parallel resonance crystal frequency
Cf1
Cf1 load capacitance for crystal parallel resonance with Cf1 = Cf2
12
24
pF
Cf2
Cf2 load capacitance for crystal parallel resonance with Cf1 = Cf2
12
24
pF
ESR(Cf1,Cf2)
Crystal ESR
100
Ω
19.2 MHz, 20 MHz, 24
MHz, 25 MHz, 26 MHz, 27
MHz
7
pF
19.2 MHz, 20 MHz
7
pF
24 MHz, 25 MHz, 26 MHz,
27 MHz
5
pF
19.2 MHz, 20 MHz
7
pF
ESR = 30 Ω
ESR = 40 Ω
ESR = 50 Ω
CO
ESR = 60 Ω
Crystal shunt capacitance
24 MHz, 25 MHz, 26 MHz,
27 MHz
Not Supported
19.2 MHz, 20 MHz
ESR = 80 Ω
LM
Crystal motional inductance for fp = 20 MHz
CM
Crystal motional capacitance
fj(OSC1_XI)
Frequency accuracy, OSC1_XI
5
24 MHz, 25 MHz, 26 MHz,
27 MHz
pF
Not Supported
19.2 MHz, 20 MHz
ESR = 100 Ω
MHz
3
24 MHz, 25 MHz, 26 MHz,
27 MHz
pF
Not Supported
-
10.16
mH
3.42
fF
Ethernet RGMII and RMII
not used
±100
Ethernet RGMII and RMII
using derived clock
±50
ppm
When selecting a crystal, the system design must consider the temperature and aging characteristics of a
based on the worst case environment and expected life expectancy of the system.
Table 5-22 details the switching characteristics of the oscillator and the requirements of the input clock.
Table 5-22. OSC1 Switching Characteristics – Crystal Mode
NAME
fp
tsX
150
DESCRIPTION
MIN
Oscillation frequency
TYP
MAX
19.2, 20, 24, 25, 26, 27
Start-up time
MHz
2
Specifications
UNIT
(1)
ms
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(1) In order to meet the start-up time defined in this table, the crystal needs to be selected according to the following equation:
Tsu = K*Lm/ (Ro-ESR) + Δt
where Lm is crystal motional inductance, RO is the negative resistance of amplifier, ESR is the crystal Effective series resistance and K
is a constant which represents the initial conditions. Δt is the time amplifier takes to reach its bias point after power down is released.
VDD_CORE (min.)
VDD_CORE
VDDS_OSC1 (min.)
VDDS_OSC1
OSC1_XO
VSS
tsX
Time
Figure 5-17. OSC1 Start-up Time
5.9.4.1.4 Auxiliary OSC1 LVCMOS Digital Clock Source
Figure 5-18 shows the recommended oscillator connections when OSC1 is connected to an LVCMOS
square-wave digital clock source The 1.8-V LVCMOS-Compatible clock source is connected to the
OSC1_XI pin. In this mode of operation, the OSC1_XO pin is left unconnected and should not be used to
source any external components.
Device
OSC1_XI
OSC1_XO
VSS
NC
PCB Ground
SPRSP08_CLK_01
Figure 5-18. 1.8-V LVCMOS-Compatible Clock Input
Table 5-23 summarizes the OSC1 input clock electrical characteristics.
Table 5-23. OSC1 Switching Characteristics – Crystal Mode
NAME
f
DESCRIPTION
MIN
Frequency
CIN
Input capacitance
IIN
Input current (3.3V mode)
TYP
MAX
19.2, 20, 24, 25, 26, 27
UNIT
MHz
2.184
2.384
2.584
pF
4
6
10
µA
Specifications
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Voltage
VSS
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Table 5-24 details the OSC1 input clock timing requirements.
Table 5-24. OSC1 Input Clock Timing Requirements
NAME
CK0
CK1
DESCRIPTION
1 / tc(OSC1_XI)
MIN
Frequency, OSC1_XI
tw(OSC1_XI)
Pulse duration, OSC1_XI low or high
tj(OSC1_XI)
Period jitter, OSC1_XI
tR(OSC1_XI)
Rise time, OSC1_XI
tF(OSC1_XI)
Fall time, OSC1_XI
tj(OSC1_XI)
TYP
MAX
19.2, 20, 24, 25, 26, 27
Frequency accuracy, OSC1_XI
UNIT
MHz
0.45 ×
0.55 ×
tc(OSC1_XI)
tc(OSC1_XI)
ns
0.01 ×
tc(OSC1_XI)
ns
5
ns
5
ns
Ethernet RGMII and RMII
not used
±100
Ethernet RGMII and RMII
using derived clock
±50
ppm
CK0
CK1
CK1
ADVANCE INFORMATION
OSC1_XI
Figure 5-19. OSC1_XI Input Clock
5.9.4.1.5 Auxiliary OSC1 Not Used
For more Information see Section 4.5, Connections for Unused Pins.
5.9.4.1.6 WKUP_LFOSC0 Internal Oscillator Clock Source
Figure 5-20 shows the recommended crystal circuit. It is recommended that preproduction printed-circuit
board (PCB) designs include the two optional resistors Rbias and Rd in case they are required for proper
oscillator operation when combined with production crystal circuit components. In most cases, Rbias is not
required and Rd is a 0 ohm resistor. These resistors may be removed from production PCB designs after
evaluating oscillator performance with production crystal circuit components installed on preproduction
PCBs.
Device
WKUP_LFOSC0_XO
WKUP_LFOSC0_XI
Rd
(Optional)
Crystal
(Optional) Rbias
Cf1
Cf2
PCB Ground
SPRSP08_PCB_CLK_OSC_3
Figure 5-20. WKUP_LFOSC0 Crystal Implementation
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NOTE
The load capacitors, Cf1 and Cf2 in Figure 5-21, should be chosen such that the below
equation is satisfied. CL in the equation is the load specified by the crystal manufacturer. All
discrete components used to implement the oscillator circuit should be placed as close as
possible to the associated oscillator WKUP_LFOSC0_XI, WKUP_LFOSC0_XO, and VSS
pins.
CL=
Cf1Cf2
(Cf1+Cf2)
SPRS932_CLOCK_03
Figure 5-21. Load Capacitance Equation
Table 5-25. WKUP_LFOSC0 Crystal Electrical Characteristics
NAME
fp
DESCRIPTION
MIN
Parallel resonance crystal frequency
TYP
MAX
UNIT
32768
Cf1
Cf1 load capacitance for crystal parallel resonance with Cf1 = Cf2
12
Cf2
Cf2 load capacitance for crystal parallel resonance with Cf1 = Cf2
12
Hz
24
pF
24
pF
Cshunt
Shunt capacitance
TBD
pF
ESR
Crystal effective series resistance
TBD
kΩ
When selecting a crystal, the system design must consider the temperature and aging characteristics of a
based on the worst case environment and expected life expectancy of the system.
Table 5-26 details the switching characteristics of the oscillator and the requirements of the input clock.
Table 5-26. WKUP_LFOSC0 Switching Characteristics – Crystal Mode
NAME
fxtal
tSX
DESCRIPTION
MIN
Oscillation frequency
TYP
MAX
32768
UNIT
Hz
(1)
Start-up time
s
Specifications
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ADVANCE INFORMATION
The crystal must be in the fundamental mode of operation and parallel resonant. Table 5-25 summarizes
the required electrical constraints
DRA80M
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(1) In order to meet the start-up time defined in this table, the crystal needs to be selected according to the following equation:
Tsu = K*Lm/ (Ro-ESR) + Δt
where Lm is crystal motional inductance, RO is the negative resistance of amplifier, ESR is the crystal Effective series resistance and K
is a constant which represents the initial conditions. Δt is the time amplifier takes to reach its bias point after power down is released.
VDD_WKUP (min.)
VDD_WKUP
Voltage
VSS
VDDA_WKUP (min.)
VSS
VDDA_WKUP
WKUP_LFOSC0_XO
tsX
ADVANCE INFORMATION
Time
Figure 5-22. WKUP_LFOSC0 Start-up Time
5.9.4.1.7 WKUP_LFOSC0 Not Used
For more Information see Section 4.5, Connections for Unused Pins.
5.9.4.2
Output Clocks
The device provides several system clock outputs. Summary of these output clocks are as follows:
• MCU_SYSCLKOUT0
– SYSCLK0 of WKUP_PLLCTRL0 is divided by 4 and then sent out of the device as a LVCMOS
clock signal (MCU_SYSCLKOUT0). This signal can be used to test if the main chip clock is
functioning or not.
• MCU_OBSCLK0
– On the clock output MCU_OBSCLK0, oscillators and PLLs clocks can be observed for tests and
debug.
• SYSCLKOUT0
– SYSCLK0 from the MAIN_PLL controller is divided by 4 and then sent out of the device as a
LVCMOS clock signal (SYSCLKOUT0). This signal can be used to test if the main chip clock is
functioning or not.
• OBSCLK0
– On the clock output OBSCLK0, oscillators and PLLs clocks can be observed for tests and debug.
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5.9.4.3
SPRSP31E – APRIL 2018 – REVISED JUNE 2019
PLLs
There are total nine Phase Locked Loops (PLLs) in the device:
• MCU_PLL0 (MCU PLL) with WKUP_PLL_CTRL0: The MCU PLL — which is used to drive the switch
fabrics, accelerators, and a majority of the peripheral clocks — requires a PLL controller to manage the
various clock divisions, gating, and synchronization in WKUP domain and MCU domain.
• MCU_PLL1 (CPSW PLL): The MCU_PLL1, which is used to drive the CPSW.
• PLL0 (MAIN PLL) with PLL_CTRL0: The Main PLL — which is used to drive the switch fabrics,
accelerators, and a majority of the peripheral clocks — requires a PLL controller to manage the various
clock divisions, gating, and synchronization in MAIN domain.
• PLL1 (PER0 PLL): The PER0 PLL, which is used to drive the Peripherals in MAIN Domain.
• PLL2 (PER1 PLL): The PER1 PLL, which is used to drive the PRU_ICSSG.
• PLL3 (DDR PLL): The DDR PLL is used to drive the DDR PHY for the DDRSS.
• PLL4 (DSS PLL): The DSS PLL, which is used to drive the Display Subsystem.
• PLL6 (ARM0 PLL): The ARM0 PLL, which is used to drive the ARM0.
• PLL7 (ARM1 PLL): The ARM1 PLL, which is used to drive the ARM1.
Most of the Device is driven by the output from the main PLL except the following items:
• Arm subsystem has its own dedicated PLL.
• MCU subsystem has its own dedicated PLL
• EMIF DDR subsystem has its own dedicated PLL to drive DDR PHY and DDRSS.
• PRU_ICSSG has clocks sourced from several PLLs:
– PER0 PLL to generate UART clock,
– PER1 PLL to generate Core clock,
– MAIN PLL to generate Industrial Ethernet Peripheral clock,
– CPSW PLL to generate Ethernet clocks.
• DSS has its own dedicated PLL, to generate Pixel Clock.
• PCIESS require separate reference clocks to drive SERDES PHYs.
NOTE
For more information, see:
• Device Configuration / Clocking / PLLs section in the device TRM
• Peripherals / Display Subsystem Overview section in the device TRM
• Programmable Real-Time Unit Subsystem and Industrial Communication Subsystem Gigabit (PRU_ICSSG) section in the device TRM
NOTE
The input reference clock (OSC1_XI/OSC1_XO) are specified and the lock time is ensured
by the PLL controller, as documented in the Device Configuration chapter in the device TRM.
Specifications
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Power is supplied to the PLL by internal regulators that derive power from the off-chip power-supply.
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Figure 5-23 shows the power supply connectivity implemented in the device.
VDDA_MCU
MCU_PLL0
(MCU PLL)
PLL3
(DDR PLL)
VDDA_PLL0_DDR
PLL4
(DSS PLL)
VDDA_PLL_DSS
MCU_PLL1
(CPSW PLL)
VDDA_PLL_CORE
PLL0
(MAIN PLL)
PLL2
(PER1 PLL)
VDDA_PLL_PER0
ADVANCE INFORMATION
PLL1
(PER0 PLL)
PLL6
(ARM0 PLL)
VDDA_PLL_MPU0
PLL7
(ARM1 PLL)
VDDA_PLL_MPU1
SPRSP08_PLL_PWR_01
Figure 5-23. PLL Power Supply Connectivity
5.9.4.4
Recommended Clock and Control Signal Transition Behavior
All clocks and strobe signals must transition between VIH and VIL (or between VIL and VIH) in a monotonic
manner. Monotonic transitions are more easily ensured with faster switching signals. Slower input
transitions are more susceptible to glitches due to noise, and special care must be taken for slow input
clocks.
5.9.4.5
Interface Clock Specifications
5.9.4.5.1 Interface Clock Terminology
The interface clock is used at the system level to sequence the data and to control transfers accordingly
with the interface protocol.
5.9.4.5.2 Interface Clock Frequency
The two interface clock characteristics are:
• The maximum clock frequency
• The maximum operating frequency
The interface clock frequency documented here is the maximum clock frequency, which corresponds to
the maximum frequency programmable on this output clock. This frequency defines the maximum limit
supported by the Device IC and does not take into account any system consideration (PCB, peripherals).
The system designer must take into account these system considerations and the Device IC timing
characteristics to properly define the maximum operating frequency that corresponds to the maximum
frequency supported to transfer the data on this interface.
156
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5.9.5
SPRSP31E – APRIL 2018 – REVISED JUNE 2019
Peripherals
5.9.5.1
VIN
Table 5-27, Figure 5-24, and Figure 5-25 present timing requirements for LVDSRX interface.
Table 5-27. Timing Requirements for LVDSRX (1)
NO.
PARAMETER
DESCRIPTION
MIN
5.76
MAX
UNIT
(1)
ns
V1
tc(PCLK)
Cycle time, VIN0_PCLK
V2
tw(PCLKH)
Pulse duration, VIN0_PCLK high
0.45 × P
(2)
ns
V3
tw(PCLKL)
Pulse duration, VIN0_PCLK low
0.45 × P
(2)
ns
V4
tsu(PCLK-CTL/DATA)
Input setup time, control (VIN0_HD, VIN0_VD) and data
(VIN0_DATA[15:0]) valid to VIN0_PCLK transition
2.38
ns
V5
th(CTL/DAT-PCLK)
Input hold time, control (VIN0_HD, VIN0_VD) valid to VIN0_PCLK
transition
-0.05
ns
(1) For maximum frequency of 165 MHz
V1
V2
ADVANCE INFORMATION
(2) P = VIN0_PCLK period
V3
VIN0_PCLK
CAL_CCDC_TIMINGS_01
Figure 5-24. LVDSRX Input Clock Signal
VIN0_PCLK
(Positive-edge clocking)
VIN0_PCLK
(Negative-edge clocking)
V4
V5
VIN_DATA[15:0]
CAL_CCDC_TIMINGS_02
Figure 5-25. LVDSRX Input Timings
For more information, see section Camera Adapter Layer (CAL) Subsystem in the device TRM.
5.9.5.2
CPSW2G
For more details about features and additional description information on the device Gigabit Ethernet
MAC, see the corresponding sections within Section 4.3, Signal Descriptions and Section 6, Detailed
Description.
5.9.5.2.1 CPSW2G MDIO Interface Timings
Table 5-28, Table 5-29, and Figure 5-26 present timing requirements for MDIO.
Table 5-28. Timing Requirements for MDIO Input
NO.
PARAMETER
MDIO1 tsu(MDIO_MDC)
Setup time, MDIO_DATA valid before MDIO_CLK high
MDIO2 th(MDIO_MDC)
Hold time, MDIO_DATA valid after MDIO_CLK high
MIN
MAX
UNIT
90
ns
0
ns
Specifications
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Table 5-29. Switching Characteristics Over Recommended Operating Conditions for MDIO Output
NO.
PARAMETER
MIN
MAX
UNIT
MDIO3 tc(MDC)
Cycle time, MDIO_CLK
400
ns
MDIO4 tw(MDCH)
Pulse Duration, MDIO_CLK high
160
ns
MDIO5 tw(MDCL)
Pulse Duration, MDIO_CLK low
160
ns
MDIO6 tt(MDC)
Transition time, MDIO_CLK
MDIO7 td(MDC_MDIO)
Delay time, MDIO_CLK low to MDIO_DATA valid
-150
5
ns
150
ns
MDIO3
MDIO4
MDIO5
MDIO_CLK
MDIO6
MDIO6
MDIO1
MDIO2
MDIO_DATA
(input)
ADVANCE INFORMATION
MDIO7
MDIO_DATA
(output)
SPRSP08_CPSW2G_MDIO
Figure 5-26. CPSW2G MDIO Diagrams Receive and Transmit
5.9.5.2.2 CPSW2G RMII Timings
Table 5-30, Table 5-31, Figure 5-27, and Figure 5-28 present timing requirements for CPSW2G RMII
receive.
Table 5-30. Timing Requirements for RMII[x]_REFCLK - RMII Mode
NO.
PARAMETER
DESCRIPTION
MIN
TYP
MAX
UNIT
RMII1
tc(REF_CLK)
Cycle time, REF_CLK
19.999
20.001
ns
RMII2
tw(REF_CLKH)
Pulse Duration, REF_CLK High
7
13
ns
RMII3
tw(REF_CLKL)
Pulse Duration, REF_CLK Low
7
13
ns
RMII1
RMII2
RMII[x]_REFCLK
(input)
RMII3
Figure 5-27. RMII[x]_REFCLK Timing - RMII Mode
Table 5-31. Timing Requirements for RMII[x]_RXD[1:0], RMII[x]_CRS_DV, and RMII[x]_RXER - RMII Mode
NO.
PARAMETER
DESCRIPTION
RMII4
tsu(RXD-REF_CLK)
Setup time, RXD[1:0] valid before REF_CLK
4
ns
tsu(CRS_DV-REF_CLK)
Setup time, CRS_DV valid before REF_CLK
4
ns
tsu(RX_ER-REF_CLK)
Setup time, RX_ER valid before REF_CLK
4
ns
158
MIN
Specifications
TYP
MAX
UNIT
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Table 5-31. Timing Requirements for RMII[x]_RXD[1:0], RMII[x]_CRS_DV, and RMII[x]_RXER - RMII
Mode (continued)
NO.
PARAMETER
DESCRIPTION
RMII5
th(REF_CLK-RXD)
Hold time RXD[1:0] valid after REF_CLK
MIN
2
TYP
MAX
UNIT
ns
th(REF_CLK-CRS_DV)
Hold time, CRS_DV valid after REF_CLK
2
ns
th(REF_CLK-RX_ER)
Hold time, RX_ER valid after REF_CLK
2
ns
RMII4
RMII5
RMII[x]_REFCLK (input)
RMII[x]_RXD[1:0],
RMII[x]_CRS_DV, RMII[x]_RXER (inputs)
Figure 5-28. RMII[x]_RXD[1:0], RMII[x]_CRS_DV, RMII[x]_RXER Timing - RMII Mode
Table 5-32, and Figure 5-29 present switching characteristics for CPSW2G RMII Transmit.
Table 5-32. Switching Characteristics for RMII[x]_TXD[1:0], and RMII[x]_TXEN - RMII Mode
NO.
PARAMETER
DESCRIPTION
RMII6
td(REF_CLK-TXD)
Delay time, REF_CLK High to TXD[1:0] valid
2
13
ns
td(REF_CLK-TXEN)
Delay time, REF_CLK to TXEN valid
2
13
ns
tr(TXD)
Rise Time, TXD Outputs
1
5
ns
tr(TX_EN)
Rise Time, TX_EN Output
1
5
ns
tf(TXD)
Fall Time, TXD Outputs
1
5
ns
tf(TX_EN)
Fall Time, TX_EN Output
1
5
ns
RMII7
RMII8
MIN
TYP
MAX
UNIT
RMII6
RMII[x]_REFCLK (input)
RMII[x]_TXD[1:0],
RMII[x]_TXEN (outputs)
RMII8
RMII7
SPRSP08_CPSW2G_RMIITX
Figure 5-29. RMII[x]_TXD[1:0], RMII[x]_TXEN Timing - RMII Mode
5.9.5.2.3 CPSW2G RGMII Timings
Table 5-33, Table 5-34, and Figure 5-30 present timing requirements for receive RGMII operation.
Table 5-33. Timing Requirements for RGMII[x]_RCLK - RGMII Mode
NO.
PARAMETER
RGMII1 tc(RXC)
DESCRIPTION
MODE
MIN
MAX
UNIT
Cycle time, RXC
10Mbps
360
TYP
440
ns
100Mbps
36
44
ns
1000Mbps
7.2
8.8
ns
Specifications
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Table 5-33. Timing Requirements for RGMII[x]_RCLK - RGMII Mode (continued)
NO.
PARAMETER
RGMII2 tw(RXCH)
RGMII3 tw(RXCL)
DESCRIPTION
MODE
MIN
Pulse duration, RXC high
10Mbps
160
Pulse duration, RXC low
RGMII4 tt(RXC)
Transition time, RXC
TYP
MAX
UNIT
240
ns
100Mbps
16
24
ns
1000Mbps
3.6
4.4
ns
10Mbps
160
240
ns
100Mbps
16
24
ns
1000Mbps
3.6
4.4
ns
10Mbps
0.75
ns
100Mbps
0.75
ns
1000Mbps
0.75
ns
Table 5-34. Timing Requirements for RGMII[x]_RD[3:0], and RGMII[x]_RCTL - RGMII Mode
NO.
PARAMETER
RGMII5 tsu(RD-RXC)
ADVANCE INFORMATION
tsu(RX_CTL-RXC)
DESCRIPTION
MODE
MIN
Setup time, RD[3:0] valid before RXC high/low
10Mbps
1
ns
Setup time, RX_CTL valid before RXC high/low
RGMII6 th(RXC-RD)
Hold time, RD[3:0] valid after RXC high/low
th(RXC-RX_CTL)
Hold time, RX_CTL valid after RXC high/low
RGMII7 tt(RD)
Transition time, RD
tt(RX_CTL)
Transition time, RX_CTL
TYP
MAX
UNIT
100Mbps
1
ns
1000Mbps
1
ns
10Mbps
1
ns
100Mbps
1
ns
1000Mbps
1
ns
10Mbps
1
ns
100Mbps
1
ns
1000Mbps
1
ns
10Mbps
1
ns
100Mbps
1
ns
1000Mbps
1
ns
10Mbps
0.75
ns
100Mbps
0.75
ns
1000Mbps
0.75
ns
10Mbps
0.75
ns
100Mbps
0.75
ns
1000Mbps
0.75
ns
RGMII1
RGMII2
RGMII[x]_RXC
RGMII4
RGMII4
RGMII3
(A)
RGMII5
1st Half-byte
RGMII6
2nd Half-byte
(B)
RGMII[x]_RXD[3:0]
RGMII[x]_RCTL
(B)
RGRXD[3:0]
RGRXD[7:4]
RXDV
RXERR
SPRSP08_CPSW2G_RGMIIRX
A.
B.
RGMII_RXC must be externally delayed relative to the data and control pins.
Data and control information is received using both edges of the clocks. RGMII_RXD[3:0] carries data bits 3-0 on the
rising edge of RGMII_RXC and data bits 7-4 on the falling edge of RGMII_RXC. Similarly, RGMII_RXCTL carries
RXDV on rising edge of RGMII_RXC and RXERR on falling edge of RGMII_RXC.
Figure 5-30. CPSW2G Receive Interface Timing, RGMII operation
160
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Table 5-35, Table 5-36, and Figure 5-31 present switching characteristics for transmit - RGMII for 10
Mbps, 100 Mbps, and 1000 Mbps.
NO.
PARAMETER
RGMII1 tc(TXC)
RGMII2 tw(TXCH)
DESCRIPTION
MODE
MIN
Cycle time, TXC
10Mbps
360
Pulse duration, TXC high
RGMII3 tw(TXCL)
Pulse duration, TXC low
RGMII4 tt(TXC)
Transition time, TXC
TYP
MAX
UNIT
440
ns
100Mbps
36
44
ns
1000Mbps
7.2
8.8
ns
10Mbps
160
240
ns
100Mbps
16
24
ns
1000Mbps
3.6
4.4
ns
10Mbps
160
240
ns
100Mbps
16
24
ns
1000Mbps
3.6
4.4
ns
10Mbps
0.75
ns
100Mbps
0.75
ns
1000Mbps
0.75
ns
Table 5-36. Switching Characteristics for RGMII[x]_TD[3:0], and RGMII[x]_TCTL - RGMII Mode
NO.
PARAMETER
RGMII5 tsk(TD-TXC)
DESCRIPTION
TD to TXC output skew
tsk(TX_CTL-TXC)
TX_CTL to TXC output skew
RGMII6 tt(TD)
Transition time, TD
tt(TX_CTL)
Transition time, TX_CTL
MODE
MIN
TYP
MAX
UNIT
10Mbps
TBD
TBD
ns
100Mbps
TBD
TBD
ns
1000Mbps
TBD
TBD
ns
10Mbps
TBD
TBD
ns
100Mbps
TBD
TBD
ns
1000Mbps
TBD
TBD
ns
10Mbps
0.75
ns
100Mbps
0.75
ns
1000Mbps
0.75
ns
10Mbps
0.75
ns
100Mbps
0.75
ns
1000Mbps
0.75
ns
RGMII1
RGMII4
RGMII2
RGMII3
RGMII4
(A)
RGMII[x]_TXC
RGMII5
(B)
RGMII[x]_TXD[3:0]
1st Half-byte
2nd Half-byte
RGMII5
RGMII[x]_TCTL
(B)
TXEN
TXERR
SPRSP08_CPSW2G_RGMIITX
A.
B.
TXC is delayed internally before being driven to the RGMII[x]_TXC pin. This internal delay is always enabled.
Data and control information is received using both edges of the clocks. RGMII_TXD[3:0] carries data bits 3-0 on the
rising edge of RGMII_TXC and data bits 7-4 on the falling edge of RGMII_TXC. Similarly, RGMII_TXCTL carries
TXDV on rising edge of RGMII_TXC and RTXERR on falling edge of RGMII_TXC.
Figure 5-31. CPSW2G Transmit Interface Timing RGMII Mode
Specifications
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Table 5-35. Switching Characteristics for RGMII[x]_TCLK - RGMII Mode
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For more information, see section Gigabit Ethernet MAC (MCU_CPSW0) in the device TRM.
5.9.5.3
CSI2
NOTE
For more information, see sectionCamera Adapter Layer (CAL) Subsystem in the device
TRM.
The camera adaptation layer (CAL) is a very flexible subsystem that enables connection to multiple
cameras supporting MIPI CSI-2 over D-PHY serial interface, a LVDS serial interface, and a traditional
parallel interface.
The device includes one instantiation of CAL Subsystem named CALSS0, with a single companion
CAMERARX0 instance.
• CSI2 Port is compliant with MIPI CSI-2 protocol with four data lanes.
5.9.5.4
DDRSS
ADVANCE INFORMATION
For more details about features and additional description information on the device DDR3L, DDR4, and
LPDDR4 Memory Interfaces, see the corresponding sections within Section 4.3, Signal Descriptions and
Section 6, Detailed Description.
The device has dedicated interfaces to DDR3L, DDR4, and LPDDR4 SDRAM. It supports JEDEC
JESD79-3-1, JESD79-4B, and JESD209-4B standards compliant DDR3L, DDR4, and LPDDR4 SDRAM
devices with the following features:
• 16-bit or 32-bit data path to external SDRAM memory
• Memory device capacity: Up to 32 GB address space available over one chip select
Table 5-37 and Figure 5-32 present switching characteristics for DDRSS.
Table 5-37. Switching Characteristics for DDRSS
NO.
1
PARAMETER
tc(DDR_CKP/D
DDR TYPE
Cycle time, DDR_CKP and DDR_CKN
MODE
MIN
MAX UNIT
DDR3L
1.25
3.3
DDR4
1.25
1.6
1.5
3.003
DR_CKN)
DDR PHY PLL:
DDRPHY_PLLCR0[31] = 0
LPDDR4
ns
1
DDR_CK[1:0]P
DDR_CK[1:0]N
Figure 5-32. DDRSS Memory Interface Clock Timing
For more information, see section DDR Subsystem (DDRSS) in the device TRM.
162
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5.9.5.5
SPRSP31E – APRIL 2018 – REVISED JUNE 2019
DSS
For more details about features and additional description information on the device Display Subsystem –
Video Output Ports, see the corresponding sections within Section 4.3, Signal Descriptions and Section 6,
Detailed Description.
Table 5-38, Table 5-39, Figure 5-33, and Figure 5-34 assume testing over the recommended operating
conditions and electrical characteristic conditions.
Table 5-38. DPI Video Output Switching Characteristics
NO.
PARAMETER
DESCRIPTION
MIN
MAX
6.06
UNIT
D1
tc(VOUT1_PCLK)
Cycle time, VOUT1_PCLK
ns
D2
tw(VOUT1_PCLKL)
Pulse duration, VOUT1_PCLK low
0.45×P
D3
tw(VOUT1_PCLKH)
Pulse duration, VOUT1_PCLK high
0.45×P(1)
D4
td(VOUT1_PCLK-
Delay time, VOUT1_PCLK to VOUT1_DATA[23:0]
-0.68
1.78
ns
Delay time, VOUT1_PCLK to VOUT1_VSYNC, VOUT1_HSYNC,
VOUT1_DE
-0.68
1.78
ns
ns
(1)
ns
VOUT_DATA)
D5
td(VOUT1_PCLKVOUT_CTRL)
ADVANCE INFORMATION
(1) P = output VOUT1_PCLK period in ns.
D2
D1
D3
Falling-edge Clock Reference
VOUT1_PCLK
Rising-edge Clock Reference
VOUT1_PCLK
D5
VOUT1_VSYNC
D5
VOUT1_HSYNC
D4
VOUT1_DATA[23:0]
data_1 data_2
data_n
D5
VOUT1_DE
DPI_01
(1) The configuration of assertion of the data can be programmed on the falling or rising edge of the pixel clock.
(2) The polarity and the pulse width of VOUT1_HSYNC and VOUT1_VSYNC are programmable, refer to section Display Subsystem (DSS)
in the device TRM.
(3) The VOUT1_PCLK frequency can be configured, refer to section Display Subsystem (DSS) in the device TRM.
Figure 5-33. DPI Video Output
(1)(2)(3)
Specifications
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Table 5-39. DPI External Pixel Clock Input Timing Requirements
NO.
PARAMETER
D6
tc(VOUT1_EXTPCLKIN)
Cycle time, VOUT1_EXTPCLKIN
DESCRIPTION
D7
tw(VOUT1_EXTPCLKIN)
D8
tw(VOUT1_EXTPCLKIN)
MIN
MAX
UNIT
6.06
ns
Pulse duration, VOUT1_EXTPCLKIN low
0.45×P(1)
ns
Pulse duration, VOUT1_EXTPCLKIN high
0.45×P(1)
ns
(1) P = output VOUT1_PCLK period in ns.
D7
D6
D8
Falling-edge Clock Reference
VOUT1_EXTPCLKIN
Rising-edge Clock Reference
VOUT1_EXTPCLKIN
DPI_02
Figure 5-34. DPI External Pixel Clock Input
For more information, see section Display Subsystem (DSS) in the device TRM.
ADVANCE INFORMATION
5.9.5.6
eCAP
The supported features by the device eCAP are:
• 32-bit time base counter
• 4-event time-stamp registers (each 32 bits)
• Independent edge polarity selection for up to four sequenced time-stamp capture events
• Interrupt capabilities on any of the four capture events
• Input capture signal pre-scaling (from 1 to 16)
• Support of different capture modes (single shot capture, continuous mode capture, absolute timestamp
capture or difference mode time-stamp capture)
Table 5-40 and Table 5-41 present timing and switching characteristics for eCAP (see Figure 5-35 and
Figure 5-36).
Table 5-40. Timing Requirements for eCAP
NO.
PARAMETER
CAP1
tw(CAP)
DESCRIPTION
MIN
Pulse duration, capture input (asynchronous)
3 + 2P
MAX
(1)
UNIT
ns
(1) P = sysclk
CAP1
CAP
EPERIPHERALS_TIMNG_01
Figure 5-35. eCAP Input Timings
Table 5-41. Switching Characteristics for eCAP
NO.
CAP2
164
PARAMETER
DESCRIPTION
tw(APWM)
Pulse duration, APWMx output high/low
MIN
Specifications
-3 + 2P(1)
MAX
UNIT
ns
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(1) P = sysclk
CAP2
APWM
EPERIPHERALS_TIMNG_02
Figure 5-36. eCAP Output Timings
For more information, see section Enhanced Capture (ECAP) Module in the device TRM.
eHRPWM
The supported features by the device eHRPWM are:
• Dedicated 16-bit time-base counter with period and frequency control
• Two independent PWM outputs which can be used in different configurations (with single-edge
operation, with dual-edge symmetric operation or one independent PWM output with dual-edge
asymmetric operation)
• Asynchronous override control of PWM signals during fault conditions
• Programmable phase-control support for lag or lead operation relative to other EPWM modules
• Dead-band generation with independent rising and falling edge delay control
• Programmable trip zone allocation of both latched and un-latched fault conditions
• Events enabling to trigger both CPU interrupts and start of ADC conversions
Table 5-42 and Table 5-43 present timing and switching characteristics for eHRPWM (see Figure 5-37,
Figure 5-38, Figure 5-39, and Figure 5-40).
Table 5-42. Timing Requirements for eHRPWM
PARAMETER
DESCRIPTION
PWM1
NO.
tw(PWM)
Pulse duration, PWM output high/low
-3 + 1P(1)
MIN
MAX
ns
PWM2
tw(SYNCOUT)
Pulse duration, Sync output
-3 + 1P(1)
ns
PWM3
td(TZ-PWM)
Delay time, trip input active to PWM forced high/low
11
ns
PWM4
td(TZ-PWMZ)
Delay time, trip input active to PWM Hi-Z
11
ns
PWM5
tw(SOC)
Pulse duration, SOC output (asynchronous)
-3 + 1P(1)
UNIT
ns
(1) P = sysclk
PWM1
EPWM_A/B_out
PWM1
PWM2
EPWM_SYNCO
PWM5
EPWM_SOCA/B
EPERIPHERALS_TIMNG_04
Figure 5-37. ePWM_A/B_out, ePWM_SYNCO, and ePWM_SOCA/B Input Timings
Specifications
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PWM3
EPWM_A/B
EPQM_TZn_IN
EPERIPHERALS_TIMING_05
Figure 5-38. ePWM_A/B and ePWM_TZn_IN Forced High/Low Input Timings
PWM4
EPWM_A/B
EPQM_TZn_IN
EPERIPHERALS_TIMING_06
Figure 5-39. ePWM_A/B and ePWM_TZn_IN Hi-Z Input Timings
ADVANCE INFORMATION
Table 5-43. Switching Characteristics for eHRPWM
PARAMETER
DESCRIPTION
PWM6
NO.
tw(SYNCIN)
Pulse duration, Sync input (asynchronous)
3 + 2P(1)
MIN
MAX
UNIT
ns
PWM7
tw(TZ)
Pulse duration, TZx input low (asynchronous)
3 + 3P(1)
ns
(1) P = sysclk
PWM6
EPWM_SYNCI
PWM7
EPWM_TZn_IN
EPERIPHERALS_TIMNG_07
Figure 5-40. ePWM_SYNCI and ePWM_TZn_IN Output Timings
For more information, see section Enhanced Pulse Width Modulation (EPWM) Module in the device TRM.
5.9.5.8
eQEP
The supported features by the device eQEP are:
• Input Synchronization
• Three Stage/Six Stage Digital Noise Filter
• Quadrature Decoder Unit
• Position Counter and Control unit for position measurement
• Quadrature Edge Capture unit for low speed measurement
• Unit Time base for speed/frequency measurement
• Watchdog Timer for detecting stalls
Table 5-44 and Table 5-45 present Timing Requirements and Switching Characteristics for eQEP (see
Figure 5-41).
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Table 5-44. Timing Requirements for eQEP
NO.
QEP1
PARAMETER
DESCRIPTION
tw(QEP)
Pulse duration, QEP input
MIN
MAX
UNIT
3 + 2P(1)
ns
(1)
ns
QEP2
tw(QEPIH)
Pulse duration, QEP Index input high
3 + 2P
QEP3
tw(QEPIL)
Pulse duration, QEP Index input low
3 + 2P(1)
ns
QEP4
tw(QEPSH)
Pulse duration, QEP Strobe high
3 + 2P(1)
ns
QEP5
tw(QEPSL)
Pulse duration, QEP Strobe low
3 + 2P(1)
ns
(1) P = sysclk
QEP1
QEP_A/B
QEP2
QEP3
QEP4
QEP_S
QEP5
EPERIPHERALS_TIMNG_03
Figure 5-41. eQEP Input Timings
Table 5-45. Switching Characteristics for eQEP
NO.
QEP6
PARAMETER
DESCRIPTION
td(QEP-CNTR)
Delay time, external clock to counter increment
MIN
MAX
24
UNIT
ns
For more information, see section Enhanced Quadrature Encoder Pulse (EQEP) Module in the device
TRM.
5.9.5.9
GPIO
The device has three instances of GPIO144 modules. The GPIO pins are grouped into banks (16 pins per
bank), which means that each GPIO module provides up to 144 dedicated general-purpose pins with input
and output capabilities; thus, the general-purpose interface supports up to 432 (3 instances × (9 banks ×
16 pins)) pins. Since WKUP_GPIO0_[56:143], GPIO0_[96:143], and GPIO1_[90:143] are reserved in this
Device, general purpose interface supports up to 242 pins.
For more details about features and additional description information on the device General-Purpose
Interface, see the corresponding sections within Section 4.3, Signal Descriptions and Section 6, Detailed
Description.
NOTE
The general-purpose input/output i (i = 0 to 1) is also referred to as GPIOi.
Table 5-46 and Table 5-47 present timings and switching characteristics of the GPIO Interface.
Specifications
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Table 5-46. GPIO Timing Requirements
NO.
PARAMETER
DESCRIPTION
GP2
tw(GPIO_IN)
Minimum Input Pulse Width
MIN
MAX
UNIT
3.6 + 2P(1)
ns
(1) P = functional clock period in ns.
Table 5-47. GPIO Switching Characteristics
NO.
PARAMETER
DESCRIPTION
GP1
tw(GPIO_OUT)
Minimum Output Pulse Width
MIN
MAX
UNIT
-4.6 +
0.975P(1)
ns
(1) P = functional clock period in ns.
For more information, see section General-Purpose Interface (GPIO) in the device TRM.
5.9.5.10 GPMC
For more details about features and additional description information on the device General-Purpose
Memory Controller, see the corresponding sections within Section 4.3, Signal Descriptions and Section 6,
Detailed Description.
ADVANCE INFORMATION
5.9.5.10.1 GPMC and NOR Flash—Synchronous Mode
Table 5-48 and Table 5-49 assume testing over the recommended operating conditions and electrical
characteristic conditions below (see Figure 5-42 through Figure 5-46).
Table 5-48. GPMC and NOR Flash Timing Requirements—Synchronous Mode
NO.
PARAMETER
F12
tsu(dV-clkH)
F13
F21
F22
th(clkH-dV)
tsu(waitV-clkH)
th(clkH-waitV)
DESCRIPTION
Setup time, input data GPMC_AD[15:0] valid
before output clock GPMC_CLK high
Hold time, input data GPMC_AD[15:0] valid after
output clock GPMC_CLK high
Setup time, input wait GPMC_WAIT[x] valid before
output clock GPMC_CLK high (1)
Hold time, input wait GPMC_WAIT[x] valid after
output clock GPMC_CLK high (1)
MODE(3)
MIN
MAX
UNIT
div_by_1_mode;
GPMC_FCLK_MUX_100;
TIMEPARAGRANULARITY_X1
0.59
ns
not_div_by_1_mode;
GPMC_FCLK_MUX_100;
TIMEPARAGRANULARITY_X1
0.34
ns
div_by_1_mode;
GPMC_FCLK_MUX_100;
TIMEPARAGRANULARITY_X1
1.78
ns
not_div_by_1_mode;
GPMC_FCLK_MUX_100;
TIMEPARAGRANULARITY_X1
1.78
ns
div_by_1_mode;
GPMC_FCLK_MUX_100;
TIMEPARAGRANULARITY_X1
0.59
ns
not_div_by_1_mode;
GPMC_FCLK_MUX_100;
TIMEPARAGRANULARITY_X1
0.34
ns
div_by_1_mode;
GPMC_FCLK_MUX_100;
TIMEPARAGRANULARITY_X1
1.78
ns
not_div_by_1_mode;
GPMC_FCLK_MUX_100;
TIMEPARAGRANULARITY_X1
1.78
ns
(1) In GPMC_WAIT[x], x is equal to 0 or 1.
(2) Wait monitoring support is limited to a WaitMonitoringTime value > 0. For a full description of wait monitoring feature, see section
General-Purpose Memory Controller (GPMC) in the device TRM.
(3) For div_by_1_mode:
– GPMC_CONFIG1_i Register: GPMCFCLKDIVIDER = 0h:
– GPMC_CLK frequency = GPMC_FCLK frequency
For not_div_by_1_mode:
– GPMC_CONFIG1_i Register: GPMCFCLKDIVIDER = 1h to 3h:
– GPMC_CLK frequency = GPMC_FCLK frequency / (2 to 4)
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For GPMC_FCLK_MUX_100:
– gpmc_fclk_sel[1:0] = 01 = PER1_PLL_CLKOUT / 3 = 300 / 3 = 100MHz
For TIMEPARAGRANULARITY_X1:
– GPMC_CONFIG1_i Register: TIMEPARAGRANULARITY = 0h = x1 latencies (affecting RD/WRCYCLETIME,
RD/WRACCESSTIME, PAGEBURSTACCESSTIME, CSONTIME, CSRD/WROFFTIME, ADVONTIME, ADVRD/WROFFTIME,
OEONTIME, OEOFFTIME, WEONTIME, WEOFFTIME, CYCLE2CYCLEDELAY, BUSTURNAROUND, TIMEOUTSTARTVALUE,
WRDATAONADMUXBUS)
Table 5-49. GPMC and NOR Flash Switching Characteristics—Synchronous Mode(2)
PARAMETER
DESCRIPTION
MODE(20)
MIN
MAX
UNIT
F0
1 / tc(clk)
Period, output clock GPMC_CLK (18)
div_by_1_mode;
GPMC_FCLK_MUX_100;
TIMEPARAGRANULARITY_X1
10
ns
F1
tw(clkH)
Typical pulse duration, output clock GPMC_CLK
high
div_by_1_mode;
GPMC_FCLK_MUX_100;
TIMEPARAGRANULARITY_X1
-0.3+0.
475*P
ns
div_by_1_mode;
GPMC_FCLK_MUX_100;
TIMEPARAGRANULARITY_X1
-0.3+0.
475*P
-500
F1
tw(clkL)
Typical pulse duration, output clock GPMC_CLK
low
tdc(clk)
Duty cycle error, output clock GPMC_CLK
div_by_1_mode;
GPMC_FCLK_MUX_100;
TIMEPARAGRANULARITY_X1
tJ(clk)
Jitter standard deviation, output clock GPMC_CLK
(19)
F2
F3
F4
(15)
ps
div_by_1_mode;
GPMC_FCLK_MUX_100;
TIMEPARAGRANULARITY_X1
33.33
ps
tR(clk)
Rise time, output clock GPMC_CLK
div_by_1_mode;
GPMC_FCLK_MUX_100;
TIMEPARAGRANULARITY_X1
2
ns
tF(clk)
Fall time, output clock GPMC_CLK
div_by_1_mode;
GPMC_FCLK_MUX_100;
TIMEPARAGRANULARITY_X1
2
ns
tR(do)
Rise time, output data GPMC_AD[15:0]
div_by_1_mode;
GPMC_FCLK_MUX_100;
TIMEPARAGRANULARITY_X1
2
ns
tF(do)
Fall time, output data GPMC_AD[15:0]
div_by_1_mode;
GPMC_FCLK_MUX_100;
TIMEPARAGRANULARITY_X1
2
ns
td(clkH-csnV)
Delay time, output clock GPMC_CLK rising edge
to output chip select GPMC_CSn[x] transition (14)
div_by_1_mode;
GPMC_FCLK_MUX_100;
TIMEPARAGRANULARITY_X1;
no extra_delay
-2.2+F 4.5+F
(6)
ns
Delay time, output clock GPMC_CLK rising edge
to output chip select GPMC_CSn[x] invalid (14)
div_by_1_mode;
GPMC_FCLK_MUX_100;
TIMEPARAGRANULARITY_X1;
no extra_delay
-2.2+E 4.5+E (5)
ns
Delay time, output address GPMC_A[27:1] valid to
output clock GPMC_CLK first edge
div_by_1_mode;
GPMC_FCLK_MUX_100;
TIMEPARAGRANULARITY_X1
-2.3+B 4.5+B (2)
td(clkH-csnIV)
td(aV-clk)
td(clkH-aIV)
Delay time, output clock GPMC_CLK rising edge
to output address GPMC_A[27:1] invalid
div_by_1_mode;
GPMC_FCLK_MUX_100;
TIMEPARAGRANULARITY_X1
F6
td(be[x]nV-clk)
Delay time, output lower byte enable and
command latch enable GPMC_BE0n_CLE, output
upper byte enable GPMC_BE1n valid to output
clock GPMC_CLK first edge
F7
ns
500
F5
F7
(15)
td(clkH-be[x]nIV)
td(clkL-be[x]nIV)
(6)
(5)
ns
(2)
-2.3
4.5
ns
div_by_1_mode;
GPMC_FCLK_MUX_100;
TIMEPARAGRANULARITY_X1
-2.3+B 1.9+B (2)
ns
Delay time, output clock GPMC_CLK rising edge
to output lower byte enable and command latch
enable GPMC_BE0n_CLE, output upper byte
enable GPMC_BE1n invalid (11)
div_by_1_mode;
GPMC_FCLK_MUX_100;
TIMEPARAGRANULARITY_X1
-2.3+D 1.9+D (4)
Delay time, GPMC_CLK falling edge to
GPMC_BE0n_CLE, GPMC_BE1n invalid (12)
div_by_1_mode;
GPMC_FCLK_MUX_100;
TIMEPARAGRANULARITY_X1
-2.3+D 1.9+D (4)
(2)
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(4)
Specifications
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ns
(4)
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Table 5-49. GPMC and NOR Flash Switching Characteristics—Synchronous Mode(2) (continued)
NO.
F7
F8
F9
PARAMETER
td(clkL-be[x]nIV).
td(clkH-advn)
td(clkH-advnIV)
DESCRIPTION
MODE(20)
MIN
MAX
Delay time, GPMC_CLK falling edge to
GPMC_BE0n_CLE, GPMC_BE1n invalid (13)
div_by_1_mode;
GPMC_FCLK_MUX_100;
TIMEPARAGRANULARITY_X1
-2.3+D 1.9+D (4)
Delay time, output clock GPMC_CLK rising edge
to output address valid and address latch enable
GPMC_ADVn_ALE transition
div_by_1_mode;
GPMC_FCLK_MUX_100;
TIMEPARAGRANULARITY_X1;
no extra_delay
-2.3+G
4.5+G
(7)
(7)
Delay time, output clock GPMC_CLK rising edge
to output address valid and address latch enable
GPMC_ADVn_ALE invalid
div_by_1_mode;
GPMC_FCLK_MUX_100;
TIMEPARAGRANULARITY_X1;
no extra_delay
-2.3+D 4.5+D (4)
UNIT
ns
(4)
ns
ns
(4)
F10
td(clkH-oen)
Delay time, output clock GPMC_CLK rising edge
to output enable GPMC_OEn_REn transition
div_by_1_mode;
GPMC_FCLK_MUX_100;
TIMEPARAGRANULARITY_X1;
no extra_delay
-2.3H (8) 3.5+H (8)
ns
F11
td(clkH-oenIV)
Delay time, output clock GPMC_CLK rising edge
to output enable GPMC_OEn_REn invalid
div_by_1_mode;
GPMC_FCLK_MUX_100;
TIMEPARAGRANULARITY_X1;
no extra_delay
-2.3+E 3.5+E (8)
ns
ADVANCE INFORMATION
F14
td(clkH-wen)
Delay time, output clock GPMC_CLK rising edge
to output write enable GPMC_WEn transition
div_by_1_mode;
GPMC_FCLK_MUX_100;
TIMEPARAGRANULARITY_X1;
no extra_delay
F15
td(clkH-do)
Delay time, output clock GPMC_CLK rising edge
to output data GPMC_AD[15:0] transition (11)
F15
F15
F17
F17
F17
F18
F19
F20
td(clkL-do)
td(clkL-do).
td(clkH-be[x]n)
td(clkL-be[x]n)
td(clkL-be[x]n).
tw(csnV)
tw(be[x]nV)
tw(advnV)
(8)
(9)
4.5+I (9)
ns
div_by_1_mode;
GPMC_FCLK_MUX_100;
TIMEPARAGRANULARITY_X1
-2.3+J
2.7+J
ns
(10)
(10)
Delay time, GPMC_CLK falling edge to
GPMC_AD[15:0] data bus transition (12)
div_by_1_mode;
GPMC_FCLK_MUX_100;
TIMEPARAGRANULARITY_X1
-2.3+J
2.7+J
(10)
(10)
Delay time, GPMC_CLK falling edge to
GPMC_AD[15:0] data bus transition (13)
div_by_1_mode;
GPMC_FCLK_MUX_100;
TIMEPARAGRANULARITY_X1
-2.3+J
2.7+J
(10)
(10)
Delay time, output clock GPMC_CLK rising edge
to output lower byte enable and command latch
enable GPMC_BE0n_CLE transition (11)
div_by_1_mode;
GPMC_FCLK_MUX_100;
TIMEPARAGRANULARITY_X1
-2.3+J
1.9+J
(10)
(10)
Delay time, GPMC_CLK falling edge to
GPMC_BE0n_CLE, GPMC_BE1n transition
div_by_1_mode;
GPMC_FCLK_MUX_100;
TIMEPARAGRANULARITY_X1
-2.3+J
1.9+J
(12)
(10)
(10)
div_by_1_mode;
GPMC_FCLK_MUX_100;
TIMEPARAGRANULARITY_X1
-2.3+J
1.9+J
(13)
(10)
(10)
Pulse duration, output chip select GPMC_CSn[x]
low (14)
Read
A
(1)
ns
Write
A
(1)
ns
Pulse duration, output lower byte enable and
command latch enable GPMC_BE0n_CLE, output
upper byte enable GPMC_BE1n low
Read
C
(3)
ns
Write
C
(3)
ns
Pulse duration, output address valid and address
latch enable GPMC_ADVn_ALE low
Read
K
(16)
ns
Write
K
(16)
ns
Delay time, GPMC_CLK falling edge to
GPMC_BE0n_CLE, GPMC_BE1n transition
-2.3+I
ns
ns
ns
ns
ns
(1) For single read: A = (CSRdOffTime - CSOnTime) × (TimeParaGranularity + 1) × GPMC_FCLK(17)
For burst read: A = (CSRdOffTime - CSOnTime + (n - 1) × PageBurstAccessTime) × (TimeParaGranularity + 1) × GPMC_FCLK(17)
For burst write: A = (CSWrOffTime - CSOnTime + (n - 1) × PageBurstAccessTime) × (TimeParaGranularity + 1) × GPMC_FCLK(17)
With n being the page burst access number.
(2) B = ClkActivationTime × GPMC_FCLK(17)
(3) For single read: C = RdCycleTime × (TimeParaGranularity + 1) × GPMC_FCLK(17)
For burst read: C = (RdCycleTime + (n - 1) × PageBurstAccessTime) × (TimeParaGranularity + 1) × GPMC_FCLK(17)
For burst write: C = (WrCycleTime + (n - 1) × PageBurstAccessTime) × (TimeParaGranularity + 1) × GPMC_FCLK(17)
With n being the page burst access number.
(4) For single read: D = (RdCycleTime - AccessTime) × (TimeParaGranularity + 1) × GPMC_FCLK(17)
For burst read: D = (RdCycleTime - AccessTime) × (TimeParaGranularity + 1) × GPMC_FCLK(17)
For burst write: D = (WrCycleTime - AccessTime) × (TimeParaGranularity + 1) × GPMC_FCLK(17)
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(5) For single read: E = (CSRdOffTime - AccessTime) × (TimeParaGranularity + 1) × GPMC_FCLK(17)
For burst read: E = (CSRdOffTime - AccessTime) × (TimeParaGranularity + 1) × GPMC_FCLK(17)
For burst write: E = (CSWrOffTime - AccessTime) × (TimeParaGranularity + 1) × GPMC_FCLK(17)
(6) For csn falling edge (CS activated):
– Case GpmcFCLKDivider = 0:
– F = 0.5 × CSExtraDelay × GPMC_FCLK(17)
– Case GpmcFCLKDivider = 1:
– F = 0.5 × CSExtraDelay × GPMC_FCLK(17) if (ClkActivationTime and CSOnTime are odd) or (ClkActivationTime and
CSOnTime are even)
– F = (1 + 0.5 × CSExtraDelay) × GPMC_FCLK(17) otherwise
– Case GpmcFCLKDivider = 2:
– F = 0.5 × CSExtraDelay × GPMC_FCLK(17) if ((CSOnTime - ClkActivationTime) is a multiple of 3)
– F = (1 + 0.5 × CSExtraDelay) × GPMC_FCLK(17) if ((CSOnTime - ClkActivationTime - 1) is a multiple of 3)
– F = (2 + 0.5 × CSExtraDelay) × GPMC_FCLK(17) if ((CSOnTime - ClkActivationTime - 2) is a multiple of 3)
ADVANCE INFORMATION
(7) For ADV falling edge (ADV activated):
– Case GpmcFCLKDivider = 0:
– G = 0.5 × ADVExtraDelay × GPMC_FCLK(17)
– Case GpmcFCLKDivider = 1:
– G = 0.5 × ADVExtraDelay × GPMC_FCLK(17) if (ClkActivationTime and ADVOnTime are odd) or (ClkActivationTime and
ADVOnTime are even)
– G = (1 + 0.5 × ADVExtraDelay) × GPMC_FCLK(17) otherwise
– Case GpmcFCLKDivider = 2:
– G = 0.5 × ADVExtraDelay × GPMC_FCLK(17) if ((ADVOnTime - ClkActivationTime) is a multiple of 3)
– G = (1 + 0.5 × ADVExtraDelay) × GPMC_FCLK(17) if ((ADVOnTime - ClkActivationTime - 1) is a multiple of 3)
– G = (2 + 0.5 × ADVExtraDelay) × GPMC_FCLK(17) if ((ADVOnTime - ClkActivationTime - 2) is a multiple of 3)
For ADV rising edge (ADV deactivated) in Reading mode:
– Case GpmcFCLKDivider = 0:
– G = 0.5 × ADVExtraDelay × GPMC_FCLK(17)
– Case GpmcFCLKDivider = 1:
– G = 0.5 × ADVExtraDelay × GPMC_FCLK(17) if (ClkActivationTime and ADVRdOffTime are odd) or (ClkActivationTime and
ADVRdOffTime are even)
– G = (1 + 0.5 × ADVExtraDelay) × GPMC_FCLK(17) otherwise
– Case GpmcFCLKDivider = 2:
– G = 0.5 × ADVExtraDelay × GPMC_FCLK(17) if ((ADVRdOffTime - ClkActivationTime) is a multiple of 3)
– G = (1 + 0.5 × ADVExtraDelay) × GPMC_FCLK(17) if ((ADVRdOffTime - ClkActivationTime - 1) is a multiple of 3)
– G = (2 + 0.5 × ADVExtraDelay) × GPMC_FCLK(17) if ((ADVRdOffTime - ClkActivationTime - 2) is a multiple of 3)
For ADV rising edge (ADV deactivated) in Writing mode:
– Case GpmcFCLKDivider = 0:
– G = 0.5 × ADVExtraDelay × GPMC_FCLK(17)
– Case GpmcFCLKDivider = 1:
– G = 0.5 × ADVExtraDelay × GPMC_FCLK(17) if (ClkActivationTime and ADVWrOffTime are odd) or (ClkActivationTime and
ADVWrOffTime are even)
– G = (1 + 0.5 × ADVExtraDelay) × GPMC_FCLK(17) otherwise
– Case GpmcFCLKDivider = 2:
– G = 0.5 × ADVExtraDelay × GPMC_FCLK(17) if ((ADVWrOffTime - ClkActivationTime) is a multiple of 3)
– G = (1 + 0.5 × ADVExtraDelay) × GPMC_FCLK(17) if ((ADVWrOffTime - ClkActivationTime - 1) is a multiple of 3)
– G = (2 + 0.5 × ADVExtraDelay) × GPMC_FCLK(17) if ((ADVWrOffTime - ClkActivationTime - 2) is a multiple of 3)
(8) For OE falling edge (OE activated) and IO DIR rising edge (Data Bus input direction):
– Case GpmcFCLKDivider = 0:
– H = 0.5 × OEExtraDelay × GPMC_FCLK(17)
– Case GpmcFCLKDivider = 1:
– H = 0.5 × OEExtraDelay × GPMC_FCLK(17) if (ClkActivationTime and OEOnTime are odd) or (ClkActivationTime and
OEOnTime are even)
– H = (1 + 0.5 × OEExtraDelay) × GPMC_FCLK(17) otherwise
– Case GpmcFCLKDivider = 2:
– H = 0.5 × OEExtraDelay × GPMC_FCLK(17) if ((OEOnTime - ClkActivationTime) is a multiple of 3)
– H = (1 + 0.5 × OEExtraDelay) × GPMC_FCLK(17) if ((OEOnTime - ClkActivationTime - 1) is a multiple of 3)
– H = (2 + 0.5 × OEExtraDelay) × GPMC_FCLK(17) if ((OEOnTime - ClkActivationTime - 2) is a multiple of 3)
For OE rising edge (OE deactivated):
– Case GpmcFCLKDivider = 0:
– H = 0.5 × OEExtraDelay × GPMC_FCLK(17)
– Case GpmcFCLKDivider = 1:
– H = 0.5 × OEExtraDelay × GPMC_FCLK(17) if (ClkActivationTime and OEOffTime are odd) or (ClkActivationTime and
OEOffTime are even)
– H = (1 + 0.5 × OEExtraDelay) × GPMC_FCLK(17) otherwise
– Case GpmcFCLKDivider = 2:
– H = 0.5 × OEExtraDelay × GPMC_FCLK(17) if ((OEOffTime - ClkActivationTime) is a multiple of 3)
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H = (1 + 0.5 × OEExtraDelay) × GPMC_FCLK(17) if ((OEOffTime - ClkActivationTime - 1) is a multiple of 3)
H = (2 + 0.5 × OEExtraDelay) × GPMC_FCLK(17) if ((OEOffTime - ClkActivationTime - 2) is a multiple of 3)
(9) For WE falling edge (WE activated):
– Case GpmcFCLKDivider = 0:
– I = 0.5 × WEExtraDelay × GPMC_FCLK(17)
– Case GpmcFCLKDivider = 1:
– I = 0.5 × WEExtraDelay × GPMC_FCLK(17) if (ClkActivationTime and WEOnTime are odd) or (ClkActivationTime and
WEOnTime are even)
– I = (1 + 0.5 × WEExtraDelay) × GPMC_FCLK(17) otherwise
– Case GpmcFCLKDivider = 2:
– I = 0.5 × WEExtraDelay × GPMC_FCLK(17) if ((WEOnTime - ClkActivationTime) is a multiple of 3)
– I = (1 + 0.5 × WEExtraDelay) × GPMC_FCLK(17) if ((WEOnTime - ClkActivationTime - 1) is a multiple of 3)
– I = (2 + 0.5 × WEExtraDelay) × GPMC_FCLK(17) if ((WEOnTime - ClkActivationTime - 2) is a multiple of 3)
ADVANCE INFORMATION
For WE rising edge (WE deactivated):
– Case GpmcFCLKDivider = 0:
– I = 0.5 × WEExtraDelay × GPMC_FCLK (17)
– Case GpmcFCLKDivider = 1:
– I = 0.5 × WEExtraDelay × GPMC_FCLK(17) if (ClkActivationTime and WEOffTime are odd) or (ClkActivationTime and
WEOffTime are even)
– I = (1 + 0.5 × WEExtraDelay) × GPMC_FCLK(17) otherwise
– Case GpmcFCLKDivider = 2:
– I = 0.5 × WEExtraDelay × GPMC_FCLK(17) if ((WEOffTime - ClkActivationTime) is a multiple of 3)
– I = (1 + 0.5 × WEExtraDelay) × GPMC_FCLK(17) if ((WEOffTime - ClkActivationTime - 1) is a multiple of 3)
– I = (2 + 0.5 × WEExtraDelay) × GPMC_FCLK(17) if ((WEOffTime - ClkActivationTime - 2) is a multiple of 3)
(10) J = GPMC_FCLK(17)
(11) First transfer only for CLK DIV 1 mode.
(12) Half cycle; for all data after initial transfer for CLK DIV 1 mode.
(13) Half cycle of GPMC_CLK_OUT; for all data for modes other than CLK DIV 1 mode. GPMC_CLK_OUT divide down from GPMC_FCLK.
(14) In GPMC_CSn[x], x is equal to 0, 1, 2 or 3. In GPMC_WAIT[x], x is equal to 0 or 1.
(15) P = GPMC_CLK period in ns
(16) For read: K = (ADVRdOffTime - ADVOnTime) × (TimeParaGranularity + 1) × GPMC_FCLK(17)
For write: K = (ADVWrOffTime - ADVOnTime) × (TimeParaGranularity + 1) × GPMC_FCLK(17)
(17) GPMC_FCLK is general-purpose memory controller internal functional clock period in ns.
(18) Related to the GPMC_CLK output clock maximum and minimum frequencies programmable in the GPMC module by setting the
GPMC_CONFIG1_CSx configuration register bit field GpmcFCLKDivider.
(19) The jitter probability density can be approximated by a Gaussian function.
(20) For div_by_1_mode:
– GPMC_CONFIG1_i Register: GPMCFCLKDIVIDER = 0h:
– GPMC_CLK frequency = GPMC_FCLK frequency
For GPMC_FCLK_MUX_100:
– gpmc_fclk_sel[1:0] = 01 = PER1_PLL_CLKOUT / 3 = 300 / 3 = 100MHz
For TIMEPARAGRANULARITY_X1:
– GPMC_CONFIG1_i Register: TIMEPARAGRANULARITY = 0h = x1 latencies (affecting RD/WRCYCLETIME,
RD/WRACCESSTIME, PAGEBURSTACCESSTIME, CSONTIME, CSRD/WROFFTIME, ADVONTIME, ADVRD/WROFFTIME,
OEONTIME, OEOFFTIME, WEONTIME, WEOFFTIME, CYCLE2CYCLEDELAY, BUSTURNAROUND, TIMEOUTSTARTVALUE,
WRDATAONADMUXBUS)
For no extra_delay:
– GPMC_CONFIG2_i Register : CSEXTRADELAY = 0h = CS i Timing control signal is not delayed
– GPMC_CONFIG4_i Register : WEEXTRADELAY = 0h = nWE timing control signal is not delayed
– GPMC_CONFIG4_i Register : OEEXTRADELAY = 0h = nOE timing control signal is not delayed
– GPMC_CONFIG3_i Register: ADVEXTRADELAY = 0h = nADV timing control signal is not delayed
172
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F1
F0
F1
GPMC_CLK
F2
F3
F18
GPMC_CSn[x]
F4
GPMC_A[MSB:1]
Valid Address
F6
F7
F19
GPMC_BE0n_CLE
F19
GPMC_BE1n
F6
F8
F8
F20
F9
F10
F11
GPMC_OEn_REn
F13
F12
GPMC_AD[15:0]
D0
GPMC_WAIT[x]
GPMC_01
A.
B.
In GPMC_CSn[x], x is equal to 0, 1, 2 or 3.
In GPMC_WAIT[x], x is equal to 0 or 1.
Figure 5-42. GPMC and NOR Flash—Synchronous Single Read—(GpmcFCLKDivider = 0)
Specifications
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GPMC_ADVn_ALE
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F1
F0
F1
GPMC_CLK
F2
F3
GPMC_CSn[x]
F4
GPMCA[MSB:1]
Valid Address
F6
F7
GPMC_BE0n_CLE
F7
GPMC_BE1n
F6
F8
F8
F9
GPMC_ADVn_ALE
F10
F11
GPMC_OEn_REn
F13
F13
ADVANCE INFORMATION
F12
D0
GPMC_AD[15:0]
F21
F12
D1
D2
D3
F22
GPMC_WAIT[x]
GPMC_02
A.
B.
In GPMC_CSn[x], x is equal to 0, 1, 2 or 3.
In GPMC_WAIT[x], x is equal to 0 or 1.
Figure 5-43. GPMC and NOR Flash—Synchronous Burst Read—4x16-bit (GpmcFCLKDivider = 0)
174
Specifications
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F1
F1
F0
GPMC_CLK
F2
F3
GPMC_CSn[x]
F4
Valid Address
GPMC_A[MSB:1]
F17
F6
F17
F17
GPMC_BE0n_CLE
F17
F17
F17
GPMC_BE1n
F6
F8
F8
F9
F14
F14
GPMC_WEn
F15
GPMC_AD[15:0]
D0
D1
F15
D2
F15
D3
GPMC_WAIT[x]
GPMC_03
A.
B.
In GPMC_CSn[x], x is equal to 0, 1, 2 or 3.
In GPMC_WAIT[x], x is equal to 0 or 1.
Figure 5-44. GPMC and NOR Flash—Synchronous Burst Write—(GpmcFCLKDivider > 0)
Specifications
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GPMC_ADVn_ALE
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F1
F0
F1
GPMC_CLK
F2
F3
GPMC_CSn[x]
F6
F7
GMPC_BE0n_CLE
Valid
F6
F7
Valid
GPMC_BE1n
F4
GPMC_A[27:17]
Address (MSB)
F12
F4
GPMC_AD[15:0]
F5
Address (LSB)
F13
D0
F8
D1
F12
D2
F8
D3
F9
GPMC_ADVn_ALE
ADVANCE INFORMATION
F10
F11
GPMC_OEn_REn
GPMC_WAIT[x]
GPMC_04
A.
B.
In GPMC_CSn[x], x is equal to 0, 1, 2 or 3.
In GPMC_WAIT[x], x is equal to 0 or 1.
Figure 5-45. GPMC and Multiplexed NOR Flash—Synchronous Burst Read
176
Specifications
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F1
F1
F0
GPMC_CLK
F2
F3
F18
GPMC_CSn[x]
F4
GPMC_A[27:17]
Address (MSB)
F17
F6
F17
F6
F17
F17
GPMC_BE1n
F17
F17
BPMC_BE0n_CLE
F8
F8
F20
F9
F14
F14
GPMC_WEn
F15
GPMC_AD[15:0]
Address (LSB)
D0
F22
F15
D1
F15
D2
D3
F21
GPMC_WAIT[x]
GPMC_05
A.
B.
In GPMC_CSn[x], x is equal to 0, 1, 2 or 3.
In GPMC_WAIT[x], x is equal to 0 or 1.
Figure 5-46. GPMC and Multiplexed NOR Flash—Synchronous Burst Write
5.9.5.10.2 GPMC and NOR Flash—Asynchronous Mode
Table 5-50 and Table 5-51 assume testing over the recommended operating conditions and electrical
characteristic conditions below (see Figure 5-47 through Figure 5-52).
Table 5-50. GPMC and NOR Flash Timing Requirements—Asynchronous Mode
NO.
MAX
UNIT
Data access time
div_by_1_mode;
GPMC_FCLK_MUX_133;
TIMEPARAGRANULARITY_X1
H
(5)
ns
FA20(2) tacc1-pgmode(d)
Page mode successive data access time
div_by_1_mode;
GPMC_FCLK_MUX_133;
TIMEPARAGRANULARITY_X1
P
(4)
ns
FA21(1) tacc2-pgmode(d)
Page mode first data access time
div_by_1_mode;
GPMC_FCLK_MUX_133;
TIMEPARAGRANULARITY_X1
H
(5)
ns
FA5(1)
PARAMETER
tacc(d)
DESCRIPTION
MODE
MIN
(1) The FA5 parameter illustrates the amount of time required to internally sample input data. It is expressed in number of GPMC functional
clock cycles. From start of read cycle and after FA5 functional clock cycles, input data is internally sampled by active functional clock
edge. FA5 value must be stored inside the AccessTime register bit field.
(2) The FA20 prameter illustrates amount of time required to internally sample successive input page data. It is expressed in number of
GPMC functional clock cycles. After each access to input page data, next input page data is internally sampled by active functional clock
edge after FA20 functional clock cycles. The FA20 value must be stored in the PageBurstAccessTime register bit field.
(3) The FA21 parameter illustrates amount of time required to internally sample first input page data. It is expressed in number of GPMC
functional clock cycles. From start of read cycle and after FA21 functional clock cycles, first input page data is internally sampled by
active functional clock edge. FA21 value must be stored inside the AccessTime register bit field.
(4) P = PageBurstAccessTime × (TimeParaGranularity + 1) × GPMC_FCLK(6)
(5) H = AccessTime × (TimeParaGranularity + 1) × GPMC_FCLK(6)
Specifications
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(6) GPMC_FCLK is general-purpose memory controller internal functional clock period in ns.
(7) For div_by_1_mode:
– GPMC_CONFIG1_i Register: GPMCFCLKDIVIDER = 0h:
– GPMC_CLK frequency = GPMC_FCLK frequency
For GPMC_FCLK_MUX_133:
– gpmc_fclk_sel[1:0] = 00 = CPSWHSDIV_CLKOUT3 = 2000/15 = 133.33 MHz
For TIMEPARAGRANULARITY_X1:
– GPMC_CONFIG1_i Register: TIMEPARAGRANULARITY = 0h = x1 latencies (affecting RD/WRCYCLETIME,
RD/WRACCESSTIME, PAGEBURSTACCESSTIME, CSONTIME, CSRD/WROFFTIME, ADVONTIME, ADVRD/WROFFTIME,
OEONTIME, OEOFFTIME, WEONTIME, WEOFFTIME, CYCLE2CYCLEDELAY, BUSTURNAROUND, TIMEOUTSTARTVALUE,
WRDATAONADMUXBUS)
Table 5-51. GPMC and NOR Flash Switching Characteristics—Asynchronous Mode
NO.
ADVANCE INFORMATION
FA0
FA1
FA3
PARAMETER
DESCRIPTION
MODE(15)
MIN
MAX
UNIT
tR(d)
Rise time, output data GPMC_AD[15:0]
div_by_1_mode;
GPMC_FCLK_MUX_133;
TIMEPARAGRANULARITY_X1
2
ns
tF(d)
Fall time, output data GPMC_AD[15:0]
div_by_1_mode;
GPMC_FCLK_MUX_133;
TIMEPARAGRANULARITY_X1
2
ns
tw(be[x]nV)
Pulse duration, output lower-byte enable and
command latch enable GPMC_BE0n_CLE, output
upper-byte enable GPMC_BE1n valid time
Read
N
(12)
ns
Write
N
(12)
Pulse duration, output chip select
GPMC_CSn[x](13) low
Read
A
(1)
Write
A
(1)
Delay time, output chip select GPMC_CSn[x](13)
valid to output address valid and address latch
enable GPMC_ADVn_ALE invalid
Read
-2+B (2)
2+B
(2)
Write
-2+B
(2)
2+B
(2)
tw(csnV)
td(csnV-advnIV)
(13)
ns
ns
FA4
td(csnV-oenIV)
Delay time, output chip select GPMC_CSn[x]
valid to output enable GPMC_OEn_REn invalid
(Single read)
div_by_1_mode;
GPMC_FCLK_MUX_133;
TIMEPARAGRANULARITY_X1
-2+C (3)
2+C
(3)
ns
FA9
td(aV-csnV)
Delay time, output address GPMC_A[27:1] valid to
output chip select GPMC_CSn[x](13) valid
div_by_1_mode;
GPMC_FCLK_MUX_133;
TIMEPARAGRANULARITY_X1
-2+J
(9)
2+J (9)
ns
FA10
td(be[x]nV-csnV)
Delay time, output lower-byte enable and
command latch enable GPMC_BE0n_CLE, output
upper-byte enable GPMC_BE1n valid to output
chip select GPMC_CSn[x](13) valid
div_by_1_mode;
GPMC_FCLK_MUX_133;
TIMEPARAGRANULARITY_X1
-2+J
(9)
2+J (9)
ns
FA12
td(csnV-advnV)
Delay time, output chip select GPMC_CSn[x](13)
valid to output address valid and address latch
enable GPMC_ADVn_ALE valid
div_by_1_mode;
GPMC_FCLK_MUX_133;
TIMEPARAGRANULARITY_X1
-2+K (10)
2+K
(10)
ns
FA13
td(csnV-oenV)
Delay time, output chip select GPMC_CSn[x](13)
valid to output enable GPMC_OEn_REn valid
div_by_1_mode;
GPMC_FCLK_MUX_133;
TIMEPARAGRANULARITY_X1
-2+L (11)
2+L
(11)
ns
FA16
tw(aIV)
Pulse duration output address GPMC_A[26:1]
invalid between 2 successive read and write
accesses
div_by_1_mode;
GPMC_FCLK_MUX_133;
TIMEPARAGRANULARITY_X1
G
FA18
td(csnV-oenIV)
Delay time, output chip select GPMC_CSn[x](13)
valid to output enable GPMC_OEn_REn invalid
(Burst read)
div_by_1_mode;
GPMC_FCLK_MUX_133;
TIMEPARAGRANULARITY_X1
-2+I (8)
FA20
tw(aV)
Pulse duration, output address GPMC_A[27:1]
valid - 2nd, 3rd, and 4th accesses
div_by_1_mode;
GPMC_FCLK_MUX_133;
TIMEPARAGRANULARITY_X1
D
FA25
td(csnV-wenV)
Delay time, output chip select GPMC_CSn[x](13)
valid to output write enable GPMC_WEn valid
div_by_1_mode;
GPMC_FCLK_MUX_133;
TIMEPARAGRANULARITY_X1
-2+E (5)
2+E
(5)
ns
FA27
td(csnV-wenIV)
Delay time, output chip select GPMC_CSn[x](13)
valid to output write enable GPMC_WEn invalid
div_by_1_mode;
GPMC_FCLK_MUX_133;
TIMEPARAGRANULARITY_X1
-2+F
2+F (6)
ns
178
Specifications
ns
(7)
2+I
(8)
ns
(4)
(6)
ns
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Table 5-51. GPMC and NOR Flash Switching Characteristics—Asynchronous Mode (continued)
DESCRIPTION
MODE(15)
FA28
NO.
td(wenV-dV)
PARAMETER
Delay time, output write enable GPMC_WEn valid
to output data GPMC_AD[15:0] valid
div_by_1_mode;
GPMC_FCLK_MUX_133;
TIMEPARAGRANULARITY_X1
FA29
td(dV-csnV)
Delay time, output data GPMC_AD[15:0] valid to
output chip select GPMC_CSn[x](13) valid
div_by_1_mode;
GPMC_FCLK_MUX_133;
TIMEPARAGRANULARITY_X1
FA37
td(oenV-aIV)
Delay time, output enable GPMC_OEn_REn valid
to output address GPMC_AD[15:0] phase end
div_by_1_mode;
GPMC_FCLK_MUX_133;
TIMEPARAGRANULARITY_X1
MIN
-2+J
(9)
MAX
UNIT
2.8
ns
2+J (9)
ns
2.8
ns
(1) For single read: A = (CSRdOffTime - CSOnTime) × (TimeParaGranularity + 1) × GPMC_FCLK(14)
For single write: A = (CSWrOffTime - CSOnTime) × (TimeParaGranularity + 1) × GPMC_FCLK(14)
For burst read: A = (CSRdOffTime - CSOnTime + (n - 1) × PageBurstAccessTime) × (TimeParaGranularity + 1) × GPMC_FCLK(14)
For burst write: A = (CSWrOffTime - CSOnTime + (n - 1) × PageBurstAccessTime) × (TimeParaGranularity + 1) × GPMC_FCLK(14)
with n being the page burst access number
(3) C = ((OEOffTime - CSOnTime) × (TimeParaGranularity + 1) + 0.5 × (OEExtraDelay - CSExtraDelay)) × GPMC_FCLK(14)
(4) D = PageBurstAccessTime × (TimeParaGranularity + 1) × GPMC_FCLK(14)
(5) E = ((WEOnTime - CSOnTime) × (TimeParaGranularity + 1) + 0.5 × (WEExtraDelay - CSExtraDelay)) × GPMC_FCLK(14)
(6) F = ((WEOffTime - CSOnTime) × (TimeParaGranularity + 1) + 0.5 × (WEExtraDelay - CSExtraDelay)) × GPMC_FCLK(14)
(7) G = Cycle2CycleDelay × GPMC_FCLK(14)
(8) I = ((OEOffTime + (n - 1) × PageBurstAccessTime - CSOnTime) × (TimeParaGranularity + 1) + 0.5 × (OEExtraDelay - CSExtraDelay)) ×
GPMC_FCLK(14)
(9) J = (CSOnTime × (TimeParaGranularity + 1) + 0.5 × CSExtraDelay) × GPMC_FCLK(14)
(10) K = ((ADVOnTime - CSOnTime) × (TimeParaGranularity + 1) + 0.5 × (ADVExtraDelay - CSExtraDelay)) × GPMC_FCLK(14)
(11) L = ((OEOnTime - CSOnTime) × (TimeParaGranularity + 1) + 0.5 × (OEExtraDelay - CSExtraDelay)) × GPMC_FCLK(14)
(12) For single read: N = RdCycleTime × (TimeParaGranularity + 1) × GPMC_FCLK(14)
For single write: N = WrCycleTime × (TimeParaGranularity + 1) × GPMC_FCLK(14)
For burst read: N = (RdCycleTime + (n - 1) × PageBurstAccessTime) × (TimeParaGranularity + 1) × GPMC_FCLK(14)
For burst write: N = (WrCycleTime + (n - 1) × PageBurstAccessTime) × (TimeParaGranularity + 1) × GPMC_FCLK(14)
(13) In GPMC_CSn[x], x is equal to 0, 1, 2 or 3.
(14) GPMC_FCLK is general-purpose memory controller internal functional clock period in ns.
(15) For div_by_1_mode:
– GPMC_CONFIG1_i Register: GPMCFCLKDIVIDER = 0h:
– GPMC_CLK frequency = GPMC_FCLK frequency
For GPMC_FCLK_MUX_133:
– gpmc_fclk_sel[1:0] = 00 = CPSWHSDIV_CLKOUT3 = 2000/15 = 133.33 MHz
For TIMEPARAGRANULARITY_X1:
– GPMC_CONFIG1_i Register: TIMEPARAGRANULARITY = 0h = x1 latencies (affecting RD/WRCYCLETIME,
RD/WRACCESSTIME, PAGEBURSTACCESSTIME, CSONTIME, CSRD/WROFFTIME, ADVONTIME, ADVRD/WROFFTIME,
OEONTIME, OEOFFTIME, WEONTIME, WEOFFTIME, CYCLE2CYCLEDELAY, BUSTURNAROUND, TIMEOUTSTARTVALUE,
WRDATAONADMUXBUS)
Specifications
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(2) For reading: B = ((ADVRdOffTime - CSOnTime) × (TimeParaGranularity + 1) + 0.5 × (ADVExtraDelay - CSExtraDelay)) ×
GPMC_FCLK(14)
For writing: B = ((ADVWrOffTime - CSOnTime) × (TimeParaGranularity + 1) + 0.5 × (ADVExtraDelay - CSExtraDelay)) ×
GPMC_FCLK(14)
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GPMC_FCLK
GPMC_CLK
FA5
FA1
GPMC_CSn[x]
FA9
Valid Address
GPMC_A[MSB:1]
FA0
FA10
GPMC_BE0n_CLE
Valid
GPMC_BE1n
Valid
FA0
FA10
FA3
FA12
GPMC_ADVn_ALE
ADVANCE INFORMATION
FA4
FA13
GPMC_OEn_REn
Data IN 0
GPMC_AD[15:0]
Data IN 0
GPMC_WAIT[x]
GPMC_06
A.
B.
C.
In GPMC_CSn[x], x is equal to 0, 1, 2 or 3. In GPMC_WAIT[x], x is equal to 0 or 1.
FA5 parameter illustrates amount of time required to internally sample input data. It is expressed in number of GPMC
functional clock cycles. From start of read cycle and after FA5 functional clock cycles, input data will be internally
sampled by active functional clock edge. FA5 value must be stored inside AccessTime register bits field.
GPMC_FCLK is an internal clock (GPMC functional clock) not provided externally.
Figure 5-47. GPMC and NOR Flash—Asynchronous Read—Single Word
180
Specifications
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GPMC_FCLK
GPMC_CLK
FA5
FA5
FA1
FA1
GPMC_CSn[x]
FA16
FA9
FA9
GPMC_A[MSB:1]
Address 0
Address 1
FA0
FA10
FA0
FA10
Valid
GPMC_BE0n_CLE
Valid
FA0
GPMC_BE1n
FA0
Valid
FA10
Valid
FA10
FA3
FA3
FA12
GPMC_ADCn_ALE
FA4
FA4
FA13
FA13
GPMC_OEn_REn
GPMC_AD[15:0]
Data Upper
GPMC_WAIT[x]
GPMC_07
A.
B.
C.
In GPMC_CSn[x], x is equal to 0, 1, 2 or 3. In GPMC_WAIT[x], x is equal to 0 or 1.
FA5 parameter illustrates amount of time required to internally sample input data. It is expressed in number of GPMC
functional clock cycles. From start of read cycle and after FA5 functional clock cycles, input data will be internally
sampled by active functional clock edge. FA5 value must be stored inside AccessTime register bits field.
GPMC_FCLK is an internal clock (GPMC functional clock) not provided externally.
Figure 5-48. GPMC and NOR Flash—Asynchronous Read—32-Bit
Specifications
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ADVANCE INFORMATION
FA12
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GPMC_FCLK
GPMC_CLK
FA20
FA20
FA20
Add1
Add2
Add3
D0
D1
D2
FA21
FA1
GPMC_CSn[x]
FA9
Add0
GPMC_A[MSB:1]
Add4
FA0
FA10
GPMC_BE0n_CLE
FA0
FA10
GPMC_BE1n
FA12
GPMC_ADVn_ALE
ADVANCE INFORMATION
FA18
FA13
GPMC_OEn_REn
GPMC_AD[15:0]
D3
D3
GPMC_WAIT[x]
GPMC_08
A.
B.
C.
D.
In GPMC_CSn[x], x is equal to 0, 1, 2 or 3. In GPMC_WAIT[x], x is equal to 0 or 1.
FA21 parameter illustrates amount of time required to internally sample first input page data. It is expressed in
number of GPMC functional clock cycles. From start of read cycle and after FA21 functional clock cycles, first input
page data will be internally sampled by active functional clock edge. FA21 calculation must be stored inside
AccessTime register bits field.
FA20 parameter illustrates amount of time required to internally sample successive input page data. It is expressed in
number of GPMC functional clock cycles. After each access to input page data, next input page data will be internally
sampled by active functional clock edge after FA20 functional clock cycles. FA20 is also the duration of address
phases for successive input page data (excluding first input page data). FA20 value must be stored in
PageBurstAccessTime register bits field.
GPMC_FCLK is an internal clock (GPMC functional clock) not provided externally.
Figure 5-49. GPMC and NOR Flash—Asynchronous Read—Page Mode 4x16-Bit
182
Specifications
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GPMC_FCLK
GPMC_CLK
FA1
GPMC_CSn[x]
FA9
GPMC_A[MSB:1]
Valid Address
FA0
FA10
GPMC_BE0n_CLE
FA0
FA10
GPMC_BE1n
FA3
FA12
GPMC_ADVn_ALE
GPMC_WEn
FA29
GPMC_AD[15:0]
Data OUT
GPMC_WAIT[x]
GPMC_09
A.
In GPMC_CSn[x], x is equal to 0, 1, 2 or 3. In GPMC_WAIT[x], x is equal to 0 or 1.
Figure 5-50. GPMC and NOR Flash—Asynchronous Write—Single Word
Specifications
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ADVANCE INFORMATION
FA27
FA25
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GPMC_FCLK
GPMC_CLK
FA1
FA5
GPMC_CSn[x]
FA9
GPMC_A[27:17]
Address (MSB)
FA0
FA10
GPMC_BE0n_CLE
Valid
FA0
FA10
GPMC_BE1n
Valid
FA3
FA12
GPMC_ADVn_ALE
ADVANCE INFORMATION
FA4
FA13
GPMC_OEn_REn
FA29
GPMC_AD[15:0]
FA37
Data IN
Address (LSB)
Data IN
GPMC_WAIT[x]
GPMC_10
A.
B.
C.
In GPMC_CSn[x], x is equal to 0, 1, 2 or 3. In GPMC_WAIT[x], x is equal to 0 or 1.
FA5 parameter illustrates amount of time required to internally sample input data. It is expressed in number of GPMC
functional clock cycles. From start of read cycle and after FA5 functional clock cycles, input data will be internally
sampled by active functional clock edge. FA5 value must be stored inside AccessTime register bits field.
GPMC_FCLK is an internal clock (GPMC functional clock) not provided externally.
Figure 5-51. GPMC and Multiplexed NOR Flash—Asynchronous Read—Single Word
184
Specifications
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GPMC_FCLK
GPMC_CLK
FA1
GPMC_CSn[x]
FA9
GPMC_A[27:17]
Address (MSB)
FA0
FA10
GPMC_BE0n_CLE
FA0
FA10
GPMC_BE1n
FA3
FA12
GPMC_ADVn_ALE
GPMC_WEn
FA29
GPMC_AD[15:0]
FA28
Valid Address (LSB)
Data OUT
GPMC_WAIT[x]
GPMC_11
A.
In GPMC_CSn[x], x is equal to 0, 1, 2 or 3. In GPMC_WAIT[x], x is equal to 0 or 1.
Figure 5-52. GPMC and Multiplexed NOR Flash—Asynchronous Write—Single Word
Specifications
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FA27
FA25
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5.9.5.10.3 GPMC and NAND Flash—Asynchronous Mode
Table 5-52 and Table 5-53 assume testing over the recommended operating conditions and electrical
characteristic conditions below (see Figure 5-53 through Figure 5-56).
Table 5-52. GPMC and NAND Flash Timing Requirements—Asynchronous Mode
NO.
PARAMETER
GNF12(1)
tacc(d)
DESCRIPTION
Access time, input data GPMC_AD[15:0]
MODE(4)
(3)
MIN
div_by_1_mode;
GPMC_FCLK_MUX_133;
TIMEPARAGRANULARITY_X1
MAX
UNIT
J
ns
(2)
(1) The GNF12 parameter illustrates the amount of time required to internally sample input data. It is expressed in number of GPMC
functional clock cycles. From start of the read cycle and after GNF12 functional clock cycles, input data is internally sampled by the
active functional clock edge. The GNF12 value must be stored inside AccessTime register bit field.
(2) J = AccessTime × (TimeParaGranularity + 1) × GPMC_FCLK(3)
(3) GPMC_FCLK is general-purpose memory controller internal functional clock period in ns.
(4) For div_by_1_mode:
– GPMC_CONFIG1_i Register: GPMCFCLKDIVIDER = 0h:
– GPMC_CLK frequency = GPMC_FCLK frequency
ADVANCE INFORMATION
For GPMC_FCLK_MUX_133:
– gpmc_fclk_sel[1:0] = 00 = CPSWHSDIV_CLKOUT3 = 2000/15 = 133.33 MHz
For TIMEPARAGRANULARITY_X1:
– GPMC_CONFIG1_i Register: TIMEPARAGRANULARITY = 0h = x1 latencies (affecting RD/WRCYCLETIME,
RD/WRACCESSTIME, PAGEBURSTACCESSTIME, CSONTIME, CSRD/WROFFTIME, ADVONTIME, ADVRD/WROFFTIME,
OEONTIME, OEOFFTIME, WEONTIME, WEOFFTIME, CYCLE2CYCLEDELAY, BUSTURNAROUND, TIMEOUTSTARTVALUE,
WRDATAONADMUXBUS)
Table 5-53. GPMC and NAND Flash Switching Characteristics—Asynchronous Mode
NO.
PARAMETER
MODE(15)
MIN
MAX
UNIT
tR(d)
Rise time, output data GPMC_AD[15:0]
div_by_1_mode;
GPMC_FCLK_MUX_133;
TIMEPARAGRANULARITY_X1
2
ns
tF(d)
Fall time, output data GPMC_AD[15:0]
div_by_1_mode;
GPMC_FCLK_MUX_133;
TIMEPARAGRANULARITY_X1
2
ns
GNF0 tw(wenV)
Pulse duration, output write enable GPMC_WEn
valid
div_by_1_mode;
GPMC_FCLK_MUX_133;
TIMEPARAGRANULARITY_X1
A(1)
GNF1 td(csnV-wenV)
Delay time, output chip select GPMC_CSn[x](13)
valid to output write enable GPMC_WEn valid
div_by_1_mode;
GPMC_FCLK_MUX_133;
TIMEPARAGRANULARITY_X1
-2+B (2)
2+B
(2)
ns
GNF2 tw(cleH-wenV)
Delay time, output lower-byte enable and
command latch enable GPMC_BE0n_CLE high to
output write enable GPMC_WEn valid
div_by_1_mode;
GPMC_FCLK_MUX_133;
TIMEPARAGRANULARITY_X1
-2+C (3)
2+C
(3)
ns
GNF3 tw(wenV-dV)
Delay time, output data GPMC_AD[15:0] valid to
output write enable GPMC_WEn valid
div_by_1_mode;
GPMC_FCLK_MUX_133;
TIMEPARAGRANULARITY_X1
-2+D (4) 2.8+D (4)
ns
GNF4 tw(wenIV-dIV)
Delay time, output write enable GPMC_WEn
invalid to output data GPMC_AD[15:0] invalid
div_by_1_mode;
GPMC_FCLK_MUX_133;
TIMEPARAGRANULARITY_X1
-2+E (5) 2.8+E (5)
ns
GNF5 tw(wenIV-cleIV)
Delay time, output write enable GPMC_WEn
invalid to output lower-byte enable and command
latch enable GPMC_BE0n_CLE invalid
div_by_1_mode;
GPMC_FCLK_MUX_133;
TIMEPARAGRANULARITY_X1
-2+F
2+F (6)
ns
GNF6 tw(wenIV-csnIV)
Delay time, output write enable GPMC_WEn
invalid to output chip select GPMC_CSn[x](13)
invalid
div_by_1_mode;
GPMC_FCLK_MUX_133;
TIMEPARAGRANULARITY_X1
-2+G (7)
2+G
(7)
ns
GNF7 tw(aleH-wenV)
Delay time, output address valid and address latch
enable GPMC_ADVn_ALE high to output write
enable GPMC_WEn valid
div_by_1_mode;
GPMC_FCLK_MUX_133;
TIMEPARAGRANULARITY_X1
-2+C (3)
2+C
(3)
ns
186
Specifications
(6)
ns
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Table 5-53. GPMC and NAND Flash Switching Characteristics—Asynchronous Mode (continued)
NO.
PARAMETER
MODE(15)
MIN
GNF8 tw(wenIV-aleIV)
Delay time, output write enable GPMC_WEn
invalid to output address valid and address latch
enable GPMC_ADVn_ALE invalid
div_by_1_mode;
GPMC_FCLK_MUX_133;
TIMEPARAGRANULARITY_X1
-2+F
GNF9 tc(wen)
Cycle time, write
div_by_1_mode;
GPMC_FCLK_MUX_133;
TIMEPARAGRANULARITY_X1
GNF1 td(csnV-oenV)
0
Delay time, output chip select GPMC_CSn[x](13)
valid to output enable GPMC_OEn_REn valid
div_by_1_mode;
GPMC_FCLK_MUX_133;
TIMEPARAGRANULARITY_X1
GNF1 tw(oenV)
3
Pulse duration, output enable GPMC_OEn_REn
valid
div_by_1_mode;
GPMC_FCLK_MUX_133;
TIMEPARAGRANULARITY_X1
GNF1 tc(oen)
4
Cycle time, read
div_by_1_mode;
GPMC_FCLK_MUX_133;
TIMEPARAGRANULARITY_X1
L
(11)
GNF1 tw(oenIV-csnIV)
5
Delay time, output enable GPMC_OEn_REn
invalid to output chip select GPMC_CSn[x](13)
invalid
div_by_1_mode;
GPMC_FCLK_MUX_133;
TIMEPARAGRANULARITY_X1
-2+M
(12)
(6)
-2+I (9)
MAX
UNIT
2+F (6)
ns
H
(8)
ns
2+I
(9)
ns
K
(10)
ns
ns
2+M
(12)
ns
ADVANCE INFORMATION
(1) A = (WEOffTime - WEOnTime) × (TimeParaGranularity + 1) × GPMC_FCLK(14)
(2) B = ((WEOnTime - CSOnTime) × (TimeParaGranularity + 1) + 0.5 × (WEExtraDelay - CSExtraDelay)) × GPMC_FCLK(14)
(3) C = ((WEOnTime - ADVOnTime) × (TimeParaGranularity + 1) + 0.5 × (WEExtraDelay - ADVExtraDelay)) × GPMC_FCLK(14)
(4) D = (WEOnTime × (TimeParaGranularity + 1) + 0.5 × WEExtraDelay) × GPMC_FCLK(14)
(5) E = ((WrCycleTime - WEOffTime) × (TimeParaGranularity + 1) - 0.5 × WEExtraDelay) × GPMC_FCLK(14)
(6) F = ((ADVWrOffTime - WEOffTime) × (TimeParaGranularity + 1) + 0.5 × (ADVExtraDelay - WEExtraDelay)) × GPMC_FCLK(14)
(7) G = ((CSWrOffTime - WEOffTime) × (TimeParaGranularity + 1) + 0.5 × (CSExtraDelay - WEExtraDelay)) × GPMC_FCLK(14)
(8) H = WrCycleTime × (1 + TimeParaGranularity) × GPMC_FCLK(14)
(9) I = ((OEOnTime - CSOnTime) × (TimeParaGranularity + 1) + 0.5 × (OEExtraDelay - CSExtraDelay)) × GPMC_FCLK(14)
(10) K = (OEOffTime - OEOnTime) × (1 + TimeParaGranularity) × GPMC_FCLK(14)
(11) L = RdCycleTime × (1 + TimeParaGranularity) × GPMC_FCLK(14)
(12) M = ((CSRdOffTime - OEOffTime) × (TimeParaGranularity + 1) + 0.5 × (CSExtraDelay - OEExtraDelay)) × GPMC_FCLK(14)
(13) In GPMC_CSn[x], x is equal to 0, 1, 2 or 3.
(14) GPMC_FCLK is general-purpose memory controller internal functional clock period in ns.
(15) For div_by_1_mode:
– GPMC_CONFIG1_i Register: GPMCFCLKDIVIDER = 0h:
– GPMC_CLK frequency = GPMC_FCLK frequency
For GPMC_FCLK_MUX_133:
– gpmc_fclk_sel[1:0] = 00 = CPSWHSDIV_CLKOUT3 = 2000/15 = 133.33 MHz
For TIMEPARAGRANULARITY_X1:
– GPMC_CONFIG1_i Register: TIMEPARAGRANULARITY = 0h = x1 latencies (affecting RD/WRCYCLETIME,
RD/WRACCESSTIME, PAGEBURSTACCESSTIME, CSONTIME, CSRD/WROFFTIME, ADVONTIME, ADVRD/WROFFTIME,
OEONTIME, OEOFFTIME, WEONTIME, WEOFFTIME, CYCLE2CYCLEDELAY, BUSTURNAROUND, TIMEOUTSTARTVALUE,
WRDATAONADMUXBUS)
Specifications
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GPMC_FCLK
GNF1
GNF6
GNF2
GNF5
GPMC_CSn[x]
GPMC_BE0n_CLE
GPMC_ADCn_ALE
GPMC_OEn_REn
GNF0
GPMC_WEn
GNF3
GNF4
GPMC_AD[15:0]
Command
GPMC_12
(1)
In GPMC_CSn[x], x is equal to 0, 1, 2 or 3.
Figure 5-53. GPMC and NAND Flash—Command Latch Cycle
ADVANCE INFORMATION
GPMC_FCLK
GNF1
GNF6
GNF7
GNF8
GPMC_CSn[x]
GPMC_BE0n_CLE
GPMC_ADVn_ALE
GPMC_OEn_REn
GNF9
GNF0
GPMC_WEn
GNF3
GPMC_AD[15:0]
GNF4
Address
GPMC_13
(1)
In GPMC_CSn[x], x is equal to 0, 1, 2 or 3.
Figure 5-54. GPMC and NAND Flash—Address Latch Cycle
188
Specifications
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GPMC_FCLK
GNF12
GNF10
GNF15
GPMC_CSn[x]
GPMC_BE0n_CLE
GPMC_ADVn_ALE
GNF14
GNF13
GPMC_OEn_REn
GPMC_AD[15:0]
DATA
GPMC_WAIT[x]
(2)
(3)
GNF12 parameter illustrates amount of time required to internally sample input data. It is expressed in number of GPMC functional
clock cycles. From start of read cycle and after GNF12 functional clock cycles, input data will be internally sampled by active
functional clock edge. GNF12 value must be stored inside AccessTime register bits field.
GPMC_FCLK is an internal clock (GPMC functional clock) not provided externally.
In GPMC_CSn[x], x is equal to 0, 1, 2 or 3. In GPMC_WAIT[x], x is equal to 0 or 1.
Figure 5-55. GPMC and NAND Flash—Data Read Cycle
GPMC_FCLK
GNF1
GNF6
GPMC_CSn[x]
GPMC_BE0n_CLE
GPMC_ADVn_ALE
GPMC_OEn_REn
GNF9
GNF0
GPMC_WEn
GNF3
GPMC_AD[15:0]
GNF4
DATA
GPMC_15
(1)
In GPMC_CSn[x], x is equal to 0, 1, 2 or 3.
Figure 5-56. GPMC and NAND Flash—Data Write Cycle
For more information, see section General-Purpose Memory Controller (GPMC) in the device TRM.
5.9.5.11 HYPERBUS
For more details about features and additional description information on the device Hyperbus, see the
corresponding sections within Section 4.3, Signal Descriptions and Section 6, Detailed Description.
Table 5-54, Table 5-55, and Table 5-56 assume testing over the recommended operating conditions and
electrical characteristic conditions (see Figure 5-57, Figure 5-58, and Figure 5-59).
Specifications
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GPMC_14
(1)
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Table 5-54. Timing Requirements for HyperBus Initialization
NO.
PARAMETER
DESCRIPTION
MIN
D1
tw(RESETn)
RESETn Pulse Width
200
MAX
UNIT
ns
D2
tw(csL)
Chip Select Pulse Width
D3
td(RESETnH-csL)
Delay time, RESETn inactive to CSn active
D4
td(csL-RWDSL)
Delay time, CSn active to RWDS falling
1000
ns
200.34
ns
115
ns
Table 5-55. HyperBus 166 MHz Switching Characteristics
ADVANCE INFORMATION
NO.
PARAMETER
DESCRIPTION
D5
tskn(rwdsX-dV)
Input skew, RWDS transitioning to D0:D7 valid
MIN
MAX
UNIT
-0.46
0.46
ns
D6
tc(clk/clkn)
CLK period, CLK/CLKn
6
ns
D7
tw(clk/clkn)
Pulse width, CLK/CLKn
2.7
ns
D8
tw(csIV)
Pulse width, CS0 invalid between operations
6
ns
D9
td(clkH-csL)
Delay time, CS0 active to CLK rising/ CLKn falling
-3.41
ns
D10
td(clkL[LE]-csH)
Delay time, last falling CLK/ rising CLKn edge to CS0 inactive
0.66
D11
td(clkX-rwdsV)
Delay time, CLK transition to RWDS valid
1.01
2.02
ns
D12
td(clkX-d[0:7]V)
Delay time, CLK transitioning to D0:7 valid
0.84
2.2
ns
MIN
MAX
UNIT
-0.81
0.81
ns
ns
Table 5-56. HyperBus 100 MHz Switching Characteristics
PARAMETER
DESCRIPTION
LFD5
NO.
tskn(rwdsX-dV)
Input skew, RWDS transitioning to D0:D7 valid
LFD6
tc(clk)
CLK period, CLK
10
ns
LFD7
tw(clk)
Pulse width, CLK
4.5
ns
LFD8
tw(csIV)
Pulse width, CS0 invalid between operations
10
ns
LFD9
td(clkH-csL)
Delay time, CS0 active to CLK rising
-3.76
ns
LFD10
td(clkL[LE]-csH)
Delay time, last falling CLK edge to CS0 inactive
1.77
ns
LFD11
td(clkX-rwdsV)
Delay time, CLK transition to RWDS valid
2.05
3.24
ns
LFD12
td(clkX-d[0:7]V)
Delay time, CLK transitioning to D0:7 valid
1.87
3.41
ns
D8/LFD8
D2
CS#
D9/LFD9
D10/LFD10
CK, CK#
D6/LFD6
D7/LFD7
D4
D11/LFD11
RWDS
D12/LFD12
D12/LFD12
DQ[7:0]
47:40
39:32
31:24
23:16
15:8
7:0
Command-Address
Dn
Dn
A
B
Dn+1 Dn+1
A
B
CK and Data are center aligned
Host drives DQ[7:0] and RWDS
Host drives DQ[7:0] and Memory drives RWDS
HYPERBUS_TIMING_01
Figure 5-57. HyperBus Timing Diagrams - Transmitter Mode
190
Specifications
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D8/LFD8
D2
CS#
D9/LFD9
D10/LFD10
CK, CK#
D6/LFD6
D4
D7/LFD7
RWDS
D5/LFD5
D12/LFD12
D5/LFD5
DQ[7:0]
47:40
39:32
31:24
23:16
15:8
7:0
Dn
Dn
A
B
Dn+1 Dn+1
A
B
CK and Data are center aligned
Command-Address
Host drives DQ[7:0] and RWDS
Host drives DQ[7:0] and Memory drives RWDS
HYPERBUS_TIMING_02
Figure 5-58. HyperBus Timing Diagrams - Receiver Mode
RESET#
D3
CS#
HYPERBUS_TIMING_03
Figure 5-59. HyperBus Timing Diagrams - Reset
For more information, see section HyperBus Interface in the device TRM.
5.9.5.12 I2C
For more details about features and additional description information on the device Inter-Integrated
Circuit, see the corresponding sections within Section 4.3, Signal Descriptions and Section 6, Detailed
Description.
Table 5-57 and Figure 5-60 assume testing over the recommended operating conditions and electrical
characteristic conditions.
Table 5-57. Timing Requirements for I2C Input Timings(1)(6)
NO.
PARAMETER
DESCRIPTION
MODE
I1
tc(SCL)
Cycle time, SCL
Standard
10000
ns
Fast
2500
ns
I2
tsu(SCLH-SDAL)
Setup time, SCL high before SDA low (for a repeated
START condition)
Standard
4700
ns
Fast
600
ns
Hold time, SCL low after SDA low (for a START and a
repeated START condition)
Standard
4000
ns
Fast
900
ns
Pulse duration, SCL low
Standard
4700
ns
Fast
1300
ns
Standard
4000
ns
Fast
600
ns
Standard
250
ns
I3
I4
I5
I6
th(SDAL-SCLL)
tw(SCLL)
tw(SCLH)
tsu(SDAV-SCLH)
Pulse duration, SCL high
Setup time, SDA valid before SCL high
Fast
I7
th(SCLL-SDAV)
Hold time, SDA valid after SCL low
MIN
MAX
(2)
100
ns
Standard
0(3)
3450(4)
ns
Fast
0(3)
900(4)
ns
Specifications
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191
ADVANCE INFORMATION
D1
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Table 5-57. Timing Requirements for I2C Input Timings(1)(6) (continued)
NO.
PARAMETER
DESCRIPTION
MODE
MIN
I8
tw(SDAH)
Pulse duration, SDA high between STOP and START
conditions
Standard
4700
Fast
1300
I9
tr(SDA)
Rise time, SDA
Standard
Fast
I10
tr(SCL)
Rise time, SCL
I11
tf(SDA)
Fall time, SDA
I12
tf(SCL)
Fall time, SCL
ADVANCE INFORMATION
I14
tsu(SCLH-SDAH)
tw(SP)
ns
ns
20+.1Cb(5)
300(3)
ns
1000
ns
20+.1Cb(5)
300(3)
ns
300
ns
20+.1Cb(5)
300(3)
ns
300
ns
300
ns
(7)
(7)
(7)
(7)
(7)
(7)
Standard
Fast
I13
ns
Standard
Fast
Setup time, SCL high before SDA high (for STOP condition)
Pulse duration, spike (must be supressed)
UNIT
1000
Standard
Fast
MAX
20+.1Cb
Standard
4000
ns
Fast
600
ns
Standard
Fast
ns
0
50
ns
1
ns
I15
tskew
Skew
Standard
1
ns
I16
Cb
Capacitive load for each bus line
Standard
400
pF
Fast
400
pF
Fast
(1) The I2C pins SDA and SCL do not feature fail-safe I/O buffers. These pins could potentially draw current when the devive is powered
down.
(2) A Fast-mode I2C-bus™ device can be used in a Standard-mode I2C-bus system, but the requirement tsu(SDA-SCLH) ≥ 250 ns must then
be met. This will automatically be the case if the device does not stretch the LOW period of the SCL signal. If such a device does stretch
the LOW period of the SCL signal, it must output the next data bit to the SDA line tr max + tsu(SDA-SCLH)= 1000 + 250 = 1250 ns
(according to the Standard-mode I2C-Bus Specification) before the SCL line is released.
(3) A device must internally provide a hold time of at least 300 ns for the SDA signal (referred to the VIHmin of the SCL signal) to bridge the
undefined region of the falling edge of SCL.
(4) The maximum th(SDA-SCLL) has only to be met if the device does not stretch the low period [tw(SCLL)] of the SCL signal.
(5) Cb = total capacitance of one bus line in pF. If mixed with HS-mode devices, faster fall-times are allowed
(6) Software must properly configure the I2C module registers to achieve the timings shown in this table. See the device TRM for details.
(7) These timings apply only to MCU_I2C0 and WKUP_I2C0. MAIN_I2C[0:3] use standard LVCMOS buffers to emulate open-drain buffers
and their rise/fall times should be referenced in the device IBIS model.
I9
I11
I2Cx_SDA
I6
I8
I14
I4
I13
I5
I10
I2Cx_SCL
I12
I1
I3
I7
I2
I3
Stop
Start
Repeated
Start
Stop
Figure 5-60. I2C Receive Timing(1)
(1) x in I2Cx_SDA and I2Cx_SCL is 0, 1 or 2.
192
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Table 5-58 and Figure 5-61 assume testing over the recommended operating conditions and electrical
characteristic conditions.
Table 5-58. Switching Characteristics Over Recommended Operating Conditions for I2C Output Timings
PARAMETER
DESCRIPTION
MODE
MIN
MAX
UNIT
I16
tc(SCL)
Cycle time, SCL
Standard
10000
ns
Fast
2500
ns
4700
ns
I17
tsu(SCLH-SDAL)
Setup time, SCL high before SDA low (for a repeated START
condition)
Standard
Fast
600
ns
I18
th(SDAL-SCLL)
Hold time, SCL low after SDA low (for a START and a
repeated START condition)
Standard
4000
ns
Fast
900
ns
Pulse duration, SCL low
Standard
4700
ns
Fast
1300
ns
Standard
4000
ns
Fast
600
ns
Standard
250
ns
Fast
100 (2)
I19
I20
I21
I22
tw(SCLL)
tw(SCLH)
tsu(SDAV-SCLH)
th(SCLL-SDAV)
Pulse duration, SCL high
Setup time, SDA valid before SCL high
Hold time, SDA valid after SCL low
Standard
Fast
I23
I24
tw(SDAH)
tr(SDA)
tr(SCL)
tf(SDA)
I28
I29
I30
tf(SCL)
tsu(SCLH-SDAH)
tskew
Cb
900
(4)
ns
ns
4700
ns
Fast
1300
ns
Rise time, SDA
Standard
Rise time, SCL
20+.1Cb
(5) (7)
1000
ns
300 (3) (7)
ns
1000
ns
Standard
Fall time, SDA
20+.1Cb
(5) (7)
300
Standard
Fast
I27
0
(3)
ns
3450 (4)
Standard
Fast
I26
(3)
Pulse duration, SDA high between STOP and START
conditions
Fast
I25
0
Fall time, SCL
Skew
Capacitive load for each bus line
(3) (7)
ns
ns
20+.1Cb
300
300
ns
Fast
20+.1Cb
300 (3) (7)
ns
Standard
4000
ns
Fast
600
ns
Standard
Setup time, SCL high before SDA high (for STOP condition)
(3) (7)
300
(5) (7)
(5) (7)
ADVANCE INFORMATION
NO.
ns
Standard
3
Fast
20
ns
ns
Standard
400
pF
Fast
400
pF
(1) The I2C pins SDA and SCL do not feature fail-safe I/O buffers. These pins could potentially draw current when the devive is powered
down.
(2) A Fast-mode I2C-bus™ device can be used in a Standard-mode I2C-bus system, but the requirement tsu(SDA-SCLH)≥ 250 ns must
then be met. This will automatically be the case if the device does not stretch the LOW period of the SCL signal. If such a device does
stretch the LOW period of the SCL signal, it must output the next data bit to the SDA line tr max + tsu(SDA-SCLH) = 1000 + 250 = 1250 ns
(according to the Standard-mode I2C-Bus Specification) before the SCL line is released.
(3) A device must internally provide a hold time of at least 300 ns for the SDA signal (referred to the VIHmin of the SCL signal) to bridge the
undefined region of the falling edge of SCL.
(4) The maximum th(SDA-SCLL) has only to be met if the device does not stretch the low period [tw(SCLL)] of the SCL signal.
(5) Cb = total capacitance of one bus line in pF. If mixed with HS-mode devices, faster fall-times are allowed.
(6) Software must properly configure the I2C module registers to achieve the timings shown in this table. See the device TRM for details.
(7) These timings apply only to MCU_I2C0 and WKUP_I2C0. MAIN_I2C[0:3] use standard LVCMOS buffers to emulate open-drain buffers
and their rise/fall times should be referenced in the device IBIS model.
Specifications
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NOTE
I2C emulation is achieved by configuring the LVCMOS buffers to output HiZ instead of
driving high when transmitting logic-1.
I26
I24
I2C[x]_SDA
I23
I21
I19
I25
I28
I20
I2C[x]_SCL
I27
I16
I18
I22
I17
I18
Stop
Start
ADVANCE INFORMATION
Repeated
Start
Stop
Figure 5-61. I2C Transmit Timing(1)
(1) x in I2Cx_SDA and I2Cx_SCL is 0, 1 or 2.
For more information, see section Inter-Integrated Circuit (I2C) Interface in the device TRM.
5.9.5.13 MCAN
For more details about features and additional description information on the device Controller Area
Network Interface, see the corresponding sections within Section 4.3, Signal Descriptions and Section 6,
Detailed Description.
Table 5-59 presents timing parameters for MCANi Interface.
Table 5-59. MCAN Register to Pin Timings
NO.
PARAMETER
DESCRIPTION
MODE
M1
tp(MCANi_TX)
Delay Time Max, Transmit Shift Register to MCANi_TX pin
Normal
MIN
MAX
10
UNIT
ns
M2
tp(MCANi_RX)
Delay Time Max, MCANi_RX pin to receive shift register
Normal
10
ns
(1) i in MCANi_* = 0 or 1.
For more information, see section Controller Area Network (MCAN) in the device TRM.
5.9.5.14 MCASP
For more details about features and additional description information on the device Multichannel Audio
Serial Port, see the corresponding sections within Section 4.3, Signal Descriptions and Section 6, Detailed
Description.
Table 5-60, and Figure 5-62 present timing requirements for MCASP0 to MCASP2.
Table 5-60. Timing Requirements for MCASP(1)
NO.
PARAMETER
DESCRIPTION
ASP1
tc(AHCLKRX)
Cycle time, AHCLKR/X
ASP2
tw(AHCLKRX)
Pulse duration, AHCLKR/X high or low
ASP3
tc(ACLKRX)
Cycle time, ACLKR/X
194
Mode
Specifications
MIN
MAX
UNIT
20
ns
0.5P - 2.5
ns
20
ns
(2)
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Table 5-60. Timing Requirements for MCASP(1) (continued)
PARAMETER
DESCRIPTION
ASP4
NO.
tw(ACLKRX)
Pulse duration, ACLKR/X high or low
Mode
ASP5
tsu(AFSRX-
Setup time, AFSR/X input valid before ACLKR/X
ACLKRX)
ASP6
th(ACLKRX-AFSRX)
ACLKR/X int
ACLKR/X int
ACLKR/X ext in/out
ASP7
tsu(AXR-ACLKRX)
Setup time, AXR input valid before ACLKR/X
ACLKR/X int
ACLKR/X ext in/out
ASP8
th(ACLKRX-AXR)
Hold time, AXR input valid after ACLKR/X
MAX
ACLKR/X int
ACLKR/X ext in/out
UNIT
ns
10.995
ns
(3)
ACLKR/X ext in/out
Hold time, AFSR/X input valid after ACLKR/X
MIN
0.5R - 2.5
4
-1
ns
1.6
10.995
ns
4
-1
ns
1.6
ADVANCE INFORMATION
(1) ACLKR internal: ACLKRCTL.CLKRM=1, PDIR.ACLKR = 1
ACLKR external input: ACLKRCTL.CLKRM=0, PDIR.ACLKR=0
ACLKR external output: ACLKRCTL.CLKRM=0, PDIR.ACLKR=1
ACLKX internal: ACLKXCTL.CLKXM=1, PDIR.ACLKX = 1
ACLKX external input: ACLKXCTL.CLKXM=0, PDIR.ACLKX=0
ACLKX external output: ACLKXCTL.CLKXM=0, PDIR.ACLKX=1
(2) P = AHCLKR/X period in ns.
(3) R = ACLKR/X period in ns.
Specifications
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ASP2
ASP1
ASP2
MCASP[x]_ACLKR/X (Falling Edge Polarity)
MCASP[x]_AHCLKR/X (Rising Edge Polarity)
ASP4
ASP3
MCASP[x]_ACLKR/X (CLKRP = CLKXP = 0)
MCASP[x]_ACLKR/X (CLKRP = CLKXP = 1)
ASP4
(A)
(B)
ASP6
ASP5
MCASP[x]_AFSR/X (Bit Width, 0 Bit Delay)
MCASP[x]_AFSR/X (Bit Width, 1 Bit Delay)
ADVANCE INFORMATION
MCASP[x]_AFSR/X (Bit Width, 2 Bit Delay)
MCASP[x]_AFSR/X (Slot Width, 0 Bit Delay)
MCASP[x]_AFSR/X (Slot Width, 1 Bit Delay)
MCASP[x]_AFSR/X (Slot Width, 2 Bit Delay)
ASP8
ASP7
MCASP[x]_AXR[x] (Data In/Receive)
A.
B.
A0 A1
A30 A31 B0 B1
B30 B31 C0 C1 C2 C3
For CLKRP = CLKXP = 0, the MCASP transmitter is configured for rising edge (to shift data out) and the MCASP
receiver is configured for falling edge (to shift data in).
For CLKRP = CLKXP = 1, the MCASP transmitter is configured for falling edge (to shift data out) and the MCASP
receiver is configured for rising edge (to shift data in).
C31
Figure 5-62. MCASP Input Timing
(1) x in MCASP[x]_* is 0, 1 or 2
196
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Table 5-61 and Figure 5-63 present switching characteristics over recommended operating conditions for
MCASP0 to MCASP2.
Table 5-61. Switching Characteristics Over Recommended Operating Conditions for MCASP(1)
ASP9
PARAMETER
DESCRIPTION
tc(AHCLKRX)
Cycle time, AHCLKR/X
Mode
MIN
MAX
20
ns
0.5P - 2.5
ns
20
ns
0.5R - 2.5
ns
ASP10 tw(AHCLKRX)
Pulse duration, AHCLKR/X high or low
ASP11 tc(ACLKRX)
Cycle time, ACLKR/X
ASP12 tw(ACLKRX)
Pulse duration, ACLKR/X high or low
ASP13 td(ACLKRX-AFSRX)
Delay time, ACLKR/X transmit edge to AFSR/X
output valid
ACLKR/X int
0
ACLKR/X ext in/out
2
14
ASP14 td(ACLKX-AXR)
Delay time, ACLKX transmit edge to AXR output
valid
ACLKR/X int
0
6.5
ACLKR/X ext in/out
2
14
Disable time, ACLKX transmit edge to AXR output
high impedance
ACLKR/X int
0
6.5
ACLKR/X ext in/out
2
14
ASP15 tdis(ACLKX-AXR)
UNIT
(2)
(3)
6.5
ns
ns
ns
ADVANCE INFORMATION
NO.
(1) ACLKR internal: ACLKRCTL.CLKRM=1, PDIR.ACLKR = 1
ACLKR external input: ACLKRCTL.CLKRM=0, PDIR.ACLKR=0
ACLKR external output: ACLKRCTL.CLKRM=0, PDIR.ACLKR=1
ACLKX internal: ACLKXCTL.CLKXM=1, PDIR.ACLKX = 1
ACLKX external input: ACLKXCTL.CLKXM=0, PDIR.ACLKX=0
ACLKX external output: ACLKXCTL.CLKXM=0, PDIR.ACLKX=1
(2) P = AHCLKR/X period in ns.
(3) R = ACLKR/X period in ns.
Specifications
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ASP9
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ASP10
ASP10
MCASP[x]_ACLKR/X (Falling Edge Polarity)
MCASP[x]_AHCLKR/X (Rising Edge Polarity)
ASP12
ASP11
MCASP[x]_ACLKR/X (CLKRP = CLKXP = 1)
MCASP[x]_ACLKR/X (CLKRP = CLKXP = 0)
ASP12
(A)
(B)
ASP13
ASP13
ASP13
ASP13
MCASP[x]_AFSR/X (Bit Width, 0 Bit Delay)
MCASP[x]_AFSR/X (Bit Width, 1 Bit Delay)
ADVANCE INFORMATION
MCASP[x]_AFSR/X (Bit Width, 2 Bit Delay)
MCASP[x]_AFSR/X (Slot Width, 0 Bit Delay)
ASP13
ASP13
ASP13
MCASP[x]_AFSR/X (Slot Width, 1 Bit Delay)
MCASP[x]_AFSR/X (Slot Width, 2 Bit Delay)
MCASP[x]_AXR[x] (Data Out/Transmit)
ASP14
ASP15
A.
B.
A0 A1
A30 A31 B0 B1
B30 B31 C0 C1 C2 C3
For CLKRP = CLKXP = 1, the MCASP transmitter is configured for falling edge (to shift data out) and the MCASP
receiver is configured for rising edge (to shift data in).
For CLKRP = CLKXP = 0, the MCASP transmitter is configured for rising edge (to shift data out) and the MCASP
receiver is configured for falling edge (to shift data in).
C31
Figure 5-63. MCASP Output Timing
(1) x in MCASP[x]_* is 0, 1 or 2
For more information, see section Multichannel Audio Serial Port (MCASP) in the device TRM.
5.9.5.15 MCSPI
For more details about features and additional description information on the device Serial Port Interface,
see the corresponding sections within Section 4.3, Signal Descriptions and Section 6, Detailed
Description.
For more information, see section Multichannel Serial Peripheral Interface (MCSPI) in the device TRM.
5.9.5.15.1 SPI—Master Mode
Table 5-62, Figure 5-64 and Figure 5-65 present Timing Requirements for SPI - Master Mode.
198
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Table 5-62. Timing Requirements for SPI - Master Mode (1)(8)
NO.
PARAMETER
DESCRIPTION
SM1
tc(SPICLK)
Cycle time, SPI_CLK (1) (2)
MODE
SM2
tw(SPICLKL)
Typical Pulse duration, SPI_CLK low
SM3
tw(SPICLKH)
Typical Pulse duration, SPI_CLK high
SM4
tsu(MISO-SPICLK)
Setup time, SPI_D[x] valid before SPI_CLK active edge
(1)
(1)
MIN
MAX
UNIT
20.8(3)
ns
-1 +
0.5P (4)
ns
-1 +
0.5P (4)
ns
2
ns
(1)
SM5
th(SPICLK-MISO)
Hold time, SPI_D[x] valid after SPI_CLK active edge (1)
3
SM6
td(SPICLK-SIMO)
Delay time, SPI_CLK active edge to SPI_D[x] transition
-3
ns
2
ns
(1)
SM7
tsk(CS-SIMO)
Delay time, SPI_CS[x] active to SPI_D[x] transition
SM8
td(SPICLK-CS)
Delay time, SPI_CS[x] active to SPI_CLK first edge
Master_PHA0_POL0; -4 + B
Master_PHA0_POL1;(
5
ns
(6)
ns
(7)
ns
(7)
ns
(6)
ns
5)
Master_PHA1_POL0; -4 + A
Master_PHA1_POL1;(
SM9
td(SPICLK-CS)
Delay time, SPI_CLK last edge to SPI_CS[x] inactive
Master_PHA0_POL0; -4 + A
Master_PHA0_POL1;(
5)
Master_PHA1_POL0; -4 + B
Master_PHA1_POL1;
(5)
(1) This timing applies to all configurations regardless of SPI_CLK polarity and which clock edges are being used to drive output data and
capture input data
(2) Related to the SPI_CLK maximum frequency
(3) 20 ns cycle time = 50 MHz
(4) P = SPICLK period
(5) SPI_CLK phase is programmable with the PHA bit of the SPI_CH(i)CONF register
(6) B = (TCS + .5) * TSPICLKREF, where TCS is a bit field of the SPI_CH(i)CONF register and Fratio = Even >= 2.
(7) When P = 20.8 ns, A = (TCS + 1) * TSPICLKREF, where TCS is a bit field of the SPI_CH(i)CONF register.
When P > 20.8 ns, A = (TCS + 0.5) * Fratio * TSPICLKREF, where TCS is a bit field of the SPI_CH(i)CONF register.
(8) The IO timings provided in this section are applicable for all combinations of signals for SPI1 and SPI2. However, the timings are only
valid for SPI3 and SPI4 if signals within a single IOSET are used. The IOSETs are defined in the following tables.
Specifications
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PHA=0
EPOL=1
SPI_CS[x] (OUT)
SM1
SM3
SM8
SPI_SCLK (OUT)
SM2
SM9
POL=0
SM1
SM3
SM2
POL=1
SPI_SCLK (OUT)
SM5
SM5
SPI_D[x] (IN)
SM4
SM4
Bit n-1
Bit n-2
Bit n-3
Bit n-4
Bit 0
ADVANCE INFORMATION
PHA=1
EPOL=1
SPI_CS[x] (OUT)
SM2
SM1
SM8
SPI_SCLK (OUT)
SM3
SM9
POL=0
SM1
SM2
SM3
POL=1
SPI_SCLK (OUT)
SM5
SM4
SM4
SPI_D[x] (IN)
Bit n-1
SM5
Bit n-2
Bit n-3
Bit 1
Bit 0
SPRSP08_TIMING_McSPI_02
Figure 5-64. SPI Master Mode Receive Timing
200
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PHA=0
EPOL=1
SPI_CS[x] (OUT)
SM1
SM3
SM8
SPI_SCLK (OUT)
SM2
SM9
POL=0
SM1
SM3
SM2
POL=1
SPI_SCLK (OUT)
SM6
Bit n-1
SPI_D[x] (OUT)
SM6
Bit n-2
Bit n-3
Bit n-4
Bit 0
PHA=1
EPOL=1
SPI_CS[x] (OUT)
SM1
SM2
SM8
SPI_SCLK (OUT)
SM3
SM9
POL=0
SM1
SM2
SM3
POL=1
SPI_SCLK (OUT)
SM6
SM6
Bit n-1
SPI_D[x] (OUT)
Bit n-2
SM6
Bit n-3
SM6
Bit 1
Bit0
SPRSP08_TIMING_McSPI_01
Figure 5-65. SPI Master Mode Transmit Timing
5.9.5.15.2 MCSPI—Slave Mode
Table 5-63, Figure 5-66, and Figure 5-67 present Timing Requirements for SPI - Slave Mode.
Table 5-63. Timing Requirements for SPI - Slave Mode
NO.
PARAMETER
DESCRIPTION
MODE
MIN
MAX
UNIT
SS1
tc(SPICLK)
Cycle time, SPI_CLK
20.8
ns
SS2
tw(SPICLKL)
Typical Pulse duration, SPI_CLK low
0.45P(2)
ns
SS3
tw(SPICLKH)
Typical Pulse duration, SPI_CLK high
0.45P(2)
ns
SS4
tsu(SIMO-SPICLK)
Setup time, SPI_D[x] valid before SPI_CLK active edge
5
ns
SS5
th(SPICLK-SIMO)
Hold time, SPI_D[x] valid after SPI_CLK active edge
5
SS6
td(SPICLK-SOMI)
Delay time, SPI_CLK active edge to mcspi_somi
transition
2
SS7
tsk(CS-SOMI)
Delay time, SPI_CS[x] active edge to mcspi_somi
transition
SS8
tsu(CS-SPICLK)
SS9
th(SPICLK-CS)
ns
5
ns
20.95
ns
Setup time, SPI_CS[x] valid before SPI_CLK first edge
5
ns
Hold time, SPI_CS[x] valid after SPI_CLK last edge
5
ns
Specifications
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SM7
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(1) This timing applies to all configurations regardless of SPI_CLK polarity and which clock edges are used to drive output data and capture
input data.
(2) P = SPICLK period.
(3) PHA = 0; SPI_CLK phase is programmable with the PHA bit of the SPI_CH(i)CONF register.
PHA=0
EPOL=1
SPI_CS[x] (IN)
SS1
SS2
SS8
SPI_SCLK (IN)
SS3
SS9
POL=0
SS1
SS2
SS3
POL=1
SPI_SCLK (IN)
SS5
SS4
ADVANCE INFORMATION
SS4
SS5
Bit n-1
SPI_D[x] (IN)
Bit n-2
Bit n-3
Bit n-4
Bit 0
PHA=1
EPOL=1
SPI_CS[x] (IN)
SS1
SS2
SS8
SPI_SCLK (IN)
SS3
SS9
POL=0
SS1
SS3
SS2
POL=1
SPI_SCLK (IN)
SS4
SS5
SPI_D[x] (IN)
SS4
SS5
Bit n-1
Bit n-2
Bit n-3
Bit 1
Bit 0
SPRSP08_TIMING_McSPI_04
Figure 5-66. SPI Slave Mode Receive Timing
202
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PHA=0
EPOL=1
SPI_CS[x] (IN)
SS1
SS2
SS8
SPI_SCLK (IN)
SS3
SS9
POL=0
SS1
SS2
SS3
POL=1
SPI_SCLK (IN)
SS7
SS6
Bit n-1
SPI_D[x] (OUT)
SS6
Bit n-2
Bit n-3
Bit n-4
Bit 0
EPOL=1
SPI_CS[x] (IN)
SS1
SS2
SS8
SPI_SCLK (IN)
SS3
SS9
POL=0
SS1
SS3
SS2
POL=1
SPI_SCLK (IN)
SS6
SS6
Bit n-1
SPI_D[x] (OUT)
Bit n-2
SS6
Bit n-3
SS6
Bit 1
Bit 0
SPRSP08_TIMING_McSPI_03
Figure 5-67. SPI Slave Mode Transmit Timing
Specifications
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PHA=1
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5.9.5.16 eMMC/SD/SDIO
NOTE
The I/O Timings provided in this section are valid only when the corresponding DLL Delays
are configured for some MMC usage modes, as described in Table 5-76.
NOTE
The MMCi (i = 0 to 1) controller is also referred to as MMCi.
For more details about features and additional description information on the device Multi Media Card, see
the corresponding sections within Section 4.3, Signal Descriptions and Section 6, Detailed Description.
5.9.5.16.1 MMCi — eMMC/SD/SDIO Card Interface
ADVANCE INFORMATION
MMCi interface is compliant with the SD Standard v3.01 as well as JC64 eMMC standard v4.5 and it
supports the following SD Card and eMMC applications:
• Default speed
• High speed
• UHS-I SDR12
• UHS-I SDR25
• UHS-I SDR50
• UHS-I SDR104 / HS200
• UHS-I DDR50
NOTE
For more information, see section Multimedia Card/Secure Digital (MMC/SD) Interface in the
device TRM.
5.9.5.16.1.1 Default speed Mode
Table 5-64 and Table 5-65 present Timing requirements and Switching characteristics for MMCi - Default
Speed in receiver and transmitter mode (see Figure 5-68 and Figure 5-69)
Table 5-64. Timing Requirements for MMCi - Default Speed Mode
PARAMETER
DESCRIPTION
MIN
DSSD5
NO.
tsu(cmdV-clkH)
Setup time, MMCi_CMD valid before MMCi_CLK rising clock edge
1.65
MAX
UNIT
ns
DSSD6
th(clkH-cmdV)
Hold time, MMCi_CMD valid after MMCi_CLK rising clock edge
19.17
ns
DSSD7
tsu(dV-clkH)
Setup time, MMCi_DAT[j:0] valid before MMCi_CLK rising clock edge
1.65
ns
DSSD8
th(clkH-dV)
Hold time, MMCi_DAT[j:0] valid after MMCi_CLK rising clock edge
19.17
ns
(1) j in [j:0] is equal to 7 (for MMC0), or 3 (for MMC1).
Table 5-65. Switching Characteristics for MMCi - Default Speed Mode
NO.
PARAMETER
DESCRIPTION
DSSD0
fop(clk)
Operating frequency, MMCi_CLK
DSSD1
tw(clkH)
Pulse duration, MMCi_CLK high
18.7
ns
DSSD2
tw(clkL)
Pulse duration, MMCi_CLK low
18.7
ns
DSSD3
td(clkL-cmdV)
Delay time, MMCi_CLK falling clock edge to MMCi_CMD transition
- 13.6
13.6
ns
DSSD4
td(clkL-dV)
Delay time, MMCi_CLK falling clock edge to MMCi_DAT[j:0] transition
- 13.6
13.6
ns
204
MIN
Specifications
MAX
UNIT
25
MHz
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(1) j in [j:0] is equal to 7 (for MMC0), or 3 (for MMC1).
Figure 5-69. eMMC/SD/SDIO in - Default Speed - Transmitter Mode
5.9.5.16.1.2 High speed Mode
Table 5-66 and Table 5-67 present Timing requirements and Switching characteristics for MMCi - High
Speed in receiver and transmitter mode (see Figure 5-70 and Figure 5-71).
Table 5-66. Timing Requirements for MMCi - High Speed Mode
PARAMETER
DESCRIPTION
MIN
HSSD3
NO.
tsu(cmdV-clkH)
Setup time, MMCi_CMD valid before MMCi_CLK rising clock edge
2.15
MAX
UNIT
ns
HSSD4
th(clkH-cmdV)
Hold time, MMCi_CMD valid after MMCi_CLK rising clock edge
2.67
ns
HSSD7
tsu(dV-clkH)
Setup time, MMCi_DAT[j:0] valid before MMCi_CLK rising clock edge
2.15
ns
HSSD8
th(clkH-dV)
Hold time, MMCi_DAT[j:0] valid after MMCi_CLK rising clock edge
2.67
ns
(1) j in [j:0] is equal to 7 (for MMC0), or 3 (for MMC1).
Table 5-67. Switching Characteristics for MMCi - High Speed Mode
PARAMETER
DESCRIPTION
HSSD1
NO.
fop(clk)
Operating frequency, MMCi_CLK
MIN
MAX
UNIT
50
HSSD2H
tw(clkH)
Pulse duration, MMCi_CLK high
9.2
MHz
ns
HSSD2L
tw(clkL)
Pulse duration, MMCi_CLK low
9.2
ns
HSSD5
td(clkL-cmdV)
Delay time, MMCi_CLK falling clock edge to MMCi_CMD transition
-6.1
3.1
ns
HSSD6
td(clkL-dV)
Delay time, MMCi_CLK falling clock edge to MMCi_DAT[j:0]
transition
-6.1
3.1
ns
Specifications
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Figure 5-68. eMMC/SD/SDIO in - Default Speed - Receiver Mode
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(1) j in [j:0] is equal to 7 (for MMC0), or 3 (for MMC1).
Figure 5-70. eMMC/SD/SDIO in - High Speed - Receiver Mode
ADVANCE INFORMATION
Figure 5-71. eMMC/SD/SDIO in - High Speed - Transmitter Mode
5.9.5.16.1.3 UHS-I SDR12 Mode
Table 5-68 and Table 5-69 present Timing requirements and Switching characteristics for MMCi - SDR12
in receiver and transmitter mode (see Figure 5-72 and Figure 5-73).
Table 5-68. Timing Requirements for MMCi - SDR12 Mode
PARAMETER
DESCRIPTION
MIN
SDR125
NO.
tsu(cmdV-clkH)
Setup time, MMCi_CMD valid before MMCi_CLK rising clock edge
9.96
MAX
UNIT
ns
SDR126
th(clkH-cmdV)
Hold time, MMCi_CMD valid after MMCi_CLK rising clock edge
1.67
ns
SDR127
tsu(dV-clkH)
Setup time, MMCi_DAT[j:0] valid before MMCi_CLK rising clock
edge
9.96
ns
SDR128
th(clkH-dV)
Hold time, MMCi_DAT[j:0] valid after MMCi_CLK rising clock edge
1.67
ns
(1) j in [j:0] is equal to 7 (for MMC0), or 3 (for MMC1).
Table 5-69. Switching Characteristics for MMCi - SDR12 Mode
PARAMETER
DESCRIPTION
SDR120
NO.
fop(clk)
Operating frequency, MMCi_CLK
SDR121
tw(clkH)
Pulse duration, MMCi_CLK high
SDR122
tw(clkL)
Pulse duration, MMCi_CLK low
SDR123
td(clkL-cmdV)
Delay time, MMCi_CLK falling clock edge to MMCi_CMD transition
-13.6
13.6
ns
SDR124
td(clkL-dV)
Delay time, MMCi_CLK falling clock edge to MMCi_DAT[j:0]
transition
-13.6
13.6
ns
206
MIN
Specifications
MAX
UNIT
25
MHz
18.7
ns
18.7
ns
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(1) j in [j:0] is equal to 7 (for MMC0), or 3 (for MMC1).
Figure 5-73. eMMC/SD/SDIO in - High Speed SDR12 - Transmitter Mode
5.9.5.16.1.4 UHS-I SDR25 Mode
Table 5-70 and Table 5-71 present Timing requirements and Switching characteristics for MMCi - SDR25
in receiver and transmitter mode (see Figure 5-74 and Figure 5-75).
Table 5-70. Timing Requirements for MMCi - SDR25 Mode
NO.
PARAMETER
DESCRIPTION
MIN
MAX
UNIT
SDR253
tsu(cmdV-clkH)
Setup time, MMCi_CMD valid before MMCi_CLK rising clock edge
2.15
ns
SDR254
th(clkH-cmdV)
Hold time, MMCi_CMD valid after MMCi_CLK rising clock edge
1.67
ns
SDR257
tsu(dV-clkH)
Setup time, MMCi_DAT[j:0] valid before MMCi_CLK rising clock
edge
2.15
ns
SDR258
th(clkH-dV)
Hold time, MMCi_DAT[j:0] valid after MMCi_CLK rising clock edge
1.67
ns
(1) j in [j:0] is equal to 7 (for MMC0), or 3 (for MMC1).
Table 5-71. Switching Characteristics for MMCi - SDR25 Mode
PARAMETER
DESCRIPTION
SDR251
NO.
fop(clk)
Operating frequency, MMCi_CLK
MIN
MAX
UNIT
50
MHz
SDR252H
tw(clkH)
Pulse duration, MMCi_CLK high
9.2
SDR252L
tw(clkL)
Pulse duration, MMCi_CLK low
9.2
SDR255
td(clkL-cmdV)
Delay time, MMCi_CLK falling clock edge to MMCi_CMD transition
-6.1
3.1
ns
SDR256
td(clkL-dV)
Delay time, MMCi_CLK falling clock edge to MMCi_DAT[j:0]
transition
-6.1
3.1
ns
ns
ns
Specifications
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Figure 5-72. eMMC/SD/SDIO in - High Speed SDR12 - Receiver Mode
DRA80M
SPRSP31E – APRIL 2018 – REVISED JUNE 2019
www.ti.com
(1) j in [j:0] is equal to 7 (for MMC0), or 3 (for MMC1).
Figure 5-74. eMMC/SD/SDIO in - High Speed SDR25 - Receiver Mode
ADVANCE INFORMATION
Figure 5-75. eMMC/SD/SDIO in - High Speed SDR25 - Transmitter Mode
5.9.5.16.1.5 UHS-I SDR50 Mode
and Table 5-72 present Timing requirements and Switching characteristics for MMCi - SDR50 in receiver
and transmitter mode (see and Figure 5-76).
Table 5-72. Switching Characteristics for MMCi - SDR50 Mode
NO.
PARAMETER
DESCRIPTION
MIN
MAX
UNIT
100
MHz
SDR501
fop(clk)
Operating frequency, MMCi_CLK
SDR502H
tw(clkH)
Pulse duration, MMCi_CLK high
4.45
ns
SDR502L
tw(clkL)
Pulse duration, MMCi_CLK low
4.45
ns
SDR505
td(clkL-cmdV)
Delay time, MMCi_CLK rising clock edge to MMCi_CMD transition
1.2
6.35
ns
SDR506
td(clkL-dV)
Delay time, MMCi_CLK rising clock edge to MMCi_DAT[j:0]
transition
1.2
6.35
ns
(1) j in [j:0] is equal to 7 (for MMC0), or 3 (for MMC1).
Figure 5-76. eMMC/SD/SDIO in - High Speed SDR50 - Transmitter Mode
208
Specifications
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5.9.5.16.1.6 UHS-I SDR104 / HS200 Mode
Table 5-73 presents Timing requirements and Switching characteristics for MMCi - SDR104 in receiver
and transmitter mode (see and Figure 5-77)
Table 5-73. Switching Characteristics for MMCi - SDR104 / HS200 Mode
PARAMETER
DESCRIPTION
SDR1041
NO.
fop(clk)
Operating frequency, MMCi_CLK
MIN
MAX
UNIT
200
SDR1042H
tw(clkH)
Pulse duration, MMCi_CLK high
2.08
MHz
ns
SDR1042L
tw(clkL)
Pulse duration, MMCi_CLK low
2.08
ns
SDR1045
td(clkL-cmdV)
Delay time, MMCi_CLK rising clock edge to MMCi_CMD transition
1.12
3.16
ns
SDR1046
td(clkL-dV)
Delay time, MMCi_CLK rising clock edge to MMCi_DAT[j:0]
transition
1.12
3.16
ns
Figure 5-77. eMMC/SD/SDIO in - High Speed SDR104 / HS200 - Transmitter Mode
5.9.5.16.1.7 UHS-I DDR50 Mode
Table 5-74 and Table 5-75 present Timing requirements and Switching characteristics for MMCi - DDR50
in receiver and transmitter mode (see Figure 5-78 and Figure 5-79).
Table 5-74. Timing Requirements for MMCi - DDR50 Mode
PARAMETER
DESCRIPTION
MIN
DDR505
NO.
tsu(cmdV-clk)
Setup time, MMCi_CMD valid before MMCi_CLK rising clock edge
3.12
MAX
UNIT
ns
DDR506
th(clk-cmdV)
Hold time, MMCi_CMD valid after MMCi_CLK rising clock edge
1.91
ns
DDR507
tsu(dV-clk)
Setup time, MMCi_DAT[j:0] valid before MMCi_CLK transition
-0.18
ns
DDR508
th(clk-dV)
Hold time, MMCi_DAT[j:0] valid after MMCi_CLK transition
1.67
ns
(1) j in [j:0] is equal to 7 (for MMC0), or 3 (for MMC1).
Table 5-75. Switching Characteristics for MMCi - DDR50 Mode
NO.
PARAMETER
DESCRIPTION
MIN
MAX
UNIT
DDR500
fop(clk)
Operating frequency, MMCi_CLK
DDR501
tw(clkH)
Pulse duration, MMCi_CLK high
9.2
50
MHz
DDR502
tw(clkL)
Pulse duration, MMCi_CLK low
9.2
DDR503
td(clk-cmdV)
Delay time, MMCi_CLK rising clock edge to MMCi_CMD transition
3.4
13.1
ns
DDR504
td(clk-dV)
Delay time, MMCi_CLK transition to MMCi_DAT[j:0] transition
2.9
6.1
ns
ns
ns
Specifications
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(1) j in [j:0] is equal to 7 (for MMC0), or 3 (for MMC1).
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(1) j in [j:0] is equal to 7 (for MMC0), or 3 (for MMC1).
Figure 5-78. eMMC/SD/SDIO - High Speed SD - DDR - Data/Command Receive
ADVANCE INFORMATION
Figure 5-79. eMMC/SD/SDIO - High Speed SD - DDR - Data/Command Transmit
210
Specifications
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Table 5-76, shows the required DLL software configuration settings for MMC timing modes.
Table 5-76. MMC DLL Delay Mapping for All Timing Modes
DESCRIPTION
DELAY VALUE
MMCSDn_PHY_CTRL_
4_REG[15:12]
OTAPDLYSEL
DELAY ENABLE
MMCSDn_PHY_CTRL_
4_REG[20]
OTAPDLYENA
DLL REFERENCE
FREQUENCY
MMCSDn_PHY_CTRL_
5_REG[9] SEL100
DLL REFERENCE
FREQUENCY
MMCSDn_PHY_CTRL_
5_REG[9] SEL50
STROBE DELAY
MMCSD0_SS_PHY_CT
RL_4_REG [27:24]
STRBSEL
MMC Default
Speed
Either 8-bit or 4-bit PHY operating
in DS mode
0x0
0x0
0x0
0x0
0x0
MMC High Speed
Either 8-bit or 4-bit PHY operating
in HS mode
0x0
0x0
0x0
0x0
0x0
MMC HS-DDR
Either 8-bit or 4-bit PHY operating
in HS-DDR mode
0x0
0x0
0x0
0x0
0x0
MMC SDR50
Either 8-bit or 4-bit PHY operating
in SDR50
0x8
0x1
0x1
0x0
0x0
MMC0 DDR50
8-bit PHY operating in DDR50
mode
0x5
0x1
0x0
0x1
0x0
MMC1 DDR50
4-bit PHY operating in DDR50
mode
0x4
0x1
0x0
0x1
0x0
MMC SDR104
Either 8-bit or 4-bit PHY operating
in SDR104 mode
0x7
0x1
0x0
0x0
0x0
MMC HS200
Either 8-bit or 4-bit PHY operating
in HS200 mode
0x5
0x1
0x0
0x0
0x0
MMC HS400
8-bit PHY operating in HS400 mode
0x0
0x1
0x0
0x0
0xF
Specifications
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MODE
211
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For more information, see section Multimedia Card/Secure Digital (MMC/SD) Interface in the device TRM.
5.9.5.17 NAVSS
Table 5-77, Table 5-78, Figure 5-80, and Figure 5-81 present timing requirement and switching
characteristics of the CPTS interface.
Table 5-77. Timing Requirements for CPTS Input
NO.
PARAMETER
DESCRIPTION
MIN
MAX
(1)
UNIT
T1
tw(HWTSPUSHH)
HWTSPUSH Pulse duration, high
6 + 12P
T2
tw(HWTSPUSHL)
HWTSPUSH pulse duration, low
6 + 12P(1)
T3
tc(RFT_CLK)
RFT_CLK cycle time
T4
tw(RFT_CLKH)
RFT_CLK pulse duration, high
0.45 ×
tc(RFT_CLK)
ns
T5
tw(RFT_CLKL)
RFT_CLK pulse duration, low
0.45 ×
tc(RFT_CLK)
ns
5
ns
ns
8
ns
(1) P = functional clock period in ns.
ADVANCE INFORMATION
T1
T2
CPTS_HWTSPUSH
T3
T4
T5
CPTS_RFT_CLK
Figure 5-80. CPTS Input Timing
Table 5-78. Switching Characteristics for CPTS Output
NO.
212
PARAMETER
DESCRIPTION
MIN
MAX
UNIT
T6
tw(TS_COMPH)
NAVSS-CPTS TS_COMP, high
-6+36P
(1)
T7
tw(TS_COMPL)
NAVSS-CPTS TS_COMP, low
-6+36P
(1)
ns
T8
tw(TS_COMPH)
CPSW-CPTS TS_COMP, high
-6+36P
(1)
ns
T9
tw(TS_COMPL)
CPSW-CPTS TS_COMP, low
-6+36P
(1)
ns
ns
ns
T10
tw(TS_SYNCH)
NAVSS-CPTS TS_SYNC, high
-6+36P
(1)
T11
tw(TS_SYNCL)
NAVSS-CPTS TS_SYNC, low
-6+36P
(1)
ns
T12
tw(TS_SYNCH)
CPSW-CPTS TS_SYNC, high
-6+36P
(1)
ns
ns
T13
tw(TS_SYNCL)
CPSW-CPTS TS_SYNC, low
-6+36P
(1)
T14
tw(SYNC_OUTH)
TS_SYNC sourcing SYNCn_OUT, high
-6+36P
(1)
ns
T15
tw(SYNC_OUTL)
TS_SYNC sourcing SYNCn_OUT, low
-6+36P
(1)
ns
(1)
ns
ns
T16
tw(SYNC_OUTH)
GENF sourcing SYNCn_OUT, high
-6+5P
T17
tw(SYNC_OUTL)
GENF sourcing SYNCn_OUT, low
-6+5P (1)
Specifications
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(1) P = functional clock period in ns.
T6
T7
T8
T9
T10
T11
CPTS_TS_COMP
CPTS_TS_SYNC
CPTS_SYNC_OUT
Figure 5-81. CPTS Output Switching Characteristics
ADVANCE INFORMATION
For more information, see section Navigator Subsystem (NAVSS) in the device TRM.
Specifications
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5.9.5.18 OSPI
For more details about features and additional description information on the device Octal Serial
Peripheral Interface, see the corresponding sections within Section 4.3, Signal Descriptions and Section 6,
Detailed Description.
5.9.5.18.1 OSPI with Data Training
Table 5-79. OSPI Switching Characteristics - Data Training
PARAMETER
DESCRIPTION
MODE
MIN
tc(CLK)
Cycle time, CLK
DDR, 1.8V
6.02
ns
DDR, 3.3V
7.52
ns
SDR, 1.8V
5.00
ns
SDR, 3.3V
7.52
ns
tc(CLK)
Cycle time, CLK
MAX
UNIT
5.9.5.18.2 OSPI without Data Training
ADVANCE INFORMATION
NOTE
The I/O Timings provided in this section are only applicable when data training is not
implemented. Additionally, the I/O Timings are valid only for some OSPI usage modes when
the corresponding DLL Delays are configured as described in Table 5-84 found in this
section. These I\O Timings also assume a matching skew of < 60 ps.
Table 5-80, Table 5-81, Figure 5-82, and Figure 5-83 present switching characteristics for OSPI DDR and
SDR Mode.
Table 5-80. OSPI Switching Characteristics - DDR Mode (1)
NO.
PARAMETER
DESCRIPTION
MODE
MIN
O1
tc(CLK)
Cycle time, CLK
1.8V
19
MAX
UNIT
ns
3.3V
19
ns
O2
tw(CLKL)
Pulse duration, CLK low
-0.3+0.475*P
ns
O3
tw(CLKH)
Pulse duration, CLK high
-0.3+0.475*P
ns
O4
td(CLK-CSn)
Delay time, CLK rising edge to CSn active edge 1.8V, OSPI0 DDR TX; -7.7-0.475 * 0-0.475 * P –
1.8V, OSPI1 DDR TX P – 0.975 * N 0.975 * N * R
(3) (4) (5)
* R (3) (4) (5)
ns
3.3V, OSPI0 DDR TX;
-8-0.475 *
0-0.475 * P –
3.3V, OSPI1 DDR TX P – 0.975 * N 0.975 * N * R
(3) (4) (5)
(3) (4) (5)
*R
ns
1.8V, OSPI0 DDR TX; -7.7+0.475 *
1.8V, OSPI1 DDR TX P + 0.975 * N
* R (3) (4) (5)
0+0.475 * P
+ 0.975 * N *
R (3) (4) (5)
ns
3.3V, OSPI0 DDR TX; -8+0.475 * P
3.3V, OSPI1 DDR TX + 0.975 * N *
R (3) (4) (5)
0+0.475 * P
+ 0.975 * N *
R (3) (4) (5)
ns
O5
O6
td(CLK-CSn)
td(CLK-D)
(2)
(2)
Delay time, CLK rising edge to CSn inactive
edge
Delay time, CLK active edge to D[i:0] transition
1.8V, OSPI0 DDR TX;
1.8V, OSPI1 DDR TX
-7.7
-1.56
ns
3.3V, OSPI0 DDR TX;
3.3V, OSPI1 DDR TX
-7.7
-1.56
ns
(1) i in [i:0] = 7 for OSPI0, i in [i:0] = 3 for OSPI1
(2) P = CLK cycle time
(3) P = SCLK period
(4) N = OSPI_DEV_DELAY_REG[D_INIT_FLD]
(5) R = refclk
214
Specifications
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OSPI_CSn
O4
O5
O3
OSPI_CLK
O6
O6
O2
O1
OSPI_D[i:0]
OSPI_TIMING_01
Figure 5-82. OSPI Switching Characteristics - DDR
Table 5-81. OSPI Switching Characteristics - SDR Mode (1)
PARAMETER
DESCRIPTION
MODE
MIN
O7
tc(CLK)
Cycle time, CLK
1.8V
7
ns
7.52
ns
O8
tw(CLKL)
Pulse duration, CLK low
-0.3+0.475*P
ns
O9
tw(CLKH)
Pulse duration, CLK high
-0.3+0.475*P
ns
O10
td(CLK-CSn)
Delay time, CLK rising edge to CSn active edge
1.8V
-1-0.475 *
1-0.475 * P –
P – 0.975 * N 0.975 * N * R
(3) (4) (5)
* R (3) (4) (5)
ns
3.3V
-1-0.475 *
1-0.475 * P –
P – 0.975 * N 0.975 * N * R
(3) (4) (5)
(3) (4) (5)
*R
ns
1.8V
-1+0.475 * P
+ 0.975 * N *
R (3) (4) (5)
1+0.475 * P
+ 0.975 * N *
R (3) (4) (5)
ns
3.3V
-1+0.475 * P
+ 0.975 * N *
R (3) (4) (5)
1+0.475 * P
+ 0.975 * N *
R (3) (4) (5)
ns
1.8V
-1.15
1.25
ns
3.3V
-1.33
1.51
ns
3.3V
O11
O12
td(CLK-CSn)
td(CLK-D)
MAX
(2)
(2)
Delay time, CLK rising edge to CSn inactive
edge
Delay time, CLK active edge to D[i:0] transition
UNIT
ADVANCE INFORMATION
NO.
(1) i in [i:0] = 7 for OSPI0, i in [i:0] = 3 for OSPI1
(2) P = CLK cycle time
(3) P = SCLK period
(4) N = OSPI_DEV_DELAY_REG[D_INIT_FLD]
(5) R = refclk
Specifications
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OSPI_CSn
O10
O9
OSPI_CLK
O11
O7
O8
O12
OSPI_D[i:0]
OSPI_TIMING_02
Figure 5-83. OSPI Switching Characteristics - SDR
Table 5-82, Table 5-83, Figure 5-84, Figure 5-85, Figure 5-86, and Figure 5-87 presents timing
requirements for OSPI DDR and SDR Mode.
ADVANCE INFORMATION
Table 5-82. OSPI Timing Requirements - DDR Mode (1)
NO.
PARAMETE
R
DESCRIPTION
O13
tsu(D-CLK)
Setup time, D[i:0] valid before active CLK edge
O14
O15
O16
O17
O18
216
th(CLK-D)
tsu(D-LBCLK)
th(LBCLK-D)
tsu(D-DQS)
th(DQS-D)
Hold time, D[i:0] valid after active CLK edge
Setup time, D[i:0] valid before active LBCLK (DQS)
edge
Hold time, D[i:0] valid after active LBCLK (DQS) edge
Setup time, DQS edge to D[i:0] transition
Hold time, DQS edge to D[i:0] transition
MODE
MIN
1.8V, No Loopback Clock;
1.8V, Internal Pad
Loopback Clock
5.23
ns
3.3V, No Loopback Clock;
3.3V, Internal Pad
Loopback Clock
6.19
ns
1.8V, No Loopback Clock;
1.8V, Internal Pad
Loopback Clock
1.84
ns
3.3V, No Loopback Clock;
3.3V, Internal Pad
Loopback Clock
2.34
ns
1.8V, External Board
Loopback Clock
0.52
ns
3.3V, External Board
Loopback Clock
1.97
ns
1.8V, External Board
Loopback Clock
1.8 (2)
ns
3.3V, External Board
Loopback Clock
2.2 (2)
ns
1.8V, OSPI0 DQS;
1.8V, OSPI1 DQS
-0.46
ns
3.3V, OSPI0 DQS;
3.3V, OSPI1 DQS
-0.66
ns
1.8V, OSPI0 DQS;
1.8V, OSPI1 DQS
3.59
ns
3.3V, OSPI0 DQS;
3.3V, OSPI1 DQS
7.92
ns
Specifications
MAX
UNIT
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(1) i in [i:0] = 7 for OSPI0, i in [i:0] = 3 for OSPI1
(2) This Hold time requirement is larger than the Hold time provided by a typical flash device. Therefore, the trace length between the SoC
and flash device must be sufficiently long enough to ensure that the Hold time is met at the SoC. The length of the SoC's external
loopback clock (OSPI_LBCLKO to OSPI_DQS) may need to be shortened to compensate.
OSPI_CLK
O13
O14
OSPI_D[i:0]
OSPI_TIMING_03
Figure 5-84. OSPI Timing Requirements - DDR, No Loopback Clock and Internal Pad Loopback Clock
OSPI_DQS
O16
OSPI_D[i:0]
OSPI_TIMING_04
Figure 5-85. OSPI Timing Requirements - DDR, External Loopback Clock and DQS
Table 5-83. OSPI Timing Requirements - SDR Mode (1)
NO.
PARAMETER
DESCRIPTION
O19
tsu(D-CLK)
Setup time, D[i:0] valid before active CLK edge
O20
O21
O22
th(CLK-D)
Hold time, D[i:0] valid after active CLK edge
tsu(D-LBCLK)
th(LBCLK-D)
Setup time, D[i:0] valid before active LBCLK
input (DQS) edge
Hold time, D[i:0] valid after active LBCLK input
(DQS) edge
MODE
MIN
1.8V, No Loopback Clock
-2.18
MAX
UNIT
ns
3.3V, No Loopback Clock
-1.7
ns
1.8V, No Loopback Clock
7.62
ns
3.3V, No Loopback Clock
8.1
ns
1.8V, External Board
Loopback Clock
-3.24
ns
3.3V, External Board
Loopback Clock
-2.72
ns
1.8V, External Board
Loopback Clock
3.81
ns
3.3V, External Board
Loopback Clock
4.33
ns
(1) i in [i:0] = 7 for OSPI0, i in [i:0] = 3 for OSPI1
OSPI_CLK
O19
O20
OSPI_D[i:0]
OSPI_TIMING_05
Figure 5-86. OSPI Timing Requirements - SDR, No Loopback Clock and Internal Pad Loopback Clock
Specifications
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ADVANCE INFORMATION
O15
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OSPI_DQS
O21
O22
OSPI_D[i:0]
OSPI_TIMING_06
Figure 5-87. OSPI Timing Requirements - SDR, External Loopback Clock
Table 5-84. OSPI DLL Delay Mapping for Timing Modes
ADVANCE INFORMATION
MODE
OSPI_PHY_CONFIGURATION_REG BITFIELD
1.8V, OSPI0 DDR TX
PHY_CONFIG_TX_DLL_DELAY_FLD
DELAY VALUE
0x45
1.8V, OSPI1 DDR TX
PHY_CONFIG_TX_DLL_DELAY_FLD
0x45
3.3V, OSPI0 DDR TX
PHY_CONFIG_TX_DLL_DELAY_FLD
0x46
3.3V, OSPI1 DDR TX
PHY_CONFIG_TX_DLL_DELAY_FLD
0x4C
1.8V, OSPI0 DQS
PHY_CONFIG_RX_DLL_DELAY_FLD
0x14
1.8V, OSPI1 DQS
PHY_CONFIG_RX_DLL_DELAY_FLD
0x16
3.3V, OSPI0 DQS
PHY_CONFIG_RX_DLL_DELAY_FLD
0x3A
3.3V, OSPI1 DQS
PHY_CONFIG_RX_DLL_DELAY_FLD
0x3E
All other modes
PHY_CONFIG_TX_DLL_DELAY_FLD,
PHY_CONFIG_RX_DLL_DELAY_FLD
0x0
For more information, see section Octal Serial Peripheral Interface (OSPI) in the device TRM.
5.9.5.19 OLDI
Table 5-85. OLDI Switching Characteristics
PARAME
DESCRIPTION
TER
NO.
MIN
TYP
MAX
UNIT
OLDI1
tt(LHTT)
Low-to-high transition time of LVDS differential signals:
OLDI0_CLKP/N, OLDI0_AxP/N
0.5
ns
OLDI2
tt(HLTT)
High-to-low transition time of LVDS differential signals:
OLDI0_CLKP/N, OLDI0_AxP/N
0.5
ns
OLDI3
tc(CLK)
Output pixel clock period (OLDI0_CLKP/N)
110.01
ns
OLDI4
tw(BIT)
Output bit width (OLDI0_AxP/N)
OLDI5
t(TPPx,
Output pulse positions normalized for each bit (OLDI0_AxP/N)
6.06
1
UI
7-1
UI
x=[6:0])
OLDI6
Δt(TPP)
Variation of pulse positions for each bit from their normalized center
(OLDI0_AxP/N)
OLDI7
tsk(TCCS)
Output channel to channel skew (OLDI0_CLKP/N, OLDI0_AxP/N)
OLDI8
tj(TJCC)
Output jitter cycle-to-cycle (OLDI0_CLKP/N, OLDI0_AxP/N)
OLDI9
tj(IJIT)
Total jitter tolerance (Includes data to clock skew, pulse position
variation from normalized edges (OLDI0_AxP/N)
218
Specifications
-0.06
0.06
110
0.028
UI
ps
0.035
UI
0.25
UI
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(1) x in OLDI0_AxP/N = [3:0]
(2) UI = tc(CLK) / 7
OLDI3
OLDI0_CLKP/N
bit 1
OLDI0_AxP/N
OLDI5
bit 4
bit 5
bit 3
bit 2
bit 0
bit 1
1UI
2UI
3UI
OLDI6
4UI
5UI
6UI
7UI
x in OLDI0_AxP/N = [3:0]
ADVANCE INFORMATION
(1)
tTPP0
tTPP1
tTPP2
tTPP3
tTPP4
tTPP5
tTPP6
bit 6
bit 0
Figure 5-88. OLDI Output Pulse Positions
Ideal Data
Bit Beginning
Ideal Data
Bit End
Sampling
Window
VTH
OLDI0_AxP/N
0V
DATA_TOL
DATA_TOL
Left
VTL
Right
Ideal Center Position (tBIT/2)
OLDI4
(1)
(2)
OLDI9 = DATA_TOL (Left+Right)
x in OLDI0_AxP/N = [3:0]
Figure 5-89. OLDI Data Output Jitter
80%
OLDI0_CLKP/N,
OLDI0_AxP/N
VSS = 2|VOD|
0V
20%
20%
OLDI1
(1)
+VOD
80%
OLDI2
-VOD
x in OLDI0_AxP/N = [3:0]
Figure 5-90. LVDS Output Transition Times
For more information, see section Display Subsystem (DSS) in the device TRM.
Specifications
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5.9.5.20 PCIE
The PCI-Express Subsystem is compliant with the PCI Express Base Specification, revision 3.1. Refer to
the specification for timing details.
For more details about features and additional description information on the device Peripheral
Component Interconnect Express, see the corresponding sections within Section 4.3, Signal Descriptions
and Section 6, Detailed Description.
For more information, see section Peripheral Component Interconnect Express (PCIe) Subsystem in the
device TRM.
5.9.5.21 PRU_ICSSG
The device has integrated three identical PRU_ICSSG subsystems (PRU_ICSSG0, PRU_ICSSG1 and
PRU_ICSSG2). The programmable nature of the PRU cores, along with their access to pins, events and
all device resources, provides flexibility in implementing fast real-time responses, specialized data
handling operations, custom peripheral interfaces, and in offloading tasks from the other processor cores
of the device.
ADVANCE INFORMATION
For more details about features and additional description information on the device Programmable RealTime Unit Subsystem and Industrial Communication Subsystem - Gigabit, see the corresponding sections
within Section 4.3, Signal Descriptions and Section 6, Detailed Description.
NOTE
The PRU_ICSSG_0 and PRU_ICSSG_1 support an internal wrapper multiplexing that
expands the device top-level multiplexing. Signal naming in this section must match the
internal wrapper multiplexing.
For more information, please refer to section Programmable Real-Time Unit Subsystem and
Industrial Communication Subsystem - Gigabit (PRU_ICSSG) in the device TRM.
5.9.5.21.1 Programmable Real-Time Unit (PRU_ICSSG PRU)
NOTE
The PRU_ICSSG PRU signals have different functionality depending on the mode of
operation. The signal naming in this section matches the naming used in the PRU Module
Interface section in the device TRM.
5.9.5.21.1.1 PRU_ICSSG PRU Direct Input/Output Mode Electrical Data and Timing
Table 5-86. PRU_ICSSG PRU Timing Requirements - Direct Input Mode
NO.
PARAMETER
DESCRIPTION
MIN
PRDI1
tsk(PRU_DATAIN)
PRU_DATAIN skew
MAX
2
UNIT
ns
PRDI1
GPI[m:0]
SPRS91x_TIMING_PRU_01
Figure 5-91. PRU_ICSSG PRU Direct Input Timing
(1) m in GPI[m:0] = 19.
220
Specifications
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Table 5-87. PRU_ICSSG PRU Switching Characteristics - Direct Output Mode
NO.
PRDO1
PARAMETER
DESCRIPTION
tsk(PRU_DATAOUT)
PRU_DATAOUT skew
MIN
MAX
4
UNIT
ns
GPO[n:0]
PRDO1
SPRS91x_TIMING_PRU_02
Figure 5-92. PRU_ICSSG PRU Direct Output Timing
(1) n in GPO[n:0] = 19.
5.9.5.21.1.2 PRU_ICSSG PRU Parallel Capture Mode Electrical Data and Timing
Table 5-88. PRU_ICSSG PRU Timing Requirements - Parallel Capture Mode
PARAMETER
DESCRIPTION
MIN
MAX
UNIT
PRPC1
tc(PRU_CLOCK)
Cycle time, PRU_CLOCK
20
ns
PRPC2
tw(PRU_CLOCKL)
Pulse Duration, PRU_CLOCK Low
10
ns
PRPC3
tw(PRU_CLOCKH)
Pulse Duration, PRU_CLOCK High
10
ns
PRPC4
tsu(PRU_DATAIN-
Setup time, PRU_DATAIN valid before PRU_CLOCK active edge
4
ns
Hold time, PRU_DATAIN valid after PRU_CLOCK active edge
0
ns
ADVANCE INFORMATION
NO.
PRU_CLOCK)
PRPC5
th(PRU_CLOCKPRU_DATAIN)
PRPC1
PRPC3
PRPC2
CLOCKIN
DATAIN
PRPC5
PRPC4
SPRS91x_TIMING_PRU_03
Figure 5-93. PRU_ICSSG PRU Parallel Capture Timing – Rising Edge Mode
PRPC1
PRPC3
PRPC2
CLOCKIN
DATAIN
PRPC5
PRPC4
SPRS91x_TIMING_PRU_04
Figure 5-94. PRU_ICSSG PRU Parallel Capture Timing – Falling Edge Mode
5.9.5.21.1.3
PRU_ICSSG PRU Shift Mode Electrical Data and Timing
Specifications
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Table 5-89. PRU_ICSSG PRU Timing Requirements - Shift In Mode
NO.
PARAMETER
DESCRIPTION
PRSI1
tw(PRU_DATAINL)
Pulse Duration, PRU_DATAIN Low
2+2*P
MIN
(1)
MAX
UNIT
ns
PRSI2
tw(PRU_DATAINH)
Pulse Duration, PRU_DATAIN High
2+2*P
(1)
ns
(1) P = Internal shift in clock period, defined by PRU0_GPI_DIV0 and PRU0_GPI_DIV1 bit fields in the GPCFGn register.
PRSI1
PRSI2
DATAIN
SPRSP08_TIMING_PRU_05
Figure 5-95. PRU_ICSSG PRU Shift In Timing
Table 5-90. PRU_ICSSG PRU Switching Characteristics - Shift Out Mode
ADVANCE INFORMATION
NO.
PARAMETER
DESCRIPTION
MIN
PRSO1
tc(PRU_CLKOUT)
Cycle time, PRU_CLKOUT
PRSO2
tw(PRU_CLKOUTL)
Pulse Duration, PRU_CLKOUT Low
MAX
UNIT
10
ns
-0.3 +
0.475*P*Z
ns
(1)(2)
PRSO3
tw(PRU_CLKOUTH)
Pulse Duration, PRU_CLKOUT High
-0.3 +
0.475*P*Y
ns
(1)(3)
PRSO4
td(PRU_CLKOUT-
Delay time, PRU_CLKOUT to PRU_DATAOUT Valid
0
3
ns
PRU_DATAOUT)
(1) P = Software programmable shift out clock period, defined by PRU0_GPO_DIV0 and PRU0_GPO_DIV1 bit fields in the GPCFGn
register.
(2) The Z parameter is defined as follows: If PRU0_GPI_DIV0 and PRU0_GPI_DIV1 are INTEGERS -or- if PRU0_GPI_DIV0 is a NONINTEGER and PRU0_GPI_DIV1 is an EVEN INTEGER then, Z equals (PRU0_GPI_DIV0 * PRU0_GPI_DIV1). If PRU0_GPI_DIV0 is a
NON-INTEGER and PRU0_GPI_DIV1 is an ODD INTEGER then, Z equals (PRU0_GPI_DIV0 * PRU0_GPI_DIV1 + 0.5). If
PRU0_GPI_DIV0 is an INTEGER and PRU0_GPI_DIV1 is a NON-INTEGER then, Z equals (PRU0_GPI_DIV0 * PRU0_GPI_DIV1 + 0.5
* PRU0_GPI_DIV0). If PRU0_GPI_DIV0 and PRU0_GPI_DIV1 are NON-INTEGERS then, Z equals (PRU0_GPI_DIV0 *
PRU0_GPI_DIV1 + 0.25 * PRU0_GPI_DIV0).
(3) The Y parameter is defined as follows: If PRU0_GPI_DIV0 and PRU0_GPI_DIV1 are INTEGERS -or- if PRU0_GPI_DIV0 is a NONINTEGER and PRU0_GPI_DIV1 is an EVEN INTEGER then, Y equals (PRU0_GPI_DIV0 * PRU0_GPI_DIV1). If PRU0_GPI_DIV0 is a
NON-INTEGER and PRU0_GPI_DIV1 is an ODD INTEGER then, Y equals (PRU0_GPI_DIV0 * PRU0_GPI_DIV1 - 0.5). If
PRU0_GPI_DIV0 is an INTEGER and PRU0_GPI_DIV1 is a NON-INTEGER then, Y equals (PRU0_GPI_DIV0 * PRU0_GPI_DIV1 - 0.5
* PRU0_GPI_DIV0). If PRU0_GPI_DIV0 and PRU0_GPI_DIV1 are NON-INTEGERS then, Y1 equals (PRU0_GPI_DIV0 *
PRU0_GPI_DIV1 - 0.25 * PRU0_GPI_DIV0) and Y2 equals (PRU0_GPI_DIV0 * PRU0_GPI_DIV1 + 0.25 * PRU0_GPI_DIV0), where Y1
is the first high pulse and Y2 is the second high pulse.
PRSO1
PRSO2H
PRSO2L
CLOCKOUT
DATAOUT
PRSO3
SPRSP08_TIMING_PRU_06
Figure 5-96. PRU_ICSSG PRU Shift Out Timing
5.9.5.21.1.4
222
PRU_ICSSG PRU Sigma Delta and Peripheral Interface Modes Electrical Data and Timing
Specifications
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Table 5-91. PRU_ICSSG PRU Timing Requirements - Sigma Delta Mode
PARAMETER
DESCRIPTION
PRSD1
NO.
tc(SD_CLK)
Cycle time, SD_CLK
MIN
40
MAX
UNIT
ns
PRSD2L
tw(SD_CLKL)
Pulse Duration, SD_CLK Low
20
ns
PRSD2H
tw(SD_CLKH)
Pulse Duration, SD_CLK High
20
ns
PRSD3
tsu(SD_DATA-SD_CLK)
Setup time, SD_DATA valid before SD_CLK active edge
10
ns
PRSD4
th(SD_CLK-SD_DATA)
Hold time, SD_DATA valid before SD_CLK active edge
5
ns
PRSD1
PRSD2H
SDx_CLK
PRSD2L
SDx_D
ADVANCE INFORMATION
PRSD4
PRSD3
SPRSP08_TIMING_PRU_07
Figure 5-97. PRU_ICSSG PRU SD_CLK Falling Active Edge
PRSD2L
SDx_CLK
SDx_D
PRSD4
PRSD3
SPRSP08_TIMING_PRU_08
Figure 5-98. PRU_ICSSG PRU SD_CLK Rising Active Edge
Table 5-92. PRU_ICSSG PRU Timing Requirements - Peripheral Interface Mode
NO.
PARAMETER
DESCRIPTION
MIN
MAX
UNIT
PRPIF1
tw(PIF_DATA_INH)
Pulse Duration, PIF_DATA_IN High
2+
0.475*(4*P) (1)
ns
PRPIF2
tw(PIF_DATA_INL)
Pulse Duration, PIF_DATA_IN Low
2+
0.475*(4*P) (1)
ns
(1) P = 1x (or TX) clock period, defined by TX_DIV_FACTOR and TX_DIV_FACTOR_FRAC in the CFG_ED_Pn_TXCFG register.
PRPIF1
PRPIF2
PIF_DATA_IN
SPRSP08_TIMING_PIF_01
Figure 5-99. PRU_ICSSG PRU Peripheral Interface Timing
Table 5-93. PRU_ICSSG PRU Switching Characteristics - Peripheral Interface Mode
NO.
PRPIF1
PARAMETER
DESCRIPTION
tc(PIF_CLK)
Cycle time, PIF_CLK
MIN
MAX
30
ns
Specifications
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Table 5-93. PRU_ICSSG PRU Switching Characteristics - Peripheral Interface Mode (continued)
NO.
PARAMETER
PRPIF2H tw(PIF_DATA_INH)
DESCRIPTION
MIN
Pulse Duration, PIF_CLK High
MAX
0 + 0.475*P
UNIT
ns
(1)
PRPIF2L tw(PIF_DATA_INL)
Pulse Duration, PIF_CLK Low
0 + 0.475*P
ns
(1)
PRPIF3
td(PIF_CLK-
Delay time, PIF_CLK fall to PIF_DATA_OUT
-5
5
ns
Delay time, PIF_CLK fall to PIF_DATA_EN
-5
5
ns
PIF_DATA_OUT)
PRPIF4
td(PIF_CLKPIF_DATA_EN)
(1) P = 1x (or TX) clock period, defined by TX_DIV_FACTOR and TX_DIV_FACTOR_FRAC in the CFG_ED_Pn_TXCFG register.
PRPIF1
PRPIF2H
PRPIF2L
PIF_CLK
PRPIF3
ADVANCE INFORMATION
PIF_DATA_OUT
PRPIF4
PIF_DATA_EN
SPRSP08_TIMING_PIF_02
Figure 5-100. PRU_ICSSG PRU Peripheral Interface Switching Characteristics
5.9.5.21.2 PRU_ICSSG Pulse Width Modulation (PWM)
5.9.5.21.2.1 PRU_ICSSG PWM Electrical Data and Timing
Table 5-94. PRU_ICSSG PWM Switching Characteristics
NO.
PRPWM
1
PARAMETER
DESCRIPTION
tsk(PWM_A/B)
PWM_A/B skew
MIN
MAX
5
UNIT
ns
PWM_A/B
PRPWM1
SPRSP08_TIMING_PRU_PWM_01
Figure 5-101. PRU_ICSSG PRU PWM Timing
5.9.5.21.3 PRU_ICSSG Industrial Ethernet Peripheral (PRU_ICSSG IEP)
5.9.5.21.3.1 PRU_ICSSG IEP Electrical Data and Timing
Table 5-95. PRU_ICSSG IEP Timing Requirements - Input Validated with SYNCx
NO.
PRIEP1
PARAMETER
DESCRIPTION
MIN
tw(EDC_SYNCx_OUTL)
Pulse Duration, EDC_SYNCx_OUT Low
-2+20*P
MAX
UNIT
ns
(1)
PRIEP2
tw(EDC_SYNCx_OUTH)
Pulse Duration, EDC_SYNCx_OUT High
-2+20*P
ns
(1)
224
Specifications
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Table 5-95. PRU_ICSSG IEP Timing Requirements - Input Validated with SYNCx (continued)
NO.
PRIEP3
PRIEP4
PARAMETER
DESCRIPTION
tsu(EDIO_DATA_IN-
20
ns
EDC_SYNCx_OUT)
Setup time, EDIO_DATA_IN valid before EDC_SYNCx_OUT active
edge
MIN
MAX
UNIT
th(EDC_SYNCx_OUT-
Hold time, EDIO_DATA_IN valid after EDC_SYNCx_OUT active edge
20
ns
EDIO_DATA_IN)
(1) P = PRU-ICSS IEP clock source period.
EDC_SYNCx_OUT
PRIEP2
PRIEP1
PRIEP3
PRIEP4
SPRSP08_TIMING_PRU_IEP_01
Figure 5-102. PRU_ICSSG PRU IEP SYNCx Timing
Table 5-96. PRU_ICSSG IEP Timing Requirements - Digital IOs
NO.
IEPIO1
PARAMETER
DESCRIPTION
tw(EDIO_OUTVALIDL)
Pulse Duration, EDIO_OUTVALID Low
MIN
MAX
-2+14*P
UNIT
ns
(1)
IEPIO2
tw(EDIO_OUTVALIDH)
Pulse Duration, EDIO_OUTVALID High
-2+32*P
ns
(1)
IEPIO3
td(EDIO_OUTVALID-
Delay time, EDIO_OUTVALID to EDIO_DATA_OUT
0 0+18*P
EDIO_DATA_OUT skew
5
(1)
ns
EDIO_DATA_OUT)
IEPIO4
tsk(EDIO_DATA_OUT)
ns
(1) P = PRU-ICSS IEP clock source period.
EDIO_DATA_OUT
IEPIO4
SPRSP08_TIMING_PRU_EDIO_DATA_OUT
Figure 5-103. PRU_ICSSG PRU IEP Digital IOs Timing
Table 5-97. PRU_ICSSG IEP Timing Requirements - LATCHx_IN
PARAMETER
DESCRIPTION
PRLA1
NO.
tw(EDC_LATCHx_INL)
Pulse Duration, EDC_LATCHx_IN Low
2+3*P
MIN
(1)
MAX
UNIT
ns
PRLA2
tw(EDC_LATCHx_INH)
Pulse Duration, EDC_LATCHx_IN High
2+3*P
(1)
ns
(1) P = PRU-ICSS IEP clock source period.
PRLA1
EDC_LATCHx_IN
PRLA2
SPRSP08_TIMING_PRU_IEP_02
Figure 5-104. PRU_ICSSG PRU IEP LATCHx_IN Timing
Specifications
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ADVANCE INFORMATION
EDIO_DATA_IN[7:0]
DRA80M
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5.9.5.21.4 PRU_ICSSG Universal Asynchronous Receiver Transmitter (PRU-ICSS UART)
5.9.5.21.4.1 PRU_ICSSG UART Electrical Data and Timing
Table 5-98. PRU_ICSSG UART Timing Requirements
PARAMETER
DESCRIPTION
PRUR1H
NO.
tw(RXH)
Pulse Duration, Receive start, stop, data bit High
0+U
MIN
(1)
MAX
UNIT
ns
PRUR1L
tw(RXL)
Pulse Duration, Receive start, stop, data bit Low
-2+U (1)
ns
(1) U = UART baud time = 1/programmed baud rate.
Table 5-99. PRU_ICSSG UART Switching Characteristics
NO.
PARAMETER
DESCRIPTION
MIN
MAX
UNIT
PRUR2
f(baud)
Maximum programmable baud rate
PRUR3L
tw(TXH)
Pulse Duration, Transmit start, stop, data bit High
0+U(1)
ns
PRUR3H
tw(TXL)
Pulse Duration, Transmit start, stop, data bit Low
-2+U(1)
ns
(1) U = UART baud time = 1/programmed baud rate.
ADVANCE INFORMATION
PRUR1L
PRUR1H
PRGi_UART0_RXD
(1)
Start
Bit
Data Bits
PRUR3L
PRUR3H
PRGi_UART0_TXD
(1)
Start
Bit
Data Bits
(1) i in PRGi_UART0_RXD and PRGi_UART0_TXD = 0, 1 or 2
SPRS91x_TIMING_PRU_UART_01
Figure 5-105. PRU_ICSSG UART Timing
5.9.5.21.5 PRU_ICSSG Enhanced Capture Peripheral (PRU-ICSS ECAP)
5.9.5.21.5.1 PRU_ICSSG ECAP Electrical Data and Timing
Table 5-100. PRU_ICSSG ECAP Timing Requirements
PARAMETER
DESCRIPTION
PREP1
NO.
tw(CAP)
Pulse Duration, Capture input (asynchronous)
2+2*P
(1)
ns
PREP2
tw(SYNCI)
Pulse Duration, Sync input (asynchronous)
2+2*P
(1)
ns
226
MIN
Specifications
MAX
UNIT
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(1) P = core_clk period
PREP1
CAP
PREP2
SYNCI
SPRSP08_TIMING_ECAP_01
Figure 5-106. PRU_ICSSG ECAP Timing
Table 5-101. PRU_ICSSG ECAP Switching Characteristics
NO.
DESCRIPTION
tw(APWM)
Pulse Duration, Auxillary PWM (APWM) output
MIN
PREP4
tw(SYNCO)
Pulse Duration, Sync output (asynchronous)
MAX
UNIT
0+2*P
(1)
ns
0+P
(1)
ns
ADVANCE INFORMATION
PARAMETER
PREP3
(1) P = core_clk period
PREP3
APWM
SYNCO
SPRSP08_TIMING_ECAP_02
Figure 5-107. PRU_ICSSG ECAP Switching Characteristics
5.9.5.21.6 PRU_ICSSG RGMII, MII_RT, and Switch
5.9.5.21.6.1 PRU_ICSSG MDIO Electrical Data and Timing
Table 5-102. PRU_ICSSG MDIO Timing Requirements – MDIO_DATA
PARAMETER
DESCRIPTION
PRMDI1
NO.
tsu(MDIO-MDC)
Setup time, MDIO valid before MDC High
MIN
PRMDI2
th(MDC-MDIO)
Hold time, MDIO valid from MDC High
MAX
ns
0
ns
Specifications
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90
227
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(1) P = Cycle time
PRMDI1
PRMDI2
MDIO_CLK (Output)
MDIO_DATA (Input)
SPRS91x_TIMING_PRU_MII_RT_01
Figure 5-108. PRU_ICSSG MDIO_DATA Timing – Input Mode
Table 5-103. PRU_ICSSG MDIO Switching Characteristics – MDIO_CLK
NO.
ADVANCE INFORMATION
PARAMETER
DESCRIPTION
MIN
PRMC1
tc(MDC)
Cycle time, MDC
400
MAX
UNIT
ns
PRMC2
tw(MDCH)
Pulse Duration, MDC High
160
ns
PRMC3
tw(MDCL)
Pulse Duration, MDC Low
160
PRMC4
tt(MDC)
Transition time, MDC
ns
5
ns
PRMC4
PRMC1
PRMC3
PRMC2
MDIO_CLK
PRMC4
SPRS91x_TIMING_PRU_MII_RT_02
Figure 5-109. PRU_ICSSG MDIO_CLK Timing
Table 5-104. PRU_ICSSG MDIO Switching Characteristics – MDIO_DATA
NO.
PARAMETER
PRMDO1 td(MDC-MDIO)
DESCRIPTION
MIN
Delay time, MDC High to MDIO valid
10
MAX
UNIT
ns
PRMDO1
MDIO_CLK (Output)
MDIO_DATA (Output)
SPRS91x_TIMING_PRU_MII_RT_03
Figure 5-110. PRU_ICSSG MDIO_DATA Timing – Output Mode
5.9.5.21.6.2 PRU_ICSSG RGMII Electrical Data and Timing
228
Specifications
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Table 5-105. PRU_ICSSG RGMII Timing Requirements - RGMII_RCLK
NO.
PRRG1
PRRG2
PARAMETER
DESCRIPTION
MODE
MIN
MAX
UNIT
tc(RXC)
Cycle time, RXC
10 Mbps
TBD
TBD
ns
100 Mbps
TBD
TBD
ns
1000 Mbps
7.2
8.8
ns
10 Mbps
TBD
TBD
ns
100 Mbps
TBD
TBD
ns
tw(RXCH)
Pulse duration, RXC high
1000 Mbps
PRRG3
PRRG4
tw(RXCL)
tt(RXC)
Pulse duration, RXC low
Transition time, RXC
3.6
4.4
ns
10 Mbps
TBD
TBD
ns
100 Mbps
TBD
TBD
ns
1000 Mbps
3.6
4.4
ns
10 Mbps
TBD
ns
100 Mbps
TBD
ns
1000 Mbps
0.75
ns
PRRG2
PRRG3
RGMII_RXC
PRRG4
SPRS91x_TIMING_PRU_RGMII_RT_04
Figure 5-111. PRU_ICSSG RGMII_RCLK Input Timing
Table 5-106. PRU_ICSSG RGMII Timing Requirements - RGMII_RD[3:0] and RGMII_RCTL
NO.
PRRG5
PARAMETER
DESCRIPTION
tsu(RD-RXC)
Setup time, RD[3:0] valid before RXC high/low
tsu(RX_CTL-RXC)
PRRG6
th(RXC-RD)
th(RXC-RX_CTL)
PRRG7
tt(RD)
tt(RX_CTL)
Setup time, RX_CTL valid before RXC high/low
Hold time, RD[3:0] valid after RXC high/low
Hold time, RX_CTL valid after RXC high/low
Transition time, RD
Transition time, RX_CTL
MODE
MIN
MAX
10 Mbps
TBD
ns
100 Mbps
TBD
ns
1000 Mbps
1
ns
10 Mbps
TBD
ns
100 Mbps
TBD
ns
1000 Mbps
1
ns
10 Mbps
TBD
ns
100 Mbps
TBD
ns
1000 Mbps
1
ns
10 Mbps
TBD
ns
100 Mbps
TBD
ns
1000 Mbps
1
ns
10 Mbps
TBD
ns
100 Mbps
TBD
ns
1000 Mbps
0.75
ns
10 Mbps
TBD
ns
100 Mbps
TBD
ns
1000 Mbps
0.75
ns
Specifications
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229
ADVANCE INFORMATION
PRRG1
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PRPG5
PRPG6
RGMII_RXCLK (Input)
RGMII_RXD[3:0],
RGMII_RXDV,
RGMII_RXER (Inputs)
PRPG7
SPRS91x_TIMING_PRU_RGMII_RT_05
Figure 5-112. PRU_ICSSG RGMII_RD[3:0] and RGMII_RCTL Input Timing
Table 5-107. PRU_ICSSG RGMII Switching Characteristics - RGMII_TCLK
NO.
PRRG8
PARAMETER
DESCRIPTION
MODE
MIN
MAX
UNIT
tc(TXC)
Cycle time, TXC
10 Mbps
TBD
TBD
ns
100 Mbps
TBD
TBD
ns
1000 Mbps
ADVANCE INFORMATION
PRRG9
PRRG10
PRRG11
tw(TXCH)
tw(TXCL)
tt(TXC)
Pulse duration, TXC high
Pulse duration, TXC low
Transition time, TXC
7.2
8.8
ns
10 Mbps
TBD
TBD
ns
100 Mbps
TBD
TBD
ns
1000 Mbps
3.6
4.4
ns
10 Mbps
TBD
TBD
ns
100 Mbps
TBD
TBD
ns
1000 Mbps
3.6
4.4
ns
10 Mbps
TBD
ns
100 Mbps
TBD
ns
1000 Mbps
0.75
ns
PRRG11
PRRG8
PRRG9
PRRG10
RGMII_TXC
PRRG11
SPRS91x_TIMING_PRU_RGMII_RT_06
Figure 5-113. PRU_ICSSG RGMII_RCLK Output Timing
Table 5-108. PRU_ICSSG RGMII Switching Characteristics - RGMII_TD[3:0] and RGMII_TCTL
NO.
PRRG12
PARAMETER
DESCRIPTION
tsk(TD-TXC)
TD to TXC output skew
tsk(TX_CTL-TXC)
230
TX_CTL to TXC output skew
Specifications
MODE
MIN
MAX
UNIT
10 Mbps
TBD
TBD
ns
100 Mbps
TBD
TBD
ns
1000 Mbps
TBD
TBD
ns
10 Mbps
TBD
TBD
ns
100 Mbps
TBD
TBD
ns
1000 Mbps
TBD
TBD
ns
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Table 5-108. PRU_ICSSG RGMII Switching Characteristics - RGMII_TD[3:0] and RGMII_TCTL (continued)
NO.
PRRG13
PARAMETER
DESCRIPTION
tt(TD)
Transition time, TD
tt(TX_CTL)
MODE
Transition time, TX_CTL
MAX
UNIT
10 Mbps
MIN
TBD
ns
100 Mbps
TBD
ns
1000 Mbps
0.75
ns
10 Mbps
TBD
ns
100 Mbps
TBD
ns
1000 Mbps
0.75
ns
(1) P = Cycle time
RGMII_TXC
RGMII_TD[3:0]
RGMII_TX_CTL
PRRG12
PRRG13
SPRS91x_TIMING_PRU_RGMII_RT_07
5.9.5.21.6.3 PRU_ICSSG MII_RT Electrical Data and Timing
NOTE
In order to ensure the MII_G_RT I/O timing values published in the device data sheet, the
PRU_ICSSG ICSSGn_CORE_CLK (where n = 0 to 2) core clock must be configured for 200
MHz, 225 MHz, or 250 MHz and the TX_CLK_DELAYn (where n = 0 or 1) bit field in the
ICSSG_TXCFG0/1 register must be set to 0h (default value).
Table 5-109. PRU_ICSSG MII_RT Timing Requirements – MII_RXCLK
NO.
PMIR1
PARAMETER
DESCRIPTION
tc(RX_CLK)
Cycle time, RX_CLK
MODE
PMIR2
tw(RX_CLKH)
Pulse Duration, RX_CLK High
PMIR3
tw(RX_CLKL)
Pulse Duration, RX_CLK Low
MIN
MAX
UNIT
10 Mbps
399.96
400.04
ns
100 Mbps
39.996
40.004
ns
10 Mbps
140
260
ns
100 Mbps
14
26
ns
10 Mbps
140
260
ns
100 Mbps
14
26
ns
PMIR1
PMIR3
PMIR2
MII_RXCLK
SPRS91x_TIMING_PRU_MII_RT_04
Figure 5-115. PRU_ICSSG MII_RXCLK Timing
Table 5-110. PRU_ICSSG MII_RT Timing Requirements – MII_TXCLK
NO.
PMIT1
PARAMETER
DESCRIPTION
tc(TX_CLK)
Cycle time, TX_CLK
MIN
MAX
10 Mbps
MODE
399.96
400.04
ns
100 Mbps
39.996
40.004
ns
Specifications
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231
ADVANCE INFORMATION
Figure 5-114. PRU_ICSSG RGMII_RD[3:0] and RGMII_RCTL Output Timing
DRA80M
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Table 5-110. PRU_ICSSG MII_RT Timing Requirements – MII_TXCLK (continued)
PARAMETER
DESCRIPTION
PMIT2
NO.
tw(TX_CLKH)
Pulse Duration, TX_CLK High
PMIT3
tw(TX_CLKL)
Pulse Duration, TX_CLK Low
PMIT4
tt(TX_CLK)
Transition time, TX_CLK
MODE
MIN
MAX
UNIT
10 Mbps
140
260
ns
100 Mbps
14
26
ns
10 Mbps
140
260
ns
100 Mbps
14
26
ns
10 Mbps
5
ns
100 Mbps
5
ns
PMIT4
PMIT1
PMIT3
PMIT2
MII_TXCLK
PMIT4
SPRS91x_TIMING_PRU_MII_RT_05
ADVANCE INFORMATION
Figure 5-116. PRU_ICSSG MII_TXCLK Timing
Table 5-111. PRU_ICSSG MII_RT Timing Requirements – MII_RXD[3:0], MII_RXDV, and MII_RXER
NO.
PARAMETER
DESCRIPTION
PMIR4
tsu(RXD-RX_CLK)
Setup time, RXD[3:0] valid before RX_CLK
8
ns
tsu(RX_DV-RX_CLK)
Setup time, RX_DV valid before RX_CLK
8
ns
tsu(RX_ER-RX_CLK)
Setup time, RX_ER valid before RX_CLK
8
ns
tsu(RXD-RX_CLK)
Setup time, RXD[3:0] valid before RX_CLK
8
ns
tsu(RX_DV-RX_CLK)
Setup time, RX_DV valid before RX_CLK
8
ns
tsu(RX_ER-RX_CLK)
Setup time, RX_ER valid before RX_CLK
8
ns
th(RX_CLK-RXD)
Hold time, RXD[3:0] valid after RX_CLK
8
ns
th(RX_CLK-RX_DV)
Hold time, RX_DV valid after RX_CLK
8
ns
th(RX_CLK-RX_ER)
Hold time, RX_ER valid after RX_CLK
8
ns
th(RX_CLK-RXD)
Hold time, RXD[3:0] valid after RX_CLK
8
ns
th(RX_CLK-RX_DV)
Hold time, RX_DV valid after RX_CLK
8
ns
th(RX_CLK-RX_ER)
Hold time, RX_ER valid after RX_CLK
8
ns
PMIR5
MODE
10 Mbps
100 Mbps
10 Mbps
100 Mbps
MIN
MAX
UNIT
PMIR4
PMIR5
MII_MRCLK (Input)
MII_RXD[3:0],
MII_RXDV,
MII_RXER (Inputs)
SPRS91x_TIMING_PRU_MII_RT_06
Figure 5-117. PRU_ICSSG MII_RXD[3:0], MII_RXDV, and MII_RXER Timing
232
Specifications
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Table 5-112. PRU_ICSSG MII_RT Switching Characteristics – MII_TXD[3:0] and MII_TXEN
NO.
PARAMETER
DESCRIPTION
PMIT5
td(TX_CLK-TXD)
Delay time, TX_CLK High to TXD[3:0] valid
MODE
td(TX_CLK-TX_EN)
Delay time, TX_CLK to TX_EN valid
td(TX_CLK-TXD)
Delay time, TX_CLK High to TXD[3:0] valid
td(TX_CLK-TX_EN)
Delay time, TX_CLK to TX_EN valid
MIN
MAX
5
25
ns
5
25
ns
5
25
ns
5
25
ns
10 Mbps
100 Mbps
UNIT
PMIT5
MII_TXCLK (input)
MII_TXD[3:0],
MII_TXEN (outputs)
SPRS91x_TIMING_PRU_MII_RT_07
For more information, see section Programmable Real-Time Unit Subsystem
Communication Subsystem - Gigabit (PRU_ICSSG) in the device TRM.
and
Industrial
5.9.5.22 Timers
For more details about features and additional description information on the device Timers, see the
corresponding sections within Section 4.3, Signal Descriptions and Section 6, Detailed Description.
Table 5-113, Table 5-114 and Figure 5-119 present timings and switching characteristics of the Timers.
Table 5-113. Timing Requirements for Timers
NO.
PARAMETER
DESCRIPTION
T1
tw(TINPH)
Pulse duration, high
CAPTURE
MODE
5 + 4P(1)
MIN
MAX
UNIT
ns
T2
tw(TINPL)
Pulse duration, low
CAPTURE
5 + 4P
ns
(1)
(1) P = functional clock period in ns.
Table 5-114. Switching Characteristics for Timers
NO.
PARAMETER
DESCRIPTION
MODE
T3
tw(TOUTH)
Pulse duration, high
T4
tw(TOUTL)
Pulse duration, low
MIN
MAX
UNIT
PWM
-3 + 4P
(1)
ns
PWM
-3 + 4P(1)
ns
(1) P = functional clock period in ns.
T1
T2
TIMIx
T3
T4
TIMOx
TIMER_01
Figure 5-119. Timer Timing
For more information, see section Timers in the device TRM.
Specifications
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ADVANCE INFORMATION
Figure 5-118. PRU_ICSSG MII_TXD[3:0], MII_TXEN Timing
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5.9.5.23 UART
For more details about features and additional description information on the device Universal
Asynchronous Receiver Transmitter, see the corresponding sections within Section 4.3, Signal
Descriptions and Section 6, Detailed Description.
Table 5-115, Table 5-116, and Figure 5-120 present Timing Requirements and Switching Characteristics
for UART interface.
Table 5-115. Timing Requirements for UART
NO.
4
5
PARAMETER
DESCRIPTION
tw(RX)
Pulse width, receive data bit, 15/30 pF high or low
MODE
MIN
0.95U
(1)
MAX
UNIT
1.05U
(1)
ns
1.05U
(1)
ns
tw(CTS)
Pulse width, receive start bit, 15/30 pF high or low
0.95U
(1)
td(RTS-TX)
Delay time, transmit start bit to transmit data
P
(2)
ns
td(CTS-TX)
Delay time, receive start bit to transmit data
P
(2)
ns
(1) U = UART baud time = 1/Programmed baud rate
(2) P = Clock period of the reference clock (FCLK, usually 48 MHz or 192 MHz)
ADVANCE INFORMATION
Table 5-116. Switching Characteristics Over Recommended Operating Conditions for UART
NO.
PARAMETER
DESCRIPTION
MODE
f(baud)
Maximum programmable baud rate
15 pF
MIN
2
tw(TX)
Pulse width, transmit data bit, 15/30 pF high or low
U-2
(1)
U+2
(1)
ns
3
tw(RTS)
Pulse width, transmit start bit, 15/30 pF high or low
U-2
(1)
U+2
(1)
ns
30 pF
MAX
UNIT
12
MHz
0.115
(1) U = UART baud time = 1/Programmed baud rate
3
2
UARTi_TXD
Start
Bit
Data Bits
5
4
UARTi_RXD
Start
Bit
Data Bits
Figure 5-120. UART Timing
For more information, see section Universal Asynchronous Receiver/Transmitter (UART) in the device
TRM.
5.9.5.24 USB
The USB 2.0 subsystem is compliant with the Universal Serial Bus (USB) Specification, revision 2.0. Refer
to the specification for timing details.
The USB 3.1 GEN1 Dual-Role Device Subsystem is compliant with the Universal Serial Bus (USB) 3.1
Specification, revision 1.0. Refer to the specification for timing details.
For more details about features and additional description information on the device Universal Serial Bus
Subsystem (USB), see the corresponding sections within Section 4.3, Signal Descriptions and Section 6,
Detailed Description.
For more information, see section Universal Serial Bus (USB) Subsystem in the device TRM.
234
Specifications
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5.9.6
SPRSP31E – APRIL 2018 – REVISED JUNE 2019
Emulation and Debug
5.9.6.1
Debug Trace
Table 5-117 and Figure 5-121 assume testing over the recommended operating conditions and electrical
characteristic conditions.
Table 5-117. Debug Trace Switching Characteristics
PARAMETER
DESCRIPTION
DBTR1
NO.
tc(TRC_CLK)
Cycle time, TRC_CLK
MIN
DBTR2
tw(TRC_CLKH)
DBTR3
DBTR4
MAX
UNIT
10.16
ns
Pulse width, TRC_CLK high
4.33
ns
tw(TRC_CLKL)
Pulse width, TRC_CLK low
4.33
ns
tosu(TRC_DATAV-
Output setup time, TRC_DATA valid to TRC_CLK edge
1.27
ns
TRC_CLK)
DBTR5
toh(TRC_CLK-TRC_DATAI)
Output hold time, TRC_CLK edge to TRC_DATA invalid
1.27
ns
DBTR6
tosu(TRC_CTLV-TRC_CLK)
Output setup time, TRC_CTL valid to TRC_CLK edge
1.27
ns
DBTR7
toh(TRC_CLK-TRC_CTLI)
Output hold time, TRC_CLK edge to TRC_CTL invalid
1.27
DBTR8
trx(TRC_CLK_DATA_CTL)
Output rise time, 30% VDD to 70% VDD
0.75
ns
DBTR9
tfx(TRC_CLK_DATA_CTL)
Output fall time, 70% VDD to 30% VDD
0.75
ns
DBTR1
DBTR2
DBTR3
TRC_CLK
(Worst Case 1)
(Ideal)
(Worst Case 2)
DBTR9
DBTR8
DBTR4
DBTR5
DBTR4
DBTR5
DBTR6
DBTR7
DBTR6
DBTR7
TRC_DATA
DBTR8
DBTR9
SPRSP08_Debug_01
Figure 5-121. Debug Trace Timing
5.9.6.2
IEEE 1149.1 Standard-Test-Access Port (JTAG)
For more details about features and additional description information on the device IEEE 1149.1
Standard-Test-Access Port, see the corresponding sections within Section 4.3, Signal Descriptions and
Section 6, Detailed Description.
5.9.6.2.1 JTAG Electrical Data and Timing
Table 5-118, Table 5-119, and Figure 5-122 assume testing over the recommended operating conditions
and electrical characteristic conditions.
Table 5-118. Timing Requirements for IEEE 1149.1 JTAG
NO.
PARAMETER
DESCRIPTION
MIN
MAX
J1
tc(TCK)
Cycle time minimum, TCK
75
ns
J2
tw(TCKH)
Pulse width minimum, TCK high
30
ns
J3
tw(TCKL)
Pulse width minimum, TCK low
30
ns
J4
tsu(TDI-TCK)
Input setup time minimum, TDI valid to TCK high
8
ns
tsu(TMS-TCK)
Input setup time minimum, TMS valid to TCK high
8
ns
Specifications
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235
ADVANCE INFORMATION
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Table 5-118. Timing Requirements for IEEE 1149.1 JTAG (continued)
NO.
J5
PARAMETER
DESCRIPTION
th(TCK-TDI)
Input hold time minimum, TDI valid from TCK high
MIN
5.2
MAX
UNIT
ns
th(TCK-TMS)
Input hold time minimum, TMS valid from TCK high
5.2
ns
Table 5-119. Switching Characteristics Over Recommended Operating Conditions for IEEE 1149.1 JTAG
NO.
PARAMETER
DESCRIPTION
J6
td(TCKL-TDOI)
Delay time minimum, TCK low to TDO invalid
MIN
J7
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ADVANCE INFORMATION
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Figure 5-122. JTAG Test-Port Timing
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6 Detailed Description
6.1
Overview
Automobiles are becoming more and more connected - both inside the car, within the various subsystems
/ domains as well as with the outside world, with connectivity via Bluetooth, LTE, WiFi etc.
DRA80x Automotive Gateway processors are built to meet the intense processing needs of automotive
gateway. The DRA80x family of devices combines four or two Arm® Cortex-A53 cores with an ASIL-C
capable dual Cortex-R5 MCU subsystem and six Gigabit Ethernet MACs in the MAIN domain and one
Gigabit Ethernet MAC in the MCU domain to create an SoC capable of implementing an Automotive
Gateway system with plenty of automotive connectivity and functional safety processing.
The four A53 cores are arranged in two dual-core clusters with shared L2 memory to create two
processing channels to address additional safety concepts. Extensive ECC is included for on-chip memory
and interconnects for reliability. Cryptographic acceleration and secure boot are available on DRA80x
devices, in addition to granular whitelist firewalls managed by a security controller core.
Programmability is provided by the quad-core ARM Cortex-A53 RISC CPUs with Neon™ extension, and
the dual Cortex-R5 MCU subsystem is available for general purpose use. The Ethernet subsystem can be
used to provide up to six ports of Ethernets, including TSN, for standard Ethernet connectivity.
Additionally, TI provides a complete set of development tools for the ARM cores including C compilers and
a debugging interface for visibility into source code execution. Safety documentation is available for
applications needing to meet functional safety standards.
NOTE
For more information on features, subsystems, and architecture of superset device System
on Chip (SoC), see the device TRM.
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Much more information and data are being shared or transferred between the various domains; for
example, video from rear and surround view cameras for displayed in the head unit; data from the chassis
is sent to the on-board diagnostic unit, etc. As the amount of data that has to be integrated and
transported between the various domains in a time sensitive manner has increased, car manufacturers are
looking to include a network gateway, based on Ethernet protocols, in cars. Such gateways should be able
to handle multiple connectivity protocols such as CAN, CAN-FD, TCP/IP to name a few. TI’s DRA80x
family of products enable automotive manufacturers to build scalable and cost optimized network gateway
features in cars, thanks to its high level of integration and purpose built peripherals, such as Gigabit
Ethernet MACs.
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6.2
6.2.1
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Processor Subsystems
Arm Cortex-A53
The SoC implements two Dual-Core Arm Cortex-A53 Subsystems (CC_ARMSS0 and CC_ARMSS1),
which are both integrated inside the Compute Cluster (along with the MSMC module). The Cortex-A53
cores are general-purpose processors that can be used for running customer applications.
NOTE
Notes on references used in this document:
• Both Arm Cortex-A53 Subsystems are functionally identical and are referred to as a
single subsystem (CC_ARMSS), where appropriate.
• CC_ARMSS is also referred to as Arm CorePac and A53SS.
• Cortex-A53 is often shortened to A53.
The CC_ARMSS is built around the Cortex-A53 MPCore (Arm A53 Cluster), which is provided by Arm and
configured by TI. It is based on the symmetric multiprocessor (SMP) architecture, and thus it delivers high
performance and optimal power management, debug and emulation capabilities.
ADVANCE INFORMATION
The A53 processor is a multi-issue out-of-order superscalar execution engine with integrated L1
Instruction and Data Caches, compatible with Arm®v8-A architecture. It delivers significantly more
performance than its predecessors at a higher level of power efficiency.
The Armv8-A architecture brings a number of new features. These include 64-bit data processing,
extended virtual addressing and 64-bit general purpose registers. The A53 processor is Arm’s first Armv8A processor aimed at providing power-efficient 64-bit processing. It features an in-order, 8-stage, dualissue pipeline, and improved integer, Arm® Neon™, Floating-Point Unit (FPU) and memory performance.
The A53 CPU supports two execution states: AArch32 and AArch64. The AArch64 state gives the A53
CPU its ability to execute 64-bit applications, while the AArch32 state allows the processor to execute
existing Arm®v7-A applications.
Details on the Compute Cluster module and the interaction between CC_ARMSS(s) and MSMC can be
found in the Compute Cluster chapter.
The CC_ARMSS supports the following key features:
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Cortex-A53 MPCore (A53 Cluster) features:
– Dual-core configuration (coherent SMP processors within the cluster)
– A53 core revision: r0p4
– Full compliance to Armv8-A architecture
• AArch32 and AArch64 Execution States
– AArch32 for full backward compatibility with Armv7
– AArch64 for 64b support and new architectural features
• All exception levels EL0-3
• A32 Instruction Set
• T32 Instruction Set
• A64 Instruction Set
– Neon Advanced SIMD
– VFPv4 Floating point
– Hardware virtualization support
– Armv8 Cryptography Extensions
– Arm GICv3 architecture
– In-order pipeline with symmetric dual-issue of most instructions
– Harvard L1 with system MMU
• 32KB Instruction (Program) Cache
• 32KB Data Cache
– 512KB Shared L2 Cache
– Snoop Control Unit (SCU) managing the interconnect, arbitration, communication, cache-to-cache
and system memory transfers, cache coherence and other capabilities for the processor
– Generic Timer(s)
– Arm® CoreSight™ Debug and Trace Architecture
– Functional safety support
• Error Correction Code (ECC) protection for:
– L1 Data Cache (Data RAM)
– L2 Cache (Data RAM, Tag RAM)
– L1 SCU Duplicate Tags
• Parity protection for:
– L1 Instruction Cache (Data RAM and Tag RAM)
– L1 Data Cache Tag RAM and Dirty Bits
– TLB
• No error protection on branch protection and L2 victim RAM
• Support for error injection to all supported ECC memory blocks
– Provided for testing ECC functionality in safety-critical applications (add-on function from TI)
– Supported by ECC Aggregators at the CC_ARMSS level
256-bit wide, synchronous or asynchronous VBUSM.C master interface
– AXI2VBUSM_MASTER Bridge
– Sync/Async boot time selectable via pin
– Cache pre-warming via use of ACP Port
64-bit graycoded system input time
48-bit graycoded debug input time
32-bit VBUSP slave interface for debug (internally converted to APB)
32-bit ATB output port for debug/trace
Interface with Arm GIC-500 Interrupt Controller (SoC level, not part of CC_ARMSS)
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Supports the SoC multi-core cache coherency architecture
Dedicated MPU clocking (Arm PLLs) for full flexibility in performance trade-offs
Advanced power management with fine-grained control of individual A53 CPU power domains, coarsegrained cluster-level power management, and low-power standby modes (WFI/WFE modes)
Dedicated RTI windowed watchdog timer per core
Support for Little-Endian (LE) at core level
For more information, see section Compute Cluster Arm Cortex-A53 Subsystem in the device TRM.
6.2.2
Arm Cortex-R5F
The MCU_ARMSS is a dual-core implementation of the Arm Cortex-R5F processor configured for
split/lock operation. It also includes accompanying memories (L1 caches and tightly-coupled memories),
standard Arm® CoreSight™ debug and trace architecture, integrated Vectored Interrupt Manager (VIM),
ECC Aggregators, and various other modules for protocol conversion and address translation for easy
integration into the SoC.
NOTE
ADVANCE INFORMATION
The Cortex-R5F processor is a Cortex-R5 processor that includes the optional Floating Point
Unit (FPU) extension.
The MCU_ARMSS supports the following features:
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Dual Arm Cortex-R5F CPU configuration
– Core revision: r1p3
– Arm®v7-R profile
– Split/Lock operation
• Split mode: Two independently operating cores (Asymetric Multi Processing, no coherence)
• Lock (lockstep) mode: One main operating core with the other operating in lockstep for safety
• Boot-time configurable to be in split or lock mode
– L1 Memory System
• 16KB Instruction Cache
– 4x4KB ways
– SECDED ECC protected per 64 bits
• 16KB Data Cache
– 4x4KB ways
– SECDED ECC protected per 32 bits
• 64KB Tightly-Coupled Memory (TCM) per CPU
– SECDED ECC protected per 32 bits
– Readable/Writable from system
– Split into A and B banks (with B further splitting into B0 and B1 interleaved banks)
– 32KB TCMA (ATCM)
– 16KB TCMB0 (B0TCM)
– 16KB TCMB1 (B1TCM)
– Low interrupt latency with restartable instructions
– Non-Maskable Interrupt (NMI)
– Full-precision Floating Point (VFPv3)
– 16-region Memory Protection Unit (MPU)
– 8 breakpoints
– 8 watchpoints
– Dynamic branch prediction with global history buffer and 4-entry return stack
– CoreSight Debug Access Port (DAP)
– CoreSight ETM-R5 interface
– Performance Monitoring Unit (PMU)
Interfaces
– 64-bit VBUSM master pair (1 read, 1 write) for L3 memory accesses (per core)
– 64-bit VBUSM slave for TCM access (per core)
• Also allows access to cache for debug purposes
– 32-bit VBUSP master for peripheral access (per core)
– 32-bit VBUSP slave configuration port (per core)
– 32-bit VBUSP slave debug port
• Allows access to all MCU_ARMSS internal debug logic
Synchronous clock domain crossing on all interfaces
32-bit to 48-bit Region-based Address Translation (RAT) on memory access masters
– 16 regions
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Integrated Vectored Interrupt Manager (VIM)
– 512 interrupts per core
• Only interrupts connected to R5F Core 0 are available in lock mode
• Each interrupt programmable as either IRQ or FIQ
• Each interrupt has a programmable enable mask
• Each interrupt has a programmable 4-bit priority
– Priority interrupt supported
– Vectored Interrupt Interface
• Compatible with R5F VIC port
• Programmable 32-bit vector address per interrupt
– Address is SECDED error protected
– Default vector addresses provided on DED
• Software interrupt generation
Standard Arm CoreSight debug and trace architecture at the MCU_ARMSS level
– Cross Triggering: Supported by Cross Trigger Interface (CTI) (per CPU) and Cross Trigger Matrix
(CTM) components
– Processor Trace: Supported by Embedded Trace Macrocell (ETM) (per CPU) and Advanced Trace
Bus (ATB) Funnel components
Integrated ECC Aggregators
– Support for error injection to all supported ECC memory blocks to test ECC functionality in safetycritical applications (add-on function from TI)
– One ECC Aggregator per core to cover all RAMs associated with that core
Boot
– From ROM or external memory
– From TCM
The MCU_ARMSS does not support the following features in this device:
• ACP port (no coherence)
• AXI peripheral port (PPX/PPV); corresponds to the VBUSM peripheral port at the MCU_ARMSS level
• Bus parity/ECC
For more information, see section MCU Arm Cortex-R5F Subsystem in the device TRM.
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Accelerators and Coprocessors
PRU_ICSSG
NOTE
The Programmable Real-Time Unit Subsystem and Industrial Communication Subsystem (PRU_ICSSG)
consists of:
• Two 32-bit load/store RISC CPU cores — Programmable Real-Time Units (PRU0 and PRU1)
• Two auxiliary 32-bit load/store RISC CPU cores — Auxiliary Programmable Real-Time Units
(RTU_PRU0 and RTU_PRU1)
• Data RAMs per PRU core
• Instruction RAMs per PRU and per RTU_PRU cores
• Shared RAM
• Peripheral modules: UART0, ECAP0, PWM, IEP0 and IEP1
• Interrupt controller (INTC)
The programmable nature of the PRU cores, along with their access to pins, events and all device
resources, provides flexibility in implementing fast real-time responses, specialized data handling
operations, custom peripheral interfaces, and in offloading tasks from the other processor cores of the
device.
The PRU cores are programmed with a small, deterministic instruction set. Each PRU can operate
independently or in coordination with each other and can also work in coordination with the device-level
host CPU. This interaction between processors is determined by the nature of the firmware loaded into the
PRU’s instruction memory.
The device has integrated three identical PRU_ICSSG subsystems (PRU_ICSSG0, PRU_ICSSG1 and
PRU_ICSSG2).
The PRU_ICSSG subsystem includes the following main features:
• Asynchronous capture [Serial Capture Unit (SCU)] with EnDat® 2.2 protocol and Sigma-Delta
demodulation support
• Two 32-bit load/store RISC CPU cores — Programmable Real-Time Units (PRU0 and PRU1), each
with:
– 20 Enhanced General-Purpose Inputs (EGPI) and 20 Enhanced General-Purpose Outputs (EGPO)
– 12KB program memory per PRU (PRU0_IRAM and PRU1_IRAM) with ECC
– 4KB Broadside (BS) RAM
– MAC (Multiplier with optional Accumulation)
– CRC16/CRC32 HW accelerator
– Byte Swap, for Little/Big Endian conversion
– SUM32 Hardware accelerator for UDP checksum
– Task Manager
– Support of 128-bit wide PSI-L TX port for streaming access to NAVSS0
– Broadside (32-bit) connection to MII_G_RTn (where n= 1 or 2), Filter Data Base (FDB), Scratchpad
Memory (SPAD), SPINLOCK, XFR2VBUS, and RTU_PRUm (where m= 0 or 1)
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This SoC only supports PRU_ICSSG functionality for MII, RGMII, SGMII, and MDIO. The
remaining features of the PRU_ICSSG are not supported for this SoC.
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Two auxiliary Real-Time Transfer Units (RTU_PRU0 and RTU_PRU1), each with:
– 8KB program memory with ECC
– 16KB Broadside (BS) RAM
– MAC (Multiplier with optional Accumulation)
– CRC16/CRC32 HW accelerator
– Byte Swap, for Little/Big Endian conversion
– Two instances of SUM32 Hardware accelerator
– Task Manager
– XFR2TR, for accelerating the internal memory copy of worklist from TRs (Transfer Requests)
– Supports 128-bit wide PSI-L RX/TX port for streaming access through NAVSS0
Scratchpad Memory (SPAD) with 4 banks of 30 x 32-bit registers
64KB Shared general purpose memory RAM with ECC (Data RAM2), shared between PRU0 and
PRU1
Two 8KB Data Memories with ECC (Data RAM0 and Data RAM1)
Two 256-bit VBUSM Master Ports:
– Separate port for each PRUn/RTU_PRUn (where n = 0 or 1)
– Optional address translation for PRUn (where n = 0 or 1) transactions to External Host
16 Software Events generated by 2 PRUs
Two Real-Time Ethernet ports (MII_G_RT1 and MII_G_RT2) configurable to connect to each PRUn
(where n = 0 or 1) to support multiple industrial communication protocols.
– Each of the Ethernet ports can be configured as MII/RGMII/SGMII ports
– NOTE: SGMII mode is supported only for PRU_ICSSG2 instance
Two Industrial Ethernet Peripheral's (IEP0/IEP1) to manage/generate Industrial Ethernet functions such
as time stamping.
– Each of the Industrial Ethernet 64-bit timers support 10 capture and 16 compare events along with
slow and fast compensation.
– Supports up to 4 sets of 3 phased motor control with 12 primary and 12 complimentary
programmable PWM outputs.
– Up to 9 safety events with optional external trip IO per PWM set with hardware glitch filter.
One MDIO port to control external Ethernet PHY
One Enhanced Capture Module (ECAP0)
16550-compatible UART with a dedicated 192MHz clock to support 12-Mbps PROFIBUS
Interrupt Controller (INTC)
– Up to 64 internal events, generated by modules, internal to the PRU_ICSSG
– Up to 96 external events, generated by the system
– Supports up to 20 interrupt channels
– Generation of 20 Host interrupts:
• 2 Host interrupts to PRU0 and PRU1
• 2 Host interrupts to RTU_PRU0 and RTU_PRU1
• 8 Host interrupts, exported from the PRU_ICSSG for signaling the Arm interrupt controllers
(pulse and level provided)
• 8 Host Interrupts for the Task Managers
– Each system event can be enabled and disabled
– Each host event can be enabled and disabled
– Hardware prioritization of events
One 32-bit VBUSP slave (target) port for memory mapped register and internal memories access
Flexible power management support
Integrated 32-bit Interconnect
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The following PRU_ICSSG features are not supported:
• Only 4 of the IEP0 (and none of the IEP1) Ethernet Digital Data Input/Output's of each PRU_ICSSG
are pinned out
• UART Modem interface is not supported
• The following features are not supported only for PRU_ICSSG0 and PRU_ICSSG1:
– 12 Enhanced General-Purpose Inputs (pr<0/1>_pru0_r31_in[31:20]) are not pinned out
– 12 Enhanced General-Purpose Outputs (pr<0/1>_pru0_r31_out[31:20]) are not pinned out
– SGMII mode is not supported on PRU_ICSSG0 and PRU_ICSSG1
• The following features are not supported only for PRU_ICSSG2:
– 14 Enhanced General-Purpose Inputs (pr<2>_pru0_r31_in[31:18]) are not pinned out
– 14 Enhanced General-Purpose Outputs (pr<2>_pru0_r31_out[31:18]) are not pinned out
and
Industrial
ADVANCE INFORMATION
For more information, see section Programmable Real-Time Unit Subsystem
Communication Subsystem - Gigabit (PRU_ICSSG) in the device TRM.
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6.4
6.4.1
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Other Subsystems
DMSC
ADVANCE INFORMATION
Integrated in WKUP domain Device Management and Security Controller (WKUP_DMSC) provides control
over the device boot sequencing, device management, power management, and security. With the
factory-sealed firmware, DMSC main functions include:
• Device management
• On-chip power management and wake-up control
• Device boot configuration and sequence
• Secure boot setup
• Authentication routines (all modes), including R5F island only boot modes
• Decryption routines
• Firewall control for isolation and Security
• Runtime Security Management and resource allocation
• Arm Cortex-M3 based DMSC acts as system security master and protects critical security assets
during run-time. As part of booting on High Security (HS) device, DMSC uses on-chip keys to establish
root-of-trust and authenticate images to reinforce trust. DMSC controls the power management of
device, hence is responsible to bring device cleanly out of reset and enforce clock and reset rules.
DMSC power management functions are critical to bring device to low power modes and sense
wakeup events to bring device back to active state. DMSC acts also as main boot processor and as
such is the very first subsystem that is brought out of reset after device power-on-reset.
Main components of the DMSC are:
• Arm Cortex-M3 processor core
• 160 KB ROM to allow boot sequence, authentication and provide security service (M3 accessible only)
• Two separate local memory banks for Instruction code (I-code) and Data space (D-code) with single
error correction and double error detection
• Firewall enabled 32-bit VBUSP CBASS interconnect
• Interrupt Aggregator with support of up to 80 interrupt inputs to the DMSC
• Four 32-bit Timers
• One RTI/WWDT module capable of issuing warm reset to the SoC
• DMSC control module - contains various control, configuration and status MMRs for power
management functions
• Debug and trace related modules
• Security Manager module for device security management, device type control (GP, EMU, HS),
emulation control, and key management
• AES engine with 128, 192 and 256-bits support
For more information, see section WKUP Device Management and Security Controller (DMSC) in the
device TRM.
6.4.2
MSMC
The Multicore Shared Memory Controller (MSMC) forms the heart of the compute cluster
(COMPUTE_CLUSTER0) providing high-bandwidth resource access both to and from all of the connected
processing elements and the rest of the system. MSMC serves as the data-movement backbone of the
compute cluster.
MSMC supports the following features:
• 2MB (2 banks x 1MB) SRAM with ECC:
– Shared coherent level 2/level 3 memory-mapped SRAM
– Shared coherent level 3 cache
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256-bit processor port bus and 40-bit physical address bus
Coherent unified bi-directional interfaces to connect to processors or device masters
One infrastructure master interface
Single external memory master interface
Supports distributed virtual system
Supports internal DMA engine – DRU (Data Routing Unit)
– DMA in/out L2 SRAM, MSMC, DDR and system
– L2, L3 cache pre-warming and post flushing
Bandwidth management with starvation bound
Two-level QoS support for real-time/nonreal-time split
Security firewall flush support for SRAM/cache and external memory
Functional safety:
– SEC/DED protection on all data and tag memories with hardware scrubbing
– SEC/DED protection on all data pipelines
– Data memory address hamming protection
– Coherent interconnect transaction metadata parity protection
One interconnect messaging interface that supports DMA/prefetch requests to DRU
Trace and debugging support
Supports dynamic power up and power down on PDs low power modes, if required by system
applications
Supports dynamic clock gating on all logic units
Supports low power mode during low-usage processor states
MSMC does not support the following:
• RAM address decode protection
• Direct cache resize changes from one non-zero cache size configuration to another non-zero cache
size configuration. In this case software is required to manually transition down to zero cache size
configuration first, followed by a second transition from zero cache size configuration to the new nonzero cache size configuration.
• MSMC SRAM or SDRAM traffic during an MSMC cache resize transition. The traffic during this
transition has undefined behavior.
For more information, see section Multicore Shared Memory Controller (MSMC) in the device TRM.
6.4.3
NAVSS
6.4.3.1
NAVSS0
Main SoC Navigator Subsystem (NAVSS0) consists of DMA/Queue Management components – UDMA
and Ring Accelerator (UDMASS), Peripherals (Module subsystem [MODSS]), and a North Bridge (NBSS).
UDMASS – UDMASS is the essential part of the DMA Architecture. UDMASS consists of:
• Unified DMA Controller
• Ring Accelerator
• Packet Streaming Interface (PSI-L)
MODSS – MODSS is a collection of peripherals with different system-level functions, for example,
interprocessor communication and time sync, among others. NAVSS0 contains the following modules:
• Mailbox
• Spinlock
• Two Timer Managers (Timer banks)
• Time Stamp Module (CPTS)
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Memory CRC module
Infrastructure components such as:
– CBASS
– Proxies
– Interrupt aggregators
– Interrupt router
NBSS – This is a north bridge infrastructure
6.4.3.2
MCU_NAVSS
MCU Navigator Subsystem (MCU NAVSS) has a subset of the modules of the main NAVSS and is
instantiated in the MCU domain.
MCU Navigator Subsystem consists of DMA/Queue Management components – UDMA and Ring
Accelerator (UDMASS), and Peripherals (Module subsystem [MODSS]).
ADVANCE INFORMATION
UDMASS – UDMASS is the essential part of the DMA Architecture. UDMASS consists of:
• Unified DMA Controller
• Ring Accelerator
• Packet Streaming Interface (PSILSS)
MODSS – MODSS is a collection of peripherals with different system-level functions. NAVSS0 contains
the following modules:
• Memory CRC module
• Infrastructure components such as CBASS, proxies, interrupt aggregators, and an interrupt router
ECC aggregators – for SEC/DED memory protection.
For more information, see sections Main Navigator Subsystem (NAVSS) and MCU Navigator Subsystem
(MCU NAVSS) in the device TRM.
6.4.4
PDMA Controller
The Peripheral DMA is a simple DMA which has been architected to specifically meet the data transfer
needs of peripherals, which perform data transfers using memory mapped registers (MMRs) accessed via
a standard non-coherent bus fabric. The PDMA module is located close to one or more peripherals which
require an external DMA for data movement and is architected to reduce cost by using VBUSP interfaces
and supporting only statically configured Transfer Request (TR) operations.
The PDMA is only responsible for performing the data movement transactions which interact with the
peripherals themselves. Data which is read from a given peripheral is packed by a PDMA source channel
into a PSI-L data stream which is then sent to a remote peer UDMA-P destination channel which then
performs the movement of the data into memory. Likewise, a remote UDMA-P source channel fetches
data from memory and transfers it to a peer PDMA destination channel over PSI-L which then performs
the writes to the peripheral.
The PDMA architecture is intentionally heterogeneous (UDMA-P + PDMA) to right size the data transfer
complexity at each point in the system to match the requirements of whatever is being transferred to or
from. Peripherals are typically FIFO based and do not require multi-dimensional transfers beyond their
FIFO dimensioning requirements, so the PDMA transfer engines are kept simple with only a few
dimensions (typically for sample size and FIFO depth), hardcoded address maps, and simple triggering
capabilities.
Multiple source and destination channels are provided within the PDMA which allow multiple simultaneous
transfer operations to be ongoing. The DMA controller maintains state information for each of the channels
and employs round-robin scheduling between channels in order to share the underlying DMA hardware.
There are five PDMA modules in the device.
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PDMA Features
6.4.4.1.1 MCU_PDMA0 Features
The MCU domain PDMA0 supports the following features:
• Implements CPPI 5.0 compliant third-party Unified Transfer Controller (UTC)
• Provides 0 memory write access units
• Provides 1 memory read access unit (Read Unit 0):
– Provides a 32-bit wide VBUSP read-only master interface for peripheral accesses
– Supports 1 outstanding read
• Supports up to 4 simultaneous source (Rx) channels
• Supports static Transfer Requests (TRs) only
• Provides per-channel buffering:
– Provides 8x128-bit word deep data FIFO for each source channel
– Provides 128-bit wide PSI-L compliant data interface to remote UDMA-P and remote peripherals
The MCU domain PDMA1 supports the following features:
• Implements CPPI 5.0 compliant third-party Unified Transfer Controller (UTC)
• Provides 1 memory write access unit (Write Unit 0):
– Provides a 32-bit wide VBUSP write-only master interface for peripheral accesses.
– Supports 1 outstanding write
• Provides 1 memory read access unit
– Provides a 32-bit wide VBUSP read-only master interface for peripheral accesses
– Supports 1 outstanding read
• Supports up to 19 simultaneous destination (Tx) channels
• Supports up to 19 simultaneous source (Rx) channels
• Supports static Transfer Requests (TRs) only
• Supports MCAN special transfer mode
• Provides per-channel buffering:
– Provides 8x128-bit word deep data FIFO for each destination channel
– Provides 8x128-bit word deep data FIFO for each source channel
– Provides 128-bit wide PSI-L compliant data interface to remote UDMA-P and remote peripherals
– Provides 128-bit wide PSI-L compliant data interface from remote UDMA-P and remote peripherals
6.4.4.1.3 PDMA0 Features
The MAIN domain PDMA0 supports the following features:
• Implements CPPI 5.0 compliant third-party Unified Transfer Controller (UTC)
• Provides 1 memory write access unit (Write Unit 0):
– Provides a 32-bit wide VBUSP write-only master interface for peripheral accesses
– Supports 1 outstanding write
• Provides 1 memory read access unit (Read Unit 0):
– Provides a 32-bit wide VBUSP read-only master interface for peripheral accesses
– Supports 1 outstanding read
• Supports up to 3 simultaneous destination (Tx) channels
• Supports up to 3 simultaneous source (Rx) channels
• Supports static Transfer Requests (TRs) only
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Provides per-channel buffering:
– Provides 8x128-bit word deep data FIFO for each destination channel
– Provides 8x128-bit word deep data FIFO for each source channel
– Provides 128-bit wide PSI-L compliant data interface to remote UDMA-P and remote peripherals
– Provides 128-bit wide PSI-L compliant data interface from remote UDMA-P and remote peripherals
6.4.4.1.4 PDMA1 Features
ADVANCE INFORMATION
The MAIN domain PDMA1 supports the following features:
• Implements CPPI 5.0 compliant third-party Unified Transfer Controller (UTC)
• Provides 1 memory write access unit (Write Unit 0):
– Provides a 32-bit wide VBUSP write-only master interface for peripheral accesses
– Supports 1 outstanding write
• Provides 1 memory read access unit (Read Unit 0):
– Provides a 32-bit wide VBUSP read-only master interface for peripheral accesses
– Supports 1 outstanding read
• Supports up to 23 simultaneous destination (Tx) channels
• Supports up to 23 simultaneous source (Rx) channels
• Supports static Transfer Requests (TRs) only
• Provides per-channel buffering:
– Provides 8x128-bit word deep data FIFO for each destination channel
– Provides 8x128-bit word deep data FIFO for each source channel
– Provides 128-bit wide PSI-L compliant data interface to remote UDMA-P and remote peripherals
– Includes 1 output event transport lane
– Provides 128-bit wide PSI-L compliant data interface from remote UDMA-P and remote peripherals
• Includes support for converting 16 local events to global events with corresponding mapping registers
6.4.4.1.5 PDMA_DEBUG Features
The Debug PDMA supports the following features:
• Implements CPPI 5.0 compliant third-party Unified Transfer Controller (UTC)
• Provides 0 memory write access units
• Provides 1 memory read access unit (Read Unit 0):
– Provides a 64-bit wide VBUSP read-only master interface for peripheral accesses
– Supports 1 outstanding read
• Supports up to 3 simultaneous source (Rx) channels
• Supports static Transfer Requests (TRs) only
• Provides per-channel buffering:
– Provides 8x128-bit word deep data FIFO for each source channel
– Provides 128-bit wide PSI-L compliant data interface to remote UDMA-P and remote peripherals
For more information, see section PDMA Controller in the device TRM.
6.4.5
Peripherals
6.4.5.1
ADC
The Analog-to-Digital Converter (ADC) module contains a single 12-bit ADC which can be multiplexed to
any 1 of 8 analog inputs (channels).
There are total of two ADC modules in the device.
Each ADC module has the following features:
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4 MSPS rate with a 60 MHz SMPL_CLK
Functional Safety Debug Mode
Single-ended or differential input options
Programmable Finite State Machine (FSM) sequencer that supports the following:
– Software initiated start of conversion
– Optional hardware start of conversion (SOC), synchronized to external hardware event
– Single conversion (one-shot mode)
– Continuous conversions (continuous mode)
– Sequence through all enabled steps based on a mask
– Programmable open delay before executing each step
– Programmable sampling delay for each step
– Programmable averaging (16, 8, 4, 2, or 1) of input samples for each step
– Store data in either of two FIFOs – 256-word × 16-bit
– Option to encode input (channel) number with data
– Support for servicing FIFOs via DMA or processor
– Programmable DMA request event (for each FIFO)
Support for the following interrupts and status, with masking:
– Interrupt if AFE fails to return end of conversion (EOC)
– Interrupt after a sequence of conversions (all non-masked steps)
– Interrupt for FIFO threshold levels
– Interrupt if sampled data is out of a programmable range
– Interrupt for FIFO overflow and underflow conditions
– Status bit to indicate if ADC is busy converting
ADC Not Supported Features:
• No packing of 16-bit FIFO data onto 32-bit DMA bus
• Big endian
• Support only 32-bit aligned read/write accesses on the MCU_CBASS0/DMA ports
For more information, see section Analog-to-Digital Converter (ADC) in the device TRM.
6.4.5.2
CAL
CALSS0 is a very flexible subsystem that enables connection to multiple cameras supporting MIPI CSI-2
over D-PHY serial interface, a LVDS serial interface, and a traditional parallel interface. It also includes an
internal write DMA engine connected to VBUSM interface.
The device includes one instantiation of CAL Subsystem named CALSS0, with a single companion
CAMERARX0 instance.
The device CALSS provides the followng main features:
• Up to 250 MHz processing clock rate
• Interfaces:
– One PHY Protocol Interfaces (PPI) to shared companion MIPI D-PHY compliant receiver
(CAMERARX)
– Serial Configuration Interface (SCP) to CAMERARX
– 32-bit slave configuration interface (OCPC) to the system interconnect
– 128-bit master data interface (OCPO) to the system interconnect and memory
• On-the-fly functional mode: A byte stream received from PPI is interpreted as a MIPI CSI-2 stream.
Pixels are extracted and sent to the system memory.
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MIPI CSI-2 low level protocol support:
– Up to 8 contexts (VCT + DT combinations)
– Data lane merger
– Error detection/correction (CRC/ECC)
– Re-synchronization FIFO
Up to four [4] independent pixel processing contexts:
– All primary and secondary MIPI CSI-2 formats supported
– Extract pixels from byte stream
– DPCM decompression (4 pixels/cycle for predictor1; 1 pixel/cycle for predictor2)
– DPCM compression (2 pixels/cycle for predictor1; predictor2 is not supported)
– Pixel packing into a byte stream (for memory storage)
Up to eight [8] independent write DMA contexts:
– Write header, pixel, or attribute data
– Horizontal cropping
– Pack data from independent streams into efficient OCP transactions
– 1D and 2D addressing modes (only INCR bursts)
– Resynchronize on line boundaries (for TxBuffer overflows)
– Linear, circular, and sub-sampled addressing modes
CALSS does not support the following features:
• ECC on internal RAMs
For more information, see section Camera Adapter Layer (CAL) Subsystem in the device TRM.
6.4.5.3
CPSW2G
The two-port Gigabit Ethernet MAC (MCU_CPSW0) subsystem provides Ethernet packet communication
for the device and is configured in a similar manner as a two-port Ethernet switch. MCU_CPSW0 features
the Reduced Gigabit Media Independent Interface (RGMII), Reduced Media Independent Interface (RMII),
and the Management Data Input/Output (MDIO) interface for physical layer device (PHY) management.
The MCU_CPSW0 subsystem provides the following features:
• One Ethernet port (port 1) with selectable RGMII and RMII interfaces and an internal Communications
Port Programming Interface (CPPI) port (port 0)
• Synchronous 10/100/1000 Mbit operation
• Flexible logical FIFO-based packet buffer structure
• Eight priority level Quality Of Service (QOS) support (802.1p)
• Support for Audio/Video Bridging (P802.1Qav/D6.0)
• Support for IEEE 1588 Clock Synchronization (2008 Annex D, Annex E and Annex F)
– Timestamp module capable of time stamping external timesync events like Pulse-Per-Second and
also generating Pulse-Per-Second outputs
– CPTS module that supports time stamping for IEEE1588 with support for 4 hardware push events
and generation of compare output pulses
• DSCP Priority Mapping (IPv4 and IPv6)
• Energy Efficient Ethernet (EEE) support (802.3az)
• Flow Control (802.3x) Support
• Non Blocking switch fabric
• Time Sensitive Network Support
– IEEE P902.3br/D2.0 Interspersing Express Traffic
– IEEE 802.1Qbv/D2.2 Enhancements for Scheduled Traffic
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Address Lookup Engine (ALE)
– Configurable number of addresses plus VLANs
– Wire rate lookup
– Host controlled time-based aging and/or auto-aging
– Spanning tree support
– L2 address lock and L2 filtering support
– MAC authentication (802.1x)
– Receive-based or destination-based Multicast and Broadcast rate limits
– MAC address blocking
– Source port locking
– OUI (Vendor ID) host accept/deny feature
– Configurable number of classifier/policers
– VLAN support
• 802.1Q compliant
– Auto add port VLAN for untagged frames on ingress
– Auto VLAN removal on egress and auto pad to minimum frame size
EtherStats and 802.3Stats Remote network Monitoring (RMON) statistics gathering (per port)
Ethernet CRC selectable per port
Ethernet Mac transmit to Ethernet Mac receive Loopback mode (digital loopback) supported
CPSGMII Loopback Modes (transmit to receive)
Maximum frame size of 2024 bytes
Management Data Input/Output (MDIO) module for PHY Management with Clause 45 support
Programmable interrupt control with selected interrupt pacing
Host port CPPI Streaming Packet Interface (CPPI_GCLK)
Flow Control Support (802.3x)
Digital loopback and FIFO loopback modes supported
Emulation support
Full duplex mode supported in 10/100/1000 Mbps. Half-duplex mode supported only in 10/100 Mbps
modes only.
RAM Error Detection and Correction (SECDED)
The following MCU_CPSW0 features are not supported:
• Maximum frame size of 9600 bytes
• MII/ GMII Mode
• SGMII Mode
• MACSEC
• Synchronous Ethernet
• Software reset
• Ethernet Port Reset Isolation
• Rate-limiting is not supported in half-duplex mode
• Dual VLAN switch operations are not supported
• Gigabit half-duplex mode is not supported (10/100 Mbps half-duplex mode is supported).
• RGMII Internal Delay Mode disabled.
For more information, see section Gigabit Ethernet MAC (MCU_CPSW0) in the device TRM.
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DCC
The Dual Clock Comparator (DCC) is used to determine the accuracy of a clock signal during the time
execution of an application. Specifically, the DCC is designed to detect drifts from the expected clock
frequency. The desired accuracy can be programed based on calculation for each application. The DCC
measures the frequency of a selectable clock source using another input clock as a reference.
The device has eleven instances of DCC modules.
The DCC uses two independent clock sources to detect when one is out of spec. Each DCC module
implements the following features:
• Two independent counter blocks count clock pulses from each clock source
• Each counter block is programmable, however, for proper operation the counters must be programmed
with seed values that respect the ratio of the two clock frequencies
• Configurable timebase for error signal
• Error signal generation when one of the clocks is out of spec
• Clock frequency measurement
For more information, see section Dual Clock Comparator (DCC) in the device TRM.
ADVANCE INFORMATION
6.4.5.5
DDRSS
The DDR subsystem in this device comprises DDR controller, DDR PHY and wrapper logic to integrate
these blocks in the device. The DDR subsystem is referred to as DDRSS0 and is used to provide an
interface to external SDRAM devices which can be utilized for storing program or data. DDRSS0 is
accessed via MSMC, and not directly through the system interconnect.
The DDRSS0 supports:
• Memory Types:
– DDR3L
– DDR4
– LPDDR4
• Memory Bus Features:
– 39-bit width with ECC (32 bits for data and 7 bits for ECC)
– 1/2 width (22-bit) mode via software configuration
– 1/4 width (13-bit) mode via software configuration
– Up to 2 ranks (LPDDR4 only)
– SDRAM address range up to 32 GB
• System Bus Interface:
– 256-bit data width
– Clock asynchronous to DDR clock
– Little endian only
– Address aliasing prevention to block accesses to unpopulated SDRAM region
• Configuration Bus Interface:
– 32-bit data width
– Linear incrementing addressing mode
– 32-bit aligned accesses only
– Little endian only
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Key Features:
– Full coherency across all commands
– Bank interleaving
– Priority based scheduling
– Scheduling based on bank openness
– Class of Service (CoS)
• Three latency classes supported
• Programmable counters to tune CoS
– Read/write scheduling to avoid turn-around time
– Prioritized refresh scheduling
– Dynamic change of refresh rate via software for extended temperatures
– Statistical counters for performance management
ECC Features:
– SEC/DED for 32-bit interface (39-bit with ECC)
• Supported only for DDR3 and DDR4
– SEC/DED for 16-bit interface (22-bit with ECC)
• Supported for DDR3, DDR4, and LPDDR4
– SEC/DED for 8-bit interface (13-bit with ECC)
• Supported only for DDR3 and DDR4
– Read-modify-write ECC for sub-word writes
– ECC address error logging
– Statistical counters for counting ECC errors
– Injecting ECC errors during normal operation for validation
– Automatic ECC scrub operation inside the DDR controller for any read command received which
has led to a single-bit error.
• At any time, only one outstanding ECC scrub operation is allowed inside the DDR controller
Low Power Features:
– All power modes defined by JEDEC (clock stop for LPDDRx, self-refresh, power-down, etc.)
– Self-refresh entry and exit via software or clock stop req/ack
– System bus clock stop via clock stop request when controller is idle
– Automatic idle power saving mode when no or low activity is detected
– DDR and system bus clock frequency change using self-refresh via software or clock stop request
– Turning off SoC power after DDR is put into self-refresh (DDR reset and CKE IO retention)
Functional Safety Features:
– ECC on data
– Parity on address and command
– ECC on internal RAMs
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DDR PHY Features:
– Partial data macro use for ECC in 39-bit and 22-bit mode
– Automatic and software controllable DDR-PHY and I/Os initialization and calibration (ZQ)
– Automatic and software controllable delay line calibrations with voltage and temeprature (VT)
compensation
– Automatic and software controllable write levelling with VT compensation
– Automatic read DQS gating training per rank with VT compensation
– Automatic and software controllable DQ/DQS eye training per rank
– Automatic and software controllable read and write data bit deskew
– Automatic and software controllable Command/Address (CA) levelling with VT compensation for
LPDDR4
– Automatic and software controllable CA bit deskew for LPDDR4
– Refreshes to SDRAM during leveling and training
– Any bit in the byte lane as prime bit for write leveling and read trainings
– No seeding requirement based on board topology for any of the leveling and training algorithms
– Max channel length of 3 inches with controlled impedance for command and data channels
– Dynamic/automatic I/O receiver disable when read transfer is not on going
– Capability of disabling unused data macros and I/Os when not in use
DDRSS0 does not support the following:
• 4-bit wide DDR4 devices
• UDIMMs
• SODIMMs
• RDIMMs
• LRDIMMs
• Address mirroring for DIMMs
• Data bus obfuscation or any other kind of encryption
• Automatic periodic scrubbing of SDRAM for ECC
• 32-bit with ECC (39-bit) for LPDDR4
• 8-bit with ECC (13-bit) for LPDDR4
• 8-bit without ECC for LPDDR4
• Two independent 16-bit channel operation for LPDDR4
• DDR4 DBI mode
• DDR3 SDRAMs
• DDR3U SDRAMs
• LPDDR3 SDRAMs
• LPDDR2 SDRAMs
• LPDDR4X SDRAMs
• Only single rank is supported for DDR3L and DDR4
• Hardware FFC (Fast Frequency Change)
• DDR4 Geardown mode
• Write data CRC for DDR4 when ECC is enabled
• PLL bypass mode for AC and Data macros
For more information, see section DDR Subsystem (DDRSS) in the device TRM.
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DSS
The Display Subsystem (DSS) is a flexible, multi-pipeline subsystem that supports high-resolution display
outputs. DSS includes input pipelines providing multi-layer blending with transparency to enable on-the-fly
composition. Various pixel processing capabilities are supported, such as color space conversion and
scaling, among others. DSS includes a DMA engine, which allows direct access to the frame buffer
(device system memory). Display outputs can connect seamlessly to an Open LVDS Display Interface
transmitter (OLDITX), or can directly drive device pads as a parallel video output interface.
DSS includes a Display Controller (DISPC), with the following main features:
• Internal DMA engine:
– Support for 1D DMA transfers only
– Support for 48-bit addressable memory space
– No support for rotation and memory fragmentation
– Integrated buffers between DMA engine and video pipelines
– Programmable buffer thresholds
– Self-refresh using the DMA buffers (outputing data on display only from the DMA buffer)
– Arbitration between normal/low priority pipelines
– On-the-fly support for source image flip along X and Y axis (flip/mirror support)
– Support for up to 4K-pixels wide frame buffer for 8/16/32/64-bit per pixel, if the frame buffer is used
without scaling (that is, no upscale/downscale) in the video pipelines
– Support for up to 2560-pixels wide frame buffer for 8/16-bit per pixel, if scaling is enabled in video
pipelines
– Support for up to 1280-pixels wide frame buffer for 32-bit per pixel, if scaling is enabled in video
pipelines
– Support for up to 640-pixels wide frame buffer for 64-bit per pixel, if scaling is enabled in video
pipelines
– Support for secure access to firewall protected frame buffer in DDR memory
– Support for MFLAG mechanism to indicate critical fullness of DMA buffer (close to underflow for a
video pipeline)
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The device includes one instantiation of DSS named DSS0 (with a single OLDITX0 instance).
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One Video Pipeline (VID):
– RGB input source pixel formats support:
• BITMAP1, BITMAP2, BITMAP4, BITMAP8
• ARGB16-4444, ABGR16-4444, RGBA16-4444, RGB16-565, BGR16-565, ARGB16-1555,
ABGR16-1555
• RGB16-565/BGR16-565 with a separate A8 plane
• RGB24-888, BGR24-888
• ARGB32-8888, ABGR32-8888, BGRA32-8888, RGBA32-8888, ARGB32-2101010, ABGR322101010
• ARGB64-16161616, RGBA64-16161616
• Additionally, equivalent RGBx, xRGB, xBGR, and BGRx pixel formats defined, considering that
A component of RGBA, ARGB, ABGR, BGRA pixel formats is ignored by DSS hardware (for
example, ARGB -> xRGB, where A can be ignored by not selecting alpha pixel)
• Pre-multiplied ARGB/RGBA formats
– YUV input source pixel formats support:
• Packed: YUV422-UYVY, YUV422-YUV2
• 2-plane: YUV420-NV12, YUV420-NV21
• 8-bit per component support for all YUV formats
• 10/12-bit per component packed/unpacked source format support for YUV420/422 (internally
processed as 8-bit component data)
– Programmable poly-phase filter (scaler):
• Independent horizontal and vertical resampling: up-sampling (up to x16), and down-sampling
(down to 1/4)
• Maximum input width supported: 1280 pixels (using 32-bit pixels and 5-tap mode), 2560 pixels
(using 16-bit pixels and 5-tap mode), and 2560 pixels (using 32-bit pixels and 3-tap mode)
• No limitation on the input height
• Supported input pixel formats: ARGB48-12121212, YUV422-UYVY, YUV422-YUV2, and
YUV420-NV12. The alpha channel is rescaled like the R, G and B color components. 16 phases
with symmetrical coefficients are implemented.
– Programmable color space conversion (CSC) from YUV422/YUV420 (after chroma upsampled to
YUV444 using the scaler) into ARGB48-12121212
– Programmable Brightness/Contrast/Hue/Saturation using the CSC block
– Programmable VC1 range mapping
– Luma Key generation
– 256 x 24-bit entries color look-up table (CLUT), used either to convert BITMAP (1, 2, 4, or 8-bit
indexed formats) into RGB format, or for RGB to RGB inverse gamma correction
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One Video Lite Pipeline (VIDL1)
– RGB input source pixel formats support:
• BITMAP1, BITMAP2, BITMAP4, BITMAP8
• ARGB16-4444, ABGR16-4444, RGBA16-4444, RGB16-565, BGR16-565, ARGB16-1555,
ABGR16-1555
• RGB16-565/BGR16-565 with a separate A8 plane
• RGB24-888, BGR24-888
• ARGB32-8888, ABGR32-8888, BGRA32-8888, RGBA32-8888, ARGB32-2101010, ABGR322101010
• ARGB64-16161616, RGBA64-16161616
• Additionally, equivalent RGBx, xRGB, xBGR, and BGRx pixel formats defined, considering that
A component of RGBA, ARGB, ABGR, BGRA pixel formats is ignored by DSS hardware (for
example, ARGB -> xRGB, where A can be ignored by not selecting alpha pixel)
• Pre-multiplied ARGB/RGBA formats
– YUV input source pixel formats support:
• Packed: YUV422-UYVY, YUV422-YUV2
• 2-plane: YUV420-NV12, YUV420-NV21
• 8-bit per component support for all YUV formats
• 10/12-bit per component packed/unpacked source format support for YUV420/422 (internally
processed as 8-bit component data)
– YUV420 to YUV422 chroma upsampling using an average filter
– YUV422 to YUV444 chroma upsampling using a 4-tap filter based on Catmull-Rom algorithm
– Programmable color space conversion (CSC) from YUV422/YUV420 into ARGB48-12121212
– Programmable Brightness/Contrast/Hue/Saturation using the CSC block
– Programmable VC1 range mapping
– Luma Key generation
– 256 x 24-bit entries color look-up table (CLUT), used either to convert BITMAP (1, 2, 4, or 8-bit
indexed formats) into RGB format, or for RGB to RGB inverse gamma correction
Two Overlay Managers (OVR1 and OVR2):
– Input pixel format: ARGB48-12121212
– Output pixel format: ARGB48-12121212
– Transparency color key (source and destination)
– Programmable background color
– Alpha blending support: embedded pixel alpha (ARGB and RGBA), global pixel, combination of
global pixel and pixel alpha
– Z-order programmable (full flexibility)
– Color bar test pattern insertion
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Two Video Port outputs (VP1 and VP2):
– Up to 24 bits per pixel on the output interface (selection between 12, 16, 18, or 24 bits)
– Independent programmable timing generator for each VP output to support up to 165 MHz pixel
clock frequency for video formats defined in CEA-861-E and VESA-DMT standards (including
1600x1200@60fps or 1920x1200@60fps with reduced blanking)
– Independent programmable 8-bit gamma correction support on each VP output
– Fully programmable color space conversion matrix to serve as color phase rotation (CPR) and/or as
brightness/contrast/saturation control on the combined output
– Independent programmable multiple cycles output format on 8/9/12/16-bit time division multiplexed
(TDM) interface for each VP output
– Configurable VP output mode: progressive or interlaced mode
– Selection between RGB and YUV422 output pixel format (YUV422 only available when a BT mode
is enabled)
Safety Features:
– Supports up to 4 programmable (position/size) safety check regions on each display output
– Support for 1 safety check region on each input video pipeline output
– Support for MISR (Multiple Input Signature Register) on each safety region, used to perform data
correctness check and/or freeze frame detection
DSS integrates a single-link Open LVDS Display Interface transmitter (OLDITX) with the following main
features:
• Up to 170MHz input pixel data interface support: RGB[23:0], VS, HS, DE. Limited by the maximum
data rate provided by the DISPC video port output connected to OLDITX.
• Single (non-duplicate) OLDI output link mode.
• 18-bit or 24-bit output with OLDI mapping modes (three or four LVDS data channels, one clock
channel).
• LVDS signaling: Compliant with ANSI/TIA/EIA644-A standard (Electrical Characteristics of Low Voltage
Differential Signaling (LVDS) Interface Circuits).
• LVDS transmit throughput performance: WUXGA (1920x1200@60), 162 MHz pixel clock resolution.
• Test support features: Built-in pattern generator; loopback mode.
DSS provides two interfaces to device interconnect:
• One 128-bit master port (with MFLAG support), used by the DISPC DMA engine to read data from
device system memory.
• One 32-bit slave port, used for configuration of the memory mapped registers inside DSS.
DISPC does not support the following features:
• Write-back pipeline for memory-to-memory composition
• 2-D tiled buffer access
• On-the-fly rotation
• Compressed data format
• Fragmented frame buffers
• YUV formats (YUV420/YUV422) on the video pipeline inputs and video port outputs (BT.656/BT.1120
modes)
OLDITX does not support the following features:
• Single link duplication mode
• Dual link (master or slave) mode
• DC balanced mode on LVDS output
• Hot plug detection
• EDID/DDC
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Gamma correction
Internal PLL clock recovery
Digital display information protection
For more information, see section Display Subsystem (DSS) in the device TRM.
6.4.5.7
ЕCAP
The ECAP module includes the following features:
• 32-bit time base counter
• 4-event time-stamp registers (each 32 bits)
• Edge polarity selection for up to four sequenced time-stamp capture events
• Interrupt on any of the four events
• Single shot capture of up to four event time-stamps
• Continuous mode capture of time-stamps in a four-deep circular buffer
• Absolute time-stamp capture
• Difference (Delta) mode time-stamp capture
• All above resources dedicated to a single input pin
• When not used in capture mode, the ECAP module can be configured as a single channel PWM
output.
For more information, see section Enhanced Capture (ECAP) Module in the device TRM.
6.4.5.8
EPWM
An effective PWM peripheral must be able to generate complex pulse width waveforms with minimal CPU
overhead or intervention. It needs to be highly programmable and very flexible while being easy to
understand and use. The EPWM unit described here addresses these requirements by allocating all
needed timing and control resources on a per PWM channel basis. Cross coupling or sharing of resources
has been avoided; instead, the EPWM is built up from smaller single channel modules with separate
resources and that can operate together as required to form a system. This modular approach results in
an orthogonal architecture and provides a more transparent view of the peripheral structure, helping users
to understand its operation quickly.
In the further description the letter x within a signal or module name is used to indicate a generic EPWM
instance on a device. For example, output signals EPWMxA and EPWMxB refer to the output signals from
the EPWMx instance. Thus, EPWM1A and EPWM1B belong to EPWM1, EPWM2A and EPWM2B belong
to EPWM2, and so forth.
Additionally, the EPWM integration allows this synchronization scheme to be extended to the capture
peripheral modules (ECAP). The number of modules is device-dependent and based on target application
needs. Modules can also operate stand-alone.
The device has six instances of EPWM modules.
Each EPWM module supports the following features:
• Dedicated 16-bit time-base counter with period and frequency control
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The enhanced Capture (ECAP) module can be used for:
• Sample rate measurements of audio inputs
• Speed measurements of rotating machinery (for example, toothed sprockets sensed via Hall sensors)
• Elapsed time measurements between position sensor pulses
• Period and duty cycle measurements of pulse train signals
• Decoding current or voltage amplitude derived from duty cycle encoded current/voltage sensors.
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Two PWM outputs (EPWMxA and EPWMxB) that can be used in the following configurations:
– Two independent PWM outputs with single-edge operation
– Two independent PWM outputs with dual-edge symmetric operation
– One independent PWM output with dual-edge asymmetric operation
Asynchronous override control of PWM signals through software
Programmable phase-control support for lag or lead operation relative to other EPWM modules
Hardware-locked (synchronized) phase relationship on a cycle-by-cycle basis
Dead-band generation with independent rising and falling edge delay control
Programmable trip zone allocation of both cycle-by-cycle trip and one-shot trip on fault conditions
A trip condition can force either high, low, or high-impedance state logic levels at PWM outputs
Allows events to trigger both CPU interrupts and ADC start of conversions
Programmable event prescaling minimizes CPU overhead on interrupts
PWM chopping by high-frequency carrier signal, useful for pulse transformer gate drives
High-resolution module with programmable delay line
– Programmable on a per PWM period basis
– Can be inserted either on the rising edge or falling edge of the PWM pulse or both or not at all.
EHRPWM Not Supported Features:
• EPWM digital comparator modules are not supported
For more information, see section Enhanced Pulse Width Modulation (EPWM) Module in the device TRM.
6.4.5.9
ELM
The ELM is used with the GPMC. Syndrome polynomials generated on-the-fly when reading a NAND flash
page and stored in GPMC registers are passed to the ELM. A host processor can then correct the data
block by flipping the bits to which the ELM error-location outputs point.
When reading from NAND flash memories, some level of error-correction is required. In the case of NAND
modules with no internal correction capability, sometimes referred to as bare NANDs, the correction
process is delegated to the memory controller. ELM can be also used to support parallel NOR flash or
NAND flash.
The General-Purpose Memory Controller (GPMC) probes data read from an external NAND flash and
uses this to compute checksum-like information, called syndrome polynomials, on a per-block basis. Each
syndrome polynomial gives a status of the read operations for a full block, including 512 bytes of data,
parity bits, and an optional spare-area data field, with a maximum block size of 1023 bytes. Computation
is based on a Bose-Chaudhuri-Hocquenghem (BCH) algorithm. The ELM extracts error addresses from
these syndrome polynomials.
Based on the syndrome polynomial value, the ELM can detect errors, compute the number of errors, and
give the location of each error bit. The actual data is not required to complete the error-correction
algorithm. Errors can be reported anywhere in the NAND flash block, including in the parity bits.
The maximum acceptable number of errors that can be corrected depends on a programmable
configuration parameter. 4-, 8-, and 16-bit error-correction levels are supported. The ELM depends on a
static and fixed definition of the generator polynomial for each error-correction level that corresponds to
the generator polynomials defined in the GPMC (there are three fixed polynomial for the three correction
error levels). A larger number of errors than the programmed error-correction level may be detected, but
the ELM cannot correct them all. The offending block is then tagged as uncorrectable in the associated
computation exit status register. If the computation is successful, that is, if the number of errors detected
does not exceed the maximum value authorized for the chosen correction capability, the exit status
register contains the information on the number of detected errors.
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When the error-location process completes, an interrupt is triggered to inform the software that its status
can be checked. The number of detected errors and their locations in the NAND block can be retrieved
from the module through register accesses.
The ELM has the following features:
• 4, 8, and 16 bits per 512-byte block error-location, based on BCH algorithms
• Eight simultaneous processing contexts
• Page-based and continuous modes
• Interrupt generation on error-location process completion:
– When the full page has been processed in page mode
– For each syndrome polynomial in continuous mode.
The following features are not supported on this family of devices:
• Local power management of clock activity
For more information, see section Error Location Module (ELM) in the device TRM.
The Error Signaling Module (ESM) aggregates safety-related events and/or errors from throughout the
device into one location. It can signal both low and high priority interrupts to a processor to deal with a
safety event and/or manipulate an I/O error pin to signal an external hardware that an error has occurred.
Therefore an external controller is able to reset the device or keep the system in a safe, known state.
The device has three instances of ESM modules.
Each ESM module implements the following features:
• Up to 1024 error event inputs
– Implemented in groups of 32 events
– Level or Pulse inputs (Pulse inputs are triple redundant)
• Selectable low and high priority interrupt error pin prioritization of each error event
• Error pin to signal severe device failure
• Configurable timebase for error signal
• Error forcing capability
• Internal redundant flops on safety critical fields
For more information, see section Error Signaling Module (ESM) in the device TRM.
6.4.5.11 EQEP
The Enhanced Quadrature Encoder Pulse (EQEP) peripheral is used for direct interface with a linear or
rotary incremental encoder to get position, direction and speed information from a rotating machine for use
in high performance motion and position control system. The disk of an incremental encoder is patterned
with a single track of slots patterns. These slots create an alternating pattern of dark and light lines. The
disk count is defined as the number of dark/light line pairs that occur per revolution (lines per revolution).
As a rule, a second track is added to generate a signal that occurs once per revolution (index signal:
QEPI), which can be used to indicate an absolute position. Encoder manufacturers identify the index pulse
using different terms such as index, marker, home position and zero reference.
To derive direction information, the lines on the disk are read out by two different photo-elements that
"look" at the disk pattern with a mechanical shift of 1/4 the pitch of a line pair between them. This shift is
realized with a reticle or mask that restricts the view of the photo-element to the desired part of the disk
lines. As the disk rotates, the two photo-elements generate signals that are shifted 90 degrees out of
phase from each other. These are commonly called the quadrature QEPA and QEPB signals. The
clockwise direction for most encoders is defined as the QEPA channel going positive before the QEPB
channel and vise versa.
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The encoder wheel typically makes one revolution for every revolution of the motor or the wheel may be at
a geared rotation ratio with respect to the motor. Therefore, the frequency of the digital signal coming from
the QEPA and QEPB outputs varies proportionally with the velocity of the motor. For example, a 2000-line
encoder directly coupled to a motor running at 5000 revolutions per minute (rpm) results in a frequency of
166.6 kHz, so by measuring the frequency of either the QEPA or QEPB output, the processor can
determine the velocity of the motor.
The EQEP module includes the following features:
• EQEP inputs (A/B/INDEX and STROBE) are available at chip level
• EQEP phase error output is also available.
The following EQEP features are not supported:
• EQEP quadrature outputs (A and B) are not pinned out
For more information, see section Enhanced Quadrature Encoder Pulse (EQEP) Module in the device
TRM.
6.4.5.12 GPIO
ADVANCE INFORMATION
The General-Purpose Input/Output (GPIO) peripheral provides dedicated general-purpose pins that can be
configured as either inputs or outputs. When configured as an output, the user can write to an internal
register to control the state driven on the output pin. When configured as an input, user can obtain the
state of the input by reading the state of an internal register.
In addition, the GPIO peripheral can produce host CPU interrupts and DMA synchronization events in
different interrupt/event generation modes.
The device has three instances of GPIO modules. The GPIO pins are grouped into banks (16 pins per
bank and 9 banks per module), which means that each GPIO module provides up to 144 dedicated
general-purpose pins with input and output capabilities; thus, the general-purpose interface supports up to
432 (3 instances × (9 banks × 16 pins)) pins. Since WKUP_GPIO0_[56:143], GPIO0_[96:143], and
GPIO1_[90:143] are reserved in this device, general purpose interface supports up to 242 pins.
Each channel in the GPIO modules has the following features:
• Supports 9 banks of 16 GPIO signals
• Supports up to 9 banks of interrupt capable GPIOs
• Interrupts:
– Can enable interrupts for each bank of 16 GPIO signals
– Interrupts can be triggered by rising and/or falling edge, specified for each interrupt capable GPIO
signal
• Set/clear functionality:
– Firmware writes 1 to corresponding bit position(s) to set or to clear GPIO signal(s). This allows
multiple firmware processes to toggle GPIO output signals without critical section protection
(disable interrupts, program GPIO, re-enable interrupts, to prevent context switching to another
process during GPIO programming).
• Separate Input/Output registers:
– If preferred by firmware, some GPIO output signals can be toggled by direct write to the output
register(s) in addition to set/clear.
– Output register, when read in, reflects output drive status. This, in addition to the input register
reflecting pin status, allows wired logic be implemented.
GPIO do not support the following features:
• The following apply to WKUP_GPIO0:
– WKUP_GPIO0_[56:143] are not pinned out.
– Interrupts [56:143] are not pinned out.
– Bank Interrupts [8:4] are not pinned out.
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The following apply to GPIO0:
– GPIO0_[96:143] are not pinned out.
– Interrupts [96:143] are not pinned out.
– Bank Interrupts [8:6] are not pinned out.
The following apply to GPIO1:
– GPIO1_[90:143] are not pinned out.
– Interrupts [90:143] are not pinned out.
– Bank Interrupts [8:6] are not pinned out.
– GPI[10] and GPI[77] buffer is input only.
– Interrupt [10] and [77] buffer is output only.
– GPO[12] buffer is output only.
For more information, see section General-Purpose Interface (GPIO) in the device TRM.
The General-Purpose Memory Controller is a unified memory controller dedicated for interfacing with
external memory devices like:
• Asynchronous SRAM-like memories and application-specific integrated circuit (ASIC) devices
• Asynchronous, synchronous, and page mode (available only in non-multiplexed mode) burst NOR flash
devices
• NAND flash
• Pseudo-SRAM devices
The main features of the GPMC are:
• 8- or 16-bit-wide data path to external memory device
• Supports up to 4 chip select regions of programmable size and programmable base addresses in a
total address space of 1GB
• Supports on-the-fly error code detection using the Bose-ChaudhurI-Hocquenghem (BCH) (t = 4, 8, or
16) or Hamming code to improve the reliability of NAND with a minimum effect on software (NAND
flash with 512-byte page size or greater)
• Fully pipelined operation for optimal memory bandwidth usage
• The clock to the external memory is provided from GPMC_FICLK divided by 1, 2, 3, or 4
• Supports programmable autoclock gating when no access is detected
• Independent and programmable control signal timing parameters for setup and hold time on a per-chip
basis. Parameters are set according to the memory device timing parameters with a timing granularity
of one GPMC_FICLK clock cycle.
• Flexible internal access time control (wait state) and flexible handshake mode using external WAIT pin
monitoring
• Support bus keeping
• Support bus turnaround
• Prefetch and write-posting engine associated with DMA controller at system level to achieve full
performance from the NAND device with minimum effect on NOR/SRAM concurrent access
• 32-bit interconnect slave interface which supports non-wrapping and wrapping burst of up to 16x32
bits.
The GPMC supports the following various access types:
• Asynchronous read/write access
• Asynchronous read page access (4, 8, and 16 Word16)
• Synchronous read/write access
• Synchronous read/write burst access without wrap capability (4, 8 and 16 Word16)
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6.4.5.13 GPMC
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Synchronous read/write burst access with wrap capability (4, 8 and 16 Word16)
Address-data-multiplexed (AD) access
Address-address-data (AAD) multiplexed access
Little-endian access only
The GPMC can communicate with a wide range of external devices:
• External asynchronous or synchronous 8-bit wide memory or device (non burst device)
• External asynchronous or synchronous 16-bit wide memory or device
• External 16-bit non-multiplexed NOR flash device
• External 16-bit address and data multiplexed NOR Flash device
• External 8-bit and 16-bit NAND flash device
• External 16-bit pseudo-SRAM (pSRAM) device
ADVANCE INFORMATION
The following features are not supported on this family of devices:
• DMA mode is not supported.
• WAIT[3-2] are not pinned out. All CS regions must use WAIT0 or WAIT1.
• Asynchronous page write mode is not supported.
• Multiple write access in asynchronous mode is not supported.
• Multiple read is not supported in address/data-multiplexed and AAD-multiplexed modes.
For more information, see section General-Purpose Memory Controller (GPMC) in the device TRM.
6.4.5.14 HYPERBUS
The HyperBus module is a part of the device Flash Subsystem (FSS).
The HyperBus module is a low pin count memory interface that provides high read/write performance. The
HyperBus module connects to HyperBus memory (HyperFlash or HyperRAM) and uses simple HyperBus
protocol for read and write transactions.
There is one HyperBus module inside the device. The HyperBus module includes one HyperBus Memory
Controller (HBMC).
HyperBus module supports the following features:
• Support for Cypress® HyperFlash and HyperRAM
• Up to 166 MHz maximum memory bus operation for reads
– Supports up to 166 MHz dual data rate (333 MBps) flash devices for system requiring rapid boot or
instant-on displays
– Supports up to 333 MBps external pseudo-RAM (HyperRAM) for systems
• Low pin count interface with LVCMOS I/O pins (can be muxed with other FSS interfaces (OSPIs))
• Two memory chip selects
• Linear incrementing mode for reads and writes
• Up to 16 outstanding read transactions
• Asynchronous bus clock
HyperBus Not Supported Features:
• Cache-line wrap and fixed address modes for reads or writes
• General Purpose Output register of the HBMC is not used
For more information, see section HyperBus Interface in the device TRM.
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6.4.5.15 I2C
The device contains six multimaster Inter-Integrated Circuit (I2C) controllers each of which provides an
interface between a local host (LH), such as an Arm and any I2C-bus-compatible device that connects via
the I2C serial bus. External components attached to the I2C bus can serially transmit and receive up to 8
bits of data to and from the LH device through the 2-wire I2C interface.
Each multimaster I2C module can be configured to act like a slave or master I2C-compatible device.
The WKUP_I2C0 and MCU_I2C0 controllers have dedicated I2C compliant open drain buffers, and
support fast mode (up to 400 Kbps).The I2C0, I2C1, I2C2, and I2C3 controllers are multiplexed with
standard LVCMOS I/O and connected to emulate open drain.The I2C emulation is achieved by configuring
the LVCMOS buffers to output Hi-Z instead of driving high when transmitting logic 1.
ADVANCE INFORMATION
The multimaster I2C module has the following features:
• Compliant with Philips I2C-bus specification version 2.1
• Supports a standard mode (up to 100 Kbps) and fast mode (up to 400 Kbps)
• 7-bit and 10-bit device addressing modes
• General call
• Start/Restart/Stop
• Multimaster transmitter/slave receiver mode
• Multimaster receiver/slave transmitter mode
• Built-in FIFO for buffered read or write
– Programmable size of 8-64 bytes
• Module enable/disable capability
• Programmable multislave channel (responds to four separate addresses)
• Programmable clock generation
• 8-bit-wide data access
• Low power consumption
• Support Auto Idle mechanism
• Support Idle Request/Idle Acknowledge handshake mechanism
• Support for asynchronous wakeup mechanism
• Wide interrupt capability
I2C Not Supported Features:
• Serial Camera Control Bus (SCCB) Protocol
• High-Speed (HS) Mode
• DMA Mode
• Full I2C electrical compliance (only for MAIN domain I2C modules)
• Local power management of clock activity
For more information, see section Inter-Integrated Circuit (I2C) Interface in the device TRM.
6.4.5.16 MCAN
The Controller Area Network (CAN) is a serial communications protocol which efficiently supports
distributed real-time control. CAN has high immunity to electrical interference. In a CAN network, many
short messages are broadcast to the entire network, which provides for data consistency in every node of
the system.
The MCAN module supports both classic CAN and CAN FD (CAN with Flexible Data-Rate) specifications.
CAN FD feature allows high throughput and increased payload per data frame. The classic CAN and CAN
FD devices can coexist on the same network without any conflict.
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The device supports two MCAN modules - MCU_MCAN0 and MCU_MCAN1. They connect to the
physical layer of the CAN network through external (for the device) transceivers. Each MCAN module
supports flexible bit rates greater than 1 Mbps and is compliant to ISO 11898-1:2015.
ADVANCE INFORMATION
Each MCAN module implements the following features:
• Conforms with CAN Protocol 2.0 A, B and ISO 11898-1:2015
• Full CAN FD support (up to 64 data bytes)
• SAE J1939 support
• AUTOSAR support (only on DRA80xM family of devices)
• Up to 32 dedicated Transmit Buffers
• Configurable Transmit FIFO, up to 32 elements
• Configurable Transmit Queue, up to 32 elements
• Configurable Transmit Event FIFO, up to 32 elements
• Up to 64 dedicated Receive Buffers
• Two configurable Receive FIFOs, up to 64 elements each
• Up to 128 filter elements
• Internal Loopback mode for self-test
• Maskable interrupts, two interrupt lines
• Two clock domains (CAN clock/Host clock)
• Parity/ECC support - Message RAM single error correction and double error detection (SECDED)
mechanism
• Local power-down and wakeup support
• Timestamp Counter
MCAN subsystems do not support the following features:
• Host bus firewall
• GPIO mode
• Clock calibration
• External (IO) Loopback mode
• Debug DMA
• TX DMA channels [31:3]
• AUTOSAR (on AM65x family of devices)
For more information, see section Modular Controller Area Network (MCAN) in the device TRM.
6.4.5.17 MCASP
The MCASP functions as a general-purpose audio serial port are optimized to the requirements of various
audio applications. The MCASP module can operate in both transmit and receive modes. The MCASP is
useful for time-division multiplexed (TDM) stream, Inter-IC Sound (I2S) protocols reception and
transmission as well as for an intercomponent digital audio interface transmission (DIT). The MCASP has
the flexibility to gluelessly connect to a Sony/Philips digital interface (S/PDIF) transmit physical layer
component.
Although intercomponent digital audio interface reception (DIR) mode (this is, S/PDIF stream receiving) is
not natively supported by the MCASP module, a specific TDM mode implementation for the MCASP
receivers allows an easy connection to external DIR components (for example, S/PDIF to I2S format
converters).
The device has integrated three MCASP modules within:
• MCASP0 supporting up to 16 channels with independent TX/RX clock/sync domain
• MCASP1 supporting up to 10 channels with independent TX/RX clock/sync domain
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MCASP2 supporting up to 4 channels with independent TX/RX clock/sync domain
MCASP module includes the following main features:
• Independent serializer for each AXRx channel of each MCASP module.
• Clock stop request/acknowledge protocol
• A single 32-bit buffer per serializer for transmit and receive operations
• Interconnect interface port for CBASS0
• Two independent clock generator modules for transmit and receive (clocking flexibility allows the
MCASP to receive and transmit at different rates. For example, the MCASP can receive data at 48 kHz
but output up-sampled data at 96 kHz or 192 kHz)
• Each MCASP module functional clock can be generated:
– internally (master mode)
– supplied over MCASP serial interface (slave mode)
– has a controllable functional clock divide ratio
• Independent transmit and receive modules, each includes:
– Programmable clock and frame sync generator
– TDM streams from 2 to 32, and 384 time slots
– Support for time slot sizes of 8, 12, 16, 20, 24, 28, and 32 bits
– Data formatter for bit manipulation
• Glueless connection to audio analog-to-digital converters (ADC), digital-to-analog converters (DAC),
codec, digital audio interface receiver (DIR), and S/PDIF transmit physical layer components
• Wide variety of I2S and similar bit-stream format
• Integrated digital audio interface transmitter (DIT):
– S/PDIF, IEC60958-1, AES-3 formats
– Enhanced channel status/user data RAM
• 384-slot TDM with external digital audio interface receiver (DIR) device
– For DIR reception, an external DIR receiver integrated circuit should be used with I2S output format
and connected to the MCASP receive section
• Support for 2 × DMA requests (one per direction):
– 1 level-sensitive transmit direct memory access (DMA) request common for all of the MCASP
serializers
– 1 level-sensitive receive direct memory access (DMA) request common for all of the MCASP
serializers
– All transmit DMA requests are mapped to the device DMA controllers
• One transmit interrupt request common for all serializers
• One receive interrupt request common for all serializers
• Each of the Rx and Tx interrupts is propagated to different host processors via the device Interrupts
NOTE
Because a serializer receive and transmit channels data is shared on the same MCASP data
pin, user can choose to have either Tx or Rx function from a serializer, not both at the same
time.
The MCASP module does not support the following features:
• Muting output (AMUTE)
• Muting input (AMUTEIN)
For more information, see section Multichannel Audio Serial Port (MCASP) in the device TRM.
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6.4.5.18 MCRC
VBUSM CRC controller is a module which is used to perform CRC (Cyclic Redundancy Check) to verify
the integrity of a memory system. A signature representing the contents of the memory is obtained when
the contents of the memory are read into MCRC Controller. The responsibility of MCRC controller is to
calculate the signature for a set of data and then compare the calculated signature value against a predetermined good signature value. MCRC controller provides four channels to perform CRC calculation on
multiple memories in parallel and can be used on any memory system. Channel 1 can also be put into
data trace mode, where MCRC controller compresses each data being read through CPU read data bus.
ADVANCE INFORMATION
MCRC has the following features:
• Four channels to perform background signature verification on any memory subsystem
• Data compression on 8-, 16-, 32-, and 64-bit data size
• Maximum-length PSA (Parallel Signature Analysis) register constructed based on 64-bit primitive
polynomial
• Each channel has a CRC Value Register which contains the pre-determined CRC value
• Use timed base event trigger from timer to initiate DMA data transfer
• Programmable 20-bit pattern counter per channel to count the number of data patterns for
compression
• Three modes of operation:
– Auto
– Semi-CPU
– Full-CPU
• For each channel, CRC can be performed either by MCRC Controller or by CPU
• Automatically performs signature verification without CPU intervention in AUTO mode
• Generates interrupt to CPU in Semi-CPU mode to allow CPU to perform signature verification itself
• Generates CRC fail interrupt in AUTO mode if signature verification fails
• Generates Timeout interrupt if CRC is not performed within the time limit
• Generates DMA request per channel to initiate CRC value transfer
• An 128-byte block burst address for the PSA register to DMA without constant mode bus attribute
The following MCRC features are not supported by the module:
• Data trace capability on VBUSM, ITCM and DTCM data buses.
For more information, see section Memory Cyclic Redundancy Check (MCRC) Controller in the device
TRM.
6.4.5.19 MCSPI
The MCSPI module is a multichannel transmit/receive, master/slave synchronous serial bus.
There are total of eight MCSPI modules in the device.
MCSPI3 and MCSPI4 include internal connectivity to MCSPI modules in the MCU domain, as follows:
• MCSPI3 is connected as a master to MCU_MCSPI1 by default at power-up. MCU_MCSPI1 and
MCSPI3 may be optionally mapped to external device pads.
• MCSPI4 is directly connected as a slave to MCU_MCSPI2 by default at power-up. MCSPI4 and
MCU_MCSPI2 are not pinned out externally.
The MCSPI modules include the following main features:
• Serial clock with programmable frequency, polarity, and phase for each channel
• Wide selection of MCSPI word lengths, ranging from 4 to 32 bits
• Up to four master channels, or single channel in slave mode
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Master multichannel mode:
– Full duplex/half duplex
– Transmit-only/receive-only/transmit-and-receive modes
– Flexible input/output (I/O) port controls per channel
– Programmable clock granularity
– MCSPI configuration per channel. This means, clock definition, polarity enabling and word width
Single interrupt line for multiple interrupt source events
Enable the addition of a programmable start-bit for MCSPI transfer per channel (start-bit mode)
Supports start-bit write command
Supports start-bit pause and break sequence
Programmable shift operations (1-32 bits)
Programmable timing control between chip select and external clock generation
Built-in FIFO available for a single channel.
The following features are not supported on this family of devices:
• Slave mode wake-up
• Retention during power down
• MCU_MCSPI2 and MCSPI4 are not pinned out
• MCSPI4 master mode is not supported
• Loopback testing is not available for MCSPI4 internal connection to MCU_MCSPI2 because DMA
operation is not verified
• In slave mode only channel 0 is used
• Local power management of clock activity.
For more information, see section Multichannel Serial Peripheral Interface (MCSPI) in the device TRM.
6.4.5.20 MMC/SD
There are two MMCSD modules inside the device - MMCSD0 and MMCSD1. Each MMCSD module
includes one MMCSD Host Controller.
Each controller has the following data bus width:
• MMCSD0 - 8-bit wide data bus
• MMCSD1 - 4-bit wide data bus
The MMCSD Host Controller provides an interface to eMMC 5.1 (embedded MultiMedia Card), SD 4.10
(Secure Digital), and SDIO 4.0 (Secure Digital IO) devices. The MMCSD Host Controller deals with
MMC/SD/SDIO protocol at transmission level, data packing, adding cyclic redundancy checks (CRCs),
start/end bit insertion, and checking for syntactical correctness.
Each MMCSD Host Controller supports:
• eMMC5.1 Host Specification (JESD84-B51)
• SD Host Controller Standard Specification 4.10
• Integrated DMA controller supporting SD Advanced DMA - ADMA2
• High Voltage eMMC – 3.3 V
• Dual Voltage eMMC – 1.8 V, 3.3 V
• System Bus Interface:
– 64-bit data width (master interface)
– 64-bit address
– Clock asynchronous to MMCSD clock (MMCi_CLK)
– Little endian only
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Configuration Bus Interface:
– 32-bit data width (slave interface)
– Linear incrementing addressing mode
– 32-bit aligned accesses only
– Little endian only
ADVANCE INFORMATION
MMCSD0 Host Controller:
MultiMedia Card Support:
– eMMC Electrical Standard 5.1 (JESD84-B51)
– Backward compatible with earlier eMMC standards
– Legacy MMC SDR:
• 3.3 V/1.8 V, 8-bit bus width, 0-25 MHz, 25 MBps
• 3.3 V/1.8 V, 4-bit bus width, 0-25 MHz, 12.5 MBps
• 3.3 V/1.8 V, 1-bit bus width, 0-25 MHz, 3.125 MBps
– High Speed SDR:
• 3.3 V/1.8 V, 8-bit bus width, 0-50 MHz, 50 MBps
• 3.3 V/1.8 V, 4-bit bus width, 0-50 MHz, 25 MBps
• 3.3 V/1.8 V, 1-bit bus width, 0-50 MHz, 6.25 MBps
– High Speed DDR:
• 3.3 V/1.8 V, 8-bit bus width, 0-50 MHz, 100 MBps
• 3.3 V/1.8 V, 4-bit bus width, 0-50 MHz, 50 MBps
– HS200 SDR:
• 1.8 V, 0-200 MHz, 8-bit bus width, 200 MBps
• 1.8 V, 0-200 MHz, 4-bit bus width, 100 MBps
Secure Digital Card Support:
– Backward compatible with earlier SD card specifications
– SD Physical Layer Specification v3.01
– SDIO support
– SDIO Specification v3.00
– High Voltage SD memory card – 3.3 V
– Default Speed mode: 3.3 V signaling, frequency up to 25 MHz, up to 12.5 MBps
– High Speed mode: 3.3 V signaling, frequency up to 50 MHz, up to 25 MBps
– SDR12: UHS-I 1.8 V signaling, frequency up to 25 MHz, up to 12.5 MBps
– SDR25: UHS-I 1.8 V signaling, frequency up to 50 MHz, up to 25 MBps
– SDR50: UHS-I 1.8 V signaling, frequency up to 100 MHz, up to 50 MBps
– SDR104: UHS-I 1.8 V signaling, frequency up to 200 MHz, up to 100 MBps
– DDR50: UHS-I 1.8 V signaling, frequency up to 50 MHz, up to 50 MBps
MMCSD1 Host Controller:
MultiMedia Card Support:
– eMMC Electrical Standard 5.1 (JESD84-B51)
– Backward compatible with earlier eMMC standards
– Legacy MMC SDR:
• 3.3 V/1.8 V, 4-bit bus width, 0-25 MHz, 12.5 MBps
• 3.3 V/1.8 V, 1-bit bus width, 0-25 MHz, 3.125 MBps
– High Speed SDR:
• 3.3 V/1.8 V, 4-bit bus width, 0-50 MHz, 25 MBps
• 3.3 V/1.8 V, 1-bit bus width, 0-50 MHz, 6.25 MBps
– High Speed DDR:
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• 3.3 V/1.8 V, 4-bit bus width, 0-50 MHz, 50 MBps
– HS200 SDR:
• 1.8 V, 0-200 MHz, 4-bit bus width, 100 MBps
Secure Digital Card Support:
– Backward compatible with earlier SD card specifications
– SD Physical Layer Specification v3.01
– SDIO support
– SDIO Specification v3.00
– High Voltage SD memory card – 3.3 V
– Default Speed mode: 3.3 V signaling, frequency up to 25 MHz, up to 12.5 MBps
– High Speed mode: 3.3 V signaling, frequency up to 50 MHz, up to 25 MBps
– SDR12: UHS-I 1.8 V signaling, frequency up to 25 MHz, up to 12.5 MBps
– SDR25: UHS-I 1.8 V signaling, frequency up to 50 MHz, up to 25 MBps
– SDR50: UHS-I 1.8 V signaling, frequency up to 100 MHz, up to 50 MBps
– SDR104: UHS-I 1.8 V signaling, frequency up to 200 MHz, up to 100 MBps
– DDR50: UHS-I 1.8 V signaling, frequency up to 50 MHz, up to 50 MBps
MMCSD Not Supported Features:
MMCSD0 Host Controller:
• MultiMedia Card:
– 3.0 V and 1.2 V
– HS400 DDR: 1.8 V, 0-200 MHz, 8-bit bus width, 400 MBps
• Secure Digital Card
– UHS II
MMCSD1 Host Controller:
• MultiMedia Card
– 3.0 V and 1.2 V
– All 8-bit modes
• Secure Digital Card
– UHS II
For more information, see section Multimedia Card/Secure Digital (MMC/SD) Interface in the device TRM.
6.4.5.21 OSPI
The Octal Serial Peripheral Interface (OSPI™) module is a kind of Serial Peripheral Interface (SPI)
module which allows single, dual, quad or octal read and write access to external flash devices.
The OSPI module is used to transfer data, either in a memory mapped direct mode (for example a
processor wishing to execute code directly from external flash memory), or in an indirect mode where the
module is set-up to silently perform some requested operation, signaling its completion via interrupts or
status registers. For indirect operations, data is transferred between system memory and external flash
memory via an internal SRAM which is loaded for writes and unloaded for reads by a device master at low
latency system speeds. Interrupts or status registers are used to identify the specific times at which this
SRAM should be accessed using user programmable configuration registers.
The OSPI modules have the following features:
• Support for single, dual, quad (QSPI mode) or octal (on MCU_FSS0_OSPI0 only) I/O instructions.
• Support dual Quad-SPI mode for fast boot applications.
• Memory mapped ‘direct’ mode of operation for performing flash data transfers and executing code from
flash memory.
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Software triggered 'indirect' mode of operation for performing low latency and non-processor intensive
flash data transfers.
Local SRAM of configurable size to reduce advanced high-performance bus overhead and buffer flash
data during indirect transfers.
Set of software advanced peripheral bus accessible flash control registers to perform any flash
command, including data transfers up to 8-bytes at a time.
Additional addressable memory bank to accommodate more than 8-bytes at a time.
Support for XIP, sometimes referred to as continuous mode.
Support for DDR Mode and DTR protocol (including Octal DDR protocol with DQS for Octal-SPI
devices)
Programmable device sizes.
Programmable write protected regions to block system writes from taking effect.
Programmable delays between transactions.
Legacy mode allowing software direct access to low level transmit and receive FIFOs, bypassing the
higher layer processes.
An independent reference clock to decouple bus clock from SPI clock – allows slow system clocks.
Programmable baud rate generator to generate OSPI clocks.
Features included to improve high speed read data capture mechanism.
Option to use adapted clocks or DQS to further improve read data capturing.
Programmable interrupt generation.
Up to four external device selects - OSPI and QSPI devices can be mixed:
– MCU_FSS0_OSPI0 has four chip-selects
– MCU_FSS0_OSPI1 has two chip-selects.
Programmable data decoder, enables continuous addressing mode for each of the connected devices
and auto-detection of boundaries between devices.
Support BOOT mode.
Support for data safety mechanisms:
– Bidirectional CRC on Multiple-SPI interface.
– Handling ECC errors for flash devices with embedded correction engine.
Full integration with PHY module dedicated to more flexible and power efficient transfers.
The following features are not supported on this family of devices:
• OSPI1_D[7-4] are not pinned out.
• OSPI1_SCn[3-2] are not pinned out.
• DMA not supported.
• Pulse events not used.
• In Octal-SPI mode, Mode 1 and 2 are not supported. In Mode 3 DDR is not supported.
• In Quad-SPI mode, Mode 1 and 2 are not supported. In Mode 3 DDR is not supported.
For more information, see section Octal Serial Peripheral Interface (OSPI) in the device TRM.
6.4.5.22 PCIE
The Peripheral Component Interconnect Express (PCIe) subsystem is built around a multi-lane dual-mode
PCIe controller that provides low pin-count, high reliability, and high-speed data transfers at rates of up to
8.0 Gbps per lane for serial links on backplanes and printed wiring boards.
The device includes two instantiations of PCIe subsystem named PCIE0 and PCIE1.
Each PCIe subsystem supports the following main features:
• Compliant with PCI-Express® Base Specification, Revision 3.1
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One or two-lane configuration with up to 8.0 Gbps/lane (Gen3)
– PCIE0 used as 2-lane controller, configurable in 1x1 or 1x2 mode
– PCIE1 used as 1-lane controller configured in 1x1 mode
Gen3 (8 Gbps 128/130-bit encoding), Gen2 (5 Gbps 8/10-bit encoding), and Gen1 (2.5 Gbps 8/10-bit
encoding) with auto-negotiation
Dynamic PIPE width change when switching between Gen1/2/3 modes
Root Complex (RC) or End Point (EP) operation modes
Maximum payload size of 256 bytes
Maximum remote read request size of 4K bytes
Ultra-low transmit and receive latency
Automatic lane reversal as specified in the PCIe specification (transmit and receive)
Polarity inversion on receive
One Physical Function (PF)
Single function in End Point (EP) mode
Four virtual channels (VC)
Four traffic classes (TC)
Automatic credit management
ECRC generation and checking
PCI Device Power Management states D0, D1, D3Hot and D3Cold with the exception of D3Cold with
Vaux
PCIe Active State Power Management (ASPM) state L0s and L1 (with exceptions)
PCIe Link Power Management states, except L2 state
PCIe Advanced Error Reporting
PCIe messages for both transmit and receive
Filtering for Posted, Non-posted, and Completion traffic
Configurable BAR filtering, I/O filtering, configuration filtering, and completion lookup/timeout
Access to configuration space registers and external application memory-mapped registers through
BAR0 and through configuration access
Legacy interrupts reception (in RC mode) and generation (in EP mode)
Custom interrupt generation in RC mode and interrupt reception in EP mode.
MSI-X generation and reception
Precision Time Measurement (PTM) in combination with internal Common Platform Time Sync (CPTS)
module
Quality-of-Service (QoS) mechanism by enabling priority or round-robin arbitration on VCs
Two host bus master interfaces for high and low priority traffic mapped to four virtual channels
PCIe compliant PHY (PIPE 4.0) interface for connection to a SERDES based PHY
The PCIe subsystems do not support the following features:
• PCIe beacon for in-band wake
• Vendor Messaging
• I/O access in inbound direction in RC or EP mode
• Single-root I/O Virtualization (SR-IOV)
• Address Translation Services (ATS)
• Addressing modes other than incremental for burst transactions. As a result, the PCIe addresses
cannot be in cacheable memory space.
For more information, see section Peripheral Component Interconnect Express (PCIe) Subsystem in the
device TRM.
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6.4.5.23 SerDes
SerDes'es goal is to convert device (SoC) parallel data into serialized data that can be output over a highspeed electrical interface. In the opposite direction, SerDes converts high-speed serial data into parallel
data that can be processed by the device. To this end, the SerDes contains a variety of functional blocks
to handle both the external analog interface as well as the internal digital logic.
Most important building blocks of SerDes are:
• Lanes: The lanes handle all inputs and outputs from the serial interface, and contain the Tx/Rx I/Os,
serializer/deserializer, and Clock and Data Recovery (CDR) unit.
• Clock Multiplier Unit (CMU): The CMU handles peripheral and Tx clocking of the SerDes. It consists of
an internal PLL and the reference clock input buffers.
• Physical Coding Sub-block (PCS): The PCS is responsible for translating data from/to the parallel
interface, as well as data encoding/decoding and symbol alignment.
• WIZ: The WIZ acts as a wrapper for the SerDes, and can both send control signals to and report status
signals from the SerDes, and muxes SerDes to peripherals.
The device contains two SerDeses: SERDES0 and SERDES1.
ADVANCE INFORMATION
The SERDES module features include:
• Single lane PHY containing:
– Transmit and Receive I/Os
– Serializer
– Deserializer
– Clock and data recovery (CDR) unit
• Clock Multiplying Unit (CMU)
– PLLs
– Master bias
– Termination calibration
– Reference clock input buffers
• Physical Coding Sub-block (PCS)
– 8b/10b encoder/decoder (PCIe 1 and PCIe 2)
– 128b/130b encoder/decoder (PCIe 3)
– Symbol alignment
– Polarity inversion
– Bit stream reordering
• Physical Media Attachment (PMA) layer
– Transmit equalization
– Receive equalization
The SERDES mux (WIZ) module supports the following features:
• Multiplexes device interfaces onto a single SERDES lane (one Tx and one Rx)
• Provides registers to implement SERDES control and status functions and alignment delays
• Clock generator block for providing MAC transmit clock
• Rx comma align block
– Performs de-stuffing the Rx data stream in the event that the Rx rate is different from the Tx rate
– Supports comma detection that is not sensitive to false commas using all 8B10B character
combinations
For more information, see section Serializer/Deserializer (SerDes) in the device TRM.
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6.4.5.24 RTI
This section describes the Real Time Interrupt (RTI) modules with Windowed Watchdog Timer (WWDT)
functionality for the device.
The Real Time Interrupt module provides timer functionality for operating systems and for benchmarking
code. The module incorporates several counters, which define the timebases needed for scheduling in the
operating system.
This module is specifically designed to fulfill the requirements for OSEK (“Offene Systeme und deren
Schnittstellen für die Elektronik im Kraftfahrzeug”; “Open Systems and the Corresponding Interfaces for
Automotive Electronics”) as well as OSEK/Time compliant operating systems.
The RTI modules include the following main features:
• Two independent 64 bit counter blocks (counter block0 or counter block1). Each block consists of
– One 32 bit up counter
– One 32 bit free running counter
– Two capture registers for capturing the prescale and free running counter on a special event.
• Free running counter 0 can be incremented by either the internal prescale counter or by an external
event.
• Four configurable compare registers for generating operating system ticks. Each event can be driven
by either counter block0 or counter block1.
• Fast enabling/disabling of events.
• Capture events to capture timestamps through recording of timer status.
• Two time-stamp (capture) functions for system or peripheral interrupts, one for each counter block.
• Windowed watchdog timer (WWDT) feature.
• RTI clock input derived from any of the available clock sources, selectable in the System Module
• Optional capability to drive a pulse-width modulated signal out on an interrupt line
The following features are not supported on this family of devices:
• RTI[3-0] are not supported in PG1.0
• Analog and Digital Watchdog (DWD) Timers
• Periodic interrupt / DMA events
• Compare events not used
• Counter operation is not supported and counter overflow interrupts are not used.
For more information, see section Real Time Interrupt (RTI) Module in the device TRM.
6.4.5.25 Timers
There are sixteen timer modules in the device.
All timers include specific functions to generate accurate tick interrupts to the operating system.
Each timer can be clocked from several different independent clocks. The selection of clock source is
made from registers in the MCU_CTRL_MMR0/CTRL_MMR0.
In the MCU domain the device provides 2 timer pins to be used as MCU Timer Capture inputs or as MCU
Timer PWM outputs. In order to provide maximum flexibility, these 2 pins may be used with any of
MCU_TIMER0 through MCU_TIMER3 instances. System level muxes are used to control the capture
source pin for each MCU_TIMER[3-0] and the MCU_TIMER[3-0] source for each MCU_TIMER_IO[1-0]
PWM output.
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The timers also provide the ability to benchmark certain areas of code by reading the counter contents at
the beginning and the end of the desired code range and calculating the difference between the values.
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In the MAIN domain the device provides 8 timer pins to be used as Timer Capture inputs or as Timer
PWM outputs. For maximum flexibility, these 8 pins may be used with any of TIMER0 through TIMER11
instances. System level muxes are used to control the capture source pin for each TIMER[11-0] and the
TIMER[11-0] source for each TIMER_IO[7-0] PWM output.
Each odd numbered timer instance from each of the domains may be optionally cascaded with the
previous even numbered timer instance from the same domain to form up to a 64-bit timer. For example,
TIMER1 may be cascaded to TIMER0, MCU_TIMER1 may be cascaded to MCU_TIMER0, etc.
When cascaded, TIMERi acts as a 32-bit prescaler to TIMERi+1, as well as MCU_TIMERn acts as a 32bit prescaler to MCU_TIMERn+1. TIMERi / MCU_TIMERn must be configured to generate a PWM output
edge at the desired rate to increment the TIMERi+1/ MCU_TIMERn+1 counter.
For more information, see section Timers in the device TRM.
6.4.5.26 UART
ADVANCE INFORMATION
The UART is a slave peripheral that utilizes the DMA for data transfer or interrupt polling via host CPU.
There are five UART modules in the device. All UART modules support IrDA and CIR modes when 48
MHz function clock is used. Each UART can be used for configuration and data exchange with a number
of external peripheral devices or interprocessor communication between devices.
The UART include the following features:
• 16C750-compatible
• RS-485 external transceiver auto flow control support
• 64-byte FIFO buffer for receiver and 64-byte FIFO buffer for transmitter
• Programmable interrupt trigger levels for FIFOs
• Programmable sleep mode
• The 48 MHz functional clock is default option and allows baud rates up to 3.6 Mbps
• The 192 MHz functional clock is not default option and allows baud rates up to 12 Мbps, and autobaud cannot be used
• Auto-baud between 1200 bits/s and 115.2 Kbits/s (only when 48 MHz function clock is used)
• Optional multi-drop transmission
• Configurable time-guard feature
• Configurable data format:
– Data bit: 5, 6, 7, or 8 bits
– Parity bit: Even, odd, none
– Stop-bit: 1, 1.5, 2 bit(s)
• Flow control: Hardware (RTS/CTS) or software (XON/XOFF)
• False start bit detection
• Line break generation and detection
• Fully prioritized interrupt system controls
• Internal test and loopback capabilities
• Modem control functions (CTS, RTS)
• UART0 module in MAIN domain has extended modem control signals (DCD, RI, DTR, DSR)
The IrDA includes the following features:
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Support of IrDA 1.4 slow infrared (SIR), medium infrared (MIR), and fast infrared (FIR)
communications:
– Slow infrared (SIR 115.2 KBAUD), medium infrared (MIR 0.576 MBAUD) and fast infrared (FIR 4.0
MBAUD) operations (very fast infrared (VFIR) is not supported)
– Frame formatting: addition of variable beginning-of-frame (xBOF) characters and end-of-frame
(EOF) characters
– Uplink/downlink cyclic redundancy check (CRC) generation/detection
– Asynchronous transparency (automatic insertion of break character)
– Eight-entry status FIFO (with selectable trigger levels) to monitor frame length and frame errors
– Framing error, CRC error, illegal symbol (FIR), and abort pattern (SIR, MIR) detection
IrDA mode when 48 MHz function clock is used
The CIR includes the following features to provide CIR support for remote-control applications:
• Transmit and receive mode
• Free data format (supports any remote-control private standards)
• Selectable bit rate
• Configurable carrier frequency
• 1/2, 5/12, 1/3, or 1/4 carrier duty cycle
• CIR mode when 48 MHz function clock is used
UART Not Supported Features:
• Synchronous mode
• ISO7816 mode
For more information, see section Universal Synchronous/Asynchronous Receiver/Transmitter (UART) in
the device TRM.
6.4.5.27 USB
Similar to earlier versions of USB bus, USB 3.0 is a general-purpose cable bus, supporting data exchange
between a host device and a wide range of simultaneously accessible peripherals.
The device supports two USB subsystems, both instantiated in the MAIN system domain:
• USB3SS0 is SuperSpeed (SS) USB 3.0 Dual-Role-Device (DRD) subsystem with integrated SS
(USB3.0) PHY and HS/FS/LS (USB2.0) PHY
• USB3SS1 is HighSpeed (HS) USB 2.0 Dual-Role-Device (DRD) subsystem with integrated HS/FS/LS
(USB2.0) PHY
The USB subsystem, supports the following USB features:
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The CIR mode uses a variable pulse-width modulation (PWM) technique (based on multiples of a
programmable t period) to encompass the various formats of infrared encoding for remote-control
applications. The CIR logic transmits data packets based on a user-definable frame structure and packet
content.
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General features:
– Supports Peripheral (aka Device) mode at Superspeed (5 Gbps), Highspeed (480 Mbps), and
Fullspeed (12 Mbps)
– Supports Host mode at Superspeed (5 Gbps), Highspeed (480 Mbps), Fullspeed (12 Mbps), and
Lowspeed (1.5 Mbps)
– Static peripheral operation
– Static host operation
– Limited OTG 2.0 functionality in conjunction with an VBUS/ID analog comparator detection circuit
and software handshake
– Host Negotiation Protocol (HNP) support in conjunction with an ID comparator detection circuit and
software handshake
– Accessory Charger Adapter (ACA) support via ID-pin comparator
– External Buffer Control (EBC) mode for IN (Tx) Endpoints 14 and 15
Each controller instance contains single xHCI with the following features:
– Compatible to the xHCI specification (revision 1.1) in Host mode
– Supports 15 Transmit (TX), 15 Receive (RX) endpoints (EPs), and one EP0 endpoint which is
bidirectional
– Internal DMA controller
– Interrupt moderation and blocking
– Supports for all USB transfer modes - Control, Bulk, Interrupt, and Isochronous
– Supports high bandwidth ISO mode
– Descriptor caching and data pre-fetching used to improve system performance
– Dynamic FIFO memory allocation for all endpoints
– USB power saving states (U0, U1, U2, and U3)
– Asynchronous wakeup signal for remote wakeup
Operation flexibility:
– Uniform programming model for SS, HS, FS, and LS operation
– Multiple interrupt lines:
• 16 interrupts associated with 16 programmable Event Rings for multi-core support
• Interrupt lines for all miscellaneous events
Functional safety:
– Internal RAM with ECC
– Loopback on USB3 PHY (SerDes)
External requirements:
– An external charge pump or power switch for VBUS 5-V generation
– An external circuitry or PMIC to start the battery charging upon Battery Charger (BC) detected
event
– An external reference clock input for USB PHY operation
– An external high-precision resistor for PHY termination calibration
The following are USB features which are not supported in current device:
• OTG 3.0 functionality
• HSIC (High Speed inter-chip) and SSIC interface
• ULPI Interface for external PHY
• SRP and ADP protocols
• External Buffer Control (EBC) for OUT (Rx) Endpoint
• Hibernation
For more information, see section Universal Serial Bus (USB) Subsystem in the device TRM.
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6.5
6.5.1
SPRSP31E – APRIL 2018 – REVISED JUNE 2019
Identification
Revision Identification
For more information about Revision Identification, see section Section 8.1, Device Nomenclature.
6.5.2
Die Identification
The device part number identification data can be read in the CTRLMMR_WKUP_JTAG_DEVICE_ID
register.
For more information about Die Identification, see section Device Identification in the device TRM.
6.5.3
JTAG Identification
The manufacturer identity, the boundary scan part number, and the silicon revision of the device can be
read in the CTRLMMR_WKUP_JTAGID register.
For more information about JTAG Identification, see section Device Identification in the device TRM.
ROM Code Identification
The ROM code uses several global memories in the MSRAM that are useful for debugging.
For more information about ROM Code Identification, see section Global Memory Addresses Used by
ROM Code in the device TRM.
6.6
6.6.1
Boot Modes
Boot Mode List
Boot Mode pins provide means to select the boot mode before the device is powered up.
Boot mode pins can be divided into the following categories:
• BOOTMODE[03:00] – Select the requested boot (primary) mode after POR, that is, the
peripheral/memory to boot from.
• BOOTMODE[06:04] – Select the backup boot mode, that is, the peripheral/memory to boot from, if
primary boot device failed.
• BOOTMODE07 – This is the minimum (MIN) configuration pin. MIN pin allows minimum BOOTMODE
pins to be set up, and thus saving DIP switches or pull-ups/pull-downs on the board. A default value,
stored in ROM Code, is loaded in place of BOOTMODE[18:8] pin values. See the particular boot mode
section for the default values when MIN was selected.
• BOOTMODE[15:08] – These pins provide optional configurations for primary boot and are used in
conjuction with the boot mode selected. See Section 6.6.2.2.1, Primary Boot Mode Configuration and
the corresponding boot mode section.
• BOOTMODE[18:16] – These pins provide optional configurations for the backup boot devices. See
Section 6.6.2.2.2, Backup Boot Mode Configuration and the corresponding boot mode section.
• MCU_BOOTMODE[02:00] – Denote system clock frequency (WKUP_HFOSC0) for PLL configuration.
• MCU_BOOTMODE[04:03] – These pins are reserved for future use.
• MCU_BOOTMODE[08:05] – On safety-enabled devices, these pins enable certain power-on tests
(POST).
• MCU_BOOTMODE09 – Selects which MMCSD port is connected to 1.8-V SDIO LDO.
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NOTE
It is user's responsibilty to set properly the (MCU_)BOOTMODE pins (via pullups or
pulldowns) depending on the desired boot scenario.
System board must provide means to switch (MCU_)BOOTMODE pin settings easily. In a
field design, some pins may be hardcoded to 0 or 1 but only after careful evaluation (for
example with MIN pin enabled).
For more information about Boot Mode List, see section Boot Mode Pins in the device TRM.
6.6.2
Boot Mode Pin Usage
6.6.2.1
MCU_BOOTMODE Pin Mapping
MCU_BOOTMODE pin mapping is shown in Table 6-1, MCU_BOOTMODE Pin Mapping.
Table 6-1. MCU_BOOTMODE Pin Mapping
9
8
7
ADVANCE INFORMATION
1.8V
MMC/SD
(1)
(2)
6
POST
5
(1)
4
3
Reserved
2
(2)
1
0
Ref Clock
Only on safety-enabled devices. Refer to device Datasheet for device nomenclature.
Always set to 0s (via pulldowns to VSS)
The ROM Code will configure any PLLs required during the boot process. The ROM Code does not have
the ability to select HFOSC1 (in main domain) during initial boot, however the selection can be done
through the boot certificate.
The ROM Code has no means to detect the system clock speed, therefore user must set the Ref Clock
pins according to the actual clock speed in the design (generated by PMIC, internal or external XTAL
oscillator, or other). Ref Clock pins are described in Table 6-2, PLL Reference Clock Selection.
Table 6-2. PLL Reference Clock Selection
MCU_BOOTMODE PINS
REFERENCE CLOCK (MHz)
2
1
0
0
0
0
19.2
0
0
1
20
0
1
0
24
0
1
1
25
1
0
0
26
1
0
1
27
1
1
0
Reserved
1
1
1
No PLL configuration (slow speed backup)
On safety-enabled devices, users can select certain POST tests to be performed on power-on. POST
tests are executed in hardware, without any ROM code intervention. More than one test can be selected
at a time. Table 6-3 shows the POST selection.
Table 6-3. POST Selection
MCU_BOOTMODE PINS
282
POST SELECT
8
7
6
5
0
0
0
0
POST bypass
X
X
X
1
Enable POST DMSC, MCU LBIST Parallel
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Table 6-3. POST Selection (continued)
MCU_BOOTMODE PINS
8
7
X
X
1
POST SELECT
6
5
X
1
X
POST DMSC LBIST Enable
1
X
X
POST MCU LBIST Enable
X
X
X
POST PBIST Enable
Table 6-4. 1.8V LDO Configuration
9
1.8V MMC/SD
0
MMCSD0 connected to 1.8V LDO
1
MMCSD1 connected to 1.8V LDO
For more information about MCU_BOOTMODE Pin Mapping, see MCU_BOOTMODE Pin Mapping in the
device TRM.
BOOTMODE Pin Mapping
In normal boot operation the ROM execution is directed through the main boot mode pins. Main boot
mode pins are shown in Table 6-5, BOOTMODE Pin Mapping.
Table 6-5. BOOTMODE Pin Mapping
18
17
16
15
14
13
12
Backup Config
11
10
9
8
7
Primary Config
6
Min
5
4
Backup Mode
3
2
1
0
Primary Mode
6.6.2.2.1 Primary Boot Mode Configuration
The mapping of primary boot mode configuration pins is shown in Table 6-6, Primary Boot Mode
Configuration.
Table 6-6. Primary Boot Mode Configuration (1)
BOOTMODE PINS
15
14
13
Pin Cmd
Port
Pin Cmd
12
11
9
8
Addr
Width
0001
OSPI
Iclk
Csel
Speed
Addr
Width
0010
QSPI
Speed
0011
Hyperflash
Read Cmd
Addr Width
0100
SPI
Speed
Addr
0101
I2C
0110
MMC/SD Card
0111
Ethernet
Csel
Mode
Csel
Clkf
Mode
Port
Interface
Interface Config
Speed
Duplex
1bit
Extern conf
Mode
Base
Dual
(1)
Port
Sref
A/D mux
Port
Sleep
Speed
Volt
Port
3-0
0000
Csel
Bus Reset
Clken
10
Iclk
ns
Port
BOOT MODE
Alt
1000
USB
1001
PCIe
1010
UART
Csel Size
Csel
Bus Width
1100
GPMC NOR
Bus Width
Speed
Ack
1101
eMMC
Shaded cells are do not cares and pins can take any value.
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6.6.2.2.2 Backup Boot Mode Configuration
The mapping of backup boot mode configuration pins is shown in Table 6-7, Backup Boot Mode
Configuration.
Table 6-7. Backup Boot Mode Configuration (1)
BOOTMODE PINS
18
17
Mode
6-4
Port
Clkout
Interface
Volt
Port
1bit
000
None
001
USB
010
UART
011
Ethernet
100
MMC/SD
Port
Addr Width/Cmd
101
SPI
Csel
Speed
110
Hyperflash
111
I2C
Bus Reset
(1)
BACKUP BOOT MODE
16
Mode
Addr
Shaded cells are do not cares and pins can take any value.
ADVANCE INFORMATION
For more information about BOOTMODE Pin Mapping, see BOOTMODE Pin Mapping in the device TRM.
6.6.3
Boot Mode Selection
6.6.3.1
Primary Boot Mode Selection
The primary boot mode is the first mode attempted after reset. Table 6-8, Primary Boot Mode Selection
lists all possible primary boot modes.
Table 6-8. Primary Boot Mode Selection
BOOTMODE PINS
284
PRIMARY BOOT MODE SELECTED
3
2
1
0
0
0
0
0
Sleep (No boot – debug mode)
0
0
0
1
OSPI
0
0
1
0
QSPI
0
0
1
1
Hyperflash
0
1
0
0
SPI (on QSPI/OSPI port 0 in legacy SPI mode)
0
1
0
1
I2C
0
1
1
0
MMC/SD card, eMMC boot from UDA or file system
0
1
1
1
Ethernet
1
0
0
0
USB
1
0
0
1
PCIe
1
0
1
0
UART
1
0
1
1
Reserved
1
1
0
0
GPMC NOR
1
1
0
1
eMMC boot from boot partition (with auto-fall back to file system)
1
1
1
0
Reserved (acts as Sleep)
1
1
1
1
Reserved (acts as Sleep)
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Backup Boot Mode Selection
The backup boot mode is attempted if the primary boot mode fails. Note that if the primary boot device is
a flash device the primary boot mode will be re-tried at multiple different flash addresses before falling to
the backup boot mode. Table 6-9, Backup Mode Selection lists all possible backup boot modes.
Table 6-9. Backup Mode Selection
6.6.3.3
BACKUP BOOT MODE SELECTED
5
4
0
0
0
None (no backup boot will be attempted)
0
0
1
USB
0
1
0
UART
0
1
1
Ethernet
1
0
0
MMC/SD
1
0
1
SPI (on OSPI port 0 in legacy SPI mode)
1
1
0
Hyperflash
1
1
1
I2C
Min Pin
The min (minimal boot config) pin is provided as a way to use minimal pin count to configure boot. When
the min pin value is 1, all configuration fields are based on pre-defined default values. In this case, no
configuration pins (BOOTMODE[18:8]) need to be driven since their values are ignored.
Table 6-10. Min Pin Configuration
BOOTMODE PINS
MINIMAL PIN CONFIGURATION
7
0
All boot mode pins must be properly set
1
Certain boot mode pins are do not cares. ROM code uses built-in values
instead.
For more information about Boot Mode Selection, see BOOTMODE Pin Mapping in the device TRM.
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7 Applications, Implementation, and Layout
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test design implementation to confirm system functionality.
7.1
DDR Board Design and Layout Guidelines
The goal of the AM65x/DRA80xM DDR Board Design and Layout Guidelines is to make the DDR3L,
DDR4, and LPDDR4 system implementation straightforward for all designers. Requirements have been
distilled down to a set of layout and routing rules that allow designers to successfully implement a robust
design for the topologies that TI supports. TI only supports board designs using DDR3L, DDR4, and
LPDDR4 memories that follow the guidelines in this document.
7.2
OSPI Board Design and Layout Guidelines
ADVANCE INFORMATION
The following section details the routing guidelines that must be observed when routing the OSPI
interfaces.
7.2.1
No Loopback & Internal Pad Loopback
•
•
•
•
The MCU_OSPI[x]_CLK output signal must be connected to the CLK pin of the flash device
The signal propagation delay from the MCU_OSPI[x]_CLK signal to the flash device must be < 450pS
(~7cm as stripline or ~8cm as microstrip)
50 Ω PCB routing is recommended along with series terminations, as shown in Figure 7-1
Propagation delays and matching:
– A to B < 450ps
– Matching skew: < 60pS
A
B
R1
0 Ω*
MCU_OSPI[x]_CLK
OSPI/QSPI/SPI
device clock input
MCU_OSPI[x]_D[y],
MCU_OSPI[x]_CSn[z]
OSPI/QSPI/SPI
device IOy, CS#
OSPI_Board_01
*0 Ω resistor (R1), located as close as possible to the MCU_OSPI[x]_CLK pin, is placeholder for fine tuning, if needed
Figure 7-1. OSPI Interface High Level Schematic
7.2.2
External Board Loopback
•
286
The MCU_OSPI[x]_CLK output signal must be connected to the CLK pin of the flash device
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•
•
•
•
•
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The MCU_OSPI[x]_LBCLKO output signal must be looped back into the MCU_OSPI[x]_DQS input
The signal propagation delay from the MCU_OSPI[x]_CLK pin to the flash device CLK input pin (A to
B) should be approximately equal to half of the signal propagation delay from the
MCU_OPSI[x]_LBCLKO pin to the MCU_OSPI[x]_DQS pin ((C to D)/2). See the note below.
The signal propagation delay from the MCU_OSPI[x]_CLK pin to the flash device CLK input pin (A to
B) must be approximately equal to the signal propagation delay of the control and data signals
between the flash device and the SoC device (E to F, or F to E)
50 Ω PCB routing is recommended along with series terminations, as shown in Figure 7-2
Propagation delays and matching:
– A to B = E to F = (C to D) / 2
– Matching skew: < 60pS
NOTE
A
ADVANCE INFORMATION
The OSPI Board Loopback Hold time requirement (described in Section 5.9.5.18, OSPI) is
larger than the Hold time provided by a typical flash device. Therefore, the length of
MCU_OPSI[x]_LBCLKO pin to the MCU_OSPI[x]_DQS pin (C to D) may need to be
shortened to compensate.
B
R1
0 Ω*
OSPI/QSPI/SPI
device clock input
MCU_OSPI[x]_CLK
C
R1
0 Ω*
MCU_OSPI[x]_LBCLKO
D
MCU_OSPI[x]_DQS
E
F
MCU_OSPI[x]_D[y],
MCU_OSPI[x]_CSn[z]
OSPI/QSPI/SPI
device IOy, CS#
OSPI_Board_02
*0 Ω resistor (R1), located as close as possible to the MCU_OSPI[x]_CLK and MCU_OSPI[x]_LBCLKO pins, is
placeholder for fine tuning, if needed
Figure 7-2. OSPI Interface High Level Schematic
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DQS (only available in Octal Flash devices)
•
•
•
•
•
The MCU_OSPI[x]_CLK output signal must be connected to the CLK pin of the flash device
The DQS pin of the flash devices must be connected to MCU_OSPI[x]_DQS signal
The signal propagation delay from the MCU_OSPI[x]_CLK pin to the flash device CLK input pin (A to
B) should be approximately equal to the signal propagation delay from the MCU_OSPI[x]_DQS pin to
the DQS output pin (C to D)
50 Ω PCB routing is recommended along with series terminations, as shown in Figure 7-3
Propagation delays and matching:
– A to B = C to D
– Matching skew: < 60pS
A
B
R1
0 Ω*
ADVANCE INFORMATION
OSPI/QSPI/SPI
device clock input
MCU_OSPI[x]_CLK
C
D
OSPI device DQS
MCU_OSPI[x]_DQS
OSPI_Board_03
*0 Ω resistor (R1), located as close as possible to the MCU_OSPI[x]_CLK pin, is placeholder for fine tuning, if needed
Figure 7-3. OSPI Interface High Level Schematic
7.3
High Speed Differential Signal Routing Guidance
The High-Speed Interface Layout Guidelines provides guidance for successful routing of the high speed
differential signals. This includes PCB stackup and materials guidance as well as routing skew, length and
spacing limits. TI supports only designs that follow the board design guidelines contained in the
application report.
7.4
USB Design Guidelines
The USB 3.1 specification allows the VBUS voltage to be as high as 5.5 V for normal operation, and as
high as 20 V when the Power Delivery addendum is supported. Some automotive applications require a
max voltage to be 30 V.
The DRA80x device requires the VBUS signal voltage be scaled down using an external resistor divider
(as shown in the Figure 7-4), which limits the voltage applied to the actual device pin (USB0_VBUS,
USB1_VBUS). The tolerance of these external resistors should be equal to or less than 1%, and the
leakage current of zener diode at 5 V should be less than 100 nA.
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Device
USBn_VBUS
76.8 kΩ
±1%
16 kΩ
±1%
23.2 kΩ
±1%
VBUS signal
6.8V
(BZX84C6V8 or equivalent)
VSS
VSS
SPRSP08_USB_VBUS_01
Figure 7-4. USB VBUS Detect Voltage Divider / Clamp Circuit(1)
The USB0_VBUS and USB1_VBUS pins may be considered to be fail-safe because the external circuit in
Figure 7-4 limits the input current to the actual device pin in a case where VBUS is applied while the
device is powered off.
7.5
System Power Supply Monitor Design Guidelines
The VDDA_VSYS_MON pin provides a way to monitor the system power supply and is not fail-safe,
unless implemented with the appropriate resistor voltage divider source. This pin should be sourced with a
resistor voltage divider that receives its power from the system power supply.
The output of the resistor voltage divider is connected to the VDDA_VSYS_MON pin which has a trigger
voltage of 0.5 V ± 5%. The resistor voltage divider should be implemented such that it has a reference
current in the range of 1 µA to 50 µA, output voltage that never exceeds the maximum value defined in
Section 5.1, Absolute Maximums Ratings, and output voltage of 0.54 V when the system supply drops to
its lowest desired operating voltage.
The recommended output voltage of 0.54 V provides 40 mV of margin that includes 5% for tolerance of
the voltage monitor, 1% for tolerance of each resistor, plus 5 mV of potential error introduced by input
leakage current. This value ensures the voltage monitor will never trigger before reaching the expected
trigger voltage.
Figure 7-5 presents an example, when the system power supply voltage is nominally 5 V and the desired
trigger threshold is -10% or 4.5 V.
Device
VDDA_VSYS_MON
220 kΩ
±1%
VSYS
(System Power Suplpy)
30 kΩ
±1%
VSS
SPRSP08_VSYS_MON_01
Figure 7-5. System Supply Monitor Voltage Divider Circuit
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(1) USBn_VBUS, where n = 0 or 1.
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In this example the voltage divider ratio should be (4.5 V / 0.54 V) = 8.33 V. This ratio produces a 0.54 V
potential on the VDDA_VSYS_MON pin when the system power supply is 4.5 V. In this case, the voltage
monitor will trigger in the range of 3.88 V to 4.5 V. Precision 1% resistors with similar thermal coefficient
are recommended for implementing the resistor voltage divider.
7.6
MMC Design Guidelines
The MMC peripheral on this device contains an integrated SDIO LDO for handling automatic voltage
transitions for SD Interfaces. For details about how to connect the device pins associated with the SDIO
LDO, refer to Figure 7-10 through Figure 7-12.
7.7
Power Distribution Network Implementation Guidance
The Sitara™ Processor Power Distribution Networks: Implementation and Analysis provides guidance for
successful implementation of the power distribution network. This includes PCB stackup guidance as well
as guidance for optimizing the selection and placement of the decoupling capacitors. TI supports only
designs that follow the board design guidelines contained in the application report.
ADVANCE INFORMATION
7.8
External Capacitors
Figure 7-6 shows an example of the external decoupling capacitor connections.
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Compute
Cluster
Device
CORE
A53
MSMC
VDD_MPU1
VDD_MPU0
VDD_CORE
MCU
Domain
VDD_MCU
VPP_MCU
VDDA_ADC_MCU
MCU PLL
VDDA_MCU
SRAM LDO
CAP_VDDAR_MCU
CPSW PLL
Wakeup
Domain
VDDA_3P3_IOLDO_WKUP
I/O Bias LDO
VDDSHV0_WKUP (1)
CAP_VDDA_1P8_IOLDO_WKUP
VDDSHV1_WKUP (1)
VDDSHV2_WKUP (1)
VDDA_POR_WKUP
VDDS0_WKUP(1)
VDDS1_WKUP
(1)
VDDS2_WKUP(1)
LF OSC
HF OSC
VDDA_WKUP
SRAM LDO
CAP_VDDAR_WKUP
VDDA_LDO_WKUP
WKUP LDO
CAP_VDD_WKUP
VDD_WKUP0 (2)
VDD_WKUP1(2)
PCIE0
VDDA_1P8_CSI0
PCIE1
VDDS_OSC1
USB0 (1.8V)
VDDA_1P8_SERDES0
USB1 (1.8V)
VDDA_3P3_USB
USB0 (3.3V)
Main
Domain
ADVANCE INFORMATION
VDDA_1P8_OLDI0
USB1 (3.3V)
VDDA_DLL_MMC0
VDDA_DLL_MMC1
VDDA_PLL0_DDR
VDDA_PLL1_DDR
VDDA_PLL_CORE
VDDA_PLL_PER0
VDDA_PLL_DSS
VDDA_SRAM_CORE0
VDDA_SRAM_CORE1
SRAM LDO
CAP_VDDAR_CORE0
SRAM LDO
CAP_VDDAR_CORE1
SRAM LDO
CAP_VDDAR_CORE2
SRAM LDO
CAP_VDDAR_CORE3
VDDA_PLL_MPU0
SRAM LDO
CAP_VDDAR_MPU0_0
VDDA_SRAM_MPU0
SRAM LDO
CAP_VDDAR_MPU0_1
VDDA_PLL_MPU1
SRAM LDO
CAP_VDDAR_CORE4
VDDA_SRAM_MPU1
SRAM LDO
CAP_VDDAR_MPU1_0
SRAM LDO
CAP_VDDAR_MPU1_1
VDDS_DDR
VDDA_3P3_IOLDO0
I/O Bias LDO
CAP_VDDA_1P8_IOLDO0
VDDA_3P3_IOLDO1
I/O Bias LDO
CAP_VDDA_1P8_IOLDO1
VDDS0 (1)
VDDSHV0 (1)
VDDSHV1(1)
VDDS1(1)
VDDSHV2 (1)
VDDS2 (1)
VDDSHV3 (1)
VDDS3(1)
VDDSHV4 (1)
VDDS4(1)
VDDSHV5 (1)
VDDS5(1)
VDDSHV6 (1)(3)
VDDS6(1)(3)
VDDSHV7 (1)(3)
VDDS7 (1)(3)
VDDSHV8 (1)
VDDS8 (1)
VPP_CORE
MMC/SD
VDDA_1P8_SDIO
CAP_VDDA_1P8_SDIO
VDDA_3P3_SDIO
SDIO LDO
CAP_VDDSHV_SDIO
SPRSP08_DECOUPLING_CAPS_01
Figure 7-6. External decoupling capacitor connections
(1) Refer to Section 7.8.1, LVCMOS External Capacitor Connections for details about external capacitor connections for
VDDSHV[2:0]_WKUP, VDDSHV[8:0], VDDS[2:0]_WKUP, and VDDS[8:0].
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(2) In this Figure, the VDD_WKUP0 and VDD_WKUP1 supplies are sourced through the WKUP LDO, not an external supply.
(3) Refer to Figure 7-10 through Figure 7-12 for details about external capacitor connections when using the SDIO LDO.
7.8.1
LVCMOS External Capacitor Connections
Each VDDSHV[8:0] and VDDSHV[0:2]_WKUP can be configured as 1.8 V or 3.3 V. Figure 7-7 through
Figure 7-12 illustrate different system configurations for the dual-voltage I/O supplies.
VDDSHV[8:0] and VDDSHV[2:0]_WKUP are the dual-voltage LVCMOS I/O supplies, while VDDS[8:0] are
the dual-voltage LVCMOS I/O bias supplies. If any of the VDDSHV[8:0] or VDDSHV[2:0]_WKUP are
configured for 3.3 V operation, the corresponding VDDS[8:0] or VDDS[2:0]_WKUP should be sourced
from the internal I/O Bias LDO. When any of the VDDSHV[8:0] or VDDSHV[2:0]_WKUP are configured for
1.8 V operation, both VDDS[8:0] and VDDSHV[8:0] or VDDS[2:0]_WKUP and VDDSHV[2:0]_WKUP
should be supplied from the same source.
ADVANCE INFORMATION
Two I/O Bias LDOs are integrated on this device to share load current. The recommended load sharing is
as follows:
• IOLDO0 : VDDS0, VDDS1, VDDS2, VDDS5, VDDS7, VDDS8
• IOLDO1 : VDDS3, VDDS4, VDDS6
Figure 7-7 shows all VDDSHV[8:0] and VDDSHV[2:0]_WKUP supplies configured for 3.3V operation.
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Device
VDDA_3P3_IOLDO_WKUP
VDDSHV0_WKUP
Wakeup
Domain
I/O Bias LDO
CAP_VDDA_1P8_IOLDO_WKUP
VDDSHV1_WKUP
VDDA_POR_WKUP
VDDSHV2_WKUP
VDDS1_WKUP
VDDS2_WKUP
VDDS0_WKUP
VDDA_3P3_IOLDO1
I/O Bias LDO
CAP_VDDA_1P8_IOLDO1
VDDA_3P3_IOLDO0
I/O Bias LDO
CAP_VDDA_1P8_IOLDO0
VDDSHV0
VDDS0
VDDSHV1
VDDS1
VDDSHV2
VDDS2
VDDSHV5
VDDS5
VDDSHV7
VDDS7
VDDSHV8
VDDS8
VDDSHV3
VDDS3
VDDSHV4
VDDS4
VDDSHV6
VDDS6
ADVANCE INFORMATION
Main
Domain
SPRSP08_DECOUPLING_CAPS_01
Figure 7-7. All VDDSHV[8:0] and VDDSHV[2:0]_WKUP supplies configured for 3.3 V operation
(1) VDDS6 and VDDS7 can be connected to SDIO LDO in some use cases. See Figure 7-10 through Figure 7-12 for more details.
Figure 7-8 shows all VDDSHV[8:0] and VDDSHV[2:0]_WKUP supplies configured for 1.8 V operation.
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Device
Wakeup
Domain
VDDA_3P3_IOLDO_WKUP
I/O Bias LDO
CAP_VDDA_1P8_IOLDO_WKUP
VDDSHV0_WKUP
VDDA_POR_WKUP
VDDS1_WKUP (2)
VDDSHV1_WKUP
VDDS2_WKUP (2)
VDDSHV2_WKUP
VDDS0_WKUP (2)
Main
Domain
ADVANCE INFORMATION
VDDA_3P3_IOLDO0
I/O Bias LDO
CAP_VDDA_1P8_IOLDO0
VDDA_3P3_IOLDO1
I/O Bias LDO
CAP_VDDA_1P8_IOLDO1
VDDSHV0
VDDS0 (2)
VDDSHV1
VDDS1(2)
VDDSHV2
VDDS2 (2)
VDDSHV3
VDDS3(2)
VDDSHV4
VDDS4(2)
VDDSHV5
VDDS5(2)
VDDSHV6
VDDS6(2)
VDDSHV7
VDDS7 (2)
VDDSHV8
VDDS8 (2)
SPRSP08_DECOUPLING_CAPS_03
Figure 7-8. All VDDSHV[8:0] and VDDSHV[2:0]_WKUP supplies configured for 1.8V operation
(1) VDDS6 and VDDS7 can be connected to SDIO LDO in some use cases. See Figure 7-10 through Figure 7-12 for more details.
(2) When any of the VDDSHV[8:0] or VDDSHV[2:0]_WKUP are configured for 1.8 V operation, the corresponding VDDS[8:0] or
VDDS[2:0]_WKUP must be connected to their respective VDDSHV[8:0] or VDDSHV[2:0]_WKUP power supply.
294
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Figure 7-9 shows a split configuration where VDDSHV[0, 1, 2, 5, 7, 8] and VDDSHV0_WKUP are
configured for 3.3 V operation, while VDDSHV[3, 4, 6] and VDDSHV[2:1]_WKUP are configured for 1.8 V
operation. Note the colors indicate rails that are tied to the same source.
Device
VDDA_3P3_IOLDO_WKUP
Wakeup
Domain
I/O Bias LDO
VDDSHV0_WKUP
CAP_VDDA_1P8_IOLDO_WKUP
VDDSHV1_WKUP
VDDA_POR_WKUP
VDDS1_WKUP(2)
VDDS0_WKUP
VDDSHV2_WKUP
VDDS2_WKUP
(2)
VDDA_3P3_IOLDO1
I/O Bias LDO
CAP_VDDA_1P8_IOLDO1
VDDA_3P3_IOLDO0
I/O Bias LDO
CAP_VDDA_1P8_IOLDO0
VDDSHV0
ADVANCE INFORMATION
Main
Domain
VDDS0
VDDSHV1
VDDS1
VDDSHV2
VDDS2
VDDSHV5
VDDS5
VDDSHV7
VDDS7
VDDSHV8
VDDS8
VDDSHV3
VDDS3 (2)
VDDSHV4
VDDS4(2)
VDDSHV6
VDDS6 (2)
SPRSP08_DECOUPLING_CAPS_04
Figure 7-9. VDDSHV[8:0] and VDDSHV[2:0]_WKUP supplies configured for combination of 1.8 V or 3.3 V
operation
(1) VDDS6 and VDDS7 can be connected to SDIO LDO in some use cases. See Figure 7-10 through Figure 7-12 for more details.
(2) When any of the VDDSHV[8:0] or VDDSHV[2:0]_WKUP are configured for 1.8 V operation, the corresponding VDDS[8:0] or
VDDS[2:0]_WKUP must be connected to their respective VDDSHV[8:0] or VDDSHV[2:0]_WKUP power supply.
Figure 7-10 through Figure 7-12 illustrate the system configuration when VDDSHV6 or VDDSHV7 is used
as the MMC/SD supply.
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Device
MMC/SD
VDDA_1P8_SDIO
VDDA_3P3_SDIO
SDIO LDO
CAP_VDDA_1P8_SDIO
CAP_VDDSHV_SDIO
VSS
VSS
VDDSHVn (1)
VDDSn
(1)
1.8V
SPRSP08_DECOUPLING_CAPS_06
Figure 7-10. VDDSHV6 or VDDSHV7 used as the MMC/SD supply for fixed 1.8V IO
(1) VDDSHVn and VDDSn, where n = 6 or 7.
ADVANCE INFORMATION
(2) VDDA_1P8_SDIO, CAP_VDDA_1P8_SDIO, CAP_VDDSHV_SDIO, and VDDA_3P3_SDIO must be connected to VSS, when
SDIO_LDO is not used with either MMC0 or MMC1.
Device
MMC/SD
VDDA_1P8_SDIO
3.3V
VDDA_3P3_SDIO
SDIO LDO
CAP_VDDA_1P8_SDIO
CAP_VDDSHV_SDIO
VDDSHVn (1)
VDDSn (1)
SPRSP08_DECOUPLING_CAPS_07
Figure 7-11. VDDSHV6 or VDDSHV7 used as the MMC/SD supply for fixed 3.3V IO
(1) VDDSHVn and VDDSn, where n = 6 or 7.
Device
MMC/SD
VDDA_1P8_SDIO
3.3V
VDDA_3P3_SDIO
SDIO LDO
CAP_VDDA_1P8_SDIO
CAP_VDDSHV_SDIO
VDDSHVn (1)
VDDSn (1)
SPRSP08_DECOUPLING_CAPS_05
Figure 7-12. VDDSHV6 or VDDSHV7 used as the MMC/SD supply for dynamic 3.3V/1.8V IO
(1) VDDSHVn and VDDSn, where n = 6 or 7.
296
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7.9
SPRSP31E – APRIL 2018 – REVISED JUNE 2019
Thermal Solution Guidance
ADVANCE INFORMATION
The Thermal Design Guide for DSP and ARM Application Processors provides guidance for successful
implementation of a thermal solution for system designs containing this device. This document provides
background information on common terms and methods related to thermal solutions. TI only supports
designs that follow system design guidelines contained in the application report.
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8 Device and Documentation Support
TI offers an extensive line of development tools. Tools and software to evaluate the performance of the
device, generate code, and develop solutions are listed below.
8.1
Device Nomenclature
To designate the stages in the product development cycle, TI assigns prefixes to the part numbers of all
microprocessors (MPUs) and support tools. Each device has one of three prefixes: X, P, or null (no prefix)
(for example, DRA80x). Texas Instruments recommends two of three possible prefix designators for its
support tools: TMDX and TMDS. These prefixes represent evolutionary stages of product development
from engineering prototypes (TMDX) through fully qualified production devices and tools (TMDS).
Device development evolutionary flow:
ADVANCE INFORMATION
X
Experimental device that is not necessarily representative of the final device's electrical
specifications and may not use production assembly flow.
P
Prototype device that is not necessarily the final silicon die and may not necessarily meet
final electrical specifications.
null
Production version of the silicon die that is fully qualified.
Support tool development evolutionary flow:
TMDX
Development-support product that has not yet completed Texas Instruments internal
qualification testing.
TMDS
Fully-qualified development-support product.
X and P devices and TMDX development-support tools are shipped against the following disclaimer:
"Developmental product is intended for internal evaluation purposes."
Production devices and TMDS development-support tools have been characterized fully, and the quality
and reliability of the device have been demonstrated fully. TI's standard warranty applies.
Predictions show that prototype devices (X or P) have a greater failure rate than the standard production
devices. Texas Instruments recommends that these devices not be used in any production system
because their expected end-use failure rate still is undefined. Only qualified production devices are to be
used.
For orderable part numbers of DRA80x devices in the ACD package type, see the Package Option
Addendum of this document, the TI website (ti.com), or contact your TI sales representative.
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8.1.1
SPRSP31E – APRIL 2018 – REVISED JUNE 2019
Standard Package Symbolization
JACINTO
aBBBBBBBrzIYyPPPQ1
ADVANCE INFORMATION
XXXXXXX
ZZZ G1
YYY
PIN ONE INDICATOR
O
SPRSP31_PACK_01
Figure 8-1. Printed Device Reference
8.1.2
Device Naming Convention
Table 8-1. Nomenclature Description
FIELD PARAMETER
FIELD DESCRIPTION
VALUE
a
Device evolution stage
X
Prototype
P
Preproduction (production test flow, no reliability data)
BLANK
BBBBBBB
Base production part
number
DRA802M Dual Core High Tier (See Table 3-1, Device Comparison)
r
Device revision
BLANK
Device Speed
X
OTHER
I
PPP
Production
DRA804M Quad Core High Tier (See Table 3-1, Device Comparison)
z
Yy
DESCRIPTION
SR 1.0
High speed grade (See Table 5-1, Speed Grade Maximum Frequency)
Alternate speed grade
ICSS designator
6
6 × ICSS MAC ports
Device type
G
General purpose (Prototype and Production)
C
ASIL Certified devices
S
ASIL Certified devices, Secure Boot Supported
H
High security devices
Package Designator
Q1
Automotive Designator
XXXXXXX
Lot Trace Code (LTC)
ACD
BLANK
Q1
YYY
Production Code; For TI use only
ZZZ
Production Code; For TI use only
O
Pin one designator
G1
ECAT—Green package designator
ACD FCBGA-N784 (23mm × 23mm) Package
not meeting automotive qualification
meeting Q100 equal requirements, with exceptions as specified in DM.
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(1) To designate the stages in the product development cycle, TI assigns prefixes to the part numbers. These prefixes represent
evolutionary stages of product development from engineering prototypes through fully qualified production devices.
Prototype devices are shipped against the following disclaimer:
“This product is still in development and is intended for internal evaluation purposes.”
Notwithstanding any provision to the contrary, TI makes no warranty expressed, implied, or statutory, including any implied warranty of
merchantability of fitness for a specific purpose, of this device.
(2) Applies to device max junction temperature.
NOTE
BLANK in the symbol or part number is collapsed so there are no gaps between characters.
8.2
Tools and Software
The following products support development for DRA80x platforms:
Design kits and evaluation modules
ADVANCE INFORMATION
DRA80xM Evaluation Module The DRA80xM evaluation module (EVM) is a development platform for
evaluating high speed networking capabilities of Jacinto™ DRA80xM processors for
automotive gateway and domain controller applications. DRA80xM devices feature Arm®
Cortex-A53 main processing units (MPUs) with auxiliary Arm® Cortex-R5F MPUs for timesensitive tasks. The EVM also integrates a host of peripherals including gigabit Ethernet,
PCIe Gen3.1, and CAN-FD.
Development tools
Clock Tree Tool for Sitara, Automotive, Vision Analytics, & Digital Signal Processors
The Clock
Tree Tool (CTT) for Sitara™ ARM®, Automotive, and Digital Signal Processors is an
interactive clock tree configuration software that provides information about the clocks and
modules in these TI devices. It allows the user to:
• Visualize the device clock tree
• Interact with clock tree elements and view the effect on PRCM registers
• Interact with the PRCM registers and view the effect on the device clock tree
• View a trace of all the device registers affected by the user interaction with clock tree
Code Composer Studio (CCS) Integrated Development Environment (IDE) for Sitara ARM
Processors
Code Composer Studio is an integrated development environment (IDE) that supports TI's
Microcontroller and Embedded Processors portfolio. Code Composer Studio comprises a
suite of tools used to develop and debug embedded applications. It includes an optimizing
C/C++ compiler, source code editor, project build environment, debugger, profiler, and many
other features. The intuitive IDE provides a single user interface taking you through each
step of the application development flow. Familiar tools and interfaces allow users to get
started faster than ever before. Code Composer Studio combines the advantages of the
Eclipse software framework with advanced embedded debug capabilities from TI resulting in
a compelling feature-rich development environment for embedded developers.
Pin mux tool The Pin MUX Utility is a software tool which provides a Graphical User Interface for
configuring pin multiplexing settings, resolving conflicts and specifying I/O cell characteristics
for TI MPUs. Results are output as C header/code files that can be imported into software
development kits (SDKs) or used to configure customer's custom software. Version 4 of the
Pin Mux utility adds the capability of automatically selecting a mux configuration that satisfies
the entered requirements.
Models
AM654x/DRA80xM BSDL Model BSDL Model
AM654x/DRA80xM IBIS File IBIS Model
AM654x/DRA80xM Thermal Models Thermal Model
For a complete listing of development-support tools for the processor platform, visit the Texas Instruments
website at ti.com. For information on pricing and availability, contact the nearest TI field sales office or
authorized distributor.
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8.3
SPRSP31E – APRIL 2018 – REVISED JUNE 2019
Documentation Support
To receive notification of documentation updates, navigate to the device product folder on ti.com. In the
upper right corner, click on Alert me to register and receive a weekly digest of any product information that
has changed. For change details, review the revision history included in any revised document.
The following documents describe the DRA80x devices.
Technical Reference Manual
AM65x/DRA80xM Processors
Details the integration, the environment, the functional description, and the programming
models for each peripheral and subsystem in the DRA80x family of devices.
Errata
AM65x/DRA80xM Processors Silicon Revision 1.0
Describes the known exceptions to the functional specifications for the device.
Related Links
The table below lists quick access links. Categories include technical documents, support and community
resources, tools and software, and quick access to sample or buy.
Table 8-2. Related Links
8.5
PARTS
PRODUCT FOLDER
SAMPLE & BUY
TECHNICAL
DOCUMENTS
TOOLS &
SOFTWARE
SUPPORT &
COMMUNITY
DRA80M
Click here
Click here
Click here
Click here
Click here
Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the
respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views;
see TI's Terms of Use.
TI E2E™ Online Community The TI engineer-to-engineer (E2E) community was created to foster
collaboration among engineers. At e2e.ti.com, you can ask questions, share knowledge,
explore ideas and help solve problems with fellow engineers.
TI Embedded Processors Wiki Established to help developers get started with Embedded Processors
from Texas Instruments and to foster innovation and growth of general knowledge about the
hardware and software surrounding these devices.
8.6
Trademarks
SafeTI, E2E are trademarks of Texas Instruments.
Arm® Neon, Neon, CoreSight are trademarks of Arm Limited (or its subsidiaries) in the US and/or
elsewhere.
Arm, Cortex, TrustZone are registered trademarks of Arm Limited (or its subsidiaries) in the US and/or
elsewhere.
OSPI is a trademark of Cadence Design Systems, Inc.
Cypress is a registered trademark of Cypress Semiconductor Corporation.
EnDat is a registered trademark of Dr. Johannes Heidenhain GmbH company with limited liability Fed Rep
Germany.
MIPI is a registered trademark of MIPI Alliance, Inc.
HyperBus is a trademark of Mobiveil Inc.
MMC, eMMC are trademarks of MultiMediaCard Association.
I2C is a trademark of NXP Semiconductors.
PCI-Express, PCIe are registered trademarks of PCI-SIG.
Secure Digital, SD are registered trademarks of SD Card Association.
All other trademarks are the property of their respective owners.
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ADVANCE INFORMATION
8.4
DRA80M
SPRSP31E – APRIL 2018 – REVISED JUNE 2019
8.7
www.ti.com
Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
8.8
Glossary
TI Glossary This glossary lists and explains terms, acronyms, and definitions.
ADVANCE INFORMATION
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SPRSP31E – APRIL 2018 – REVISED JUNE 2019
9 Mechanical, Packaging, and Orderable Information
9.1
Packaging Information
ADVANCE INFORMATION
The following pages include mechanical, packaging, and orderable information. This information is the
most current data available for the designated devices. This data is subject to change without notice and
revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
Copyright © 2018–2019, Texas Instruments Incorporated
Mechanical, Packaging, and Orderable Information
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PACKAGE OPTION ADDENDUM
www.ti.com
25-Jun-2019
PACKAGING INFORMATION
Orderable Device
Status
(1)
XDRA804MX6GACDQ1
ACTIVE
Package Type Package Pins Package
Drawing
Qty
FCBGA
ACD
784
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
TBD
Call TI
Call TI
Op Temp (°C)
Device Marking
(4/5)
-40 to 125
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
Samples
PACKAGE OUTLINE
ACD0784A
FCBGA - 1.63 mm max height
SCALE 0.600
BALL GRID ARRAY
23.1
22.9
B
A
BALL A1
CORNER
(
23.1
22.9
17)
4X (R1)
(0.4)
(0.635)
1.63 MAX
C
SEATING PLANE
BALL TYP
0.42
0.32
0.2 C
21.6
TYP
SYMM
(0.7) TYP
AH
21.6
TYP
0.8
TYP
AG
AF
AE
AD
AC
AB
AA
Y
W
V
U
T
R
P
N
M
L
K
J
H
G
F
E
D
C
(0.7) TYP
SYMM
784X
0.57
0.47
0.2
C A B
0.08
C
B
A
1
2
3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28
0.8 TYP
4223579/B 01/2019
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
www.ti.com
EXAMPLE BOARD LAYOUT
ACD0784A
FCBGA - 1.63 mm max height
BALL GRID ARRAY
(0.8) TYP
784X ( 0.4)
1
2 3
4
5
6
7
8
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28
A
B
C
(0.8) TYP
D
E
F
G
H
J
K
L
M
N
SYMM
P
R
T
U
V
W
Y
AA
AB
AC
AD
AE
AF
AG
AH
SYMM
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE: 4X
0.05 MAX
METAL UNDER
SOLDER MASK
0.05 MIN
( 0.4)
METAL
SOLDER MASK
OPENING
EXPOSED
METAL
NON-SOLDER MASK
DEFINED
(PREFERRED)
( 0.4)
SOLDER MASK
OPENING
EXPOSED
METAL
SOLDER MASK
DEFINED
SOLDER MASK DETAILS
NOT TO SCALE
4223579/B 01/2019
NOTES: (continued)
3. Final dimensions may vary due to manufacturing tolerance considerations and also routing constraints.
See Texas Instruments Literature No. SPRU811 (www.ti.com/lit/spru811).
www.ti.com
EXAMPLE STENCIL DESIGN
ACD0784A
FCBGA - 1.63 mm max height
BALL GRID ARRAY
(0.8) TYP
784X ( 0.4)
1
2 3
4
5
6
7
8
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28
A
B
C
(0.8) TYP
D
E
F
G
H
J
K
L
M
N
SYMM
P
R
T
U
V
W
Y
AA
AB
AC
AD
AE
AF
AG
AH
SYMM
SOLDER PASTE EXAMPLE
BASED ON 0.15 mm THICK STENCIL
SCALE: 4X
4223579/B 01/2019
NOTES: (continued)
4. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release.
www.ti.com
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TI PROVIDES TECHNICAL AND RELIABILITY DATA (INCLUDING DATASHEETS), DESIGN RESOURCES (INCLUDING REFERENCE
DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND OTHER RESOURCES “AS IS”
AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS AND IMPLIED, INCLUDING WITHOUT LIMITATION ANY
IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD
PARTY INTELLECTUAL PROPERTY RIGHTS.
These resources are intended for skilled developers designing with TI products. You are solely responsible for (1) selecting the appropriate
TI products for your application, (2) designing, validating and testing your application, and (3) ensuring your application meets applicable
standards, and any other safety, security, or other requirements. These resources are subject to change without notice. TI grants you
permission to use these resources only for development of an application that uses the TI products described in the resource. Other
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