Texas Instruments | Tiva™ C Series TM4C1230C3PM Microcontroller Data Sheet (Rev. E) | Datasheet | Texas Instruments Tiva™ C Series TM4C1230C3PM Microcontroller Data Sheet (Rev. E) Datasheet

Texas Instruments Tiva™ C Series TM4C1230C3PM Microcontroller Data Sheet (Rev. E) Datasheet
TE X AS I NS TRUM E NTS - P RO DUCTION D ATA
Tiva™ TM4C1230C3PM Microcontroller
D ATA SHE E T
D S -T M 4C 1230 C3 P M - 1 5 8 4 2 . 2 7 4 1
S P M S 329E
C o p yri g h t © 2 0 07-2014
Te xa s In stru me n ts In co rporated
Copyright
Copyright © 2007-2014 Texas Instruments Incorporated. Tiva and TivaWare are trademarks of Texas Instruments Incorporated. ARM and Thumb are
registered trademarks and Cortex is a trademark of ARM Limited. All other trademarks are the property of others.
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard
warranty. Production processing does not necessarily include testing of all parameters.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor
products and disclaimers thereto appears at the end of this data sheet.
Texas Instruments Incorporated
108 Wild Basin, Suite 350
Austin, TX 78746
http://www.ti.com/tm4c
http://www-k.ext.ti.com/sc/technical-support/product-information-centers.htm
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Table of Contents
Revision History ............................................................................................................................. 30
About This Document .................................................................................................................... 33
Audience ..............................................................................................................................................
About This Manual ................................................................................................................................
Related Documents ...............................................................................................................................
Documentation Conventions ..................................................................................................................
33
33
33
34
1
Architectural Overview .......................................................................................... 36
1.1
1.2
1.3
1.3.1
1.3.2
1.3.3
1.3.4
1.3.5
1.3.6
1.3.7
1.4
1.5
1.6
Tiva™ C Series Overview .............................................................................................. 36
TM4C1230C3PM Microcontroller Overview ..................................................................... 37
TM4C1230C3PM Microcontroller Features ..................................................................... 39
ARM Cortex-M4F Processor Core .................................................................................. 39
On-Chip Memory ........................................................................................................... 41
Serial Communications Peripherals ................................................................................ 43
System Integration ........................................................................................................ 46
Analog .......................................................................................................................... 51
JTAG and ARM Serial Wire Debug ................................................................................ 53
Packaging and Temperature .......................................................................................... 54
TM4C1230C3PM Microcontroller Hardware Details ......................................................... 54
Kits .............................................................................................................................. 54
Support Information ....................................................................................................... 54
2
The Cortex-M4F Processor ................................................................................... 55
2.1
2.2
2.2.1
2.2.2
2.2.3
2.2.4
2.3
2.3.1
2.3.2
2.3.3
2.3.4
2.3.5
2.3.6
2.4
2.4.1
2.4.2
2.4.3
2.4.4
2.4.5
2.4.6
2.4.7
2.5
2.5.1
2.5.2
Block Diagram .............................................................................................................. 56
Overview ...................................................................................................................... 57
System-Level Interface .................................................................................................. 57
Integrated Configurable Debug ...................................................................................... 57
Trace Port Interface Unit (TPIU) ..................................................................................... 58
Cortex-M4F System Component Details ......................................................................... 58
Programming Model ...................................................................................................... 59
Processor Mode and Privilege Levels for Software Execution ........................................... 59
Stacks .......................................................................................................................... 60
Register Map ................................................................................................................ 60
Register Descriptions .................................................................................................... 62
Exceptions and Interrupts .............................................................................................. 78
Data Types ................................................................................................................... 78
Memory Model .............................................................................................................. 78
Memory Regions, Types and Attributes ........................................................................... 80
Memory System Ordering of Memory Accesses .............................................................. 81
Behavior of Memory Accesses ....................................................................................... 81
Software Ordering of Memory Accesses ......................................................................... 82
Bit-Banding ................................................................................................................... 83
Data Storage ................................................................................................................ 85
Synchronization Primitives ............................................................................................. 86
Exception Model ........................................................................................................... 87
Exception States ........................................................................................................... 88
Exception Types ............................................................................................................ 88
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2.5.3
2.5.4
2.5.5
2.5.6
2.5.7
2.6
2.6.1
2.6.2
2.6.3
2.6.4
2.7
2.7.1
2.7.2
2.8
Exception Handlers ....................................................................................................... 92
Vector Table .................................................................................................................. 92
Exception Priorities ....................................................................................................... 93
Interrupt Priority Grouping .............................................................................................. 94
Exception Entry and Return ........................................................................................... 94
Fault Handling .............................................................................................................. 97
Fault Types ................................................................................................................... 98
Fault Escalation and Hard Faults .................................................................................... 98
Fault Status Registers and Fault Address Registers ........................................................ 99
Lockup ......................................................................................................................... 99
Power Management .................................................................................................... 100
Entering Sleep Modes ................................................................................................. 100
Wake Up from Sleep Mode .......................................................................................... 100
Instruction Set Summary .............................................................................................. 101
3
Cortex-M4 Peripherals ......................................................................................... 108
3.1
3.1.1
3.1.2
3.1.3
3.1.4
3.1.5
3.2
3.3
3.4
3.5
3.6
3.7
Functional Description ................................................................................................. 108
System Timer (SysTick) ............................................................................................... 109
Nested Vectored Interrupt Controller (NVIC) .................................................................. 110
System Control Block (SCB) ........................................................................................ 111
Memory Protection Unit (MPU) ..................................................................................... 111
Floating-Point Unit (FPU) ............................................................................................. 116
Register Map .............................................................................................................. 120
System Timer (SysTick) Register Descriptions .............................................................. 123
NVIC Register Descriptions .......................................................................................... 127
System Control Block (SCB) Register Descriptions ........................................................ 142
Memory Protection Unit (MPU) Register Descriptions .................................................... 171
Floating-Point Unit (FPU) Register Descriptions ............................................................ 180
4
JTAG Interface ...................................................................................................... 186
4.1
4.2
4.3
4.3.1
4.3.2
4.3.3
4.3.4
4.4
4.5
4.5.1
4.5.2
Block Diagram ............................................................................................................
Signal Description .......................................................................................................
Functional Description .................................................................................................
JTAG Interface Pins .....................................................................................................
JTAG TAP Controller ...................................................................................................
Shift Registers ............................................................................................................
Operational Considerations ..........................................................................................
Initialization and Configuration .....................................................................................
Register Descriptions ..................................................................................................
Instruction Register (IR) ...............................................................................................
Data Registers ............................................................................................................
187
187
188
188
190
190
191
193
194
194
196
5
System Control ..................................................................................................... 198
5.1
5.2
5.2.1
5.2.2
5.2.3
5.2.4
5.2.5
5.2.6
Signal Description .......................................................................................................
Functional Description .................................................................................................
Device Identification ....................................................................................................
Reset Control ..............................................................................................................
Non-Maskable Interrupt ...............................................................................................
Power Control .............................................................................................................
Clock Control ..............................................................................................................
System Control ...........................................................................................................
4
198
198
198
199
204
204
205
211
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5.3
5.4
5.5
5.6
Initialization and Configuration .....................................................................................
Register Map ..............................................................................................................
System Control Register Descriptions ...........................................................................
System Control Legacy Register Descriptions ...............................................................
215
216
220
381
6
System Exception Module ................................................................................... 438
6.1
6.2
6.3
Functional Description ................................................................................................. 438
Register Map .............................................................................................................. 438
Register Descriptions .................................................................................................. 438
7
Internal Memory ................................................................................................... 446
7.1
7.2
7.2.1
7.2.2
7.2.3
7.2.4
7.3
7.4
7.5
7.6
Block Diagram ............................................................................................................ 446
Functional Description ................................................................................................. 447
SRAM ........................................................................................................................ 447
ROM .......................................................................................................................... 448
Flash Memory ............................................................................................................. 450
EEPROM .................................................................................................................... 456
Register Map .............................................................................................................. 461
Flash Memory Register Descriptions (Flash Control Offset) ............................................ 463
EEPROM Register Descriptions (EEPROM Offset) ........................................................ 481
Memory Register Descriptions (System Control Offset) .................................................. 498
8
Micro Direct Memory Access (μDMA) ................................................................ 506
8.1
8.2
8.2.1
8.2.2
8.2.3
8.2.4
8.2.5
8.2.6
8.2.7
8.2.8
8.2.9
8.2.10
8.3
8.3.1
8.3.2
8.3.3
8.3.4
8.3.5
8.4
8.5
8.6
Block Diagram ............................................................................................................ 507
Functional Description ................................................................................................. 507
Channel Assignments .................................................................................................. 508
Priority ........................................................................................................................ 509
Arbitration Size ............................................................................................................ 509
Request Types ............................................................................................................ 509
Channel Configuration ................................................................................................. 510
Transfer Modes ........................................................................................................... 512
Transfer Size and Increment ........................................................................................ 520
Peripheral Interface ..................................................................................................... 520
Software Request ........................................................................................................ 520
Interrupts and Errors .................................................................................................... 521
Initialization and Configuration ..................................................................................... 521
Module Initialization ..................................................................................................... 521
Configuring a Memory-to-Memory Transfer ................................................................... 522
Configuring a Peripheral for Simple Transmit ................................................................ 523
Configuring a Peripheral for Ping-Pong Receive ............................................................ 525
Configuring Channel Assignments ................................................................................ 527
Register Map .............................................................................................................. 527
μDMA Channel Control Structure ................................................................................. 529
μDMA Register Descriptions ........................................................................................ 536
9
General-Purpose Input/Outputs (GPIOs) ........................................................... 570
9.1
9.2
9.2.1
9.2.2
9.2.3
Signal Description .......................................................................................................
Functional Description .................................................................................................
Data Control ...............................................................................................................
Interrupt Control ..........................................................................................................
Mode Control ..............................................................................................................
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573
574
575
576
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9.2.4
9.2.5
9.2.6
9.3
9.4
9.5
Commit Control ........................................................................................................... 577
Pad Control ................................................................................................................. 577
Identification ............................................................................................................... 577
Initialization and Configuration ..................................................................................... 577
Register Map .............................................................................................................. 579
Register Descriptions .................................................................................................. 582
10
General-Purpose Timers ...................................................................................... 625
10.1
10.2
10.3
10.3.1
10.3.2
10.3.3
10.3.4
10.3.5
10.3.6
10.3.7
10.4
10.4.1
10.4.2
10.4.3
10.4.4
10.4.5
10.5
10.6
Block Diagram ............................................................................................................ 626
Signal Description ....................................................................................................... 627
Functional Description ................................................................................................. 628
GPTM Reset Conditions .............................................................................................. 629
Timer Modes ............................................................................................................... 630
Wait-for-Trigger Mode .................................................................................................. 639
Synchronizing GP Timer Blocks ................................................................................... 640
DMA Operation ........................................................................................................... 641
Accessing Concatenated 16/32-Bit GPTM Register Values ............................................ 641
Accessing Concatenated 32/64-Bit Wide GPTM Register Values .................................... 641
Initialization and Configuration ..................................................................................... 643
One-Shot/Periodic Timer Mode .................................................................................... 643
Real-Time Clock (RTC) Mode ...................................................................................... 644
Input Edge-Count Mode ............................................................................................... 644
Input Edge Time Mode ................................................................................................. 645
PWM Mode ................................................................................................................. 645
Register Map .............................................................................................................. 646
Register Descriptions .................................................................................................. 647
11
Watchdog Timers ................................................................................................. 695
11.1
11.2
11.2.1
11.3
11.4
11.5
Block Diagram ............................................................................................................
Functional Description .................................................................................................
Register Access Timing ...............................................................................................
Initialization and Configuration .....................................................................................
Register Map ..............................................................................................................
Register Descriptions ..................................................................................................
696
696
697
697
697
698
12
Analog-to-Digital Converter (ADC) ..................................................................... 720
12.1
12.2
12.3
12.3.1
12.3.2
12.3.3
12.3.4
12.3.5
12.3.6
12.3.7
12.4
12.4.1
12.4.2
12.5
12.6
Block Diagram ............................................................................................................ 721
Signal Description ....................................................................................................... 722
Functional Description ................................................................................................. 723
Sample Sequencers .................................................................................................... 723
Module Control ............................................................................................................ 724
Hardware Sample Averaging Circuit ............................................................................. 727
Analog-to-Digital Converter .......................................................................................... 728
Differential Sampling ................................................................................................... 731
Internal Temperature Sensor ........................................................................................ 733
Digital Comparator Unit ............................................................................................... 734
Initialization and Configuration ..................................................................................... 738
Module Initialization ..................................................................................................... 738
Sample Sequencer Configuration ................................................................................. 739
Register Map .............................................................................................................. 739
Register Descriptions .................................................................................................. 741
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Universal Asynchronous Receivers/Transmitters (UARTs) ............................. 811
13.1
Block Diagram ............................................................................................................
13.2
Signal Description .......................................................................................................
13.3
Functional Description .................................................................................................
13.3.1 Transmit/Receive Logic ...............................................................................................
13.3.2 Baud-Rate Generation .................................................................................................
13.3.3 Data Transmission ......................................................................................................
13.3.4 Serial IR (SIR) .............................................................................................................
13.3.5 ISO 7816 Support .......................................................................................................
13.3.6 Modem Handshake Support .........................................................................................
13.3.7 9-Bit UART Mode ........................................................................................................
13.3.8 FIFO Operation ...........................................................................................................
13.3.9 Interrupts ....................................................................................................................
13.3.10 Loopback Operation ....................................................................................................
13.3.11 DMA Operation ...........................................................................................................
13.4
Initialization and Configuration .....................................................................................
13.5
Register Map ..............................................................................................................
13.6
Register Descriptions ..................................................................................................
812
812
813
813
814
815
815
816
817
818
818
818
819
820
820
821
823
14
Synchronous Serial Interface (SSI) .................................................................... 870
14.1
14.2
14.3
14.3.1
14.3.2
14.3.3
14.3.4
14.3.5
14.4
14.5
14.6
Block Diagram ............................................................................................................
Signal Description .......................................................................................................
Functional Description .................................................................................................
Bit Rate Generation .....................................................................................................
FIFO Operation ...........................................................................................................
Interrupts ....................................................................................................................
Frame Formats ...........................................................................................................
DMA Operation ...........................................................................................................
Initialization and Configuration .....................................................................................
Register Map ..............................................................................................................
Register Descriptions ..................................................................................................
15
Inter-Integrated Circuit (I2C) Interface ................................................................ 915
15.1
15.2
15.3
15.3.1
15.3.2
15.3.3
15.3.4
15.3.5
15.4
15.4.1
15.4.2
15.5
15.6
15.7
15.8
Block Diagram ............................................................................................................ 916
Signal Description ....................................................................................................... 916
Functional Description ................................................................................................. 917
I2C Bus Functional Overview ........................................................................................ 917
Available Speed Modes ............................................................................................... 922
Interrupts .................................................................................................................... 924
Loopback Operation .................................................................................................... 925
Command Sequence Flow Charts ................................................................................ 925
Initialization and Configuration ..................................................................................... 933
Configure the I2C Module to Transmit a Single Byte as a Master .................................... 933
Configure the I2C Master to High Speed Mode .............................................................. 934
Register Map .............................................................................................................. 935
Register Descriptions (I2C Master) ............................................................................... 936
Register Descriptions (I2C Slave) ................................................................................. 953
Register Descriptions (I2C Status and Control) .............................................................. 963
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871
872
872
873
873
874
882
883
885
886
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16
Controller Area Network (CAN) Module ............................................................. 966
16.1
Block Diagram ............................................................................................................ 967
16.2
Signal Description ....................................................................................................... 967
16.3
Functional Description ................................................................................................. 968
16.3.1 Initialization ................................................................................................................. 969
16.3.2 Operation ................................................................................................................... 969
16.3.3 Transmitting Message Objects ..................................................................................... 970
16.3.4 Configuring a Transmit Message Object ........................................................................ 971
16.3.5 Updating a Transmit Message Object ........................................................................... 972
16.3.6 Accepting Received Message Objects .......................................................................... 972
16.3.7 Receiving a Data Frame .............................................................................................. 973
16.3.8 Receiving a Remote Frame .......................................................................................... 973
16.3.9 Receive/Transmit Priority ............................................................................................. 974
16.3.10 Configuring a Receive Message Object ........................................................................ 974
16.3.11 Handling of Received Message Objects ........................................................................ 975
16.3.12 Handling of Interrupts .................................................................................................. 977
16.3.13 Test Mode ................................................................................................................... 978
16.3.14 Bit Timing Configuration Error Considerations ............................................................... 980
16.3.15 Bit Time and Bit Rate ................................................................................................... 980
16.3.16 Calculating the Bit Timing Parameters .......................................................................... 982
16.4
Register Map .............................................................................................................. 985
16.5
CAN Register Descriptions .......................................................................................... 986
17
Analog Comparators .......................................................................................... 1016
17.1
17.2
17.3
17.3.1
17.4
17.5
17.6
Block Diagram ...........................................................................................................
Signal Description .....................................................................................................
Functional Description ...............................................................................................
Internal Reference Programming ................................................................................
Initialization and Configuration ....................................................................................
Register Map ............................................................................................................
Register Descriptions .................................................................................................
18
Pin Diagram ........................................................................................................ 1031
1017
1017
1018
1019
1021
1021
1022
19
Signal Tables ...................................................................................................... 1032
19.1
19.2
19.3
19.4
19.5
19.6
Signals by Pin Number ..............................................................................................
Signals by Signal Name .............................................................................................
Signals by Function, Except for GPIO .........................................................................
GPIO Pins and Alternate Functions ............................................................................
Possible Pin Assignments for Alternate Functions .......................................................
Connections for Unused Signals .................................................................................
1033
1038
1044
1048
1051
1053
20
Electrical Characteristics .................................................................................. 1055
20.1
20.2
20.3
20.4
20.5
20.6
20.6.1
20.6.2
Maximum Ratings ......................................................................................................
Operating Characteristics ...........................................................................................
Recommended Operating Conditions .........................................................................
Load Conditions ........................................................................................................
JTAG and Boundary Scan ..........................................................................................
Power and Brown-Out ...............................................................................................
VDDA Levels ............................................................................................................
VDD Levels ...............................................................................................................
8
1055
1056
1057
1059
1060
1062
1062
1063
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20.6.3 VDDC Levels ............................................................................................................ 1064
20.6.4 VDD Glitches ............................................................................................................ 1065
20.6.5 VDD Droop Response ............................................................................................... 1065
20.7
Reset ........................................................................................................................ 1067
20.8
On-Chip Low Drop-Out (LDO) Regulator ..................................................................... 1070
20.9
Clocks ...................................................................................................................... 1071
20.9.1 PLL Specifications ..................................................................................................... 1071
20.9.2 PIOSC Specifications ................................................................................................ 1072
20.9.3 Low-Frequency Internal Oscillator (LFIOSC) Specifications .......................................... 1072
20.9.4 Main Oscillator Specifications ..................................................................................... 1072
20.9.5 System Clock Specification with ADC Operation .......................................................... 1076
20.10 Sleep Modes ............................................................................................................. 1077
20.11 Flash Memory and EEPROM ..................................................................................... 1079
20.12 Input/Output Pin Characteristics ................................................................................. 1080
20.12.1 GPIO Module Characteristics ..................................................................................... 1080
20.12.2 Types of I/O Pins and ESD Protection ......................................................................... 1080
20.13 Analog-to-Digital Converter (ADC) .............................................................................. 1084
20.14 Synchronous Serial Interface (SSI) ............................................................................. 1087
20.15 Inter-Integrated Circuit (I2C) Interface ......................................................................... 1090
20.16 Analog Comparator ................................................................................................... 1091
20.17 Current Consumption ................................................................................................. 1093
A
Package Information .......................................................................................... 1096
A.1
A.2
A.3
A.4
Orderable Devices .....................................................................................................
Device Nomenclature ................................................................................................
Device Markings ........................................................................................................
Packaging Diagram ...................................................................................................
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1096
1097
1098
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List of Figures
Figure 1-1.
Figure 2-1.
Figure 2-2.
Figure 2-3.
Figure 2-4.
Figure 2-5.
Figure 2-6.
Figure 2-7.
Figure 3-1.
Figure 3-2.
Figure 4-1.
Figure 4-2.
Figure 4-3.
Figure 4-4.
Figure 4-5.
Figure 5-1.
Figure 5-2.
Figure 5-3.
Figure 5-4.
Figure 5-5.
Figure 5-6.
Figure 7-1.
Figure 7-2.
Figure 8-1.
Figure 8-2.
Figure 8-3.
Figure 8-4.
Figure 8-5.
Figure 8-6.
Figure 9-1.
Figure 9-2.
Figure 9-3.
Figure 9-4.
Figure 10-1.
Figure 10-2.
Figure 10-3.
Figure 10-4.
Figure 10-5.
Figure 10-6.
Figure 10-7.
Figure 10-8.
Figure 10-9.
Figure 11-1.
Figure 12-1.
Figure 12-2.
Figure 12-3.
Tiva™ TM4C1230C3PM Microcontroller High-Level Block Diagram ......................... 38
CPU Block Diagram ............................................................................................. 57
TPIU Block Diagram ............................................................................................ 58
Cortex-M4F Register Set ...................................................................................... 61
Bit-Band Mapping ................................................................................................ 85
Data Storage ....................................................................................................... 86
Vector Table ........................................................................................................ 93
Exception Stack Frame ........................................................................................ 96
SRD Use Example ............................................................................................. 114
FPU Register Bank ............................................................................................ 117
JTAG Module Block Diagram .............................................................................. 187
Test Access Port State Machine ......................................................................... 190
IDCODE Register Format ................................................................................... 196
BYPASS Register Format ................................................................................... 196
Boundary Scan Register Format ......................................................................... 197
Basic RST Configuration .................................................................................... 201
External Circuitry to Extend Power-On Reset ....................................................... 201
Reset Circuit Controlled by Switch ...................................................................... 202
Power Architecture ............................................................................................ 205
Main Clock Tree ................................................................................................ 207
Module Clock Selection ...................................................................................... 213
Internal Memory Block Diagram .......................................................................... 446
EEPROM Block Diagram ................................................................................... 447
μDMA Block Diagram ......................................................................................... 507
Example of Ping-Pong μDMA Transaction ........................................................... 513
Memory Scatter-Gather, Setup and Configuration ................................................ 515
Memory Scatter-Gather, μDMA Copy Sequence .................................................. 516
Peripheral Scatter-Gather, Setup and Configuration ............................................. 518
Peripheral Scatter-Gather, μDMA Copy Sequence ............................................... 519
Digital I/O Pads ................................................................................................. 573
Analog/Digital I/O Pads ...................................................................................... 574
GPIODATA Write Example ................................................................................. 575
GPIODATA Read Example ................................................................................. 575
GPTM Module Block Diagram ............................................................................ 626
Reading the RTC Value ...................................................................................... 633
Input Edge-Count Mode Example, Counting Down ............................................... 635
16-Bit Input Edge-Time Mode Example ............................................................... 636
16-Bit PWM Mode Example ................................................................................ 638
CCP Output, GPTMTnMATCHR > GPTMTnILR ................................................... 638
CCP Output, GPTMTnMATCHR = GPTMTnILR ................................................... 639
CCP Output, GPTMTnILR > GPTMTnMATCHR ................................................... 639
Timer Daisy Chain ............................................................................................. 640
WDT Module Block Diagram .............................................................................. 696
Implementation of Two ADC Blocks .................................................................... 721
ADC Module Block Diagram ............................................................................... 722
ADC Sample Phases ......................................................................................... 725
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Figure 12-4.
Figure 12-5.
Figure 12-6.
Figure 12-7.
Figure 12-8.
Figure 12-9.
Figure 12-10.
Figure 12-11.
Figure 12-12.
Figure 12-13.
Figure 12-14.
Figure 13-1.
Figure 13-2.
Figure 13-3.
Figure 14-1.
Figure 14-2.
Figure 14-3.
Figure 14-4.
Figure 14-5.
Figure 14-6.
Figure 14-7.
Figure 14-8.
Figure 14-9.
Figure 14-10.
Figure 14-11.
Figure 14-12.
Figure 15-1.
Figure 15-2.
Figure 15-3.
Figure 15-4.
Figure 15-5.
Figure 15-6.
Figure 15-7.
Figure 15-8.
Figure 15-9.
Figure 15-10.
Figure 15-11.
Figure 15-12.
Figure 15-13.
Figure 15-14.
Figure 15-15.
Figure 16-1.
Figure 16-2.
Figure 16-3.
Figure 16-4.
Figure 17-1.
Figure 17-2.
Figure 17-3.
Doubling the ADC Sample Rate .......................................................................... 726
Skewed Sampling .............................................................................................. 726
Sample Averaging Example ............................................................................... 728
ADC Input Equivalency ...................................................................................... 729
ADC Voltage Reference ..................................................................................... 730
ADC Conversion Result ..................................................................................... 731
Differential Voltage Representation ..................................................................... 733
Internal Temperature Sensor Characteristic ......................................................... 734
Low-Band Operation (CIC=0x0) .......................................................................... 736
Mid-Band Operation (CIC=0x1) .......................................................................... 737
High-Band Operation (CIC=0x3) ......................................................................... 738
UART Module Block Diagram ............................................................................. 812
UART Character Frame ..................................................................................... 814
IrDA Data Modulation ......................................................................................... 816
SSI Module Block Diagram ................................................................................. 871
TI Synchronous Serial Frame Format (Single Transfer) ........................................ 875
TI Synchronous Serial Frame Format (Continuous Transfer) ................................ 876
Freescale SPI Format (Single Transfer) with SPO=0 and SPH=0 .......................... 877
Freescale SPI Format (Continuous Transfer) with SPO=0 and SPH=0 .................. 877
Freescale SPI Frame Format with SPO=0 and SPH=1 ......................................... 878
Freescale SPI Frame Format (Single Transfer) with SPO=1 and SPH=0 ............... 879
Freescale SPI Frame Format (Continuous Transfer) with SPO=1 and SPH=0 ........ 879
Freescale SPI Frame Format with SPO=1 and SPH=1 ......................................... 880
MICROWIRE Frame Format (Single Frame) ........................................................ 881
MICROWIRE Frame Format (Continuous Transfer) ............................................. 882
MICROWIRE Frame Format, SSInFss Input Setup and Hold Requirements .......... 882
I2C Block Diagram ............................................................................................. 916
I2C Bus Configuration ........................................................................................ 917
START and STOP Conditions ............................................................................. 918
Complete Data Transfer with a 7-Bit Address ....................................................... 918
R/S Bit in First Byte ............................................................................................ 919
Data Validity During Bit Transfer on the I2C Bus ................................................... 919
High-Speed Data Format ................................................................................... 924
Master Single TRANSMIT .................................................................................. 926
Master Single RECEIVE ..................................................................................... 927
Master TRANSMIT of Multiple Data Bytes ........................................................... 928
Master RECEIVE of Multiple Data Bytes ............................................................. 929
Master RECEIVE with Repeated START after Master TRANSMIT ........................ 930
Master TRANSMIT with Repeated START after Master RECEIVE ........................ 931
Standard High Speed Mode Master Transmit ....................................................... 932
Slave Command Sequence ................................................................................ 933
CAN Controller Block Diagram ............................................................................ 967
CAN Data/Remote Frame .................................................................................. 968
Message Objects in a FIFO Buffer ...................................................................... 977
CAN Bit Time .................................................................................................... 981
Analog Comparator Module Block Diagram ....................................................... 1017
Structure of Comparator Unit ............................................................................ 1018
Comparator Internal Reference Structure .......................................................... 1019
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Table of Contents
Figure 18-1.
Figure 20-1.
Figure 20-2.
Figure 20-3.
Figure 20-4.
Figure 20-5.
Figure 20-6.
Figure 20-7.
Figure 20-8.
Figure 20-9.
Figure 20-10.
Figure 20-11.
Figure 20-12.
Figure 20-13.
Figure 20-14.
Figure 20-15.
Figure 20-16.
Figure 20-17.
Figure 20-18.
Figure 20-19.
Figure 20-20.
Figure 20-21.
Figure 20-22.
Figure A-1.
Figure A-2.
64-Pin LQFP Package Pin Diagram .................................................................. 1031
Load Conditions ............................................................................................... 1059
JTAG Test Clock Input Timing ........................................................................... 1060
JTAG Test Access Port (TAP) Timing ................................................................ 1061
Power Assertions versus VDDA Levels ............................................................. 1063
Power and Brown-Out Assertions versus VDD Levels ........................................ 1064
POK assertion vs VDDC ................................................................................... 1065
POR-BOR0-BOR1 VDD Glitch Response .......................................................... 1065
POR-BOR0-BOR1 VDD Droop Response ......................................................... 1066
Digital Power-On Reset Timing ......................................................................... 1067
Brown-Out Reset Timing .................................................................................. 1068
External Reset Timing (RST) ............................................................................ 1068
Software Reset Timing ..................................................................................... 1068
Watchdog Reset Timing ................................................................................... 1068
MOSC Failure Reset Timing ............................................................................. 1069
ESD Protection on Fail-Safe Pins ...................................................................... 1081
ESD Protection on Non-Fail-Safe Pins .............................................................. 1082
ADC Input Equivalency Diagram ....................................................................... 1086
SSI Timing for TI Frame Format (FRF=01), Single Transfer Timing
Measurement .................................................................................................. 1088
SSI Timing for MICROWIRE Frame Format (FRF=10), Single Transfer ............... 1088
Master Mode SSI Timing for SPI Frame Format (FRF=00), with SPH=1 .............. 1089
Slave Mode SSI Timing for SPI Frame Format (FRF=00), with SPH=1 ................ 1089
I2C Timing ....................................................................................................... 1090
Key to Part Numbers ........................................................................................ 1096
TM4C1230C3PM 64-Pin LQFP Package Diagram ............................................. 1098
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Tiva™ TM4C1230C3PM Microcontroller
List of Tables
Table 1.
Table 2.
Table 1-1.
Table 2-1.
Table 2-2.
Table 2-3.
Table 2-4.
Table 2-5.
Table 2-6.
Table 2-7.
Table 2-8.
Table 2-9.
Table 2-10.
Table 2-11.
Table 2-12.
Table 2-13.
Table 3-1.
Table 3-2.
Table 3-3.
Table 3-4.
Table 3-5.
Table 3-6.
Table 3-7.
Table 3-8.
Table 3-9.
Table 3-10.
Table 4-1.
Table 4-2.
Table 4-3.
Table 5-1.
Table 5-2.
Table 5-3.
Table 5-4.
Table 5-5.
Table 5-6.
Table 5-7.
Table 5-8.
Table 6-1.
Table 7-1.
Table 7-2.
Table 7-3.
Table 8-1.
Table 8-2.
Table 8-3.
Table 8-4.
Table 8-5.
Revision History .................................................................................................. 30
Documentation Conventions ................................................................................ 34
TM4C1230C3PM Microcontroller Features ............................................................ 37
Summary of Processor Mode, Privilege Level, and Stack Use ................................ 60
Processor Register Map ....................................................................................... 61
PSR Register Combinations ................................................................................. 67
Memory Map ....................................................................................................... 78
Memory Access Behavior ..................................................................................... 81
SRAM Memory Bit-Banding Regions .................................................................... 83
Peripheral Memory Bit-Banding Regions ............................................................... 83
Exception Types .................................................................................................. 89
Interrupts ............................................................................................................ 90
Exception Return Behavior ................................................................................... 97
Faults ................................................................................................................. 98
Fault Status and Fault Address Registers .............................................................. 99
Cortex-M4F Instruction Summary ....................................................................... 101
Core Peripheral Register Regions ....................................................................... 108
Memory Attributes Summary .............................................................................. 112
TEX, S, C, and B Bit Field Encoding ................................................................... 114
Cache Policy for Memory Attribute Encoding ....................................................... 115
AP Bit Field Encoding ........................................................................................ 115
Memory Region Attributes for Tiva™ C Series Microcontrollers ............................. 116
QNaN and SNaN Handling ................................................................................. 119
Peripherals Register Map ................................................................................... 120
Interrupt Priority Levels ...................................................................................... 150
Example SIZE Field Values ................................................................................ 178
JTAG_SWD_SWO Signals (64LQFP) ................................................................. 187
JTAG Port Pins State after Power-On Reset or RST assertion .............................. 188
JTAG Instruction Register Commands ................................................................. 194
System Control & Clocks Signals (64LQFP) ........................................................ 198
Reset Sources ................................................................................................... 199
Clock Source Options ........................................................................................ 206
Possible System Clock Frequencies Using the SYSDIV Field ............................... 208
Examples of Possible System Clock Frequencies Using the SYSDIV2 Field .......... 208
Examples of Possible System Clock Frequencies with DIV400=1 ......................... 209
System Control Register Map ............................................................................. 216
RCC2 Fields that Override RCC Fields ............................................................... 242
System Exception Register Map ......................................................................... 438
Flash Memory Protection Policy Combinations .................................................... 451
User-Programmable Flash Memory Resident Registers ....................................... 455
Flash Register Map ............................................................................................ 462
μDMA Channel Assignments .............................................................................. 508
Request Type Support ....................................................................................... 510
Control Structure Memory Map ........................................................................... 511
Channel Control Structure .................................................................................. 511
μDMA Read Example: 8-Bit Peripheral ................................................................ 520
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Table of Contents
Table 8-6.
Table 8-7.
Table 8-8.
Table 8-9.
Table 8-10.
Table 8-11.
Table 8-12.
μDMA Interrupt Assignments .............................................................................. 521
Channel Control Structure Offsets for Channel 30 ................................................ 522
Channel Control Word Configuration for Memory Transfer Example ...................... 523
Channel Control Structure Offsets for Channel 7 .................................................. 524
Channel Control Word Configuration for Peripheral Transmit Example .................. 524
Primary and Alternate Channel Control Structure Offsets for Channel 8 ................. 525
Channel Control Word Configuration for Peripheral Ping-Pong Receive
Example ............................................................................................................ 526
Table 8-13.
μDMA Register Map .......................................................................................... 528
Table 9-1.
GPIO Pins With Special Considerations .............................................................. 571
Table 9-2.
GPIO Pins and Alternate Functions (64LQFP) ..................................................... 571
Table 9-3.
GPIO Pad Configuration Examples ..................................................................... 578
Table 9-4.
GPIO Interrupt Configuration Example ................................................................ 579
Table 9-5.
GPIO Pins With Special Considerations .............................................................. 580
Table 9-6.
GPIO Register Map ........................................................................................... 581
Table 9-7.
GPIO Pins With Special Considerations .............................................................. 592
Table 9-8.
GPIO Pins With Special Considerations .............................................................. 598
Table 9-9.
GPIO Pins With Special Considerations .............................................................. 600
Table 9-10.
GPIO Pins With Special Considerations .............................................................. 603
Table 9-11.
GPIO Pins With Special Considerations .............................................................. 609
Table 10-1.
Available CCP Pins ............................................................................................ 627
Table 10-2.
General-Purpose Timers Signals (64LQFP) ......................................................... 627
Table 10-3.
General-Purpose Timer Capabilities .................................................................... 629
Table 10-4.
Counter Values When the Timer is Enabled in Periodic or One-Shot Modes .......... 630
Table 10-5.
16-Bit Timer With Prescaler Configurations ......................................................... 631
Table 10-6.
32-Bit Timer (configured in 32/64-bit mode) With Prescaler Configurations ............ 632
Table 10-7.
Counter Values When the Timer is Enabled in RTC Mode .................................... 632
Table 10-8.
Counter Values When the Timer is Enabled in Input Edge-Count Mode ................. 634
Table 10-9.
Counter Values When the Timer is Enabled in Input Event-Count Mode ................ 635
Table 10-10. Counter Values When the Timer is Enabled in PWM Mode ................................... 637
Table 10-11. Timeout Actions for GPTM Modes ...................................................................... 640
Table 10-12. Timers Register Map .......................................................................................... 647
Table 11-1.
Watchdog Timers Register Map .......................................................................... 698
Table 12-1.
ADC Signals (64LQFP) ...................................................................................... 722
Table 12-2.
Samples and FIFO Depth of Sequencers ............................................................ 723
Table 12-3.
Differential Sampling Pairs ................................................................................. 731
Table 12-4.
ADC Register Map ............................................................................................. 739
Table 13-1.
UART Signals (64LQFP) .................................................................................... 813
Table 13-2.
Flow Control Mode ............................................................................................. 817
Table 13-3.
UART Register Map ........................................................................................... 822
Table 14-1.
SSI Signals (64LQFP) ........................................................................................ 872
Table 14-2.
SSI Register Map .............................................................................................. 885
Table 15-1.
I2C Signals (64LQFP) ........................................................................................ 916
Table 15-2.
Examples of I2C Master Timer Period Versus Speed Mode ................................... 922
Table 15-3.
Examples of I2C Master Timer Period in High-Speed Mode .................................. 923
Table 15-4.
Inter-Integrated Circuit (I2C) Interface Register Map ............................................. 935
Table 15-5.
Write Field Decoding for I2CMCS[3:0] Field ......................................................... 941
Table 16-1.
Controller Area Network Signals (64LQFP) .......................................................... 968
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Tiva™ TM4C1230C3PM Microcontroller
Table 16-2.
Table 16-3.
Table 16-4.
Table 16-5.
Table 17-1.
Table 17-2.
Table 17-3.
Table 17-4.
Table 17-5.
Table 19-1.
Table 19-2.
Table 19-3.
Table 19-4.
Table 19-5.
Table 19-6.
Table 19-7.
Table 20-1.
Table 20-2.
Table 20-3.
Table 20-4.
Table 20-5.
Table 20-6.
Table 20-7.
Table 20-8.
Table 20-9.
Table 20-10.
Table 20-11.
Table 20-12.
Table 20-13.
Table 20-14.
Table 20-15.
Table 20-16.
Table 20-17.
Table 20-18.
Table 20-19.
Table 20-20.
Table 20-21.
Table 20-22.
Table 20-23.
Table 20-24.
Table 20-25.
Table 20-26.
Table 20-27.
Table 20-28.
Table 20-29.
Table 20-30.
Message Object Configurations .......................................................................... 973
CAN Protocol Ranges ........................................................................................ 981
CANBIT Register Values .................................................................................... 981
CAN Register Map ............................................................................................. 985
Analog Comparators Signals (64LQFP) ............................................................. 1017
Internal Reference Voltage and ACREFCTL Field Values ................................... 1019
Analog Comparator Voltage Reference Characteristics, VDDA = 3.3V, EN= 1, and
RNG = 0 .......................................................................................................... 1020
Analog Comparator Voltage Reference Characteristics, VDDA = 3.3V, EN= 1, and
RNG = 1 .......................................................................................................... 1020
Analog Comparators Register Map ................................................................... 1021
GPIO Pins With Special Considerations ............................................................ 1032
Signals by Pin Number ..................................................................................... 1033
Signals by Signal Name ................................................................................... 1038
Signals by Function, Except for GPIO ............................................................... 1044
GPIO Pins and Alternate Functions ................................................................... 1048
Possible Pin Assignments for Alternate Functions .............................................. 1051
Connections for Unused Signals (64-Pin LQFP) ................................................. 1053
Absolute Maximum Ratings .............................................................................. 1055
ESD Absolute Maximum Ratings ...................................................................... 1055
Temperature Characteristics ............................................................................. 1056
Thermal Characteristics ................................................................................... 1056
Recommended DC Operating Conditions .......................................................... 1057
Recommended GPIO Pad Operating Conditions ................................................ 1057
GPIO Current Restrictions ................................................................................ 1057
GPIO Package Side Assignments ..................................................................... 1058
JTAG Characteristics ....................................................................................... 1060
Power-On and Brown-Out Levels ...................................................................... 1062
Reset Characteristics ....................................................................................... 1067
LDO Regulator Characteristics ......................................................................... 1070
Phase Locked Loop (PLL) Characteristics ......................................................... 1071
Actual PLL Frequency ...................................................................................... 1071
PIOSC Clock Characteristics ............................................................................ 1072
Low-Frequency internal Oscillator Characteristics .............................................. 1072
Main Oscillator Input Characteristics ................................................................. 1072
Crystal Parameters .......................................................................................... 1074
Supported MOSC Crystal Frequencies .............................................................. 1075
System Clock Characteristics with ADC Operation ............................................. 1076
Sleep Modes AC Characteristics ....................................................................... 1077
Time to Wake with Respect to Low-Power Modes .............................................. 1077
Flash Memory Characteristics ........................................................................... 1079
EEPROM Characteristics ................................................................................. 1079
GPIO Module Characteristics ............................................................................ 1080
Pad Voltage/Current Characteristics for Fail-Safe Pins ....................................... 1081
Fail-Safe GPIOs that Require an External Pull-up .............................................. 1082
Non-Fail-Safe I/O Pad Voltage/Current Characteristics ....................................... 1082
ADC Electrical Characteristics .......................................................................... 1084
SSI Characteristics .......................................................................................... 1087
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I2C Characteristics ...........................................................................................
Analog Comparator Characteristics ...................................................................
Analog Comparator Voltage Reference Characteristics ......................................
Analog Comparator Voltage Reference Characteristics, VDDA = 3.3V, EN= 1, and
RNG = 0 ..........................................................................................................
Table 20-35. Analog Comparator Voltage Reference Characteristics, VDDA = 3.3V, EN= 1, and
RNG = 1 ..........................................................................................................
Table 20-36. Current Consumption .......................................................................................
Table 20-31.
Table 20-32.
Table 20-33.
Table 20-34.
16
1090
1091
1091
1091
1092
1093
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Tiva™ TM4C1230C3PM Microcontroller
List of Registers
The Cortex-M4F Processor ........................................................................................................... 55
Register 1:
Register 2:
Register 3:
Register 4:
Register 5:
Register 6:
Register 7:
Register 8:
Register 9:
Register 10:
Register 11:
Register 12:
Register 13:
Register 14:
Register 15:
Register 16:
Register 17:
Register 18:
Register 19:
Register 20:
Register 21:
Register 22:
Cortex General-Purpose Register 0 (R0) ........................................................................... 63
Cortex General-Purpose Register 1 (R1) ........................................................................... 63
Cortex General-Purpose Register 2 (R2) ........................................................................... 63
Cortex General-Purpose Register 3 (R3) ........................................................................... 63
Cortex General-Purpose Register 4 (R4) ........................................................................... 63
Cortex General-Purpose Register 5 (R5) ........................................................................... 63
Cortex General-Purpose Register 6 (R6) ........................................................................... 63
Cortex General-Purpose Register 7 (R7) ........................................................................... 63
Cortex General-Purpose Register 8 (R8) ........................................................................... 63
Cortex General-Purpose Register 9 (R9) ........................................................................... 63
Cortex General-Purpose Register 10 (R10) ....................................................................... 63
Cortex General-Purpose Register 11 (R11) ........................................................................ 63
Cortex General-Purpose Register 12 (R12) ....................................................................... 63
Stack Pointer (SP) ........................................................................................................... 64
Link Register (LR) ............................................................................................................ 65
Program Counter (PC) ..................................................................................................... 66
Program Status Register (PSR) ........................................................................................ 67
Priority Mask Register (PRIMASK) .................................................................................... 71
Fault Mask Register (FAULTMASK) .................................................................................. 72
Base Priority Mask Register (BASEPRI) ............................................................................ 73
Control Register (CONTROL) ........................................................................................... 74
Floating-Point Status Control (FPSC) ................................................................................ 76
Cortex-M4 Peripherals ................................................................................................................. 108
Register 1:
Register 2:
Register 3:
Register 4:
Register 5:
Register 6:
Register 7:
Register 8:
Register 9:
Register 10:
Register 11:
Register 12:
Register 13:
Register 14:
Register 15:
Register 16:
Register 17:
Register 18:
Register 19:
Register 20:
Register 21:
SysTick Control and Status Register (STCTRL), offset 0x010 ........................................... 124
SysTick Reload Value Register (STRELOAD), offset 0x014 .............................................. 126
SysTick Current Value Register (STCURRENT), offset 0x018 ........................................... 127
Interrupt 0-31 Set Enable (EN0), offset 0x100 .................................................................. 128
Interrupt 32-63 Set Enable (EN1), offset 0x104 ................................................................ 128
Interrupt 64-95 Set Enable (EN2), offset 0x108 ................................................................ 128
Interrupt 96-127 Set Enable (EN3), offset 0x10C ............................................................. 128
Interrupt 128-138 Set Enable (EN4), offset 0x110 ............................................................ 129
Interrupt 0-31 Clear Enable (DIS0), offset 0x180 .............................................................. 130
Interrupt 32-63 Clear Enable (DIS1), offset 0x184 ............................................................ 130
Interrupt 64-95 Clear Enable (DIS2), offset 0x188 ............................................................ 130
Interrupt 96-127 Clear Enable (DIS3), offset 0x18C .......................................................... 130
Interrupt 128-138 Clear Enable (DIS4), offset 0x190 ........................................................ 131
Interrupt 0-31 Set Pending (PEND0), offset 0x200 ........................................................... 132
Interrupt 32-63 Set Pending (PEND1), offset 0x204 ......................................................... 132
Interrupt 64-95 Set Pending (PEND2), offset 0x208 ......................................................... 132
Interrupt 96-127 Set Pending (PEND3), offset 0x20C ....................................................... 132
Interrupt 128-138 Set Pending (PEND4), offset 0x210 ...................................................... 133
Interrupt 0-31 Clear Pending (UNPEND0), offset 0x280 ................................................... 134
Interrupt 32-63 Clear Pending (UNPEND1), offset 0x284 .................................................. 134
Interrupt 64-95 Clear Pending (UNPEND2), offset 0x288 .................................................. 134
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Table of Contents
Register 22:
Register 23:
Register 24:
Register 25:
Register 26:
Register 27:
Register 28:
Register 29:
Register 30:
Register 31:
Register 32:
Register 33:
Register 34:
Register 35:
Register 36:
Register 37:
Register 38:
Register 39:
Register 40:
Register 41:
Register 42:
Register 43:
Register 44:
Register 45:
Register 46:
Register 47:
Register 48:
Register 49:
Register 50:
Register 51:
Register 52:
Register 53:
Register 54:
Register 55:
Register 56:
Register 57:
Register 58:
Register 59:
Register 60:
Register 61:
Register 62:
Register 63:
Register 64:
Register 65:
Register 66:
Register 67:
Register 68:
Register 69:
Interrupt 96-127 Clear Pending (UNPEND3), offset 0x28C ............................................... 134
Interrupt 128-138 Clear Pending (UNPEND4), offset 0x290 .............................................. 135
Interrupt 0-31 Active Bit (ACTIVE0), offset 0x300 ............................................................. 136
Interrupt 32-63 Active Bit (ACTIVE1), offset 0x304 ........................................................... 136
Interrupt 64-95 Active Bit (ACTIVE2), offset 0x308 ........................................................... 136
Interrupt 96-127 Active Bit (ACTIVE3), offset 0x30C ........................................................ 136
Interrupt 128-138 Active Bit (ACTIVE4), offset 0x310 ....................................................... 137
Interrupt 0-3 Priority (PRI0), offset 0x400 ......................................................................... 138
Interrupt 4-7 Priority (PRI1), offset 0x404 ......................................................................... 138
Interrupt 8-11 Priority (PRI2), offset 0x408 ....................................................................... 138
Interrupt 12-15 Priority (PRI3), offset 0x40C .................................................................... 138
Interrupt 16-19 Priority (PRI4), offset 0x410 ..................................................................... 138
Interrupt 20-23 Priority (PRI5), offset 0x414 ..................................................................... 138
Interrupt 24-27 Priority (PRI6), offset 0x418 ..................................................................... 138
Interrupt 28-31 Priority (PRI7), offset 0x41C .................................................................... 138
Interrupt 32-35 Priority (PRI8), offset 0x420 ..................................................................... 138
Interrupt 36-39 Priority (PRI9), offset 0x424 ..................................................................... 138
Interrupt 40-43 Priority (PRI10), offset 0x428 ................................................................... 138
Interrupt 44-47 Priority (PRI11), offset 0x42C ................................................................... 138
Interrupt 48-51 Priority (PRI12), offset 0x430 ................................................................... 138
Interrupt 52-55 Priority (PRI13), offset 0x434 ................................................................... 138
Interrupt 56-59 Priority (PRI14), offset 0x438 ................................................................... 138
Interrupt 60-63 Priority (PRI15), offset 0x43C .................................................................. 138
Interrupt 64-67 Priority (PRI16), offset 0x440 ................................................................... 140
Interrupt 68-71 Priority (PRI17), offset 0x444 ................................................................... 140
Interrupt 72-75 Priority (PRI18), offset 0x448 ................................................................... 140
Interrupt 76-79 Priority (PRI19), offset 0x44C .................................................................. 140
Interrupt 80-83 Priority (PRI20), offset 0x450 ................................................................... 140
Interrupt 84-87 Priority (PRI21), offset 0x454 ................................................................... 140
Interrupt 88-91 Priority (PRI22), offset 0x458 ................................................................... 140
Interrupt 92-95 Priority (PRI23), offset 0x45C .................................................................. 140
Interrupt 96-99 Priority (PRI24), offset 0x460 ................................................................... 140
Interrupt 100-103 Priority (PRI25), offset 0x464 ............................................................... 140
Interrupt 104-107 Priority (PRI26), offset 0x468 ............................................................... 140
Interrupt 108-111 Priority (PRI27), offset 0x46C ............................................................... 140
Interrupt 112-115 Priority (PRI28), offset 0x470 ................................................................ 140
Interrupt 116-119 Priority (PRI29), offset 0x474 ................................................................ 140
Interrupt 120-123 Priority (PRI30), offset 0x478 ............................................................... 140
Interrupt 124-127 Priority (PRI31), offset 0x47C ............................................................... 140
Interrupt 128-131 Priority (PRI32), offset 0x480 ............................................................... 140
Interrupt 132-135 Priority (PRI33), offset 0x484 ............................................................... 140
Interrupt 136-138 Priority (PRI34), offset 0x488 ............................................................... 140
Software Trigger Interrupt (SWTRIG), offset 0xF00 .......................................................... 142
Auxiliary Control (ACTLR), offset 0x008 .......................................................................... 143
CPU ID Base (CPUID), offset 0xD00 ............................................................................... 145
Interrupt Control and State (INTCTRL), offset 0xD04 ........................................................ 146
Vector Table Offset (VTABLE), offset 0xD08 .................................................................... 149
Application Interrupt and Reset Control (APINT), offset 0xD0C ......................................... 150
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Tiva™ TM4C1230C3PM Microcontroller
Register 70:
Register 71:
Register 72:
Register 73:
Register 74:
Register 75:
Register 76:
Register 77:
Register 78:
Register 79:
Register 80:
Register 81:
Register 82:
Register 83:
Register 84:
Register 85:
Register 86:
Register 87:
Register 88:
Register 89:
Register 90:
Register 91:
Register 92:
Register 93:
Register 94:
System Control (SYSCTRL), offset 0xD10 ....................................................................... 152
Configuration and Control (CFGCTRL), offset 0xD14 ....................................................... 154
System Handler Priority 1 (SYSPRI1), offset 0xD18 ......................................................... 156
System Handler Priority 2 (SYSPRI2), offset 0xD1C ........................................................ 157
System Handler Priority 3 (SYSPRI3), offset 0xD20 ......................................................... 158
System Handler Control and State (SYSHNDCTRL), offset 0xD24 .................................... 159
Configurable Fault Status (FAULTSTAT), offset 0xD28 ..................................................... 163
Hard Fault Status (HFAULTSTAT), offset 0xD2C .............................................................. 169
Memory Management Fault Address (MMADDR), offset 0xD34 ........................................ 170
Bus Fault Address (FAULTADDR), offset 0xD38 .............................................................. 171
MPU Type (MPUTYPE), offset 0xD90 ............................................................................. 172
MPU Control (MPUCTRL), offset 0xD94 .......................................................................... 173
MPU Region Number (MPUNUMBER), offset 0xD98 ....................................................... 175
MPU Region Base Address (MPUBASE), offset 0xD9C ................................................... 176
MPU Region Base Address Alias 1 (MPUBASE1), offset 0xDA4 ....................................... 176
MPU Region Base Address Alias 2 (MPUBASE2), offset 0xDAC ...................................... 176
MPU Region Base Address Alias 3 (MPUBASE3), offset 0xDB4 ....................................... 176
MPU Region Attribute and Size (MPUATTR), offset 0xDA0 ............................................... 178
MPU Region Attribute and Size Alias 1 (MPUATTR1), offset 0xDA8 .................................. 178
MPU Region Attribute and Size Alias 2 (MPUATTR2), offset 0xDB0 .................................. 178
MPU Region Attribute and Size Alias 3 (MPUATTR3), offset 0xDB8 .................................. 178
Coprocessor Access Control (CPAC), offset 0xD88 .......................................................... 181
Floating-Point Context Control (FPCC), offset 0xF34 ........................................................ 182
Floating-Point Context Address (FPCA), offset 0xF38 ...................................................... 184
Floating-Point Default Status Control (FPDSC), offset 0xF3C ........................................... 185
System Control ............................................................................................................................ 198
Register 1:
Register 2:
Register 3:
Register 4:
Register 5:
Register 6:
Register 7:
Register 8:
Register 9:
Register 10:
Register 11:
Register 12:
Register 13:
Register 14:
Register 15:
Register 16:
Register 17:
Register 18:
Register 19:
Register 20:
Register 21:
Register 22:
Device Identification 0 (DID0), offset 0x000 ..................................................................... 221
Device Identification 1 (DID1), offset 0x004 ..................................................................... 223
Brown-Out Reset Control (PBORCTL), offset 0x030 ........................................................ 226
Raw Interrupt Status (RIS), offset 0x050 .......................................................................... 227
Interrupt Mask Control (IMC), offset 0x054 ...................................................................... 229
Masked Interrupt Status and Clear (MISC), offset 0x058 .................................................. 231
Reset Cause (RESC), offset 0x05C ................................................................................ 234
Run-Mode Clock Configuration (RCC), offset 0x060 ......................................................... 236
GPIO High-Performance Bus Control (GPIOHBCTL), offset 0x06C ................................... 240
Run-Mode Clock Configuration 2 (RCC2), offset 0x070 .................................................... 242
Main Oscillator Control (MOSCCTL), offset 0x07C ........................................................... 245
Deep Sleep Clock Configuration (DSLPCLKCFG), offset 0x144 ........................................ 246
System Properties (SYSPROP), offset 0x14C .................................................................. 248
Precision Internal Oscillator Calibration (PIOSCCAL), offset 0x150 ................................... 250
PLL Frequency 0 (PLLFREQ0), offset 0x160 ................................................................... 251
PLL Frequency 1 (PLLFREQ1), offset 0x164 ................................................................... 252
PLL Status (PLLSTAT), offset 0x168 ............................................................................... 253
Sleep Power Configuration (SLPPWRCFG), offset 0x188 ................................................. 254
Deep-Sleep Power Configuration (DSLPPWRCFG), offset 0x18C ..................................... 256
LDO Sleep Power Control (LDOSPCTL), offset 0x1B4 ..................................................... 258
LDO Sleep Power Calibration (LDOSPCAL), offset 0x1B8 ................................................ 260
LDO Deep-Sleep Power Control (LDODPCTL), offset 0x1BC ........................................... 261
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Table of Contents
Register 23:
Register 24:
Register 25:
Register 26:
Register 27:
Register 28:
Register 29:
Register 30:
Register 31:
Register 32:
Register 33:
Register 34:
Register 35:
Register 36:
Register 37:
Register 38:
Register 39:
Register 40:
Register 41:
Register 42:
Register 43:
Register 44:
Register 45:
Register 46:
Register 47:
Register 48:
Register 49:
Register 50:
Register 51:
Register 52:
Register 53:
Register 54:
Register 55:
Register 56:
Register 57:
Register 58:
Register 59:
Register 60:
Register 61:
Register 62:
Register 63:
Register 64:
LDO Deep-Sleep Power Calibration (LDODPCAL), offset 0x1C0 ...................................... 263
Sleep / Deep-Sleep Power Mode Status (SDPMST), offset 0x1CC .................................... 264
Watchdog Timer Peripheral Present (PPWD), offset 0x300 ............................................... 267
16/32-Bit General-Purpose Timer Peripheral Present (PPTIMER), offset 0x304 ................. 268
General-Purpose Input/Output Peripheral Present (PPGPIO), offset 0x308 ........................ 270
Micro Direct Memory Access Peripheral Present (PPDMA), offset 0x30C .......................... 273
Hibernation Peripheral Present (PPHIB), offset 0x314 ...................................................... 274
Universal Asynchronous Receiver/Transmitter Peripheral Present (PPUART), offset
0x318 ........................................................................................................................... 275
Synchronous Serial Interface Peripheral Present (PPSSI), offset 0x31C ............................ 277
Inter-Integrated Circuit Peripheral Present (PPI2C), offset 0x320 ...................................... 279
Universal Serial Bus Peripheral Present (PPUSB), offset 0x328 ........................................ 281
Controller Area Network Peripheral Present (PPCAN), offset 0x334 .................................. 282
Analog-to-Digital Converter Peripheral Present (PPADC), offset 0x338 ............................. 283
Analog Comparator Peripheral Present (PPACMP), offset 0x33C ...................................... 284
Pulse Width Modulator Peripheral Present (PPPWM), offset 0x340 ................................... 285
Quadrature Encoder Interface Peripheral Present (PPQEI), offset 0x344 ........................... 286
EEPROM Peripheral Present (PPEEPROM), offset 0x358 ................................................ 287
32/64-Bit Wide General-Purpose Timer Peripheral Present (PPWTIMER), offset 0x35C ..... 288
Watchdog Timer Software Reset (SRWD), offset 0x500 ................................................... 290
16/32-Bit General-Purpose Timer Software Reset (SRTIMER), offset 0x504 ...................... 292
General-Purpose Input/Output Software Reset (SRGPIO), offset 0x508 ............................ 294
Micro Direct Memory Access Software Reset (SRDMA), offset 0x50C ............................... 296
Universal Asynchronous Receiver/Transmitter Software Reset (SRUART), offset 0x518 .... 297
Synchronous Serial Interface Software Reset (SRSSI), offset 0x51C ................................ 299
Inter-Integrated Circuit Software Reset (SRI2C), offset 0x520 ........................................... 301
Controller Area Network Software Reset (SRCAN), offset 0x534 ....................................... 303
Analog-to-Digital Converter Software Reset (SRADC), offset 0x538 .................................. 304
Analog Comparator Software Reset (SRACMP), offset 0x53C .......................................... 306
EEPROM Software Reset (SREEPROM), offset 0x558 .................................................... 307
32/64-Bit Wide General-Purpose Timer Software Reset (SRWTIMER), offset 0x55C .......... 308
Watchdog Timer Run Mode Clock Gating Control (RCGCWD), offset 0x600 ...................... 310
16/32-Bit General-Purpose Timer Run Mode Clock Gating Control (RCGCTIMER), offset
0x604 ........................................................................................................................... 311
General-Purpose Input/Output Run Mode Clock Gating Control (RCGCGPIO), offset
0x608 ........................................................................................................................... 313
Micro Direct Memory Access Run Mode Clock Gating Control (RCGCDMA), offset
0x60C ........................................................................................................................... 315
Universal Asynchronous Receiver/Transmitter Run Mode Clock Gating Control (RCGCUART),
offset 0x618 .................................................................................................................. 316
Synchronous Serial Interface Run Mode Clock Gating Control (RCGCSSI), offset
0x61C ........................................................................................................................... 318
Inter-Integrated Circuit Run Mode Clock Gating Control (RCGCI2C), offset 0x620 ............. 320
Controller Area Network Run Mode Clock Gating Control (RCGCCAN), offset 0x634 ......... 322
Analog-to-Digital Converter Run Mode Clock Gating Control (RCGCADC), offset 0x638 .... 323
Analog Comparator Run Mode Clock Gating Control (RCGCACMP), offset 0x63C ............. 324
EEPROM Run Mode Clock Gating Control (RCGCEEPROM), offset 0x658 ....................... 325
32/64-Bit Wide General-Purpose Timer Run Mode Clock Gating Control (RCGCWTIMER),
offset 0x65C .................................................................................................................. 326
20
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Tiva™ TM4C1230C3PM Microcontroller
Register 65:
Register 66:
Register 67:
Register 68:
Register 69:
Register 70:
Register 71:
Register 72:
Register 73:
Register 74:
Register 75:
Register 76:
Register 77:
Register 78:
Register 79:
Register 80:
Register 81:
Register 82:
Register 83:
Register 84:
Register 85:
Register 86:
Register 87:
Register 88:
Register 89:
Register 90:
Register 91:
Register 92:
Register 93:
Register 94:
Register 95:
Register 96:
Watchdog Timer Sleep Mode Clock Gating Control (SCGCWD), offset 0x700 .................... 328
16/32-Bit General-Purpose Timer Sleep Mode Clock Gating Control (SCGCTIMER), offset
0x704 ........................................................................................................................... 329
General-Purpose Input/Output Sleep Mode Clock Gating Control (SCGCGPIO), offset
0x708 ........................................................................................................................... 331
Micro Direct Memory Access Sleep Mode Clock Gating Control (SCGCDMA), offset
0x70C ........................................................................................................................... 333
Universal Asynchronous Receiver/Transmitter Sleep Mode Clock Gating Control
(SCGCUART), offset 0x718 ............................................................................................ 334
Synchronous Serial Interface Sleep Mode Clock Gating Control (SCGCSSI), offset
0x71C ........................................................................................................................... 336
Inter-Integrated Circuit Sleep Mode Clock Gating Control (SCGCI2C), offset 0x720 ........... 338
Controller Area Network Sleep Mode Clock Gating Control (SCGCCAN), offset 0x734 ....... 340
Analog-to-Digital Converter Sleep Mode Clock Gating Control (SCGCADC), offset
0x738 ........................................................................................................................... 341
Analog Comparator Sleep Mode Clock Gating Control (SCGCACMP), offset 0x73C .......... 342
EEPROM Sleep Mode Clock Gating Control (SCGCEEPROM), offset 0x758 ..................... 343
32/64-Bit Wide General-Purpose Timer Sleep Mode Clock Gating Control (SCGCWTIMER),
offset 0x75C .................................................................................................................. 344
Watchdog Timer Deep-Sleep Mode Clock Gating Control (DCGCWD), offset 0x800 .......... 346
16/32-Bit General-Purpose Timer Deep-Sleep Mode Clock Gating Control (DCGCTIMER),
offset 0x804 .................................................................................................................. 347
General-Purpose Input/Output Deep-Sleep Mode Clock Gating Control (DCGCGPIO), offset
0x808 ........................................................................................................................... 349
Micro Direct Memory Access Deep-Sleep Mode Clock Gating Control (DCGCDMA), offset
0x80C ........................................................................................................................... 351
Universal Asynchronous Receiver/Transmitter Deep-Sleep Mode Clock Gating Control
(DCGCUART), offset 0x818 ............................................................................................ 352
Synchronous Serial Interface Deep-Sleep Mode Clock Gating Control (DCGCSSI), offset
0x81C ........................................................................................................................... 354
Inter-Integrated Circuit Deep-Sleep Mode Clock Gating Control (DCGCI2C), offset
0x820 ........................................................................................................................... 356
Controller Area Network Deep-Sleep Mode Clock Gating Control (DCGCCAN), offset
0x834 ........................................................................................................................... 358
Analog-to-Digital Converter Deep-Sleep Mode Clock Gating Control (DCGCADC), offset
0x838 ........................................................................................................................... 359
Analog Comparator Deep-Sleep Mode Clock Gating Control (DCGCACMP), offset
0x83C ........................................................................................................................... 360
EEPROM Deep-Sleep Mode Clock Gating Control (DCGCEEPROM), offset 0x858 ........... 361
32/64-Bit Wide General-Purpose Timer Deep-Sleep Mode Clock Gating Control
(DCGCWTIMER), offset 0x85C ...................................................................................... 362
Watchdog Timer Peripheral Ready (PRWD), offset 0xA00 ................................................ 364
16/32-Bit General-Purpose Timer Peripheral Ready (PRTIMER), offset 0xA04 ................... 365
General-Purpose Input/Output Peripheral Ready (PRGPIO), offset 0xA08 ......................... 367
Micro Direct Memory Access Peripheral Ready (PRDMA), offset 0xA0C ........................... 369
Universal Asynchronous Receiver/Transmitter Peripheral Ready (PRUART), offset
0xA18 ........................................................................................................................... 370
Synchronous Serial Interface Peripheral Ready (PRSSI), offset 0xA1C ............................. 372
Inter-Integrated Circuit Peripheral Ready (PRI2C), offset 0xA20 ....................................... 374
Controller Area Network Peripheral Ready (PRCAN), offset 0xA34 ................................... 376
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Register 97:
Register 98:
Register 99:
Register 100:
Register 101:
Register 102:
Register 103:
Register 104:
Register 105:
Register 106:
Register 107:
Register 108:
Register 109:
Register 110:
Register 111:
Register 112:
Register 113:
Register 114:
Register 115:
Register 116:
Register 117:
Register 118:
Register 119:
Register 120:
Register 121:
Register 122:
Register 123:
Analog-to-Digital Converter Peripheral Ready (PRADC), offset 0xA38 ............................... 377
Analog Comparator Peripheral Ready (PRACMP), offset 0xA3C ....................................... 378
EEPROM Peripheral Ready (PREEPROM), offset 0xA58 ................................................. 379
32/64-Bit Wide General-Purpose Timer Peripheral Ready (PRWTIMER), offset 0xA5C ...... 380
Device Capabilities 0 (DC0), offset 0x008 ........................................................................ 382
Device Capabilities 1 (DC1), offset 0x010 ........................................................................ 384
Device Capabilities 2 (DC2), offset 0x014 ........................................................................ 387
Device Capabilities 3 (DC3), offset 0x018 ........................................................................ 390
Device Capabilities 4 (DC4), offset 0x01C ....................................................................... 394
Device Capabilities 5 (DC5), offset 0x020 ........................................................................ 397
Device Capabilities 6 (DC6), offset 0x024 ........................................................................ 399
Device Capabilities 7 (DC7), offset 0x028 ........................................................................ 400
Device Capabilities 8 (DC8), offset 0x02C ....................................................................... 403
Software Reset Control 0 (SRCR0), offset 0x040 ............................................................. 406
Software Reset Control 1 (SRCR1), offset 0x044 ............................................................. 408
Software Reset Control 2 (SRCR2), offset 0x048 ............................................................. 411
Run Mode Clock Gating Control Register 0 (RCGC0), offset 0x100 ................................... 413
Run Mode Clock Gating Control Register 1 (RCGC1), offset 0x104 ................................... 416
Run Mode Clock Gating Control Register 2 (RCGC2), offset 0x108 ................................... 419
Sleep Mode Clock Gating Control Register 0 (SCGC0), offset 0x110 ................................. 421
Sleep Mode Clock Gating Control Register 1 (SCGC1), offset 0x114 ................................. 423
Sleep Mode Clock Gating Control Register 2 (SCGC2), offset 0x118 ................................. 426
Deep Sleep Mode Clock Gating Control Register 0 (DCGC0), offset 0x120 ....................... 428
Deep-Sleep Mode Clock Gating Control Register 1 (DCGC1), offset 0x124 ....................... 430
Deep Sleep Mode Clock Gating Control Register 2 (DCGC2), offset 0x128 ....................... 433
Device Capabilities 9 (DC9), offset 0x190 ........................................................................ 435
Non-Volatile Memory Information (NVMSTAT), offset 0x1A0 ............................................. 437
System Exception Module .......................................................................................................... 438
Register 1:
Register 2:
Register 3:
Register 4:
System Exception Raw Interrupt Status (SYSEXCRIS), offset 0x000 ................................
System Exception Interrupt Mask (SYSEXCIM), offset 0x004 ...........................................
System Exception Masked Interrupt Status (SYSEXCMIS), offset 0x008 ...........................
System Exception Interrupt Clear (SYSEXCIC), offset 0x00C ...........................................
439
441
443
445
Internal Memory ........................................................................................................................... 446
Register 1:
Register 2:
Register 3:
Register 4:
Register 5:
Register 6:
Register 7:
Register 8:
Register 9:
Register 10:
Register 11:
Register 12:
Register 13:
Register 14:
Register 15:
Flash Memory Address (FMA), offset 0x000 .................................................................... 464
Flash Memory Data (FMD), offset 0x004 ......................................................................... 465
Flash Memory Control (FMC), offset 0x008 ..................................................................... 466
Flash Controller Raw Interrupt Status (FCRIS), offset 0x00C ............................................ 468
Flash Controller Interrupt Mask (FCIM), offset 0x010 ........................................................ 471
Flash Controller Masked Interrupt Status and Clear (FCMISC), offset 0x014 ..................... 473
Flash Memory Control 2 (FMC2), offset 0x020 ................................................................. 476
Flash Write Buffer Valid (FWBVAL), offset 0x030 ............................................................. 477
Flash Write Buffer n (FWBn), offset 0x100 - 0x17C .......................................................... 478
Flash Size (FSIZE), offset 0xFC0 .................................................................................... 479
SRAM Size (SSIZE), offset 0xFC4 .................................................................................. 480
ROM Software Map (ROMSWMAP), offset 0xFCC ........................................................... 481
EEPROM Size Information (EESIZE), offset 0x000 .......................................................... 482
EEPROM Current Block (EEBLOCK), offset 0x004 .......................................................... 483
EEPROM Current Offset (EEOFFSET), offset 0x008 ........................................................ 484
22
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Tiva™ TM4C1230C3PM Microcontroller
Register 16:
Register 17:
Register 18:
Register 19:
Register 20:
Register 21:
Register 22:
Register 23:
Register 24:
Register 25:
Register 26:
Register 27:
Register 28:
Register 29:
Register 30:
Register 31:
Register 32:
Register 33:
Register 34:
Register 35:
Register 36:
EEPROM Read-Write (EERDWR), offset 0x010 .............................................................. 485
EEPROM Read-Write with Increment (EERDWRINC), offset 0x014 .................................. 486
EEPROM Done Status (EEDONE), offset 0x018 .............................................................. 487
EEPROM Support Control and Status (EESUPP), offset 0x01C ........................................ 489
EEPROM Unlock (EEUNLOCK), offset 0x020 .................................................................. 491
EEPROM Protection (EEPROT), offset 0x030 ................................................................. 492
EEPROM Password (EEPASS0), offset 0x034 ................................................................. 494
EEPROM Password (EEPASS1), offset 0x038 ................................................................. 494
EEPROM Password (EEPASS2), offset 0x03C ................................................................ 494
EEPROM Interrupt (EEINT), offset 0x040 ........................................................................ 495
EEPROM Block Hide (EEHIDE), offset 0x050 .................................................................. 496
EEPROM Debug Mass Erase (EEDBGME), offset 0x080 ................................................. 497
EEPROM Peripheral Properties (EEPROMPP), offset 0xFC0 ........................................... 498
ROM Control (RMCTL), offset 0x0F0 .............................................................................. 499
Flash Memory Protection Read Enable 0 (FMPRE0), offset 0x130 and 0x200 ................... 500
Flash Memory Protection Program Enable 0 (FMPPE0), offset 0x134 and 0x400 ............... 501
Boot Configuration (BOOTCFG), offset 0x1D0 ................................................................. 502
User Register 0 (USER_REG0), offset 0x1E0 .................................................................. 505
User Register 1 (USER_REG1), offset 0x1E4 .................................................................. 505
User Register 2 (USER_REG2), offset 0x1E8 .................................................................. 505
User Register 3 (USER_REG3), offset 0x1EC ................................................................. 505
Micro Direct Memory Access (μDMA) ........................................................................................ 506
Register 1:
Register 2:
Register 3:
Register 4:
Register 5:
Register 6:
Register 7:
Register 8:
Register 9:
Register 10:
Register 11:
Register 12:
Register 13:
Register 14:
Register 15:
Register 16:
Register 17:
Register 18:
Register 19:
Register 20:
Register 21:
Register 22:
Register 23:
Register 24:
Register 25:
Register 26:
DMA Channel Source Address End Pointer (DMASRCENDP), offset 0x000 ...................... 530
DMA Channel Destination Address End Pointer (DMADSTENDP), offset 0x004 ................ 531
DMA Channel Control Word (DMACHCTL), offset 0x008 .................................................. 532
DMA Status (DMASTAT), offset 0x000 ............................................................................ 537
DMA Configuration (DMACFG), offset 0x004 ................................................................... 539
DMA Channel Control Base Pointer (DMACTLBASE), offset 0x008 .................................. 540
DMA Alternate Channel Control Base Pointer (DMAALTBASE), offset 0x00C .................... 541
DMA Channel Wait-on-Request Status (DMAWAITSTAT), offset 0x010 ............................. 542
DMA Channel Software Request (DMASWREQ), offset 0x014 ......................................... 543
DMA Channel Useburst Set (DMAUSEBURSTSET), offset 0x018 .................................... 544
DMA Channel Useburst Clear (DMAUSEBURSTCLR), offset 0x01C ................................. 545
DMA Channel Request Mask Set (DMAREQMASKSET), offset 0x020 .............................. 546
DMA Channel Request Mask Clear (DMAREQMASKCLR), offset 0x024 ........................... 547
DMA Channel Enable Set (DMAENASET), offset 0x028 ................................................... 548
DMA Channel Enable Clear (DMAENACLR), offset 0x02C ............................................... 549
DMA Channel Primary Alternate Set (DMAALTSET), offset 0x030 .................................... 550
DMA Channel Primary Alternate Clear (DMAALTCLR), offset 0x034 ................................. 551
DMA Channel Priority Set (DMAPRIOSET), offset 0x038 ................................................. 552
DMA Channel Priority Clear (DMAPRIOCLR), offset 0x03C .............................................. 553
DMA Bus Error Clear (DMAERRCLR), offset 0x04C ........................................................ 554
DMA Channel Assignment (DMACHASGN), offset 0x500 ................................................. 555
DMA Channel Interrupt Status (DMACHIS), offset 0x504 .................................................. 556
DMA Channel Map Select 0 (DMACHMAP0), offset 0x510 ............................................... 557
DMA Channel Map Select 1 (DMACHMAP1), offset 0x514 ............................................... 558
DMA Channel Map Select 2 (DMACHMAP2), offset 0x518 ............................................... 559
DMA Channel Map Select 3 (DMACHMAP3), offset 0x51C .............................................. 560
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Texas Instruments-Production Data
Table of Contents
Register 27:
Register 28:
Register 29:
Register 30:
Register 31:
Register 32:
Register 33:
Register 34:
Register 35:
DMA Peripheral Identification 0 (DMAPeriphID0), offset 0xFE0 .........................................
DMA Peripheral Identification 1 (DMAPeriphID1), offset 0xFE4 .........................................
DMA Peripheral Identification 2 (DMAPeriphID2), offset 0xFE8 .........................................
DMA Peripheral Identification 3 (DMAPeriphID3), offset 0xFEC ........................................
DMA Peripheral Identification 4 (DMAPeriphID4), offset 0xFD0 .........................................
DMA PrimeCell Identification 0 (DMAPCellID0), offset 0xFF0 ...........................................
DMA PrimeCell Identification 1 (DMAPCellID1), offset 0xFF4 ...........................................
DMA PrimeCell Identification 2 (DMAPCellID2), offset 0xFF8 ...........................................
DMA PrimeCell Identification 3 (DMAPCellID3), offset 0xFFC ...........................................
561
562
563
564
565
566
567
568
569
General-Purpose Input/Outputs (GPIOs) ................................................................................... 570
Register 1:
Register 2:
Register 3:
Register 4:
Register 5:
Register 6:
Register 7:
Register 8:
Register 9:
Register 10:
Register 11:
Register 12:
Register 13:
Register 14:
Register 15:
Register 16:
Register 17:
Register 18:
Register 19:
Register 20:
Register 21:
Register 22:
Register 23:
Register 24:
Register 25:
Register 26:
Register 27:
Register 28:
Register 29:
Register 30:
Register 31:
Register 32:
Register 33:
Register 34:
Register 35:
Register 36:
GPIO Data (GPIODATA), offset 0x000 ............................................................................ 583
GPIO Direction (GPIODIR), offset 0x400 ......................................................................... 584
GPIO Interrupt Sense (GPIOIS), offset 0x404 .................................................................. 585
GPIO Interrupt Both Edges (GPIOIBE), offset 0x408 ........................................................ 586
GPIO Interrupt Event (GPIOIEV), offset 0x40C ................................................................ 587
GPIO Interrupt Mask (GPIOIM), offset 0x410 ................................................................... 588
GPIO Raw Interrupt Status (GPIORIS), offset 0x414 ........................................................ 589
GPIO Masked Interrupt Status (GPIOMIS), offset 0x418 ................................................... 590
GPIO Interrupt Clear (GPIOICR), offset 0x41C ................................................................ 591
GPIO Alternate Function Select (GPIOAFSEL), offset 0x420 ............................................ 592
GPIO 2-mA Drive Select (GPIODR2R), offset 0x500 ........................................................ 594
GPIO 4-mA Drive Select (GPIODR4R), offset 0x504 ........................................................ 595
GPIO 8-mA Drive Select (GPIODR8R), offset 0x508 ........................................................ 596
GPIO Open Drain Select (GPIOODR), offset 0x50C ......................................................... 597
GPIO Pull-Up Select (GPIOPUR), offset 0x510 ................................................................ 598
GPIO Pull-Down Select (GPIOPDR), offset 0x514 ........................................................... 600
GPIO Slew Rate Control Select (GPIOSLR), offset 0x518 ................................................ 602
GPIO Digital Enable (GPIODEN), offset 0x51C ................................................................ 603
GPIO Lock (GPIOLOCK), offset 0x520 ............................................................................ 605
GPIO Commit (GPIOCR), offset 0x524 ............................................................................ 606
GPIO Analog Mode Select (GPIOAMSEL), offset 0x528 ................................................... 608
GPIO Port Control (GPIOPCTL), offset 0x52C ................................................................. 609
GPIO ADC Control (GPIOADCCTL), offset 0x530 ............................................................ 611
GPIO DMA Control (GPIODMACTL), offset 0x534 ........................................................... 612
GPIO Peripheral Identification 4 (GPIOPeriphID4), offset 0xFD0 ....................................... 613
GPIO Peripheral Identification 5 (GPIOPeriphID5), offset 0xFD4 ....................................... 614
GPIO Peripheral Identification 6 (GPIOPeriphID6), offset 0xFD8 ....................................... 615
GPIO Peripheral Identification 7 (GPIOPeriphID7), offset 0xFDC ...................................... 616
GPIO Peripheral Identification 0 (GPIOPeriphID0), offset 0xFE0 ....................................... 617
GPIO Peripheral Identification 1 (GPIOPeriphID1), offset 0xFE4 ....................................... 618
GPIO Peripheral Identification 2 (GPIOPeriphID2), offset 0xFE8 ....................................... 619
GPIO Peripheral Identification 3 (GPIOPeriphID3), offset 0xFEC ...................................... 620
GPIO PrimeCell Identification 0 (GPIOPCellID0), offset 0xFF0 .......................................... 621
GPIO PrimeCell Identification 1 (GPIOPCellID1), offset 0xFF4 .......................................... 622
GPIO PrimeCell Identification 2 (GPIOPCellID2), offset 0xFF8 .......................................... 623
GPIO PrimeCell Identification 3 (GPIOPCellID3), offset 0xFFC ......................................... 624
General-Purpose Timers ............................................................................................................. 625
Register 1:
GPTM Configuration (GPTMCFG), offset 0x000 .............................................................. 648
24
June 12, 2014
Texas Instruments-Production Data
Tiva™ TM4C1230C3PM Microcontroller
Register 2:
Register 3:
Register 4:
Register 5:
Register 6:
Register 7:
Register 8:
Register 9:
Register 10:
Register 11:
Register 12:
Register 13:
Register 14:
Register 15:
Register 16:
Register 17:
Register 18:
Register 19:
Register 20:
Register 21:
Register 22:
Register 23:
Register 24:
Register 25:
Register 26:
Register 27:
GPTM Timer A Mode (GPTMTAMR), offset 0x004 ........................................................... 650
GPTM Timer B Mode (GPTMTBMR), offset 0x008 ........................................................... 654
GPTM Control (GPTMCTL), offset 0x00C ........................................................................ 658
GPTM Synchronize (GPTMSYNC), offset 0x010 .............................................................. 662
GPTM Interrupt Mask (GPTMIMR), offset 0x018 .............................................................. 666
GPTM Raw Interrupt Status (GPTMRIS), offset 0x01C ..................................................... 669
GPTM Masked Interrupt Status (GPTMMIS), offset 0x020 ................................................ 672
GPTM Interrupt Clear (GPTMICR), offset 0x024 .............................................................. 675
GPTM Timer A Interval Load (GPTMTAILR), offset 0x028 ................................................ 677
GPTM Timer B Interval Load (GPTMTBILR), offset 0x02C ................................................ 678
GPTM Timer A Match (GPTMTAMATCHR), offset 0x030 .................................................. 679
GPTM Timer B Match (GPTMTBMATCHR), offset 0x034 ................................................. 680
GPTM Timer A Prescale (GPTMTAPR), offset 0x038 ....................................................... 681
GPTM Timer B Prescale (GPTMTBPR), offset 0x03C ...................................................... 682
GPTM TimerA Prescale Match (GPTMTAPMR), offset 0x040 ........................................... 683
GPTM TimerB Prescale Match (GPTMTBPMR), offset 0x044 ........................................... 684
GPTM Timer A (GPTMTAR), offset 0x048 ....................................................................... 685
GPTM Timer B (GPTMTBR), offset 0x04C ....................................................................... 686
GPTM Timer A Value (GPTMTAV), offset 0x050 ............................................................... 687
GPTM Timer B Value (GPTMTBV), offset 0x054 .............................................................. 688
GPTM RTC Predivide (GPTMRTCPD), offset 0x058 ........................................................ 689
GPTM Timer A Prescale Snapshot (GPTMTAPS), offset 0x05C ........................................ 690
GPTM Timer B Prescale Snapshot (GPTMTBPS), offset 0x060 ........................................ 691
GPTM Timer A Prescale Value (GPTMTAPV), offset 0x064 .............................................. 692
GPTM Timer B Prescale Value (GPTMTBPV), offset 0x068 .............................................. 693
GPTM Peripheral Properties (GPTMPP), offset 0xFC0 ..................................................... 694
Watchdog Timers ......................................................................................................................... 695
Register 1:
Register 2:
Register 3:
Register 4:
Register 5:
Register 6:
Register 7:
Register 8:
Register 9:
Register 10:
Register 11:
Register 12:
Register 13:
Register 14:
Register 15:
Register 16:
Register 17:
Register 18:
Register 19:
Register 20:
Watchdog Load (WDTLOAD), offset 0x000 ...................................................................... 699
Watchdog Value (WDTVALUE), offset 0x004 ................................................................... 700
Watchdog Control (WDTCTL), offset 0x008 ..................................................................... 701
Watchdog Interrupt Clear (WDTICR), offset 0x00C .......................................................... 703
Watchdog Raw Interrupt Status (WDTRIS), offset 0x010 .................................................. 704
Watchdog Masked Interrupt Status (WDTMIS), offset 0x014 ............................................. 705
Watchdog Test (WDTTEST), offset 0x418 ....................................................................... 706
Watchdog Lock (WDTLOCK), offset 0xC00 ..................................................................... 707
Watchdog Peripheral Identification 4 (WDTPeriphID4), offset 0xFD0 ................................. 708
Watchdog Peripheral Identification 5 (WDTPeriphID5), offset 0xFD4 ................................. 709
Watchdog Peripheral Identification 6 (WDTPeriphID6), offset 0xFD8 ................................. 710
Watchdog Peripheral Identification 7 (WDTPeriphID7), offset 0xFDC ................................ 711
Watchdog Peripheral Identification 0 (WDTPeriphID0), offset 0xFE0 ................................. 712
Watchdog Peripheral Identification 1 (WDTPeriphID1), offset 0xFE4 ................................. 713
Watchdog Peripheral Identification 2 (WDTPeriphID2), offset 0xFE8 ................................. 714
Watchdog Peripheral Identification 3 (WDTPeriphID3), offset 0xFEC ................................. 715
Watchdog PrimeCell Identification 0 (WDTPCellID0), offset 0xFF0 .................................... 716
Watchdog PrimeCell Identification 1 (WDTPCellID1), offset 0xFF4 .................................... 717
Watchdog PrimeCell Identification 2 (WDTPCellID2), offset 0xFF8 .................................... 718
Watchdog PrimeCell Identification 3 (WDTPCellID3 ), offset 0xFFC .................................. 719
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Analog-to-Digital Converter (ADC) ............................................................................................. 720
Register 1:
Register 2:
Register 3:
Register 4:
Register 5:
Register 6:
Register 7:
Register 8:
Register 9:
Register 10:
Register 11:
Register 12:
Register 13:
Register 14:
Register 15:
Register 16:
Register 17:
Register 18:
Register 19:
Register 20:
Register 21:
Register 22:
Register 23:
Register 24:
Register 25:
Register 26:
Register 27:
Register 28:
Register 29:
Register 30:
Register 31:
Register 32:
Register 33:
Register 34:
Register 35:
Register 36:
Register 37:
Register 38:
Register 39:
Register 40:
Register 41:
Register 42:
Register 43:
Register 44:
Register 45:
Register 46:
Register 47:
ADC Active Sample Sequencer (ADCACTSS), offset 0x000 ............................................. 742
ADC Raw Interrupt Status (ADCRIS), offset 0x004 ........................................................... 744
ADC Interrupt Mask (ADCIM), offset 0x008 ..................................................................... 746
ADC Interrupt Status and Clear (ADCISC), offset 0x00C .................................................. 749
ADC Overflow Status (ADCOSTAT), offset 0x010 ............................................................ 752
ADC Event Multiplexer Select (ADCEMUX), offset 0x014 ................................................. 754
ADC Underflow Status (ADCUSTAT), offset 0x018 ........................................................... 759
ADC Sample Sequencer Priority (ADCSSPRI), offset 0x020 ............................................. 760
ADC Sample Phase Control (ADCSPC), offset 0x024 ...................................................... 762
ADC Processor Sample Sequence Initiate (ADCPSSI), offset 0x028 ................................. 764
ADC Sample Averaging Control (ADCSAC), offset 0x030 ................................................. 766
ADC Digital Comparator Interrupt Status and Clear (ADCDCISC), offset 0x034 ................. 767
ADC Control (ADCCTL), offset 0x038 ............................................................................. 769
ADC Sample Sequence Input Multiplexer Select 0 (ADCSSMUX0), offset 0x040 ............... 770
ADC Sample Sequence Control 0 (ADCSSCTL0), offset 0x044 ........................................ 772
ADC Sample Sequence Result FIFO 0 (ADCSSFIFO0), offset 0x048 ................................ 779
ADC Sample Sequence Result FIFO 1 (ADCSSFIFO1), offset 0x068 ................................ 779
ADC Sample Sequence Result FIFO 2 (ADCSSFIFO2), offset 0x088 ................................ 779
ADC Sample Sequence Result FIFO 3 (ADCSSFIFO3), offset 0x0A8 ............................... 779
ADC Sample Sequence FIFO 0 Status (ADCSSFSTAT0), offset 0x04C ............................. 780
ADC Sample Sequence FIFO 1 Status (ADCSSFSTAT1), offset 0x06C ............................. 780
ADC Sample Sequence FIFO 2 Status (ADCSSFSTAT2), offset 0x08C ............................ 780
ADC Sample Sequence FIFO 3 Status (ADCSSFSTAT3), offset 0x0AC ............................ 780
ADC Sample Sequence 0 Operation (ADCSSOP0), offset 0x050 ...................................... 782
ADC Sample Sequence 0 Digital Comparator Select (ADCSSDC0), offset 0x054 .............. 784
ADC Sample Sequence Input Multiplexer Select 1 (ADCSSMUX1), offset 0x060 ............... 786
ADC Sample Sequence Input Multiplexer Select 2 (ADCSSMUX2), offset 0x080 ............... 786
ADC Sample Sequence Control 1 (ADCSSCTL1), offset 0x064 ........................................ 787
ADC Sample Sequence Control 2 (ADCSSCTL2), offset 0x084 ........................................ 787
ADC Sample Sequence 1 Operation (ADCSSOP1), offset 0x070 ...................................... 791
ADC Sample Sequence 2 Operation (ADCSSOP2), offset 0x090 ..................................... 791
ADC Sample Sequence 1 Digital Comparator Select (ADCSSDC1), offset 0x074 .............. 792
ADC Sample Sequence 2 Digital Comparator Select (ADCSSDC2), offset 0x094 .............. 792
ADC Sample Sequence Input Multiplexer Select 3 (ADCSSMUX3), offset 0x0A0 ............... 794
ADC Sample Sequence Control 3 (ADCSSCTL3), offset 0x0A4 ........................................ 795
ADC Sample Sequence 3 Operation (ADCSSOP3), offset 0x0B0 ..................................... 797
ADC Sample Sequence 3 Digital Comparator Select (ADCSSDC3), offset 0x0B4 .............. 798
ADC Digital Comparator Reset Initial Conditions (ADCDCRIC), offset 0xD00 ..................... 799
ADC Digital Comparator Control 0 (ADCDCCTL0), offset 0xE00 ....................................... 804
ADC Digital Comparator Control 1 (ADCDCCTL1), offset 0xE04 ....................................... 804
ADC Digital Comparator Control 2 (ADCDCCTL2), offset 0xE08 ....................................... 804
ADC Digital Comparator Control 3 (ADCDCCTL3), offset 0xE0C ...................................... 804
ADC Digital Comparator Control 4 (ADCDCCTL4), offset 0xE10 ....................................... 804
ADC Digital Comparator Control 5 (ADCDCCTL5), offset 0xE14 ....................................... 804
ADC Digital Comparator Control 6 (ADCDCCTL6), offset 0xE18 ....................................... 804
ADC Digital Comparator Control 7 (ADCDCCTL7), offset 0xE1C ...................................... 804
ADC Digital Comparator Range 0 (ADCDCCMP0), offset 0xE40 ....................................... 806
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Register 48:
Register 49:
Register 50:
Register 51:
Register 52:
Register 53:
Register 54:
Register 55:
Register 56:
Register 57:
ADC Digital Comparator Range 1 (ADCDCCMP1), offset 0xE44 ....................................... 806
ADC Digital Comparator Range 2 (ADCDCCMP2), offset 0xE48 ....................................... 806
ADC Digital Comparator Range 3 (ADCDCCMP3), offset 0xE4C ...................................... 806
ADC Digital Comparator Range 4 (ADCDCCMP4), offset 0xE50 ....................................... 806
ADC Digital Comparator Range 5 (ADCDCCMP5), offset 0xE54 ....................................... 806
ADC Digital Comparator Range 6 (ADCDCCMP6), offset 0xE58 ....................................... 806
ADC Digital Comparator Range 7 (ADCDCCMP7), offset 0xE5C ...................................... 806
ADC Peripheral Properties (ADCPP), offset 0xFC0 .......................................................... 807
ADC Peripheral Configuration (ADCPC), offset 0xFC4 ..................................................... 809
ADC Clock Configuration (ADCCC), offset 0xFC8 ............................................................ 810
Universal Asynchronous Receivers/Transmitters (UARTs) ..................................................... 811
Register 1:
Register 2:
Register 3:
Register 4:
Register 5:
Register 6:
Register 7:
Register 8:
Register 9:
Register 10:
Register 11:
Register 12:
Register 13:
Register 14:
Register 15:
Register 16:
Register 17:
Register 18:
Register 19:
Register 20:
Register 21:
Register 22:
Register 23:
Register 24:
Register 25:
Register 26:
Register 27:
Register 28:
Register 29:
Register 30:
UART Data (UARTDR), offset 0x000 ............................................................................... 824
UART Receive Status/Error Clear (UARTRSR/UARTECR), offset 0x004 ........................... 826
UART Flag (UARTFR), offset 0x018 ................................................................................ 829
UART IrDA Low-Power Register (UARTILPR), offset 0x020 ............................................. 831
UART Integer Baud-Rate Divisor (UARTIBRD), offset 0x024 ............................................ 832
UART Fractional Baud-Rate Divisor (UARTFBRD), offset 0x028 ....................................... 833
UART Line Control (UARTLCRH), offset 0x02C ............................................................... 834
UART Control (UARTCTL), offset 0x030 ......................................................................... 836
UART Interrupt FIFO Level Select (UARTIFLS), offset 0x034 ........................................... 840
UART Interrupt Mask (UARTIM), offset 0x038 ................................................................. 842
UART Raw Interrupt Status (UARTRIS), offset 0x03C ...................................................... 845
UART Masked Interrupt Status (UARTMIS), offset 0x040 ................................................. 848
UART Interrupt Clear (UARTICR), offset 0x044 ............................................................... 851
UART DMA Control (UARTDMACTL), offset 0x048 .......................................................... 853
UART 9-Bit Self Address (UART9BITADDR), offset 0x0A4 ............................................... 854
UART 9-Bit Self Address Mask (UART9BITAMASK), offset 0x0A8 .................................... 855
UART Peripheral Properties (UARTPP), offset 0xFC0 ...................................................... 856
UART Clock Configuration (UARTCC), offset 0xFC8 ........................................................ 857
UART Peripheral Identification 4 (UARTPeriphID4), offset 0xFD0 ..................................... 858
UART Peripheral Identification 5 (UARTPeriphID5), offset 0xFD4 ..................................... 859
UART Peripheral Identification 6 (UARTPeriphID6), offset 0xFD8 ..................................... 860
UART Peripheral Identification 7 (UARTPeriphID7), offset 0xFDC ..................................... 861
UART Peripheral Identification 0 (UARTPeriphID0), offset 0xFE0 ...................................... 862
UART Peripheral Identification 1 (UARTPeriphID1), offset 0xFE4 ...................................... 863
UART Peripheral Identification 2 (UARTPeriphID2), offset 0xFE8 ...................................... 864
UART Peripheral Identification 3 (UARTPeriphID3), offset 0xFEC ..................................... 865
UART PrimeCell Identification 0 (UARTPCellID0), offset 0xFF0 ........................................ 866
UART PrimeCell Identification 1 (UARTPCellID1), offset 0xFF4 ........................................ 867
UART PrimeCell Identification 2 (UARTPCellID2), offset 0xFF8 ........................................ 868
UART PrimeCell Identification 3 (UARTPCellID3), offset 0xFFC ........................................ 869
Synchronous Serial Interface (SSI) ............................................................................................ 870
Register 1:
Register 2:
Register 3:
Register 4:
Register 5:
Register 6:
SSI Control 0 (SSICR0), offset 0x000 ..............................................................................
SSI Control 1 (SSICR1), offset 0x004 ..............................................................................
SSI Data (SSIDR), offset 0x008 ......................................................................................
SSI Status (SSISR), offset 0x00C ...................................................................................
SSI Clock Prescale (SSICPSR), offset 0x010 ..................................................................
SSI Interrupt Mask (SSIIM), offset 0x014 .........................................................................
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891
892
894
895
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Register 7:
Register 8:
Register 9:
Register 10:
Register 11:
Register 12:
Register 13:
Register 14:
Register 15:
Register 16:
Register 17:
Register 18:
Register 19:
Register 20:
Register 21:
Register 22:
Register 23:
SSI Raw Interrupt Status (SSIRIS), offset 0x018 .............................................................. 896
SSI Masked Interrupt Status (SSIMIS), offset 0x01C ........................................................ 898
SSI Interrupt Clear (SSIICR), offset 0x020 ....................................................................... 900
SSI DMA Control (SSIDMACTL), offset 0x024 ................................................................. 901
SSI Clock Configuration (SSICC), offset 0xFC8 ............................................................... 902
SSI Peripheral Identification 4 (SSIPeriphID4), offset 0xFD0 ............................................. 903
SSI Peripheral Identification 5 (SSIPeriphID5), offset 0xFD4 ............................................. 904
SSI Peripheral Identification 6 (SSIPeriphID6), offset 0xFD8 ............................................. 905
SSI Peripheral Identification 7 (SSIPeriphID7), offset 0xFDC ............................................ 906
SSI Peripheral Identification 0 (SSIPeriphID0), offset 0xFE0 ............................................. 907
SSI Peripheral Identification 1 (SSIPeriphID1), offset 0xFE4 ............................................. 908
SSI Peripheral Identification 2 (SSIPeriphID2), offset 0xFE8 ............................................. 909
SSI Peripheral Identification 3 (SSIPeriphID3), offset 0xFEC ............................................ 910
SSI PrimeCell Identification 0 (SSIPCellID0), offset 0xFF0 ............................................... 911
SSI PrimeCell Identification 1 (SSIPCellID1), offset 0xFF4 ............................................... 912
SSI PrimeCell Identification 2 (SSIPCellID2), offset 0xFF8 ............................................... 913
SSI PrimeCell Identification 3 (SSIPCellID3), offset 0xFFC ............................................... 914
Inter-Integrated Circuit (I2C) Interface ........................................................................................ 915
Register 1:
Register 2:
Register 3:
Register 4:
Register 5:
Register 6:
Register 7:
Register 8:
Register 9:
Register 10:
Register 11:
Register 12:
Register 13:
Register 14:
Register 15:
Register 16:
Register 17:
Register 18:
Register 19:
Register 20:
Register 21:
Register 22:
Register 23:
I2C Master Slave Address (I2CMSA), offset 0x000 ........................................................... 937
I2C Master Control/Status (I2CMCS), offset 0x004 ........................................................... 938
I2C Master Data (I2CMDR), offset 0x008 ......................................................................... 943
I2C Master Timer Period (I2CMTPR), offset 0x00C ........................................................... 944
I2C Master Interrupt Mask (I2CMIMR), offset 0x010 ......................................................... 945
I2C Master Raw Interrupt Status (I2CMRIS), offset 0x014 ................................................. 946
I2C Master Masked Interrupt Status (I2CMMIS), offset 0x018 ........................................... 947
I2C Master Interrupt Clear (I2CMICR), offset 0x01C ......................................................... 948
I2C Master Configuration (I2CMCR), offset 0x020 ............................................................ 949
I2C Master Clock Low Timeout Count (I2CMCLKOCNT), offset 0x024 ............................... 951
I2C Master Bus Monitor (I2CMBMON), offset 0x02C ........................................................ 952
I2C Master Configuration 2 (I2CMCR2), offset 0x038 ....................................................... 953
I2C Slave Own Address (I2CSOAR), offset 0x800 ............................................................ 954
I2C Slave Control/Status (I2CSCSR), offset 0x804 ........................................................... 955
I2C Slave Data (I2CSDR), offset 0x808 ........................................................................... 957
I2C Slave Interrupt Mask (I2CSIMR), offset 0x80C ........................................................... 958
I2C Slave Raw Interrupt Status (I2CSRIS), offset 0x810 ................................................... 959
I2C Slave Masked Interrupt Status (I2CSMIS), offset 0x814 .............................................. 960
I2C Slave Interrupt Clear (I2CSICR), offset 0x818 ............................................................ 961
I2C Slave Own Address 2 (I2CSOAR2), offset 0x81C ....................................................... 962
I2C Slave ACK Control (I2CSACKCTL), offset 0x820 ....................................................... 963
I2C Peripheral Properties (I2CPP), offset 0xFC0 .............................................................. 964
I2C Peripheral Configuration (I2CPC), offset 0xFC4 ......................................................... 965
Controller Area Network (CAN) Module ..................................................................................... 966
Register 1:
Register 2:
Register 3:
Register 4:
Register 5:
CAN Control (CANCTL), offset 0x000 ............................................................................. 987
CAN Status (CANSTS), offset 0x004 ............................................................................... 989
CAN Error Counter (CANERR), offset 0x008 ................................................................... 992
CAN Bit Timing (CANBIT), offset 0x00C .......................................................................... 993
CAN Interrupt (CANINT), offset 0x010 ............................................................................. 994
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Tiva™ TM4C1230C3PM Microcontroller
Register 6:
Register 7:
Register 8:
Register 9:
Register 10:
Register 11:
Register 12:
Register 13:
Register 14:
Register 15:
Register 16:
Register 17:
Register 18:
Register 19:
Register 20:
Register 21:
Register 22:
Register 23:
Register 24:
Register 25:
Register 26:
Register 27:
Register 28:
Register 29:
Register 30:
Register 31:
Register 32:
Register 33:
Register 34:
Register 35:
Register 36:
Register 37:
CAN Test (CANTST), offset 0x014 .................................................................................. 995
CAN Baud Rate Prescaler Extension (CANBRPE), offset 0x018 ....................................... 997
CAN IF1 Command Request (CANIF1CRQ), offset 0x020 ................................................ 998
CAN IF2 Command Request (CANIF2CRQ), offset 0x080 ................................................ 998
CAN IF1 Command Mask (CANIF1CMSK), offset 0x024 .................................................. 999
CAN IF2 Command Mask (CANIF2CMSK), offset 0x084 .................................................. 999
CAN IF1 Mask 1 (CANIF1MSK1), offset 0x028 .............................................................. 1002
CAN IF2 Mask 1 (CANIF2MSK1), offset 0x088 .............................................................. 1002
CAN IF1 Mask 2 (CANIF1MSK2), offset 0x02C .............................................................. 1003
CAN IF2 Mask 2 (CANIF2MSK2), offset 0x08C .............................................................. 1003
CAN IF1 Arbitration 1 (CANIF1ARB1), offset 0x030 ....................................................... 1005
CAN IF2 Arbitration 1 (CANIF2ARB1), offset 0x090 ....................................................... 1005
CAN IF1 Arbitration 2 (CANIF1ARB2), offset 0x034 ....................................................... 1006
CAN IF2 Arbitration 2 (CANIF2ARB2), offset 0x094 ....................................................... 1006
CAN IF1 Message Control (CANIF1MCTL), offset 0x038 ................................................ 1008
CAN IF2 Message Control (CANIF2MCTL), offset 0x098 ................................................ 1008
CAN IF1 Data A1 (CANIF1DA1), offset 0x03C ............................................................... 1011
CAN IF1 Data A2 (CANIF1DA2), offset 0x040 ................................................................ 1011
CAN IF1 Data B1 (CANIF1DB1), offset 0x044 ................................................................ 1011
CAN IF1 Data B2 (CANIF1DB2), offset 0x048 ................................................................ 1011
CAN IF2 Data A1 (CANIF2DA1), offset 0x09C ............................................................... 1011
CAN IF2 Data A2 (CANIF2DA2), offset 0x0A0 ............................................................... 1011
CAN IF2 Data B1 (CANIF2DB1), offset 0x0A4 ............................................................... 1011
CAN IF2 Data B2 (CANIF2DB2), offset 0x0A8 ............................................................... 1011
CAN Transmission Request 1 (CANTXRQ1), offset 0x100 .............................................. 1012
CAN Transmission Request 2 (CANTXRQ2), offset 0x104 .............................................. 1012
CAN New Data 1 (CANNWDA1), offset 0x120 ............................................................... 1013
CAN New Data 2 (CANNWDA2), offset 0x124 ............................................................... 1013
CAN Message 1 Interrupt Pending (CANMSG1INT), offset 0x140 ................................... 1014
CAN Message 2 Interrupt Pending (CANMSG2INT), offset 0x144 ................................... 1014
CAN Message 1 Valid (CANMSG1VAL), offset 0x160 ..................................................... 1015
CAN Message 2 Valid (CANMSG2VAL), offset 0x164 ..................................................... 1015
Analog Comparators ................................................................................................................. 1016
Register 1:
Register 2:
Register 3:
Register 4:
Register 5:
Register 6:
Register 7:
Register 8:
Register 9:
Analog Comparator Masked Interrupt Status (ACMIS), offset 0x000 ................................ 1023
Analog Comparator Raw Interrupt Status (ACRIS), offset 0x004 ..................................... 1024
Analog Comparator Interrupt Enable (ACINTEN), offset 0x008 ....................................... 1025
Analog Comparator Reference Voltage Control (ACREFCTL), offset 0x010 ..................... 1026
Analog Comparator Status 0 (ACSTAT0), offset 0x020 ................................................... 1027
Analog Comparator Status 1 (ACSTAT1), offset 0x040 ................................................... 1027
Analog Comparator Control 0 (ACCTL0), offset 0x024 ................................................... 1028
Analog Comparator Control 1 (ACCTL1), offset 0x044 ................................................... 1028
Analog Comparator Peripheral Properties (ACMPPP), offset 0xFC0 ................................ 1030
June 12, 2014
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Revision History
Revision History
The revision history table notes changes made between the indicated revisions of the
TM4C1230C3PM data sheet.
Table 1. Revision History
Date
June 2014
March 2014
November 2013
Revision
Description
15842.2741 ■
In System Control Chapter, corrected description for MINSYSDIV bitfield in Device Capabilities 1
(DC1) legacy register.
■
In Timers chapter, removed erroneous references to TCACT bit field.
■
In SSI chapter, corrected that during idle periods the transmit data line SSInTx is tristated.
■
In Package Information appendix:
– Corrected Key to Part Numbers diagram.
– Moved Orderable Part Numbers table to addendum.
– Deleted Packaging Materials section and put into separate packaging document.
■
Additional minor data sheet clarifications and corrections.
15741.2722 ■
In the Internal Memory chapter, in the EEPROM section:
– Added section on soft reset handling.
– Added important information on EEPROM initialization and configuration.
■
In the DMA chapter, added information regarding interrupts and transfers from the UART or SSI
modules.
■
In the GPIO chapter:
– Corrected table GPIO Pins with Special Considerations.
– Added information on preventing false interrupts.
– Corrected GPIOAMSEL register to be 8 bits.
■
In the Timer chapter:
– Clarified initialization and configuration for Input-Edge Count mode.
– Clarified behavior of TnMIE and TnCINTD bits in the GPTM Timer n Mode (GPTMTnMR)
register.
■
In the Electrical Characteristics chapter:
– In table Reset Characteristics, clarified internal reset time parameter values.
– In table Hibernation Oscillator Input Characteristics, added parameter CINSE Input capacitance.
– In tables Hibernation Oscillator Input Characteristics and Main Oscillator Input Characteristics,
removed parameter C0 Crystal shunt capacitance.
– Updated table Crystal Parameters.
– In table GPIO Module Characteristics, added parameter CGPIO GPIO Digital Input Capacitance.
– Added table PWM Timing Characteristics.
■
In the Package Information appendix:
– Updated Orderable Devices section to reflect silicon revision 7 part numbers.
– Added Tape and Reel pin 1 location.
■
Additional minor data sheet clarifications and corrections.
15553.2700 ■
In System Control chapter, clarified PIOSC features and accuracy.
■
In Watchdog Timers chapter, clarified Watchdog Control (WDTCTL) register description.
■
In ADC chapter:
–
Clarified functionality when using an ADC digital comparator as a fault source.
30
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Tiva™ TM4C1230C3PM Microcontroller
Table 1. Revision History (continued)
Date
Revision
Description
–
Corrected VREF bit in ADC Control (ADCCTL) register from 2-bit field [1:0] to 1-bit field [0].
In UART chapter, clarified DMA operation.
■
In SSI chapter:
■
■
15033.2672 ■
■
July 2013
Clarified signals used for ADC voltage reference.
■
■
July 16, 2013
–
14995.2667 ■
–
Corrected timing guidelines in figures "Freescale SPI Frame Format (Continuous Transfer) with
SPO=1 and SPH=0" and "Freescale SPI Format (Continuous Transfer) with SPO=0 and SPH=0".
–
Clarified SSI Initialization and Configuration.
–
Corrected bit 3 in SSI Control 1 (SSICR1) register from SOD (SSI Slave Mode Output Disable)
to reserved.
In Signal Tables chapter:
–
In Unused Signals table, corrected preferred and acceptable practices for RST pin.
–
Clarified GNDX pin description.
In Electrical Characteristics chapter:
–
In Power-On and Brown-Out Levels table, corrected TVDDC_RISE parameter min and max values.
–
In PIOSC Clock Characteristics table, clarified FPIOSC parameter values by defining values for
both factory calibration and recalibration. Also added PIOSC startup time parameter to table.
–
In Main Oscillator Specifications section, corrected minimum value for External load capacitance
on OSC0, OSC1 pins. Also added two 25-MHz crystals to Crystal Parameters table.
–
Corrected figure "Master Mode SSI Timing for SPI Frame Format (FRF=00), with SPH=1".
–
In I2C Characteristics table, clarified TDH data hold time parameter values by defining values
for both slave and master. In addition, added parameter I10 TDV data valid.
–
Modified figure "I2C Timing" to add new parameter I10.
In Packaging Information appendix, added Packaging Materials figures.
In the Electrical Characteristics chapter:
–
Added maximum junction temperature to Maximum Ratings table. Also moved Unpowered
storage temperature range parameter to this table.
–
In SSI Characteristics table, corrected values for TRXDMS, TRXDMH, and TRXDSSU. Also clarified
footnotes to table.
–
Corrected parameter numbers in figures "Master Mode SSI Timing for SPI Frame Format
(FRF=00), with SPH=1" and "Slave Mode SSI Timing for SPI Frame Format (FRF=00), with
SPH=1".
Additional minor data sheet clarifications and corrections.
In the System Control chapter, corrected resets for bits [7:4] in System Properties (SYSPROP)
register.
■
In the Internal Memory chapter, removed the INVPL bit from the EEPROM Done Status (EEDONE)
register.
■
In the uDMA chapter, in the µDMA Channel Assignments table, corrected names of timers 6-11 to
wide timers 0-5.
June 12, 2014
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Revision History
Table 1. Revision History (continued)
Date
Revision
Description
■
In the Timers chapter:
–
Clarified that the timer must be configured for one-shot or periodic time-out mode to produce
an ADC trigger assertion and that the GPTM does not generate triggers for match, compare
events or compare match events.
–
Added a step in the RTC Mode initialization and configuration: If the timer has been operating
in a different mode prior to this, clear any residual set bits in the GPTM Timer n Mode
(GPTMTnMR) register before reconfiguring.
■
In the Watchdog Timer chapter, added a note that locking the watchdog registers using the
WDTLOCK register does not affect the WDTICR register and allows interrupts to always be serviced.
■
In the SSI chapter, clarified note in Bit Rate Generation section to indicate that the System Clock
or the PIOSC can be used as the source for SSIClk. Also corrected to indicate maximum SSIClk
limit in SSI slave mode as well as the fact that SYSCLK has to be at least 12 times that of SSICLk.
■
In the Electrical Characteristics chapter:
–
Moved Maximum Ratings and ESD Absolute Maximum Ratings to the front of the chapter.
–
Added VBATRMP parameter to Maximum Ratings and Hibernation Module Battery Characteristics
tables.
–
Added ambient and junction temperatures to Temperature Characteristics table and clarified
values in Thermal Characteristics table.
–
Added clarifying footnote to VVDD_POK parameter in Power-On and Brown-Out Levels table.
–
In the Flash Memory and EEPROM Characteristics tables, added a parameter for page/mass
erase times for 10k cycles and corrected existing values for all page and mass erase parameters.
–
Corrected DNL max value in ADC Electrical Characteristics table.
–
In the SSI Characteristics table, changed parameter names for S7-S14, provided a max number
instead of a min for S7, and corrected values for S9-S14.
–
Replaced figure "SSI Timing for SPI Frame Format (FRF=00), with SPH=1" with two figures,
one for Master Mode and one for Slave Mode.
–
Updated and added values to the table Table 20-36 on page 1093.
■
In the Package Information appendix, moved orderable devices table from addendum to appendix,
clarified part markings and moved packaging diagram from addendum to appendix.
■
Additional minor data sheet clarifications and corrections.
32
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Tiva™ TM4C1230C3PM Microcontroller
About This Document
This data sheet provides reference information for the TM4C1230C3PM microcontroller, describing
the functional blocks of the system-on-chip (SoC) device designed around the ARM® Cortex™-M4F
core.
Audience
This manual is intended for system software developers, hardware designers, and application
developers.
About This Manual
This document is organized into sections that correspond to each major feature.
Related Documents
The following related documents are available on the Tiva™ C Series web site at
http://www.ti.com/tiva-c:
■ Tiva™ C Series TM4C123x Silicon Errata (literature number SPMZ849)
■ TivaWare™ Boot Loader for C Series User's Guide (literature number SPMU301)
■ TivaWare™ Graphics Library for C Series User's Guide (literature number SPMU300)
■ TivaWare™ for C Series Release Notes (literature number SPMU299)
■ TivaWare™ Peripheral Driver Library for C Series User's Guide (literature number SPMU298)
■ TivaWare™ USB Library for C Series User's Guide (literature number SPMU297)
■ Tiva™ C Series TM4C123x ROM User’s Guide (literature number SPMU367)
The following related documents may also be useful:
■ ARM® Cortex™-M4 Errata (literature number SPMZ637)
■ ARM® Cortex™-M4 Technical Reference Manual
■ ARM® Debug Interface V5 Architecture Specification
■ ARM® Embedded Trace Macrocell Architecture Specification
■ Cortex™-M4 instruction set chapter in the ARM® Cortex™-M4 Devices Generic User Guide
(literature number ARM DUI 0553A)
■ IEEE Standard 1149.1-Test Access Port and Boundary-Scan Architecture
This documentation list was current as of publication date. Please check the web site for additional
documentation, including application notes and white papers.
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About This Document
Documentation Conventions
This document uses the conventions shown in Table 2 on page 34.
Table 2. Documentation Conventions
Notation
Meaning
General Register Notation
REGISTER
APB registers are indicated in uppercase bold. For example, PBORCTL is the Power-On and
Brown-Out Reset Control register. If a register name contains a lowercase n, it represents more
than one register. For example, SRCRn represents any (or all) of the three Software Reset Control
registers: SRCR0, SRCR1 , and SRCR2.
bit
A single bit in a register.
bit field
Two or more consecutive and related bits.
offset 0xnnn
A hexadecimal increment to a register's address, relative to that module's base address as specified
in Table 2-4 on page 78.
Register N
Registers are numbered consecutively throughout the document to aid in referencing them. The
register number has no meaning to software.
reserved
Register bits marked reserved are reserved for future use. In most cases, reserved bits are set to
0; however, user software should not rely on the value of a reserved bit. To provide software
compatibility with future products, the value of a reserved bit should be preserved across a
read-modify-write operation.
yy:xx
The range of register bits inclusive from xx to yy. For example, 31:15 means bits 15 through 31 in
that register.
Register Bit/Field
Types
This value in the register bit diagram indicates whether software running on the controller can
change the value of the bit field.
RC
Software can read this field. The bit or field is cleared by hardware after reading the bit/field.
RO
Software can read this field. Always write the chip reset value.
RW
Software can read or write this field.
RWC
Software can read or write this field. Writing to it with any value clears the register.
RW1C
Software can read or write this field. A write of a 0 to a W1C bit does not affect the bit value in the
register. A write of a 1 clears the value of the bit in the register; the remaining bits remain unchanged.
This register type is primarily used for clearing interrupt status bits where the read operation provides
the interrupt status and the write of the read value clears only the interrupts being reported at the
time the register was read.
RW1S
Software can read or write a 1 to this field. A write of a 0 to a RW1S bit does not affect the bit value
in the register.
W1C
Software can write this field. A write of a 0 to a W1C bit does not affect the bit value in the register.
A write of a 1 clears the value of the bit in the register; the remaining bits remain unchanged. A
read of the register returns no meaningful data.
This register is typically used to clear the corresponding bit in an interrupt register.
WO
Only a write by software is valid; a read of the register returns no meaningful data.
Register Bit/Field
Reset Value
This value in the register bit diagram shows the bit/field value after any reset, unless noted.
0
Bit cleared to 0 on chip reset.
1
Bit set to 1 on chip reset.
-
Nondeterministic.
Pin/Signal Notation
[]
Pin alternate function; a pin defaults to the signal without the brackets.
pin
Refers to the physical connection on the package.
signal
Refers to the electrical signal encoding of a pin.
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Table 2. Documentation Conventions (continued)
Notation
Meaning
assert a signal
Change the value of the signal from the logically False state to the logically True state. For active
High signals, the asserted signal value is 1 (High); for active Low signals, the asserted signal value
is 0 (Low). The active polarity (High or Low) is defined by the signal name (see SIGNAL and SIGNAL
below).
deassert a signal
Change the value of the signal from the logically True state to the logically False state.
SIGNAL
Signal names are in uppercase and in the Courier font. An overbar on a signal name indicates that
it is active Low. To assert SIGNAL is to drive it Low; to deassert SIGNAL is to drive it High.
SIGNAL
Signal names are in uppercase and in the Courier font. An active High signal has no overbar. To
assert SIGNAL is to drive it High; to deassert SIGNAL is to drive it Low.
Numbers
X
An uppercase X indicates any of several values is allowed, where X can be any legal pattern. For
example, a binary value of 0X00 can be either 0100 or 0000, a hex value of 0xX is 0x0 or 0x1, and
so on.
0x
Hexadecimal numbers have a prefix of 0x. For example, 0x00FF is the hexadecimal number FF.
All other numbers within register tables are assumed to be binary. Within conceptual information,
binary numbers are indicated with a b suffix, for example, 1011b, and decimal numbers are written
without a prefix or suffix.
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Architectural Overview
1
Architectural Overview
®
Texas Instrument's Tiva™ C Series microcontrollers provide designers a high-performance ARM
Cortex™-M-based architecture with a broad set of integration capabilities and a strong ecosystem
of software and development tools. Targeting performance and flexibility, the Tiva™ C Series
architecture offers a 80 MHz Cortex-M with FPU, a variety of integrated memories and multiple
programmable GPIO. Tiva™ C Series devices offer consumers compelling cost-effective solutions
by integrating application-specific peripherals and providing a comprehensive library of software
tools which minimize board costs and design-cycle time. Offering quicker time-to-market and cost
savings, the Tiva™ C Series microcontrollers are the leading choice in high-performance 32-bit
applications.
This chapter contains an overview of the Tiva™ C Series microcontrollers as well as details on the
TM4C1230C3PM microcontroller:
■
■
■
■
■
■
1.1
“Tiva™ C Series Overview” on page 36
“TM4C1230C3PM Microcontroller Overview” on page 37
“TM4C1230C3PM Microcontroller Features” on page 39
“TM4C1230C3PM Microcontroller Hardware Details” on page 54
“Kits” on page 54
“Support Information” on page 54
Tiva™ C Series Overview
The Tiva™ C Series ARM Cortex-M4 microcontrollers provide top performance and advanced
integration. The product family is positioned for cost-conscious applications requiring significant
control processing and connectivity capabilities such as:
■
■
■
■
■
■
■
■
■
■
■
Low power, hand-held smart devices
Gaming equipment
Home and commercial site monitoring and control
Motion control
Medical instrumentation
Test and measurement equipment
Factory automation
Fire and security
Smart Energy/Smart Grid solutions
Intelligent lighting control
Transportation
In addition, the TM4C1230C3PM microcontroller offers the advantages of ARM's widely available
development tools, System-on-Chip (SoC) infrastructure IP applications, and a large user community.
Additionally, the microcontroller uses ARM's Thumb®-compatible Thumb-2 instruction set to reduce
memory requirements and, thereby, cost. Finally, much of the TM4C1230C3PM microcontroller
code is compatible to the Tiva™ C Series product line, providing flexibility across designs.
Texas Instruments offers a complete solution to get to market quickly, with evaluation and
development boards, white papers and application notes, an easy-to-use peripheral driver library,
and a strong support, sales, and distributor network.
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1.2
TM4C1230C3PM Microcontroller Overview
The TM4C1230C3PM microcontroller combines complex integration and high performance with the
features shown in Table 1-1.
Table 1-1. TM4C1230C3PM Microcontroller Features
Feature
Description
Performance
Core
ARM Cortex-M4F processor core
Performance
80-MHz operation; 100 DMIPS performance
Flash
32 KB single-cycle Flash memory
System SRAM
12 KB single-cycle SRAM
EEPROM
2KB of EEPROM
Internal ROM
Internal ROM loaded with TivaWare™ for C Series software
Security
Communication Interfaces
Universal Asynchronous Receivers/Transmitter (UART) Eight UARTs
Synchronous Serial Interface (SSI)
Inter-Integrated Circuit
(I2C)
Four SSI modules
Six I2C modules with four transmission speeds including high-speed
mode
Controller Area Network (CAN)
CAN 2.0 A/B controllers
System Integration
Micro Direct Memory Access (µDMA)
ARM® PrimeCell® 32-channel configurable μDMA controller
General-Purpose Timer (GPTM)
Six 16/32-bit GPTM blocks and six 32/64-bit Wide GPTM blocks
Watchdog Timer (WDT)
Two watchdog timers
General-Purpose Input/Output (GPIO)
Seven physical GPIO blocks
Analog Support
Analog-to-Digital Converter (ADC)
Two 12-bit ADC modules, each with a maximum sample rate of one
million samples/second
Analog Comparator Controller
Two independent integrated analog comparators
Digital Comparator
16 digital comparators
JTAG and Serial Wire Debug (SWD)
One JTAG module with integrated ARM SWD
Package Information
Package
64-pin LQFP
Operating Range (Ambient)
Industrial (-40°C to 85°C) temperature range
Figure 1-1 on page 38 shows the features on the TM4C1230C3PM microcontroller. Note that there
are two on-chip buses that connect the core to the peripherals. The Advanced Peripheral Bus (APB)
bus is the legacy bus. The Advanced High-Performance Bus (AHB) bus provides better back-to-back
access performance than the APB bus.
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Architectural Overview
Figure 1-1. Tiva™ TM4C1230C3PM Microcontroller High-Level Block Diagram
JTAG/SWD
ARM®
Cortex™-M4F
ROM
(80MHz)
System
Control and
Clocks
(w/ Precis. Osc.)
ETM
FPU
NVIC
MPU
Boot Loader
DriverLib
AES & CRC
Flash
(32KB)
DCode bus
ICode bus
System Bus
TM4C1230C3PM
Bus Matrix
SRAM
(12KB)
SYSTEM PERIPHERALS
GeneralPurpose
Timer (12)
EEPROM
(2K)
I2C
(6)
CAN
Controller
(1)
Advanced Peripheral Bus (APB)
Watchdog
Timer
(2)
Advanced High-Performance Bus (AHB)
DMA
GPIOs
(49)
SERIAL PERIPHERALS
UART
(8)
SSI
(4)
ANALOG PERIPHERALS
Analog
Comparator
(2)
12- Bit ADC
Channels
(12)
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1.3
TM4C1230C3PM Microcontroller Features
The TM4C1230C3PM microcontroller component features and general function are discussed in
more detail in the following section.
1.3.1
ARM Cortex-M4F Processor Core
All members of the Tiva™ C Series, including the TM4C1230C3PM microcontroller, are designed
around an ARM Cortex-M processor core. The ARM Cortex-M processor provides the core for a
high-performance, low-cost platform that meets the needs of minimal memory implementation,
reduced pin count, and low power consumption, while delivering outstanding computational
performance and exceptional system response to interrupts.
1.3.1.1
Processor Core (see page 55)
■ 32-bit ARM Cortex-M4F architecture optimized for small-footprint embedded applications
■ 80-MHz operation; 100 DMIPS performance
■ Outstanding processing performance combined with fast interrupt handling
■ Thumb-2 mixed 16-/32-bit instruction set delivers the high performance expected of a 32-bit
ARM core in a compact memory size usually associated with 8- and 16-bit devices, typically in
the range of a few kilobytes of memory for microcontroller-class applications
– Single-cycle multiply instruction and hardware divide
– Atomic bit manipulation (bit-banding), delivering maximum memory utilization and streamlined
peripheral control
– Unaligned data access, enabling data to be efficiently packed into memory
■ IEEE754-compliant single-precision Floating-Point Unit (FPU)
■ 16-bit SIMD vector processing unit
■ Fast code execution permits slower processor clock or increases sleep mode time
■ Harvard architecture characterized by separate buses for instruction and data
■ Efficient processor core, system and memories
■ Hardware division and fast digital-signal-processing orientated multiply accumulate
■ Saturating arithmetic for signal processing
■ Deterministic, high-performance interrupt handling for time-critical applications
■ Memory protection unit (MPU) to provide a privileged mode for protected operating system
functionality
■ Enhanced system debug with extensive breakpoint and trace capabilities
■ Serial Wire Debug and Serial Wire Trace reduce the number of pins required for debugging and
tracing
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■ Migration from the ARM7™ processor family for better performance and power efficiency
■ Optimized for single-cycle Flash memory usage up to specific frequencies; see “Internal
Memory” on page 446 for more information.
■ Ultra-low power consumption with integrated sleep modes
1.3.1.2
System Timer (SysTick) (see page 109)
ARM Cortex-M4F includes an integrated system timer, SysTick. SysTick provides a simple, 24-bit,
clear-on-write, decrementing, wrap-on-zero counter with a flexible control mechanism. The counter
can be used in several different ways, for example:
■ An RTOS tick timer that fires at a programmable rate (for example, 100 Hz) and invokes a SysTick
routine
■ A high-speed alarm timer using the system clock
■ A variable rate alarm or signal timer—the duration is range-dependent on the reference clock
used and the dynamic range of the counter
■ A simple counter used to measure time to completion and time used
■ An internal clock-source control based on missing/meeting durations
1.3.1.3
Nested Vectored Interrupt Controller (NVIC) (see page 110)
The TM4C1230C3PM controller includes the ARM Nested Vectored Interrupt Controller (NVIC).
The NVIC and Cortex-M4F prioritize and handle all exceptions in Handler Mode. The processor
state is automatically stored to the stack on an exception and automatically restored from the stack
at the end of the Interrupt Service Routine (ISR). The interrupt vector is fetched in parallel to the
state saving, enabling efficient interrupt entry. The processor supports tail-chaining, meaning that
back-to-back interrupts can be performed without the overhead of state saving and restoration.
Software can set eight priority levels on 7 exceptions (system handlers) and 66 interrupts.
■ Deterministic, fast interrupt processing: always 12 cycles, or just 6 cycles with tail-chaining (these
values reflect no FPU stacking)
■ External non-maskable interrupt signal (NMI) available for immediate execution of NMI handler
for safety critical applications
■ Dynamically reprioritizable interrupts
■ Exceptional interrupt handling via hardware implementation of required register manipulations
1.3.1.4
System Control Block (SCB) (see page 111)
The SCB provides system implementation information and system control, including configuration,
control, and reporting of system exceptions.
1.3.1.5
Memory Protection Unit (MPU) (see page 111)
The MPU supports the standard ARM7 Protected Memory System Architecture (PMSA) model. The
MPU provides full support for protection regions, overlapping protection regions, access permissions,
and exporting memory attributes to the system.
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1.3.1.6
Floating-Point Unit (FPU) (see page 116)
The FPU fully supports single-precision add, subtract, multiply, divide, multiply and accumulate,
and square root operations. It also provides conversions between fixed-point and floating-point data
formats, and floating-point constant instructions.
■ 32-bit instructions for single-precision (C float) data-processing operations
■ Combined multiply and accumulate instructions for increased precision (Fused MAC)
■ Hardware support for conversion, addition, subtraction, multiplication with optional accumulate,
division, and square-root
■ Hardware support for denormals and all IEEE rounding modes
■ 32 dedicated 32-bit single-precision registers, also addressable as 16 double-word registers
■ Decoupled three stage pipeline
1.3.2
On-Chip Memory
The TM4C1230C3PM microcontroller is integrated with the following set of on-chip memory and
features:
■ 12 KB single-cycle SRAM
■ 32 KB Flash memory
■ 2KB EEPROM
■ Internal ROM loaded with TivaWare™ for C Series software:
– TivaWare™ Peripheral Driver Library
– TivaWare Boot Loader
– Advanced Encryption Standard (AES) cryptography tables
– Cyclic Redundancy Check (CRC) error detection functionality
1.3.2.1
SRAM (see page 447)
The TM4C1230C3PM microcontroller provides 12 KB of single-cycle on-chip SRAM. The internal
SRAM of the device is located at offset 0x2000.0000 of the device memory map.
Because read-modify-write (RMW) operations are very time consuming, ARM has introduced
bit-banding technology in the Cortex-M4F processor. With a bit-band-enabled processor, certain
regions in the memory map (SRAM and peripheral space) can use address aliases to access
individual bits in a single, atomic operation.
Data can be transferred to and from SRAM by the following masters:
■ µDMA
1.3.2.2
Flash Memory (see page 450)
The TM4C1230C3PM microcontroller provides 32 KB of single-cycle on-chip Flash memory. The
Flash memory is organized as a set of 1-KB blocks that can be individually erased. Erasing a block
causes the entire contents of the block to be reset to all 1s. These blocks are paired into a set of
2-KB blocks that can be individually protected. The blocks can be marked as read-only or
execute-only, providing different levels of code protection. Read-only blocks cannot be erased or
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Architectural Overview
programmed, protecting the contents of those blocks from being modified. Execute-only blocks
cannot be erased or programmed, and can only be read by the controller instruction fetch mechanism,
protecting the contents of those blocks from being read by either the controller or by a debugger.
1.3.2.3
ROM (see page 448)
The TM4C1230C3PM ROM is preprogrammed with the following software and programs:
■ TivaWare Peripheral Driver Library
■ TivaWare Boot Loader
■ Advanced Encryption Standard (AES) cryptography tables
■ Cyclic Redundancy Check (CRC) error-detection functionality
The TivaWare Peripheral Driver Library is a royalty-free software library for controlling on-chip
peripherals with a boot-loader capability. The library performs both peripheral initialization and
control functions, with a choice of polled or interrupt-driven peripheral support. In addition, the library
is designed to take full advantage of the stellar interrupt performance of the ARM Cortex-M4F core.
No special pragmas or custom assembly code prologue/epilogue functions are required. For
applications that require in-field programmability, the royalty-free TivaWare Boot Loader can act as
an application loader and support in-field firmware updates.
The Advanced Encryption Standard (AES) is a publicly defined encryption standard used by the
U.S. Government. AES is a strong encryption method with reasonable performance and size. In
addition, it is fast in both hardware and software, is fairly easy to implement, and requires little
memory. The Texas Instruments encryption package is available with full source code, and is based
on Lesser General Public License (LGPL) source. An LGPL means that the code can be used within
an application without any copyleft implications for the application (the code does not automatically
become open source). Modifications to the package source, however, must be open source.
CRC (Cyclic Redundancy Check) is a technique to validate a span of data has the same contents
as when previously checked. This technique can be used to validate correct receipt of messages
(nothing lost or modified in transit), to validate data after decompression, to validate that Flash
memory contents have not been changed, and for other cases where the data needs to be validated.
A CRC is preferred over a simple checksum (for example, XOR all bits) because it catches changes
more readily.
1.3.2.4
EEPROM (see page 456)
The TM4C1230C3PM microcontroller includes an EEPROM with the following features:
■ 2Kbytes of memory accessible as 512 32-bit words
■ 32 blocks of 16 words (64 bytes) each
■ Built-in wear leveling
■ Access protection per block
■ Lock protection option for the whole peripheral as well as per block using 32-bit to 96-bit unlock
codes (application selectable)
■ Interrupt support for write completion to avoid polling
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■ Endurance of 500K writes (when writing at fixed offset in every alternate page in circular fashion)
to 15M operations (when cycling through two pages ) per each 2-page block.
1.3.3
Serial Communications Peripherals
The TM4C1230C3PM controller supports both asynchronous and synchronous serial communications
with:
■ CAN 2.0 A/B controller
■ Eight UARTs with IrDA, 9-bit and ISO 7816 support.
■ Six I2C modules with four transmission speeds including high-speed mode
■ Four Synchronous Serial Interface modules (SSI)
The following sections provide more detail on each of these communications functions.
1.3.3.1
Controller Area Network (CAN) (see page 966)
Controller Area Network (CAN) is a multicast shared serial-bus standard for connecting electronic
control units (ECUs). CAN was specifically designed to be robust in electromagnetically noisy
environments and can utilize a differential balanced line like RS-485 or twisted-pair wire. Originally
created for automotive purposes, it is now used in many embedded control applications (for example,
industrial or medical). Bit rates up to 1 Mbps are possible at network lengths below 40 meters.
Decreased bit rates allow longer network distances (for example, 125 Kbps at 500m).
A transmitter sends a message to all CAN nodes (broadcasting). Each node decides on the basis
of the identifier received whether it should process the message. The identifier also determines the
priority that the message enjoys in competition for bus access. Each CAN message can transmit
from 0 to 8 bytes of user information.
The TM4C1230C3PM microcontroller includes one CAN unit with the following features:
■ CAN protocol version 2.0 part A/B
■ Bit rates up to 1 Mbps
■ 32 message objects with individual identifier masks
■ Maskable interrupt
■ Disable Automatic Retransmission mode for Time-Triggered CAN (TTCAN) applications
■ Programmable loopback mode for self-test operation
■ Programmable FIFO mode enables storage of multiple message objects
■ Gluelessly attaches to an external CAN transceiver through the CANnTX and CANnRX signals
1.3.3.2
UART (see page 811)
A Universal Asynchronous Receiver/Transmitter (UART) is an integrated circuit used for RS-232C
serial communications, containing a transmitter (parallel-to-serial converter) and a receiver
(serial-to-parallel converter), each clocked separately.
The TM4C1230C3PM microcontroller includes eight fully programmable 16C550-type UARTs.
Although the functionality is similar to a 16C550 UART, this UART design is not register compatible.
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The UART can generate individually masked interrupts from the Rx, Tx, modem flow control, and
error conditions. The module generates a single combined interrupt when any of the interrupts are
asserted and are unmasked.
The eight UARTs have the following features:
■ Programmable baud-rate generator allowing speeds up to 5 Mbps for regular speed (divide by
16) and 10 Mbps for high speed (divide by 8)
■ Separate 16x8 transmit (TX) and receive (RX) FIFOs to reduce CPU interrupt service loading
■ Programmable FIFO length, including 1-byte deep operation providing conventional
double-buffered interface
■ FIFO trigger levels of 1/8, 1/4, 1/2, 3/4, and 7/8
■ Standard asynchronous communication bits for start, stop, and parity
■ Line-break generation and detection
■ Fully programmable serial interface characteristics
– 5, 6, 7, or 8 data bits
– Even, odd, stick, or no-parity bit generation/detection
– 1 or 2 stop bit generation
■ IrDA serial-IR (SIR) encoder/decoder providing
– Programmable use of IrDA Serial Infrared (SIR) or UART input/output
– Support of IrDA SIR encoder/decoder functions for data rates up to 115.2 Kbps half-duplex
– Support of normal 3/16 and low-power (1.41-2.23 μs) bit durations
– Programmable internal clock generator enabling division of reference clock by 1 to 256 for
low-power mode bit duration
■ Support for communication with ISO 7816 smart cards
■ Modem flow control (on UART1)
■ EIA-485 9-bit support
■ Standard FIFO-level and End-of-Transmission interrupts
■ Efficient transfers using Micro Direct Memory Access Controller (µDMA)
– Separate channels for transmit and receive
– Receive single request asserted when data is in the FIFO; burst request asserted at
programmed FIFO level
– Transmit single request asserted when there is space in the FIFO; burst request asserted at
programmed FIFO level
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1.3.3.3
I2C (see page 915)
The Inter-Integrated Circuit (I2C) bus provides bi-directional data transfer through a two-wire design
(a serial data line SDA and a serial clock line SCL). The I2C bus interfaces to external I2C devices
such as serial memory (RAMs and ROMs), networking devices, LCDs, tone generators, and so on.
The I2C bus may also be used for system testing and diagnostic purposes in product development
and manufacture.
Each device on the I2C bus can be designated as either a master or a slave. I2C module supports
both sending and receiving data as either a master or a slave and can operate simultaneously as
both a master and a slave. Both the I2C master and slave can generate interrupts.
The TM4C1230C3PM microcontroller includes six I2C modules with the following features:
■ Devices on the I2C bus can be designated as either a master or a slave
– Supports both transmitting and receiving data as either a master or a slave
– Supports simultaneous master and slave operation
■ Four I2C modes
– Master transmit
– Master receive
– Slave transmit
– Slave receive
■ Four transmission speeds:
– Standard (100 Kbps)
– Fast-mode (400 Kbps)
– Fast-mode plus (1 Mbps)
– High-speed mode (3.33 Mbps)
■ Clock low timeout interrupt
■ Dual slave address capability
■ Glitch suppression
■ Master and slave interrupt generation
– Master generates interrupts when a transmit or receive operation completes (or aborts due
to an error)
– Slave generates interrupts when data has been transferred or requested by a master or when
a START or STOP condition is detected
■ Master with arbitration and clock synchronization, multimaster support, and 7-bit addressing
mode
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1.3.3.4
SSI (see page 870)
Synchronous Serial Interface (SSI) is a four-wire bi-directional communications interface that converts
data between parallel and serial. The SSI module performs serial-to-parallel conversion on data
received from a peripheral device, and parallel-to-serial conversion on data transmitted to a peripheral
device. The SSI module can be configured as either a master or slave device. As a slave device,
the SSI module can also be configured to disable its output, which allows a master device to be
coupled with multiple slave devices. The TX and RX paths are buffered with separate internal FIFOs.
The SSI module also includes a programmable bit rate clock divider and prescaler to generate the
output serial clock derived from the SSI module's input clock. Bit rates are generated based on the
input clock and the maximum bit rate is determined by the connected peripheral.
The TM4C1230C3PM microcontroller includes four SSI modules with the following features:
■ Programmable interface operation for Freescale SPI, MICROWIRE, or Texas Instruments
synchronous serial interfaces
■ Master or slave operation
■ Programmable clock bit rate and prescaler
■ Separate transmit and receive FIFOs, each 16 bits wide and 8 locations deep
■ Programmable data frame size from 4 to 16 bits
■ Internal loopback test mode for diagnostic/debug testing
■ Standard FIFO-based interrupts and End-of-Transmission interrupt
■ Efficient transfers using Micro Direct Memory Access Controller (µDMA)
– Separate channels for transmit and receive
– Receive single request asserted when data is in the FIFO; burst request asserted when FIFO
contains 4 entries
– Transmit single request asserted when there is space in the FIFO; burst request asserted
when four or more entries are available to be written in the FIFO
1.3.4
System Integration
The TM4C1230C3PM microcontroller provides a variety of standard system functions integrated
into the device, including:
■ Direct Memory Access Controller (DMA)
■ System control and clocks including on-chip precision 16-MHz oscillator
■ Six 32-bit timers (up to twelve 16-bit), with real-time clock capability
■ Six wide 64-bit timers (up to twelve 32-bit), with real-time clock capability
■ Twelve 32/64-bit Capture Compare PWM (CCP) pins
■ Two Watchdog Timers
– One timer runs off the main oscillator
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– One timer runs off the precision internal oscillator
■ Up to 49 GPIOs, depending on configuration
– Highly flexible pin muxing allows use as GPIO or one of several peripheral functions
– Independently configurable to 2-, 4- or 8-mA drive capability
– Up to 4 GPIOs can have 18-mA drive capability
The following sections provide more detail on each of these functions.
1.3.4.1
Direct Memory Access (see page 506)
The TM4C1230C3PM microcontroller includes a Direct Memory Access (DMA) controller, known
as micro-DMA (μDMA). The μDMA controller provides a way to offload data transfer tasks from the
Cortex-M4F processor, allowing for more efficient use of the processor and the available bus
bandwidth. The μDMA controller can perform transfers between memory and peripherals. It has
dedicated channels for each supported on-chip module and can be programmed to automatically
perform transfers between peripherals and memory as the peripheral is ready to transfer more data.
The μDMA controller provides the following features:
®
■ ARM PrimeCell 32-channel configurable µDMA controller
■ Support for memory-to-memory, memory-to-peripheral, and peripheral-to-memory in multiple
transfer modes
– Basic for simple transfer scenarios
– Ping-pong for continuous data flow
– Scatter-gather for a programmable list of up to 256 arbitrary transfers initiated from a single
request
■ Highly flexible and configurable channel operation
– Independently configured and operated channels
– Dedicated channels for supported on-chip modules
– Flexible channel assignments
– One channel each for receive and transmit path for bidirectional modules
– Dedicated channel for software-initiated transfers
– Per-channel configurable priority scheme
– Optional software-initiated requests for any channel
■ Two levels of priority
■ Design optimizations for improved bus access performance between µDMA controller and the
processor core
– µDMA controller access is subordinate to core access
– RAM striping
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– Peripheral bus segmentation
■ Data sizes of 8, 16, and 32 bits
■ Transfer size is programmable in binary steps from 1 to 1024
■ Source and destination address increment size of byte, half-word, word, or no increment
■ Maskable peripheral requests
■ Interrupt on transfer completion, with a separate interrupt per channel
1.3.4.2
System Control and Clocks (see page 198)
System control determines the overall operation of the device. It provides information about the
device, controls power-saving features, controls the clocking of the device and individual peripherals,
and handles reset detection and reporting.
■ Device identification information: version, part number, SRAM size, Flash memory size, and so
on
■ Power control
– On-chip fixed Low Drop-Out (LDO) voltage regulator
– Low-power options for microcontroller: Sleep and Deep-Sleep modes with clock gating
– Low-power options for on-chip modules: software controls shutdown of individual peripherals
and memory
– 3.3-V supply brown-out detection and reporting via interrupt or reset
■ Multiple clock sources for microcontroller system clock. The following clock sources are provided
to the TM4C1230C3PM microcontroller:
– Precision Internal Oscillator (PIOSC) providing a 16-MHz frequency
• 16 MHz ±3% across temperature and voltage
• Can be recalibrated with 7-bit trim resolution to achieve better accuracy (16 MHz ±1%)
• Software power down control for low power modes
– Main Oscillator (MOSC): A frequency-accurate clock source by one of two means: an external
single-ended clock source is connected to the OSC0 input pin, or an external crystal is
connected across the OSC0 input and OSC1 output pins.
– Low Frequency Internal Oscillator (LFIOSC): On-chip resource used during power-saving
modes
■ Flexible reset sources
– Power-on reset (POR)
– Reset pin assertion
– Brown-out reset (BOR) detector alerts to system power drops
– Software reset
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– Watchdog timer reset
– MOSC failure
1.3.4.3
Programmable Timers (see page 625)
Programmable timers can be used to count or time external events that drive the Timer input pins.
Each 16/32-bit GPTM block provides two 16-bit timers/counters that can be configured to operate
independently as timers or event counters, or configured to operate as one 32-bit timer or one 32-bit
Real-Time Clock (RTC). Each 32/64-bit Wide GPTM block provides two 32-bit timers/counters that
can be configured to operate independently as timersor event counters, or configured to operate
as one 64-bit timer or one 64-bit Real-Time Clock (RTC). Timers can also be used to trigger
analog-to-digital (ADC) conversions and DMA transfers.
The General-Purpose Timer Module (GPTM) contains six 16/32-bit GPTM blocks and six 32/64-bit
Wide GPTM blocks with the following functional options:
■ 16/32-bit operating modes:
– 16- or 32-bit programmable one-shot timer
– 16- or 32-bit programmable periodic timer
– 16-bit general-purpose timer with an 8-bit prescaler
– 32-bit Real-Time Clock (RTC) when using an external 32.768-KHz clock as the input
– 16-bit input-edge count- or time-capture modes with an 8-bit prescaler
– 16-bit PWM mode with an 8-bit prescaler and software-programmable output inversion of the
PWM signal
■ 32/64-bit operating modes:
– 32- or 64-bit programmable one-shot timer
– 32- or 64-bit programmable periodic timer
– 32-bit general-purpose timer with a 16-bit prescaler
– 64-bit Real-Time Clock (RTC) when using an external 32.768-KHz clock as the input
– 32-bit input-edge count- or time-capture modes with a16-bit prescaler
– 32-bit PWM mode with a 16-bit prescaler and software-programmable output inversion of the
PWM signal
■ Count up or down
■ Twelve 16/32-bit Capture Compare PWM pins (CCP)
■ Twelve 32/64-bit Capture Compare PWM pins (CCP)
■ Daisy chaining of timer modules to allow a single timer to initiate multiple timing events
■ Timer synchronization allows selected timers to start counting on the same clock cycle
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■ ADC event trigger
■ User-enabled stalling when the microcontroller asserts CPU Halt flag during debug (excluding
RTC mode)
■ Ability to determine the elapsed time between the assertion of the timer interrupt and entry into
the interrupt service routine
■ Efficient transfers using Micro Direct Memory Access Controller (µDMA)
– Dedicated channel for each timer
– Burst request generated on timer interrupt
1.3.4.4
CCP Pins (see page 633)
Capture Compare PWM pins (CCP) can be used by the General-Purpose Timer Module to time/count
external events using the CCP pin as an input. Alternatively, the GPTM can generate a simple PWM
output on the CCP pin.
The TM4C1230C3PM microcontroller includes twelve 16/32-bit CCP pins that can be programmed
to operate in the following modes:
■ Capture: The GP Timer is incremented/decremented by programmed events on the CCP input.
The GP Timer captures and stores the current timer value when a programmed event occurs.
■ Compare: The GP Timer is incremented/decremented by programmed events on the CCP input.
The GP Timer compares the current value with a stored value and generates an interrupt when
a match occurs.
■ PWM: The GP Timer is incremented/decremented by the system clock. A PWM signal is generated
based on a match between the counter value and a value stored in a match register and is output
on the CCP pin.
1.3.4.5
Watchdog Timers (see page 695)
A watchdog timer is used to regain control when a system has failed due to a software error or to
the failure of an external device to respond in the expected way. The TM4C1230C3PM Watchdog
Timer can generate an interrupt, a non-maskable interrupt, or a reset when a time-out value is
reached. In addition, the Watchdog Timer is ARM FiRM-compliant and can be configured to generate
an interrupt to the microcontroller on its first time-out, and to generate a reset signal on its second
timeout. Once the Watchdog Timer has been configured, the lock register can be written to prevent
the timer configuration from being inadvertently altered.
The TM4C1230C3PM microcontroller has two Watchdog Timer modules: Watchdog Timer 0 uses
the system clock for its timer clock; Watchdog Timer 1 uses the PIOSC as its timer clock. The
Watchdog Timer module has the following features:
■ 32-bit down counter with a programmable load register
■ Separate watchdog clock with an enable
■ Programmable interrupt generation logic with interrupt masking and optional NMI function
■ Lock register protection from runaway software
■ Reset generation logic with an enable/disable
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■ User-enabled stalling when the microcontroller asserts the CPU Halt flag during debug
1.3.4.6
Programmable GPIOs (see page 570)
General-purpose input/output (GPIO) pins offer flexibility for a variety of connections. The
TM4C1230C3PM GPIO module is comprised of seven physical GPIO blocks, each corresponding
to an individual GPIO port. The GPIO module is FiRM-compliant (compliant to the ARM Foundation
IP for Real-Time Microcontrollers specification) and supports 0-49 programmable input/output pins.
The number of GPIOs available depends on the peripherals being used (see “Signal
Tables” on page 1032 for the signals available to each GPIO pin).
■ Up to 49 GPIOs, depending on configuration
■ Highly flexible pin muxing allows use as GPIO or one of several peripheral functions
■ 5-V-tolerant in input configuration
■ Ports A-G accessed through the Advanced Peripheral Bus (APB)
■ Fast toggle capable of a change every clock cycle for ports on AHB, every two clock cycles for
ports on APB
■ Programmable control for GPIO interrupts
– Interrupt generation masking
– Edge-triggered on rising, falling, or both
– Level-sensitive on High or Low values
■ Bit masking in both read and write operations through address lines
■ Can be used to initiate an ADC sample sequence or a μDMA transfer
■ Pins configured as digital inputs are Schmitt-triggered
■ Programmable control for GPIO pad configuration
– Weak pull-up or pull-down resistors
– 2-mA, 4-mA, and 8-mA pad drive for digital communication; up to four pads can sink 18-mA
for high-current applications
– Slew rate control for 8-mA pad drive
– Open drain enables
– Digital input enables
1.3.5
Analog
The TM4C1230C3PM microcontroller provides analog functions integrated into the device, including:
■ Two 12-bit Analog-to-Digital Converters (ADC), with a total of 12 analog input channels and each
with a sample rate of one million samples/second
■ Two analog comparators
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■ On-chip voltage regulator
The following provides more detail on these analog functions.
1.3.5.1
ADC (see page 720)
An analog-to-digital converter (ADC) is a peripheral that converts a continuous analog voltage to a
discrete digital number. The TM4C1230C3PM ADC module features 12-bit conversion resolution
and supports 12 input channels plus an internal temperature sensor. Four buffered sample
sequencers allow rapid sampling of up to 12 analog input sources without controller intervention.
Each sample sequencer provides flexible programming with fully configurable input source, trigger
events, interrupt generation, and sequencer priority. Each ADC module has a digital comparator
function that allows the conversion value to be diverted to a comparison unit that provides eight
digital comparators.
The TM4C1230C3PM microcontroller provides two ADC modules, each with the following features:
■ 12 shared analog input channels
■ 12-bit precision ADC
■ Single-ended and differential-input configurations
■ On-chip internal temperature sensor
■ Maximum sample rate of one million samples/second
■ Optional phase shift in sample time programmable from 22.5º to 337.5º
■ Four programmable sample conversion sequencers from one to eight entries long, with
corresponding conversion result FIFOs
■ Flexible trigger control
– Controller (software)
– Timers
– Analog Comparators
– GPIO
■ Hardware averaging of up to 64 samples
■ Eight digital comparators
■ Power and ground for the analog circuitry is separate from the digital power and ground
■ Efficient transfers using Micro Direct Memory Access Controller (µDMA)
– Dedicated channel for each sample sequencer
– ADC module uses burst requests for DMA
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1.3.5.2
Analog Comparators (see page 1016)
An analog comparator is a peripheral that compares two analog voltages and provides a logical
output that signals the comparison result. The TM4C1230C3PM microcontroller provides two
independent integrated analog comparators that can be configured to drive an output or generate
an interrupt or ADC event.
The comparator can provide its output to a device pin, acting as a replacement for an analog
comparator on the board, or it can be used to signal the application via interrupts or triggers to the
ADC to cause it to start capturing a sample sequence. The interrupt generation and ADC triggering
logic is separate. This means, for example, that an interrupt can be generated on a rising edge and
the ADC triggered on a falling edge.
The TM4C1230C3PM microcontroller provides two independent integrated analog comparators
with the following functions:
■ Compare external pin input to external pin input or to internal programmable voltage reference
■ Compare a test voltage against any one of the following voltages:
– An individual external reference voltage
– A shared single external reference voltage
– A shared internal reference voltage
1.3.6
JTAG and ARM Serial Wire Debug (see page 186)
The Joint Test Action Group (JTAG) port is an IEEE standard that defines a Test Access Port and
Boundary Scan Architecture for digital integrated circuits and provides a standardized serial interface
for controlling the associated test logic. The TAP, Instruction Register (IR), and Data Registers (DR)
can be used to test the interconnections of assembled printed circuit boards and obtain manufacturing
information on the components. The JTAG Port also provides a means of accessing and controlling
design-for-test features such as I/O pin observation and control, scan testing, and debugging. Texas
Instruments replaces the ARM SW-DP and JTAG-DP with the ARM Serial Wire JTAG Debug Port
(SWJ-DP) interface. The SWJ-DP interface combines the SWD and JTAG debug ports into one
module providing all the normal JTAG debug and test functionality plus real-time access to system
memory without halting the core or requiring any target resident code. The SWJ-DP interface has
the following features:
■ IEEE 1149.1-1990 compatible Test Access Port (TAP) controller
■ Four-bit Instruction Register (IR) chain for storing JTAG instructions
■ IEEE standard instructions: BYPASS, IDCODE, SAMPLE/PRELOAD, and EXTEST
■ ARM additional instructions: APACC, DPACC and ABORT
■ Integrated ARM Serial Wire Debug (SWD)
– Serial Wire JTAG Debug Port (SWJ-DP)
– Flash Patch and Breakpoint (FPB) unit for implementing breakpoints
– Data Watchpoint and Trace (DWT) unit for implementing watchpoints, trigger resources, and
system profiling
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– Instrumentation Trace Macrocell (ITM) for support of printf style debugging
– Embedded Trace Macrocell (ETM) for instruction trace capture
– Trace Port Interface Unit (TPIU) for bridging to a Trace Port Analyzer
1.3.7
Packaging and Temperature
■ 64-pin RoHS-compliant LQFP package
■ Industrial (-40°C to 85°C) ambient temperature range
1.4
TM4C1230C3PM Microcontroller Hardware Details
Details on the pins and package can be found in the following sections:
■ “Pin Diagram” on page 1031
■ “Signal Tables” on page 1032
■ “Electrical Characteristics” on page 1055
■ “Package Information” on page 1096
1.5
Kits
The Tiva™ C Series provides the hardware and software tools that engineers need to begin
development quickly.
■ Reference Design Kits accelerate product development by providing ready-to-run hardware and
comprehensive documentation including hardware design files
■ Evaluation Kits provide a low-cost and effective means of evaluating TM4C1230C3PM
microcontrollers before purchase
■ Development Kits provide you with all the tools you need to develop and prototype embedded
applications right out of the box
See the Tiva series website at http://www.ti.com/tiva-c for the latest tools available, or ask your
distributor.
1.6
Support Information
For support on Tiva™ C Series products, contact the TI Worldwide Product Information Center
nearest you.
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2
The Cortex-M4F Processor
The ARM® Cortex™-M4F processor provides a high-performance, low-cost platform that meets the
system requirements of minimal memory implementation, reduced pin count, and low power
consumption, while delivering outstanding computational performance and exceptional system
response to interrupts. Features include:
®
■ 32-bit ARM Cortex™-M4F architecture optimized for small-footprint embedded applications
■ 80-MHz operation; 100 DMIPS performance
■ Outstanding processing performance combined with fast interrupt handling
■ Thumb-2 mixed 16-/32-bit instruction set delivers the high performance expected of a 32-bit
ARM core in a compact memory size usually associated with 8- and 16-bit devices, typically in
the range of a few kilobytes of memory for microcontroller-class applications
– Single-cycle multiply instruction and hardware divide
– Atomic bit manipulation (bit-banding), delivering maximum memory utilization and streamlined
peripheral control
– Unaligned data access, enabling data to be efficiently packed into memory
■ IEEE754-compliant single-precision Floating-Point Unit (FPU)
■ 16-bit SIMD vector processing unit
■ Fast code execution permits slower processor clock or increases sleep mode time
■ Harvard architecture characterized by separate buses for instruction and data
■ Efficient processor core, system and memories
■ Hardware division and fast digital-signal-processing orientated multiply accumulate
■ Saturating arithmetic for signal processing
■ Deterministic, high-performance interrupt handling for time-critical applications
■ Memory protection unit (MPU) to provide a privileged mode for protected operating system
functionality
■ Enhanced system debug with extensive breakpoint and trace capabilities
■ Serial Wire Debug and Serial Wire Trace reduce the number of pins required for debugging and
tracing
■ Migration from the ARM7™ processor family for better performance and power efficiency
■ Optimized for single-cycle Flash memory usage up to specific frequencies; see “Internal
Memory” on page 446 for more information.
■ Ultra-low power consumption with integrated sleep modes
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The Cortex-M4F Processor
The Tiva™ C Series microcontrollers builds on this core to bring high-performance 32-bit computing
to
This chapter provides information on the Tiva™ C Series implementation of the Cortex-M4F
processor, including the programming model, the memory model, the exception model, fault handling,
and power management.
For technical details on the instruction set, see the Cortex™-M4 instruction set chapter in the ARM®
Cortex™-M4 Devices Generic User Guide (literature number ARM DUI 0553A).
2.1
Block Diagram
The Cortex-M4F processor is built on a high-performance processor core, with a 3-stage pipeline
Harvard architecture, making it ideal for demanding embedded applications. The processor delivers
exceptional power efficiency through an efficient instruction set and extensively optimized design,
providing high-end processing hardware including IEEE754-compliant single-precision floating-point
computation, a range of single-cycle and SIMD multiplication and multiply-with-accumulate
capabilities, saturating arithmetic and dedicated hardware division.
To facilitate the design of cost-sensitive devices, the Cortex-M4F processor implements tightly
coupled system components that reduce processor area while significantly improving interrupt
handling and system debug capabilities. The Cortex-M4F processor implements a version of the
Thumb® instruction set based on Thumb-2 technology, ensuring high code density and reduced
program memory requirements. The Cortex-M4F instruction set provides the exceptional performance
expected of a modern 32-bit architecture, with the high code density of 8-bit and 16-bit
microcontrollers.
The Cortex-M4F processor closely integrates a nested interrupt controller (NVIC), to deliver
industry-leading interrupt performance. The TM4C1230C3PM NVIC includes a non-maskable
interrupt (NMI) and provides eight interrupt priority levels. The tight integration of the processor core
and NVIC provides fast execution of interrupt service routines (ISRs), dramatically reducing interrupt
latency. The hardware stacking of registers and the ability to suspend load-multiple and store-multiple
operations further reduce interrupt latency. Interrupt handlers do not require any assembler stubs
which removes code overhead from the ISRs. Tail-chaining optimization also significantly reduces
the overhead when switching from one ISR to another. To optimize low-power designs, the NVIC
integrates with the sleep modes, including Deep-sleep mode, which enables the entire device to be
rapidly powered down.
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Figure 2-1. CPU Block Diagram
Nested
Vectored
Interrupt
Controller
FPU
Interrupts
Sleep
ARM
Cortex-M4F
CM4 Core
Debug
Instructions
Data
Embedded
Trace
Macrocell
Memory
Protection
Unit
Flash
Patch and
Breakpoint
Instrumentation
Data
Watchpoint Trace Macrocell
and Trace
ROM
Table
Private Peripheral
Bus
(internal)
Adv. Peripheral
Bus
Bus
Matrix
Serial Wire JTAG
Debug Port
Debug
Access Port
2.2
Overview
2.2.1
System-Level Interface
Trace
Port
Interface
Unit
Serial
Wire
Output
Trace
Port
(SWO)
I-code bus
D-code bus
System bus
The Cortex-M4F processor provides multiple interfaces using AMBA® technology to provide
high-speed, low-latency memory accesses. The core supports unaligned data accesses and
implements atomic bit manipulation that enables faster peripheral controls, system spinlocks, and
thread-safe Boolean data handling.
The Cortex-M4F processor has a memory protection unit (MPU) that provides fine-grain memory
control, enabling applications to implement security privilege levels and separate code, data and
stack on a task-by-task basis.
2.2.2
Integrated Configurable Debug
The Cortex-M4F processor implements a complete hardware debug solution, providing high system
visibility of the processor and memory through either a traditional JTAG port or a 2-pin Serial Wire
Debug (SWD) port that is ideal for microcontrollers and other small package devices. The Tiva™
C Series implementation replaces the ARM SW-DP and JTAG-DP with the ARM
CoreSight™-compliant Serial Wire JTAG Debug Port (SWJ-DP) interface. The SWJ-DP interface
combines the SWD and JTAG debug ports into one module. See the ARM® Debug Interface V5
Architecture Specification for details on SWJ-DP.
For system trace, the processor integrates an Instrumentation Trace Macrocell (ITM) alongside data
watchpoints and a profiling unit. To enable simple and cost-effective profiling of the system trace
events, a Serial Wire Viewer (SWV) can export a stream of software-generated messages, data
trace, and profiling information through a single pin.
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The Embedded Trace Macrocell (ETM) delivers unrivaled instruction trace capture in an area smaller
than traditional trace units, enabling full instruction trace. For more details on the ARM ETM, see
the ARM® Embedded Trace Macrocell Architecture Specification.
The Flash Patch and Breakpoint Unit (FPB) provides up to eight hardware breakpoint comparators
that debuggers can use. The comparators in the FPB also provide remap functions for up to eight
words of program code in the code memory region. This FPB enables applications stored in a
read-only area of Flash memory to be patched in another area of on-chip SRAM or Flash memory.
If a patch is required, the application programs the FPB to remap a number of addresses. When
those addresses are accessed, the accesses are redirected to a remap table specified in the FPB
configuration.
For more information on the Cortex-M4F debug capabilities, see theARM® Debug Interface V5
Architecture Specification.
2.2.3
Trace Port Interface Unit (TPIU)
The TPIU acts as a bridge between the Cortex-M4F trace data from the ITM, and an off-chip Trace
Port Analyzer, as shown in Figure 2-2 on page 58.
Figure 2-2. TPIU Block Diagram
2.2.4
Debug
ATB
Slave
Port
ARM® Trace
Bus (ATB)
Interface
APB
Slave
Port
Advance
Peripheral
Bus (APB)
Interface
Asynchronous FIFO
Trace Out
(serializer)
Serial Wire
Trace Port
(SWO)
Cortex-M4F System Component Details
The Cortex-M4F includes the following system components:
■ SysTick
A 24-bit count-down timer that can be used as a Real-Time Operating System (RTOS) tick timer
or as a simple counter (see “System Timer (SysTick)” on page 109).
■ Nested Vectored Interrupt Controller (NVIC)
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An embedded interrupt controller that supports low latency interrupt processing (see “Nested
Vectored Interrupt Controller (NVIC)” on page 110).
■ System Control Block (SCB)
The programming model interface to the processor. The SCB provides system implementation
information and system control, including configuration, control, and reporting of system exceptions
(see “System Control Block (SCB)” on page 111).
■ Memory Protection Unit (MPU)
Improves system reliability by defining the memory attributes for different memory regions. The
MPU provides up to eight different regions and an optional predefined background region (see
“Memory Protection Unit (MPU)” on page 111).
■ Floating-Point Unit (FPU)
Fully supports single-precision add, subtract, multiply, divide, multiply and accumulate, and
square-root operations. It also provides conversions between fixed-point and floating-point data
formats, and floating-point constant instructions (see “Floating-Point Unit (FPU)” on page 116).
2.3
Programming Model
This section describes the Cortex-M4F programming model. In addition to the individual core register
descriptions, information about the processor modes and privilege levels for software execution and
stacks is included.
2.3.1
Processor Mode and Privilege Levels for Software Execution
The Cortex-M4F has two modes of operation:
■ Thread mode
Used to execute application software. The processor enters Thread mode when it comes out of
reset.
■ Handler mode
Used to handle exceptions. When the processor has finished exception processing, it returns to
Thread mode.
In addition, the Cortex-M4F has two privilege levels:
■ Unprivileged
In this mode, software has the following restrictions:
– Limited access to the MSR and MRS instructions and no use of the CPS instruction
– No access to the system timer, NVIC, or system control block
– Possibly restricted access to memory or peripherals
■ Privileged
In this mode, software can use all the instructions and has access to all resources.
In Thread mode, the CONTROL register (see page 74) controls whether software execution is
privileged or unprivileged. In Handler mode, software execution is always privileged.
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Only privileged software can write to the CONTROL register to change the privilege level for software
execution in Thread mode. Unprivileged software can use the SVC instruction to make a supervisor
call to transfer control to privileged software.
2.3.2
Stacks
The processor uses a full descending stack, meaning that the stack pointer indicates the last stacked
item on the memory. When the processor pushes a new item onto the stack, it decrements the stack
pointer and then writes the item to the new memory location. The processor implements two stacks:
the main stack and the process stack, with a pointer for each held in independent registers (see the
SP register on page 64).
In Thread mode, the CONTROL register (see page 74) controls whether the processor uses the
main stack or the process stack. In Handler mode, the processor always uses the main stack. The
options for processor operations are shown in Table 2-1 on page 60.
Table 2-1. Summary of Processor Mode, Privilege Level, and Stack Use
Processor Mode
Use
Privilege Level
Thread
Applications
Privileged or unprivileged
Handler
Exception handlers
Always privileged
Stack Used
a
Main stack or process stack
a
Main stack
a. See CONTROL (page 74).
2.3.3
Register Map
Figure 2-3 on page 61 shows the Cortex-M4F register set. Table 2-2 on page 61 lists the Core
registers. The core registers are not memory mapped and are accessed by register name, so the
base address is n/a (not applicable) and there is no offset.
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Figure 2-3. Cortex-M4F Register Set
R0
R1
R2
R3
Low registers
R4
R5
General-purpose registers
R6
R7
R8
R9
High registers
R10
R11
R12
Stack Pointer
SP (R13)
Link Register
LR (R14)
Program Counter
PC (R15)
PSP‡
PSR
MSP‡
‡
Banked version of SP
Program status register
PRIMASK
FAULTMASK
Exception mask registers
Special registers
BASEPRI
CONTROL
CONTROL register
Table 2-2. Processor Register Map
Offset
Name
Type
Reset
Description
See
page
-
R0
RW
-
Cortex General-Purpose Register 0
63
-
R1
RW
-
Cortex General-Purpose Register 1
63
-
R2
RW
-
Cortex General-Purpose Register 2
63
-
R3
RW
-
Cortex General-Purpose Register 3
63
-
R4
RW
-
Cortex General-Purpose Register 4
63
-
R5
RW
-
Cortex General-Purpose Register 5
63
-
R6
RW
-
Cortex General-Purpose Register 6
63
-
R7
RW
-
Cortex General-Purpose Register 7
63
-
R8
RW
-
Cortex General-Purpose Register 8
63
-
R9
RW
-
Cortex General-Purpose Register 9
63
-
R10
RW
-
Cortex General-Purpose Register 10
63
-
R11
RW
-
Cortex General-Purpose Register 11
63
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Table 2-2. Processor Register Map (continued)
Offset
Name
Type
Reset
Description
See
page
-
R12
RW
-
Cortex General-Purpose Register 12
63
-
SP
RW
-
Stack Pointer
64
-
LR
RW
0xFFFF.FFFF
Link Register
65
-
PC
RW
-
Program Counter
66
-
PSR
RW
0x0100.0000
Program Status Register
67
-
PRIMASK
RW
0x0000.0000
Priority Mask Register
71
-
FAULTMASK
RW
0x0000.0000
Fault Mask Register
72
-
BASEPRI
RW
0x0000.0000
Base Priority Mask Register
73
-
CONTROL
RW
0x0000.0000
Control Register
74
-
FPSC
RW
-
Floating-Point Status Control
76
2.3.4
Register Descriptions
This section lists and describes the Cortex-M4F registers, in the order shown in Figure
2-3 on page 61. The core registers are not memory mapped and are accessed by register name
rather than offset.
Note:
The register type shown in the register descriptions refers to type during program execution
in Thread mode and Handler mode. Debug access can differ.
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Register 1: Cortex General-Purpose Register 0 (R0)
Register 2: Cortex General-Purpose Register 1 (R1)
Register 3: Cortex General-Purpose Register 2 (R2)
Register 4: Cortex General-Purpose Register 3 (R3)
Register 5: Cortex General-Purpose Register 4 (R4)
Register 6: Cortex General-Purpose Register 5 (R5)
Register 7: Cortex General-Purpose Register 6 (R6)
Register 8: Cortex General-Purpose Register 7 (R7)
Register 9: Cortex General-Purpose Register 8 (R8)
Register 10: Cortex General-Purpose Register 9 (R9)
Register 11: Cortex General-Purpose Register 10 (R10)
Register 12: Cortex General-Purpose Register 11 (R11)
Register 13: Cortex General-Purpose Register 12 (R12)
The Rn registers are 32-bit general-purpose registers for data operations and can be accessed
from either privileged or unprivileged mode.
Cortex General-Purpose Register 0 (R0)
Type RW, reset 31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
RW
-
RW
-
RW
-
RW
-
RW
-
RW
-
RW
-
RW
-
RW
-
RW
-
RW
-
RW
-
RW
-
RW
-
RW
-
RW
-
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
RW
-
RW
-
RW
-
RW
-
RW
-
RW
-
RW
-
RW
-
RW
-
RW
-
RW
-
RW
-
RW
-
RW
-
RW
-
RW
-
DATA
Type
Reset
DATA
Type
Reset
Bit/Field
Name
Type
Reset
31:0
DATA
RW
-
Description
Register data.
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Register 14: Stack Pointer (SP)
The Stack Pointer (SP) is register R13. In Thread mode, the function of this register changes
depending on the ASP bit in the Control Register (CONTROL) register. When the ASP bit is clear,
this register is the Main Stack Pointer (MSP). When the ASP bit is set, this register is the Process
Stack Pointer (PSP). On reset, the ASP bit is clear, and the processor loads the MSP with the value
from address 0x0000.0000. The MSP can only be accessed in privileged mode; the PSP can be
accessed in either privileged or unprivileged mode.
Stack Pointer (SP)
Type RW, reset 31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
RW
-
RW
-
RW
-
RW
-
RW
-
RW
-
RW
-
RW
-
RW
-
RW
-
RW
-
RW
-
RW
-
RW
-
RW
-
RW
-
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
RW
-
RW
-
RW
-
RW
-
RW
-
RW
-
RW
-
RW
-
RW
-
RW
-
RW
-
RW
-
RW
-
RW
-
RW
-
RW
-
SP
Type
Reset
SP
Type
Reset
Bit/Field
Name
Type
Reset
31:0
SP
RW
-
Description
This field is the address of the stack pointer.
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Register 15: Link Register (LR)
The Link Register (LR) is register R14, and it stores the return information for subroutines, function
calls, and exceptions. The Link Register can be accessed from either privileged or unprivileged
mode.
EXC_RETURN is loaded into the LR on exception entry. See Table 2-10 on page 97 for the values
and description.
Link Register (LR)
Type RW, reset 0xFFFF.FFFF
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
RW
1
RW
1
RW
1
RW
1
RW
1
RW
1
RW
1
RW
1
7
6
5
4
3
2
1
0
RW
1
RW
1
RW
1
RW
1
RW
1
RW
1
RW
1
RW
1
LINK
Type
Reset
RW
1
RW
1
RW
1
RW
1
RW
1
RW
1
RW
1
RW
1
15
14
13
12
11
10
9
8
LINK
Type
Reset
RW
1
RW
1
RW
1
RW
1
RW
1
RW
1
Bit/Field
Name
Type
31:0
LINK
RW
RW
1
Reset
RW
1
Description
0xFFFF.FFFF This field is the return address.
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Register 16: Program Counter (PC)
The Program Counter (PC) is register R15, and it contains the current program address. On reset,
the processor loads the PC with the value of the reset vector, which is at address 0x0000.0004. Bit
0 of the reset vector is loaded into the THUMB bit of the EPSR at reset and must be 1. The PC register
can be accessed in either privileged or unprivileged mode.
Program Counter (PC)
Type RW, reset 31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
RW
-
RW
-
RW
-
RW
-
RW
-
RW
-
RW
-
RW
-
RW
-
RW
-
RW
-
RW
-
RW
-
RW
-
RW
-
RW
-
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
RW
-
RW
-
RW
-
RW
-
RW
-
RW
-
RW
-
RW
-
RW
-
RW
-
RW
-
RW
-
RW
-
RW
-
RW
-
RW
-
PC
Type
Reset
PC
Type
Reset
Bit/Field
Name
Type
Reset
31:0
PC
RW
-
Description
This field is the current program address.
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Register 17: Program Status Register (PSR)
Note:
This register is also referred to as xPSR.
The Program Status Register (PSR) has three functions, and the register bits are assigned to the
different functions:
■ Application Program Status Register (APSR), bits 31:27, bits 19:16
■ Execution Program Status Register (EPSR), bits 26:24, 15:10
■ Interrupt Program Status Register (IPSR), bits 7:0
The PSR, IPSR, and EPSR registers can only be accessed in privileged mode; the APSR register
can be accessed in either privileged or unprivileged mode.
APSR contains the current state of the condition flags from previous instruction executions.
EPSR contains the Thumb state bit and the execution state bits for the If-Then (IT) instruction or
the Interruptible-Continuable Instruction (ICI) field for an interrupted load multiple or store multiple
instruction. Attempts to read the EPSR directly through application software using the MSR instruction
always return zero. Attempts to write the EPSR using the MSR instruction in application software
are always ignored. Fault handlers can examine the EPSR value in the stacked PSR to determine
the operation that faulted (see “Exception Entry and Return” on page 94).
IPSR contains the exception type number of the current Interrupt Service Routine (ISR).
These registers can be accessed individually or as a combination of any two or all three registers,
using the register name as an argument to the MSR or MRS instructions. For example, all of the
registers can be read using PSR with the MRS instruction, or APSR only can be written to using
APSR with the MSR instruction. page 67 shows the possible register combinations for the PSR. See
the MRS and MSR instruction descriptions in the Cortex™-M4 instruction set chapter in the ARM®
Cortex™-M4 Devices Generic User Guide (literature number ARM DUI 0553A) for more information
about how to access the program status registers.
Table 2-3. PSR Register Combinations
Register
Type
PSR
RW
Combination
APSR, EPSR, and IPSR
IEPSR
RO
EPSR and IPSR
a, b
a
APSR and IPSR
b
APSR and EPSR
IAPSR
RW
EAPSR
RW
a. The processor ignores writes to the IPSR bits.
b. Reads of the EPSR bits return zero, and the processor ignores writes to these bits.
Program Status Register (PSR)
Type RW, reset 0x0100.0000
Type
Reset
31
30
29
28
27
N
Z
C
V
Q
26
RW
0
RW
0
RW
0
RW
0
RW
0
RO
0
RO
0
RO
1
RO
0
RO
0
RO
0
RO
0
RW
0
15
14
13
12
11
10
9
8
7
6
5
4
ICI / IT
Type
Reset
RO
0
RO
0
RO
0
25
ICI / IT
24
23
22
THUMB
21
RO
0
RO
0
RO
0
RO
0
19
18
17
16
RW
0
RW
0
RW
0
3
2
1
0
RO
0
RO
0
RO
0
RO
0
GE
reserved
RO
0
20
reserved
ISRNUM
RO
0
RO
0
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0
RO
0
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Bit/Field
Name
Type
Reset
31
N
RW
0
Description
APSR Negative or Less Flag
Value Description
1
The previous operation result was negative or less than.
0
The previous operation result was positive, zero, greater than,
or equal.
The value of this bit is only meaningful when accessing PSR or APSR.
30
Z
RW
0
APSR Zero Flag
Value Description
1
The previous operation result was zero.
0
The previous operation result was non-zero.
The value of this bit is only meaningful when accessing PSR or APSR.
29
C
RW
0
APSR Carry or Borrow Flag
Value Description
1
The previous add operation resulted in a carry bit or the previous
subtract operation did not result in a borrow bit.
0
The previous add operation did not result in a carry bit or the
previous subtract operation resulted in a borrow bit.
The value of this bit is only meaningful when accessing PSR or APSR.
28
V
RW
0
APSR Overflow Flag
Value Description
1
The previous operation resulted in an overflow.
0
The previous operation did not result in an overflow.
The value of this bit is only meaningful when accessing PSR or APSR.
27
Q
RW
0
APSR DSP Overflow and Saturation Flag
Value Description
1
DSP Overflow or saturation has occurred when using a SIMD
instruction.
0
DSP overflow or saturation has not occurred since reset or since
the bit was last cleared.
The value of this bit is only meaningful when accessing PSR or APSR.
This bit is cleared by software using an MRS instruction.
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Bit/Field
Name
Type
Reset
26:25
ICI / IT
RO
0x0
Description
EPSR ICI / IT status
These bits, along with bits 15:10, contain the Interruptible-Continuable
Instruction (ICI) field for an interrupted load multiple or store multiple
instruction or the execution state bits of the IT instruction.
When EPSR holds the ICI execution state, bits 26:25 are zero.
The If-Then block contains up to four instructions following an IT
instruction. Each instruction in the block is conditional. The conditions
for the instructions are either all the same, or some can be the inverse
of others. See the Cortex™-M4 instruction set chapter in the ARM®
Cortex™-M4 Devices Generic User Guide (literature number ARM DUI
0553A) for more information.
The value of this field is only meaningful when accessing PSR or EPSR.
Note that these EPSR bits cannot be accessed using MRS and MSR
instructions but the definitions are provided to allow the stacked (E)PSR
value to be decoded within an exception handler.
24
THUMB
RO
1
EPSR Thumb State
This bit indicates the Thumb state and should always be set.
The following can clear the THUMB bit:
■
The BLX, BX and POP{PC} instructions
■
Restoration from the stacked xPSR value on an exception return
■
Bit 0 of the vector value on an exception entry or reset
Attempting to execute instructions when this bit is clear results in a fault
or lockup. See “Lockup” on page 99 for more information.
The value of this bit is only meaningful when accessing PSR or EPSR.
23:20
reserved
RO
0x00
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
19:16
GE
RW
0x0
Greater Than or Equal Flags
See the description of the SEL instruction in the Cortex™-M4 instruction
set chapter in the ARM® Cortex™-M4 Devices Generic User Guide
(literature number ARM DUI 0553A) for more information.
The value of this field is only meaningful when accessing PSR or APSR.
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Bit/Field
Name
Type
Reset
15:10
ICI / IT
RO
0x0
Description
EPSR ICI / IT status
These bits, along with bits 26:25, contain the Interruptible-Continuable
Instruction (ICI) field for an interrupted load multiple or store multiple
instruction or the execution state bits of the IT instruction.
When an interrupt occurs during the execution of an LDM, STM, PUSH
POP, VLDM, VSTM, VPUSH, or VPOP instruction, the processor stops the
load multiple or store multiple instruction operation temporarily and
stores the next register operand in the multiple operation to bits 15:12.
After servicing the interrupt, the processor returns to the register pointed
to by bits 15:12 and resumes execution of the multiple load or store
instruction. When EPSR holds the ICI execution state, bits 11:10 are
zero.
The If-Then block contains up to four instructions following a 16-bit IT
instruction. Each instruction in the block is conditional. The conditions
for the instructions are either all the same, or some can be the inverse
of others. See the Cortex™-M4 instruction set chapter in the ARM®
Cortex™-M4 Devices Generic User Guide (literature number ARM DUI
0553A) for more information.
The value of this field is only meaningful when accessing PSR or EPSR.
9:8
reserved
RO
0x0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
7:0
ISRNUM
RO
0x00
IPSR ISR Number
This field contains the exception type number of the current Interrupt
Service Routine (ISR).
Value
Description
0x00
Thread mode
0x01
Reserved
0x02
NMI
0x03
Hard fault
0x04
Memory management fault
0x05
Bus fault
0x06
Usage fault
0x07-0x0A Reserved
0x0B
SVCall
0x0C
Reserved for Debug
0x0D
Reserved
0x0E
PendSV
0x0F
SysTick
0x10
Interrupt Vector 0
0x11
Interrupt Vector 1
...
...
0x9A
Interrupt Vector 138
See “Exception Types” on page 88 for more information.
The value of this field is only meaningful when accessing PSR or IPSR.
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Register 18: Priority Mask Register (PRIMASK)
The PRIMASK register prevents activation of all exceptions with programmable priority. Reset,
non-maskable interrupt (NMI), and hard fault are the only exceptions with fixed priority. Exceptions
should be disabled when they might impact the timing of critical tasks. This register is only accessible
in privileged mode. The MSR and MRS instructions are used to access the PRIMASK register, and
the CPS instruction may be used to change the value of the PRIMASK register. See the Cortex™-M4
instruction set chapter in the ARM® Cortex™-M4 Devices Generic User Guide (literature number
ARM DUI 0553A) for more information on these instructions. For more information on exception
priority levels, see “Exception Types” on page 88.
Priority Mask Register (PRIMASK)
Type RW, reset 0x0000.0000
31
30
29
28
27
26
25
24
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
8
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
23
22
21
20
19
18
17
16
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
7
6
5
4
3
2
1
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
reserved
Type
Reset
reserved
Type
Reset
Bit/Field
Name
Type
Reset
31:1
reserved
RO
0x0000.000
0
PRIMASK
RW
0
RO
0
PRIMASK
RW
0
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
Priority Mask
Value Description
1
Prevents the activation of all exceptions with configurable
priority.
0
No effect.
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Register 19: Fault Mask Register (FAULTMASK)
The FAULTMASK register prevents activation of all exceptions except for the Non-Maskable Interrupt
(NMI). Exceptions should be disabled when they might impact the timing of critical tasks. This register
is only accessible in privileged mode. The MSR and MRS instructions are used to access the
FAULTMASK register, and the CPS instruction may be used to change the value of the FAULTMASK
register. See the Cortex™-M4 instruction set chapter in the ARM® Cortex™-M4 Devices Generic
User Guide (literature number ARM DUI 0553A) for more information on these instructions. For
more information on exception priority levels, see “Exception Types” on page 88.
Fault Mask Register (FAULTMASK)
Type RW, reset 0x0000.0000
31
30
29
28
27
26
25
24
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
8
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
23
22
21
20
19
18
17
16
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
7
6
5
4
3
2
1
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
reserved
Type
Reset
reserved
Type
Reset
Bit/Field
Name
Type
Reset
31:1
reserved
RO
0x0000.000
0
FAULTMASK
RW
0
RO
0
FAULTMASK
RW
0
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
Fault Mask
Value Description
1
Prevents the activation of all exceptions except for NMI.
0
No effect.
The processor clears the FAULTMASK bit on exit from any exception
handler except the NMI handler.
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Register 20: Base Priority Mask Register (BASEPRI)
The BASEPRI register defines the minimum priority for exception processing. When BASEPRI is
set to a nonzero value, it prevents the activation of all exceptions with the same or lower priority
level as the BASEPRI value. Exceptions should be disabled when they might impact the timing of
critical tasks. This register is only accessible in privileged mode. For more information on exception
priority levels, see “Exception Types” on page 88.
Base Priority Mask Register (BASEPRI)
Type RW, reset 0x0000.0000
31
30
29
28
27
26
25
24
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
23
22
21
20
19
18
17
16
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
8
7
6
5
4
3
2
1
0
RO
0
RW
0
RW
0
RO
0
RO
0
RO
0
RO
0
reserved
Type
Reset
reserved
Type
Reset
BASEPRI
RO
0
Bit/Field
Name
Type
Reset
31:8
reserved
RO
0x0000.00
7:5
BASEPRI
RW
0x0
RW
0
reserved
RO
0
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
Base Priority
Any exception that has a programmable priority level with the same or
lower priority as the value of this field is masked. The PRIMASK register
can be used to mask all exceptions with programmable priority levels.
Higher priority exceptions have lower priority levels.
Value Description
4:0
reserved
RO
0x0
0x0
All exceptions are unmasked.
0x1
All exceptions with priority level 1-7 are masked.
0x2
All exceptions with priority level 2-7 are masked.
0x3
All exceptions with priority level 3-7 are masked.
0x4
All exceptions with priority level 4-7 are masked.
0x5
All exceptions with priority level 5-7 are masked.
0x6
All exceptions with priority level 6-7 are masked.
0x7
All exceptions with priority level 7 are masked.
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
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Register 21: Control Register (CONTROL)
The CONTROL register controls the stack used and the privilege level for software execution when
the processor is in Thread mode, and indicates whether the FPU state is active. This register is only
accessible in privileged mode.
Handler mode always uses the MSP, so the processor ignores explicit writes to the ASP bit of the
CONTROL register when in Handler mode. The exception entry and return mechanisms automatically
update the CONTROL register based on the EXC_RETURN value (see Table 2-10 on page 97).
In an OS environment, threads running in Thread mode should use the process stack and the kernel
and exception handlers should use the main stack. By default, Thread mode uses the MSP. To
switch the stack pointer used in Thread mode to the PSP, either use the MSR instruction to set the
ASP bit, as detailed in the Cortex™-M4 instruction set chapter in the ARM® Cortex™-M4 Devices
Generic User Guide (literature number ARM DUI 0553A), or perform an exception return to Thread
mode with the appropriate EXC_RETURN value, as shown in Table 2-10 on page 97.
Note:
When changing the stack pointer, software must use an ISB instruction immediately after
the MSR instruction, ensuring that instructions after the ISB execute use the new stack
pointer. See the Cortex™-M4 instruction set chapter in the ARM® Cortex™-M4 Devices
Generic User Guide (literature number ARM DUI 0553A).
Control Register (CONTROL)
Type RW, reset 0x0000.0000
31
30
29
28
27
26
25
24
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
23
22
21
20
19
18
17
16
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
8
7
6
5
4
3
2
1
0
FPCA
ASP
TMPL
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RW
0
RW
0
RW
0
reserved
Type
Reset
reserved
Type
Reset
RO
0
Bit/Field
Name
Type
Reset
31:3
reserved
RO
0x0000.000
2
FPCA
RW
0
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
Floating-Point Context Active
Value Description
1
Floating-point context active
0
No floating-point context active
The Cortex-M4F uses this bit to determine whether to preserve
floating-point state when processing an exception.
Important:
Two bits control when FPCA can be enabled: the ASPEN
bit in the Floating-Point Context Control (FPCC)
register and the DISFPCA bit in the Auxiliary Control
(ACTLR) register.
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Bit/Field
Name
Type
Reset
1
ASP
RW
0
Description
Active Stack Pointer
Value Description
1
The PSP is the current stack pointer.
0
The MSP is the current stack pointer
In Handler mode, this bit reads as zero and ignores writes. The
Cortex-M4F updates this bit automatically on exception return.
0
TMPL
RW
0
Thread Mode Privilege Level
Value Description
1
Unprivileged software can be executed in Thread mode.
0
Only privileged software can be executed in Thread mode.
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Register 22: Floating-Point Status Control (FPSC)
The FPSC register provides all necessary user-level control of the floating-point system.
Floating-Point Status Control (FPSC)
Type RW, reset 31
Type
Reset
30
29
28
27
26
25
24
22
21
20
19
RMODE
18
17
16
N
Z
C
V
reserved
AHP
DN
FZ
RW
-
RW
-
RW
-
RW
-
RO
0
RW
-
RW
-
RW
-
RW
-
RW
-
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
IXC
UFC
OFC
DZC
IOC
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RW
-
RW
-
RW
-
RW
-
RW
-
reserved
Type
Reset
23
IDC
RO
0
Bit/Field
Name
Type
Reset
31
N
RW
-
RW
-
reserved
reserved
RO
0
RO
0
Description
Negative Condition Code Flag
Floating-point comparison operations update this condition code flag.
30
Z
RW
-
Zero Condition Code Flag
Floating-point comparison operations update this condition code flag.
29
C
RW
-
Carry Condition Code Flag
Floating-point comparison operations update this condition code flag.
28
V
RW
-
Overflow Condition Code Flag
Floating-point comparison operations update this condition code flag.
27
reserved
RO
0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
26
AHP
RW
-
Alternative Half-Precision
When set, alternative half-precision format is selected. When clear,
IEEE half-precision format is selected.
The AHP bit in the FPDSC register holds the default value for this bit.
25
DN
RW
-
Default NaN Mode
When set, any operation involving one or more NaNs returns the Default
NaN. When clear, NaN operands propagate through to the output of a
floating-point operation.
The DN bit in the FPDSC register holds the default value for this bit.
24
FZ
RW
-
Flush-to-Zero Mode
When set, Flush-to-Zero mode is enabled. When clear, Flush-to-Zero
mode is disabled and the behavior of the floating-point system is fully
compliant with the IEEE 754 standard.
The FZ bit in the FPDSC register holds the default value for this bit.
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Bit/Field
Name
Type
Reset
23:22
RMODE
RW
-
Description
Rounding Mode
The specified rounding mode is used by almost all floating-point
instructions.
The RMODE bit in the FPDSC register holds the default value for this bit.
Value Description
21:8
reserved
RO
0x0
7
IDC
RW
-
0x0
Round to Nearest (RN) mode
0x1
Round towards Plus Infinity (RP) mode
0x2
Round towards Minus Infinity (RM) mode
0x3
Round towards Zero (RZ) mode
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
Input Denormal Cumulative Exception
When set, indicates this exception has occurred since 0 was last written
to this bit.
6:5
reserved
RO
0x0
4
IXC
RW
-
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
Inexact Cumulative Exception
When set, indicates this exception has occurred since 0 was last written
to this bit.
3
UFC
RW
-
Underflow Cumulative Exception
When set, indicates this exception has occurred since 0 was last written
to this bit.
2
OFC
RW
-
Overflow Cumulative Exception
When set, indicates this exception has occurred since 0 was last written
to this bit.
1
DZC
RW
-
Division by Zero Cumulative Exception
When set, indicates this exception has occurred since 0 was last written
to this bit.
0
IOC
RW
-
Invalid Operation Cumulative Exception
When set, indicates this exception has occurred since 0 was last written
to this bit.
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The Cortex-M4F Processor
2.3.5
Exceptions and Interrupts
The Cortex-M4F processor supports interrupts and system exceptions. The processor and the
Nested Vectored Interrupt Controller (NVIC) prioritize and handle all exceptions. An exception
changes the normal flow of software control. The processor uses Handler mode to handle all
exceptions except for reset. See “Exception Entry and Return” on page 94 for more information.
The NVIC registers control interrupt handling. See “Nested Vectored Interrupt Controller
(NVIC)” on page 110 for more information.
2.3.6
Data Types
The Cortex-M4F supports 32-bit words, 16-bit halfwords, and 8-bit bytes. The processor also supports
64-bit data transfer instructions. All instruction and data memory accesses are little endian. See
“Memory Regions, Types and Attributes” on page 80 for more information.
2.4
Memory Model
This section describes the processor memory map, the behavior of memory accesses, and the
bit-banding features. The processor has a fixed memory map that provides up to 4 GB of addressable
memory.
The memory map for the TM4C1230C3PM controller is provided in Table 2-4 on page 78. In this
manual, register addresses are given as a hexadecimal increment, relative to the module's base
address as shown in the memory map.
The regions for SRAM and peripherals include bit-band regions. Bit-banding provides atomic
operations to bit data (see “Bit-Banding” on page 83).
The processor reserves regions of the Private peripheral bus (PPB) address range for core peripheral
registers (see “Cortex-M4 Peripherals” on page 108).
Note:
Within the memory map, attempts to read or write addresses in reserved spaces result in
a bus fault. In addition, attempts to write addresses in the flash range also result in a bus
fault.
Table 2-4. Memory Map
Start
End
Description
For details,
see page ...
0x0000.0000
0x0000.7FFF
On-chip Flash
461
0x0000.8000
0x1FFF.FFFF
Reserved
-
0x2000.0000
0x2000.2FFF
Bit-banded on-chip SRAM
447
0x2000.3000
0x21FF.FFFF
Reserved
-
0x2200.0000
0x2205.FFFF
Bit-band alias of bit-banded on-chip SRAM starting at
0x2000.0000
447
0x2206.0000
0x3FFF.FFFF
Reserved
-
0x4000.0000
0x4000.0FFF
Watchdog timer 0
697
0x4000.1000
0x4000.1FFF
Watchdog timer 1
697
0x4000.2000
0x4000.3FFF
Reserved
-
0x4000.4000
0x4000.4FFF
GPIO Port A
579
0x4000.5000
0x4000.5FFF
GPIO Port B
579
Memory
Peripherals
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Table 2-4. Memory Map (continued)
Start
End
Description
For details,
see page ...
0x4000.6000
0x4000.6FFF
GPIO Port C
579
0x4000.7000
0x4000.7FFF
GPIO Port D
579
0x4000.8000
0x4000.8FFF
SSI0
885
0x4000.9000
0x4000.9FFF
SSI1
885
0x4000.A000
0x4000.AFFF
SSI2
885
0x4000.B000
0x4000.BFFF
SSI3
885
0x4000.C000
0x4000.CFFF
UART0
821
0x4000.D000
0x4000.DFFF
UART1
821
0x4000.E000
0x4000.EFFF
UART2
821
0x4000.F000
0x4000.FFFF
UART3
821
0x4001.0000
0x4001.0FFF
UART4
821
0x4001.1000
0x4001.1FFF
UART5
821
0x4001.2000
0x4001.2FFF
UART6
821
0x4001.3000
0x4001.3FFF
UART7
821
0x4001.4000
0x4001.FFFF
Reserved
-
0x4002.0FFF
I2C 0
935
0x4002.1FFF
I2C
1
935
0x4002.2000
0x4002.2FFF
I2C
2
935
0x4002.3000
0x4002.3FFF
I2C 3
935
0x4002.4000
0x4002.4FFF
GPIO Port E
579
0x4002.5000
0x4002.5FFF
GPIO Port F
579
0x4002.6000
0x4002.6FFF
GPIO Port G
579
0x4002.7000
0x4002.FFFF
Reserved
-
0x4003.0000
0x4003.0FFF
16/32-bit Timer 0
646
0x4003.1000
0x4003.1FFF
16/32-bit Timer 1
646
0x4003.2000
0x4003.2FFF
16/32-bit Timer 2
646
0x4003.3000
0x4003.3FFF
16/32-bit Timer 3
646
0x4003.4000
0x4003.4FFF
16/32-bit Timer 4
646
0x4003.5000
0x4003.5FFF
16/32-bit Timer 5
646
0x4003.6000
0x4003.6FFF
32/64-bit Timer 0
646
0x4003.7000
0x4003.7FFF
32/64-bit Timer 1
646
0x4003.8000
0x4003.8FFF
ADC0
739
0x4003.9000
0x4003.9FFF
ADC1
739
0x4003.A000
0x4003.BFFF
Reserved
-
0x4003.C000
0x4003.CFFF
Analog Comparators
1021
0x4003.D000
0x4003.FFFF
Reserved
-
0x4004.0000
0x4004.0FFF
CAN0 Controller
985
0x4004.1000
0x4004.BFFF
Reserved
-
0x4004.C000
0x4004.CFFF
32/64-bit Timer 2
646
0x4004.D000
0x4004.DFFF
32/64-bit Timer 3
646
Peripherals
0x4002.0000
0x4002.1000
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Table 2-4. Memory Map (continued)
Start
End
Description
For details,
see page ...
0x4004.E000
0x4004.EFFF
32/64-bit Timer 4
646
0x4004.F000
0x4004.FFFF
32/64-bit Timer 5
646
0x4005.0000
0x4005.7FFF
Reserved
-
0x4005.8000
0x4005.8FFF
GPIO Port A (AHB aperture)
579
0x4005.9000
0x4005.9FFF
GPIO Port B (AHB aperture)
579
0x4005.A000
0x4005.AFFF
GPIO Port C (AHB aperture)
579
0x4005.B000
0x4005.BFFF
GPIO Port D (AHB aperture)
579
0x4005.C000
0x4005.CFFF
GPIO Port E (AHB aperture)
579
0x4005.D000
0x4005.DFFF
GPIO Port F (AHB aperture)
579
0x4005.E000
0x4005.EFFF
GPIO Port G (AHB aperture)
579
0x4005.F000
0x400A.EFFF
Reserved
-
0x400A.F000
0x400A.FFFF
EEPROM and Key Locker
461
0x400B.0000
0x400B.FFFF
Reserved
-
0x400C.0000
0x400C.0FFF
I2C 4
935
0x400C.1000
0x400C.1FFF
I2C
935
0x400C.2000
0x400F.8FFF
Reserved
-
0x400F.9000
0x400F.9FFF
System Exception Module
438
0x400F.A000
0x400F.CFFF
Reserved
-
0x400F.D000
0x400F.DFFF
Flash memory control
461
0x400F.E000
0x400F.EFFF
System control
216
0x400F.F000
0x400F.FFFF
µDMA
527
0x4010.0000
0x41FF.FFFF
Reserved
-
0x4200.0000
0x43FF.FFFF
Bit-banded alias of 0x4000.0000 through 0x400F.FFFF
-
0x4400.0000
0xDFFF.FFFF
Reserved
-
0xE000.0000
0xE000.0FFF
Instrumentation Trace Macrocell (ITM)
57
0xE000.1000
0xE000.1FFF
Data Watchpoint and Trace (DWT)
57
0xE000.2000
0xE000.2FFF
Flash Patch and Breakpoint (FPB)
57
0xE000.3000
0xE000.DFFF
Reserved
-
0xE000.E000
0xE000.EFFF
Cortex-M4F Peripherals (SysTick, NVIC, MPU, FPU and SCB) 120
0xE000.F000
0xE003.FFFF
Reserved
-
0xE004.0000
0xE004.0FFF
Trace Port Interface Unit (TPIU)
58
0xE004.1000
0xE004.1FFF
Embedded Trace Macrocell (ETM)
57
0xE004.2000
0xFFFF.FFFF
Reserved
-
5
Private Peripheral Bus
2.4.1
Memory Regions, Types and Attributes
The memory map and the programming of the MPU split the memory map into regions. Each region
has a defined memory type, and some regions have additional memory attributes. The memory
type and attributes determine the behavior of accesses to the region.
The memory types are:
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■ Normal: The processor can re-order transactions for efficiency and perform speculative reads.
■ Device: The processor preserves transaction order relative to other transactions to Device or
Strongly Ordered memory.
■ Strongly Ordered: The processor preserves transaction order relative to all other transactions.
The different ordering requirements for Device and Strongly Ordered memory mean that the memory
system can buffer a write to Device memory but must not buffer a write to Strongly Ordered memory.
An additional memory attribute is Execute Never (XN), which means the processor prevents
instruction accesses. A fault exception is generated only on execution of an instruction executed
from an XN region.
2.4.2
Memory System Ordering of Memory Accesses
For most memory accesses caused by explicit memory access instructions, the memory system
does not guarantee that the order in which the accesses complete matches the program order of
the instructions, providing the order does not affect the behavior of the instruction sequence. Normally,
if correct program execution depends on two memory accesses completing in program order,
software must insert a memory barrier instruction between the memory access instructions (see
“Software Ordering of Memory Accesses” on page 82).
However, the memory system does guarantee ordering of accesses to Device and Strongly Ordered
memory. For two memory access instructions A1 and A2, if both A1 and A2 are accesses to either
Device or Strongly Ordered memory, and if A1 occurs before A2 in program order, A1 is always
observed before A2.
2.4.3
Behavior of Memory Accesses
Table 2-5 on page 81 shows the behavior of accesses to each region in the memory map. See
“Memory Regions, Types and Attributes” on page 80 for more information on memory types and
the XN attribute. Tiva™ C Series devices may have reserved memory areas within the address
ranges shown below (refer to Table 2-4 on page 78 for more information).
Table 2-5. Memory Access Behavior
Address Range
Memory Region
Memory Type
Execute
Never
(XN)
Description
0x0000.0000 - 0x1FFF.FFFF Code
Normal
-
This executable region is for program code.
Data can also be stored here.
0x2000.0000 - 0x3FFF.FFFF SRAM
Normal
-
This executable region is for data. Code
can also be stored here. This region
includes bit band and bit band alias areas
(see Table 2-6 on page 83).
0x4000.0000 - 0x5FFF.FFFF Peripheral
Device
XN
This region includes bit band and bit band
alias areas (see Table 2-7 on page 83).
0x6000.0000 - 0x9FFF.FFFF External RAM
Normal
-
This executable region is for data.
0xA000.0000 - 0xDFFF.FFFF External device
Device
XN
This region is for external device memory.
0xE000.0000- 0xE00F.FFFF Private peripheral
bus
Strongly
Ordered
XN
This region includes the NVIC, system
timer, and system control block.
0xE010.0000- 0xFFFF.FFFF Reserved
-
-
-
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The Code, SRAM, and external RAM regions can hold programs. However, it is recommended that
programs always use the Code region because the Cortex-M4F has separate buses that can perform
instruction fetches and data accesses simultaneously.
The MPU can override the default memory access behavior described in this section. For more
information, see “Memory Protection Unit (MPU)” on page 111.
The Cortex-M4F prefetches instructions ahead of execution and speculatively prefetches from
branch target addresses.
2.4.4
Software Ordering of Memory Accesses
The order of instructions in the program flow does not always guarantee the order of the
corresponding memory transactions for the following reasons:
■ The processor can reorder some memory accesses to improve efficiency, providing this does
not affect the behavior of the instruction sequence.
■ The processor has multiple bus interfaces.
■ Memory or devices in the memory map have different wait states.
■ Some memory accesses are buffered or speculative.
“Memory System Ordering of Memory Accesses” on page 81 describes the cases where the memory
system guarantees the order of memory accesses. Otherwise, if the order of memory accesses is
critical, software must include memory barrier instructions to force that ordering. The Cortex-M4F
has the following memory barrier instructions:
■ The Data Memory Barrier (DMB) instruction ensures that outstanding memory transactions
complete before subsequent memory transactions.
■ The Data Synchronization Barrier (DSB) instruction ensures that outstanding memory transactions
complete before subsequent instructions execute.
■ The Instruction Synchronization Barrier (ISB) instruction ensures that the effect of all completed
memory transactions is recognizable by subsequent instructions.
Memory barrier instructions can be used in the following situations:
■ MPU programming
– If the MPU settings are changed and the change must be effective on the very next instruction,
use a DSB instruction to ensure the effect of the MPU takes place immediately at the end of
context switching.
– Use an ISB instruction to ensure the new MPU setting takes effect immediately after
programming the MPU region or regions, if the MPU configuration code was accessed using
a branch or call. If the MPU configuration code is entered using exception mechanisms, then
an ISB instruction is not required.
■ Vector table
If the program changes an entry in the vector table and then enables the corresponding exception,
use a DMB instruction between the operations. The DMB instruction ensures that if the exception
is taken immediately after being enabled, the processor uses the new exception vector.
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■ Self-modifying code
If a program contains self-modifying code, use an ISB instruction immediately after the code
modification in the program. The ISB instruction ensures subsequent instruction execution uses
the updated program.
■ Memory map switching
If the system contains a memory map switching mechanism, use a DSB instruction after switching
the memory map in the program. The DSB instruction ensures subsequent instruction execution
uses the updated memory map.
■ Dynamic exception priority change
When an exception priority has to change when the exception is pending or active, use DSB
instructions after the change. The change then takes effect on completion of the DSB instruction.
Memory accesses to Strongly Ordered memory, such as the System Control Block, do not require
the use of DMB instructions.
For more information on the memory barrier instructions, see the Cortex™-M4 instruction set chapter
in the ARM® Cortex™-M4 Devices Generic User Guide (literature number ARM DUI 0553A).
2.4.5
Bit-Banding
A bit-band region maps each word in a bit-band alias region to a single bit in the bit-band region.
The bit-band regions occupy the lowest 1 MB of the SRAM and peripheral memory regions. Accesses
to the 32-MB SRAM alias region map to the 1-MB SRAM bit-band region, as shown in Table
2-6 on page 83. Accesses to the 32-MB peripheral alias region map to the 1-MB peripheral bit-band
region, as shown in Table 2-7 on page 83. For the specific address range of the bit-band regions,
see Table 2-4 on page 78.
Note:
A word access to the SRAM or the peripheral bit-band alias region maps to a single bit in
the SRAM or peripheral bit-band region.
A word access to a bit band address results in a word access to the underlying memory,
and similarly for halfword and byte accesses. This allows bit band accesses to match the
access requirements of the underlying peripheral.
Table 2-6. SRAM Memory Bit-Banding Regions
Address Range
Memory Region
Instruction and Data Accesses
Start
End
0x2000.0000
0x2000.2FFF
SRAM bit-band region Direct accesses to this memory range behave as SRAM
memory accesses, but this region is also bit addressable
through bit-band alias.
0x2200.0000
0x2205.FFFF
SRAM bit-band alias
Data accesses to this region are remapped to bit band
region. A write operation is performed as
read-modify-write. Instruction accesses are not remapped.
Table 2-7. Peripheral Memory Bit-Banding Regions
Address Range
Start
End
0x4000.0000
0x400F.FFFF
Memory Region
Instruction and Data Accesses
Peripheral bit-band
region
Direct accesses to this memory range behave as
peripheral memory accesses, but this region is also bit
addressable through bit-band alias.
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Table 2-7. Peripheral Memory Bit-Banding Regions (continued)
Address Range
Memory Region
Start
End
0x4200.0000
0x43FF.FFFF
Instruction and Data Accesses
Peripheral bit-band alias Data accesses to this region are remapped to bit band
region. A write operation is performed as
read-modify-write. Instruction accesses are not permitted.
The following formula shows how the alias region maps onto the bit-band region:
bit_word_offset = (byte_offset x 32) + (bit_number x 4)
bit_word_addr = bit_band_base + bit_word_offset
where:
bit_word_offset
The position of the target bit in the bit-band memory region.
bit_word_addr
The address of the word in the alias memory region that maps to the targeted bit.
bit_band_base
The starting address of the alias region.
byte_offset
The number of the byte in the bit-band region that contains the targeted bit.
bit_number
The bit position, 0-7, of the targeted bit.
Figure 2-4 on page 85 shows examples of bit-band mapping between the SRAM bit-band alias
region and the SRAM bit-band region:
■ The alias word at 0x23FF.FFE0 maps to bit 0 of the bit-band byte at 0x200F.FFFF:
0x23FF.FFE0 = 0x2200.0000 + (0x000F.FFFF*32) + (0*4)
■ The alias word at 0x23FF.FFFC maps to bit 7 of the bit-band byte at 0x200F.FFFF:
0x23FF.FFFC = 0x2200.0000 + (0x000F.FFFF*32) + (7*4)
■ The alias word at 0x2200.0000 maps to bit 0 of the bit-band byte at 0x2000.0000:
0x2200.0000 = 0x2200.0000 + (0*32) + (0*4)
■ The alias word at 0x2200.001C maps to bit 7 of the bit-band byte at 0x2000.0000:
0x2200.001C = 0x2200.0000+ (0*32) + (7*4)
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Figure 2-4. Bit-Band Mapping
32-MB Alias Region
0x23FF.FFFC
0x23FF.FFF8
0x23FF.FFF4
0x23FF.FFF0
0x23FF.FFEC
0x23FF.FFE8
0x23FF.FFE4
0x23FF.FFE0
0x2200.001C
0x2200.0018
0x2200.0014
0x2200.0010
0x2200.000C
0x2200.0008
0x2200.0004
0x2200.0000
7
3
1-MB SRAM Bit-Band Region
7
6
5
4
3
2
1
0
7
6
0x200F.FFFF
7
6
5
4
3
2
0x2000.0003
2.4.5.1
5
4
3
2
1
0
7
6
0x200F.FFFE
1
0
7
6
5
4
3
2
5
4
3
2
1
0
6
0x200F.FFFD
1
0
0x2000.0002
7
6
5
4
3
2
0x2000.0001
5
4
2
1
0
1
0
0x200F.FFFC
1
0
7
6
5
4
3
2
0x2000.0000
Directly Accessing an Alias Region
Writing to a word in the alias region updates a single bit in the bit-band region.
Bit 0 of the value written to a word in the alias region determines the value written to the targeted
bit in the bit-band region. Writing a value with bit 0 set writes a 1 to the bit-band bit, and writing a
value with bit 0 clear writes a 0 to the bit-band bit.
Bits 31:1 of the alias word have no effect on the bit-band bit. Writing 0x01 has the same effect as
writing 0xFF. Writing 0x00 has the same effect as writing 0x0E.
When reading a word in the alias region, 0x0000.0000 indicates that the targeted bit in the bit-band
region is clear and 0x0000.0001 indicates that the targeted bit in the bit-band region is set.
2.4.5.2
Directly Accessing a Bit-Band Region
“Behavior of Memory Accesses” on page 81 describes the behavior of direct byte, halfword, or word
accesses to the bit-band regions.
2.4.6
Data Storage
The processor views memory as a linear collection of bytes numbered in ascending order from zero.
For example, bytes 0-3 hold the first stored word, and bytes 4-7 hold the second stored word. Data
is stored in little-endian format, with the least-significant byte (lsbyte) of a word stored at the
lowest-numbered byte, and the most-significant byte (msbyte) stored at the highest-numbered byte.
Figure 2-5 on page 86 illustrates how data is stored.
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Figure 2-5. Data Storage
Memory
7
Register
0
31
2.4.7
Address A
B0
A+1
B1
A+2
B2
A+3
B3
lsbyte
24 23
B3
16 15
B2
8 7
B1
0
B0
msbyte
Synchronization Primitives
The Cortex-M4F instruction set includes pairs of synchronization primitives which provide a
non-blocking mechanism that a thread or process can use to obtain exclusive access to a memory
location. Software can use these primitives to perform a guaranteed read-modify-write memory
update sequence or for a semaphore mechanism.
A pair of synchronization primitives consists of:
■ A Load-Exclusive instruction, which is used to read the value of a memory location and requests
exclusive access to that location.
■ A Store-Exclusive instruction, which is used to attempt to write to the same memory location and
returns a status bit to a register. If this status bit is clear, it indicates that the thread or process
gained exclusive access to the memory and the write succeeds; if this status bit is set, it indicates
that the thread or process did not gain exclusive access to the memory and no write was
performed.
The pairs of Load-Exclusive and Store-Exclusive instructions are:
■ The word instructions LDREX and STREX
■ The halfword instructions LDREXH and STREXH
■ The byte instructions LDREXB and STREXB
Software must use a Load-Exclusive instruction with the corresponding Store-Exclusive instruction.
To perform an exclusive read-modify-write of a memory location, software must:
1. Use a Load-Exclusive instruction to read the value of the location.
2. Modify the value, as required.
3. Use a Store-Exclusive instruction to attempt to write the new value back to the memory location.
4. Test the returned status bit.
If the status bit is clear, the read-modify-write completed successfully. If the status bit is set, no
write was performed, which indicates that the value returned at step 1 might be out of date. The
software must retry the entire read-modify-write sequence.
Software can use the synchronization primitives to implement a semaphore as follows:
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1. Use a Load-Exclusive instruction to read from the semaphore address to check whether the
semaphore is free.
2. If the semaphore is free, use a Store-Exclusive to write the claim value to the semaphore
address.
3. If the returned status bit from step 2 indicates that the Store-Exclusive succeeded, then the
software has claimed the semaphore. However, if the Store-Exclusive failed, another process
might have claimed the semaphore after the software performed step 1.
The Cortex-M4F includes an exclusive access monitor that tags the fact that the processor has
executed a Load-Exclusive instruction. The processor removes its exclusive access tag if:
■ It executes a CLREX instruction.
■ It executes a Store-Exclusive instruction, regardless of whether the write succeeds.
■ An exception occurs, which means the processor can resolve semaphore conflicts between
different threads.
For more information about the synchronization primitive instructions, see the Cortex™-M4 instruction
set chapter in the ARM® Cortex™-M4 Devices Generic User Guide (literature number ARM DUI
0553A).
2.5
Exception Model
The ARM Cortex-M4F processor and the Nested Vectored Interrupt Controller (NVIC) prioritize and
handle all exceptions in Handler Mode. The processor state is automatically stored to the stack on
an exception and automatically restored from the stack at the end of the Interrupt Service Routine
(ISR). The vector is fetched in parallel to the state saving, enabling efficient interrupt entry. The
processor supports tail-chaining, which enables back-to-back interrupts to be performed without the
overhead of state saving and restoration.
Table 2-8 on page 89 lists all exception types. Software can set eight priority levels on seven of
these exceptions (system handlers) as well as on 66 interrupts (listed in Table 2-9 on page 90).
Priorities on the system handlers are set with the NVIC System Handler Priority n (SYSPRIn)
registers. Interrupts are enabled through the NVIC Interrupt Set Enable n (ENn) register and
prioritized with the NVIC Interrupt Priority n (PRIn) registers. Priorities can be grouped by splitting
priority levels into preemption priorities and subpriorities. All the interrupt registers are described in
“Nested Vectored Interrupt Controller (NVIC)” on page 110.
Internally, the highest user-programmable priority (0) is treated as fourth priority, after a Reset,
Non-Maskable Interrupt (NMI), and a Hard Fault, in that order. Note that 0 is the default priority for
all the programmable priorities.
Important: After a write to clear an interrupt source, it may take several processor cycles for the
NVIC to see the interrupt source deassert. Thus if the interrupt clear is done as the last
action in an interrupt handler, it is possible for the interrupt handler to complete while
the NVIC sees the interrupt as still asserted, causing the interrupt handler to be
re-entered errantly. This situation can be avoided by either clearing the interrupt source
at the beginning of the interrupt handler or by performing a read or write after the write
to clear the interrupt source (and flush the write buffer).
See “Nested Vectored Interrupt Controller (NVIC)” on page 110 for more information on exceptions
and interrupts.
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2.5.1
Exception States
Each exception is in one of the following states:
■ Inactive. The exception is not active and not pending.
■ Pending. The exception is waiting to be serviced by the processor. An interrupt request from a
peripheral or from software can change the state of the corresponding interrupt to pending.
■ Active. An exception that is being serviced by the processor but has not completed.
Note:
An exception handler can interrupt the execution of another exception handler. In this
case, both exceptions are in the active state.
■ Active and Pending. The exception is being serviced by the processor, and there is a pending
exception from the same source.
2.5.2
Exception Types
The exception types are:
■ Reset. Reset is invoked on power up or a warm reset. The exception model treats reset as a
special form of exception. When reset is asserted, the operation of the processor stops, potentially
at any point in an instruction. When reset is deasserted, execution restarts from the address
provided by the reset entry in the vector table. Execution restarts as privileged execution in
Thread mode.
■ NMI. A non-maskable Interrupt (NMI) can be signaled using the NMI signal or triggered by
software using the Interrupt Control and State (INTCTRL) register. This exception has the
highest priority other than reset. NMI is permanently enabled and has a fixed priority of -2. NMIs
cannot be masked or prevented from activation by any other exception or preempted by any
exception other than reset.
■ Hard Fault. A hard fault is an exception that occurs because of an error during exception
processing, or because an exception cannot be managed by any other exception mechanism.
Hard faults have a fixed priority of -1, meaning they have higher priority than any exception with
configurable priority.
■ Memory Management Fault. A memory management fault is an exception that occurs because
of a memory protection related fault, including access violation and no match. The MPU or the
fixed memory protection constraints determine this fault, for both instruction and data memory
transactions. This fault is used to abort instruction accesses to Execute Never (XN) memory
regions, even if the MPU is disabled.
■ Bus Fault. A bus fault is an exception that occurs because of a memory-related fault for an
instruction or data memory transaction such as a prefetch fault or a memory access fault. This
fault can be enabled or disabled.
■ Usage Fault. A usage fault is an exception that occurs because of a fault related to instruction
execution, such as:
– An undefined instruction
– An illegal unaligned access
– Invalid state on instruction execution
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– An error on exception return
An unaligned address on a word or halfword memory access or division by zero can cause a
usage fault when the core is properly configured.
■ SVCall. A supervisor call (SVC) is an exception that is triggered by the SVC instruction. In an
OS environment, applications can use SVC instructions to access OS kernel functions and device
drivers.
■ Debug Monitor. This exception is caused by the debug monitor (when not halting). This exception
is only active when enabled. This exception does not activate if it is a lower priority than the
current activation.
■ PendSV. PendSV is a pendable, interrupt-driven request for system-level service. In an OS
environment, use PendSV for context switching when no other exception is active. PendSV is
triggered using the Interrupt Control and State (INTCTRL) register.
■ SysTick. A SysTick exception is an exception that the system timer generates when it reaches
zero when it is enabled to generate an interrupt. Software can also generate a SysTick exception
using the Interrupt Control and State (INTCTRL) register. In an OS environment, the processor
can use this exception as system tick.
■ Interrupt (IRQ). An interrupt, or IRQ, is an exception signaled by a peripheral or generated by
a software request and fed through the NVIC (prioritized). All interrupts are asynchronous to
instruction execution. In the system, peripherals use interrupts to communicate with the processor.
Table 2-9 on page 90 lists the interrupts on the TM4C1230C3PM controller.
For an asynchronous exception, other than reset, the processor can execute another instruction
between when the exception is triggered and when the processor enters the exception handler.
Privileged software can disable the exceptions that Table 2-8 on page 89 shows as having
configurable priority (see the SYSHNDCTRL register on page 159 and the DIS0 register on page 130).
For more information about hard faults, memory management faults, bus faults, and usage faults,
see “Fault Handling” on page 97.
Table 2-8. Exception Types
Exception Type
a
Vector
Number
Priority
Vector Address or
b
Offset
-
0
-
0x0000.0000
Stack top is loaded from the first
entry of the vector table on reset.
Reset
1
-3 (highest)
0x0000.0004
Asynchronous
Non-Maskable Interrupt
(NMI)
2
-2
0x0000.0008
Asynchronous
Hard Fault
3
-1
0x0000.000C
-
c
0x0000.0010
Synchronous
c
0x0000.0014
Synchronous when precise and
asynchronous when imprecise
c
Synchronous
Memory Management
4
programmable
Bus Fault
5
programmable
Usage Fault
6
programmable
0x0000.0018
7-10
-
-
-
Activation
c
c
Reserved
SVCall
11
programmable
0x0000.002C
Synchronous
Debug Monitor
12
programmable
0x0000.0030
Synchronous
-
13
-
-
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Table 2-8. Exception Types (continued)
Exception Type
PendSV
SysTick
a
Vector
Number
Priority
14
programmable
15
Interrupts
Vector Address or
b
Offset
c
0x0000.0038
Asynchronous
c
0x0000.003C
Asynchronous
programmable
16 and above
Activation
d
programmable
0x0000.0040 and above Asynchronous
a. 0 is the default priority for all the programmable priorities.
b. See “Vector Table” on page 92.
c. See SYSPRI1 on page 156.
d. See PRIn registers on page 138.
Table 2-9. Interrupts
Vector Number
Interrupt Number (Bit
in Interrupt Registers)
Vector Address or
Offset
Description
0-15
-
0x0000.0000 0x0000.003C
16
0
0x0000.0040
GPIO Port A
17
1
0x0000.0044
GPIO Port B
18
2
0x0000.0048
GPIO Port C
19
3
0x0000.004C
GPIO Port D
20
4
0x0000.0050
GPIO Port E
21
5
0x0000.0054
UART0
22
6
0x0000.0058
UART1
23
7
0x0000.005C
SSI0
24
8
0x0000.0060
I2C0
25-29
9-13
-
30
14
0x0000.0078
ADC0 Sequence 0
31
15
0x0000.007C
ADC0 Sequence 1
32
16
0x0000.0080
ADC0 Sequence 2
33
17
0x0000.0084
ADC0 Sequence 3
34
18
0x0000.0088
Watchdog Timers 0 and 1
35
19
0x0000.008C
16/32-Bit Timer 0A
36
20
0x0000.0090
16/32-Bit Timer 0B
37
21
0x0000.0094
16/32-Bit Timer 1A
38
22
0x0000.0098
16/32-Bit Timer 1B
39
23
0x0000.009C
16/32-Bit Timer 2A
40
24
0x0000.00A0
16/32-Bit Timer 2B
41
25
0x0000.00A4
Analog Comparator 0
42
26
0x0000.00A8
Analog Comparator 1
43
27
-
44
28
0x0000.00B0
System Control
45
29
0x0000.00B4
Flash Memory Control and EEPROM Control
46
30
0x0000.00B8
GPIO Port F
47
31
0x0000.00BC
GPIO Port G
48
32
-
Processor exceptions
Reserved
Reserved
Reserved
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Table 2-9. Interrupts (continued)
Vector Number
Interrupt Number (Bit
in Interrupt Registers)
Vector Address or
Offset
Description
49
33
0x0000.00C4
UART2
50
34
0x0000.00C8
SSI1
51
35
0x0000.00CC
16/32-Bit Timer 3A
52
36
0x0000.00D0
16/32-Bit Timer 3B
53
37
0x0000.00D4
I2C1
54
38
-
55
39
0x0000.00DC
56-61
40-45
-
Reserved
CAN0
Reserved
62
46
0x0000.00F8
µDMA Software
63
47
0x0000.00FC
µDMA Error
64
48
0x0000.0100
ADC1 Sequence 0
65
49
0x0000.0104
ADC1 Sequence 1
66
50
0x0000.0108
ADC1 Sequence 2
ADC1 Sequence 3
67
51
0x0000.010C
68-72
52-56
-
73
57
0x0000.0124
SSI2
74
58
0x0000.0128
SSI3
75
59
0x0000.012C
UART3
76
60
0x0000.0130
UART4
77
61
0x0000.0134
UART5
78
62
0x0000.0138
UART6
79
63
0x0000.013C
UART7
80-83
64-67
0x0000.0140 0x0000.014C
Reserved
84
68
0x0000.0150
I2C2
85
69
0x0000.0154
I2C3
86
70
0x0000.0158
16/32-Bit Timer 4A
Reserved
87
71
0x0000.015C
16/32-Bit Timer 4B
88-107
72-91
0x0000.0160 0x0000.01AC
Reserved
108
92
0x0000.01B0
16/32-Bit Timer 5A
109
93
0x0000.01B4
16/32-Bit Timer 5B
110
94
0x0000.01B8
32/64-Bit Timer 0A
111
95
0x0000.01BC
32/64-Bit Timer 0B
112
96
0x0000.01C0
32/64-Bit Timer 1A
113
97
0x0000.01C4
32/64-Bit Timer 1B
114
98
0x0000.01C8
32/64-Bit Timer 2A
115
99
0x0000.01CC
32/64-Bit Timer 2B
116
100
0x0000.01D0
32/64-Bit Timer 3A
117
101
0x0000.01D4
32/64-Bit Timer 3B
118
102
0x0000.01D8
32/64-Bit Timer 4A
119
103
0x0000.01DC
32/64-Bit Timer 4B
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Table 2-9. Interrupts (continued)
2.5.3
Vector Number
Interrupt Number (Bit
in Interrupt Registers)
Vector Address or
Offset
Description
120
104
0x0000.01E0
32/64-Bit Timer 5A
121
105
0x0000.01E4
32/64-Bit Timer 5B
122
106
0x0000.01E8
System Exception (imprecise)
123-124
107-108
-
125
109
0x0000.01F4
I2C4
126
110
0x0000.01F8
I2C5
127-154
111-138
-
Reserved
Reserved
Exception Handlers
The processor handles exceptions using:
■ Interrupt Service Routines (ISRs). Interrupts (IRQx) are the exceptions handled by ISRs.
■ Fault Handlers. Hard fault, memory management fault, usage fault, and bus fault are fault
exceptions handled by the fault handlers.
■ System Handlers. NMI, PendSV, SVCall, SysTick, and the fault exceptions are all system
exceptions that are handled by system handlers.
2.5.4
Vector Table
The vector table contains the reset value of the stack pointer and the start addresses, also called
exception vectors, for all exception handlers. The vector table is constructed using the vector address
or offset shown in Table 2-8 on page 89. Figure 2-6 on page 93 shows the order of the exception
vectors in the vector table. The least-significant bit of each vector must be 1, indicating that the
exception handler is Thumb code
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Figure 2-6. Vector Table
Exception number IRQ number
154
138
.
.
.
18
2
17
1
16
0
15
-1
14
-2
13
Offset
0x0268
.
.
.
0x004C
0x0048
0x0044
0x0040
0x003C
0x0038
12
11
Vector
IRQ131
.
.
.
IRQ2
IRQ1
IRQ0
Systick
PendSV
Reserved
Reserved for Debug
-5
10
0x002C
9
SVCall
Reserved
8
7
6
-10
5
-11
4
-12
3
-13
2
-14
1
0x0018
0x0014
0x0010
0x000C
0x0008
0x0004
0x0000
Usage fault
Bus fault
Memory management fault
Hard fault
NMI
Reset
Initial SP value
On system reset, the vector table is fixed at address 0x0000.0000. Privileged software can write to
the Vector Table Offset (VTABLE) register to relocate the vector table start address to a different
memory location, in the range 0x0000.0400 to 0x3FFF.FC00 (see “Vector Table” on page 92). Note
that when configuring the VTABLE register, the offset must be aligned on a 1024-byte boundary.
2.5.5
Exception Priorities
As Table 2-8 on page 89 shows, all exceptions have an associated priority, with a lower priority
value indicating a higher priority and configurable priorities for all exceptions except Reset, Hard
fault, and NMI. If software does not configure any priorities, then all exceptions with a configurable
priority have a priority of 0. For information about configuring exception priorities, see page 156 and
page 138.
Note:
Configurable priority values for the Tiva™ C Series implementation are in the range 0-7.
This means that the Reset, Hard fault, and NMI exceptions, with fixed negative priority
values, always have higher priority than any other exception.
For example, assigning a higher priority value to IRQ[0] and a lower priority value to IRQ[1] means
that IRQ[1] has higher priority than IRQ[0]. If both IRQ[1] and IRQ[0] are asserted, IRQ[1] is processed
before IRQ[0].
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If multiple pending exceptions have the same priority, the pending exception with the lowest exception
number takes precedence. For example, if both IRQ[0] and IRQ[1] are pending and have the same
priority, then IRQ[0] is processed before IRQ[1].
When the processor is executing an exception handler, the exception handler is preempted if a
higher priority exception occurs. If an exception occurs with the same priority as the exception being
handled, the handler is not preempted, irrespective of the exception number. However, the status
of the new interrupt changes to pending.
2.5.6
Interrupt Priority Grouping
To increase priority control in systems with interrupts, the NVIC supports priority grouping. This
grouping divides each interrupt priority register entry into two fields:
■ An upper field that defines the group priority
■ A lower field that defines a subpriority within the group
Only the group priority determines preemption of interrupt exceptions. When the processor is
executing an interrupt exception handler, another interrupt with the same group priority as the
interrupt being handled does not preempt the handler.
If multiple pending interrupts have the same group priority, the subpriority field determines the order
in which they are processed. If multiple pending interrupts have the same group priority and
subpriority, the interrupt with the lowest IRQ number is processed first.
For information about splitting the interrupt priority fields into group priority and subpriority, see
page 150.
2.5.7
Exception Entry and Return
Descriptions of exception handling use the following terms:
■ Preemption. When the processor is executing an exception handler, an exception can preempt
the exception handler if its priority is higher than the priority of the exception being handled. See
“Interrupt Priority Grouping” on page 94 for more information about preemption by an interrupt.
When one exception preempts another, the exceptions are called nested exceptions. See
“Exception Entry” on page 95 more information.
■ Return. Return occurs when the exception handler is completed, and there is no pending
exception with sufficient priority to be serviced and the completed exception handler was not
handling a late-arriving exception. The processor pops the stack and restores the processor
state to the state it had before the interrupt occurred. See “Exception Return” on page 96 for
more information.
■ Tail-Chaining. This mechanism speeds up exception servicing. On completion of an exception
handler, if there is a pending exception that meets the requirements for exception entry, the
stack pop is skipped and control transfers to the new exception handler.
■ Late-Arriving. This mechanism speeds up preemption. If a higher priority exception occurs
during state saving for a previous exception, the processor switches to handle the higher priority
exception and initiates the vector fetch for that exception. State saving is not affected by late
arrival because the state saved is the same for both exceptions. Therefore, the state saving
continues uninterrupted. The processor can accept a late arriving exception until the first instruction
of the exception handler of the original exception enters the execute stage of the processor. On
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return from the exception handler of the late-arriving exception, the normal tail-chaining rules
apply.
2.5.7.1
Exception Entry
Exception entry occurs when there is a pending exception with sufficient priority and either the
processor is in Thread mode or the new exception is of higher priority than the exception being
handled, in which case the new exception preempts the original exception.
When one exception preempts another, the exceptions are nested.
Sufficient priority means the exception has more priority than any limits set by the mask registers
(see PRIMASK on page 71, FAULTMASK on page 72, and BASEPRI on page 73). An exception
with less priority than this is pending but is not handled by the processor.
When the processor takes an exception, unless the exception is a tail-chained or a late-arriving
exception, the processor pushes information onto the current stack. This operation is referred to as
stacking and the structure of eight data words is referred to as stack frame.
When using floating-point routines, the Cortex-M4F processor automatically stacks the architected
floating-point state on exception entry. Figure 2-7 on page 96 shows the Cortex-M4F stack frame
layout when floating-point state is preserved on the stack as the result of an interrupt or an exception.
Note:
Where stack space for floating-point state is not allocated, the stack frame is the same as
that of ARMv7-M implementations without an FPU. Figure 2-7 on page 96 shows this stack
frame also.
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Figure 2-7. Exception Stack Frame
...
{aligner}
FPSCR
S15
S14
S13
S12
S11
S10
S9
S8
S7
S6
S5
S4
S3
S2
S1
S0
xPSR
PC
LR
R12
R3
R2
R1
R0
Exception frame with
floating-point storage
Pre-IRQ top of stack
Decreasing
memory
address
IRQ top of stack
...
{aligner}
xPSR
PC
LR
R12
R3
R2
R1
R0
Pre-IRQ top of stack
IRQ top of stack
Exception frame without
floating-point storage
Immediately after stacking, the stack pointer indicates the lowest address in the stack frame.
The stack frame includes the return address, which is the address of the next instruction in the
interrupted program. This value is restored to the PC at exception return so that the interrupted
program resumes.
In parallel with the stacking operation, the processor performs a vector fetch that reads the exception
handler start address from the vector table. When stacking is complete, the processor starts executing
the exception handler. At the same time, the processor writes an EXC_RETURN value to the LR,
indicating which stack pointer corresponds to the stack frame and what operation mode the processor
was in before the entry occurred.
If no higher-priority exception occurs during exception entry, the processor starts executing the
exception handler and automatically changes the status of the corresponding pending interrupt to
active.
If another higher-priority exception occurs during exception entry, known as late arrival, the processor
starts executing the exception handler for this exception and does not change the pending status
of the earlier exception.
2.5.7.2
Exception Return
Exception return occurs when the processor is in Handler mode and executes one of the following
instructions to load the EXC_RETURN value into the PC:
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■ An LDM or POP instruction that loads the PC
■ A BX instruction using any register
■ An LDR instruction with the PC as the destination
EXC_RETURN is the value loaded into the LR on exception entry. The exception mechanism relies
on this value to detect when the processor has completed an exception handler. The lowest five
bits of this value provide information on the return stack and processor mode. Table 2-10 on page 97
shows the EXC_RETURN values with a description of the exception return behavior.
EXC_RETURN bits 31:5 are all set. When this value is loaded into the PC, it indicates to the processor
that the exception is complete, and the processor initiates the appropriate exception return sequence.
Table 2-10. Exception Return Behavior
EXC_RETURN[31:0]
Description
0xFFFF.FFE0
Reserved
0xFFFF.FFE1
Return to Handler mode.
Exception return uses floating-point state from MSP.
Execution uses MSP after return.
0xFFFF.FFE2 - 0xFFFF.FFE8
Reserved
0xFFFF.FFE9
Return to Thread mode.
Exception return uses floating-point state from MSP.
Execution uses MSP after return.
0xFFFF.FFEA - 0xFFFF.FFEC
Reserved
0xFFFF.FFED
Return to Thread mode.
Exception return uses floating-point state from PSP.
Execution uses PSP after return.
0xFFFF.FFEE - 0xFFFF.FFF0
Reserved
0xFFFF.FFF1
Return to Handler mode.
Exception return uses non-floating-point state from MSP.
Execution uses MSP after return.
0xFFFF.FFF2 - 0xFFFF.FFF8
Reserved
0xFFFF.FFF9
Return to Thread mode.
Exception return uses non-floating-point state from MSP.
Execution uses MSP after return.
0xFFFF.FFFA - 0xFFFF.FFFC
Reserved
0xFFFF.FFFD
Return to Thread mode.
Exception return uses non-floating-point state from PSP.
Execution uses PSP after return.
0xFFFF.FFFE - 0xFFFF.FFFF
2.6
Reserved
Fault Handling
Faults are a subset of the exceptions (see “Exception Model” on page 87). The following conditions
generate a fault:
■ A bus error on an instruction fetch or vector table load or a data access.
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■ An internally detected error such as an undefined instruction or an attempt to change state with
a BX instruction.
■ Attempting to execute an instruction from a memory region marked as Non-Executable (XN).
■ An MPU fault because of a privilege violation or an attempt to access an unmanaged region.
2.6.1
Fault Types
Table 2-11 on page 98 shows the types of fault, the handler used for the fault, the corresponding
fault status register, and the register bit that indicates the fault has occurred. See page 163 for more
information about the fault status registers.
Table 2-11. Faults
Fault
Handler
Fault Status Register
Bit Name
Bus error on a vector read
Hard fault
Hard Fault Status (HFAULTSTAT)
VECT
Fault escalated to a hard fault
Hard fault
Hard Fault Status (HFAULTSTAT)
FORCED
MPU or default memory mismatch on
instruction access
Memory management
fault
Memory Management Fault Status
(MFAULTSTAT)
IERR
MPU or default memory mismatch on
data access
Memory management
fault
Memory Management Fault Status
(MFAULTSTAT)
DERR
MPU or default memory mismatch on
exception stacking
Memory management
fault
Memory Management Fault Status
(MFAULTSTAT)
MSTKE
MPU or default memory mismatch on
exception unstacking
Memory management
fault
Memory Management Fault Status
(MFAULTSTAT)
MUSTKE
MPU or default memory mismatch
during lazy floating-point state
preservation
Memory management
fault
Memory Management Fault Status
(MFAULTSTAT)
MLSPERR
Bus error during exception stacking
Bus fault
Bus Fault Status (BFAULTSTAT)
BSTKE
Bus error during exception unstacking Bus fault
Bus Fault Status (BFAULTSTAT)
BUSTKE
Bus error during instruction prefetch
Bus fault
Bus Fault Status (BFAULTSTAT)
IBUS
Bus error during lazy floating-point state Bus fault
preservation
Bus Fault Status (BFAULTSTAT)
BLSPE
Precise data bus error
Bus fault
Bus Fault Status (BFAULTSTAT)
PRECISE
Imprecise data bus error
Bus fault
Bus Fault Status (BFAULTSTAT)
IMPRE
Attempt to access a coprocessor
Usage fault
Usage Fault Status (UFAULTSTAT)
NOCP
Undefined instruction
Usage fault
Usage Fault Status (UFAULTSTAT)
UNDEF
Attempt to enter an invalid instruction
b
set state
Usage fault
Usage Fault Status (UFAULTSTAT)
INVSTAT
Invalid EXC_RETURN value
Usage fault
Usage Fault Status (UFAULTSTAT)
INVPC
Illegal unaligned load or store
Usage fault
Usage Fault Status (UFAULTSTAT)
UNALIGN
Divide by 0
Usage fault
Usage Fault Status (UFAULTSTAT)
DIV0
a
a. Occurs on an access to an XN region even if the MPU is disabled.
b. Attempting to use an instruction set other than the Thumb instruction set, or returning to a non load-store-multiply instruction
with ICI continuation.
2.6.2
Fault Escalation and Hard Faults
All fault exceptions except for hard fault have configurable exception priority (see SYSPRI1 on
page 156). Software can disable execution of the handlers for these faults (see SYSHNDCTRL on
page 159).
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Usually, the exception priority, together with the values of the exception mask registers, determines
whether the processor enters the fault handler, and whether a fault handler can preempt another
fault handler as described in “Exception Model” on page 87.
In some situations, a fault with configurable priority is treated as a hard fault. This process is called
priority escalation, and the fault is described as escalated to hard fault. Escalation to hard fault
occurs when:
■ A fault handler causes the same kind of fault as the one it is servicing. This escalation to hard
fault occurs because a fault handler cannot preempt itself because it must have the same priority
as the current priority level.
■ A fault handler causes a fault with the same or lower priority as the fault it is servicing. This
situation happens because the handler for the new fault cannot preempt the currently executing
fault handler.
■ An exception handler causes a fault for which the priority is the same as or lower than the currently
executing exception.
■ A fault occurs and the handler for that fault is not enabled.
If a bus fault occurs during a stack push when entering a bus fault handler, the bus fault does not
escalate to a hard fault. Thus if a corrupted stack causes a fault, the fault handler executes even
though the stack push for the handler failed. The fault handler operates but the stack contents are
corrupted.
Note:
2.6.3
Only Reset and NMI can preempt the fixed priority hard fault. A hard fault can preempt any
exception other than Reset, NMI, or another hard fault.
Fault Status Registers and Fault Address Registers
The fault status registers indicate the cause of a fault. For bus faults and memory management
faults, the fault address register indicates the address accessed by the operation that caused the
fault, as shown in Table 2-12 on page 99.
Table 2-12. Fault Status and Fault Address Registers
Handler
Status Register Name
Address Register Name
Register Description
Hard fault
Hard Fault Status (HFAULTSTAT)
-
page 169
Memory management Memory Management Fault Status
fault
(MFAULTSTAT)
Memory Management Fault
Address (MMADDR)
page 163
Bus fault
Bus Fault Address
(FAULTADDR)
page 163
-
page 163
Bus Fault Status (BFAULTSTAT)
Usage fault
2.6.4
Usage Fault Status (UFAULTSTAT)
page 170
page 171
Lockup
The processor enters a lockup state if a hard fault occurs when executing the NMI or hard fault
handlers. When the processor is in the lockup state, it does not execute any instructions. The
processor remains in lockup state until it is reset, an NMI occurs, or it is halted by a debugger.
Note:
If the lockup state occurs from the NMI handler, a subsequent NMI does not cause the
processor to leave the lockup state.
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2.7
Power Management
The Cortex-M4F processor sleep modes reduce power consumption:
■ Sleep mode stops the processor clock.
■ Deep-sleep mode stops the system clock and switches off the PLL and Flash memory.
The SLEEPDEEP bit of the System Control (SYSCTRL) register selects which sleep mode is used
(see page 152). For more information about the behavior of the sleep modes, see “System
Control” on page 211.
This section describes the mechanisms for entering sleep mode and the conditions for waking up
from sleep mode, both of which apply to Sleep mode and Deep-sleep mode.
2.7.1
Entering Sleep Modes
This section describes the mechanisms software can use to put the processor into one of the sleep
modes.
The system can generate spurious wake-up events, for example a debug operation wakes up the
processor. Therefore, software must be able to put the processor back into sleep mode after such
an event. A program might have an idle loop to put the processor back to sleep mode.
2.7.1.1
Wait for Interrupt
The wait for interrupt instruction, WFI, causes immediate entry to sleep mode unless the wake-up
condition is true (see “Wake Up from WFI or Sleep-on-Exit” on page 101). When the processor
executes a WFI instruction, it stops executing instructions and enters sleep mode. See the
Cortex™-M4 instruction set chapter in the ARM® Cortex™-M4 Devices Generic User Guide (literature
number ARM DUI 0553A) for more information.
2.7.1.2
Wait for Event
The wait for event instruction, WFE, causes entry to sleep mode conditional on the value of a one-bit
event register. When the processor executes a WFE instruction, it checks the event register. If the
register is 0, the processor stops executing instructions and enters sleep mode. If the register is 1,
the processor clears the register and continues executing instructions without entering sleep mode.
If the event register is 1, the processor must not enter sleep mode on execution of a WFE instruction.
Typically, this situation occurs if an SEV instruction has been executed. Software cannot access
this register directly.
See the Cortex™-M4 instruction set chapter in the ARM® Cortex™-M4 Devices Generic User Guide
(literature number ARM DUI 0553A) for more information.
2.7.1.3
Sleep-on-Exit
If the SLEEPEXIT bit of the SYSCTRL register is set, when the processor completes the execution
of all exception handlers, it returns to Thread mode and immediately enters sleep mode. This
mechanism can be used in applications that only require the processor to run when an exception
occurs.
2.7.2
Wake Up from Sleep Mode
The conditions for the processor to wake up depend on the mechanism that caused it to enter sleep
mode.
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2.7.2.1
Wake Up from WFI or Sleep-on-Exit
Normally, the processor wakes up only when the NVIC detects an exception with sufficient priority
to cause exception entry. Some embedded systems might have to execute system restore tasks
after the processor wakes up and before executing an interrupt handler. Entry to the interrupt handler
can be delayed by setting the PRIMASK bit and clearing the FAULTMASK bit. If an interrupt arrives
that is enabled and has a higher priority than current exception priority, the processor wakes up but
does not execute the interrupt handler until the processor clears PRIMASK. For more information
about PRIMASK and FAULTMASK, see page 71 and page 72.
2.7.2.2
Wake Up from WFE
The processor wakes up if it detects an exception with sufficient priority to cause exception entry.
In addition, if the SEVONPEND bit in the SYSCTRL register is set, any new pending interrupt triggers
an event and wakes up the processor, even if the interrupt is disabled or has insufficient priority to
cause exception entry. For more information about SYSCTRL, see page 152.
2.8
Instruction Set Summary
The processor implements a version of the Thumb instruction set. Table 2-13 on page 101 lists the
supported instructions.
Note:
In Table 2-13 on page 101:
■
■
■
■
■
Angle brackets, <>, enclose alternative forms of the operand
Braces, {}, enclose optional operands
The Operands column is not exhaustive
Op2 is a flexible second operand that can be either a register or a constant
Most instructions can use an optional condition code suffix
For more information on the instructions and operands, see the instruction descriptions in
the ARM® Cortex™-M4 Technical Reference Manual.
Table 2-13. Cortex-M4F Instruction Summary
Mnemonic
Operands
Brief Description
Flags
ADC, ADCS
{Rd,} Rn, Op2
Add with carry
N,Z,C,V
ADD, ADDS
{Rd,} Rn, Op2
Add
N,Z,C,V
ADD, ADDW
{Rd,} Rn , #imm12
Add
-
ADR
Rd, label
Load PC-relative address
-
AND, ANDS
{Rd,} Rn, Op2
Logical AND
N,Z,C
ASR, ASRS
Rd, Rm, <Rs|#n>
Arithmetic shift right
N,Z,C
B
label
Branch
-
BFC
Rd, #lsb, #width
Bit field clear
-
BFI
Rd, Rn, #lsb, #width
Bit field insert
-
BIC, BICS
{Rd,} Rn, Op2
Bit clear
N,Z,C
BKPT
#imm
Breakpoint
-
BL
label
Branch with link
-
BLX
Rm
Branch indirect with link
-
BX
Rm
Branch indirect
-
CBNZ
Rn, label
Compare and branch if non-zero
-
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Table 2-13. Cortex-M4F Instruction Summary (continued)
Mnemonic
Operands
Brief Description
Flags
CBZ
Rn, label
Compare and branch if zero
-
CLREX
-
Clear exclusive
-
CLZ
Rd, Rm
Count leading zeros
-
CMN
Rn, Op2
Compare negative
N,Z,C,V
CMP
Rn, Op2
Compare
N,Z,C,V
CPSID
i
Change processor state, disable
interrupts
-
CPSIE
i
Change processor state, enable
interrupts
-
DMB
-
Data memory barrier
-
DSB
-
Data synchronization barrier
-
EOR, EORS
{Rd,} Rn, Op2
Exclusive OR
N,Z,C
ISB
-
Instruction synchronization barrier
-
IT
-
If-Then condition block
-
LDM
Rn{!}, reglist
Load multiple registers, increment after -
LDMDB, LDMEA
Rn{!}, reglist
Load multiple registers, decrement
before
LDMFD, LDMIA
Rn{!}, reglist
Load multiple registers, increment after -
LDR
Rt, [Rn, #offset]
Load register with word
-
LDRB, LDRBT
Rt, [Rn, #offset]
Load register with byte
-
LDRD
Rt, Rt2, [Rn, #offset]
Load register with two bytes
-
LDREX
Rt, [Rn, #offset]
Load register exclusive
-
LDREXB
Rt, [Rn]
Load register exclusive with byte
-
LDREXH
Rt, [Rn]
Load register exclusive with halfword
-
LDRH, LDRHT
Rt, [Rn, #offset]
Load register with halfword
-
LDRSB, LDRSBT
Rt, [Rn, #offset]
Load register with signed byte
-
LDRSH, LDRSHT
Rt, [Rn, #offset]
Load register with signed halfword
-
LDRT
Rt, [Rn, #offset]
Load register with word
-
LSL, LSLS
Rd, Rm, <Rs|#n>
Logical shift left
N,Z,C
LSR, LSRS
Rd, Rm, <Rs|#n>
Logical shift right
N,Z,C
MLA
Rd, Rn, Rm, Ra
Multiply with accumulate, 32-bit result
-
MLS
Rd, Rn, Rm, Ra
Multiply and subtract, 32-bit result
-
MOV, MOVS
Rd, Op2
Move
N,Z,C
MOV, MOVW
Rd, #imm16
Move 16-bit constant
N,Z,C
MOVT
Rd, #imm16
Move top
-
MRS
Rd, spec_reg
Move from special register to general
register
-
MSR
spec_reg, Rm
Move from general register to special
register
N,Z,C,V
MUL, MULS
{Rd,} Rn, Rm
Multiply, 32-bit result
N,Z
MVN, MVNS
Rd, Op2
Move NOT
N,Z,C
NOP
-
No operation
-
ORN, ORNS
{Rd,} Rn, Op2
Logical OR NOT
N,Z,C
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Table 2-13. Cortex-M4F Instruction Summary (continued)
Mnemonic
Operands
Brief Description
Flags
ORR, ORRS
{Rd,} Rn, Op2
Logical OR
N,Z,C
PKHTB, PKHBT
{Rd,} Rn, Rm, Op2
Pack halfword
-
POP
reglist
Pop registers from stack
-
PUSH
reglist
Push registers onto stack
-
QADD
{Rd,} Rn, Rm
Saturating add
Q
QADD16
{Rd,} Rn, Rm
Saturating add 16
-
QADD8
{Rd,} Rn, Rm
Saturating add 8
-
QASX
{Rd,} Rn, Rm
Saturating add and subtract with
exchange
-
QDADD
{Rd,} Rn, Rm
Saturating double and add
Q
QDSUB
{Rd,} Rn, Rm
Saturating double and subtract
Q
QSAX
{Rd,} Rn, Rm
Saturating subtract and add with
exchange
-
QSUB
{Rd,} Rn, Rm
Saturating subtract
Q
QSUB16
{Rd,} Rn, Rm
Saturating subtract 16
-
QSUB8
{Rd,} Rn, Rm
Saturating subtract 8
-
RBIT
Rd, Rn
Reverse bits
-
REV
Rd, Rn
Reverse byte order in a word
-
REV16
Rd, Rn
Reverse byte order in each halfword
-
REVSH
Rd, Rn
Reverse byte order in bottom halfword
and sign extend
-
ROR, RORS
Rd, Rm, <Rs|#n>
Rotate right
N,Z,C
RRX, RRXS
Rd, Rm
Rotate right with extend
N,Z,C
RSB, RSBS
{Rd,} Rn, Op2
Reverse subtract
N,Z,C,V
SADD16
{Rd,} Rn, Rm
Signed add 16
GE
SADD8
{Rd,} Rn, Rm
Signed add 8
GE
SASX
{Rd,} Rn, Rm
Signed add and subtract with exchange GE
SBC, SBCS
{Rd,} Rn, Op2
Subtract with carry
N,Z,C,V
SBFX
Rd, Rn, #lsb, #width
Signed bit field extract
-
SDIV
{Rd,} Rn, Rm
Signed divide
-
SEL
{Rd,} Rn, Rm
Select bytes
-
SEV
-
Send event
-
SHADD16
{Rd,} Rn, Rm
Signed halving add 16
-
SHADD8
{Rd,} Rn, Rm
Signed halving add 8
-
SHASX
{Rd,} Rn, Rm
Signed halving add and subtract with
exchange
-
SHSAX
{Rd,} Rn, Rm
Signed halving add and subtract with
exchange
-
SHSUB16
{Rd,} Rn, Rm
Signed halving subtract 16
-
SHSUB8
{Rd,} Rn, Rm
Signed halving subtract 8
-
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Table 2-13. Cortex-M4F Instruction Summary (continued)
Mnemonic
Operands
Brief Description
Flags
SMLABB,
Rd, Rn, Rm, Ra
Signed multiply accumulate long
(halfwords)
Q
Rd, Rn, Rm, Ra
Signed multiply accumulate dual
Q
SMLAL
RdLo, RdHi, Rn, Rm
Signed multiply with accumulate
(32x32+64), 64-bit result
-
SMLALBB,
RdLo, RdHi, Rn, Rm
Signed multiply accumulate long
(halfwords)
-
SMLALD, SMLALDX
RdLo, RdHi, Rn, Rm
Signed multiply accumulate long dual
-
SMLAWB,SMLAWT
Rd, Rn, Rm, Ra
Signed multiply accumulate, word by
halfword
Q
SMLSD
Rd, Rn, Rm, Ra
Signed multiply subtract dual
Q
RdLo, RdHi, Rn, Rm
Signed multiply subtract long dual
SMMLA
Rd, Rn, Rm, Ra
Signed most significant word multiply
accumulate
-
SMMLS,
Rd, Rn, Rm, Ra
Signed most significant word multiply
subtract
-
{Rd,} Rn, Rm
Signed most significant word multiply
-
{Rd,} Rn, Rm
Signed dual multiply add
Q
{Rd,} Rn, Rm
Signed multiply halfwords
-
SMULL
RdLo, RdHi, Rn, Rm
Signed multiply (32x32), 64-bit result
-
SMULWB,
{Rd,} Rn, Rm
Signed multiply by halfword
-
{Rd,} Rn, Rm
Signed dual multiply subtract
-
SSAT
Rd, #n, Rm {,shift #s}
Signed saturate
Q
SSAT16
Rd, #n, Rm
Signed saturate 16
Q
SSAX
{Rd,} Rn, Rm
Saturating subtract and add with
exchange
GE
SSUB16
{Rd,} Rn, Rm
Signed subtract 16
-
SSUB8
{Rd,} Rn, Rm
Signed subtract 8
-
STM
Rn{!}, reglist
Store multiple registers, increment after -
SMLABT,
SMLATB,
SMLATT
SMLAD,
SMLADX
SMLALBT,
SMLALTB,
SMLALTT
SMLSDX
SMLSLD
SMLSLDX
SMMLR
SMMUL,
SMMULR
SMUAD
SMUADX
SMULBB,
SMULBT,
SMULTB,
SMULTT
SMULWT
SMUSD,
SMUSDX
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Table 2-13. Cortex-M4F Instruction Summary (continued)
Mnemonic
Operands
Brief Description
Flags
STMDB, STMEA
Rn{!}, reglist
Store multiple registers, decrement
before
-
STMFD, STMIA
Rn{!}, reglist
Store multiple registers, increment after -
STR
Rt, [Rn {, #offset}]
Store register word
-
STRB, STRBT
Rt, [Rn {, #offset}]
Store register byte
-
STRD
Rt, Rt2, [Rn {, #offset}]
Store register two words
-
STREX
Rt, Rt, [Rn {, #offset}]
Store register exclusive
-
STREXB
Rd, Rt, [Rn]
Store register exclusive byte
-
STREXH
Rd, Rt, [Rn]
Store register exclusive halfword
-
STRH, STRHT
Rt, [Rn {, #offset}]
Store register halfword
-
STRSB, STRSBT
Rt, [Rn {, #offset}]
Store register signed byte
-
STRSH, STRSHT
Rt, [Rn {, #offset}]
Store register signed halfword
-
STRT
Rt, [Rn {, #offset}]
Store register word
-
SUB, SUBS
{Rd,} Rn, Op2
Subtract
N,Z,C,V
SUB, SUBW
{Rd,} Rn, #imm12
Subtract 12-bit constant
N,Z,C,V
SVC
#imm
Supervisor call
-
SXTAB
{Rd,} Rn, Rm, {,ROR #}
Extend 8 bits to 32 and add
-
SXTAB16
{Rd,} Rn, Rm,{,ROR #}
Dual extend 8 bits to 16 and add
-
SXTAH
{Rd,} Rn, Rm,{,ROR #}
Extend 16 bits to 32 and add
-
SXTB16
{Rd,} Rm {,ROR #n}
Signed extend byte 16
-
SXTB
{Rd,} Rm {,ROR #n}
Sign extend a byte
-
SXTH
{Rd,} Rm {,ROR #n}
Sign extend a halfword
-
TBB
[Rn, Rm]
Table branch byte
-
TBH
[Rn, Rm, LSL #1]
Table branch halfword
-
TEQ
Rn, Op2
Test equivalence
N,Z,C
TST
Rn, Op2
Test
N,Z,C
UADD16
{Rd,} Rn, Rm
Unsigned add 16
GE
UADD8
{Rd,} Rn, Rm
Unsigned add 8
GE
UASX
{Rd,} Rn, Rm
Unsigned add and subtract with
exchange
GE
UHADD16
{Rd,} Rn, Rm
Unsigned halving add 16
-
UHADD8
{Rd,} Rn, Rm
Unsigned halving add 8
-
UHASX
{Rd,} Rn, Rm
Unsigned halving add and subtract with exchange
UHSAX
{Rd,} Rn, Rm
Unsigned halving subtract and add with exchange
UHSUB16
{Rd,} Rn, Rm
Unsigned halving subtract 16
-
UHSUB8
{Rd,} Rn, Rm
Unsigned halving subtract 8
-
UBFX
Rd, Rn, #lsb, #width
Unsigned bit field extract
-
UDIV
{Rd,} Rn, Rm
Unsigned divide
-
UMAAL
RdLo, RdHi, Rn, Rm
Unsigned multiply accumulate
accumulate long (32x32+64), 64-bit
result
-
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Table 2-13. Cortex-M4F Instruction Summary (continued)
Mnemonic
Operands
Brief Description
Flags
UMLAL
RdLo, RdHi, Rn, Rm
Unsigned multiply with accumulate
(32x32+32+32), 64-bit result
-
UMULL
RdLo, RdHi, Rn, Rm
Unsigned multiply (32x 2), 64-bit result -
UQADD16
{Rd,} Rn, Rm
Unsigned Saturating Add 16
-
UQADD8
{Rd,} Rn, Rm
Unsigned Saturating Add 8
-
UQASX
{Rd,} Rn, Rm
Unsigned Saturating Add and Subtract with Exchange
UQSAX
{Rd,} Rn, Rm
Unsigned Saturating Subtract and Add with Exchange
UQSUB16
{Rd,} Rn, Rm
Unsigned Saturating Subtract 16
-
UQSUB8
{Rd,} Rn, Rm
Unsigned Saturating Subtract 8
-
USAD8
{Rd,} Rn, Rm
Unsigned Sum of Absolute Differences -
USADA8
{Rd,} Rn, Rm, Ra
Unsigned Sum of Absolute Differences and Accumulate
USAT
Rd, #n, Rm {,shift #s}
Unsigned Saturate
Q
USAT16
Rd, #n, Rm
Unsigned Saturate 16
Q
USAX
{Rd,} Rn, Rm
Unsigned Subtract and add with
Exchange
GE
USUB16
{Rd,} Rn, Rm
Unsigned Subtract 16
GE
USUB8
{Rd,} Rn, Rm
Unsigned Subtract 8
GE
UXTAB
{Rd,} Rn, Rm, {,ROR #}
Rotate, extend 8 bits to 32 and Add
-
UXTAB16
{Rd,} Rn, Rm, {,ROR #}
Rotate, dual extend 8 bits to 16 and Add -
UXTAH
{Rd,} Rn, Rm, {,ROR #}
Rotate, unsigned extend and Add
Halfword
-
UXTB
{Rd,} Rm, {,ROR #n}
Zero extend a Byte
-
UXTB16
{Rd,} Rm, {,ROR #n}
Unsigned Extend Byte 16
-
UXTH
{Rd,} Rm, {,ROR #n}
Zero extend a Halfword
-
VABS.F32
Sd, Sm
Floating-point Absolute
-
VADD.F32
{Sd,} Sn, Sm
Floating-point Add
-
VCMP.F32
Sd, <Sm | #0.0>
Compare two floating-point registers, or FPSCR
one floating-point register and zero
VCMPE.F32
Sd, <Sm | #0.0>
Compare two floating-point registers, or FPSCR
one floating-point register and zero with
Invalid Operation check
VCVT.S32.F32
Sd, Sm
Convert between floating-point and
integer
VCVT.S16.F32
Sd, Sd, #fbits
Convert between floating-point and fixed point
VCVTR.S32.F32
Sd, Sm
Convert between floating-point and
integer with rounding
-
VCVT<B|H>.F32.F16
Sd, Sm
Converts half-precision value to
single-precision
-
VCVTT<B|T>.F32.F16
Sd, Sm
Converts single-precision register to
half-precision
-
VDIV.F32
{Sd,} Sn, Sm
Floating-point Divide
-
VFMA.F32
{Sd,} Sn, Sm
Floating-point Fused Multiply Accumulate -
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Table 2-13. Cortex-M4F Instruction Summary (continued)
Mnemonic
Operands
Brief Description
Flags
VFNMA.F32
{Sd,} Sn, Sm
Floating-point Fused Negate Multiply
Accumulate
-
VFMS.F32
{Sd,} Sn, Sm
Floating-point Fused Multiply Subtract
-
VFNMS.F32
{Sd,} Sn, Sm
Floating-point Fused Negate Multiply
Subtract
-
VLDM.F<32|64>
Rn{!}, list
Load Multiple extension registers
-
VLDR.F<32|64>
<Dd|Sd>, [Rn]
Load an extension register from memory -
VLMA.F32
{Sd,} Sn, Sm
Floating-point Multiply Accumulate
-
VLMS.F32
{Sd,} Sn, Sm
Floating-point Multiply Subtract
-
VMOV.F32
Sd, #imm
Floating-point Move immediate
-
VMOV
Sd, Sm
Floating-point Move register
-
VMOV
Sn, Rt
Copy ARM core register to single
precision
-
VMOV
Sm, Sm1, Rt, Rt2
Copy 2 ARM core registers to 2 single
precision
-
VMOV
Dd[x], Rt
Copy ARM core register to scalar
-
VMOV
Rt, Dn[x]
Copy scalar to ARM core register
-
VMRS
Rt, FPSCR
Move FPSCR to ARM core register or
APSR
N,Z,C,V
VMSR
FPSCR, Rt
Move to FPSCR from ARM Core register FPSCR
VMUL.F32
{Sd,} Sn, Sm
Floating-point Multiply
-
VNEG.F32
Sd, Sm
Floating-point Negate
-
VNMLA.F32
{Sd,} Sn, Sm
Floating-point Multiply and Add
-
VNMLS.F32
{Sd,} Sn, Sm
Floating-point Multiply and Subtract
-
VNMUL
{Sd,} Sn, Sm
Floating-point Multiply
-
VPOP
list
Pop extension registers
-
VPUSH
list
Push extension registers
-
VSQRT.F32
Sd, Sm
Calculates floating-point Square Root
-
VSTM
Rn{!}, list
Floating-point register Store Multiple
-
VSTR.F3<32|64>
Sd, [Rn]
Stores an extension register to memory -
VSUB.F<32|64>
{Sd,} Sn, Sm
Floating-point Subtract
-
WFE
-
Wait for event
-
WFI
-
Wait for interrupt
-
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3
Cortex-M4 Peripherals
This chapter provides information on the Tiva™ C Series implementation of the Cortex-M4 processor
peripherals, including:
■ SysTick (see page 109)
Provides a simple, 24-bit clear-on-write, decrementing, wrap-on-zero counter with a flexible
control mechanism.
■ Nested Vectored Interrupt Controller (NVIC) (see page 110)
– Facilitates low-latency exception and interrupt handling
– Controls power management
– Implements system control registers
■ System Control Block (SCB) (see page 111)
Provides system implementation information and system control, including configuration, control,
and reporting of system exceptions.
■ Memory Protection Unit (MPU) (see page 111)
Supports the standard ARMv7 Protected Memory System Architecture (PMSA) model. The MPU
provides full support for protection regions, overlapping protection regions, access permissions,
and exporting memory attributes to the system.
■ Floating-Point Unit (FPU) (see page 116)
Fully supports single-precision add, subtract, multiply, divide, multiply and accumulate, and
square root operations. It also provides conversions between fixed-point and floating-point data
formats, and floating-point constant instructions.
Table 3-1 on page 108 shows the address map of the Private Peripheral Bus (PPB). Some peripheral
register regions are split into two address regions, as indicated by two addresses listed.
Table 3-1. Core Peripheral Register Regions
Address
Core Peripheral
Description (see page ...)
0xE000.E010-0xE000.E01F
System Timer
109
0xE000.E100-0xE000.E4EF
Nested Vectored Interrupt Controller
110
System Control Block
111
0xE000.ED90-0xE000.EDB8
Memory Protection Unit
111
0xE000.EF30-0xE000.EF44
Floating Point Unit
116
0xE000.EF00-0xE000.EF03
0xE000.E008-0xE000.E00F
0xE000.ED00-0xE000.ED3F
3.1
Functional Description
This chapter provides information on the Tiva™ C Series implementation of the Cortex-M4 processor
peripherals: SysTick, NVIC, SCB, MPU, FPU.
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3.1.1
System Timer (SysTick)
Cortex-M4 includes an integrated system timer, SysTick, which provides a simple, 24-bit
clear-on-write, decrementing, wrap-on-zero counter with a flexible control mechanism. The counter
can be used in several different ways, for example as:
■ An RTOS tick timer that fires at a programmable rate (for example, 100 Hz) and invokes a SysTick
routine.
■ A high-speed alarm timer using the system clock.
■ A variable rate alarm or signal timer—the duration is range-dependent on the reference clock
used and the dynamic range of the counter.
■ A simple counter used to measure time to completion and time used.
■ An internal clock source control based on missing/meeting durations. The COUNT bit in the
STCTRL control and status register can be used to determine if an action completed within a
set duration, as part of a dynamic clock management control loop.
The timer consists of three registers:
■ SysTick Control and Status (STCTRL): A control and status counter to configure its clock,
enable the counter, enable the SysTick interrupt, and determine counter status.
■ SysTick Reload Value (STRELOAD): The reload value for the counter, used to provide the
counter's wrap value.
■ SysTick Current Value (STCURRENT): The current value of the counter.
When enabled, the timer counts down on each clock from the reload value to zero, reloads (wraps)
to the value in the STRELOAD register on the next clock edge, then decrements on subsequent
clocks. Clearing the STRELOAD register disables the counter on the next wrap. When the counter
reaches zero, the COUNT status bit is set. The COUNT bit clears on reads.
Writing to the STCURRENT register clears the register and the COUNT status bit. The write does
not trigger the SysTick exception logic. On a read, the current value is the value of the register at
the time the register is accessed.
The SysTick counter runs on either the system clock or the precision internal oscillator (PIOSC)
divided by 4. If this clock signal is stopped for low power mode, the SysTick counter stops. SysTick
can be kept running during Deep-sleep mode by setting the CLK_SRC bit in the SysTick Control
and Status Register (STCTRL) register and ensuring that the PIOSCPD bit in the Deep Sleep
Clock Configuration (DSLPCLKCFG) register is clear. Ensure software uses aligned word accesses
to access the SysTick registers.
The SysTick counter reload and current value are undefined at reset; the correct initialization
sequence for the SysTick counter is:
1. Program the value in the STRELOAD register.
2. Clear the STCURRENT register by writing to it with any value.
3. Configure the STCTRL register for the required operation.
Note:
When the processor is halted for debugging, the counter does not decrement.
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3.1.2
Nested Vectored Interrupt Controller (NVIC)
This section describes the Nested Vectored Interrupt Controller (NVIC) and the registers it uses.
The NVIC supports:
■ 66 interrupts.
■ A programmable priority level of 0-7 for each interrupt. A higher level corresponds to a lower
priority, so level 0 is the highest interrupt priority.
■ Low-latency exception and interrupt handling.
■ Level and pulse detection of interrupt signals.
■ Dynamic reprioritization of interrupts.
■ Grouping of priority values into group priority and subpriority fields.
■ Interrupt tail-chaining.
■ An external Non-maskable interrupt (NMI).
The processor automatically stacks its state on exception entry and unstacks this state on exception
exit, with no instruction overhead, providing low latency exception handling.
3.1.2.1
Level-Sensitive and Pulse Interrupts
The processor supports both level-sensitive and pulse interrupts. Pulse interrupts are also described
as edge-triggered interrupts.
A level-sensitive interrupt is held asserted until the peripheral deasserts the interrupt signal. Typically
this happens because the ISR accesses the peripheral, causing it to clear the interrupt request. A
pulse interrupt is an interrupt signal sampled synchronously on the rising edge of the processor
clock. To ensure the NVIC detects the interrupt, the peripheral must assert the interrupt signal for
at least one clock cycle, during which the NVIC detects the pulse and latches the interrupt.
When the processor enters the ISR, it automatically removes the pending state from the interrupt
(see “Hardware and Software Control of Interrupts” on page 110 for more information). For a
level-sensitive interrupt, if the signal is not deasserted before the processor returns from the ISR,
the interrupt becomes pending again, and the processor must execute its ISR again. As a result,
the peripheral can hold the interrupt signal asserted until it no longer needs servicing.
3.1.2.2
Hardware and Software Control of Interrupts
The Cortex-M4 latches all interrupts. A peripheral interrupt becomes pending for one of the following
reasons:
■ The NVIC detects that the interrupt signal is High and the interrupt is not active.
■ The NVIC detects a rising edge on the interrupt signal.
■ Software writes to the corresponding interrupt set-pending register bit, or to the Software Trigger
Interrupt (SWTRIG) register to make a Software-Generated Interrupt pending. See the INT bit
in the PEND0 register on page 132 or SWTRIG on page 142.
A pending interrupt remains pending until one of the following:
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■ The processor enters the ISR for the interrupt, changing the state of the interrupt from pending
to active. Then:
– For a level-sensitive interrupt, when the processor returns from the ISR, the NVIC samples
the interrupt signal. If the signal is asserted, the state of the interrupt changes to pending,
which might cause the processor to immediately re-enter the ISR. Otherwise, the state of the
interrupt changes to inactive.
– For a pulse interrupt, the NVIC continues to monitor the interrupt signal, and if this is pulsed
the state of the interrupt changes to pending and active. In this case, when the processor
returns from the ISR the state of the interrupt changes to pending, which might cause the
processor to immediately re-enter the ISR.
If the interrupt signal is not pulsed while the processor is in the ISR, when the processor
returns from the ISR the state of the interrupt changes to inactive.
■ Software writes to the corresponding interrupt clear-pending register bit
– For a level-sensitive interrupt, if the interrupt signal is still asserted, the state of the interrupt
does not change. Otherwise, the state of the interrupt changes to inactive.
– For a pulse interrupt, the state of the interrupt changes to inactive, if the state was pending
or to active, if the state was active and pending.
3.1.3
System Control Block (SCB)
The System Control Block (SCB) provides system implementation information and system control,
including configuration, control, and reporting of the system exceptions.
3.1.4
Memory Protection Unit (MPU)
This section describes the Memory protection unit (MPU). The MPU divides the memory map into
a number of regions and defines the location, size, access permissions, and memory attributes of
each region. The MPU supports independent attribute settings for each region, overlapping regions,
and export of memory attributes to the system.
The memory attributes affect the behavior of memory accesses to the region. The Cortex-M4 MPU
defines eight separate memory regions, 0-7, and a background region.
When memory regions overlap, a memory access is affected by the attributes of the region with the
highest number. For example, the attributes for region 7 take precedence over the attributes of any
region that overlaps region 7.
The background region has the same memory access attributes as the default memory map, but is
accessible from privileged software only.
The Cortex-M4 MPU memory map is unified, meaning that instruction accesses and data accesses
have the same region settings.
If a program accesses a memory location that is prohibited by the MPU, the processor generates
a memory management fault, causing a fault exception and possibly causing termination of the
process in an OS environment. In an OS environment, the kernel can update the MPU region setting
dynamically based on the process to be executed. Typically, an embedded OS uses the MPU for
memory protection.
Configuration of MPU regions is based on memory types (see “Memory Regions, Types and
Attributes” on page 80 for more information).
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Table 3-2 on page 112 shows the possible MPU region attributes. See the section called “MPU
Configuration for a Tiva™ C Series Microcontroller” on page 116 for guidelines for programming a
microcontroller implementation.
Table 3-2. Memory Attributes Summary
Memory Type
Description
Strongly Ordered
All accesses to Strongly Ordered memory occur in program order.
Device
Memory-mapped peripherals
Normal
Normal memory
To avoid unexpected behavior, disable the interrupts before updating the attributes of a region that
the interrupt handlers might access.
Ensure software uses aligned accesses of the correct size to access MPU registers:
■ Except for the MPU Region Attribute and Size (MPUATTR) register, all MPU registers must
be accessed with aligned word accesses.
■ The MPUATTR register can be accessed with byte or aligned halfword or word accesses.
The processor does not support unaligned accesses to MPU registers.
When setting up the MPU, and if the MPU has previously been programmed, disable unused regions
to prevent any previous region settings from affecting the new MPU setup.
3.1.4.1
Updating an MPU Region
To update the attributes for an MPU region, the MPU Region Number (MPUNUMBER), MPU
Region Base Address (MPUBASE) and MPUATTR registers must be updated. Each register can
be programmed separately or with a multiple-word write to program all of these registers. You can
use the MPUBASEx and MPUATTRx aliases to program up to four regions simultaneously using
an STM instruction.
Updating an MPU Region Using Separate Words
This example simple code configures one region:
; R1 = region number
; R2 = size/enable
; R3 = attributes
; R4 = address
LDR R0,=MPUNUMBER
STR R1, [R0, #0x0]
STR R4, [R0, #0x4]
STRH R2, [R0, #0x8]
STRH R3, [R0, #0xA]
;
;
;
;
;
0xE000ED98, MPU region number register
Region Number
Region Base Address
Region Size and Enable
Region Attribute
Disable a region before writing new region settings to the MPU if you have previously enabled the
region being changed. For example:
; R1 = region number
; R2 = size/enable
; R3 = attributes
; R4 = address
LDR R0,=MPUNUMBER
; 0xE000ED98, MPU region number register
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STR R1, [R0, #0x0]
BIC R2, R2, #1
STRH R2, [R0, #0x8]
STR R4, [R0, #0x4]
STRH R3, [R0, #0xA]
ORR R2, #1
STRH R2, [R0, #0x8]
;
;
;
;
;
;
;
Region Number
Disable
Region Size and Enable
Region Base Address
Region Attribute
Enable
Region Size and Enable
Software must use memory barrier instructions:
■ Before MPU setup, if there might be outstanding memory transfers, such as buffered writes, that
might be affected by the change in MPU settings.
■ After MPU setup, if it includes memory transfers that must use the new MPU settings.
However, memory barrier instructions are not required if the MPU setup process starts by entering
an exception handler, or is followed by an exception return, because the exception entry and
exception return mechanism cause memory barrier behavior.
Software does not need any memory barrier instructions during MPU setup, because it accesses
the MPU through the Private Peripheral Bus (PPB), which is a Strongly Ordered memory region.
For example, if all of the memory access behavior is intended to take effect immediately after the
programming sequence, then a DSB instruction and an ISB instruction should be used. A DSB is
required after changing MPU settings, such as at the end of context switch. An ISB is required if
the code that programs the MPU region or regions is entered using a branch or call. If the
programming sequence is entered using a return from exception, or by taking an exception, then
an ISB is not required.
Updating an MPU Region Using Multi-Word Writes
The MPU can be programmed directly using multi-word writes, depending how the information is
divided. Consider the following reprogramming:
; R1 = region number
; R2 = address
; R3 = size, attributes in one
LDR R0, =MPUNUMBER ; 0xE000ED98, MPU region number register
STR R1, [R0, #0x0] ; Region Number
STR R2, [R0, #0x4] ; Region Base Address
STR R3, [R0, #0x8] ; Region Attribute, Size and Enable
An STM instruction can be used to optimize this:
; R1 = region number
; R2 = address
; R3 = size, attributes in one
LDR R0, =MPUNUMBER ; 0xE000ED98, MPU region number register
STM R0, {R1-R3}
; Region number, address, attribute, size and enable
This operation can be done in two words for prepacked information, meaning that the MPU Region
Base Address (MPUBASE) register (see page 176) contains the required region number and has
the VALID bit set. This method can be used when the data is statically packed, for example in a
boot loader:
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; R1 = address and region number in one
; R2 = size and attributes in one
LDR R0, =MPUBASE
; 0xE000ED9C, MPU Region Base register
STR R1, [R0, #0x0] ; Region base address and region number combined
; with VALID (bit 4) set
STR R2, [R0, #0x4] ; Region Attribute, Size and Enable
Subregions
Regions of 256 bytes or more are divided into eight equal-sized subregions. Set the corresponding
bit in the SRD field of the MPU Region Attribute and Size (MPUATTR) register (see page 178) to
disable a subregion. The least-significant bit of the SRD field controls the first subregion, and the
most-significant bit controls the last subregion. Disabling a subregion means another region
overlapping the disabled range matches instead. If no other enabled region overlaps the disabled
subregion, the MPU issues a fault.
Regions of 32, 64, and 128 bytes do not support subregions. With regions of these sizes, the SRD
field must be configured to 0x00, otherwise the MPU behavior is unpredictable.
Example of SRD Use
Two regions with the same base address overlap. Region one is 128 KB, and region two is 512 KB.
To ensure the attributes from region one apply to the first 128 KB region, configure the SRD field for
region two to 0x03 to disable the first two subregions, as Figure 3-1 on page 114 shows.
Figure 3-1. SRD Use Example
Region 2, with
subregions
Region 1
Base address of both regions
3.1.4.2
Offset from
base address
512KB
448KB
384KB
320KB
256KB
192KB
128KB
Disabled subregion
64KB
Disabled subregion
0
MPU Access Permission Attributes
The access permission bits, TEX, S, C, B, AP, and XN of the MPUATTR register, control access to
the corresponding memory region. If an access is made to an area of memory without the required
permissions, then the MPU generates a permission fault.
Table 3-3 on page 114 shows the encodings for the TEX, C, B, and S access permission bits. All
encodings are shown for completeness, however the current implementation of the Cortex-M4 does
not support the concept of cacheability or shareability. Refer to the section called “MPU Configuration
for a Tiva™ C Series Microcontroller” on page 116 for information on programming the MPU for
TM4C1230C3PM implementations.
Table 3-3. TEX, S, C, and B Bit Field Encoding
TEX
S
000b
x
000
B
Memory Type
Shareability
Other Attributes
0
0
Strongly Ordered
Shareable
-
a
0
1
Device
Shareable
-
x
C
a
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Table 3-3. TEX, S, C, and B Bit Field Encoding (continued)
TEX
S
C
B
Memory Type
Shareability
000
0
1
0
Normal
Not shareable
000
1
1
0
Normal
Shareable
000
0
1
1
Normal
Not shareable
000
1
1
1
Normal
Shareable
Other Attributes
Outer and inner
write-through. No write
allocate.
001
0
0
0
Normal
Not shareable
001
1
0
0
Normal
Shareable
Outer and inner
non-cacheable.
001
x
a
0
1
Reserved encoding
-
-
a
001
x
1
0
Reserved encoding
-
-
001
0
1
1
Normal
Not shareable
001
1
1
1
Normal
Shareable
Outer and inner
write-back. Write and
read allocate.
010
x
a
0
0
Device
Not shareable
Nonshared Device.
a
a
010
x
0
1
Reserved encoding
-
-
010
x
1
x
Reserved encoding
-
-
1BB
0
A
A
Normal
Not shareable
1BB
1
A
A
Normal
Shareable
Cached memory (BB =
outer policy, AA = inner
policy).
a
See Table 3-4 for the
encoding of the AA and
BB bits.
a. The MPU ignores the value of this bit.
Table 3-4 on page 115 shows the cache policy for memory attribute encodings with a TEX value in
the range of 0x4-0x7.
Table 3-4. Cache Policy for Memory Attribute Encoding
Encoding, AA or BB
Corresponding Cache Policy
00
Non-cacheable
01
Write back, write and read allocate
10
Write through, no write allocate
11
Write back, no write allocate
Table 3-5 on page 115 shows the AP encodings in the MPUATTR register that define the access
permissions for privileged and unprivileged software.
Table 3-5. AP Bit Field Encoding
AP Bit Field
Privileged
Permissions
Unprivileged
Permissions
Description
000
No access
No access
All accesses generate a permission fault.
001
RW
No access
Access from privileged software only.
010
RW
RO
Writes by unprivileged software generate a
permission fault.
011
RW
RW
Full access.
100
Unpredictable
Unpredictable
Reserved.
101
RO
No access
Reads by privileged software only.
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Table 3-5. AP Bit Field Encoding (continued)
AP Bit Field
Privileged
Permissions
Unprivileged
Permissions
Description
110
RO
RO
Read-only, by privileged or unprivileged software.
111
RO
RO
Read-only, by privileged or unprivileged software.
MPU Configuration for a Tiva™ C Series Microcontroller
Tiva™ C Series microcontrollers have only a single processor and no caches. As a result, the MPU
should be programmed as shown in Table 3-6 on page 116.
Table 3-6. Memory Region Attributes for Tiva™ C Series Microcontrollers
Memory Region
TEX
S
C
B
Memory Type and Attributes
Flash memory
000b
0
1
0
Normal memory, non-shareable, write-through
Internal SRAM
000b
1
1
0
Normal memory, shareable, write-through
External SRAM
000b
1
1
1
Normal memory, shareable, write-back,
write-allocate
Peripherals
000b
1
0
1
Device memory, shareable
In current Tiva™ C Series microcontroller implementations, the shareability and cache policy
attributes do not affect the system behavior. However, using these settings for the MPU regions
can make the application code more portable. The values given are for typical situations.
3.1.4.3
MPU Mismatch
When an access violates the MPU permissions, the processor generates a memory management
fault (see “Exceptions and Interrupts” on page 78 for more information). The MFAULTSTAT register
indicates the cause of the fault. See page 163 for more information.
3.1.5
Floating-Point Unit (FPU)
This section describes the Floating-Point Unit (FPU) and the registers it uses. The FPU provides:
■ 32-bit instructions for single-precision (C float) data-processing operations
■ Combined multiply and accumulate instructions for increased precision (Fused MAC)
■ Hardware support for conversion, addition, subtraction, multiplication with optional accumulate,
division, and square-root
■ Hardware support for denormals and all IEEE rounding modes
■ 32 dedicated 32-bit single-precision registers, also addressable as 16 double-word registers
■ Decoupled three stage pipeline
The Cortex-M4F FPU fully supports single-precision add, subtract, multiply, divide, multiply and
accumulate, and square root operations. It also provides conversions between fixed-point and
floating-point data formats, and floating-point constant instructions. The FPU provides floating-point
computation functionality that is compliant with the ANSI/IEEE Std 754-2008, IEEE Standard for
Binary Floating-Point Arithmetic, referred to as the IEEE 754 standard. The FPU's single-precision
extension registers can also be accessed as 16 doubleword registers for load, store, and move
operations.
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3.1.5.1
FPU Views of the Register Bank
The FPU provides an extension register file containing 32 single-precision registers. These can be
viewed as:
■ Sixteen 64-bit doubleword registers, D0-D15
■ Thirty-two 32-bit single-word registers, S0-S31
■ A combination of registers from the above views
Figure 3-2. FPU Register Bank
S0
S1
S2
S3
S4
S5
S6
S7
...
S28
S29
S30
S31
D0
D1
D2
D3
...
D14
D15
The mapping between the registers is as follows:
■ S<2n> maps to the least significant half of D<n>
■ S<2n+1> maps to the most significant half of D<n>
For example, you can access the least significant half of the value in D6 by accessing S12, and the
most significant half of the elements by accessing S13.
3.1.5.2
Modes of Operation
The FPU provides three modes of operation to accommodate a variety of applications.
Full-Compliance mode. In Full-Compliance mode, the FPU processes all operations according to
the IEEE 754 standard in hardware.
Flush-to-Zero mode. Setting the FZ bit of the Floating-Point Status and Control (FPSC) register
enables Flush-to-Zero mode. In this mode, the FPU treats all subnormal input operands of arithmetic
CDP operations as zeros in the operation. Exceptions that result from a zero operand are signalled
appropriately. VABS, VNEG, and VMOV are not considered arithmetic CDP operations and are not
affected by Flush-to-Zero mode. A result that is tiny, as described in the IEEE 754 standard, where
the destination precision is smaller in magnitude than the minimum normal value before rounding,
is replaced with a zero. The IDC bit in FPSC indicates when an input flush occurs. The UFC bit in
FPSC indicates when a result flush occurs.
Default NaN mode. Setting the DN bit in the FPSC register enables default NaN mode. In this mode,
the result of any arithmetic data processing operation that involves an input NaN, or that generates
a NaN result, returns the default NaN. Propagation of the fraction bits is maintained only by VABS,
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VNEG, and VMOV operations. All other CDP operations ignore any information in the fraction bits
of an input NaN.
3.1.5.3
Compliance with the IEEE 754 standard
When Default NaN (DN) and Flush-to-Zero (FZ) modes are disabled, FPv4 functionality is compliant
with the IEEE 754 standard in hardware. No support code is required to achieve this compliance.
3.1.5.4
Complete Implementation of the IEEE 754 standard
The Cortex-M4F floating point instruction set does not support all operations defined in the IEEE
754-2008 standard. Unsupported operations include, but are not limited to the following:
■ Remainder
■ Round floating-point number to integer-valued floating-point number
■ Binary-to-decimal conversions
■ Decimal-to-binary conversions
■ Direct comparison of single-precision and double-precision values
The Cortex-M4 FPU supports fused MAC operations as described in the IEEE standard. For complete
implementation of the IEEE 754-2008 standard, floating-point functionality must be augmented with
library functions.
3.1.5.5
IEEE 754 standard implementation choices
NaN handling
All single-precision values with the maximum exponent field value and a nonzero fraction field are
valid NaNs. A most-significant fraction bit of zero indicates a Signaling NaN (SNaN). A one indicates
a Quiet NaN (QNaN). Two NaN values are treated as different NaNs if they differ in any bit. The
below table shows the default NaN values.
Sign
Fraction
Fraction
0
0xFF
bit [22] = 1, bits [21:0] are all zeros
Processing of input NaNs for ARM floating-point functionality and libraries is defined as follows:
■ In full-compliance mode, NaNs are handled as described in the ARM Architecture Reference
Manual. The hardware processes the NaNs directly for arithmetic CDP instructions. For data
transfer operations, NaNs are transferred without raising the Invalid Operation exception. For
the non-arithmetic CDP instructions, VABS, VNEG, and VMOV, NaNs are copied, with a change
of sign if specified in the instructions, without causing the Invalid Operation exception.
■ In default NaN mode, arithmetic CDP instructions involving NaN operands return the default
NaN regardless of the fractions of any NaN operands. SNaNs in an arithmetic CDP operation
set the IOC flag, FPSCR[0]. NaN handling by data transfer and non-arithmetic CDP instructions
is the same as in full-compliance mode.
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Table 3-7. QNaN and SNaN Handling
Instruction Type
Default NaN
Mode
With QNaN Operand
With SNaN Operand
Off
The QNaN or one of the QNaN operands,
if there is more than one, is returned
according to the rules given in the ARM
Architecture Reference Manual.
IOC set. The SNaN is quieted and the
result NaN is determined by the rules
given in the ARM Architecture Reference
Manual.
On
Default NaN returns.
IOC set. Default NaN returns.
Arithmetic CDP
Non-arithmetic CDP Off/On
a
a
NaN passes to destination with sign changed as appropriate.
FCMP(Z)
-
Unordered compare.
IOC set. Unordered compare.
FCMPE(Z)
-
IOC set. Unordered compare.
IOC set. Unordered compare.
Load/store
Off/On
All NaNs transferred.
a. IOC is the Invalid Operation exception flag, FPSCR[0].
Comparisons
Comparison results modify the flags in the FPSCR. You can use the MVRS APSR_nzcv instruction
(formerly FMSTAT) to transfer the current flags from the FPSCR to the APSR. See the ARM
Architecture Reference Manual for mapping of IEEE 754-2008 standard predicates to ARM conditions.
The flags used are chosen so that subsequent conditional execution of ARM instructions can test
the predicates defined in the IEEE standard.
Underflow
The Cortex-M4F FPU uses the before rounding form of tininess and the inexact result form of loss
of accuracy as described in the IEEE 754-2008 standard to generate Underflow exceptions.
In flush-to-zero mode, results that are tiny before rounding, as described in the IEEE standard, are
flushed to a zero, and the UFC flag, FPSCR[3], is set. See the ARM Architecture Reference Manual
for information on flush-to-zero mode.
When the FPU is not in flush-to-zero mode, operations are performed on subnormal operands. If
the operation does not produce a tiny result, it returns the computed result, and the UFC flag,
FPSCR[3], is not set. The IXC flag, FPSCR[4], is set if the operation is inexact. If the operation
produces a tiny result, the result is a subnormal or zero value, and the UFC flag, FPSCR[3], is set
if the result was also inexact.
3.1.5.6
Exceptions
The FPU sets the cumulative exception status flag in the FPSCR register as required for each
instruction, in accordance with the FPv4 architecture. The FPU does not support user-mode traps.
The exception enable bits in the FPSCR read-as-zero, and writes are ignored. The processor also
has six output pins, FPIXC, FPUFC, FPOFC, FPDZC, FPIDC, and FPIOC, that each reflect the
status of one of the cumulative exception flags. For a description of these outputs, see the ARM
Cortex-M4 Integration and Implementation Manual (ARM DII 0239, available from ARM).
The processor can reduce the exception latency by using lazy stacking. See Auxiliary Control
Register, ACTLR on page 4-5. This means that the processor reserves space on the stack for the
FP state, but does not save that state information to the stack. See the ARMv7-M Architecture
Reference Manual (available from ARM) for more information.
3.1.5.7
Enabling the FPU
The FPU is disabled from reset. You must enable it before you can use any floating-point instructions.
The processor must be in privileged mode to read from and write to the Coprocessor Access
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Control (CPAC) register. The below example code sequence enables the FPU in both privileged
and user modes.
; CPACR is located at address 0xE000ED88
LDR.W R0, =0xE000ED88
; Read CPACR
LDR R1, [R0]
; Set bits 20-23 to enable CP10 and CP11 coprocessors
ORR R1, R1, #(0xF << 20)
; Write back the modified value to the CPACR
STR R1, [R0]; wait for store to complete
DSB
;reset pipeline now the FPU is enabled
ISB
3.2
Register Map
Table 3-8 on page 120 lists the Cortex-M4 Peripheral SysTick, NVIC, MPU, FPU and SCB registers.
The offset listed is a hexadecimal increment to the register's address, relative to the Core Peripherals
base address of 0xE000.E000.
Note:
Register spaces that are not used are reserved for future or internal use. Software should
not modify any reserved memory address.
Table 3-8. Peripherals Register Map
Offset
Name
Type
Reset
Description
See
page
System Timer (SysTick) Registers
0x010
STCTRL
RW
0x0000.0004
SysTick Control and Status Register
124
0x014
STRELOAD
RW
-
SysTick Reload Value Register
126
0x018
STCURRENT
RWC
-
SysTick Current Value Register
127
Nested Vectored Interrupt Controller (NVIC) Registers
0x100
EN0
RW
0x0000.0000
Interrupt 0-31 Set Enable
128
0x104
EN1
RW
0x0000.0000
Interrupt 32-63 Set Enable
128
0x108
EN2
RW
0x0000.0000
Interrupt 64-95 Set Enable
128
0x10C
EN3
RW
0x0000.0000
Interrupt 96-127 Set Enable
128
0x110
EN4
RW
0x0000.0000
Interrupt 128-138 Set Enable
129
0x180
DIS0
RW
0x0000.0000
Interrupt 0-31 Clear Enable
130
0x184
DIS1
RW
0x0000.0000
Interrupt 32-63 Clear Enable
130
0x188
DIS2
RW
0x0000.0000
Interrupt 64-95 Clear Enable
130
0x18C
DIS3
RW
0x0000.0000
Interrupt 96-127 Clear Enable
130
0x190
DIS4
RW
0x0000.0000
Interrupt 128-138 Clear Enable
131
0x200
PEND0
RW
0x0000.0000
Interrupt 0-31 Set Pending
132
0x204
PEND1
RW
0x0000.0000
Interrupt 32-63 Set Pending
132
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Table 3-8. Peripherals Register Map (continued)
Offset
Name
0x208
Description
See
page
Type
Reset
PEND2
RW
0x0000.0000
Interrupt 64-95 Set Pending
132
0x20C
PEND3
RW
0x0000.0000
Interrupt 96-127 Set Pending
132
0x210
PEND4
RW
0x0000.0000
Interrupt 128-138 Set Pending
133
0x280
UNPEND0
RW
0x0000.0000
Interrupt 0-31 Clear Pending
134
0x284
UNPEND1
RW
0x0000.0000
Interrupt 32-63 Clear Pending
134
0x288
UNPEND2
RW
0x0000.0000
Interrupt 64-95 Clear Pending
134
0x28C
UNPEND3
RW
0x0000.0000
Interrupt 96-127 Clear Pending
134
0x290
UNPEND4
RW
0x0000.0000
Interrupt 128-138 Clear Pending
135
0x300
ACTIVE0
RO
0x0000.0000
Interrupt 0-31 Active Bit
136
0x304
ACTIVE1
RO
0x0000.0000
Interrupt 32-63 Active Bit
136
0x308
ACTIVE2
RO
0x0000.0000
Interrupt 64-95 Active Bit
136
0x30C
ACTIVE3
RO
0x0000.0000
Interrupt 96-127 Active Bit
136
0x310
ACTIVE4
RO
0x0000.0000
Interrupt 128-138 Active Bit
137
0x400
PRI0
RW
0x0000.0000
Interrupt 0-3 Priority
138
0x404
PRI1
RW
0x0000.0000
Interrupt 4-7 Priority
138
0x408
PRI2
RW
0x0000.0000
Interrupt 8-11 Priority
138
0x40C
PRI3
RW
0x0000.0000
Interrupt 12-15 Priority
138
0x410
PRI4
RW
0x0000.0000
Interrupt 16-19 Priority
138
0x414
PRI5
RW
0x0000.0000
Interrupt 20-23 Priority
138
0x418
PRI6
RW
0x0000.0000
Interrupt 24-27 Priority
138
0x41C
PRI7
RW
0x0000.0000
Interrupt 28-31 Priority
138
0x420
PRI8
RW
0x0000.0000
Interrupt 32-35 Priority
138
0x424
PRI9
RW
0x0000.0000
Interrupt 36-39 Priority
138
0x428
PRI10
RW
0x0000.0000
Interrupt 40-43 Priority
138
0x42C
PRI11
RW
0x0000.0000
Interrupt 44-47 Priority
138
0x430
PRI12
RW
0x0000.0000
Interrupt 48-51 Priority
138
0x434
PRI13
RW
0x0000.0000
Interrupt 52-55 Priority
138
0x438
PRI14
RW
0x0000.0000
Interrupt 56-59 Priority
138
0x43C
PRI15
RW
0x0000.0000
Interrupt 60-63 Priority
138
0x440
PRI16
RW
0x0000.0000
Interrupt 64-67 Priority
140
0x444
PRI17
RW
0x0000.0000
Interrupt 68-71 Priority
140
0x448
PRI18
RW
0x0000.0000
Interrupt 72-75 Priority
140
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Table 3-8. Peripherals Register Map (continued)
Description
See
page
Offset
Name
Type
Reset
0x44C
PRI19
RW
0x0000.0000
Interrupt 76-79 Priority
140
0x450
PRI20
RW
0x0000.0000
Interrupt 80-83 Priority
140
0x454
PRI21
RW
0x0000.0000
Interrupt 84-87 Priority
140
0x458
PRI22
RW
0x0000.0000
Interrupt 88-91 Priority
140
0x45C
PRI23
RW
0x0000.0000
Interrupt 92-95 Priority
140
0x460
PRI24
RW
0x0000.0000
Interrupt 96-99 Priority
140
0x464
PRI25
RW
0x0000.0000
Interrupt 100-103 Priority
140
0x468
PRI26
RW
0x0000.0000
Interrupt 104-107 Priority
140
0x46C
PRI27
RW
0x0000.0000
Interrupt 108-111 Priority
140
0x470
PRI28
RW
0x0000.0000
Interrupt 112-115 Priority
140
0x474
PRI29
RW
0x0000.0000
Interrupt 116-119 Priority
140
0x478
PRI30
RW
0x0000.0000
Interrupt 120-123 Priority
140
0x47C
PRI31
RW
0x0000.0000
Interrupt 124-127 Priority
140
0x480
PRI32
RW
0x0000.0000
Interrupt 128-131 Priority
140
0x484
PRI33
RW
0x0000.0000
Interrupt 132-135 Priority
140
0x488
PRI34
RW
0x0000.0000
Interrupt 136-138 Priority
140
0xF00
SWTRIG
WO
0x0000.0000
Software Trigger Interrupt
142
System Control Block (SCB) Registers
0x008
ACTLR
RW
0x0000.0000
Auxiliary Control
143
0xD00
CPUID
RO
0x410F.C241
CPU ID Base
145
0xD04
INTCTRL
RW
0x0000.0000
Interrupt Control and State
146
0xD08
VTABLE
RW
0x0000.0000
Vector Table Offset
149
0xD0C
APINT
RW
0xFA05.0000
Application Interrupt and Reset Control
150
0xD10
SYSCTRL
RW
0x0000.0000
System Control
152
0xD14
CFGCTRL
RW
0x0000.0200
Configuration and Control
154
0xD18
SYSPRI1
RW
0x0000.0000
System Handler Priority 1
156
0xD1C
SYSPRI2
RW
0x0000.0000
System Handler Priority 2
157
0xD20
SYSPRI3
RW
0x0000.0000
System Handler Priority 3
158
0xD24
SYSHNDCTRL
RW
0x0000.0000
System Handler Control and State
159
0xD28
FAULTSTAT
RW1C
0x0000.0000
Configurable Fault Status
163
0xD2C
HFAULTSTAT
RW1C
0x0000.0000
Hard Fault Status
169
0xD34
MMADDR
RW
-
Memory Management Fault Address
170
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Table 3-8. Peripherals Register Map (continued)
Offset
Name
0xD38
FAULTADDR
Type
Reset
RW
-
Description
See
page
Bus Fault Address
171
Memory Protection Unit (MPU) Registers
0xD90
MPUTYPE
RO
0x0000.0800
MPU Type
172
0xD94
MPUCTRL
RW
0x0000.0000
MPU Control
173
0xD98
MPUNUMBER
RW
0x0000.0000
MPU Region Number
175
0xD9C
MPUBASE
RW
0x0000.0000
MPU Region Base Address
176
0xDA0
MPUATTR
RW
0x0000.0000
MPU Region Attribute and Size
178
0xDA4
MPUBASE1
RW
0x0000.0000
MPU Region Base Address Alias 1
176
0xDA8
MPUATTR1
RW
0x0000.0000
MPU Region Attribute and Size Alias 1
178
0xDAC
MPUBASE2
RW
0x0000.0000
MPU Region Base Address Alias 2
176
0xDB0
MPUATTR2
RW
0x0000.0000
MPU Region Attribute and Size Alias 2
178
0xDB4
MPUBASE3
RW
0x0000.0000
MPU Region Base Address Alias 3
176
0xDB8
MPUATTR3
RW
0x0000.0000
MPU Region Attribute and Size Alias 3
178
Floating-Point Unit (FPU) Registers
0xD88
CPAC
RW
0x0000.0000
Coprocessor Access Control
181
0xF34
FPCC
RW
0xC000.0000
Floating-Point Context Control
182
0xF38
FPCA
RW
-
Floating-Point Context Address
184
0xF3C
FPDSC
RW
0x0000.0000
Floating-Point Default Status Control
185
3.3
System Timer (SysTick) Register Descriptions
This section lists and describes the System Timer registers, in numerical order by address offset.
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Register 1: SysTick Control and Status Register (STCTRL), offset 0x010
Note:
This register can only be accessed from privileged mode.
The SysTick STCTRL register enables the SysTick features.
SysTick Control and Status Register (STCTRL)
Base 0xE000.E000
Offset 0x010
Type RW, reset 0x0000.0004
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
9
8
7
6
5
4
3
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
16
COUNT
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
2
1
0
CLK_SRC
INTEN
ENABLE
RW
1
RW
0
RW
0
Bit/Field
Name
Type
Reset
Description
31:17
reserved
RO
0x000
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
16
COUNT
RO
0
Count Flag
Value
Description
0
The SysTick timer has not counted to 0 since the last time
this bit was read.
1
The SysTick timer has counted to 0 since the last time
this bit was read.
This bit is cleared by a read of the register or if the STCURRENT register
is written with any value.
If read by the debugger using the DAP, this bit is cleared only if the
MasterType bit in the AHB-AP Control Register is clear. Otherwise,
the COUNT bit is not changed by the debugger read. See the ARM®
Debug Interface V5 Architecture Specification for more information on
MasterType.
15:3
reserved
RO
0x000
2
CLK_SRC
RW
1
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
Clock Source
Value Description
0
Precision internal oscillator (PIOSC) divided by 4
1
System clock
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Bit/Field
Name
Type
Reset
1
INTEN
RW
0
0
ENABLE
RW
0
Description
Interrupt Enable
Value
Description
0
Interrupt generation is disabled. Software can use the
COUNT bit to determine if the counter has ever reached 0.
1
An interrupt is generated to the NVIC when SysTick counts
to 0.
Enable
Value
Description
0
The counter is disabled.
1
Enables SysTick to operate in a multi-shot way. That is, the
counter loads the RELOAD value and begins counting down.
On reaching 0, the COUNT bit is set and an interrupt is
generated if enabled by INTEN. The counter then loads the
RELOAD value again and begins counting.
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Register 2: SysTick Reload Value Register (STRELOAD), offset 0x014
Note:
This register can only be accessed from privileged mode.
The STRELOAD register specifies the start value to load into the SysTick Current Value
(STCURRENT) register when the counter reaches 0. The start value can be between 0x1 and
0x00FF.FFFF. A start value of 0 is possible but has no effect because the SysTick interrupt and the
COUNT bit are activated when counting from 1 to 0.
SysTick can be configured as a multi-shot timer, repeated over and over, firing every N+1 clock
pulses, where N is any value from 1 to 0x00FF.FFFF. For example, if a tick interrupt is required
every 100 clock pulses, 99 must be written into the RELOAD field.
Note that in order to access this register correctly, the system clock must be faster than 8 MHz.
SysTick Reload Value Register (STRELOAD)
Base 0xE000.E000
Offset 0x014
Type RW, reset 31
30
29
28
27
26
25
24
23
22
21
20
reserved
Type
Reset
19
18
17
16
RELOAD
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
RELOAD
Type
Reset
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
Bit/Field
Name
Type
Reset
Description
31:24
reserved
RO
0x00
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
23:0
RELOAD
RW
0x00.0000
Reload Value
Value to load into the SysTick Current Value (STCURRENT) register
when the counter reaches 0.
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Register 3: SysTick Current Value Register (STCURRENT), offset 0x018
Note:
This register can only be accessed from privileged mode.
The STCURRENT register contains the current value of the SysTick counter.
SysTick Current Value Register (STCURRENT)
Base 0xE000.E000
Offset 0x018
Type RWC, reset 31
30
29
28
27
26
25
24
23
22
21
reserved
Type
Reset
20
19
18
17
16
CURRENT
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RWC
0
RWC
0
RWC
0
RWC
0
RWC
0
RWC
0
RWC
0
RWC
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
RWC
0
RWC
0
RWC
0
RWC
0
RWC
0
RWC
0
RWC
0
CURRENT
Type
Reset
RWC
0
RWC
0
RWC
0
RWC
0
RWC
0
RWC
0
RWC
0
RWC
0
RWC
0
Bit/Field
Name
Type
Reset
Description
31:24
reserved
RO
0x00
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
23:0
CURRENT
RWC
0x00.0000
Current Value
This field contains the current value at the time the register is accessed.
No read-modify-write protection is provided, so change with care.
This register is write-clear. Writing to it with any value clears the register.
Clearing this register also clears the COUNT bit of the STCTRL register.
3.4
NVIC Register Descriptions
This section lists and describes the NVIC registers, in numerical order by address offset.
The NVIC registers can only be fully accessed from privileged mode, but interrupts can be pended
while in unprivileged mode by enabling the Configuration and Control (CFGCTRL) register. Any
other unprivileged mode access causes a bus fault.
Ensure software uses correctly aligned register accesses. The processor does not support unaligned
accesses to NVIC registers.
An interrupt can enter the pending state even if it is disabled.
Before programming the VTABLE register to relocate the vector table, ensure the vector table
entries of the new vector table are set up for fault handlers, NMI, and all enabled exceptions such
as interrupts. For more information, see page 149.
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Register 4: Interrupt 0-31 Set Enable (EN0), offset 0x100
Register 5: Interrupt 32-63 Set Enable (EN1), offset 0x104
Register 6: Interrupt 64-95 Set Enable (EN2), offset 0x108
Register 7: Interrupt 96-127 Set Enable (EN3), offset 0x10C
Note:
This register can only be accessed from privileged mode.
The ENn registers enable interrupts and show which interrupts are enabled. Bit 0 of EN0 corresponds
to Interrupt 0; bit 31 corresponds to Interrupt 31. Bit 0 of EN1 corresponds to Interrupt 32; bit 31
corresponds to Interrupt 63. Bit 0 of EN2 corresponds to Interrupt 64; bit 31 corresponds to Interrupt
95. Bit 0 of EN3 corresponds to Interrupt 96; bit 31 corresponds to Interrupt 127. Bit 0 of EN4 (see
page 129) corresponds to Interrupt 128; bit 10 corresponds to Interrupt 138.
See Table 2-9 on page 90 for interrupt assignments.
If a pending interrupt is enabled, the NVIC activates the interrupt based on its priority. If an interrupt
is not enabled, asserting its interrupt signal changes the interrupt state to pending, but the NVIC
never activates the interrupt, regardless of its priority.
Interrupt 0-31 Set Enable (EN0)
Base 0xE000.E000
Offset 0x100
Type RW, reset 0x0000.0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
7
6
5
4
3
2
1
0
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
INT
Type
Reset
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
15
14
13
12
11
10
9
8
INT
Type
Reset
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
Bit/Field
Name
Type
31:0
INT
RW
RW
0
Reset
RW
0
Description
0x0000.0000 Interrupt Enable
Value
Description
0
On a read, indicates the interrupt is disabled.
On a write, no effect.
1
On a read, indicates the interrupt is enabled.
On a write, enables the interrupt.
A bit can only be cleared by setting the corresponding INT[n] bit in
the DISn register.
128
June 12, 2014
Texas Instruments-Production Data
Tiva™ TM4C1230C3PM Microcontroller
Register 8: Interrupt 128-138 Set Enable (EN4), offset 0x110
Note:
This register can only be accessed from privileged mode.
The EN4 register enables interrupts and shows which interrupts are enabled. Bit 0 corresponds to
Interrupt 128; bit 10 corresponds to Interrupt 138. See Table 2-9 on page 90 for interrupt assignments.
If a pending interrupt is enabled, the NVIC activates the interrupt based on its priority. If an interrupt
is not enabled, asserting its interrupt signal changes the interrupt state to pending, but the NVIC
never activates the interrupt, regardless of its priority.
Interrupt 128-138 Set Enable (EN4)
Base 0xE000.E000
Offset 0x110
Type RW, reset 0x0000.0000
31
30
29
28
27
26
25
24
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
RO
0
RO
0
RO
0
RO
0
RW
0
RW
0
23
22
21
20
19
18
17
16
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
8
7
6
5
4
3
2
1
0
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
reserved
Type
Reset
reserved
Type
Reset
RO
0
INT
Bit/Field
Name
Type
Reset
31:11
reserved
RO
0x0000.000
10:0
INT
RW
0x0
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
Interrupt Enable
Value
Description
0
On a read, indicates the interrupt is disabled.
On a write, no effect.
1
On a read, indicates the interrupt is enabled.
On a write, enables the interrupt.
A bit can only be cleared by setting the corresponding INT[n] bit in
the DIS4 register.
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Cortex-M4 Peripherals
Register 9: Interrupt 0-31 Clear Enable (DIS0), offset 0x180
Register 10: Interrupt 32-63 Clear Enable (DIS1), offset 0x184
Register 11: Interrupt 64-95 Clear Enable (DIS2), offset 0x188
Register 12: Interrupt 96-127 Clear Enable (DIS3), offset 0x18C
Note:
This register can only be accessed from privileged mode.
The DISn registers disable interrupts. Bit 0 of DIS0 corresponds to Interrupt 0; bit 31 corresponds
to Interrupt 31. Bit 0 of DIS1 corresponds to Interrupt 32; bit 31 corresponds to Interrupt 63. Bit 0 of
DIS2 corresponds to Interrupt 64; bit 31 corresponds to Interrupt 95. Bit 0 of DIS3 corresponds to
Interrupt 96; bit 31 corresponds to Interrupt 127. Bit 0 of DIS4 (see page 131) corresponds to Interrupt
128; bit 10 corresponds to Interrupt 138.
See Table 2-9 on page 90 for interrupt assignments.
Interrupt 0-31 Clear Enable (DIS0)
Base 0xE000.E000
Offset 0x180
Type RW, reset 0x0000.0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
INT
Type
Reset
INT
Type
Reset
Bit/Field
Name
Type
31:0
INT
RW
Reset
Description
0x0000.0000 Interrupt Disable
Value Description
0
On a read, indicates the interrupt is disabled.
On a write, no effect.
1
On a read, indicates the interrupt is enabled.
On a write, clears the corresponding INT[n] bit in the EN0
register, disabling interrupt [n].
130
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Texas Instruments-Production Data
Tiva™ TM4C1230C3PM Microcontroller
Register 13: Interrupt 128-138 Clear Enable (DIS4), offset 0x190
Note:
This register can only be accessed from privileged mode.
The DIS4 register disables interrupts. Bit 0 corresponds to Interrupt 128; bit 10 corresponds to
Interrupt 138. See Table 2-9 on page 90 for interrupt assignments.
Interrupt 128-138 Clear Enable (DIS4)
Base 0xE000.E000
Offset 0x190
Type RW, reset 0x0000.0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
5
4
3
2
1
0
RW
0
RW
0
RW
0
RW
0
RW
0
reserved
Type
Reset
RO
0
RO
0
15
14
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
13
12
11
10
9
8
7
6
reserved
Type
Reset
RO
0
RO
0
RO
0
INT
RO
0
RO
0
RW
0
RW
0
Bit/Field
Name
Type
Reset
31:11
reserved
RO
0x0000.000
10:0
INT
RW
0x0
RW
0
RW
0
RW
0
RW
0
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
Interrupt Disable
Value Description
0
On a read, indicates the interrupt is disabled.
On a write, no effect.
1
On a read, indicates the interrupt is enabled.
On a write, clears the corresponding INT[n] bit in the EN4
register, disabling interrupt [n].
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Cortex-M4 Peripherals
Register 14: Interrupt 0-31 Set Pending (PEND0), offset 0x200
Register 15: Interrupt 32-63 Set Pending (PEND1), offset 0x204
Register 16: Interrupt 64-95 Set Pending (PEND2), offset 0x208
Register 17: Interrupt 96-127 Set Pending (PEND3), offset 0x20C
Note:
This register can only be accessed from privileged mode.
The PENDn registers force interrupts into the pending state and show which interrupts are pending.
Bit 0 of PEND0 corresponds to Interrupt 0; bit 31 corresponds to Interrupt 31. Bit 0 of PEND1
corresponds to Interrupt 32; bit 31 corresponds to Interrupt 63. Bit 0 of PEND2 corresponds to
Interrupt 64; bit 31 corresponds to Interrupt 95. Bit 0 of PEND3 corresponds to Interrupt 96; bit 31
corresponds to Interrupt 127. Bit 0 of PEND4 (see page 133) corresponds to Interrupt 128; bit 10
corresponds to Interrupt 138.
See Table 2-9 on page 90 for interrupt assignments.
Interrupt 0-31 Set Pending (PEND0)
Base 0xE000.E000
Offset 0x200
Type RW, reset 0x0000.0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
INT
Type
Reset
INT
Type
Reset
Bit/Field
Name
Type
31:0
INT
RW
Reset
Description
0x0000.0000 Interrupt Set Pending
Value
Description
0
On a read, indicates that the interrupt is not pending.
On a write, no effect.
1
On a read, indicates that the interrupt is pending.
On a write, the corresponding interrupt is set to pending
even if it is disabled.
If the corresponding interrupt is already pending, setting a bit has no
effect.
A bit can only be cleared by setting the corresponding INT[n] bit in
the UNPEND0 register.
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Tiva™ TM4C1230C3PM Microcontroller
Register 18: Interrupt 128-138 Set Pending (PEND4), offset 0x210
Note:
This register can only be accessed from privileged mode.
The PEND4 register forces interrupts into the pending state and shows which interrupts are pending.
Bit 0 corresponds to Interrupt 128; bit 10 corresponds to Interrupt 138. See Table 2-9 on page 90
for interrupt assignments.
Interrupt 128-138 Set Pending (PEND4)
Base 0xE000.E000
Offset 0x210
Type RW, reset 0x0000.0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
5
4
3
2
1
0
RW
0
RW
0
RW
0
RW
0
RW
0
reserved
Type
Reset
RO
0
RO
0
15
14
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
13
12
11
10
9
8
7
6
reserved
Type
Reset
RO
0
RO
0
RO
0
INT
RO
0
RO
0
RW
0
RW
0
Bit/Field
Name
Type
Reset
31:11
reserved
RO
0x0000.000
10:0
INT
RW
0x0
RW
0
RW
0
RW
0
RW
0
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
Interrupt Set Pending
Value
Description
0
On a read, indicates that the interrupt is not pending.
On a write, no effect.
1
On a read, indicates that the interrupt is pending.
On a write, the corresponding interrupt is set to pending
even if it is disabled.
If the corresponding interrupt is already pending, setting a bit has no
effect.
A bit can only be cleared by setting the corresponding INT[n] bit in
the UNPEND4 register.
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Register 19: Interrupt 0-31 Clear Pending (UNPEND0), offset 0x280
Register 20: Interrupt 32-63 Clear Pending (UNPEND1), offset 0x284
Register 21: Interrupt 64-95 Clear Pending (UNPEND2), offset 0x288
Register 22: Interrupt 96-127 Clear Pending (UNPEND3), offset 0x28C
Note:
This register can only be accessed from privileged mode.
The UNPENDn registers show which interrupts are pending and remove the pending state from
interrupts. Bit 0 of UNPEND0 corresponds to Interrupt 0; bit 31 corresponds to Interrupt 31. Bit 0 of
UNPEND1 corresponds to Interrupt 32; bit 31 corresponds to Interrupt 63. Bit 0 of UNPEND2
corresponds to Interrupt 64; bit 31 corresponds to Interrupt 95. Bit 0 of UNPEND3 corresponds to
Interrupt 96; bit 31 corresponds to Interrupt 127. Bit 0 of UNPEND4 (see page 135) corresponds to
Interrupt 128; bit 10 corresponds to Interrupt 138.
See Table 2-9 on page 90 for interrupt assignments.
Interrupt 0-31 Clear Pending (UNPEND0)
Base 0xE000.E000
Offset 0x280
Type RW, reset 0x0000.0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
INT
Type
Reset
INT
Type
Reset
Bit/Field
Name
Type
31:0
INT
RW
Reset
Description
0x0000.0000 Interrupt Clear Pending
Value Description
0
On a read, indicates that the interrupt is not pending.
On a write, no effect.
1
On a read, indicates that the interrupt is pending.
On a write, clears the corresponding INT[n] bit in the PEND0
register, so that interrupt [n] is no longer pending.
Setting a bit does not affect the active state of the corresponding
interrupt.
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Tiva™ TM4C1230C3PM Microcontroller
Register 23: Interrupt 128-138 Clear Pending (UNPEND4), offset 0x290
Note:
This register can only be accessed from privileged mode.
The UNPEND4 register shows which interrupts are pending and removes the pending state from
interrupts. Bit 0 corresponds to Interrupt 128; bit 10 corresponds to Interrupt 138. See Table
2-9 on page 90 for interrupt assignments.
Interrupt 128-138 Clear Pending (UNPEND4)
Base 0xE000.E000
Offset 0x290
Type RW, reset 0x0000.0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
5
4
3
2
1
0
RW
0
RW
0
RW
0
RW
0
RW
0
reserved
Type
Reset
RO
0
RO
0
15
14
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
13
12
11
10
9
8
7
6
reserved
Type
Reset
RO
0
RO
0
RO
0
INT
RO
0
RO
0
RW
0
RW
0
Bit/Field
Name
Type
Reset
31:11
reserved
RO
0x0000.000
10:0
INT
RW
0x0
RW
0
RW
0
RW
0
RW
0
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
Interrupt Clear Pending
Value Description
0
On a read, indicates that the interrupt is not pending.
On a write, no effect.
1
On a read, indicates that the interrupt is pending.
On a write, clears the corresponding INT[n] bit in the PEND4
register, so that interrupt [n] is no longer pending.
Setting a bit does not affect the active state of the corresponding
interrupt.
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Register 24: Interrupt 0-31 Active Bit (ACTIVE0), offset 0x300
Register 25: Interrupt 32-63 Active Bit (ACTIVE1), offset 0x304
Register 26: Interrupt 64-95 Active Bit (ACTIVE2), offset 0x308
Register 27: Interrupt 96-127 Active Bit (ACTIVE3), offset 0x30C
Note:
This register can only be accessed from privileged mode.
The UNPENDn registers indicate which interrupts are active. Bit 0 of ACTIVE0 corresponds to
Interrupt 0; bit 31 corresponds to Interrupt 31. Bit 0 of ACTIVE1 corresponds to Interrupt 32; bit 31
corresponds to Interrupt 63. Bit 0 of ACTIVE2 corresponds to Interrupt 64; bit 31 corresponds to
Interrupt 95. Bit 0 of ACTIVE3 corresponds to Interrupt 96; bit 31 corresponds to Interrupt 127. Bit
0 of ACTIVE4 (see page 137) corresponds to Interrupt 128; bit 10 corresponds to Interrupt 138.
See Table 2-9 on page 90 for interrupt assignments.
Caution – Do not manually set or clear the bits in this register.
Interrupt 0-31 Active Bit (ACTIVE0)
Base 0xE000.E000
Offset 0x300
Type RO, reset 0x0000.0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
INT
Type
Reset
INT
Type
Reset
Bit/Field
Name
Type
31:0
INT
RO
Reset
Description
0x0000.0000 Interrupt Active
Value Description
0
The corresponding interrupt is not active.
1
The corresponding interrupt is active, or active and pending.
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Tiva™ TM4C1230C3PM Microcontroller
Register 28: Interrupt 128-138 Active Bit (ACTIVE4), offset 0x310
Note:
This register can only be accessed from privileged mode.
The ACTIVE4 register indicates which interrupts are active. Bit 0 corresponds to Interrupt 128; bit
10 corresponds to Interrupt 131. See Table 2-9 on page 90 for interrupt assignments.
Caution – Do not manually set or clear the bits in this register.
Interrupt 128-138 Active Bit (ACTIVE4)
Base 0xE000.E000
Offset 0x310
Type RO, reset 0x0000.0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
5
4
3
2
1
0
RO
0
RO
0
RO
0
RO
0
RO
0
reserved
Type
Reset
RO
0
RO
0
15
14
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
13
12
11
10
9
8
7
6
reserved
Type
Reset
RO
0
RO
0
RO
0
INT
RO
0
RO
0
RO
0
RO
0
Bit/Field
Name
Type
Reset
31:11
reserved
RO
0x0000.000
10:0
INT
RO
0x0
RO
0
RO
0
RO
0
RO
0
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
Interrupt Active
Value Description
0
The corresponding interrupt is not active.
1
The corresponding interrupt is active, or active and pending.
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Register 29: Interrupt 0-3 Priority (PRI0), offset 0x400
Register 30: Interrupt 4-7 Priority (PRI1), offset 0x404
Register 31: Interrupt 8-11 Priority (PRI2), offset 0x408
Register 32: Interrupt 12-15 Priority (PRI3), offset 0x40C
Register 33: Interrupt 16-19 Priority (PRI4), offset 0x410
Register 34: Interrupt 20-23 Priority (PRI5), offset 0x414
Register 35: Interrupt 24-27 Priority (PRI6), offset 0x418
Register 36: Interrupt 28-31 Priority (PRI7), offset 0x41C
Register 37: Interrupt 32-35 Priority (PRI8), offset 0x420
Register 38: Interrupt 36-39 Priority (PRI9), offset 0x424
Register 39: Interrupt 40-43 Priority (PRI10), offset 0x428
Register 40: Interrupt 44-47 Priority (PRI11), offset 0x42C
Register 41: Interrupt 48-51 Priority (PRI12), offset 0x430
Register 42: Interrupt 52-55 Priority (PRI13), offset 0x434
Register 43: Interrupt 56-59 Priority (PRI14), offset 0x438
Register 44: Interrupt 60-63 Priority (PRI15), offset 0x43C
Note:
This register can only be accessed from privileged mode.
The PRIn registers (see also page 140) provide 3-bit priority fields for each interrupt. These registers
are byte accessible. Each register holds four priority fields that are assigned to interrupts as follows:
PRIn Register Bit Field
Interrupt
Bits 31:29
Interrupt [4n+3]
Bits 23:21
Interrupt [4n+2]
Bits 15:13
Interrupt [4n+1]
Bits 7:5
Interrupt [4n]
See Table 2-9 on page 90 for interrupt assignments.
Each priority level can be split into separate group priority and subpriority fields. The PRIGROUP
field in the Application Interrupt and Reset Control (APINT) register (see page 150) indicates the
position of the binary point that splits the priority and subpriority fields.
These registers can only be accessed from privileged mode.
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Interrupt 0-3 Priority (PRI0)
Base 0xE000.E000
Offset 0x400
Type RW, reset 0x0000.0000
31
30
29
28
27
INTD
Type
Reset
25
24
23
reserved
22
21
20
19
INTC
18
17
16
reserved
RW
0
RW
0
RW
0
RO
0
RO
0
RO
0
RO
0
RO
0
RW
0
RW
0
RW
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
RW
0
RO
0
RO
0
RO
0
RO
0
RW
0
RW
0
RO
0
RO
0
RO
0
RO
0
INTB
Type
Reset
26
RW
0
RW
0
reserved
RO
0
INTA
Bit/Field
Name
Type
Reset
31:29
INTD
RW
0x0
RW
0
reserved
RO
0
Description
Interrupt Priority for Interrupt [4n+3]
This field holds a priority value, 0-7, for the interrupt with the number
[4n+3], where n is the number of the Interrupt Priority register (n=0 for
PRI0, and so on). The lower the value, the greater the priority of the
corresponding interrupt.
28:24
reserved
RO
0x0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
23:21
INTC
RW
0x0
Interrupt Priority for Interrupt [4n+2]
This field holds a priority value, 0-7, for the interrupt with the number
[4n+2], where n is the number of the Interrupt Priority register (n=0 for
PRI0, and so on). The lower the value, the greater the priority of the
corresponding interrupt.
20:16
reserved
RO
0x0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
15:13
INTB
RW
0x0
Interrupt Priority for Interrupt [4n+1]
This field holds a priority value, 0-7, for the interrupt with the number
[4n+1], where n is the number of the Interrupt Priority register (n=0 for
PRI0, and so on). The lower the value, the greater the priority of the
corresponding interrupt.
12:8
reserved
RO
0x0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
7:5
INTA
RW
0x0
Interrupt Priority for Interrupt [4n]
This field holds a priority value, 0-7, for the interrupt with the number
[4n], where n is the number of the Interrupt Priority register (n=0 for
PRI0, and so on). The lower the value, the greater the priority of the
corresponding interrupt.
4:0
reserved
RO
0x0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
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Register 45: Interrupt 64-67 Priority (PRI16), offset 0x440
Register 46: Interrupt 68-71 Priority (PRI17), offset 0x444
Register 47: Interrupt 72-75 Priority (PRI18), offset 0x448
Register 48: Interrupt 76-79 Priority (PRI19), offset 0x44C
Register 49: Interrupt 80-83 Priority (PRI20), offset 0x450
Register 50: Interrupt 84-87 Priority (PRI21), offset 0x454
Register 51: Interrupt 88-91 Priority (PRI22), offset 0x458
Register 52: Interrupt 92-95 Priority (PRI23), offset 0x45C
Register 53: Interrupt 96-99 Priority (PRI24), offset 0x460
Register 54: Interrupt 100-103 Priority (PRI25), offset 0x464
Register 55: Interrupt 104-107 Priority (PRI26), offset 0x468
Register 56: Interrupt 108-111 Priority (PRI27), offset 0x46C
Register 57: Interrupt 112-115 Priority (PRI28), offset 0x470
Register 58: Interrupt 116-119 Priority (PRI29), offset 0x474
Register 59: Interrupt 120-123 Priority (PRI30), offset 0x478
Register 60: Interrupt 124-127 Priority (PRI31), offset 0x47C
Register 61: Interrupt 128-131 Priority (PRI32), offset 0x480
Register 62: Interrupt 132-135 Priority (PRI33), offset 0x484
Register 63: Interrupt 136-138 Priority (PRI34), offset 0x488
Note:
This register can only be accessed from privileged mode.
The PRIn registers (see also page 138) provide 3-bit priority fields for each interrupt. These registers
are byte accessible. Each register holds four priority fields that are assigned to interrupts as follows:
PRIn Register Bit Field
Interrupt
Bits 31:29
Interrupt [4n+3]
Bits 23:21
Interrupt [4n+2]
Bits 15:13
Interrupt [4n+1]
Bits 7:5
Interrupt [4n]
See Table 2-9 on page 90 for interrupt assignments.
Each priority level can be split into separate group priority and subpriority fields. The PRIGROUP
field in the Application Interrupt and Reset Control (APINT) register (see page 150) indicates the
position of the binary point that splits the priority and subpriority fields .
These registers can only be accessed from privileged mode.
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Interrupt 64-67 Priority (PRI16)
Base 0xE000.E000
Offset 0x440
Type RW, reset 0x0000.0000
31
30
29
28
27
INTD
Type
Reset
25
24
23
reserved
22
21
20
19
INTC
18
17
16
reserved
RW
0
RW
0
RW
0
RO
0
RO
0
RO
0
RO
0
RO
0
RW
0
RW
0
RW
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
RW
0
RO
0
RO
0
RO
0
RO
0
RW
0
RW
0
RO
0
RO
0
RO
0
RO
0
INTB
Type
Reset
26
RW
0
RW
0
reserved
RO
0
INTA
Bit/Field
Name
Type
Reset
31:29
INTD
RW
0x0
RW
0
reserved
RO
0
Description
Interrupt Priority for Interrupt [4n+3]
This field holds a priority value, 0-7, for the interrupt with the number
[4n+3], where n is the number of the Interrupt Priority register (n=0 for
PRI0, and so on). The lower the value, the greater the priority of the
corresponding interrupt.
28:24
reserved
RO
0x0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
23:21
INTC
RW
0x0
Interrupt Priority for Interrupt [4n+2]
This field holds a priority value, 0-7, for the interrupt with the number
[4n+2], where n is the number of the Interrupt Priority register (n=0 for
PRI0, and so on). The lower the value, the greater the priority of the
corresponding interrupt.
20:16
reserved
RO
0x0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
15:13
INTB
RW
0x0
Interrupt Priority for Interrupt [4n+1]
This field holds a priority value, 0-7, for the interrupt with the number
[4n+1], where n is the number of the Interrupt Priority register (n=0 for
PRI0, and so on). The lower the value, the greater the priority of the
corresponding interrupt.
12:8
reserved
RO
0x0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
7:5
INTA
RW
0x0
Interrupt Priority for Interrupt [4n]
This field holds a priority value, 0-7, for the interrupt with the number
[4n], where n is the number of the Interrupt Priority register (n=0 for
PRI0, and so on). The lower the value, the greater the priority of the
corresponding interrupt.
4:0
reserved
RO
0x0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
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Register 64: Software Trigger Interrupt (SWTRIG), offset 0xF00
Note:
Only privileged software can enable unprivileged access to the SWTRIG register.
Writing an interrupt number to the SWTRIG register generates a Software Generated Interrupt (SGI).
See Table 2-9 on page 90 for interrupt assignments.
When the MAINPEND bit in the Configuration and Control (CFGCTRL) register (see page 154) is
set, unprivileged software can access the SWTRIG register.
Software Trigger Interrupt (SWTRIG)
Base 0xE000.E000
Offset 0xF00
Type WO, reset 0x0000.0000
31
30
29
28
27
26
25
24
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
23
22
21
20
19
18
17
16
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
8
7
6
5
4
3
2
1
0
RO
0
WO
0
WO
0
WO
0
WO
0
WO
0
WO
0
WO
0
WO
0
reserved
Type
Reset
reserved
Type
Reset
INTID
RO
0
Bit/Field
Name
Type
Reset
31:8
reserved
RO
0x0000.00
7:0
INTID
WO
0x00
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
Interrupt ID
This field holds the interrupt ID of the required SGI. For example, a value
of 0x3 generates an interrupt on IRQ3.
3.5
System Control Block (SCB) Register Descriptions
This section lists and describes the System Control Block (SCB) registers, in numerical order by
address offset. The SCB registers can only be accessed from privileged mode.
All registers must be accessed with aligned word accesses except for the FAULTSTAT and
SYSPRI1-SYSPRI3 registers, which can be accessed with byte or aligned halfword or word accesses.
The processor does not support unaligned accesses to system control block registers.
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Register 65: Auxiliary Control (ACTLR), offset 0x008
Note:
This register can only be accessed from privileged mode.
The ACTLR register provides disable bits for IT folding, write buffer use for accesses to the default
memory map, and interruption of multi-cycle instructions. By default, this register is set to provide
optimum performance from the Cortex-M4 processor and does not normally require modification.
Auxiliary Control (ACTLR)
Base 0xE000.E000
Offset 0x008
Type RW, reset 0x0000.0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
5
4
3
2
1
0
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
9
8
7
6
DISOOFP DISFPCA
RO
0
RO
0
RW
0
RW
0
reserved
RO
0
RO
0
RO
0
DISFOLD DISWBUF DISMCYC
RO
0
RO
0
RW
0
RW
0
RW
0
Bit/Field
Name
Type
Reset
Description
31:10
reserved
RO
0x00
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
9
DISOOFP
RW
0
Disable Out-Of-Order Floating Point
Disables floating-point instructions completing out of order with respect
to integer instructions.
8
DISFPCA
RW
0
Disable CONTROL.FPCA
Disable automatic update of the FPCA bit in the CONTROL register.
Important:
7:3
reserved
RO
0x00
2
DISFOLD
RW
0
Two bits control when FPCA can be enabled: the ASPEN
bit in the Floating-Point Context Control (FPCC)
register and the DISFPCA bit in the Auxiliary Control
(ACTLR) register.
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
Disable IT Folding
Value Description
0
No effect.
1
Disables IT folding.
In some situations, the processor can start executing the first instruction
in an IT block while it is still executing the IT instruction. This behavior
is called IT folding, and improves performance, However, IT folding can
cause jitter in looping. If a task must avoid jitter, set the DISFOLD bit
before executing the task, to disable IT folding.
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Bit/Field
Name
Type
Reset
1
DISWBUF
RW
0
Description
Disable Write Buffer
Value Description
0
No effect.
1
Disables write buffer use during default memory map accesses.
In this situation, all bus faults are precise bus faults but
performance is decreased because any store to memory must
complete before the processor can execute the next instruction.
Note:
0
DISMCYC
RW
0
This bit only affects write buffers implemented in the
Cortex-M4 processor.
Disable Interrupts of Multiple Cycle Instructions
Value Description
0
No effect.
1
Disables interruption of load multiple and store multiple
instructions. In this situation, the interrupt latency of the
processor is increased because any LDM or STM must complete
before the processor can stack the current state and enter the
interrupt handler.
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Register 66: CPU ID Base (CPUID), offset 0xD00
Note:
This register can only be accessed from privileged mode.
The CPUID register contains the ARM® Cortex™-M4 processor part number, version, and
implementation information.
CPU ID Base (CPUID)
Base 0xE000.E000
Offset 0xD00
Type RO, reset 0x410F.C241
31
30
29
28
27
26
25
24
23
22
IMP
Type
Reset
21
20
19
18
VAR
RO
0
RO
1
RO
0
RO
0
RO
0
RO
0
RO
0
RO
1
RO
0
RO
0
RO
0
RO
0
RO
1
RO
1
15
14
13
12
11
10
9
8
7
6
5
4
3
2
PARTNO
Type
Reset
RO
1
RO
1
RO
0
RO
0
RO
0
RO
0
RO
1
17
16
RO
1
RO
1
1
0
RO
0
RO
1
CON
REV
RO
0
RO
0
RO
1
Bit/Field
Name
Type
Reset
Description
31:24
IMP
RO
0x41
Implementer Code
RO
0
RO
0
RO
0
RO
0
Value Description
0x41 ARM
23:20
VAR
RO
0x0
Variant Number
Value Description
0x0
19:16
CON
RO
0xF
The rn value in the rnpn product revision identifier, for example,
the 0 in r0p0.
Constant
Value Description
0xF
15:4
PARTNO
RO
0xC24
Always reads as 0xF.
Part Number
Value Description
0xC24 Cortex-M4 processor.
3:0
REV
RO
0x1
Revision Number
Value Description
0x1
The pn value in the rnpn product revision identifier, for example,
the 1 in r0p1.
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Register 67: Interrupt Control and State (INTCTRL), offset 0xD04
Note:
This register can only be accessed from privileged mode.
The INCTRL register provides a set-pending bit for the NMI exception, and set-pending and
clear-pending bits for the PendSV and SysTick exceptions. In addition, bits in this register indicate
the exception number of the exception being processed, whether there are preempted active
exceptions, the exception number of the highest priority pending exception, and whether any interrupts
are pending.
When writing to INCTRL, the effect is unpredictable when writing a 1 to both the PENDSV and
UNPENDSV bits, or writing a 1 to both the PENDSTSET and PENDSTCLR bits.
Interrupt Control and State (INTCTRL)
Base 0xE000.E000
Offset 0xD04
Type RW, reset 0x0000.0000
31
NMISET
Type
Reset
30
29
reserved
28
26
PENDSV UNPENDSV
25
PENDSTSET PENDSTCLR
24
reserved
23
22
21
ISRPRE ISRPEND
20
19
18
reserved
17
16
VECPEND
RW
0
RO
0
RO
0
RW
0
WO
0
RW
0
WO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
VECPEND
Type
Reset
27
RO
0
RETBASE
RO
0
reserved
RO
0
RO
0
RO
0
Bit/Field
Name
Type
Reset
31
NMISET
RW
0
VECACT
Description
NMI Set Pending
Value Description
0
On a read, indicates an NMI exception is not pending.
On a write, no effect.
1
On a read, indicates an NMI exception is pending.
On a write, changes the NMI exception state to pending.
Because NMI is the highest-priority exception, normally the processor
enters the NMI exception handler as soon as it registers the setting of
this bit, and clears this bit on entering the interrupt handler. A read of
this bit by the NMI exception handler returns 1 only if the NMI signal is
reasserted while the processor is executing that handler.
30:29
reserved
RO
0x0
28
PENDSV
RW
0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
PendSV Set Pending
Value Description
0
On a read, indicates a PendSV exception is not pending.
On a write, no effect.
1
On a read, indicates a PendSV exception is pending.
On a write, changes the PendSV exception state to pending.
Setting this bit is the only way to set the PendSV exception state to
pending. This bit is cleared by writing a 1 to the UNPENDSV bit.
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Bit/Field
Name
Type
Reset
27
UNPENDSV
WO
0
Description
PendSV Clear Pending
Value Description
0
On a write, no effect.
1
On a write, removes the pending state from the PendSV
exception.
This bit is write only; on a register read, its value is unknown.
26
PENDSTSET
RW
0
SysTick Set Pending
Value Description
0
On a read, indicates a SysTick exception is not pending.
On a write, no effect.
1
On a read, indicates a SysTick exception is pending.
On a write, changes the SysTick exception state to pending.
This bit is cleared by writing a 1 to the PENDSTCLR bit.
25
PENDSTCLR
WO
0
SysTick Clear Pending
Value Description
0
On a write, no effect.
1
On a write, removes the pending state from the SysTick
exception.
This bit is write only; on a register read, its value is unknown.
24
reserved
RO
0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
23
ISRPRE
RO
0
Debug Interrupt Handling
Value Description
0
The release from halt does not take an interrupt.
1
The release from halt takes an interrupt.
This bit is only meaningful in Debug mode and reads as zero when the
processor is not in Debug mode.
22
ISRPEND
RO
0
Interrupt Pending
Value Description
0
No interrupt is pending.
1
An interrupt is pending.
This bit provides status for all interrupts excluding NMI and Faults.
21:20
reserved
RO
0x0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
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Bit/Field
Name
Type
Reset
Description
19:12
VECPEND
RO
0x00
Interrupt Pending Vector Number
This field contains the exception number of the highest priority pending
enabled exception. The value indicated by this field includes the effect
of the BASEPRI and FAULTMASK registers, but not any effect of the
PRIMASK register.
Value
Description
0x00
No exceptions are pending
0x01
Reserved
0x02
NMI
0x03
Hard fault
0x04
Memory management fault
0x05
Bus fault
0x06
Usage fault
0x07-0x0A Reserved
11
RETBASE
RO
0
0x0B
SVCall
0x0C
Reserved for Debug
0x0D
Reserved
0x0E
PendSV
0x0F
SysTick
0x10
Interrupt Vector 0
0x11
Interrupt Vector 1
...
...
0x9A
Interrupt Vector 138
Return to Base
Value Description
0
There are preempted active exceptions to execute.
1
There are no active exceptions, or the currently executing
exception is the only active exception.
This bit provides status for all interrupts excluding NMI and Faults. This
bit only has meaning if the processor is currently executing an ISR (the
Interrupt Program Status (IPSR) register is non-zero).
10:8
reserved
RO
0x0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
7:0
VECACT
RO
0x00
Interrupt Pending Vector Number
This field contains the active exception number. The exception numbers
can be found in the description for the VECPEND field. If this field is clear,
the processor is in Thread mode. This field contains the same value as
the ISRNUM field in the IPSR register.
Subtract 16 from this value to obtain the IRQ number required to index
into the Interrupt Set Enable (ENn), Interrupt Clear Enable (DISn),
Interrupt Set Pending (PENDn), Interrupt Clear Pending (UNPENDn),
and Interrupt Priority (PRIn) registers (see page 67).
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Register 68: Vector Table Offset (VTABLE), offset 0xD08
Note:
This register can only be accessed from privileged mode.
The VTABLE register indicates the offset of the vector table base address from memory address
0x0000.0000.
Vector Table Offset (VTABLE)
Base 0xE000.E000
Offset 0xD08
Type RW, reset 0x0000.0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
OFFSET
Type
Reset
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
RO
0
RO
0
RO
0
RO
0
RO
0
OFFSET
Type
Reset
RW
0
RW
0
RW
0
RW
0
reserved
RW
0
RW
0
RO
0
Bit/Field
Name
Type
Reset
31:10
OFFSET
RW
0x000.00
RO
0
RO
0
RO
0
RO
0
Description
Vector Table Offset
When configuring the OFFSET field, the offset must be aligned to the
number of exception entries in the vector table. Because there are 138
interrupts, the offset must be aligned on a 1024-byte boundary.
9:0
reserved
RO
0x00
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
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Register 69: Application Interrupt and Reset Control (APINT), offset 0xD0C
Note:
This register can only be accessed from privileged mode.
The APINT register provides priority grouping control for the exception model, endian status for
data accesses, and reset control of the system. To write to this register, 0x05FA must be written to
the VECTKEY field, otherwise the write is ignored.
The PRIGROUP field indicates the position of the binary point that splits the INTx fields in the
Interrupt Priority (PRIx) registers into separate group priority and subpriority fields. Table
3-9 on page 150 shows how the PRIGROUP value controls this split. The bit numbers in the Group
Priority Field and Subpriority Field columns in the table refer to the bits in the INTA field. For the
INTB field, the corresponding bits are 15:13; for INTC, 23:21; and for INTD, 31:29.
Note:
Determining preemption of an exception uses only the group priority field.
Table 3-9. Interrupt Priority Levels
a
PRIGROUP Bit Field
Binary Point
Group Priority Field Subpriority Field
Group
Priorities
Subpriorities
0x0 - 0x4
bxxx.
[7:5]
None
8
1
0x5
bxx.y
[7:6]
[5]
4
2
0x6
bx.yy
[7]
[6:5]
2
4
0x7
b.yyy
None
[7:5]
1
8
a. INTx field showing the binary point. An x denotes a group priority field bit, and a y denotes a subpriority field bit.
Application Interrupt and Reset Control (APINT)
Base 0xE000.E000
Offset 0xD0C
Type RW, reset 0xFA05.0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
RW
0
RW
0
RW
0
RW
1
RW
0
RW
1
5
4
3
2
1
0
VECTKEY
Type
Reset
RW
1
RW
1
RW
1
RW
1
RW
1
RW
0
15
14
13
12
11
10
reserved
ENDIANESS
Type
Reset
RO
0
RO
0
RO
0
RO
0
RW
1
RW
0
RW
0
RW
0
9
8
7
6
PRIGROUP
RO
0
RW
0
RW
0
Bit/Field
Name
Type
Reset
31:16
VECTKEY
RW
0xFA05
reserved
RW
0
RO
0
RO
0
RO
0
SYSRESREQ VECTCLRACT VECTRESET
RO
0
RO
0
WO
0
WO
0
WO
0
Description
Register Key
This field is used to guard against accidental writes to this register.
0x05FA must be written to this field in order to change the bits in this
register. On a read, 0xFA05 is returned.
15
ENDIANESS
RO
0
Data Endianess
The Tiva™ C Series implementation uses only little-endian mode so
this is cleared to 0.
14:11
reserved
RO
0x0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
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Bit/Field
Name
Type
Reset
10:8
PRIGROUP
RW
0x0
Description
Interrupt Priority Grouping
This field determines the split of group priority from subpriority (see
Table 3-9 on page 150 for more information).
7:3
reserved
RO
0x0
2
SYSRESREQ
WO
0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
System Reset Request
Value Description
0
No effect.
1
Resets the core and all on-chip peripherals except the Debug
interface.
This bit is automatically cleared during the reset of the core and reads
as 0.
1
VECTCLRACT
WO
0
Clear Active NMI / Fault
This bit is reserved for Debug use and reads as 0. This bit must be
written as a 0, otherwise behavior is unpredictable.
0
VECTRESET
WO
0
System Reset
This bit is reserved for Debug use and reads as 0. This bit must be
written as a 0, otherwise behavior is unpredictable.
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Register 70: System Control (SYSCTRL), offset 0xD10
Note:
This register can only be accessed from privileged mode.
The SYSCTRL register controls features of entry to and exit from low-power state.
System Control (SYSCTRL)
Base 0xE000.E000
Offset 0xD10
Type RW, reset 0x0000.0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
RO
0
RO
0
RO
0
RO
0
RO
0
2
1
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
10
9
8
7
6
5
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
Bit/Field
Name
Type
Reset
31:5
reserved
RO
0x0000.00
4
SEVONPEND
RW
0
RO
0
RO
0
RO
0
RO
0
4
3
SEVONPEND
reserved
RW
0
RO
0
SLEEPDEEP SLEEPEXIT
RW
0
RW
0
0
reserved
RO
0
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
Wake Up on Pending
Value Description
0
Only enabled interrupts or events can wake up the processor;
disabled interrupts are excluded.
1
Enabled events and all interrupts, including disabled interrupts,
can wake up the processor.
When an event or interrupt enters the pending state, the event signal
wakes up the processor from WFE. If the processor is not waiting for an
event, the event is registered and affects the next WFE.
The processor also wakes up on execution of a SEV instruction or an
external event.
3
reserved
RO
0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
2
SLEEPDEEP
RW
0
Deep Sleep Enable
Value Description
0
Use Sleep mode as the low power mode.
1
Use Deep-sleep mode as the low power mode.
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Bit/Field
Name
Type
Reset
1
SLEEPEXIT
RW
0
Description
Sleep on ISR Exit
Value Description
0
When returning from Handler mode to Thread mode, do not
sleep when returning to Thread mode.
1
When returning from Handler mode to Thread mode, enter sleep
or deep sleep on return from an ISR.
Setting this bit enables an interrupt-driven application to avoid returning
to an empty main application.
0
reserved
RO
0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
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Register 71: Configuration and Control (CFGCTRL), offset 0xD14
Note:
This register can only be accessed from privileged mode.
The CFGCTRL register controls entry to Thread mode and enables: the handlers for NMI, hard fault
and faults escalated by the FAULTMASK register to ignore bus faults; trapping of divide by zero
and unaligned accesses; and access to the SWTRIG register by unprivileged software (see page 142).
Configuration and Control (CFGCTRL)
Base 0xE000.E000
Offset 0xD14
Type RW, reset 0x0000.0200
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
6
5
2
1
0
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
9
8
7
reserved
STKALIGN BFHFNMIGN
RO
0
RO
0
RW
1
Bit/Field
Name
Type
Reset
31:10
reserved
RO
0x0000.00
9
STKALIGN
RW
1
RW
0
RO
0
RO
0
RO
0
4
3
DIV0
UNALIGNED
RW
0
RW
0
reserved MAINPEND BASETHR
RO
0
RW
0
RW
0
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
Stack Alignment on Exception Entry
Value Description
0
The stack is 4-byte aligned.
1
The stack is 8-byte aligned.
On exception entry, the processor uses bit 9 of the stacked PSR to
indicate the stack alignment. On return from the exception, it uses this
stacked bit to restore the correct stack alignment.
8
BFHFNMIGN
RW
0
Ignore Bus Fault in NMI and Fault
This bit enables handlers with priority -1 or -2 to ignore data bus faults
caused by load and store instructions. The setting of this bit applies to
the hard fault, NMI, and FAULTMASK escalated handlers.
Value Description
0
Data bus faults caused by load and store instructions cause a
lock-up.
1
Handlers running at priority -1 and -2 ignore data bus faults
caused by load and store instructions.
Set this bit only when the handler and its data are in absolutely safe
memory. The normal use of this bit is to probe system devices and
bridges to detect control path problems and fix them.
7:5
reserved
RO
0x0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
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Bit/Field
Name
Type
Reset
4
DIV0
RW
0
Description
Trap on Divide by 0
This bit enables faulting or halting when the processor executes an
SDIV or UDIV instruction with a divisor of 0.
Value Description
3
UNALIGNED
RW
0
0
Do not trap on divide by 0. A divide by zero returns a quotient
of 0.
1
Trap on divide by 0.
Trap on Unaligned Access
Value Description
0
Do not trap on unaligned halfword and word accesses.
1
Trap on unaligned halfword and word accesses. An unaligned
access generates a usage fault.
Unaligned LDM, STM, LDRD, and STRD instructions always fault
regardless of whether UNALIGNED is set.
2
reserved
RO
0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
1
MAINPEND
RW
0
Allow Main Interrupt Trigger
Value Description
0
BASETHR
RW
0
0
Disables unprivileged software access to the SWTRIG register.
1
Enables unprivileged software access to the SWTRIG register
(see page 142).
Thread State Control
Value Description
0
The processor can enter Thread mode only when no exception
is active.
1
The processor can enter Thread mode from any level under the
control of an EXC_RETURN value (see “Exception
Return” on page 96 for more information).
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Register 72: System Handler Priority 1 (SYSPRI1), offset 0xD18
Note:
This register can only be accessed from privileged mode.
The SYSPRI1 register configures the priority level, 0 to 7 of the usage fault, bus fault, and memory
management fault exception handlers. This register is byte-accessible.
System Handler Priority 1 (SYSPRI1)
Base 0xE000.E000
Offset 0xD18
Type RW, reset 0x0000.0000
31
30
29
28
27
26
25
24
23
reserved
Type
Reset
RO
0
15
RO
0
RO
0
RO
0
RO
0
14
13
12
11
BUS
Type
Reset
RW
0
RW
0
RO
0
RO
0
RO
0
RW
0
10
9
8
7
reserved
RW
0
RO
0
22
21
20
19
USAGE
RO
0
RO
0
RW
0
RW
0
RO
0
RO
0
6
5
4
3
MEM
RO
0
RO
0
RW
0
RW
0
18
17
16
RO
0
RO
0
RO
0
2
1
0
RO
0
RO
0
reserved
reserved
RW
0
RO
0
RO
0
RO
0
Bit/Field
Name
Type
Reset
Description
31:24
reserved
RO
0x00
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
23:21
USAGE
RW
0x0
Usage Fault Priority
This field configures the priority level of the usage fault. Configurable
priority values are in the range 0-7, with lower values having higher
priority.
20:16
reserved
RO
0x0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
15:13
BUS
RW
0x0
Bus Fault Priority
This field configures the priority level of the bus fault. Configurable priority
values are in the range 0-7, with lower values having higher priority.
12:8
reserved
RO
0x0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
7:5
MEM
RW
0x0
Memory Management Fault Priority
This field configures the priority level of the memory management fault.
Configurable priority values are in the range 0-7, with lower values
having higher priority.
4:0
reserved
RO
0x0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
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Register 73: System Handler Priority 2 (SYSPRI2), offset 0xD1C
Note:
This register can only be accessed from privileged mode.
The SYSPRI2 register configures the priority level, 0 to 7 of the SVCall handler. This register is
byte-accessible.
System Handler Priority 2 (SYSPRI2)
Base 0xE000.E000
Offset 0xD1C
Type RW, reset 0x0000.0000
31
30
29
28
27
26
25
24
23
SVC
Type
Reset
22
21
20
19
18
17
16
reserved
RW
0
RW
0
RW
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
Bit/Field
Name
Type
Reset
31:29
SVC
RW
0x0
RO
0
Description
SVCall Priority
This field configures the priority level of SVCall. Configurable priority
values are in the range 0-7, with lower values having higher priority.
28:0
reserved
RO
0x000.0000
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
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Register 74: System Handler Priority 3 (SYSPRI3), offset 0xD20
Note:
This register can only be accessed from privileged mode.
The SYSPRI3 register configures the priority level, 0 to 7 of the SysTick exception and PendSV
handlers. This register is byte-accessible.
System Handler Priority 3 (SYSPRI3)
Base 0xE000.E000
Offset 0xD20
Type RW, reset 0x0000.0000
31
30
29
28
27
TICK
Type
Reset
26
25
24
23
reserved
RW
0
RW
0
RW
0
RO
0
RO
0
RO
0
RO
0
RO
0
RW
0
15
14
13
12
11
10
9
8
7
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
22
21
20
19
PENDSV
RW
0
RW
0
RO
0
RO
0
6
5
4
3
DEBUG
RO
0
RO
0
RO
0
Bit/Field
Name
Type
Reset
31:29
TICK
RW
0x0
RO
0
RW
0
RW
0
18
17
16
RO
0
RO
0
RO
0
2
1
0
RO
0
RO
0
reserved
reserved
RW
0
RO
0
RO
0
RO
0
Description
SysTick Exception Priority
This field configures the priority level of the SysTick exception.
Configurable priority values are in the range 0-7, with lower values
having higher priority.
28:24
reserved
RO
0x0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
23:21
PENDSV
RW
0x0
PendSV Priority
This field configures the priority level of PendSV. Configurable priority
values are in the range 0-7, with lower values having higher priority.
20:8
reserved
RO
0x000
7:5
DEBUG
RW
0x0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
Debug Priority
This field configures the priority level of Debug. Configurable priority
values are in the range 0-7, with lower values having higher priority.
4:0
reserved
RO
0x0.0000
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
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Register 75: System Handler Control and State (SYSHNDCTRL), offset 0xD24
Note:
This register can only be accessed from privileged mode.
The SYSHNDCTRL register enables the system handlers, and indicates the pending status of the
usage fault, bus fault, memory management fault, and SVC exceptions as well as the active status
of the system handlers.
If a system handler is disabled and the corresponding fault occurs, the processor treats the fault as
a hard fault.
This register can be modified to change the pending or active status of system exceptions. An OS
kernel can write to the active bits to perform a context switch that changes the current exception
type.
Caution – Software that changes the value of an active bit in this register without correct adjustment
to the stacked content can cause the processor to generate a fault exception. Ensure software that writes
to this register retains and subsequently restores the current active status.
If the value of a bit in this register must be modified after enabling the system handlers, a
read-modify-write procedure must be used to ensure that only the required bit is modified.
System Handler Control and State (SYSHNDCTRL)
Base 0xE000.E000
Offset 0xD24
Type RW, reset 0x0000.0000
31
30
29
28
27
26
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
SVC
BUSP
MEMP
USAGEP
RW
0
RW
0
RW
0
RW
0
25
24
23
22
21
20
19
18
17
16
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
USAGE
BUS
MEM
RW
0
RW
0
RW
0
10
9
8
7
6
5
4
3
2
1
0
TICK
PNDSV
reserved
MON
SVCA
RW
0
RW
0
RO
0
RW
0
RW
0
USGA
reserved
BUSA
MEMA
RW
0
RO
0
RW
0
RW
0
reserved
Type
Reset
Type
Reset
reserved
RO
0
RO
0
RO
0
Bit/Field
Name
Type
Reset
Description
31:19
reserved
RO
0x000
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
18
USAGE
RW
0
Usage Fault Enable
Value Description
17
BUS
RW
0
0
Disables the usage fault exception.
1
Enables the usage fault exception.
Bus Fault Enable
Value Description
0
Disables the bus fault exception.
1
Enables the bus fault exception.
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Bit/Field
Name
Type
Reset
16
MEM
RW
0
Description
Memory Management Fault Enable
Value Description
15
SVC
RW
0
0
Disables the memory management fault exception.
1
Enables the memory management fault exception.
SVC Call Pending
Value Description
0
An SVC call exception is not pending.
1
An SVC call exception is pending.
This bit can be modified to change the pending status of the SVC call
exception.
14
BUSP
RW
0
Bus Fault Pending
Value Description
0
A bus fault exception is not pending.
1
A bus fault exception is pending.
This bit can be modified to change the pending status of the bus fault
exception.
13
MEMP
RW
0
Memory Management Fault Pending
Value Description
0
A memory management fault exception is not pending.
1
A memory management fault exception is pending.
This bit can be modified to change the pending status of the memory
management fault exception.
12
USAGEP
RW
0
Usage Fault Pending
Value Description
0
A usage fault exception is not pending.
1
A usage fault exception is pending.
This bit can be modified to change the pending status of the usage fault
exception.
11
TICK
RW
0
SysTick Exception Active
Value Description
0
A SysTick exception is not active.
1
A SysTick exception is active.
This bit can be modified to change the active status of the SysTick
exception, however, see the Caution above before setting this bit.
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Bit/Field
Name
Type
Reset
10
PNDSV
RW
0
Description
PendSV Exception Active
Value Description
0
A PendSV exception is not active.
1
A PendSV exception is active.
This bit can be modified to change the active status of the PendSV
exception, however, see the Caution above before setting this bit.
9
reserved
RO
0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
8
MON
RW
0
Debug Monitor Active
Value Description
7
SVCA
RW
0
0
The Debug monitor is not active.
1
The Debug monitor is active.
SVC Call Active
Value Description
0
SVC call is not active.
1
SVC call is active.
This bit can be modified to change the active status of the SVC call
exception, however, see the Caution above before setting this bit.
6:4
reserved
RO
0x0
3
USGA
RW
0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
Usage Fault Active
Value Description
0
Usage fault is not active.
1
Usage fault is active.
This bit can be modified to change the active status of the usage fault
exception, however, see the Caution above before setting this bit.
2
reserved
RO
0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
1
BUSA
RW
0
Bus Fault Active
Value Description
0
Bus fault is not active.
1
Bus fault is active.
This bit can be modified to change the active status of the bus fault
exception, however, see the Caution above before setting this bit.
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Bit/Field
Name
Type
Reset
0
MEMA
RW
0
Description
Memory Management Fault Active
Value Description
0
Memory management fault is not active.
1
Memory management fault is active.
This bit can be modified to change the active status of the memory
management fault exception, however, see the Caution above before
setting this bit.
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Register 76: Configurable Fault Status (FAULTSTAT), offset 0xD28
Note:
This register can only be accessed from privileged mode.
The FAULTSTAT register indicates the cause of a memory management fault, bus fault, or usage
fault. Each of these functions is assigned to a subregister as follows:
■ Usage Fault Status (UFAULTSTAT), bits 31:16
■ Bus Fault Status (BFAULTSTAT), bits 15:8
■ Memory Management Fault Status (MFAULTSTAT), bits 7:0
FAULTSTAT is byte accessible. FAULTSTAT or its subregisters can be accessed as follows:
■
■
■
■
■
The complete FAULTSTAT register, with a word access to offset 0xD28
The MFAULTSTAT, with a byte access to offset 0xD28
The MFAULTSTAT and BFAULTSTAT, with a halfword access to offset 0xD28
The BFAULTSTAT, with a byte access to offset 0xD29
The UFAULTSTAT, with a halfword access to offset 0xD2A
Bits are cleared by writing a 1 to them.
In a fault handler, the true faulting address can be determined by:
1. Read and save the Memory Management Fault Address (MMADDR) or Bus Fault Address
(FAULTADDR) value.
2. Read the MMARV bit in MFAULTSTAT, or the BFARV bit in BFAULTSTAT to determine if the
MMADDR or FAULTADDR contents are valid.
Software must follow this sequence because another higher priority exception might change the
MMADDR or FAULTADDR value. For example, if a higher priority handler preempts the current
fault handler, the other fault might change the MMADDR or FAULTADDR value.
Configurable Fault Status (FAULTSTAT)
Base 0xE000.E000
Offset 0xD28
Type RW1C, reset 0x0000.0000
31
30
29
28
27
26
reserved
Type
Reset
RO
0
15
BFARV
Type
Reset
RW1C
0
RO
0
RO
0
RO
0
14
13
12
reserved BLSPERR BSTKE
RO
0
RW1C
0
RW1C
0
RO
0
RO
0
25
24
DIV0
UNALIGN
RW1C
0
RW1C
0
23
22
21
20
reserved
RO
0
11
10
9
8
7
BUSTKE
IMPRE
PRECISE
IBUS
MMARV
RW1C
0
RW1C
0
RW1C
0
RW1C
0
RW1C
0
RO
0
RO
0
RO
0
6
5
4
reserved MLSPERR MSTKE
RO
0
RW1C
0
RW1C
0
19
18
17
16
NOCP
INVPC
INVSTAT
UNDEF
RW1C
0
RW1C
0
RW1C
0
RW1C
0
3
2
MUSTKE reserved
RW1C
0
RO
0
1
0
DERR
IERR
RW1C
0
RW1C
0
Bit/Field
Name
Type
Reset
Description
31:26
reserved
RO
0x00
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
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Bit/Field
Name
Type
Reset
25
DIV0
RW1C
0
Description
Divide-by-Zero Usage Fault
Value Description
0
No divide-by-zero fault has occurred, or divide-by-zero trapping
is not enabled.
1
The processor has executed an SDIV or UDIV instruction with
a divisor of 0.
When this bit is set, the PC value stacked for the exception return points
to the instruction that performed the divide by zero.
Trapping on divide-by-zero is enabled by setting the DIV0 bit in the
Configuration and Control (CFGCTRL) register (see page 154).
This bit is cleared by writing a 1 to it.
24
UNALIGN
RW1C
0
Unaligned Access Usage Fault
Value Description
0
No unaligned access fault has occurred, or unaligned access
trapping is not enabled.
1
The processor has made an unaligned memory access.
Unaligned LDM, STM, LDRD, and STRD instructions always fault
regardless of the configuration of this bit.
Trapping on unaligned access is enabled by setting the UNALIGNED bit
in the CFGCTRL register (see page 154).
This bit is cleared by writing a 1 to it.
23:20
reserved
RO
0x00
19
NOCP
RW1C
0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
No Coprocessor Usage Fault
Value Description
0
A usage fault has not been caused by attempting to access a
coprocessor.
1
The processor has attempted to access a coprocessor.
This bit is cleared by writing a 1 to it.
18
INVPC
RW1C
0
Invalid PC Load Usage Fault
Value Description
0
A usage fault has not been caused by attempting to load an
invalid PC value.
1
The processor has attempted an illegal load of EXC_RETURN
to the PC as a result of an invalid context or an invalid
EXC_RETURN value.
When this bit is set, the PC value stacked for the exception return points
to the instruction that tried to perform the illegal load of the PC.
This bit is cleared by writing a 1 to it.
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Bit/Field
Name
Type
Reset
17
INVSTAT
RW1C
0
Description
Invalid State Usage Fault
Value Description
0
A usage fault has not been caused by an invalid state.
1
The processor has attempted to execute an instruction that
makes illegal use of the EPSR register.
When this bit is set, the PC value stacked for the exception return points
to the instruction that attempted the illegal use of the Execution
Program Status Register (EPSR) register.
This bit is not set if an undefined instruction uses the EPSR register.
This bit is cleared by writing a 1 to it.
16
UNDEF
RW1C
0
Undefined Instruction Usage Fault
Value Description
0
A usage fault has not been caused by an undefined instruction.
1
The processor has attempted to execute an undefined
instruction.
When this bit is set, the PC value stacked for the exception return points
to the undefined instruction.
An undefined instruction is an instruction that the processor cannot
decode.
This bit is cleared by writing a 1 to it.
15
BFARV
RW1C
0
Bus Fault Address Register Valid
Value Description
0
The value in the Bus Fault Address (FAULTADDR) register
is not a valid fault address.
1
The FAULTADDR register is holding a valid fault address.
This bit is set after a bus fault, where the address is known. Other faults
can clear this bit, such as a memory management fault occurring later.
If a bus fault occurs and is escalated to a hard fault because of priority,
the hard fault handler must clear this bit. This action prevents problems
if returning to a stacked active bus fault handler whose FAULTADDR
register value has been overwritten.
This bit is cleared by writing a 1 to it.
14
reserved
RO
0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
13
BLSPERR
RW1C
0
Bus Fault on Floating-Point Lazy State Preservation
Value Description
0
No bus fault has occurred during floating-point lazy state
preservation.
1
A bus fault has occurred during floating-point lazy state
preservation.
This bit is cleared by writing a 1 to it.
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Bit/Field
Name
Type
Reset
12
BSTKE
RW1C
0
Description
Stack Bus Fault
Value Description
0
No bus fault has occurred on stacking for exception entry.
1
Stacking for an exception entry has caused one or more bus
faults.
When this bit is set, the SP is still adjusted but the values in the context
area on the stack might be incorrect. A fault address is not written to
the FAULTADDR register.
This bit is cleared by writing a 1 to it.
11
BUSTKE
RW1C
0
Unstack Bus Fault
Value Description
0
No bus fault has occurred on unstacking for a return from
exception.
1
Unstacking for a return from exception has caused one or more
bus faults.
This fault is chained to the handler. Thus, when this bit is set, the original
return stack is still present. The SP is not adjusted from the failing return,
a new save is not performed, and a fault address is not written to the
FAULTADDR register.
This bit is cleared by writing a 1 to it.
10
IMPRE
RW1C
0
Imprecise Data Bus Error
Value Description
0
An imprecise data bus error has not occurred.
1
A data bus error has occurred, but the return address in the
stack frame is not related to the instruction that caused the error.
When this bit is set, a fault address is not written to the FAULTADDR
register.
This fault is asynchronous. Therefore, if the fault is detected when the
priority of the current process is higher than the bus fault priority, the
bus fault becomes pending and becomes active only when the processor
returns from all higher-priority processes. If a precise fault occurs before
the processor enters the handler for the imprecise bus fault, the handler
detects that both the IMPRE bit is set and one of the precise fault status
bits is set.
This bit is cleared by writing a 1 to it.
9
PRECISE
RW1C
0
Precise Data Bus Error
Value Description
0
A precise data bus error has not occurred.
1
A data bus error has occurred, and the PC value stacked for
the exception return points to the instruction that caused the
fault.
When this bit is set, the fault address is written to the FAULTADDR
register.
This bit is cleared by writing a 1 to it.
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Bit/Field
Name
Type
Reset
8
IBUS
RW1C
0
Description
Instruction Bus Error
Value Description
0
An instruction bus error has not occurred.
1
An instruction bus error has occurred.
The processor detects the instruction bus error on prefetching an
instruction, but sets this bit only if it attempts to issue the faulting
instruction.
When this bit is set, a fault address is not written to the FAULTADDR
register.
This bit is cleared by writing a 1 to it.
7
MMARV
RW1C
0
Memory Management Fault Address Register Valid
Value Description
0
The value in the Memory Management Fault Address
(MMADDR) register is not a valid fault address.
1
The MMADDR register is holding a valid fault address.
If a memory management fault occurs and is escalated to a hard fault
because of priority, the hard fault handler must clear this bit. This action
prevents problems if returning to a stacked active memory management
fault handler whose MMADDR register value has been overwritten.
This bit is cleared by writing a 1 to it.
6
reserved
RO
0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
5
MLSPERR
RW1C
0
Memory Management Fault on Floating-Point Lazy State Preservation
Value Description
0
No memory management fault has occurred during floating-point
lazy state preservation.
1
No memory management fault has occurred during floating-point
lazy state preservation.
This bit is cleared by writing a 1 to it.
4
MSTKE
RW1C
0
Stack Access Violation
Value Description
0
No memory management fault has occurred on stacking for
exception entry.
1
Stacking for an exception entry has caused one or more access
violations.
When this bit is set, the SP is still adjusted but the values in the context
area on the stack might be incorrect. A fault address is not written to
the MMADDR register.
This bit is cleared by writing a 1 to it.
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Bit/Field
Name
Type
Reset
3
MUSTKE
RW1C
0
Description
Unstack Access Violation
Value Description
0
No memory management fault has occurred on unstacking for
a return from exception.
1
Unstacking for a return from exception has caused one or more
access violations.
This fault is chained to the handler. Thus, when this bit is set, the original
return stack is still present. The SP is not adjusted from the failing return,
a new save is not performed, and a fault address is not written to the
MMADDR register.
This bit is cleared by writing a 1 to it.
2
reserved
RO
0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
1
DERR
RW1C
0
Data Access Violation
Value Description
0
A data access violation has not occurred.
1
The processor attempted a load or store at a location that does
not permit the operation.
When this bit is set, the PC value stacked for the exception return points
to the faulting instruction and the address of the attempted access is
written to the MMADDR register.
This bit is cleared by writing a 1 to it.
0
IERR
RW1C
0
Instruction Access Violation
Value Description
0
An instruction access violation has not occurred.
1
The processor attempted an instruction fetch from a location
that does not permit execution.
This fault occurs on any access to an XN region, even when the MPU
is disabled or not present.
When this bit is set, the PC value stacked for the exception return points
to the faulting instruction and the address of the attempted access is
not written to the MMADDR register.
This bit is cleared by writing a 1 to it.
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Register 77: Hard Fault Status (HFAULTSTAT), offset 0xD2C
Note:
This register can only be accessed from privileged mode.
The HFAULTSTAT register gives information about events that activate the hard fault handler.
Bits are cleared by writing a 1 to them.
Hard Fault Status (HFAULTSTAT)
Base 0xE000.E000
Offset 0xD2C
Type RW1C, reset 0x0000.0000
Type
Reset
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
DBG
FORCED
RW1C
0
RW1C
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
reserved
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
VECT
reserved
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RW1C
0
RO
0
reserved
Type
Reset
Bit/Field
Name
Type
Reset
31
DBG
RW1C
0
Description
Debug Event
This bit is reserved for Debug use. This bit must be written as a 0,
otherwise behavior is unpredictable.
30
FORCED
RW1C
0
Forced Hard Fault
Value Description
0
No forced hard fault has occurred.
1
A forced hard fault has been generated by escalation of a fault
with configurable priority that cannot be handled, either because
of priority or because it is disabled.
When this bit is set, the hard fault handler must read the other fault
status registers to find the cause of the fault.
This bit is cleared by writing a 1 to it.
29:2
reserved
RO
0x00
1
VECT
RW1C
0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
Vector Table Read Fault
Value Description
0
No bus fault has occurred on a vector table read.
1
A bus fault occurred on a vector table read.
This error is always handled by the hard fault handler.
When this bit is set, the PC value stacked for the exception return points
to the instruction that was preempted by the exception.
This bit is cleared by writing a 1 to it.
0
reserved
RO
0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
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Register 78: Memory Management Fault Address (MMADDR), offset 0xD34
Note:
This register can only be accessed from privileged mode.
The MMADDR register contains the address of the location that generated a memory management
fault. When an unaligned access faults, the address in the MMADDR register is the actual address
that faulted. Because a single read or write instruction can be split into multiple aligned accesses,
the fault address can be any address in the range of the requested access size. Bits in the Memory
Management Fault Status (MFAULTSTAT) register indicate the cause of the fault and whether
the value in the MMADDR register is valid (see page 163).
Memory Management Fault Address (MMADDR)
Base 0xE000.E000
Offset 0xD34
Type RW, reset 31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
RW
-
RW
-
RW
-
RW
-
RW
-
RW
-
RW
-
RW
-
7
6
5
4
3
2
1
0
RW
-
RW
-
RW
-
RW
-
RW
-
RW
-
RW
-
RW
-
ADDR
Type
Reset
RW
-
RW
-
RW
-
RW
-
RW
-
RW
-
RW
-
RW
-
15
14
13
12
11
10
9
8
ADDR
Type
Reset
RW
-
RW
-
RW
-
RW
-
RW
-
RW
-
RW
-
Bit/Field
Name
Type
Reset
31:0
ADDR
RW
-
RW
-
Description
Fault Address
When the MMARV bit of MFAULTSTAT is set, this field holds the address
of the location that generated the memory management fault.
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Register 79: Bus Fault Address (FAULTADDR), offset 0xD38
Note:
This register can only be accessed from privileged mode.
The FAULTADDR register contains the address of the location that generated a bus fault. When
an unaligned access faults, the address in the FAULTADDR register is the one requested by the
instruction, even if it is not the address of the fault. Bits in the Bus Fault Status (BFAULTSTAT)
register indicate the cause of the fault and whether the value in the FAULTADDR register is valid
(see page 163).
Bus Fault Address (FAULTADDR)
Base 0xE000.E000
Offset 0xD38
Type RW, reset 31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
RW
-
RW
-
RW
-
RW
-
RW
-
RW
-
RW
-
RW
-
7
6
5
4
3
2
1
0
RW
-
RW
-
RW
-
RW
-
RW
-
RW
-
RW
-
RW
-
ADDR
Type
Reset
RW
-
RW
-
RW
-
RW
-
RW
-
RW
-
RW
-
RW
-
15
14
13
12
11
10
9
8
ADDR
Type
Reset
RW
-
RW
-
RW
-
RW
-
RW
-
RW
-
RW
-
Bit/Field
Name
Type
Reset
31:0
ADDR
RW
-
RW
-
Description
Fault Address
When the FAULTADDRV bit of BFAULTSTAT is set, this field holds the
address of the location that generated the bus fault.
3.6
Memory Protection Unit (MPU) Register Descriptions
This section lists and describes the Memory Protection Unit (MPU) registers, in numerical order by
address offset.
The MPU registers can only be accessed from privileged mode.
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Register 80: MPU Type (MPUTYPE), offset 0xD90
Note:
This register can only be accessed from privileged mode.
The MPUTYPE register indicates whether the MPU is present, and if so, how many regions it
supports.
MPU Type (MPUTYPE)
Base 0xE000.E000
Offset 0xD90
Type RO, reset 0x0000.0800
31
30
29
28
27
26
25
24
23
22
21
20
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
8
7
6
5
DREGION
Type
Reset
RO
0
RO
0
RO
0
RO
0
19
18
17
16
RO
0
IREGION
RO
0
RO
0
RO
0
RO
0
4
3
2
1
reserved
RO
1
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
0
SEPARATE
RO
0
RO
0
RO
0
RO
0
Bit/Field
Name
Type
Reset
Description
31:24
reserved
RO
0x00
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
23:16
IREGION
RO
0x00
Number of I Regions
This field indicates the number of supported MPU instruction regions.
This field always contains 0x00. The MPU memory map is unified and
is described by the DREGION field.
15:8
DREGION
RO
0x08
Number of D Regions
Value Description
0x08 Indicates there are eight supported MPU data regions.
7:1
reserved
RO
0x00
0
SEPARATE
RO
0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
Separate or Unified MPU
Value Description
0
Indicates the MPU is unified.
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Register 81: MPU Control (MPUCTRL), offset 0xD94
Note:
This register can only be accessed from privileged mode.
The MPUCTRL register enables the MPU, enables the default memory map background region,
and enables use of the MPU when in the hard fault, Non-maskable Interrupt (NMI), and Fault Mask
Register (FAULTMASK) escalated handlers.
When the ENABLE and PRIVDEFEN bits are both set:
■ For privileged accesses, the default memory map is as described in “Memory Model” on page 78.
Any access by privileged software that does not address an enabled memory region behaves
as defined by the default memory map.
■ Any access by unprivileged software that does not address an enabled memory region causes
a memory management fault.
Execute Never (XN) and Strongly Ordered rules always apply to the System Control Space regardless
of the value of the ENABLE bit.
When the ENABLE bit is set, at least one region of the memory map must be enabled for the system
to function unless the PRIVDEFEN bit is set. If the PRIVDEFEN bit is set and no regions are enabled,
then only privileged software can operate.
When the ENABLE bit is clear, the system uses the default memory map, which has the same
memory attributes as if the MPU is not implemented (see Table 2-5 on page 81 for more information).
The default memory map applies to accesses from both privileged and unprivileged software.
When the MPU is enabled, accesses to the System Control Space and vector table are always
permitted. Other areas are accessible based on regions and whether PRIVDEFEN is set.
Unless HFNMIENA is set, the MPU is not enabled when the processor is executing the handler for
an exception with priority –1 or –2. These priorities are only possible when handling a hard fault or
NMI exception or when FAULTMASK is enabled. Setting the HFNMIENA bit enables the MPU when
operating with these two priorities.
MPU Control (MPUCTRL)
Base 0xE000.E000
Offset 0xD94
Type RW, reset 0x0000.0000
31
30
29
28
27
26
25
24
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
23
22
21
20
19
18
17
16
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
8
7
6
5
4
3
2
1
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
reserved
Type
Reset
reserved
Type
Reset
RO
0
Bit/Field
Name
Type
Reset
31:3
reserved
RO
0x0000.000
PRIVDEFEN HFNMIENA
RW
0
RW
0
ENABLE
RW
0
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
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Bit/Field
Name
Type
Reset
2
PRIVDEFEN
RW
0
Description
MPU Default Region
This bit enables privileged software access to the default memory map.
Value Description
0
If the MPU is enabled, this bit disables use of the default memory
map. Any memory access to a location not covered by any
enabled region causes a fault.
1
If the MPU is enabled, this bit enables use of the default memory
map as a background region for privileged software accesses.
When this bit is set, the background region acts as if it is region number
-1. Any region that is defined and enabled has priority over this default
map.
If the MPU is disabled, the processor ignores this bit.
1
HFNMIENA
RW
0
MPU Enabled During Faults
This bit controls the operation of the MPU during hard fault, NMI, and
FAULTMASK handlers.
Value Description
0
The MPU is disabled during hard fault, NMI, and FAULTMASK
handlers, regardless of the value of the ENABLE bit.
1
The MPU is enabled during hard fault, NMI, and FAULTMASK
handlers.
When the MPU is disabled and this bit is set, the resulting behavior is
unpredictable.
0
ENABLE
RW
0
MPU Enable
Value Description
0
The MPU is disabled.
1
The MPU is enabled.
When the MPU is disabled and the HFNMIENA bit is set, the resulting
behavior is unpredictable.
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Register 82: MPU Region Number (MPUNUMBER), offset 0xD98
Note:
This register can only be accessed from privileged mode.
The MPUNUMBER register selects which memory region is referenced by the MPU Region Base
Address (MPUBASE) and MPU Region Attribute and Size (MPUATTR) registers. Normally, the
required region number should be written to this register before accessing the MPUBASE or the
MPUATTR register. However, the region number can be changed by writing to the MPUBASE
register with the VALID bit set (see page 176). This write updates the value of the REGION field.
MPU Region Number (MPUNUMBER)
Base 0xE000.E000
Offset 0xD98
Type RW, reset 0x0000.0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
RO
0
RO
0
1
0
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
9
8
7
6
5
4
3
2
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
Bit/Field
Name
Type
Reset
31:3
reserved
RO
0x0000.000
2:0
NUMBER
RW
0x0
NUMBER
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RW
0
RW
0
RW
0
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
MPU Region to Access
This field indicates the MPU region referenced by the MPUBASE and
MPUATTR registers. The MPU supports eight memory regions.
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Register 83: MPU Region Base Address (MPUBASE), offset 0xD9C
Register 84: MPU Region Base Address Alias 1 (MPUBASE1), offset 0xDA4
Register 85: MPU Region Base Address Alias 2 (MPUBASE2), offset 0xDAC
Register 86: MPU Region Base Address Alias 3 (MPUBASE3), offset 0xDB4
Note:
This register can only be accessed from privileged mode.
The MPUBASE register defines the base address of the MPU region selected by the MPU Region
Number (MPUNUMBER) register and can update the value of the MPUNUMBER register. To
change the current region number and update the MPUNUMBER register, write the MPUBASE
register with the VALID bit set.
The ADDR field is bits 31:N of the MPUBASE register. Bits (N-1):5 are reserved. The region size,
as specified by the SIZE field in the MPU Region Attribute and Size (MPUATTR) register, defines
the value of N where:
N = Log2(Region size in bytes)
If the region size is configured to 4 GB in the MPUATTR register, there is no valid ADDR field. In
this case, the region occupies the complete memory map, and the base address is 0x0000.0000.
The base address is aligned to the size of the region. For example, a 64-KB region must be aligned
on a multiple of 64 KB, for example, at 0x0001.0000 or 0x0002.0000.
MPU Region Base Address (MPUBASE)
Base 0xE000.E000
Offset 0xD9C
Type RW, reset 0x0000.0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
RW
0
RW
0
RW
0
RW
0
RW
0
VALID
reserved
RW
0
RW
0
RW
0
RW
0
RW
0
WO
0
RO
0
ADDR
Type
Reset
ADDR
Type
Reset
RW
0
Bit/Field
Name
Type
Reset
31:5
ADDR
RW
0x0000.000
REGION
RW
0
RW
0
RW
0
Description
Base Address Mask
Bits 31:N in this field contain the region base address. The value of N
depends on the region size, as shown above. The remaining bits (N-1):5
are reserved.
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
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Bit/Field
Name
Type
Reset
4
VALID
WO
0
Description
Region Number Valid
Value Description
0
The MPUNUMBER register is not changed and the processor
updates the base address for the region specified in the
MPUNUMBER register and ignores the value of the REGION
field.
1
The MPUNUMBER register is updated with the value of the
REGION field and the base address is updated for the region
specified in the REGION field.
This bit is always read as 0.
3
reserved
RO
0
2:0
REGION
RW
0x0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
Region Number
On a write, contains the value to be written to the MPUNUMBER register.
On a read, returns the current region number in the MPUNUMBER
register.
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Register 87: MPU Region Attribute and Size (MPUATTR), offset 0xDA0
Register 88: MPU Region Attribute and Size Alias 1 (MPUATTR1), offset 0xDA8
Register 89: MPU Region Attribute and Size Alias 2 (MPUATTR2), offset 0xDB0
Register 90: MPU Region Attribute and Size Alias 3 (MPUATTR3), offset 0xDB8
Note:
This register can only be accessed from privileged mode.
The MPUATTR register defines the region size and memory attributes of the MPU region specified
by the MPU Region Number (MPUNUMBER) register and enables that region and any subregions.
The MPUATTR register is accessible using word or halfword accesses with the most-significant
halfword holding the region attributes and the least-significant halfword holds the region size and
the region and subregion enable bits.
The MPU access permission attribute bits, XN, AP, TEX, S, C, and B, control access to the
corresponding memory region. If an access is made to an area of memory without the required
permissions, then the MPU generates a permission fault.
The SIZE field defines the size of the MPU memory region specified by the MPUNUMBER register
as follows:
(Region size in bytes) = 2(SIZE+1)
The smallest permitted region size is 32 bytes, corresponding to a SIZE value of 4. Table
3-10 on page 178 gives example SIZE values with the corresponding region size and value of N in
the MPU Region Base Address (MPUBASE) register.
Table 3-10. Example SIZE Field Values
a
SIZE Encoding
Region Size
Value of N
Note
00100b (0x4)
32 B
5
Minimum permitted size
01001b (0x9)
1 KB
10
-
10011b (0x13)
1 MB
20
-
11101b (0x1D)
1 GB
30
-
11111b (0x1F)
4 GB
No valid ADDR field in MPUBASE; the Maximum possible size
region occupies the complete
memory map.
a. Refers to the N parameter in the MPUBASE register (see page 176).
MPU Region Attribute and Size (MPUATTR)
Base 0xE000.E000
Offset 0xDA0
Type RW, reset 0x0000.0000
31
30
29
28
27
reserved
Type
Reset
26
25
24
23
AP
21
reserved
20
19
18
TEX
17
16
XN
reserved
S
C
B
RO
0
RO
0
RO
0
RW
0
RO
0
RW
0
RW
0
RW
0
RO
0
RO
0
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
RO
0
RO
0
RW
0
RW
0
RW
0
RW
0
SRD
Type
Reset
22
reserved
178
SIZE
RW
0
ENABLE
RW
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Bit/Field
Name
Type
Reset
Description
31:29
reserved
RO
0x00
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
28
XN
RW
0
Instruction Access Disable
Value Description
0
Instruction fetches are enabled.
1
Instruction fetches are disabled.
27
reserved
RO
0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
26:24
AP
RW
0
Access Privilege
For information on using this bit field, see Table 3-5 on page 115.
23:22
reserved
RO
0x0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
21:19
TEX
RW
0x0
Type Extension Mask
For information on using this bit field, see Table 3-3 on page 114.
18
S
RW
0
Shareable
For information on using this bit, see Table 3-3 on page 114.
17
C
RW
0
Cacheable
For information on using this bit, see Table 3-3 on page 114.
16
B
RW
0
Bufferable
For information on using this bit, see Table 3-3 on page 114.
15:8
SRD
RW
0x00
Subregion Disable Bits
Value Description
0
The corresponding subregion is enabled.
1
The corresponding subregion is disabled.
Region sizes of 128 bytes and less do not support subregions. When
writing the attributes for such a region, configure the SRD field as 0x00.
See the section called “Subregions” on page 114 for more information.
7:6
reserved
RO
0x0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
5:1
SIZE
RW
0x0
Region Size Mask
The SIZE field defines the size of the MPU memory region specified by
the MPUNUMBER register. Refer to Table 3-10 on page 178 for more
information.
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Bit/Field
Name
Type
Reset
0
ENABLE
RW
0
Description
Region Enable
Value Description
3.7
0
The region is disabled.
1
The region is enabled.
Floating-Point Unit (FPU) Register Descriptions
This section lists and describes the Floating-Point Unit (FPU) registers, in numerical order by address
offset.
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Register 91: Coprocessor Access Control (CPAC), offset 0xD88
The CPAC register specifies the access privileges for coprocessors.
Coprocessor Access Control (CPAC)
Base 0xE000.E000
Offset 0xD88
Type RW, reset 0x0000.0000
31
30
29
28
RO
0
RO
0
RO
0
RO
0
15
14
13
RO
0
RO
0
RO
0
27
26
25
24
23
22
21
RO
0
RO
0
RO
0
RO
0
RW
0
RW
0
12
11
10
9
8
7
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
reserved
Type
Reset
20
19
18
RW
0
RW
0
RO
0
RO
0
RO
0
RO
0
6
5
4
3
2
1
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
CP11
CP10
17
16
reserved
reserved
Type
Reset
Bit/Field
Name
Type
Reset
Description
31:24
reserved
RO
0x00
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
23:22
CP11
RW
0x00
CP11 Coprocessor Access Privilege
Value Description
0x0
Access Denied
Any attempted access generates a NOCP Usage Fault.
0x1
Privileged Access Only
An unprivileged access generates a NOCP fault.
0x2
Reserved
The result of any access is unpredictable.
0x3
21:20
CP10
RW
0x00
Full Access
CP10 Coprocessor Access Privilege
Value Description
0x0
Access Denied
Any attempted access generates a NOCP Usage Fault.
0x1
Privileged Access Only
An unprivileged access generates a NOCP fault.
0x2
Reserved
The result of any access is unpredictable.
0x3
19:0
reserved
RO
0x00
Full Access
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
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Register 92: Floating-Point Context Control (FPCC), offset 0xF34
The FPCC register sets or returns FPU control data.
Floating-Point Context Control (FPCC)
Base 0xE000.E000
Offset 0xF34
Type RW, reset 0xC000.0000
Type
Reset
31
30
29
28
27
26
25
24
23
ASPEN
LSPEN
RW
1
RW
1
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
8
7
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
21
20
19
18
17
16
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
6
5
4
3
2
1
0
BFRDY
MMRDY
HFRDY
USER
LSPACT
RW
0
RW
0
RW
0
RW
0
RW
0
reserved
reserved
Type
Reset
22
RO
0
MONRDY reserved
Bit/Field
Name
Type
Reset
31
ASPEN
RW
1
RW
0
RO
0
THREAD reserved
RW
0
RO
0
Description
Automatic State Preservation Enable
When set, enables the use of the FRACTV bit in the CONTROL register
on execution of a floating-point instruction. This results in automatic
hardware state preservation and restoration, for floating-point context,
on exception entry and exit.
Important:
30
LSPEN
RW
1
Two bits control when FPCA can be enabled: the ASPEN
bit in the Floating-Point Context Control (FPCC)
register and the DISFPCA bit in the Auxiliary Control
(ACTLR) register.
Lazy State Preservation Enable
When set, enables automatic lazy state preservation for floating-point
context.
29:9
reserved
RO
0x00
8
MONRDY
RW
0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
Monitor Ready
When set, DebugMonitor is enabled and priority permits setting
MON_PEND when the floating-point stack frame was allocated.
7
reserved
RO
0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
6
BFRDY
RW
0
Bus Fault Ready
When set, BusFault is enabled and priority permitted setting the BusFault
handler to the pending state when the floating-point stack frame was
allocated.
5
MMRDY
RW
0
Memory Management Fault Ready
When set, MemManage is enabled and priority permitted setting the
MemManage handler to the pending state when the floating-point stack
frame was allocated.
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Bit/Field
Name
Type
Reset
4
HFRDY
RW
0
Description
Hard Fault Ready
When set, priority permitted setting the HardFault handler to the pending
state when the floating-point stack frame was allocated.
3
THREAD
RW
0
Thread Mode
When set, mode was Thread Mode when the floating-point stack frame
was allocated.
2
reserved
RO
0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
1
USER
RW
0
User Privilege Level
When set, privilege level was user when the floating-point stack frame
was allocated.
0
LSPACT
RW
0
Lazy State Preservation Active
When set, Lazy State preservation is active. Floating-point stack frame
has been allocated but saving state to it has been deferred.
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Register 93: Floating-Point Context Address (FPCA), offset 0xF38
The FPCA register holds the location of the unpopulated floating-point register space allocated on
an exception stack frame.
Floating-Point Context Address (FPCA)
Base 0xE000.E000
Offset 0xF38
Type RW, reset 31
30
29
28
27
26
25
24
RW
-
RW
-
RW
-
RW
-
RW
-
RW
-
RW
-
RW
-
15
14
13
12
11
10
9
RW
-
RW
-
RW
-
RW
-
RW
-
RW
-
23
22
21
20
19
18
17
16
RW
-
RW
-
RW
-
RW
-
RW
-
RW
-
RW
-
RW
-
8
7
6
5
4
3
2
1
0
RW
-
RW
-
RW
-
RW
-
RW
-
RW
-
RO
0
ADDRESS
Type
Reset
ADDRESS
Type
Reset
RW
-
Bit/Field
Name
Type
Reset
31:3
ADDRESS
RW
-
reserved
RO
0
RO
0
Description
Address
The location of the unpopulated floating-point register space allocated
on an exception stack frame.
2:0
reserved
RO
0x00
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
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Register 94: Floating-Point Default Status Control (FPDSC), offset 0xF3C
The FPDSC register holds the default values for the Floating-Point Status Control (FPSC) register.
Floating-Point Default Status Control (FPDSC)
Base 0xE000.E000
Offset 0xF3C
Type RW, reset 0x0000.0000
31
30
RO
0
RO
0
15
RO
0
29
28
27
26
AHP
DN
FZ
RO
0
RO
0
RO
0
RW
-
RW
-
RW
-
14
13
12
11
10
9
8
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
reserved
Type
Reset
25
24
23
22
21
20
19
RW
-
17
16
RW
-
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
7
6
5
4
3
2
1
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RMODE
18
reserved
reserved
Type
Reset
Bit/Field
Name
Type
Reset
Description
31:27
reserved
RO
0x00
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
26
AHP
RW
-
AHP Bit Default
This bit holds the default value for the AHP bit in the FPSC register.
25
DN
RW
-
DN Bit Default
This bit holds the default value for the DN bit in the FPSC register.
24
FZ
RW
-
FZ Bit Default
This bit holds the default value for the FZ bit in the FPSC register.
23:22
RMODE
RW
-
RMODE Bit Default
This bit holds the default value for the RMODE bit field in the FPSC
register.
Value Description
21:0
reserved
RO
0x00
0x0
Round to Nearest (RN) mode
0x1
Round towards Plus Infinity (RP) mode
0x2
Round towards Minus Infinity (RM) mode
0x3
Round towards Zero (RZ) mode
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
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JTAG Interface
4
JTAG Interface
The Joint Test Action Group (JTAG) port is an IEEE standard that defines a Test Access Port and
Boundary Scan Architecture for digital integrated circuits and provides a standardized serial interface
for controlling the associated test logic. The TAP, Instruction Register (IR), and Data Registers (DR)
can be used to test the interconnections of assembled printed circuit boards and obtain manufacturing
information on the components. The JTAG Port also provides a means of accessing and controlling
design-for-test features such as I/O pin observation and control, scan testing, and debugging.
The JTAG port is comprised of four pins: TCK, TMS, TDI, and TDO. Data is transmitted serially into
the controller on TDI and out of the controller on TDO. The interpretation of this data is dependent
on the current state of the TAP controller. For detailed information on the operation of the JTAG
port and TAP controller, please refer to the IEEE Standard 1149.1-Test Access Port and
Boundary-Scan Architecture.
The TM4C1230C3PM JTAG controller works with the ARM JTAG controller built into the Cortex-M4F
core by multiplexing the TDO outputs from both JTAG controllers. ARM JTAG instructions select the
ARM TDO output while JTAG instructions select the TDO output. The multiplexer is controlled by the
JTAG controller, which has comprehensive programming for the ARM, Tiva™ C Series
microcontroller, and unimplemented JTAG instructions.
The TM4C1230C3PM JTAG module has the following features:
■ IEEE 1149.1-1990 compatible Test Access Port (TAP) controller
■ Four-bit Instruction Register (IR) chain for storing JTAG instructions
■ IEEE standard instructions: BYPASS, IDCODE, SAMPLE/PRELOAD, and EXTEST
■ ARM additional instructions: APACC, DPACC and ABORT
■ Integrated ARM Serial Wire Debug (SWD)
– Serial Wire JTAG Debug Port (SWJ-DP)
– Flash Patch and Breakpoint (FPB) unit for implementing breakpoints
– Data Watchpoint and Trace (DWT) unit for implementing watchpoints, trigger resources, and
system profiling
– Instrumentation Trace Macrocell (ITM) for support of printf style debugging
– Embedded Trace Macrocell (ETM) for instruction trace capture
– Trace Port Interface Unit (TPIU) for bridging to a Trace Port Analyzer
See the ARM® Debug Interface V5 Architecture Specification for more information on the ARM
JTAG controller.
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4.1
Block Diagram
Figure 4-1. JTAG Module Block Diagram
TCK
TMS
TAP Controller
TDI
Instruction Register (IR)
BYPASS Data Register
TDO
Boundary Scan Data Register
IDCODE Data Register
ABORT Data Register
DPACC Data Register
APACC Data Register
Cortex-M4F
Debug
Port
4.2
Signal Description
The following table lists the external signals of the JTAG/SWD controller and describes the function
of each. The JTAG/SWD controller signals are alternate functions for some GPIO signals, however
note that the reset state of the pins is for the JTAG/SWD function. The JTAG/SWD controller signals
are under commit protection and require a special process to be configured as GPIOs, see “Commit
Control” on page 577. The column in the table below titled "Pin Mux/Pin Assignment" lists the GPIO
pin placement for the JTAG/SWD controller signals. The AFSEL bit in the GPIO Alternate Function
Select (GPIOAFSEL) register (page 592) is set to choose the JTAG/SWD function. The number in
parentheses is the encoding that must be programmed into the PMCn field in the GPIO Port Control
(GPIOPCTL) register (page 609) to assign the JTAG/SWD controller signals to the specified GPIO
port pin. For more information on configuring GPIOs, see “General-Purpose Input/Outputs
(GPIOs)” on page 570.
Table 4-1. JTAG_SWD_SWO Signals (64LQFP)
Pin Name
Pin Number Pin Mux / Pin
Assignment
a
Pin Type
Buffer Type
Description
SWCLK
52
PC0 (1)
I
TTL
JTAG/SWD CLK.
SWDIO
51
PC1 (1)
I/O
TTL
JTAG TMS and SWDIO.
SWO
49
PC3 (1)
O
TTL
JTAG TDO and SWO.
TCK
52
PC0 (1)
I
TTL
JTAG/SWD CLK.
TDI
50
PC2 (1)
I
TTL
JTAG TDI.
TDO
49
PC3 (1)
O
TTL
JTAG TDO and SWO.
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Table 4-1. JTAG_SWD_SWO Signals (64LQFP) (continued)
Pin Name
Pin Number Pin Mux / Pin
Assignment
51
TMS
PC1 (1)
a
Pin Type
Buffer Type
I
TTL
Description
JTAG TMS and SWDIO.
a. The TTL designation indicates the pin has TTL-compatible voltage levels.
4.3
Functional Description
A high-level conceptual drawing of the JTAG module is shown in Figure 4-1 on page 187. The JTAG
module is composed of the Test Access Port (TAP) controller and serial shift chains with parallel
update registers. The TAP controller is a simple state machine controlled by the TCK and TMS inputs.
The current state of the TAP controller depends on the sequence of values captured on TMS at the
rising edge of TCK. The TAP controller determines when the serial shift chains capture new data,
shift data from TDI towards TDO, and update the parallel load registers. The current state of the
TAP controller also determines whether the Instruction Register (IR) chain or one of the Data Register
(DR) chains is being accessed.
The serial shift chains with parallel load registers are comprised of a single Instruction Register (IR)
chain and multiple Data Register (DR) chains. The current instruction loaded in the parallel load
register determines which DR chain is captured, shifted, or updated during the sequencing of the
TAP controller.
Some instructions, like EXTEST, operate on data currently in a DR chain and do not capture, shift,
or update any of the chains. Instructions that are not implemented decode to the BYPASS instruction
to ensure that the serial path between TDI and TDO is always connected (see Table 4-3 on page 194
for a list of implemented instructions).
See “JTAG and Boundary Scan” on page 1060 for JTAG timing diagrams.
Note:
4.3.1
Of all the possible reset sources, only Power-On reset (POR) and the assertion of the RST
input have any effect on the JTAG module. The pin configurations are reset by both the
RST input and POR, whereas the internal JTAG logic is only reset with POR. See “Reset
Sources” on page 199 for more information on reset.
JTAG Interface Pins
The JTAG interface consists of four standard pins: TCK, TMS, TDI, and TDO. These pins and their
associated state after a power-on reset or reset caused by the RST input are given in Table 4-2.
Detailed information on each pin follows.
Note:
The following pins are configured as JTAG port pins out of reset. Refer to “General-Purpose
Input/Outputs (GPIOs)” on page 570 for information on how to reprogram the configuration
of these pins.
Table 4-2. JTAG Port Pins State after Power-On Reset or RST assertion
Pin Name
Data Direction
Internal Pull-Up
Internal Pull-Down
Drive Strength
Drive Value
TCK
Input
Enabled
Disabled
N/A
N/A
TMS
Input
Enabled
Disabled
N/A
N/A
TDI
Input
Enabled
Disabled
N/A
N/A
TDO
Output
Enabled
Disabled
2-mA driver
High-Z
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4.3.1.1
Test Clock Input (TCK)
The TCK pin is the clock for the JTAG module. This clock is provided so the test logic can operate
independently of any other system clocks and to ensure that multiple JTAG TAP controllers that
are daisy-chained together can synchronously communicate serial test data between components.
During normal operation, TCK is driven by a free-running clock with a nominal 50% duty cycle. When
necessary, TCK can be stopped at 0 or 1 for extended periods of time. While TCK is stopped at 0
or 1, the state of the TAP controller does not change and data in the JTAG Instruction and Data
Registers is not lost.
By default, the internal pull-up resistor on the TCK pin is enabled after reset, assuring that no clocking
occurs if the pin is not driven from an external source. The internal pull-up and pull-down resistors
can be turned off to save internal power as long as the TCK pin is constantly being driven by an
external source (see page 598 and page 600).
4.3.1.2
Test Mode Select (TMS)
The TMS pin selects the next state of the JTAG TAP controller. TMS is sampled on the rising edge
of TCK. Depending on the current TAP state and the sampled value of TMS, the next state may be
entered. Because the TMS pin is sampled on the rising edge of TCK, the IEEE Standard 1149.1
expects the value on TMS to change on the falling edge of TCK.
Holding TMS high for five consecutive TCK cycles drives the TAP controller state machine to the
Test-Logic-Reset state. When the TAP controller enters the Test-Logic-Reset state, the JTAG
module and associated registers are reset to their default values. This procedure should be performed
to initialize the JTAG controller. The JTAG Test Access Port state machine can be seen in its entirety
in Figure 4-2 on page 190.
By default, the internal pull-up resistor on the TMS pin is enabled after reset. Changes to the pull-up
resistor settings on GPIO Port C should ensure that the internal pull-up resistor remains enabled
on PC1/TMS; otherwise JTAG communication could be lost (see page 598).
4.3.1.3
Test Data Input (TDI)
The TDI pin provides a stream of serial information to the IR chain and the DR chains. TDI is
sampled on the rising edge of TCK and, depending on the current TAP state and the current
instruction, may present this data to the proper shift register chain. Because the TDI pin is sampled
on the rising edge of TCK, the IEEE Standard 1149.1 expects the value on TDI to change on the
falling edge of TCK.
By default, the internal pull-up resistor on the TDI pin is enabled after reset. Changes to the pull-up
resistor settings on GPIO Port C should ensure that the internal pull-up resistor remains enabled
on PC2/TDI; otherwise JTAG communication could be lost (see page 598).
4.3.1.4
Test Data Output (TDO)
The TDO pin provides an output stream of serial information from the IR chain or the DR chains.
The value of TDO depends on the current TAP state, the current instruction, and the data in the
chain being accessed. In order to save power when the JTAG port is not being used, the TDO pin
is placed in an inactive drive state when not actively shifting out data. Because TDO can be connected
to the TDI of another controller in a daisy-chain configuration, the IEEE Standard 1149.1 expects
the value on TDO to change on the falling edge of TCK.
By default, the internal pull-up resistor on the TDO pin is enabled after reset, assuring that the pin
remains at a constant logic level when the JTAG port is not being used. The internal pull-up and
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pull-down resistors can be turned off to save internal power if a High-Z output value is acceptable
during certain TAP controller states (see page 598 and page 600).
4.3.2
JTAG TAP Controller
The JTAG TAP controller state machine is shown in Figure 4-2. The TAP controller state machine
is reset to the Test-Logic-Reset state on the assertion of a Power-On-Reset (POR). In order to reset
the JTAG module after the microcontroller has been powered on, the TMS input must be held HIGH
for five TCK clock cycles, resetting the TAP controller and all associated JTAG chains. Asserting
the correct sequence on the TMS pin allows the JTAG module to shift in new instructions, shift in
data, or idle during extended testing sequences. For detailed information on the function of the TAP
controller and the operations that occur in each state, please refer to IEEE Standard 1149.1.
Figure 4-2. Test Access Port State Machine
Test Logic Reset
1
0
Run Test Idle
0
Select DR Scan
1
Select IR Scan
1
0
1
Capture DR
1
Capture IR
0
0
Shift DR
Shift IR
0
1
Exit 1 DR
Exit 1 IR
1
Pause IR
0
1
Exit 2 DR
0
1
0
Exit 2 IR
1
1
Update DR
4.3.3
1
0
Pause DR
1
0
1
0
0
1
0
0
Update IR
1
0
Shift Registers
The Shift Registers consist of a serial shift register chain and a parallel load register. The serial shift
register chain samples specific information during the TAP controller's CAPTURE states and allows
this information to be shifted out on TDO during the TAP controller's SHIFT states. While the sampled
data is being shifted out of the chain on TDO, new data is being shifted into the serial shift register
on TDI. This new data is stored in the parallel load register during the TAP controller's UPDATE
states. Each of the shift registers is discussed in detail in “Register Descriptions” on page 194.
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4.3.4
Operational Considerations
Certain operational parameters must be considered when using the JTAG module. Because the
JTAG pins can be programmed to be GPIOs, board configuration and reset conditions on these
pins must be considered. In addition, because the JTAG module has integrated ARM Serial Wire
Debug, the method for switching between these two operational modes is described below.
4.3.4.1
GPIO Functionality
When the microcontroller is reset with either a POR or RST, the JTAG/SWD port pins default to their
JTAG/SWD configurations. The default configuration includes enabling digital functionality (DEN[3:0]
set in the Port C GPIO Digital Enable (GPIODEN) register), enabling the pull-up resistors (PUE[3:0]
set in the Port C GPIO Pull-Up Select (GPIOPUR) register), disabling the pull-down resistors
(PDE[3:0] cleared in the Port C GPIO Pull-Down Select (GPIOPDR) register) and enabling the
alternate hardware function (AFSEL[3:0] set in the Port C GPIO Alternate Function Select
(GPIOAFSEL) register) on the JTAG/SWD pins. See page 592, page 598, page 600, and page 603.
It is possible for software to configure these pins as GPIOs after reset by clearing AFSEL[3:0] in
the Port C GPIOAFSEL register. If the user does not require the JTAG/SWD port for debugging or
board-level testing, this provides four more GPIOs for use in the design.
Caution – It is possible to create a software sequence that prevents the debugger from connecting to
the TM4C1230C3PM microcontroller. If the program code loaded into flash immediately changes the
JTAG pins to their GPIO functionality, the debugger may not have enough time to connect and halt
the controller before the JTAG pin functionality switches. As a result, the debugger may be locked out
of the part. This issue can be avoided with a software routine that restores JTAG functionality based
on an external or software trigger. In the case that the software routine is not implemented and the
device is locked out of the part, this issue can be solved by using the TM4C1230C3PM Flash Programmer
"Unlock" feature. Please refer to LMFLASHPROGRAMMER on the TI web for more information.
The GPIO commit control registers provide a layer of protection against accidental programming of
critical hardware peripherals. Protection is provided for the GPIO pins that can be used as the four
JTAG/SWD pins and the NMI pin (see “Signal Tables” on page 1032 for pin numbers). Writes to
protected bits of the GPIO Alternate Function Select (GPIOAFSEL) register (see page 592), GPIO
Pull Up Select (GPIOPUR) register (see page 598), GPIO Pull-Down Select (GPIOPDR) register
(see page 600), and GPIO Digital Enable (GPIODEN) register (see page 603) are not committed to
storage unless the GPIO Lock (GPIOLOCK) register (see page 605) has been unlocked and the
appropriate bits of the GPIO Commit (GPIOCR) register (see page 606) have been set.
4.3.4.2
Communication with JTAG/SWD
Because the debug clock and the system clock can be running at different frequencies, care must
be taken to maintain reliable communication with the JTAG/SWD interface. In the Capture-DR state,
the result of the previous transaction, if any, is returned, together with a 3-bit ACK response. Software
should check the ACK response to see if the previous operation has completed before initiating a
new transaction. Alternatively, if the system clock is at least 8 times faster than the debug clock
(TCK or SWCLK), the previous operation has enough time to complete and the ACK bits do not have
to be checked.
4.3.4.3
Recovering a "Locked" Microcontroller
Note:
Performing the sequence below restores the non-volatile registers discussed in “Non-Volatile
Register Programming” on page 454 to their factory default values. The mass erase of the
Flash memory caused by the sequence below occurs prior to the non-volatile registers
being restored.
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In addition, the EEPROM is erased and its wear-leveling counters are returned to factory
default values when performing the sequence below.
If software configures any of the JTAG/SWD pins as GPIO and loses the ability to communicate
with the debugger, there is a debug port unlock sequence that can be used to recover the
microcontroller. Performing a total of ten JTAG-to-SWD and SWD-to-JTAG switch sequences while
holding the microcontroller in reset mass erases the Flash memory. The debug port unlock sequence
is:
1. Assert and hold the RST signal.
2. Apply power to the device.
3. Perform steps 1 and 2 of the JTAG-to-SWD switch sequence on the section called “JTAG-to-SWD
Switching” on page 193.
4. Perform steps 1 and 2 of the SWD-to-JTAG switch sequence on the section called “SWD-to-JTAG
Switching” on page 193.
5. Perform steps 1 and 2 of the JTAG-to-SWD switch sequence.
6. Perform steps 1 and 2 of the SWD-to-JTAG switch sequence.
7. Perform steps 1 and 2 of the JTAG-to-SWD switch sequence.
8. Perform steps 1 and 2 of the SWD-to-JTAG switch sequence.
9. Perform steps 1 and 2 of the JTAG-to-SWD switch sequence.
10. Perform steps 1 and 2 of the SWD-to-JTAG switch sequence.
11. Perform steps 1 and 2 of the JTAG-to-SWD switch sequence.
12. Perform steps 1 and 2 of the SWD-to-JTAG switch sequence.
13. Release the RST signal.
14. Wait 400 ms.
15. Power-cycle the microcontroller.
4.3.4.4
ARM Serial Wire Debug (SWD)
In order to seamlessly integrate the ARM Serial Wire Debug (SWD) functionality, a serial-wire
debugger must be able to connect to the Cortex-M4F core without having to perform, or have any
knowledge of, JTAG cycles. This integration is accomplished with a SWD preamble that is issued
before the SWD session begins.
The switching preamble used to enable the SWD interface of the SWJ-DP module starts with the
TAP controller in the Test-Logic-Reset state. From here, the preamble sequences the TAP controller
through the following states: Run Test Idle, Select DR, Select IR, Test Logic Reset, Test Logic
Reset, Run Test Idle, Run Test Idle, Select DR, Select IR, Test Logic Reset, Test Logic Reset, Run
Test Idle, Run Test Idle, Select DR, Select IR, and Test Logic Reset states.
Stepping through this sequence of the TAP state machine enables the SWD interface and disables
the JTAG interface. For more information on this operation and the SWD interface, see the ARM®
Debug Interface V5 Architecture Specification.
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Because this sequence is a valid series of JTAG operations that could be issued, the ARM JTAG
TAP controller is not fully compliant to the IEEE Standard 1149.1. This instance is the only one
where the ARM JTAG TAP controller does not meet full compliance with the specification. Due to
the low probability of this sequence occurring during normal operation of the TAP controller, it should
not affect normal performance of the JTAG interface.
JTAG-to-SWD Switching
To switch the operating mode of the Debug Access Port (DAP) from JTAG to SWD mode, the
external debug hardware must send the switching preamble to the microcontroller. The 16-bit
TMS/SWDIO command for switching to SWD mode is defined as b1110.0111.1001.1110, transmitted
LSB first. This command can also be represented as 0xE79E when transmitted LSB first. The
complete switch sequence should consist of the following transactions on the TCK/SWCLK and
TMS/SWDIO signals:
1. Send at least 50 TCK/SWCLK cycles with TMS/SWDIO High to ensure that both JTAG and SWD
are in their reset states.
2. Send the 16-bit JTAG-to-SWD switch command, 0xE79E, on TMS/SWDIO.
3. Send at least 50 TCK/SWCLK cycles with TMS/SWDIO High to ensure that if SWJ-DP was already
in SWD mode before sending the switch sequence, the SWD goes into the line reset state.
To verify that the Debug Access Port (DAP) has switched to the Serial Wire Debug (SWD) operating
mode, perform a SWD READID operation. The ID value can be compared against the device's
known ID to verify the switch.
SWD-to-JTAG Switching
To switch the operating mode of the Debug Access Port (DAP) from SWD to JTAG mode, the
external debug hardware must send a switch command to the microcontroller. The 16-bit TMS/SWDIO
command for switching to JTAG mode is defined as b1110.0111.0011.1100, transmitted LSB first.
This command can also be represented as 0xE73C when transmitted LSB first. The complete switch
sequence should consist of the following transactions on the TCK/SWCLK and TMS/SWDIO signals:
1. Send at least 50 TCK/SWCLK cycles with TMS/SWDIO High to ensure that both JTAG and SWD
are in their reset states.
2. Send the 16-bit SWD-to-JTAG switch command, 0xE73C, on TMS/SWDIO.
3. Send at least 50 TCK/SWCLK cycles with TMS/SWDIO High to ensure that if SWJ-DP was already
in JTAG mode before sending the switch sequence, the JTAG goes into the Test Logic Reset
state.
To verify that the Debug Access Port (DAP) has switched to the JTAG operating mode, set the
JTAG Instruction Register (IR) to the IDCODE instruction and shift out the Data Register (DR). The
DR value can be compared against the device's known IDCODE to verify the switch.
4.4
Initialization and Configuration
After a Power-On-Reset or an external reset (RST), the JTAG pins are automatically configured for
JTAG communication. No user-defined initialization or configuration is needed. However, if the user
application changes these pins to their GPIO function, they must be configured back to their JTAG
functionality before JTAG communication can be restored. To return the pins to their JTAG functions,
enable the four JTAG pins (PC[3:0]) for their alternate function using the GPIOAFSEL register.
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In addition to enabling the alternate functions, any other changes to the GPIO pad configurations
on the four JTAG pins (PC[3:0]) should be returned to their default settings.
4.5
Register Descriptions
The registers in the JTAG TAP Controller or Shift Register chains are not memory mapped and are
not accessible through the on-chip Advanced Peripheral Bus (APB). Instead, the registers within
the JTAG controller are all accessed serially through the TAP Controller. These registers include
the Instruction Register and the six Data Registers.
4.5.1
Instruction Register (IR)
The JTAG TAP Instruction Register (IR) is a four-bit serial scan chain connected between the JTAG
TDI and TDO pins with a parallel load register. When the TAP Controller is placed in the correct
states, bits can be shifted into the IR. Once these bits have been shifted into the chain and updated,
they are interpreted as the current instruction. The decode of the IR bits is shown in Table 4-3. A
detailed explanation of each instruction, along with its associated Data Register, follows.
Table 4-3. JTAG Instruction Register Commands
4.5.1.1
IR[3:0]
Instruction
0x0
EXTEST
0x2
SAMPLE / PRELOAD
Description
Drives the values preloaded into the Boundary Scan Chain by the
SAMPLE/PRELOAD instruction onto the pads.
Captures the current I/O values and shifts the sampled values out of the
Boundary Scan Chain while new preload data is shifted in.
0x8
ABORT
Shifts data into the ARM Debug Port Abort Register.
0xA
DPACC
Shifts data into and out of the ARM DP Access Register.
0xB
APACC
Shifts data into and out of the ARM AC Access Register.
0xE
IDCODE
Loads manufacturing information defined by the IEEE Standard 1149.1 into
the IDCODE chain and shifts it out.
0xF
BYPASS
Connects TDI to TDO through a single Shift Register chain.
All Others
Reserved
Defaults to the BYPASS instruction to ensure that TDI is always connected
to TDO.
EXTEST Instruction
The EXTEST instruction is not associated with its own Data Register chain. Instead, the EXTEST
instruction uses the data that has been preloaded into the Boundary Scan Data Register using the
SAMPLE/PRELOAD instruction. When the EXTEST instruction is present in the Instruction Register,
the preloaded data in the Boundary Scan Data Register associated with the outputs and output
enables are used to drive the GPIO pads rather than the signals coming from the core. With tests
that drive known values out of the controller, this instruction can be used to verify connectivity. While
the EXTEST instruction is present in the Instruction Register, the Boundary Scan Data Register can
be accessed to sample and shift out the current data and load new data into the Boundary Scan
Data Register.
4.5.1.2
SAMPLE/PRELOAD Instruction
The SAMPLE/PRELOAD instruction connects the Boundary Scan Data Register chain between
TDI and TDO. This instruction samples the current state of the pad pins for observation and preloads
new test data. Each GPIO pad has an associated input, output, and output enable signal. When the
TAP controller enters the Capture DR state during this instruction, the input, output, and output-enable
signals to each of the GPIO pads are captured. These samples are serially shifted out on TDO while
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the TAP controller is in the Shift DR state and can be used for observation or comparison in various
tests.
While these samples of the inputs, outputs, and output enables are being shifted out of the Boundary
Scan Data Register, new data is being shifted into the Boundary Scan Data Register from TDI.
Once the new data has been shifted into the Boundary Scan Data Register, the data is saved in the
parallel load registers when the TAP controller enters the Update DR state. This update of the
parallel load register preloads data into the Boundary Scan Data Register that is associated with
each input, output, and output enable. This preloaded data can be used with the EXTEST instruction
to drive data into or out of the controller. See “Boundary Scan Data Register” on page 196 for more
information.
4.5.1.3
ABORT Instruction
The ABORT instruction connects the associated ABORT Data Register chain between TDI and
TDO. This instruction provides read and write access to the ABORT Register of the ARM Debug
Access Port (DAP). Shifting the proper data into this Data Register clears various error bits or initiates
a DAP abort of a previous request. See the “ABORT Data Register” on page 197 for more information.
4.5.1.4
DPACC Instruction
The DPACC instruction connects the associated DPACC Data Register chain between TDI and
TDO. This instruction provides read and write access to the DPACC Register of the ARM Debug
Access Port (DAP). Shifting the proper data into this register and reading the data output from this
register allows read and write access to the ARM debug and status registers. See “DPACC Data
Register” on page 197 for more information.
4.5.1.5
APACC Instruction
The APACC instruction connects the associated APACC Data Register chain between TDI and
TDO. This instruction provides read and write access to the APACC Register of the ARM Debug
Access Port (DAP). Shifting the proper data into this register and reading the data output from this
register allows read and write access to internal components and buses through the Debug Port.
See “APACC Data Register” on page 197 for more information.
4.5.1.6
IDCODE Instruction
The IDCODE instruction connects the associated IDCODE Data Register chain between TDI and
TDO. This instruction provides information on the manufacturer, part number, and version of the
ARM core. This information can be used by testing equipment and debuggers to automatically
configure input and output data streams. IDCODE is the default instruction loaded into the JTAG
Instruction Register when a Power-On-Reset (POR) is asserted, or the Test-Logic-Reset state is
entered. See “IDCODE Data Register” on page 196 for more information.
4.5.1.7
BYPASS Instruction
The BYPASS instruction connects the associated BYPASS Data Register chain between TDI and
TDO. This instruction is used to create a minimum length serial path between the TDI and TDO ports.
The BYPASS Data Register is a single-bit shift register. This instruction improves test efficiency by
allowing components that are not needed for a specific test to be bypassed in the JTAG scan chain
by loading them with the BYPASS instruction. See “BYPASS Data Register” on page 196 for more
information.
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4.5.2
Data Registers
The JTAG module contains six Data Registers. These serial Data Register chains include: IDCODE,
BYPASS, Boundary Scan, APACC, DPACC, and ABORT and are discussed in the following sections.
4.5.2.1
IDCODE Data Register
The format for the 32-bit IDCODE Data Register defined by the IEEE Standard 1149.1 is shown in
Figure 4-3. The standard requires that every JTAG-compliant microcontroller implement either the
IDCODE instruction or the BYPASS instruction as the default instruction. The LSB of the IDCODE
Data Register is defined to be a 1 to distinguish it from the BYPASS instruction, which has an LSB
of 0. This definition allows auto-configuration test tools to determine which instruction is the default
instruction.
The major uses of the JTAG port are for manufacturer testing of component assembly and program
development and debug. To facilitate the use of auto-configuration debug tools, the IDCODE
instruction outputs a value of 0x4BA0.0477. This value allows the debuggers to automatically
configure themselves to work correctly with the Cortex-M4F during debug.
Figure 4-3. IDCODE Register Format
31
TDI
4.5.2.2
28 27
12 11
Version
Part Number
1 0
Manufacturer ID
1
TDO
BYPASS Data Register
The format for the 1-bit BYPASS Data Register defined by the IEEE Standard 1149.1 is shown in
Figure 4-4. The standard requires that every JTAG-compliant microcontroller implement either the
BYPASS instruction or the IDCODE instruction as the default instruction. The LSB of the BYPASS
Data Register is defined to be a 0 to distinguish it from the IDCODE instruction, which has an LSB
of 1. This definition allows auto-configuration test tools to determine which instruction is the default
instruction.
Figure 4-4. BYPASS Register Format
0
TDI
4.5.2.3
0
TDO
Boundary Scan Data Register
The format of the Boundary Scan Data Register is shown in Figure 4-5. Each GPIO pin, starting
with a GPIO pin next to the JTAG port pins, is included in the Boundary Scan Data Register. Each
GPIO pin has three associated digital signals that are included in the chain. These signals are input,
output, and output enable, and are arranged in that order as shown in the figure.
When the Boundary Scan Data Register is accessed with the SAMPLE/PRELOAD instruction, the
input, output, and output enable from each digital pad are sampled and then shifted out of the chain
to be verified. The sampling of these values occurs on the rising edge of TCK in the Capture DR
state of the TAP controller. While the sampled data is being shifted out of the Boundary Scan chain
in the Shift DR state of the TAP controller, new data can be preloaded into the chain for use with
the EXTEST instruction. The EXTEST instruction forces data out of the controller.
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Figure 4-5. Boundary Scan Register Format
TDI
I
N
O
U
T
O
E
...
1st GPIO
4.5.2.4
I
N
O
U
T
mth GPIO
O
E
I
N
O
U
T
(m+1)th GPIO
O
E
...
I
N
O
U
T
O
E
TDO
GPIO nth
APACC Data Register
The format for the 35-bit APACC Data Register defined by ARM is described in the ARM® Debug
Interface V5 Architecture Specification.
4.5.2.5
DPACC Data Register
The format for the 35-bit DPACC Data Register defined by ARM is described in the ARM® Debug
Interface V5 Architecture Specification.
4.5.2.6
ABORT Data Register
The format for the 35-bit ABORT Data Register defined by ARM is described in the ARM® Debug
Interface V5 Architecture Specification.
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5
System Control
System control configures the overall operation of the device and provides information about the
device. Configurable features include reset control, NMI operation, power control, clock control, and
low-power modes.
5.1
Signal Description
The following table lists the external signals of the System Control module and describes the function
of each. The NMI signal is the alternate function for two GPIO signals and functions as a GPIO after
reset. The NMI pins are under commit protection and require a special process to be configured as
any alternate function or to subsequently return to the GPIO function, see “Commit
Control” on page 577. The column in the table below titled "Pin Mux/Pin Assignment" lists the GPIO
pin placement for the NMI signal. The AFSEL bit in the GPIO Alternate Function Select
(GPIOAFSEL) register (page 592) should be set to choose the NMI function. The number in
parentheses is the encoding that must be programmed into the PMCn field in the GPIO Port Control
(GPIOPCTL) register (page 609) to assign the NMI signal to the specified GPIO port pin. For more
information on configuring GPIOs, see “General-Purpose Input/Outputs (GPIOs)” on page 570. The
remaining signals (with the word "fixed" in the Pin Mux/Pin Assignment column) have a fixed pin
assignment and function.
Table 5-1. System Control & Clocks Signals (64LQFP)
Pin Name
Pin Number Pin Mux / Pin
Assignment
a
Pin Type
Buffer Type
Description
NMI
10
28
PD7 (8)
PF0 (8)
I
TTL
Non-maskable interrupt.
OSC0
40
fixed
I
Analog
Main oscillator crystal input or an external clock
reference input.
OSC1
41
fixed
O
Analog
Main oscillator crystal output. Leave unconnected
when using a single-ended clock source.
RST
38
fixed
I
TTL
System reset input.
a. The TTL designation indicates the pin has TTL-compatible voltage levels.
5.2
Functional Description
The System Control module provides the following capabilities:
■ Device identification, see “Device Identification” on page 198
■ Local control, such as reset (see “Reset Control” on page 199), power (see “Power
Control” on page 204) and clock control (see “Clock Control” on page 205)
■ System control (Run, Sleep, and Deep-Sleep modes), see “System Control” on page 211
5.2.1
Device Identification
Several read-only registers provide software with information on the microcontroller, such as version,
part number, memory sizes, and peripherals present on the device. The Device Identification 0
(DID0) (page 221) and Device Identification 1 (DID1) (page 223) registers provide details about the
device's version, package, temperature range, and so on. The Peripheral Present registers starting
at System Control offset 0x300, such as the Watchdog Timer Peripheral Present (PPWD) register,
provide information on how many of each type of module are included on the device. Finally,
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information about the capabilities of the on-chip peripherals are provided at offset 0xFC0 in each
peripheral's register space in the Peripheral Properties registers, such as the GPTM Peripheral
Properties (GPTMPP) register. Previous devices used the Device Capabilities (DC0-DC9) registers
for information about the peripherals and their capabilities. These registers are present on this device
for backward software capability, but provide no information about peripherals that were not available
on older devices.
5.2.2
Reset Control
This section discusses aspects of hardware functions during reset as well as system software
requirements following the reset sequence.
5.2.2.1
Reset Sources
The TM4C1230C3PM microcontroller has six sources of reset:
1. Power-on reset (POR) (see page 200).
2. External reset input pin (RST) assertion (see page 201).
3. A brown-out detection that can be caused by any of the following events: (see page 202).
■ V DD under BOR0. The trigger value is the highest VDD voltage level for BOR0.
■ VDD under BOR1. The trigger value is the highest VDD voltage level for BOR1.
4. Software-initiated reset (with the software reset registers) (see page 203).
5. A watchdog timer reset condition violation (see page 203).
6. MOSC failure (see page 204).
Table 5-2 provides a summary of results of the various reset operations.
Table 5-2. Reset Sources
Core Reset?
JTAG Reset?
On-Chip Peripherals Reset?
Power-On Reset
Reset Source
Yes
Yes
Yes
RST
Yes
Pin Config Only
Yes
Brown-Out Reset
Yes
Pin Config Only
Yes
Software System Request
Reset using the SYSRESREQ
bit in the APINT register.
Yes
Pin Config Only
Yes
Software System Request
Reset using the VECTRESET
bit in the APINT register.
Yes
Pin Config Only
No
Software Peripheral Reset
No
Pin Config Only
Yes
Watchdog Reset
Yes
Pin Config Only
Yes
MOSC Failure Reset
Yes
Pin Config Only
Yes
a
a. Programmable on a module-by-module basis using the Software Reset Control Registers.
After a reset, the Reset Cause (RESC) register is set with the reset cause. The bits in this register
are sticky and maintain their state across multiple reset sequences, except when an internal POR
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is the cause, in which case, all the bits in the RESC register are cleared except for the POR indicator.
A bit in the RESC register can be cleared by writing a 0.
At any reset that resets the core, the user has the opportunity to direct the core to execute the ROM
Boot Loader or the application in Flash memory by using any GPIO signal as configured in the Boot
Configuration (BOOTCFG) register.
At reset, the following sequence is performed:
1. The BOOTCFG register is read. If the EN bit is clear, the ROM Boot Loader is executed.
2. In the ROM Boot Loader, the status of the specified GPIO pin is compared with the specified
polarity. If the status matches the specified polarity, the ROM is mapped to address 0x0000.0000
and execution continues out of the ROM Boot Loader.
3. f then EN bit is set or the status doesn't match the specified polarity, the data at address
0x0000.0004 is read, and if the data at this address is 0xFFFF.FFFF, the ROM is mapped to
address 0x0000.0000 and execution continues out of the ROM Boot Loader.
4. If there is data at address 0x0000.0004 that is not 0xFFFF.FFFF, the stack pointer (SP) is loaded
from Flash memory at address 0x0000.0000 and the program counter (PC) is loaded from
address 0x0000.0004. The user application begins executing.
Note:
If the device fails the initialization phase, it toggles the TDO output pin as an indication the
device is not executing. This feature is provided for debug purposes.
For example, if the BOOTCFG register is written and committed with the value of 0x0000.3C01,
then PB7 is examined at reset to determine if the ROM Boot Loader should be executed. If PB7 is
Low, the core unconditionally begins executing the ROM boot loader. If PB7 is High, then the
application in Flash memory is executed if the reset vector at location 0x0000.0004 is not
0xFFFF.FFFF. Otherwise, the ROM boot loader is executed.
5.2.2.2
Power-On Reset (POR)
Note:
The JTAG controller can only be reset by the power-on reset.
The internal Power-On Reset (POR) circuit monitors the power supply voltage (VDD) and generates
a reset signal to all of the internal logic including JTAG when the power supply ramp reaches a
threshold value (VVDD_POK). The microcontroller must be operating within the specified operating
parameters when the on-chip power-on reset pulse is complete (see “Power and
Brown-Out” on page 1062). For applications that require the use of an external reset signal to hold
the microcontroller in reset longer than the internal POR, the RST input may be used as discussed
in “External RST Pin” on page 201.
The Power-On Reset sequence is as follows:
1. The microcontroller waits for internal POR to go inactive.
2. The internal reset is released and the core loads from memory the initial stack pointer, the initial
program counter, and the first instruction designated by the program counter, and then begins
execution.
The internal POR is only active on the initial power-up of the microcontroller. The Power-On Reset
timing is shown in “Power and Brown-Out” on page 1062.
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5.2.2.3
External RST Pin
Note:
It is recommended that the trace for the RST signal must be kept as short as possible. Be
sure to place any components connected to the RST signal as close to the microcontroller
as possible.
If the application only uses the internal POR circuit, the RST input must be connected to the power
supply (VDD) through an optional pull-up resistor (0 to 100K Ω) as shown in Figure 5-1 on page 201.
The RST input has filtering which requires a minimum pulse width in order for the reset pulse to be
recognized, see Table 20-11 on page 1067.
Figure 5-1. Basic RST Configuration
VDD
Tiva™
Microcontroller
RPU
RST
RPU = 0 to 100 kΩ
The external reset pin (RST) resets the microcontroller including the core and all the on-chip
peripherals. The external reset sequence is as follows:
1. The external reset pin (RST) is asserted for the duration specified by TMIN and then deasserted
(see “Reset” on page 1067).
2. The internal reset is released and the core loads from memory the initial stack pointer, the initial
program counter, and the first instruction designated by the program counter, and then begins
execution.
To improve noise immunity and/or to delay reset at power up, the RST input may be connected to
an RC network as shown in Figure 5-2 on page 201.
Figure 5-2. External Circuitry to Extend Power-On Reset
VDD
Tiva™
Microcontroller
RPU
RST
C1
RPU = 1 kΩ to 100 kΩ
C1 = 1 nF to 10 µF
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If the application requires the use of an external reset switch, Figure 5-3 on page 202 shows the
proper circuitry to use.
Figure 5-3. Reset Circuit Controlled by Switch
VDD
Tiva™
Microcontroller
RPU
RST
C1
RS
Typical RPU = 10 kΩ
Typical RS = 470 Ω
C1 = 10 nF
The RPU and C1 components define the power-on delay.
The external reset timing is shown in Figure 20-11 on page 1068.
5.2.2.4
Brown-Out Reset (BOR)
The microcontroller provides a brown-out detection circuit that triggers if any of the following occur:
■ VDD under BOR0. The external VDD supply voltage is below the specified VDD BOR0 value. The
trigger value is the highest VDD voltage level for BOR0.
■ VDD under BOR1. The external VDD supply voltage is below the specified VDD BOR1 value. The
trigger value is the highest VDD voltage level for BOR1.
The application can identify that a BOR event caused a reset by reading the Reset Cause (RESC)
register. When a brown-out condition is detected, the default condition is to generate a reset. The
BOR events can also be programmed to generate an interrupt by clearing the BOR0 bit or BOR1 bit
in the Power-On and Brown-Out Reset Control (PBORCTL) register.
The brown-out reset sequence is as follows:
1. When VDD drops below VBORnTH, an internal BOR condition is set. Please refer to “Power and
Brown-Out” on page 1062 for VBORnTH value.
2. If the BOR condition exists, an internal reset is asserted.
3. The internal reset is released and the microcontroller fetches and loads the initial stack pointer,
the initial program counter, the first instruction designated by the program counter, and begins
execution.
The result of a brown-out reset is equivalent to that of an assertion of the external RST input, and
the reset is held active until the proper VDD level is restored. The RESC register can be examined
in the reset interrupt handler to determine if a Brown-Out condition was the cause of the reset, thus
allowing software to determine what actions are required to recover.
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The internal Brown-Out Reset timing is shown in “Power and Brown-Out” on page 1062.
5.2.2.5
Software Reset
Software can reset a specific peripheral or generate a reset to the entire microcontroller.
Peripherals can be individually reset by software via peripheral-specific reset registers available
beginning at System Control offset 0x500 (for example the Watchdog Timer Software Reset
(SRWD) register). If the bit position corresponding to a peripheral is set and subsequently cleared,
the peripheral is reset.
The entire microcontroller, including the core, can be reset by software by setting the SYSRESREQ
bit in the Application Interrupt and Reset Control (APINT) register. The software-initiated system
reset sequence is as follows:
1. A software microcontroller reset is initiated by setting the SYSRESREQ bit.
2. An internal reset is asserted.
3. The internal reset is deasserted and the microcontroller loads from memory the initial stack
pointer, the initial program counter, and the first instruction designated by the program counter,
and then begins execution.
The core only can be reset by software by setting the VECTRESET bit in the APINT register. The
software-initiated core reset sequence is as follows:
1. A core reset is initiated by setting the VECTRESET bit.
2. An internal reset is asserted.
3. The internal reset is deasserted and the microcontroller loads from memory the initial stack
pointer, the initial program counter, and the first instruction designated by the program counter,
and then begins execution.
The software-initiated system reset timing is shown in Figure 20-12 on page 1068.
5.2.2.6
Watchdog Timer Reset
The Watchdog Timer module's function is to prevent system hangs. The TM4C1230C3PM
microcontroller has two Watchdog Timer modules in case one watchdog clock source fails. One
watchdog is run off the system clock and the other is run off the Precision Internal Oscillator (PIOSC).
Each module operates in the same manner except that because the PIOSC watchdog timer module
is in a different clock domain, register accesses must have a time delay between them. The watchdog
timer can be configured to generate an interrupt or a non-maskable interrupt to the microcontroller
on its first time-out and to generate a reset on its second time-out.
After the watchdog's first time-out event, the 32-bit watchdog counter is reloaded with the value of
the Watchdog Timer Load (WDTLOAD) register and resumes counting down from that value. If
the timer counts down to zero again before the first time-out interrupt is cleared, and the reset signal
has been enabled, the watchdog timer asserts its reset signal to the microcontroller. The watchdog
timer reset sequence is as follows:
1. The watchdog timer times out for the second time without being serviced.
2. An internal reset is asserted.
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3. The internal reset is released and the microcontroller loads from memory the initial stack pointer,
the initial program counter, and the first instruction designated by the program counter, and
then begins execution.
For more information on the Watchdog Timer module, see “Watchdog Timers” on page 695.
The watchdog reset timing is shown in Figure 20-13 on page 1068.
5.2.3
Non-Maskable Interrupt
The microcontroller has four sources of non-maskable interrupt (NMI):
■ The assertion of the NMI signal
■ A main oscillator verification error
■ The NMISET bit in the Interrupt Control and State (INTCTRL) register in the Cortex™-M4F (see
page 146).
■ The Watchdog module time-out interrupt when the INTTYPE bit in the Watchdog Control
(WDTCTL) register is set (see page 701).
Software must check the cause of the interrupt in order to distinguish among the sources.
5.2.3.1
NMI Pin
The NMI signal is an alternate function for either GPIO port pin PD7 or PF0. The alternate function
must be enabled in the GPIO for the signal to be used as an interrupt, as described in
“General-Purpose Input/Outputs (GPIOs)” on page 570. Note that enabling the NMI alternate function
requires the use of the GPIO lock and commit function just like the GPIO port pins associated with
JTAG/SWD functionality, see page 606. The active sense of the NMI signal is High; asserting the
enabled NMI signal above VIH initiates the NMI interrupt sequence.
5.2.3.2
Main Oscillator Verification Failure
The TM4C1230C3PM microcontroller provides a main oscillator verification circuit that generates
an error condition if the oscillator is running too fast or too slow. If the main oscillator verification
circuit is enabled and a failure occurs, either a power-on reset is generated and control is transferred
to the NMI handler, or an interrupt is generated. The MOSCIM bit in the MOSCCTL register determines
which action occurs. In either case, the system clock source is automatically switched to the PIOSC.
If a MOSC failure reset occurs, the NMI handler is used to address the main oscillator verification
failure because the necessary code can be removed from the general reset handler, speeding up
reset processing. The detection circuit is enabled by setting the CVAL bit in the Main Oscillator
Control (MOSCCTL) register. The main oscillator verification error is indicated in the main oscillator
fail status (MOSCFAIL) bit in the Reset Cause (RESC) register. The main oscillator verification circuit
action is described in more detail in “Main Oscillator Verification Circuit” on page 211.
5.2.4
Power Control
The TM4C1230C3PM microcontroller provides an integrated LDO regulator that is used to provide
power to the majority of the microcontroller's internal logic. Figure 5-4 shows the power architecture.
An external LDO may not be used.
Note:
VDDA must be supplied with a voltage that meets the specification in Table 20-5 on page 1057,
or the microcontroller does not function properly. VDDA is the supply for all of the analog
circuitry on the device, including the clock circuitry.
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Figure 5-4. Power Architecture
VDDC
Internal
Logic and PLL
VDDC
GND
GND
LDO Voltage
Regulator
+3.3V
VDD
GND
I/O Buffers
VDD
GND
+3.3V
GNDA
VDDA
Analog Circuits
VDDA
5.2.5
GNDA
Clock Control
System control determines the control of clocks in this part.
5.2.5.1
Fundamental Clock Sources
There are multiple clock sources for use in the microcontroller:
■ Precision Internal Oscillator (PIOSC). The precision internal oscillator is an on-chip clock
source that is the clock source the microcontroller uses during and following POR. It does not
require the use of any external components and provides a 16-MHz clock with ±1% accuracy
with calibration and ±3% accuracy across temperature (see “PIOSC Specifications” on page 1072).
The PIOSC allows for a reduced system cost in applications that require an accurate clock
source. If the main oscillator is required, software must enable the main oscillator following reset
and allow the main oscillator to stabilize before changing the clock reference. Regardless of
whether or not the PIOSC is the source for the system clock, the PIOSC can be configured to
be the source for the ADC clock as well as the baud clock for the UART and SSI, see “System
Control” on page 211.
■ Main Oscillator (MOSC). The main oscillator provides a frequency-accurate clock source by
one of two means: an external single-ended clock source is connected to the OSC0 input pin, or
an external crystal is connected across the OSC0 input and OSC1 output pins. If the PLL is being
used, the crystal value must be one of the supported frequencies between 5 MHz to 25 MHz
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(inclusive). If the PLL is not being used, the crystal may be any one of the supported frequencies
between 4 MHz to 25 MHz. The single-ended clock source range is as specified in Table
20-13 on page 1071. The supported crystals are listed in the XTAL bit field in the RCC register
(see page 236).
■ Low-Frequency Internal Oscillator (LFIOSC). The low-frequency internal oscillator is intended
for use during Deep-Sleep power-saving modes. The frequency can have wide variations; refer
to “Low-Frequency Internal Oscillator (LFIOSC) Specifications” on page 1072 for more details. This
power-savings mode benefits from reduced internal switching and also allows the MOSC to be
powered down. In addition, the PIOSC can be powered down while in Deep-Sleep mode.
The internal system clock (SysClk), is derived from any of the above sources plus two others: the
output of the main internal PLL and the precision internal oscillator divided by four (4 MHz ± 1%).
The frequency of the PLL clock reference must be in the range of 5 MHz to 25 MHz (inclusive).
Table 5-3 on page 206 shows how the various clock sources can be used in a system.
Table 5-3. Clock Source Options
5.2.5.2
Clock Source
Drive PLL?
Precision Internal Oscillator
Yes
Used as SysClk?
BYPASS = 0, OSCSRC Yes
= 0x1
BYPASS = 1, OSCSRC = 0x1
Precision Internal Oscillator divide by No
4 (4 MHz ± 1%)
-
Yes
BYPASS = 1, OSCSRC = 0x2
Main Oscillator
Yes
BYPASS = 0, OSCSRC Yes
= 0x0
BYPASS = 1, OSCSRC = 0x0
Low-Frequency Internal Oscillator
(LFIOSC)
No
-
BYPASS = 1, OSCSRC = 0x3
Yes
Clock Configuration
The Run-Mode Clock Configuration (RCC) and Run-Mode Clock Configuration 2 (RCC2)
registers provide control for the system clock. The RCC2 register is provided to extend fields that
offer additional encodings over the RCC register. When used, the RCC2 register field values are
used by the logic over the corresponding field in the RCC register. In particular, RCC2 provides for
a larger assortment of clock configuration options. These registers control the following clock
functionality:
■ Source of clocks in sleep and deep-sleep modes
■ System clock derived from PLL or other clock source
■ Enabling/disabling of oscillators and PLL
■ Clock divisors
■ Crystal input selection
Important: Write the RCC register prior to writing the RCC2 register.
When transitioning the system clock configuration to use the MOSC as the fundamental
clock source, the MOSCDIS bit must be set prior to reselecting the MOSC or an undefined
system clock configuration can sporadically occur.
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The configuration of the system clock must not be changed while an EEPROM operation
is in process. Software must wait until the WORKING bit in the EEPROM Done Status
(EEDONE) register is clear before making any changes to the system clock.
Figure 5-5 shows the logic for the main clock tree. The peripheral blocks are driven by the system
clock signal and can be individually enabled/disabled. The ADC clock signal can be selected from
the PIOSC, the system clock if the PLL is disabled, or the PLL output divided down to 16 MHz if the
PLL is enabled.
Note:
If the ADC module is not using the PIOSC as the clock source, the system clock must be
at least 16 MHz.
Figure 5-5. Main Clock Tree
XTALa
PWRDN b
CS f
MOSCDIS a
PLL
(400 MHz)
Main OSC
DIV400 c
BYPASS b,d
USESYSDIV a,d
UART Baud Clock
÷2
IOSCDIS
a
System Clock
Precision
Internal OSC
(16 MHz)
÷ SYSDIV
÷4
e
CS f
BYPASS b,d
PWRDN
Internal OSC
(30 kHz)
SSI Baud Clock
÷ 25
OSCSRC b,d
CS f
ADC Clock
Note:
a.
b.
c.
d.
e.
f.
Control provided by RCC register bit/field.
Control provided by RCC register bit/field or RCC2 register bit/field, if overridden with RCC2 register bit
USERCC2.
Control provided by RCC2 register bit/field.
Also may be controlled by DSLPCLKCFG when in deep sleep mode.
Control provided by RCC register SYSDIV field, RCC2 register SYSDIV2 field if overridden with USERCC2
bit, or [SYSDIV2,SYSDIV2LSB] if both USERCC2 and DIV400 bits are set.
Control provided by UARTCC, SSICC, and ADCCC register field.
Communication Clock Sources
In addition to the main clock tree described above, the UART, and SSI modules all have a Clock
Control register in the peripheral's register map at offset 0xFC8 that can be used to select the clock
source for the module's baud clock. Users can choose between the system clock, which is the
default source for the baud clock, and the PIOSC. Note that there may be special considerations
when using the PIOSC as the baud clock. For more information, see the Clock Control register
description in the chapter describing the operation of the module.
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Using the SYSDIV and SYSDIV2 Fields
In the RCC register, the SYSDIV field specifies which divisor is used to generate the system clock
from either the PLL output or the oscillator source (depending on how the BYPASS bit in this register
is configured). When using the PLL, the VCO frequency of 400 MHz is predivided by 2 before the
divisor is applied. Table 5-4 shows how the SYSDIV encoding affects the system clock frequency,
depending on whether the PLL is used (BYPASS=0) or another clock source is used (BYPASS=1).
The divisor is equivalent to the SYSDIV encoding plus 1. For a list of possible clock sources, see
Table 5-3 on page 206.
Table 5-4. Possible System Clock Frequencies Using the SYSDIV Field
SYSDIV
Divisor
a
Frequency (BYPASS=0) Frequency (BYPASS=1)
TivaWare™ Parameter
0x0
/1
reserved
Clock source frequency/1
SYSCTL_SYSDIV_1
0x1
/2
reserved
Clock source frequency/2
SYSCTL_SYSDIV_2
0x2
/3
66.67 MHz
Clock source frequency/3
SYSCTL_SYSDIV_3
0x3
/4
50 MHz
Clock source frequency/4
SYSCTL_SYSDIV_4
0x4
/5
40 MHz
Clock source frequency/5
SYSCTL_SYSDIV_5
0x5
/6
33.33 MHz
Clock source frequency/6
SYSCTL_SYSDIV_6
0x6
/7
28.57 MHz
Clock source frequency/7
SYSCTL_SYSDIV_7
0x7
/8
25 MHz
Clock source frequency/8
SYSCTL_SYSDIV_8
0x8
/9
22.22 MHz
Clock source frequency/9
SYSCTL_SYSDIV_9
0x9
/10
20 MHz
Clock source frequency/10
SYSCTL_SYSDIV_10
0xA
/11
18.18 MHz
Clock source frequency/11
SYSCTL_SYSDIV_11
0xB
/12
16.67 MHz
Clock source frequency/12
SYSCTL_SYSDIV_12
0xC
/13
15.38 MHz
Clock source frequency/13
SYSCTL_SYSDIV_13
0xD
/14
14.29 MHz
Clock source frequency/14
SYSCTL_SYSDIV_14
0xE
/15
13.33 MHz
Clock source frequency/15
SYSCTL_SYSDIV_15
0xF
/16
12.5 MHz (default)
Clock source frequency/16
SYSCTL_SYSDIV_16
a. This parameter is used in functions such as SysCtlClockSet() in the TivaWare Peripheral Driver Library.
The SYSDIV2 field in the RCC2 register is 2 bits wider than the SYSDIV field in the RCC register
so that additional larger divisors up to /64 are possible, allowing a lower system clock frequency for
improved Deep Sleep power consumption. When using the PLL, the VCO frequency of 400 MHz is
predivided by 2 before the divisor is applied. The divisor is equivalent to the SYSDIV2 encoding
plus 1. Table 5-5 shows how the SYSDIV2 encoding affects the system clock frequency, depending
on whether the PLL is used (BYPASS2=0) or another clock source is used (BYPASS2=1). For a list
of possible clock sources, see Table 5-3 on page 206.
Table 5-5. Examples of Possible System Clock Frequencies Using the SYSDIV2 Field
SYSDIV2
Divisor
Frequency
(BYPASS2=0)
Frequency (BYPASS2=1)
a
TivaWare Parameter
0x00
/1
reserved
Clock source frequency/1
SYSCTL_SYSDIV_1
0x01
/2
reserved
Clock source frequency/2
SYSCTL_SYSDIV_2
0x02
/3
66.67 MHz
Clock source frequency/3
SYSCTL_SYSDIV_3
0x03
/4
50 MHz
Clock source frequency/4
SYSCTL_SYSDIV_4
0x04
/5
40 MHz
Clock source frequency/5
SYSCTL_SYSDIV_5
...
...
...
...
...
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Table 5-5. Examples of Possible System Clock Frequencies Using the SYSDIV2 Field
(continued)
Divisor
a
Frequency
(BYPASS2=0)
Frequency (BYPASS2=1)
TivaWare Parameter
/10
20 MHz
Clock source frequency/10
SYSCTL_SYSDIV_10
...
...
...
...
...
0x3F
/64
3.125 MHz
Clock source frequency/64
SYSCTL_SYSDIV_64
SYSDIV2
0x09
a. This parameter is used in functions such as SysCtlClockSet() in the TivaWare Peripheral Driver Library.
To allow for additional frequency choices when using the PLL, the DIV400 bit is provided along
with the SYSDIV2LSB bit. When the DIV400 bit is set, bit 22 becomes the LSB for SYSDIV2. In
this situation, the divisor is equivalent to the (SYSDIV2 encoding with SYSDIV2LSB appended) plus
one. Table 5-6 shows the frequency choices when DIV400 is set. When the DIV400 bit is clear,
SYSDIV2LSB is ignored, and the system clock frequency is determined as shown in Table
5-5 on page 208.
Table 5-6. Examples of Possible System Clock Frequencies with DIV400=1
/2
reserved
-
/3
reserved
-
1
/4
reserved
-
0
/5
80 MHz
SYSCTL_SYSDIV_2_5
1
/6
66.67 MHz
SYSCTL_SYSDIV_3
0
/7
reserved
-
1
/8
50 MHz
SYSCTL_SYSDIV_4
0
/9
44.44 MHz
SYSCTL_SYSDIV_4_5
1
/10
40 MHz
SYSCTL_SYSDIV_5
...
...
...
...
0
/127
3.15 MHz
SYSCTL_SYSDIV_63_5
1
/128
3.125 MHz
SYSCTL_SYSDIV_64
0x00
reserved
0
0x01
0x02
0x03
0x04
...
0x3F
b
TivaWare Parameter
SYSDIV2LSB
Divisor
a
Frequency (BYPASS2=0)
SYSDIV2
a. Note that DIV400 and SYSDIV2LSB are only valid when BYPASS2=0.
b. This parameter is used in functions such as SysCtlClockSet() in the TivaWare Peripheral Driver Library.
5.2.5.3
Precision Internal Oscillator Operation (PIOSC)
The microcontroller powers up with the PIOSC running. If another clock source is desired, the PIOSC
must remain enabled as it is used for internal functions. The PIOSC can only be disabled during
Deep-Sleep mode. It can be powered down by setting the PIOSCPD bit in the DSLPCLKCFG register.
The PIOSC generates a 16-MHz clock with ±1% accuracy with calibration and ±3% accuracy across
temperature (see “PIOSC Specifications” on page 1072). At the factory, the PIOSC is set to 16 MHz,
however, the frequency can be trimmed for other voltage or temperature conditions using software
in one of two ways:
■ Default calibration: clear the UTEN bit and set the UPDATE bit in the Precision Internal Oscillator
Calibration (PIOSCCAL) register.
■ User-defined calibration: The user can program the UT value to adjust the PIOSC frequency. As
the UT value increases, the generated period increases. To commit a new UT value, first set the
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UTEN bit, then program the UT field, and then set the UPDATE bit. The adjustment finishes within
a few clock periods and is glitch free.
5.2.5.4
Crystal Configuration for the Main Oscillator (MOSC)
The main oscillator supports the use of a select number of crystals from 4 to 25 MHz.
The XTAL bit in the RCC register (see page 236) describes the available crystal choices and default
programming values.
Software configures the RCC register XTAL field with the crystal number. If the PLL is used in the
design, the XTAL field value is internally translated to the PLL settings.
5.2.5.5
Main PLL Frequency Configuration
The main PLL is disabled by default during power-on reset and is enabled later by software if
required. Software specifies the output divisor to set the system clock frequency and enables the
main PLL to drive the output. The PLL operates at 400 MHz, but is divided by two prior to the
application of the output divisor, unless the DIV400 bit in the RCC2 register is set.
To configure the PIOSC to be the clock source for the main PLL, program the OSCRC2 field in the
Run-Mode Clock Configuration 2 (RCC2) register to be 0x1.
If the main oscillator provides the clock reference to the main PLL, the translation provided by
hardware and used to program the PLL is available for software in the PLL Frequency n
(PLLFREQn) registers (see page 251). The internal translation provides a translation within ± 1% of
the targeted PLL VCO frequency. Table 20-14 on page 1071 shows the actual PLL frequency and
error for a given crystal choice.
The Crystal Value field (XTAL) in the Run-Mode Clock Configuration (RCC) register (see page 236)
describes the available crystal choices and default programming of the PLLFREQn registers. Any
time the XTAL field changes, the new settings are translated and the internal PLL settings are
updated.
5.2.5.6
PLL Modes
■ Normal: The PLL multiplies the input clock reference and drives the output.
■ Power-Down: Most of the PLL internal circuitry is disabled and the PLL does not drive the output.
The modes are programmed using the RCC/RCC2 register fields (see page 236 and page 242).
5.2.5.7
PLL Operation
If a PLL configuration is changed, the PLL output frequency is unstable until it reconverges (relocks)
to the new setting. The time between the configuration change and relock is TREADY (see Table
20-13 on page 1071). During the relock time, the affected PLL is not usable as a clock reference.
Software can poll the LOCK bit in the PLL Status (PLLSTAT) register to determine when the PLL
has locked.
The PLL is changed by one of the following:
■ Change to the XTAL value in the RCC register—writes of the same value do not cause a relock.
■ Change in the PLL from Power-Down to Normal mode.
A counter clocked by the system clock is used to measure the TREADY requirement. The down
counter is set to 0x200 if the PLL is powering up. If the M or N values in the PLLFREQn registers
210
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are changed, the counter is set to 0xC0. Hardware is provided to keep the PLL from being used as
a system clock until the TREADY condition is met after one of the two changes above. It is the user's
responsibility to have a stable clock source (like the main oscillator) before the RCC/RCC2 register
is switched to use the PLL.
If the main PLL is enabled and the system clock is switched to use the PLL in one step, the system
control hardware continues to clock the microcontroller from the oscillator selected by the RCC/RCC2
register until the main PLL is stable (TREADY time met), after which it changes to the PLL. Software
can use many methods to ensure that the system is clocked from the main PLL, including periodically
polling the PLLLRIS bit in the Raw Interrupt Status (RIS) register, and enabling the PLL Lock
interrupt.
5.2.5.8
Main Oscillator Verification Circuit
The clock control includes circuitry to ensure that the main oscillator is running at the appropriate
frequency. The circuit monitors the main oscillator frequency and signals if the frequency is outside
of the allowable band of attached crystals.
The detection circuit is enabled using the CVAL bit in the Main Oscillator Control (MOSCCTL)
register. If this circuit is enabled and detects an error, and if the MOSCIM bit in the MOSCCTL register
is clear, then the following sequence is performed by the hardware:
1. The MOSCFAIL bit in the Reset Cause (RESC) register is set.
2. The system clock is switched from the main oscillator to the PIOSC.
3. An internal power-on reset is initiated.
4. Reset is deasserted and the processor is directed to the NMI handler during the reset sequence.
if the MOSCIM bit in the MOSCCTL register is set, then the following sequence is performed by the
hardware:
1. The system clock is switched from the main oscillator to the PIOSC.
2. The MOFRIS bit in the RIS register is set to indicate a MOSC failure.
5.2.6
System Control
For power-savings purposes, the peripheral-specific RCGCx, SCGCx, and DCGCx registers (for
example, RCGCWD) control the clock gating logic for that peripheral or block in the system while
the microcontroller is in Run, Sleep, and Deep-Sleep mode, respectively. These registers are located
in the System Control register map starting at offsets 0x600, 0x700, and 0x800, respectively. There
must be a delay of 3 system clocks after a peripheral module clock is enabled in the RCGC register
before any module registers are accessed.
Important: To support legacy software, the RCGCn, SCGCn, and DCGCn registers are available
at offsets 0x100 - 0x128. A write to any of these legacy registers also writes the
corresponding bit in the peripheral-specific RCGCx, SCGCx, and DCGCx registers.
Software must use the peripheral-specific registers to support modules that are not
present in the legacy registers. It is recommended that new software use the new
registers and not rely on legacy operation.
If software uses a peripheral-specific register to write a legacy peripheral (such as
TIMER0), the write causes proper operation, but the value of that bit is not reflected in
the legacy register. Any bits that are changed by writing to a legacy register can be
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read back correctly with a read of the legacy register. If software uses both legacy and
peripheral-specific register accesses, the peripheral-specific registers must be accessed
by read-modify-write operations that affect only peripherals that are not present in the
legacy registers. In this manner, both the peripheral-specific and legacy registers have
coherent information.
There are three levels of operation for the microcontroller defined as:
■ Run mode
■ Sleep mode
■ Deep-Sleep mode
The following sections describe the different modes in detail.
Caution – If the Cortex-M4F Debug Access Port (DAP) has been enabled, and the device wakes from
a low power sleep or deep-sleep mode, the core may start executing code before all clocks to peripherals
have been restored to their Run mode configuration. The DAP is usually enabled by software tools
accessing the JTAG or SWD interface when debugging or flash programming. If this condition occurs,
a Hard Fault is triggered when software accesses a peripheral with an invalid clock.
A software delay loop can be used at the beginning of the interrupt routine that is used to wake up a
system from a WFI (Wait For Interrupt) instruction. This stalls the execution of any code that accesses
a peripheral register that might cause a fault. This loop can be removed for production software as the
DAP is most likely not enabled during normal execution.
Because the DAP is disabled by default (power on reset), the user can also power cycle the device. The
DAP is not enabled unless it is enabled through the JTAG or SWD interface.
5.2.6.1
Run Mode
In Run mode, the microcontroller actively executes code. Run mode provides normal operation of
the processor and all of the peripherals that are currently enabled by the peripheral-specific RCGC
registers. The system clock can be any of the available clock sources including the PLL.
5.2.6.2
Sleep Mode
In Sleep mode, the clock frequency of the active peripherals is unchanged, but the processor and
the memory subsystem are not clocked and therefore no longer execute code. Sleep mode is entered
by the Cortex-M4F core executing a WFI (Wait for Interrupt) instruction. Any properly configured
interrupt event in the system brings the processor back into Run mode. See “Power
Management” on page 100 for more details.
Peripherals are clocked that are enabled in the peripheral-specific SCGC registers when auto-clock
gating is enabled (see the RCC register) or the peripheral-specific RCGC registers when the
auto-clock gating is disabled. The system clock has the same source and frequency as that during
Run mode.
Additional sleep modes are available that lower the power consumption of the SRAM and Flash
memory. However, the lower power consumption modes have slower sleep and wake-up times,
see “Dynamic Power Management” on page 214 for more information.
Important: Before executing the WFI instruction, software must confirm that the EEPROM is not
busy by checking to see that the WORKING bit in the EEPROM Done Status (EEDONE)
register is clear.
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5.2.6.3
Deep-Sleep Mode
In Deep-Sleep mode, the clock frequency of the active peripherals may change (depending on the
Deep-Sleep mode clock configuration) in addition to the processor clock being stopped. An interrupt
returns the microcontroller to Run mode from one of the sleep modes; the sleep modes are entered
on request from the code. Deep-Sleep mode is entered by first setting the SLEEPDEEP bit in the
System Control (SYSCTRL) register (see page 152) and then executing a WFI instruction. Any
properly configured interrupt event in the system brings the processor back into Run mode. See
“Power Management” on page 100 for more details.
The Cortex-M4F processor core and the memory subsystem are not clocked in Deep-Sleep mode.
Peripherals are clocked that are enabled in the peripheral-specific DCGC registers when auto-clock
gating is enabled (see the RCC register) or the peripheral-specific RCGC registers when auto-clock
gating is disabled. The system clock source is specified in the DSLPCLKCFG register. When the
DSLPCLKCFG register is used, the internal oscillator source is powered up, if necessary, and other
clocks are powered down. If the PLL is running at the time of the WFI instruction, hardware powers
the PLL down and overrides the SYSDIV field of the active RCC/RCC2 register, to be determined
by the DSDIVORIDE setting in the DSLPCLKCFG register, up to /16 or /64 respectively. USB PLL
is not powered down by execution of WFI instruction. When the Deep-Sleep exit event occurs,
hardware brings the system clock back to the source and frequency it had at the onset of Deep-Sleep
mode before enabling the clocks that had been stopped during the Deep-Sleep duration. If the
PIOSC is used as the PLL reference clock source, it may continue to provide the clock during
Deep-Sleep. See page 246.
Important: Before executing the WFI instruction, software must confirm that the EEPROM is not
busy by checking to see that the WORKING bit in the EEPROM Done Status (EEDONE)
register is clear.
To provide the lowest possible Deep-Sleep power consumption as well the ability to wake the
processor from a peripheral without reconfiguring the peripheral for a change in clock, some of the
communications modules have a Clock Control register at offset 0xFC8 in the module register space.
The CS field in the Clock Control register allows the user to select the PIOSC as the clock source
for the module's baud clock. When the microcontroller enters Deep-Sleep mode, the PIOSC becomes
the source for the module clock as well, which allows the transmit and receive FIFOs to continue
operation while the part is in Deep-Sleep. Figure 5-6 on page 213 shows how the clocks are selected.
Figure 5-6. Module Clock Selection
Clock Control Register
PIOSC
1
Baud Clock
0
Deep Sleep
1
Module Clock
System Clock
0
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Additional deep-sleep modes are available that lower the power consumption of the SRAM and
Flash memory. However, the lower power consumption modes have slower deep-sleep and wake-up
times, see “Dynamic Power Management” on page 214 for more information.
5.2.6.4
Dynamic Power Management
In addition to the Sleep and Deep-Sleep modes and the clock gating for the on-chip modules, there
are several additional power mode options that allow the LDO, Flash memory, and SRAM into
different levels of power savings while in Sleep or Deep-Sleep modes. Note that these features may
not be available on all devices; the System Properties (SYSPROP) register provides information
on whether a mode is supported on a given MCU. The following registers provides these capabilities:
■ LDO Sleep Power Control (LDOSPCTL): controls the LDO value in Sleep mode
■ LDO Deep-Sleep Power Control (LDODPCTL): controls the LDO value in Deep-Sleep mode
■ LDO Sleep Power Calibration (LDOSPCAL): provides factory recommendations for the LDO
value in Sleep mode
■ LDO Deep-Sleep Power Calibration (LDODPCAL): provides factory recommendations for the
LDO value in Deep-Sleep mode
■ Sleep Power Configuration (SLPPWRCFG): controls the power saving modes for Flash memory
and SRAM in Sleep mode
■ Deep-Sleep Power Configuration (DSLPPWRCFG): controls the power saving modes for Flash
memory and SRAM in Deep-Sleep mode
■ Deep-Sleep Clock Configuration (DSLPCLKCFG): controls the clocking in Deep-Sleep mode
■ Sleep / Deep-Sleep Power Mode Status (SDPMST): provides status information on the various
power saving events
LDO Sleep/Deep-Sleep Power Control
Note:
While the device is connected through JTAG, the LDO control settings for Sleep or
Deep-Sleep are not available and will not be applied.
The user can dynamically request to raise or lower the LDO voltage level to trade-off
power/performance using either the LDOSPCTL register (see page 258) or the LDODPCTL register
(see page 261). When lowering the LDO level, software must configure the system clock for the lower
LDO value in RCC/RCC2 for Sleep mode and in DSLPCLKCFG for Deep-Sleep mode before
requesting the LDO to lower.
The LDO Power Calibration registers, LDOSPCAL and LDODPCAL, provide suggested values for
the LDO in the various modes. If software requests an LDO value that is too low or too high, the
value is not accepted and an error is reported in the SDPMST register.
The table below shows the maximum system clock frequency and PIOSC frequency with respect
to the configured LDO voltage.
Operating Voltage (LDO)
Maximum System Clock Frequency
PIOSC
1.2
80 MHz
16 MHz
0.9
20 MHz
16 MHz
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Flash Memory and SRAM Power Control
During Sleep or Deep-Sleep mode, Flash memory can be in either the default active mode or the
low power mode; SRAM can be in the default active mode, standby mode, or low power mode. The
active mode in each case provides the fastest times to sleep and wake up, but consumes more
power. Low power mode provides the lowest power consumption, but takes longer to sleep and
wake up.
The SRAM can be programmed to prohibit any power management by configuring the SRAMSM bit
in the System Properties (SYSPROP) register. This configuration operates in the same way that
®
legacy Stellaris devices operate and provides the fastest sleep and wake-up times, but consumes
the most power while in Sleep and Deep-Sleep mode. Other power options are retention mode, and
retention mode with lower SRAM voltage. The SRAM retention mode with lower SRAM voltage
provides the lowest power consumption, but has the longest sleep and wake-up times. These modes
can be independently configured for Flash memory and SRAM using the SLPPWRCFG and
DSLPPWRCFG registers.
The following power saving options are available in Sleep and Deep-Sleep modes:
■ The clocks can be gated according to the settings in the the peripheral-specific SCGC or DCGC
registers.
■ In Deep-Sleep mode, the clock source can be changed and the PIOSC can be powered off (if
no active peripheral requires it) using the DSLPCLKCFG register. These options are not available
for Sleep mode.
■ The LDO voltage can be changed using the LDOSPCTL or LDODPCTL register.
■ The Flash memory can be put into low power mode. Refer to Table 20-22 on page 1077 for wake
times from Sleep and Deep-Sleep.
■ The SRAM can be put into standby or low power mode. Refer to Table 20-22 on page 1077 for
wake times from Sleep and Deep-Sleep.
The SDPMST register provides results on the Dynamic Power Management command issued. It
also has some real time status that can be viewed by a debugger or the core if it is running. These
events do not trigger an interrupt and are meant to provide information to help tune software for
power management. The status register gets written at the beginning of every Dynamic Power
Management event request that provides error checking. There is no mechanism to clear the bits;
they are overwritten on the next event. The real time data is real time and there is no event to register
that information.
5.3
Initialization and Configuration
The PLL is configured using direct register writes to the RCC/RCC2 register. If the RCC2 register
is being used, the USERCC2 bit must be set and the appropriate RCC2 bit/field is used. The steps
required to successfully change the PLL-based system clock are:
1. Bypass the PLL and system clock divider by setting the BYPASS bit and clearing the USESYS
bit in the RCC register, thereby configuring the microcontroller to run off a "raw" clock source
and allowing for the new PLL configuration to be validated before switching the system clock
to the PLL.
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2. Select the crystal value (XTAL) and oscillator source (OSCSRC), and clear the PWRDN bit in
RCC/RCC2. Setting the XTAL field automatically pulls valid PLL configuration data for the
appropriate crystal, and clearing the PWRDN bit powers and enables the PLL and its output.
3. Select the desired system divider (SYSDIV) in RCC/RCC2 and set the USESYS bit in RCC. The
SYSDIV field determines the system frequency for the microcontroller.
4. Wait for the PLL to lock by polling the PLLLRIS bit in the Raw Interrupt Status (RIS) register.
5. Enable use of the PLL by clearing the BYPASS bit in RCC/RCC2.
5.4
Register Map
Table 5-7 on page 216 lists the System Control registers, grouped by function. The offset listed is a
hexadecimal increment to the register's address, relative to the System Control base address of
0x400F.E000.
Note:
Spaces in the System Control register space that are not used are reserved for future or
internal use. Software should not modify any reserved memory address.
Additional Flash and ROM registers defined in the System Control register space are
described in the “Internal Memory” on page 446.
Table 5-7. System Control Register Map
Offset
Name
Type
Reset
Description
See
page
System Control Registers
0x000
DID0
RO
-
Device Identification 0
221
0x004
DID1
RO
0x1022.602E
Device Identification 1
223
0x030
PBORCTL
RW
0x0000.7FFF
Brown-Out Reset Control
226
0x050
RIS
RO
0x0000.0000
Raw Interrupt Status
227
0x054
IMC
RW
0x0000.0000
Interrupt Mask Control
229
0x058
MISC
RW1C
0x0000.0000
Masked Interrupt Status and Clear
231
0x05C
RESC
RW
-
Reset Cause
234
0x060
RCC
RW
0x0780.3AD1
Run-Mode Clock Configuration
236
0x06C
GPIOHBCTL
RW
0x0000.7E00
GPIO High-Performance Bus Control
240
0x070
RCC2
RW
0x07C0.6810
Run-Mode Clock Configuration 2
242
0x07C
MOSCCTL
RW
0x0000.0000
Main Oscillator Control
245
0x144
DSLPCLKCFG
RW
0x0780.0000
Deep Sleep Clock Configuration
246
0x14C
SYSPROP
RO
0x0000.1D31
System Properties
248
0x150
PIOSCCAL
RW
0x0000.0000
Precision Internal Oscillator Calibration
250
0x160
PLLFREQ0
RO
0x0000.0032
PLL Frequency 0
251
0x164
PLLFREQ1
RO
0x0000.0001
PLL Frequency 1
252
0x168
PLLSTAT
RO
0x0000.0000
PLL Status
253
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Table 5-7. System Control Register Map (continued)
Offset
Name
0x188
Description
See
page
Type
Reset
SLPPWRCFG
RW
0x0000.0000
Sleep Power Configuration
254
0x18C
DSLPPWRCFG
RW
0x0000.0000
Deep-Sleep Power Configuration
256
0x1B4
LDOSPCTL
RW
0x0000.0018
LDO Sleep Power Control
258
0x1B8
LDOSPCAL
RO
0x0000.1818
LDO Sleep Power Calibration
260
0x1BC
LDODPCTL
RW
0x0000.0012
LDO Deep-Sleep Power Control
261
0x1C0
LDODPCAL
RO
0x0000.1212
LDO Deep-Sleep Power Calibration
263
0x1CC
SDPMST
RO
0x0000.0000
Sleep / Deep-Sleep Power Mode Status
264
0x300
PPWD
RO
0x0000.0003
Watchdog Timer Peripheral Present
267
0x304
PPTIMER
RO
0x0000.003F
16/32-Bit General-Purpose Timer Peripheral Present
268
0x308
PPGPIO
RO
0x0000.007F
General-Purpose Input/Output Peripheral Present
270
0x30C
PPDMA
RO
0x0000.0001
Micro Direct Memory Access Peripheral Present
273
0x314
PPHIB
RO
0x0000.0000
Hibernation Peripheral Present
274
0x318
PPUART
RO
0x0000.00FF
Universal Asynchronous Receiver/Transmitter Peripheral
Present
275
0x31C
PPSSI
RO
0x0000.000F
Synchronous Serial Interface Peripheral Present
277
0x320
PPI2C
RO
0x0000.003F
Inter-Integrated Circuit Peripheral Present
279
0x328
PPUSB
RO
0x0000.0000
Universal Serial Bus Peripheral Present
281
0x334
PPCAN
RO
0x0000.0001
Controller Area Network Peripheral Present
282
0x338
PPADC
RO
0x0000.0003
Analog-to-Digital Converter Peripheral Present
283
0x33C
PPACMP
RO
0x0000.0001
Analog Comparator Peripheral Present
284
0x340
PPPWM
RO
0x0000.0000
Pulse Width Modulator Peripheral Present
285
0x344
PPQEI
RO
0x0000.0000
Quadrature Encoder Interface Peripheral Present
286
0x358
PPEEPROM
RO
0x0000.0001
EEPROM Peripheral Present
287
0x35C
PPWTIMER
RO
0x0000.003F
32/64-Bit Wide General-Purpose Timer Peripheral
Present
288
0x500
SRWD
RW
0x0000.0000
Watchdog Timer Software Reset
290
0x504
SRTIMER
RW
0x0000.0000
16/32-Bit General-Purpose Timer Software Reset
292
0x508
SRGPIO
RW
0x0000.0000
General-Purpose Input/Output Software Reset
294
0x50C
SRDMA
RW
0x0000.0000
Micro Direct Memory Access Software Reset
296
0x518
SRUART
RW
0x0000.0000
Universal Asynchronous Receiver/Transmitter Software
Reset
297
0x51C
SRSSI
RW
0x0000.0000
Synchronous Serial Interface Software Reset
299
0x520
SRI2C
RW
0x0000.0000
Inter-Integrated Circuit Software Reset
301
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Table 5-7. System Control Register Map (continued)
Offset
Name
0x534
See
page
Type
Reset
Description
SRCAN
RW
0x0000.0000
Controller Area Network Software Reset
303
0x538
SRADC
RW
0x0000.0000
Analog-to-Digital Converter Software Reset
304
0x53C
SRACMP
RW
0x0000.0000
Analog Comparator Software Reset
306
0x558
SREEPROM
RW
0x0000.0000
EEPROM Software Reset
307
0x55C
SRWTIMER
RW
0x0000.0000
32/64-Bit Wide General-Purpose Timer Software Reset
308
0x600
RCGCWD
RW
0x0000.0000
Watchdog Timer Run Mode Clock Gating Control
310
0x604
RCGCTIMER
RW
0x0000.0000
16/32-Bit General-Purpose Timer Run Mode Clock Gating
Control
311
0x608
RCGCGPIO
RW
0x0000.0000
General-Purpose Input/Output Run Mode Clock Gating
Control
313
0x60C
RCGCDMA
RW
0x0000.0000
Micro Direct Memory Access Run Mode Clock Gating
Control
315
0x618
RCGCUART
RW
0x0000.0000
Universal Asynchronous Receiver/Transmitter Run Mode
Clock Gating Control
316
0x61C
RCGCSSI
RW
0x0000.0000
Synchronous Serial Interface Run Mode Clock Gating
Control
318
0x620
RCGCI2C
RW
0x0000.0000
Inter-Integrated Circuit Run Mode Clock Gating Control
320
0x634
RCGCCAN
RW
0x0000.0000
Controller Area Network Run Mode Clock Gating Control
322
0x638
RCGCADC
RW
0x0000.0000
Analog-to-Digital Converter Run Mode Clock Gating
Control
323
0x63C
RCGCACMP
RW
0x0000.0000
Analog Comparator Run Mode Clock Gating Control
324
0x658
RCGCEEPROM
RW
0x0000.0000
EEPROM Run Mode Clock Gating Control
325
0x65C
RCGCWTIMER
RW
0x0000.0000
32/64-Bit Wide General-Purpose Timer Run Mode Clock
Gating Control
326
0x700
SCGCWD
RW
0x0000.0000
Watchdog Timer Sleep Mode Clock Gating Control
328
0x704
SCGCTIMER
RW
0x0000.0000
16/32-Bit General-Purpose Timer Sleep Mode Clock
Gating Control
329
0x708
SCGCGPIO
RW
0x0000.0000
General-Purpose Input/Output Sleep Mode Clock Gating
Control
331
0x70C
SCGCDMA
RW
0x0000.0000
Micro Direct Memory Access Sleep Mode Clock Gating
Control
333
0x718
SCGCUART
RW
0x0000.0000
Universal Asynchronous Receiver/Transmitter Sleep
Mode Clock Gating Control
334
0x71C
SCGCSSI
RW
0x0000.0000
Synchronous Serial Interface Sleep Mode Clock Gating
Control
336
0x720
SCGCI2C
RW
0x0000.0000
Inter-Integrated Circuit Sleep Mode Clock Gating Control
338
0x734
SCGCCAN
RW
0x0000.0000
Controller Area Network Sleep Mode Clock Gating
Control
340
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Table 5-7. System Control Register Map (continued)
Offset
Name
0x738
Description
See
page
Type
Reset
SCGCADC
RW
0x0000.0000
Analog-to-Digital Converter Sleep Mode Clock Gating
Control
341
0x73C
SCGCACMP
RW
0x0000.0000
Analog Comparator Sleep Mode Clock Gating Control
342
0x758
SCGCEEPROM
RW
0x0000.0000
EEPROM Sleep Mode Clock Gating Control
343
0x75C
SCGCWTIMER
RW
0x0000.0000
32/64-Bit Wide General-Purpose Timer Sleep Mode Clock
Gating Control
344
0x800
DCGCWD
RW
0x0000.0000
Watchdog Timer Deep-Sleep Mode Clock Gating Control
346
0x804
DCGCTIMER
RW
0x0000.0000
16/32-Bit General-Purpose Timer Deep-Sleep Mode
Clock Gating Control
347
0x808
DCGCGPIO
RW
0x0000.0000
General-Purpose Input/Output Deep-Sleep Mode Clock
Gating Control
349
0x80C
DCGCDMA
RW
0x0000.0000
Micro Direct Memory Access Deep-Sleep Mode Clock
Gating Control
351
0x818
DCGCUART
RW
0x0000.0000
Universal Asynchronous Receiver/Transmitter
Deep-Sleep Mode Clock Gating Control
352
0x81C
DCGCSSI
RW
0x0000.0000
Synchronous Serial Interface Deep-Sleep Mode Clock
Gating Control
354
0x820
DCGCI2C
RW
0x0000.0000
Inter-Integrated Circuit Deep-Sleep Mode Clock Gating
Control
356
0x834
DCGCCAN
RW
0x0000.0000
Controller Area Network Deep-Sleep Mode Clock Gating
Control
358
0x838
DCGCADC
RW
0x0000.0000
Analog-to-Digital Converter Deep-Sleep Mode Clock
Gating Control
359
0x83C
DCGCACMP
RW
0x0000.0000
Analog Comparator Deep-Sleep Mode Clock Gating
Control
360
0x858
DCGCEEPROM
RW
0x0000.0000
EEPROM Deep-Sleep Mode Clock Gating Control
361
0x85C
DCGCWTIMER
RW
0x0000.0000
32/64-Bit Wide General-Purpose Timer Deep-Sleep Mode
Clock Gating Control
362
0xA00
PRWD
RO
0x0000.0000
Watchdog Timer Peripheral Ready
364
0xA04
PRTIMER
RO
0x0000.0000
16/32-Bit General-Purpose Timer Peripheral Ready
365
0xA08
PRGPIO
RO
0x0000.0000
General-Purpose Input/Output Peripheral Ready
367
0xA0C
PRDMA
RO
0x0000.0000
Micro Direct Memory Access Peripheral Ready
369
0xA18
PRUART
RO
0x0000.0000
Universal Asynchronous Receiver/Transmitter Peripheral
Ready
370
0xA1C
PRSSI
RO
0x0000.0000
Synchronous Serial Interface Peripheral Ready
372
0xA20
PRI2C
RO
0x0000.0000
Inter-Integrated Circuit Peripheral Ready
374
0xA34
PRCAN
RO
0x0000.0000
Controller Area Network Peripheral Ready
376
0xA38
PRADC
RO
0x0000.0000
Analog-to-Digital Converter Peripheral Ready
377
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Table 5-7. System Control Register Map (continued)
Offset
Name
0xA3C
See
page
Type
Reset
Description
PRACMP
RO
0x0000.0000
Analog Comparator Peripheral Ready
378
0xA58
PREEPROM
RO
0x0000.0000
EEPROM Peripheral Ready
379
0xA5C
PRWTIMER
RO
0x0000.0000
32/64-Bit Wide General-Purpose Timer Peripheral Ready
380
System Control Legacy Registers
0x008
DC0
RO
0x002F.000F
Device Capabilities 0
382
0x010
DC1
RO
0x1103.2FBF
Device Capabilities 1
384
0x014
DC2
RO
0x030F.F037
Device Capabilities 2
387
0x018
DC3
RO
0xBFFF.0FC0
Device Capabilities 3
390
0x01C
DC4
RO
0x0004.F07F
Device Capabilities 4
394
0x020
DC5
RO
0x0000.0000
Device Capabilities 5
397
0x024
DC6
RO
0x0000.0000
Device Capabilities 6
399
0x028
DC7
RO
0xFFFF.FFFF
Device Capabilities 7
400
0x02C
DC8
RO
0x0FFF.0FFF
Device Capabilities 8
403
0x040
SRCR0
RO
0x0000.0000
Software Reset Control 0
406
0x044
SRCR1
RO
0x0000.0000
Software Reset Control 1
408
0x048
SRCR2
RO
0x0000.0000
Software Reset Control 2
411
0x100
RCGC0
RO
0x0000.0040
Run Mode Clock Gating Control Register 0
413
0x104
RCGC1
RO
0x0000.0000
Run Mode Clock Gating Control Register 1
416
0x108
RCGC2
RO
0x0000.0000
Run Mode Clock Gating Control Register 2
419
0x110
SCGC0
RO
0x0000.0040
Sleep Mode Clock Gating Control Register 0
421
0x114
SCGC1
RO
0x0000.0000
Sleep Mode Clock Gating Control Register 1
423
0x118
SCGC2
RO
0x0000.0000
Sleep Mode Clock Gating Control Register 2
426
0x120
DCGC0
RO
0x0000.0040
Deep Sleep Mode Clock Gating Control Register 0
428
0x124
DCGC1
RO
0x0000.0000
Deep-Sleep Mode Clock Gating Control Register 1
430
0x128
DCGC2
RO
0x0000.0000
Deep Sleep Mode Clock Gating Control Register 2
433
0x190
DC9
RO
0x00FF.00FF
Device Capabilities 9
435
0x1A0
NVMSTAT
RO
0x0000.0001
Non-Volatile Memory Information
437
5.5
System Control Register Descriptions
All addresses given are relative to the System Control base address of 0x400F.E000. Registers
provided for legacy software support only are listed in “System Control Legacy Register
Descriptions” on page 381.
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Tiva™ TM4C1230C3PM Microcontroller
Register 1: Device Identification 0 (DID0), offset 0x000
This register identifies the version of the microcontroller. Each microcontroller is uniquely identified
by the combined values of the CLASS field in the DID0 register and the PARTNO field in the DID1
register. The MAJOR and MINOR bit fields indicate the die revision number. Combined, the MAJOR
and MINOR bit fields indicate the part revision number.
MAJOR Bitfield Value
MINOR Bitfield Value
Die Revision
Part Revision
0x0
0x0
A0
1
0x0
0x1
A1
2
0x0
0x2
A2
3
0x0
0x3
A3
4
0x1
0x0
B0
5
0x1
0x1
B1
6
0x1
0x2
B2
7
Device Identification 0 (DID0)
Base 0x400F.E000
Offset 0x000
Type RO, reset 31
30
reserved
Type
Reset
29
28
27
26
VER
25
24
23
22
21
20
reserved
18
17
16
CLASS
RO
0
RO
0
RO
0
RO
1
RO
1
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
1
RO
0
RO
1
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
RO
-
RO
-
RO
-
RO
-
RO
-
RO
-
RO
-
RO
-
RO
-
RO
-
RO
-
RO
-
RO
-
RO
-
RO
-
RO
-
MAJOR
Type
Reset
19
MINOR
Bit/Field
Name
Type
Reset
31
reserved
RO
0
30:28
VER
RO
0x01
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
DID0 Version
This field defines the DID0 register format version. The version number
is numeric. The value of the VER field is encoded as follows (all other
encodings are reserved):
Value Description
0x1
27:24
reserved
RO
0x08
Second version of the DID0 register format.
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
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System Control
Bit/Field
Name
Type
Reset
Description
23:16
CLASS
RO
0x05
Device Class
The CLASS field value identifies the internal design from which all mask
sets are generated for all microcontrollers in a particular product line.
The CLASS field value is changed for new product lines, for changes in
fab process (for example, a remap or shrink), or any case where the
MAJOR or MINOR fields require differentiation from prior microcontrollers.
The value of the CLASS field is encoded as follows (all other encodings
are reserved):
Value Description
0x05 Tiva™ TM4C123x microcontrollers
15:8
MAJOR
RO
-
Major Die Revision
This field specifies the major revision number of the microcontroller.
The major revision reflects changes to base layers of the design. This
field is encoded as follows:
Value Description
0x0
Revision A (initial device)
0x1
Revision B (first base layer revision)
0x2
Revision C (second base layer revision)
and so on.
7:0
MINOR
RO
-
Minor Die Revision
This field specifies the minor revision number of the microcontroller.
The minor revision reflects changes to the metal layers of the design.
The MINOR field value is reset when the MAJOR field is changed. This
field is numeric and is encoded as follows:
Value Description
0x0
Initial device, or a major revision update.
0x1
First metal layer change.
0x2
Second metal layer change.
and so on.
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Register 2: Device Identification 1 (DID1), offset 0x004
This register identifies the device family, part number, temperature range, pin count, and package
type. Each microcontroller is uniquely identified by the combined values of the CLASS field in the
DID0 register and the PARTNO field in the DID1 register.
Device Identification 1 (DID1)
Base 0x400F.E000
Offset 0x004
Type RO, reset 0x1022.602E
31
30
29
28
27
26
RO
0
15
25
24
23
22
21
20
RO
0
RO
0
RO
1
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
1
RO
0
14
13
12
11
10
9
8
7
6
5
4
RO
1
RO
0
RO
0
RO
0
RO
0
RO
0
RO
1
RO
0
VER
Type
Reset
FAM
PINCOUNT
Type
Reset
RO
0
RO
1
18
17
16
RO
0
RO
0
RO
1
RO
0
3
2
1
0
PARTNO
reserved
RO
0
19
TEMP
Bit/Field
Name
Type
Reset
31:28
VER
RO
0x1
RO
0
PKG
ROHS
RO
1
RO
1
QUAL
RO
1
RO
0
Description
DID1 Version
This field defines the DID1 register format version. The version number
is numeric. The value of the VER field is encoded as follows (all other
encodings are reserved):
Value Description
27:24
FAM
RO
0x0
0x0
Initial DID1 register format definition, indicating a Stellaris
LM3Snnn device.
0x1
Second version of the DID1 register format.
Family
This field provides the family identification of the device within the product
portfolio. The value is encoded as follows (all other encodings are
reserved):
Value Description
0x0
23:16
PARTNO
RO
0x22
Tiva™ C Series microcontrollers and legacy Stellaris
microcontrollers, that is, all devices with external part numbers
starting with TM4C, LM4F or LM3S.
Part Number
This field provides the part number of the device within the family. The
reset value shown indicates the TM4C1230C3PM microcontroller.
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System Control
Bit/Field
Name
Type
Reset
15:13
PINCOUNT
RO
0x3
Description
Package Pin Count
This field specifies the number of pins on the device package. The value
is encoded as follows (all other encodings are reserved):
Value Description
12:8
reserved
RO
0
7:5
TEMP
RO
0x1
0x0
reserved
0x1
reserved
0x2
100-pin package
0x3
64-pin package
0x4
144-pin package
0x5
157-pin package
0x6
168-pin package
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
Temperature Range
This field specifies the temperature rating of the device. The value is
encoded as follows (all other encodings are reserved):
Value Description
4:3
PKG
RO
0x1
0x0
Reserved
0x1
Industrial temperature range (-40°C to 85°C)
0x2
Extended temperature range (-40°C to 105°C)
0x3
Available in both industrial temperature range (-40°C to 85°C)
and extended temperature range (-40°C to 105°C) devices. See
“Package Information” on page 1096 for specific order numbers.
Package Type
This field specifies the package type. The value is encoded as follows
(all other encodings are reserved):
Value Description
2
ROHS
RO
0x1
0x0
Reserved
0x1
LQFP package
0x2
BGA package
RoHS-Compliance
This bit specifies whether the device is RoHS-compliant. A 1 indicates
the part is RoHS-compliant.
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Bit/Field
Name
Type
Reset
1:0
QUAL
RO
0x2
Description
Qualification Status
This field specifies the qualification status of the device. The value is
encoded as follows (all other encodings are reserved):
Value Description
0x0
Engineering Sample (unqualified)
0x1
Pilot Production (unqualified)
0x2
Fully Qualified
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System Control
Register 3: Brown-Out Reset Control (PBORCTL), offset 0x030
This register is responsible for controlling reset conditions after initial power-on reset.
Note:
The BOR voltage values and center points are based on simulation only. These values are
yet to be characterized and are subject to change.
Brown-Out Reset Control (PBORCTL)
Base 0x400F.E000
Offset 0x030
Type RW, reset 0x0000.7FFF
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
RO
0
RO
0
RO
0
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
9
8
7
6
5
4
3
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
2
1
0
BOR0
BOR1
reserved
RW
1
RW
1
RO
0
Bit/Field
Name
Type
Reset
Description
31:3
reserved
RO
0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
2
BOR0
RW
1
VDD under BOR0 Event Action
The VDD BOR0 trip value is 3.02V +/- 90mv.
Value Description
1
BOR1
RW
1
0
A BOR0 event causes an interrupt to be generated in the
interrupt controller.
1
A BOR0 event causes a reset of the microcontroller.
VDD under BOR1 Event Action
The VDD BOR1 trip value is 2.88V +/- 90mv.
Value Description
0
reserved
RO
0
0
A BOR1 event causes an interrupt to be generated to the
interrupt controller.
1
A BOR1 event causes a reset of the microcontroller.
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
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Tiva™ TM4C1230C3PM Microcontroller
Register 4: Raw Interrupt Status (RIS), offset 0x050
This register indicates the status for system control raw interrupts. An interrupt is sent to the interrupt
controller if the corresponding bit in the Interrupt Mask Control (IMC) register is set. Writing a 1
to the corresponding bit in the Masked Interrupt Status and Clear (MISC) register clears an interrupt
status bit.
Raw Interrupt Status (RIS)
Base 0x400F.E000
Offset 0x050
Type RO, reset 0x0000.0000
31
30
29
28
27
26
25
24
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
8
RO
0
RO
0
23
22
21
20
19
18
17
16
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
7
6
5
4
3
2
1
0
reserved
Type
Reset
reserved
Type
Reset
BOR0RIS VDDARIS reserved
RO
0
RO
0
RO
0
RO
0
MOSCPUPRIS
RO
0
Bit/Field
Name
Type
Reset
31:12
reserved
RO
0x0000.00
11
BOR0RIS
RO
0
RO
0
reserved PLLLRIS
RO
0
RO
0
reserved
RO
0
MOFRIS
RO
0
RO
0
reserved BOR1RIS reserved
RO
0
RO
0
RO
0
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
VDD under BOR0 Raw Interrupt Status
Value Description
0
A VDD BOR0 condition is not currently active.
1
A VDD BOR0 condition is currently active.
Note the BOR0 bit in the PBORCTL register must be cleared to cause
an interrupt due to a BOR0 Event.
This bit is cleared by writing a 1 to the BOR0MIS bit in the MISC register.
10
VDDARIS
RO
0
VDDA Power OK Event Raw Interrupt Status
Value Description
0
VDDA power is not at its appropriate functional voltage.
1
VDDA is at an appropriate functional voltage.
This bit is cleared by writing a 1 to the VDDAMIS bit in the MISC register.
9
reserved
RO
0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
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System Control
Bit/Field
Name
Type
Reset
8
MOSCPUPRIS
RO
0
Description
MOSC Power Up Raw Interrupt Status
Value Description
0
Sufficient time has not passed for the MOSC to reach the
expected frequency.
1
Sufficient time has passed for the MOSC to reach the expected
frequency. The value for this power-up time is indicated by
TMOSC_START.
This bit is cleared by writing a 1 to the MOSCPUPMIS bit in the MISC
register.
7
reserved
RO
0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
6
PLLLRIS
RO
0
PLL Lock Raw Interrupt Status
Value Description
0
The PLL timer has not reached TREADY.
1
The PLL timer has reached TREADY indicating that sufficient time
has passed for the PLL to lock.
This bit is cleared by writing a 1 to the PLLLMIS bit in the MISC register.
5:4
reserved
RO
0x0
3
MOFRIS
RO
0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
Main Oscillator Failure Raw Interrupt Status
Value Description
0
The main oscillator has not failed.
1
The MOSCIM bit in the MOSCCTL register is set and the main
oscillator has failed.
This bit is cleared by writing a 1 to the MOFMIS bit in the MISC register.
2
reserved
RO
0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
1
BOR1RIS
RO
0
VDD under BOR1 Raw Interrupt Status
Value Description
0
A VDDS BOR1 condition is not currently active.
1
A VDDS BOR1 condition is currently active.
Note the BOR1 bit in the PBORCTL register must be cleared to cause
an interrupt due to a BOR1 Event.
This bit is cleared by writing a 1 to the BOR1MIS bit in the MISC register.
0
reserved
RO
0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
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Tiva™ TM4C1230C3PM Microcontroller
Register 5: Interrupt Mask Control (IMC), offset 0x054
This register contains the mask bits for system control raw interrupts. A raw interrupt, indicated by
a bit being set in the Raw Interrupt Status (RIS) register, is sent to the interrupt controller if the
corresponding bit in this register is set.
Interrupt Mask Control (IMC)
Base 0x400F.E000
Offset 0x054
Type RW, reset 0x0000.0000
31
30
29
28
27
26
25
24
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
BOR0IM
VDDAIM
RO
0
RO
0
RW
0
RW
0
23
22
21
20
19
18
17
16
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
8
7
6
5
4
3
2
1
0
reserved
MOSCPUPIM
reserved
PLLLIM
MOFIM
reserved
BOR1IM
reserved
RO
0
RW
0
RO
0
RW
0
RW
0
RO
0
RW
0
RO
0
reserved
Type
Reset
reserved
Type
Reset
RO
0
RO
0
Bit/Field
Name
Type
Reset
31:12
reserved
RO
0x0000.00
11
BOR0IM
RW
0
reserved
RO
0
RO
0
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
VDD under BOR0 Interrupt Mask
Value Description
10
VDDAIM
RW
0
0
The BOR0RIS interrupt is suppressed and not sent to the
interrupt controller.
1
An interrupt is sent to the interrupt controller when the BOR0RIS
bit in the RIS register is set.
VDDA Power OK Interrupt Mask
Value Description
0
The VDDARIS interrupt is suppressed and not sent to the
interrupt controller.
1
An interrupt is sent to the interrupt controller when the VDDARIS
bit in the RIS register is set.
9
reserved
RO
0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
8
MOSCPUPIM
RW
0
MOSC Power Up Interrupt Mask
Value Description
0
The MOSCPUPRIS interrupt is suppressed and not sent to the
interrupt controller.
1
An interrupt is sent to the interrupt controller when the
MOSCPUPRIS bit in the RIS register is set.
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System Control
Bit/Field
Name
Type
Reset
Description
7
reserved
RO
0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
6
PLLLIM
RW
0
PLL Lock Interrupt Mask
Value Description
5:4
reserved
RO
0x0
3
MOFIM
RW
0
0
The PLLLRIS interrupt is suppressed and not sent to the
interrupt controller.
1
An interrupt is sent to the interrupt controller when the PLLLRIS
bit in the RIS register is set.
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
Main Oscillator Failure Interrupt Mask
Value Description
0
The MOFRIS interrupt is suppressed and not sent to the interrupt
controller.
1
An interrupt is sent to the interrupt controller when the MOFRIS
bit in the RIS register is set.
2
reserved
RO
0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
1
BOR1IM
RW
0
VDD under BOR1 Interrupt Mask
Value Description
0
reserved
RO
0
0
The BOR1RIS interrupt is suppressed and not sent to the
interrupt controller.
1
An interrupt is sent to the interrupt controller when the BOR1RIS
bit in the RIS register is set.
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
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Tiva™ TM4C1230C3PM Microcontroller
Register 6: Masked Interrupt Status and Clear (MISC), offset 0x058
On a read, this register gives the current masked status value of the corresponding interrupt in the
Raw Interrupt Status (RIS) register. All of the bits are RW1C, thus writing a 1 to a bit clears the
corresponding raw interrupt bit in the RIS register (see page 227).
Masked Interrupt Status and Clear (MISC)
Base 0x400F.E000
Offset 0x058
Type RW1C, reset 0x0000.0000
31
30
29
28
27
26
25
24
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
8
RO
0
RO
0
23
22
21
20
19
18
17
16
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
7
6
5
4
3
2
1
0
reserved
Type
Reset
reserved
Type
Reset
BOR0MIS VDDAMIS reserved
RO
0
RO
0
RW1C
0
RW1C
0
MOSCPUPMIS
RO
0
Bit/Field
Name
Type
Reset
31:12
reserved
RO
0x0000.00
11
BOR0MIS
RW1C
0
RW1C
0
reserved PLLLMIS
RO
0
RW1C
0
reserved
RO
0
RO
0
MOFMIS reserved BOR1MIS reserved
RO
0
RO
0
RW1C
0
RO
0
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
VDD under BOR0 Masked Interrupt Status
Value Description
0
When read, a 0 indicates that a BOR0 condition has not
occurred.
A write of 0 has no effect on the state of this bit.
1
When read, a 1 indicates that an unmasked interrupt was
signaled because of a BOR0 condition.
Writing a 1 to this bit clears it and also the BOR0RIS bit in the
RIS register.
10
VDDAMIS
RW1C
0
VDDA Power OK Masked Interrupt Status
Value Description
0
When read, a 0 indicates that VDDA power is good.
A write of 0 has no effect on the state of this bit.
1
When read, a 1 indicates that an unmasked interrupt was
signaled because VDDA was below the proper functioning
voltage.
Writing a 1 to this bit clears it and also the VDDARIS bit in the
RIS register.
9
reserved
RO
0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
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System Control
Bit/Field
Name
Type
Reset
8
MOSCPUPMIS
RW1C
0
Description
MOSC Power Up Masked Interrupt Status
Value Description
0
When read, a 0 indicates that sufficient time has not passed for
the MOSC PLL to lock.
A write of 0 has no effect on the state of this bit.
1
When read, a 1 indicates that an unmasked interrupt was
signaled because sufficient time has passed for the MOSC PLL
to lock.
Writing a 1 to this bit clears it and also the MOSCPUPRIS bit in
the RIS register.
7
reserved
RO
0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
6
PLLLMIS
RW1C
0
PLL Lock Masked Interrupt Status
Value Description
0
When read, a 0 indicates that sufficient time has not passed for
the PLL to lock.
A write of 0 has no effect on the state of this bit.
1
When read, a 1 indicates that an unmasked interrupt was
signaled because sufficient time has passed for the PLL to lock.
Writing a 1 to this bit clears it and also the PLLLRIS bit in the
RIS register.
5:4
reserved
RO
0x0
3
MOFMIS
RO
0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
Main Oscillator Failure Masked Interrupt Status
Value Description
0
When read, a 0 indicates that the main oscillator has not failed.
A write of 0 has no effect on the state of this bit.
1
When read, a 1 indicates that an unmasked interrupt was
signaled because the main oscillator failed.
Writing a 1 to this bit clears it and also the MOFRIS bit in the
RIS register.
2
reserved
RO
0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
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Bit/Field
Name
Type
Reset
1
BOR1MIS
RW1C
0
Description
VDD under BOR1 Masked Interrupt Status
Value Description
0
When read, a 0 indicates that a BOR1 condition has not
occurred.
A write of 0 has no effect on the state of this bit.
1
When read, a 1 indicates that an unmasked interrupt was
signaled because of a BOR1 condition.
Writing a 1 to this bit clears it and also the BOR1RIS bit in the
RIS register.
0
reserved
RO
0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
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System Control
Register 7: Reset Cause (RESC), offset 0x05C
This register is set with the reset cause after reset. The bits in this register are sticky and maintain
their state across multiple reset sequences, except when an power-on reset is the cause, in which
case, all bits other than POR in the RESC register are cleared.
Reset Cause (RESC)
Base 0x400F.E000
Offset 0x05C
Type RW, reset 31
30
29
28
27
26
25
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
RO
0
RO
0
RO
0
RO
0
RO
0
24
23
22
21
20
19
18
17
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RW
-
9
8
7
6
5
4
3
2
1
0
WDT1
SW
WDT0
BOR
POR
EXT
RO
0
RO
0
RO
0
RO
0
RW
-
RW
-
RW
-
RW
-
RW
-
RW
-
reserved
Type
Reset
MOSCFAIL
reserved
Type
Reset
RO
0
16
Bit/Field
Name
Type
Reset
Description
31:17
reserved
RO
0x000
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
16
MOSCFAIL
RW
-
MOSC Failure Reset
Value Description
0
When read, this bit indicates that a MOSC failure has not
generated a reset since the previous power-on reset.
Writing a 0 to this bit clears it.
1
15:6
reserved
RO
0x00
5
WDT1
RW
-
When read, this bit indicates that the MOSC circuit was enabled
for clock validation and failed while the MOSCIM bit in the
MOSCCTL register is clear, generating a reset event.
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
Watchdog Timer 1 Reset
Value Description
0
When read, this bit indicates that Watchdog Timer 1 has not
generated a reset since the previous power-on reset.
Writing a 0 to this bit clears it.
1
When read, this bit indicates that Watchdog Timer 1 timed out
and generated a reset.
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Bit/Field
Name
Type
Reset
4
SW
RW
-
Description
Software Reset
Value Description
0
When read, this bit indicates that a software reset has not
generated a reset since the previous power-on reset.
Writing a 0 to this bit clears it.
1
3
WDT0
RW
-
When read, this bit indicates that a software reset has caused
a reset event.
Watchdog Timer 0 Reset
Value Description
0
When read, this bit indicates that Watchdog Timer 0 has not
generated a reset since the previous power-on reset.
Writing a 0 to this bit clears it.
1
2
BOR
RW
-
When read, this bit indicates that Watchdog Timer 0 timed out
and generated a reset.
Brown-Out Reset
Value Description
0
When read, this bit indicates that a brown-out (BOR0 or BOR1)
reset has not generated a reset since the previous power-on
reset.
Writing a 0 to this bit clears it.
1
1
POR
RW
-
When read, this bit indicates that a brown-out (BOR0 or BOR1)
reset has caused a reset event.
Power-On Reset
Value Description
0
When read, this bit indicates that a power-on reset has not
generated a reset.
Writing a 0 to this bit clears it.
1
0
EXT
RW
-
When read, this bit indicates that a power-on reset has caused
a reset event.
External Reset
Value Description
0
When read, this bit indicates that an external reset (RST
assertion) has not caused a reset event since the previous
power-on reset.
Writing a 0 to this bit clears it.
1
When read, this bit indicates that an external reset (RST
assertion) has caused a reset event.
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System Control
Register 8: Run-Mode Clock Configuration (RCC), offset 0x060
The bits in this register configure the system clock and oscillators.
Important: Write the RCC register prior to writing the RCC2 register.
Run-Mode Clock Configuration (RCC)
Base 0x400F.E000
Offset 0x060
Type RW, reset 0x0780.3AD1
31
30
29
28
RO
0
RO
0
RO
0
RO
0
15
14
13
12
reserved
Type
Reset
reserved
Type
Reset
RO
0
RO
0
27
26
25
24
23
RW
0
RW
1
RW
1
RW
1
RW
1
11
10
9
8
RW
0
RW
1
ACG
PWRDN
reserved BYPASS
RW
1
RO
1
21
20
19
RW
0
RO
0
RO
0
RO
0
7
6
5
4
3
RW
1
RW
1
RW
0
RW
1
RO
0
SYSDIV
22
Bit/Field
Name
Type
Reset
31:28
reserved
RO
0x0
27
ACG
RW
0
RW
0
17
16
RO
0
RO
0
RO
0
2
1
0
reserved
USESYSDIV
XTAL
RW
1
18
OSCSRC
reserved
RO
0
MOSCDIS
RO
0
RW
1
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
Auto Clock Gating
This bit specifies whether the system uses the Sleep-Mode Clock
Gating Control (SCGCn) registers and Deep-Sleep-Mode Clock
Gating Control (DCGCn) registers if the microcontroller enters a Sleep
or Deep-Sleep mode (respectively).
Value Description
0
The Run-Mode Clock Gating Control (RCGCn) registers are
used when the microcontroller enters a sleep mode.
1
The SCGCn or DCGCn registers are used to control the clocks
distributed to the peripherals when the microcontroller is in a
sleep mode. The SCGCn and DCGCn registers allow unused
peripherals to consume less power when the microcontroller is
in a sleep mode.
The RCGCn registers are always used to control the clocks in Run
mode.
26:23
SYSDIV
RW
0xF
System Clock Divisor
Specifies which divisor is used to generate the system clock from either
the PLL output or the oscillator source (depending on how the BYPASS
bit in this register is configured). See Table 5-4 on page 208 for bit
encodings.
If the SYSDIV value is less than MINSYSDIV (see page 384), and the
PLL is being used, then the MINSYSDIV value is used as the divisor.
If the PLL is not being used, the SYSDIV value can be less than
MINSYSDIV.
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Bit/Field
Name
Type
Reset
22
USESYSDIV
RW
0
Description
Enable System Clock Divider
Value Description
0
The system clock is used undivided.
1
The system clock divider is the source for the system clock. The
system clock divider is forced to be used when the PLL is
selected as the source.
If the USERCC2 bit in the RCC2 register is set, then the SYSDIV2
field in the RCC2 register is used as the system clock divider
rather than the SYSDIV field in this register.
21:14
reserved
RO
0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
13
PWRDN
RW
1
PLL Power Down
Value Description
0
The PLL is operating normally.
1
The PLL is powered down. Care must be taken to ensure that
another clock source is functioning and that the BYPASS bit is
set before setting this bit.
12
reserved
RO
1
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
11
BYPASS
RW
1
PLL Bypass
Value Description
0
The system clock is the PLL output clock divided by the divisor
specified by SYSDIV.
1
The system clock is derived from the OSC source and divided
by the divisor specified by SYSDIV.
See Table 5-4 on page 208 for programming guidelines.
Note:
The ADC must be clocked from the PLL or directly from a
16-MHz clock source to operate properly.
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System Control
Bit/Field
Name
Type
Reset
Description
10:6
XTAL
RW
0x0B
Crystal Value
This field specifies the crystal value attached to the main oscillator. The
encoding for this field is provided below.
Value
Crystal Frequency (MHz) Not
Using the PLL
0x00-0x5
5:4
OSCSRC
RW
0x1
Crystal Frequency (MHz)
Using the PLL
reserved
0x06
4 MHz
reserved
0x07
4.096 MHz
reserved
0x08
4.9152 MHz
reserved
0x09
5 MHz
0x0A
5.12 MHz
0x0B
6 MHz
0x0C
6.144 MHz
0x0D
7.3728 MHz
0x0E
8 MHz
0x0F
8.192 MHz
0x10
10.0 MHz
0x11
12.0 MHz
0x12
12.288 MHz
0x13
13.56 MHz
0x14
14.31818 MHz
0x15
16.0 MHz
0x16
16.384 MHz
0x17
18.0 MHz
0x18
20.0 MHz
0x19
24.0 MHz
0x1A
25.0 MHz
Oscillator Source
Selects the input source for the OSC. The values are:
Value Input Source
0x0
MOSC
Main oscillator
0x1
PIOSC
Precision internal oscillator
(default)
0x2
PIOSC/4
Precision internal oscillator / 4
0x3
LFIOSC
Low-frequency internal oscillator
For additional oscillator sources, see the RCC2 register.
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Bit/Field
Name
Type
Reset
3:1
reserved
RO
0x0
0
MOSCDIS
RW
1
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
Main Oscillator Disable
Value Description
0
The main oscillator is enabled.
1
The main oscillator is disabled (default).
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System Control
Register 9: GPIO High-Performance Bus Control (GPIOHBCTL), offset 0x06C
This register controls which internal bus is used to access each GPIO port. When a bit is clear, the
corresponding GPIO port is accessed across the legacy Advanced Peripheral Bus (APB) bus and
through the APB memory aperture. When a bit is set, the corresponding port is accessed across
the Advanced High-Performance Bus (AHB) bus and through the AHB memory aperture. Each
GPIO port can be individually configured to use AHB or APB, but may be accessed only through
one aperture. The AHB bus provides better back-to-back access performance than the APB bus.
The address aperture in the memory map changes for the ports that are enabled for AHB access
(see Table 9-6 on page 581).
Important: Ports K-N and P-Q are only available on the AHB bus, and therefore the corresponding
bits reset to 1. If one of these bits is cleared, the corresponding port is disabled. If any
of these ports is in use, read-modify-write operations should be used to change the
value of this register so that these ports remain enabled.
GPIO High-Performance Bus Control (GPIOHBCTL)
Base 0x400F.E000
Offset 0x06C
Type RW, reset 0x0000.7E00
31
30
29
28
27
26
25
24
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
23
22
21
20
19
18
17
16
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
8
7
6
5
4
3
2
1
0
PORTG
PORTF
PORTE
PORTD
PORTC
PORTB
PORTA
RO
0
RO
0
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
reserved
Type
Reset
reserved
Type
Reset
RO
0
Bit/Field
Name
Type
Reset
31:7
reserved
RO
0x0000.0
6
PORTG
RW
0
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
Port G Advanced High-Performance Bus
This bit defines the memory aperture for Port G.
Value Description
5
PORTF
RW
0
0
Advanced Peripheral Bus (APB). This bus is the legacy bus.
1
Advanced High-Performance Bus (AHB)
Port F Advanced High-Performance Bus
This bit defines the memory aperture for Port F.
Value Description
0
Advanced Peripheral Bus (APB). This bus is the legacy bus.
1
Advanced High-Performance Bus (AHB)
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Bit/Field
Name
Type
Reset
4
PORTE
RW
0
Description
Port E Advanced High-Performance Bus
This bit defines the memory aperture for Port E.
Value Description
3
PORTD
RW
0
0
Advanced Peripheral Bus (APB). This bus is the legacy bus.
1
Advanced High-Performance Bus (AHB)
Port D Advanced High-Performance Bus
This bit defines the memory aperture for Port D.
Value Description
2
PORTC
RW
0
0
Advanced Peripheral Bus (APB). This bus is the legacy bus.
1
Advanced High-Performance Bus (AHB)
Port C Advanced High-Performance Bus
This bit defines the memory aperture for Port C.
Value Description
1
PORTB
RW
0
0
Advanced Peripheral Bus (APB). This bus is the legacy bus.
1
Advanced High-Performance Bus (AHB)
Port B Advanced High-Performance Bus
This bit defines the memory aperture for Port B.
Value Description
0
PORTA
RW
0
0
Advanced Peripheral Bus (APB). This bus is the legacy bus.
1
Advanced High-Performance Bus (AHB)
Port A Advanced High-Performance Bus
This bit defines the memory aperture for Port A.
Value Description
0
Advanced Peripheral Bus (APB). This bus is the legacy bus.
1
Advanced High-Performance Bus (AHB)
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System Control
Register 10: Run-Mode Clock Configuration 2 (RCC2), offset 0x070
This register overrides the RCC equivalent register fields, as shown in Table 5-8, when the USERCC2
bit is set, allowing the extended capabilities of the RCC2 register to be used while also providing a
means to be backward-compatible to previous parts. Each RCC2 field that supersedes an RCC
field is located at the same LSB bit position; however, some RCC2 fields are larger than the
corresponding RCC field.
Table 5-8. RCC2 Fields that Override RCC Fields
RCC2 Field...
Overrides RCC Field
SYSDIV2, bits[28:23]
SYSDIV, bits[26:23]
PWRDN2, bit[13]
PWRDN, bit[13]
BYPASS2, bit[11]
BYPASS, bit[11]
OSCSRC2, bits[6:4]
OSCSRC, bits[5:4]
Important: Write the RCC register prior to writing the RCC2 register.
Run-Mode Clock Configuration 2 (RCC2)
Base 0x400F.E000
Offset 0x070
Type RW, reset 0x07C0.6810
31
30
USERCC2 DIV400
Type
Reset
RW
0
RW
0
15
14
reserved
Type
Reset
RO
0
RO
0
29
28
27
26
reserved
25
24
23
SYSDIV2
22
RO
0
RW
0
RW
0
RW
1
RW
1
RW
1
RW
1
RW
1
13
12
11
10
9
8
7
6
PWRDN2 reserved BYPASS2
RW
1
RO
0
reserved
RW
1
RO
0
21
20
19
RO
0
RO
0
Bit/Field
Name
Type
Reset
Description
31
USERCC2
RW
0
Use RCC2
17
16
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
5
4
3
2
1
0
RO
0
RO
0
OSCSRC2
RO
0
18
reserved
SYSDIV2LSB
RW
0
RW
0
reserved
RW
1
RO
0
RO
0
Value Description
30
DIV400
RW
0
0
The RCC register fields are used, and the fields in RCC2 are
ignored.
1
The RCC2 register fields override the RCC register fields.
Divide PLL as 400 MHz versus 200 MHz
This bit, along with the SYSDIV2LSB bit, allows additional frequency
choices.
Value Description
0
Use SYSDIV2 as is and apply to 200 MHz predivided PLL
output. See Table 5-5 on page 208 for programming guidelines.
1
Append the SYSDIV2LSB bit to the SYSDIV2 field to create a
7 bit divisor using the 400 MHz PLL output, see Table
5-6 on page 209.
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Bit/Field
Name
Type
Reset
29
reserved
RO
0x0
28:23
SYSDIV2
RW
0x0F
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
System Clock Divisor 2
Specifies which divisor is used to generate the system clock from either
the PLL output or the oscillator source (depending on how the BYPASS2
bit is configured). SYSDIV2 is used for the divisor when both the
USESYSDIV bit in the RCC register and the USERCC2 bit in this register
are set. See Table 5-5 on page 208 for programming guidelines.
22
SYSDIV2LSB
RW
1
Additional LSB for SYSDIV2
When DIV400 is set, this bit becomes the LSB of SYSDIV2. If DIV400
is clear, this bit is not used. See Table 5-5 on page 208 for programming
guidelines.
This bit can only be set or cleared when DIV400 is set.
21:14
reserved
RO
0x0
13
PWRDN2
RW
1
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
Power-Down PLL 2
Value Description
0
The PLL operates normally.
1
The PLL is powered down.
12
reserved
RO
0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
11
BYPASS2
RW
1
PLL Bypass 2
Value Description
0
The system clock is the PLL output clock divided by the divisor
specified by SYSDIV2.
1
The system clock is derived from the OSC source and divided
by the divisor specified by SYSDIV2.
See Table 5-5 on page 208 for programming guidelines.
Note:
10:7
reserved
RO
0x0
The ADC must be clocked from the PLL or directly from a
16-MHz clock source to operate properly.
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
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System Control
Bit/Field
Name
Type
Reset
6:4
OSCSRC2
RW
0x1
Description
Oscillator Source 2
Selects the input source for the OSC. The values are:
Value
Description
0x0
MOSC
Main oscillator
0x1
PIOSC
Precision internal oscillator
0x2
PIOSC/4
Precision internal oscillator / 4
0x3
LFIOSC
Low-frequency internal oscillator
0x4-0x7 Reserved
3:0
reserved
RO
0x0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
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Tiva™ TM4C1230C3PM Microcontroller
Register 11: Main Oscillator Control (MOSCCTL), offset 0x07C
This register provides control over the features of the main oscillator, including the ability to enable
the MOSC clock verification circuit, what action to take when the MOSC fails, and whether or not a
crystal is connected. When enabled, this circuit monitors the frequency of the MOSC to verify that
the oscillator is operating within specified limits. If the clock goes invalid after being enabled, the
microcontroller issues a power-on reset and reboots to the NMI handler or generates an interrupt.
Main Oscillator Control (MOSCCTL)
Base 0x400F.E000
Offset 0x07C
Type RW, reset 0x0000.0000
31
30
29
28
27
26
25
24
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
23
22
21
20
19
18
17
16
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
8
7
6
5
4
3
2
1
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
reserved
Type
Reset
reserved
Type
Reset
RO
0
Bit/Field
Name
Type
Reset
31:3
reserved
RO
0x0000.000
2
NOXTAL
RW
0
NOXTAL MOSCIM
RW
0
RW
0
CVAL
RW
0
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
No Crystal Connected
Value Description
1
MOSCIM
RW
0
0
This bit should be cleared when a crystal or oscillator is
connected to the OSC0 and OSC1 inputs, regardless of whether
or not the MOSC is used or powered down.
1
This bit should be set when a crystal or external oscillator is not
connected to the OSC0 and OSC1 inputs to reduce power
consumption.
MOSC Failure Action
Value Description
0
If the MOSC fails, a MOSC failure reset is generated and reboots
to the NMI handler.
1
If the MOSC fails, an interrupt is generated as indicated by the
MOFRIS bit in the RIS register..
Regardless of the action taken, if the MOSC fails, the oscillator source
is switched to the PIOSC automatically.
0
CVAL
RW
0
Clock Validation for MOSC
Value Description
0
The MOSC monitor circuit is disabled.
1
The MOSC monitor circuit is enabled.
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System Control
Register 12: Deep Sleep Clock Configuration (DSLPCLKCFG), offset 0x144
This register provides configuration information for the hardware control of Deep Sleep Mode.
Deep Sleep Clock Configuration (DSLPCLKCFG)
Base 0x400F.E000
Offset 0x144
Type RW, reset 0x0780.0000
31
30
29
28
27
26
reserved
Type
Reset
25
24
23
22
21
20
DSDIVORIDE
18
17
16
reserved
RO
0
RO
0
RO
0
RW
0
RW
0
RW
1
RW
1
RW
1
RW
1
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RW
0
RW
0
RO
0
reserved
Type
Reset
19
DSOSCSRC
RO
0
Bit/Field
Name
Type
Reset
31:29
reserved
RO
0x0
28:23
DSDIVORIDE
RW
0x0F
RW
0
reserved
RO
0
PIOSCPD reserved
RW
0
RO
0
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
Divider Field Override
If Deep-Sleep mode is enabled when the PLL is running, the PLL is
disabled. This 6-bit field contains a system divider field that overrides
the SYSDIV field in the RCC register or the SYSDIV2 field in the RCC2
register during Deep Sleep. This divider is applied to the source selected
by the DSOSCSRC field.
Value Description
0x0
/1
0x1
/2
0x2
/3
0x3
/4
...
...
0x3F /64
22:7
reserved
RO
0x000
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
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Bit/Field
Name
Type
Reset
6:4
DSOSCSRC
RW
0x0
Description
Clock Source
Specifies the clock source during Deep-Sleep mode.
Value
Description
0x0
MOSC
Use the main oscillator as the source. To use the MOSC as
the Deep-Sleep mode clock source, the MOSC must also be
configured as the Run mode clock source in the Run-Mode
Clock Configuration (RCC) register.
Note:
0x1
If the PIOSC is being used as the clock reference
for the PLL, the PIOSC is the clock source instead
of MOSC in Deep-Sleep mode.
PIOSC
Use the precision internal 16-MHz oscillator as the source.
0x2
Reserved
0x3
LFIOSC
Use the low-frequency internal oscillator as the source.
0x4-0x7 Reserved
3:2
reserved
RO
0x0
1
PIOSCPD
RW
0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
PIOSC Power Down Request
Allows software to request the PIOSC to be powered-down in
Deep-Sleep mode. If the PIOSC is needed by an enabled peripheral
during Deep-Sleep, the PIOSC is powered down, but a warning is
generated using the PPDW bit in the SDPMST register. If it is not possible
to power down the PIOSC, an error is reported using the PPDERR bit in
the SDPMST register.
This bit can only be used to power down the PIOSC when the PIOSCPDE
bit in the SYSPROP register is set.
Value Description
0
reserved
RO
0
0
No action.
1
Software requests that the PIOSC is powered down during
Deep-Sleep mode.
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
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System Control
Register 13: System Properties (SYSPROP), offset 0x14C
This register provides information on whether certain System Control properties are present on the
microcontroller.
System Properties (SYSPROP)
Base 0x400F.E000
Offset 0x14C
Type RO, reset 0x0000.1D31
31
30
29
28
27
26
25
24
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
8
23
22
21
20
19
18
17
16
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
7
6
5
4
3
2
1
0
RO
0
RO
1
RO
1
RO
0
reserved
Type
Reset
reserved
Type
Reset
RO
0
RO
0
PIOSCPDE
RO
0
RO
1
SRAMSM SRAMLPM reserved FLASHLPM
RO
1
RO
1
RO
0
RO
1
reserved
RO
0
reserved
reserved
RO
0
FPU
RO
0
RO
1
Bit/Field
Name
Type
Reset
Description
31:13
reserved
RO
0x0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
12
PIOSCPDE
RO
0x1
PIOSC Power Down Present
This bit determines whether the PIOSCPD bit in the DSLPCLKCFG
register can be set to power down the PIOSC in Deep-Sleep mode.
Value Description
11
SRAMSM
RO
0x1
0
The status of the PIOSCPD bit is ignored.
1
The PIOSCPD bit can be set to power down the PIOSC in
Deep-Sleep mode.
SRAM Sleep/Deep-Sleep Standby Mode Present
This bit determines whether the SRAMPM field in the SLPPWRCFG and
DSLPPWRCFG registers can be configured to put the SRAM into
Standby mode while in Sleep or Deep-Sleep mode.
Value Description
10
SRAMLPM
RO
0x1
0
A value of 0x1 in the SRAMPM fields is ignored.
1
The SRAMPM fields can be configured to put the SRAM into
Standby mode while in Sleep or Deep-Sleep mode.
SRAM Sleep/Deep-Sleep Low Power Mode Present
This bit determines whether the SRAMPM field in the SLPPWRCFG and
DSLPPWRCFG registers can be configured to put the SRAM into Low
Power mode while in Sleep or Deep-Sleep mode.
Value Description
0
A value of 0x3 in the SRAMPM fields is ignored.
1
The SRAMPM fields can be configured to put the SRAM into Low
Power mode while in Sleep or Deep-Sleep mode.
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Bit/Field
Name
Type
Reset
9
reserved
RO
0
8
FLASHLPM
RO
0x1
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
Flash Memory Sleep/Deep-Sleep Low Power Mode Present
This bit determines whether the FLASHPM field in the SLPPWRCFG
and DSLPPWRCFG registers can be configured to put the Flash memory
into Low Power mode while in Sleep or Deep-Sleep mode.
Value Description
0
A value of 0x2 in the FLASHPM fields is ignored.
1
The FLASHPM fields can be configured to put the Flash memory
into Low Power mode while in Sleep or Deep-Sleep mode.
7:6
reserved
RO
0x0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
5:4
reserved
RO
0x3
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
3:1
reserved
RO
0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0
FPU
RO
0x1
FPU Present
This bit indicates if the FPU is present in the Cortex-M4 core.
Value Description
0
FPU is not present.
1
FPU is present.
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System Control
Register 14: Precision Internal Oscillator Calibration (PIOSCCAL), offset 0x150
This register provides the ability to update or recalibrate the precision internal oscillator.
Precision Internal Oscillator Calibration (PIOSCCAL)
Base 0x400F.E000
Offset 0x150
Type RW, reset 0x0000.0000
31
30
29
28
27
26
25
24
RW
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
8
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
UTEN
Type
Reset
22
21
20
19
18
17
16
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
7
6
5
4
3
2
1
0
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
reserved
reserved
Type
Reset
23
RO
0
UPDATE reserved
Bit/Field
Name
Type
Reset
31
UTEN
RW
0
RW
0
RO
0
UT
Description
Use User Trim Value
Value Description
30:9
reserved
RO
0x0000
8
UPDATE
RW
0
0
The factory calibration value is used for an update trim operation.
1
The trim value in bits[6:0] of this register are used for any update
trim operation.
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
Update Trim
Value Description
0
No action.
1
Updates the PIOSC trim value with the UT bit. Used with UTEN.
This bit is auto-cleared after the update.
7
reserved
RO
0
6:0
UT
RW
0x0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
User Trim Value
User trim value that can be loaded into the PIOSC.
Refer to “Precision Internal Oscillator Operation (PIOSC)” on page 209
for more information on calibrating the PIOSC.
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Tiva™ TM4C1230C3PM Microcontroller
Register 15: PLL Frequency 0 (PLLFREQ0), offset 0x160
This register always contains the current M value presented to the system PLL.
The PLL frequency can be calculated using the following equation:
PLL frequency = (XTAL frequency * MDIV) / ((Q + 1) * (N + 1))
where
MDIV = MINT + (MFRAC / 1024)
The Q and N values are shown in the PLLFREQ1 register. Table 20-14 on page 1071 shows the M,
Q, and N values as well as the resulting PLL frequency for the various XTAL configurations.
PLL Frequency 0 (PLLFREQ0)
Base 0x400F.E000
Offset 0x160
Type RO, reset 0x0000.0032
31
30
29
28
27
26
25
24
23
22
21
20
19
18
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
8
7
6
5
MFRAC
Type
Reset
RO
1
RO
1
RO
0
RO
0
17
16
MFRAC
RO
0
RO
0
RO
0
RO
0
RO
0
4
3
2
1
0
RO
0
RO
0
RO
0
RO
0
RO
0
MINT
RO
1
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
Bit/Field
Name
Type
Reset
Description
31:20
reserved
RO
0x000
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
19:10
MFRAC
RO
0x32
PLL M Fractional Value
This field contains the integer value of the PLL M value.
9:0
MINT
RO
0x00
PLL M Integer Value
This field contains the integer value of the PLL M value.
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System Control
Register 16: PLL Frequency 1 (PLLFREQ1), offset 0x164
This register always contains the current Q and N values presented to the system PLL.
The M value is shown in the PLLFREQ0 register. Table 20-14 on page 1071 shows the M, Q, and N
values as well as the resulting PLL frequency for the various XTAL configurations.
PLL Frequency 1 (PLLFREQ1)
Base 0x400F.E000
Offset 0x164
Type RO, reset 0x0000.0001
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
6
5
4
3
2
1
0
RO
0
RO
1
reserved
Type
Reset
RO
0
15
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
14
13
12
11
10
9
8
7
reserved
Type
Reset
RO
0
RO
0
Q
RO
0
RO
0
RO
0
RO
0
reserved
RO
0
Bit/Field
Name
Type
Reset
31:13
reserved
RO
0x0000.0
12:8
Q
RO
0x0
RO
0
RO
0
RO
0
N
RO
0
RO
0
RO
0
RO
0
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
PLL Q Value
This field contains the PLL Q value.
7:5
reserved
RO
0x0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
4:0
N
RO
0x1
PLL N Value
This field contains the PLL N value.
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Register 17: PLL Status (PLLSTAT), offset 0x168
This register shows the direct status of the PLL lock.
PLL Status (PLLSTAT)
Base 0x400F.E000
Offset 0x168
Type RO, reset 0x0000.0000
31
30
29
28
27
26
25
24
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
8
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
23
22
21
20
19
18
17
16
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
7
6
5
4
3
2
1
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
reserved
Type
Reset
reserved
Type
Reset
Bit/Field
Name
Type
Reset
31:1
reserved
RO
0x0000.000
0
LOCK
RO
0x0
RO
0
LOCK
RO
0
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
PLL Lock
Value Description
0
The PLL is unpowered or is not yet locked.
1
The PLL is powered and locked.
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System Control
Register 18: Sleep Power Configuration (SLPPWRCFG), offset 0x188
This register provides configuration information for the power control of the SRAM and Flash memory
while in Sleep mode.
Sleep Power Configuration (SLPPWRCFG)
Base 0x400F.E000
Offset 0x188
Type RW, reset 0x0000.0000
31
30
29
28
27
26
25
24
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
23
22
21
20
19
18
17
16
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
8
7
6
5
4
3
2
1
0
RO
0
RO
0
RO
0
RW
0
RO
0
RW
0
reserved
Type
Reset
reserved
Type
Reset
RO
0
FLASHPM
Bit/Field
Name
Type
Reset
31:6
reserved
RO
0x0000.00
5:4
FLASHPM
RW
0x0
RW
0
reserved
RO
0
SRAMPM
RW
0
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
Flash Power Modes
Value Description
0x0
Active Mode
Flash memory is not placed in a lower power mode. This mode
provides the fastest time to sleep and wakeup but the highest
power consumption while the microcontroller is in Sleep mode.
0x1
Reserved
0x2
Low Power Mode
Flash memory is placed in low power mode. This mode provides
the lowers power consumption but requires more time to come
out of Sleep mode.
0x3
3:2
reserved
RO
0x0
Reserved
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
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Bit/Field
Name
Type
Reset
1:0
SRAMPM
RW
0x0
Description
SRAM Power Modes
This field controls the low power modes of the on-chip SRAM while the
microcontroller is in Deep-Sleep mode.
Value Description
0x0
Active Mode
SRAM is not placed in a lower power mode. This mode provides
the fastest time to sleep and wakeup but the highest power
consumption while the microcontroller is in Sleep mode.
0x1
Standby Mode
SRAM is place in standby mode while in Sleep mode.
0x2
Reserved
0x3
Low Power Mode
SRAM is placed in low power mode. This mode provides the
slowest time to sleep and wakeup but the lowest power
consumption while in Sleep mode.
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System Control
Register 19: Deep-Sleep Power Configuration (DSLPPWRCFG), offset 0x18C
This register provides configuration information for the power control of the SRAM and Flash memory
while in Deep-Sleep mode.
Deep-Sleep Power Configuration (DSLPPWRCFG)
Base 0x400F.E000
Offset 0x18C
Type RW, reset 0x0000.0000
31
30
29
28
27
26
25
24
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
23
22
21
20
19
18
17
16
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
8
7
6
5
4
3
2
1
0
RO
0
RO
0
RO
0
RW
0
RO
0
RW
0
reserved
Type
Reset
reserved
Type
Reset
RO
0
FLASHPM
Bit/Field
Name
Type
Reset
31:6
reserved
RO
0x0000.00
5:4
FLASHPM
RW
0x0
RW
0
reserved
RO
0
SRAMPM
RW
0
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
Flash Power Modes
Value Description
0x0
Active Mode
Flash memory is not placed in a lower power mode. This mode
provides the fastest time to sleep and wakeup but the highest
power consumption while the microcontroller is in Deep-Sleep
mode.
0x1
Reserved
0x2
Low Power Mode
Flash memory is placed in low power mode. This mode provides
the lowers power consumption but requires more time to come
out of Deep-Sleep mode.
0x3
3:2
reserved
RO
0x0
Reserved
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
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Tiva™ TM4C1230C3PM Microcontroller
Bit/Field
Name
Type
Reset
1:0
SRAMPM
RW
0x0
Description
SRAM Power Modes
This field controls the low power modes of the on-chip SRAM while the
microcontroller is in Deep-Sleep mode.
Value Description
0x0
Active Mode
SRAM is not placed in a lower power mode. This mode provides
the fastest time to sleep and wakeup but the highest power
consumption while the microcontroller is in Deep-Sleep mode.
0x1
Standby Mode
SRAM is place in standby mode while in Deep-Sleep mode.
0x2
Reserved
0x3
Low Power Mode
SRAM is placed in low power mode. This mode provides the
slowest time to sleep and wakeup but the lowest power
consumption while in Deep-Sleep mode.
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System Control
Register 20: LDO Sleep Power Control (LDOSPCTL), offset 0x1B4
This register specifies the LDO output voltage while in Sleep mode. Writes to the VLDO bit field have
no effect on the LDO output voltage, regardless of what is specified for the VADJEN bit. The LDO
output voltage is fixed at the recommended factory reset value.
The table below shows the maximum system clock frequency and PIOSC frequency with respect
to the configured LDO voltage.
Operating Voltage (LDO)
Maximum System Clock Frequency
PIOSC
1.2
80 MHz
16 MHz
0.9
20 MHz
16 MHz
Note:
■ The LDO will not automatically adjust in Sleep/Deepsleep mode if a debugger has been
connected since the last power-on reset.
■ If the LDO voltage is adjusted, it will take an extra 4 us to wake up from Sleep or
Deep-Sleep mode.
LDO Sleep Power Control (LDOSPCTL)
Base 0x400F.E000
Offset 0x1B4
Type RW, reset 0x0000.0018
31
30
29
28
27
26
25
24
22
21
20
19
18
17
16
RW
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RW
0
RW
0
RW
0
RW
1
RW
1
RW
0
RW
0
RW
0
VADJEN
Type
Reset
23
reserved
reserved
Type
Reset
VLDO
RO
0
Bit/Field
Name
Type
Reset
31
VADJEN
RW
0
Description
Voltage Adjust Enable
This bit enables the value of the VLDO field to be used to specify the
output voltage of the LDO in Sleep mode.
Value Description
30:8
reserved
RO
0x000.00
0
The LDO output voltage is set to the factory default value in
Sleep mode. The value of the VLDO field does not affect the
LDO operation.
1
The LDO output value in Sleep mode is configured by the value
in the VLDO field.
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
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Bit/Field
Name
Type
Reset
Description
7:0
VLDO
RW
0x18
LDO Output Voltage
This field provides program control of the LDO output voltage in Run
mode. The value of the field is only used for the LDO voltage when the
VADJEN bit is set.
For lowest power in Sleep mode, it is recommended to configure an
LDO output voltage that is equal to or lower than the default value of
1.2 V.
Value
Description
0x12
0.90 V
0x13
0.95 V
0x14
1.00 V
0x15
1.05 V
0x16
1.10 V
0x17
1.15 V
0x18
1.20 V
0x19 - 0xFF reserved
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System Control
Register 21: LDO Sleep Power Calibration (LDOSPCAL), offset 0x1B8
This register provides factory determined values that are recommended for the VLDO field in the
LDOSPCTL register while in Sleep mode.
LDO Sleep Power Calibration (LDOSPCAL)
Base 0x400F.E000
Offset 0x1B8
Type RO, reset 0x0000.1818
31
30
29
28
27
26
25
24
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
RO
0
RO
0
RO
0
RO
1
RO
0
RO
0
23
22
21
20
19
18
17
16
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
8
7
6
5
4
3
2
1
0
RO
0
RO
0
RO
0
RO
0
RO
1
RO
1
RO
0
RO
0
RO
0
reserved
Type
Reset
WITHPLL
Type
Reset
NOPLL
RO
1
Bit/Field
Name
Type
Reset
Description
31:16
reserved
RO
0x0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
15:8
WITHPLL
RO
0x18
Sleep with PLL
The value in this field is the suggested value for the VLDO field in the
LDOSPCTL register when using the PLL. This value provides the lowest
recommended LDO output voltage for use with the PLL at the maximum
specified value.
7:0
NOPLL
RO
0x18
Sleep without PLL
The value in this field is the suggested value for the VLDO field in the
LDOSPCTL register when not using the PLL. This value provides the
lowest recommended LDO output voltage for use without the PLL.
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Register 22: LDO Deep-Sleep Power Control (LDODPCTL), offset 0x1BC
This register specifies the LDO output voltage while in Deep-Sleep mode. This register must be
configured in Run mode before entering Deep-Sleep. Writes to the VLDO bit field have no effect on
the LDO output voltage, regardless of what is specified for the VADJEN bit. The LDO output voltage
is fixed at the recommended factory reset value.
The table below shows the maximum system clock frequency and PIOSC frequency with respect
to the configured LDO voltage.
Operating Voltage (LDO)
Maximum System Clock Frequency
PIOSC
1.2
80 MHz
16 MHz
0.9
20 MHz
16 MHz
Note:
■ The LDO will not automatically adjust in Sleep/Deepsleep mode if a debugger has been
connected since the last power-on reset.
■ If the LDO voltage is adjusted, it will take an extra 4 us to wake up from Sleep or
Deep-Sleep mode.
LDO Deep-Sleep Power Control (LDODPCTL)
Base 0x400F.E000
Offset 0x1BC
Type RW, reset 0x0000.0012
31
30
29
28
27
26
25
24
22
21
20
19
18
17
16
RW
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RW
0
RW
0
RW
0
RW
1
RW
0
RW
0
RW
1
RW
0
VADJEN
Type
Reset
23
reserved
reserved
Type
Reset
VLDO
RO
0
Bit/Field
Name
Type
Reset
31
VADJEN
RW
0
Description
Voltage Adjust Enable
This bit enables the value of the VLDO field to be used to specify the
output voltage of the LDO in Deep-Sleep mode.
Value Description
30:8
reserved
RO
0x000.00
0
The LDO output voltage is set to the factory default value in
Deep-Sleep mode. The value of the VLDO field does not affect
the LDO operation.
1
The LDO output value in Deep-Sleep mode is configured by the
value in the VLDO field.
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
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Bit/Field
Name
Type
Reset
Description
7:0
VLDO
RW
0x12
LDO Output Voltage
This field provides program control of the LDO output voltage in Run
mode. The value of the field is only used for the LDO voltage when the
VADJEN bit is set.
For lowest power in Deep-Sleep mode, it is recommended to configure
the LDO output voltage to the default value of 0.90 V.
Value
Description
0x12
0.90 V
0x13
0.95 V
0x14
1.00 V
0x15
1.05 V
0x16
1.10 V
0x17
1.15 V
0x18
1.20 V
0x19 - 0xFF reserved
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Register 23: LDO Deep-Sleep Power Calibration (LDODPCAL), offset 0x1C0
This register provides factory determined values that are recommended for the VLDO field in the
LDODPCTL register while in Deep-Sleep mode.
LDO Deep-Sleep Power Calibration (LDODPCAL)
Base 0x400F.E000
Offset 0x1C0
Type RO, reset 0x0000.1212
31
30
29
28
27
26
25
24
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
RO
0
RO
0
RO
0
RO
1
RO
0
RO
0
RO
1
23
22
21
20
19
18
17
16
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
8
7
6
5
4
3
2
1
0
RO
0
RO
0
RO
0
RO
0
RO
1
RO
0
RO
0
RO
1
RO
0
reserved
Type
Reset
NOPLL
Type
Reset
30KHZ
Bit/Field
Name
Type
Reset
Description
31:16
reserved
RO
0x0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
15:8
NOPLL
RO
0x12
Deep-Sleep without PLL
The value in this field is the suggested value for the VLDO field in the
LDODPCTL register when not using the PLL. This value provides the
lowest recommended LDO output voltage for use with the system clock.
7:0
30KHZ
RO
0x12
Deep-Sleep with IOSC
The value in this field is the suggested value for the VLDO field in the
LDODPCTL register when not using the PLL. This value provides the
lowest recommended LDO output voltage for use with the low-frequency
internal oscillator.
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Register 24: Sleep / Deep-Sleep Power Mode Status (SDPMST), offset 0x1CC
This register provides status information on the Sleep and Deep-Sleep power modes as well as
some real time status that can be viewed by a debugger or the core if it is running. These events
do not trigger an interrupt and are meant to provide information that can help tune software for power
management. The status register gets written at the beginning of every Dynamic Power Management
event request with the results of any error checking. There is no mechanism to clear the bits; they
are overwritten on the next event. The LDOUA, FLASHLP, LOWPWR, PRACT bits provide real time
data and there are no events to register that information.
Sleep / Deep-Sleep Power Mode Status (SDPMST)
Base 0x400F.E000
Offset 0x1CC
Type RO, reset 0x0000.0000
31
30
29
28
27
26
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
RO
0
RO
0
RO
0
RO
0
25
24
23
22
21
20
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
10
9
8
7
6
5
4
3
2
1
0
RO
0
RO
0
RO
0
reserved
Type
Reset
PPDW
RO
0
18
17
16
LDOUA FLASHLP LOWPWR PRACT
reserved
Type
Reset
19
RO
0
LMAXERR reserved LSMINERR LDMINERR PPDERR FPDERR SPDERR
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
Bit/Field
Name
Type
Reset
Description
31:20
reserved
RO
0x000
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
19
LDOUA
RO
0
LDO Update Active
Value Description
18
FLASHLP
RO
0
0
The LDO voltage level is not changing.
1
The LDO voltage level is changing.
Flash Memory in Low Power State
Value Description
17
LOWPWR
RO
0
0
The Flash memory is currently in the active state.
1
The Flash memory is currently in the low power state as
programmed in the SLPPWRCFG or DSLPPWRCFG register.
Sleep or Deep-Sleep Mode
Value Description
0
The microcontroller is currently in Run mode.
1
The microcontroller is currently in Sleep or Deep-Sleep mode
and is waiting for an interrupt or is in the process of powering
up. The status of this bit is not affected by the power state of
the Flash memory or SRAM.
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Bit/Field
Name
Type
Reset
16
PRACT
RO
0
Description
Sleep or Deep-Sleep Power Request Active
Value Description
15:8
reserved
RO
0x00
7
PPDW
RO
0
0
A power request is not active.
1
The microcontroller is currently in Deep-Sleep mode or is in
Sleep mode and a request to put the SRAM and/or Flash
memory into a lower power mode is currently active as
configured by the SLPPWRCFG register.
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
PIOSC Power Down Request Warning
Value Description
6
LMAXERR
RO
0
0
No error.
1
A warning has occurred because software has requested that
the PIOSC be powered down during Deep-Sleep using the
PIOSCPD bit in the DSLPCLKCFG register and a peripheral
requires that it be active in Deep-Sleep. The PIOSC is powered
down regardless of the warning.
VLDO Value Above Maximum Error
Value Description
0
No error.
1
An error has occurred because software has requested that the
LDO voltage be above the maximum value allowed using the
VLDO bit in the LDOSPCTL or LDODPCTL register.
In this situation, the LDO is set to the factory default value.
5
reserved
RO
0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
4
LSMINERR
RO
0
VLDO Value Below Minimum Error in Sleep Mode
Value Description
0
No error.
1
An error has occurred because software has requested that the
LDO voltage be below the minimum value allowed using the
VLDO bit in the LDOSPCTL register.
In this situation, the LDO voltage is not changed when entering
Sleep mode.
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Bit/Field
Name
Type
Reset
3
LDMINERR
RO
0
Description
VLDO Value Below Minimum Error in Deep-Sleep Mode
Value Description
0
No error.
1
An error has occurred because software has requested that the
LDO voltage be below the minimum value allowed using the
VLDO bit in the LDODPCTL register.
In this situation, the LDO voltage is not changed when entering
Deep-Sleep mode.
2
PPDERR
RO
0
PIOSC Power Down Request Error
Value Description
0
No error.
1
An error has occurred because software has requested that the
PIOSC be powered down during Deep-Sleep and it is not
possible to power down the PIOSC.
In this situation, the PIOSC is not powered down when entering
Deep-Sleep mode.
1
FPDERR
RO
0
Flash Memory Power Down Request Error
Value Description
0
SPDERR
RO
0
0
No error.
1
An error has occurred because software has requested a Flash
memory power down mode that is not available using the
FLASHPM field in the SLPPWRCFG or the DSLPPWRCFG
register.
SRAM Power Down Request Error
Value Description
0
No error.
1
An error has occurred because software has requested an
SRAM power down mode that is not available using the SRAMPM
field in the SLPPWRCFG or the DSLPPWRCFG register.
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Register 25: Watchdog Timer Peripheral Present (PPWD), offset 0x300
The PPWD register provides software information regarding the watchdog modules.
Important: This register should be used to determine which watchdog timers are implemented on
this microcontroller. However, to support legacy software, the DC1 register is available.
A read of the DC1 register correctly identifies if a legacy module is present.
Watchdog Timer Peripheral Present (PPWD)
Base 0x400F.E000
Offset 0x300
Type RO, reset 0x0000.0003
31
30
29
28
27
26
25
24
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
23
22
21
20
19
18
17
16
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
8
7
6
5
4
3
2
1
0
P1
P0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
1
RO
1
reserved
Type
Reset
reserved
Type
Reset
Bit/Field
Name
Type
Reset
31:2
reserved
RO
0
1
P1
RO
0x1
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
Watchdog Timer 1 Present
Value Description
0
P0
RO
0x1
0
Watchdog module 1 is not present.
1
Watchdog module 1 is present.
Watchdog Timer 0 Present
Value Description
0
Watchdog module 0 is not present.
1
Watchdog module 0 is present.
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System Control
Register 26: 16/32-Bit General-Purpose Timer Peripheral Present (PPTIMER),
offset 0x304
The PPTIMER register provides software information regarding the 16/32-bit general-purpose timer
modules.
Important: This register should be used to determine which timers are implemented on this
microcontroller. However, to support legacy software, the DC2 register is available. A
read of the DC2 register correctly identifies if a legacy module is present. Software must
use this register to determine if a module that is not supported by the DC2 register is
present.
16/32-Bit General-Purpose Timer Peripheral Present (PPTIMER)
Base 0x400F.E000
Offset 0x304
Type RO, reset 0x0000.003F
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
8
7
6
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
Bit/Field
Name
Type
Reset
31:6
reserved
RO
0
5
P5
RO
0x1
RO
0
RO
0
RO
0
5
4
3
2
1
0
P5
P4
P3
P2
P1
P0
RO
1
RO
1
RO
1
RO
1
RO
1
RO
1
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
16/32-Bit General-Purpose Timer 5 Present
Value Description
4
P4
RO
0x1
0
16/32-bit general-purpose timer module 6 is not present.
1
16/32-bit general-purpose timer module 5 is present.
16/32-Bit General-Purpose Timer 4 Present
Value Description
3
P3
RO
0x1
0
16/32-bit general-purpose timer module 4 is not present.
1
16/32-bit general-purpose timer module 4 is present.
16/32-Bit General-Purpose Timer 3 Present
Value Description
0
16/32-bit general-purpose timer module 3 is not present.
1
16/32-bit general-purpose timer module 3 is present.
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Bit/Field
Name
Type
Reset
2
P2
RO
0x1
Description
16/32-Bit General-Purpose Timer 2 Present
Value Description
1
P1
RO
0x1
0
16/32-bit general-purpose timer module 2 is not present.
1
16/32-bit general-purpose timer module 2 is present.
16/32-Bit General-Purpose Timer 1 Present
Value Description
0
P0
RO
0x1
0
16/32-bit general-purpose timer module 1 is not present.
1
16/32-bit general-purpose timer module 1 is present.
16/32-Bit General-Purpose Timer 0 Present
Value Description
0
16/32-bit general-purpose timer module 0 is not present.
1
16/32-bit general-purpose timer module 0 is present.
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Register 27: General-Purpose Input/Output Peripheral Present (PPGPIO),
offset 0x308
The PPGPIO register provides software information regarding the general-purpose input/output
modules.
Important: This register should be used to determine which GPIO ports are implemented on this
microcontroller. However, to support legacy software, the DC4 register is available. A
read of the DC4 register correctly identifies if a legacy module is present. Software must
use this register to determine if a module that is not supported by the DC4 register is
present.
General-Purpose Input/Output Peripheral Present (PPGPIO)
Base 0x400F.E000
Offset 0x308
Type RO, reset 0x0000.007F
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
reserved
Type
Reset
RO
0
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
reserved
P14
P13
P12
P11
P10
P9
P8
P7
P6
P5
P4
P3
P2
P1
P0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
1
RO
1
RO
1
RO
1
RO
1
RO
1
RO
1
Bit/Field
Name
Type
Reset
31:15
reserved
RO
0
14
P14
RO
0x0
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
GPIO Port Q Present
Value Description
13
P13
RO
0x0
0
GPIO Port Q is not present.
1
GPIO Port Q is present.
GPIO Port P Present
Value Description
12
P12
RO
0x0
0
GPIO Port P is not present.
1
GPIO Port P is present.
GPIO Port N Present
Value Description
0
GPIO Port N is not present.
1
GPIO Port N is present.
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Tiva™ TM4C1230C3PM Microcontroller
Bit/Field
Name
Type
Reset
11
P11
RO
0x0
Description
GPIO Port M Present
Value Description
10
P10
RO
0x0
0
GPIO Port M is not present.
1
GPIO Port M is present.
GPIO Port L Present
Value Description
9
P9
RO
0x0
0
GPIO Port L is not present.
1
GPIO Port L is present.
GPIO Port K Present
Value Description
8
P8
RO
0x0
0
GPIO Port K is not present.
1
GPIO Port K is present.
GPIO Port J Present
Value Description
7
P7
RO
0x0
0
GPIO Port J is not present.
1
GPIO Port J is present.
GPIO Port H Present
Value Description
6
P6
RO
0x1
0
GPIO Port H is not present.
1
GPIO Port H is present.
GPIO Port G Present
Value Description
5
P5
RO
0x1
0
GPIO Port G is not present.
1
GPIO Port G is present.
GPIO Port F Present
Value Description
0
GPIO Port F is not present.
1
GPIO Port F is present.
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Bit/Field
Name
Type
Reset
4
P4
RO
0x1
Description
GPIO Port E Present
Value Description
3
P3
RO
0x1
0
GPIO Port E is not present.
1
GPIO Port E is present.
GPIO Port D Present
Value Description
2
P2
RO
0x1
0
GPIO Port D is not present.
1
GPIO Port D is present.
GPIO Port C Present
Value Description
1
P1
RO
0x1
0
GPIO Port C is not present.
1
GPIO Port C is present.
GPIO Port B Present
Value Description
0
P0
RO
0x1
0
GPIO Port B is not present.
1
GPIO Port B is present.
GPIO Port A Present
Value Description
0
GPIO Port A is not present.
1
GPIO Port A is present.
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Register 28: Micro Direct Memory Access Peripheral Present (PPDMA), offset
0x30C
The PPDMA register provides software information regarding the μDMA module.
Important: This register should be used to determine if the μDMA module is implemented on this
microcontroller. However, to support legacy software, the DC7 register is available. A
read of the DC7 register correctly identifies if the μDMA module is present.
Micro Direct Memory Access Peripheral Present (PPDMA)
Base 0x400F.E000
Offset 0x30C
Type RO, reset 0x0000.0001
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
RO
0
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
8
7
6
5
4
3
2
1
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
Bit/Field
Name
Type
Reset
31:1
reserved
RO
0
0
P0
RO
0x1
RO
0
0
P0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
1
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
μDMA Module Present
Value Description
0
μDMA module is not present.
1
μDMA module is present.
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Register 29: Hibernation Peripheral Present (PPHIB), offset 0x314
The PPHIB register provides software information regarding the Hibernation module.
Important: This register should be used to determine if the Hibernation module is implemented on
this microcontroller. However, to support legacy software, the DC1 register is available.
A read of the DC1 register correctly identifies if the Hibernation module is present.
Hibernation Peripheral Present (PPHIB)
Base 0x400F.E000
Offset 0x314
Type RO, reset 0x0000.0000
31
30
29
28
27
26
25
24
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
8
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
23
22
21
20
19
18
17
16
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
7
6
5
4
3
2
1
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
reserved
Type
Reset
reserved
Type
Reset
Bit/Field
Name
Type
Reset
31:1
reserved
RO
0
0
P0
RO
0x0
RO
0
P0
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
Hibernation Module Present
Value Description
0
Hibernation module is not present.
1
Hibernation module is present.
274
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Tiva™ TM4C1230C3PM Microcontroller
Register 30: Universal Asynchronous Receiver/Transmitter Peripheral Present
(PPUART), offset 0x318
The PPUART register provides software information regarding the UART modules.
Important: This register should be used to determine which UART modules are implemented on
this microcontroller. However, to support legacy software, the DC2 register is available.
A read of the DC2 register correctly identifies if a legacy UART module is present.
Software must use this register to determine if a module that is not supported by the
DC2 register is present.
Universal Asynchronous Receiver/Transmitter Peripheral Present (PPUART)
Base 0x400F.E000
Offset 0x318
Type RO, reset 0x0000.00FF
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
8
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
Bit/Field
Name
Type
Reset
31:8
reserved
RO
0
7
P7
RO
0x1
RO
0
RO
0
7
6
5
4
3
2
1
0
P7
P6
P5
P4
P3
P2
P1
P0
RO
1
RO
1
RO
1
RO
1
RO
1
RO
1
RO
1
RO
1
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
UART Module 7 Present
Value Description
6
P6
RO
0x1
0
UART module 7 is not present.
1
UART module 7 is present.
UART Module 6 Present
Value Description
5
P5
RO
0x1
0
UART module 6 is not present.
1
UART module 6 is present.
UART Module 5 Present
Value Description
0
UART module 5 is not present.
1
UART module 5 is present.
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Bit/Field
Name
Type
Reset
4
P4
RO
0x1
Description
UART Module 4 Present
Value Description
3
P3
RO
0x1
0
UART module 4 is not present.
1
UART module 4 is present.
UART Module 3 Present
Value Description
2
P2
RO
0x1
0
UART module 3 is not present.
1
UART module 3 is present.
UART Module 2 Present
Value Description
1
P1
RO
0x1
0
UART module 2 is not present.
1
UART module 2 is present.
UART Module 1 Present
Value Description
0
P0
RO
0x1
0
UART module 1 is not present.
1
UART module 1 is present.
UART Module 0 Present
Value Description
0
UART module 0 is not present.
1
UART module 0 is present.
276
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Tiva™ TM4C1230C3PM Microcontroller
Register 31: Synchronous Serial Interface Peripheral Present (PPSSI), offset
0x31C
The PPSSI register provides software information regarding the SSI modules.
Important: This register should be used to determine which SSI modules are implemented on this
microcontroller. However, to support legacy software, the DC2 register is available. A
read of the DC2 register correctly identifies if a legacy SSI module is present. Software
must use this register to determine if a module that is not supported by the DC2 register
is present.
Synchronous Serial Interface Peripheral Present (PPSSI)
Base 0x400F.E000
Offset 0x31C
Type RO, reset 0x0000.000F
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
RO
0
RO
0
RO
0
RO
0
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
8
7
6
5
4
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
Bit/Field
Name
Type
Reset
31:4
reserved
RO
0
3
P3
RO
0x1
RO
0
RO
0
RO
0
RO
0
RO
0
3
2
1
0
P3
P2
P1
P0
RO
1
RO
1
RO
1
RO
1
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
SSI Module 3 Present
Value Description
2
P2
RO
0x1
0
SSI module 3 is not present.
1
SSI module 3 is present.
SSI Module 2 Present
Value Description
1
P1
RO
0x1
0
SSI module 2 is not present.
1
SSI module 2 is present.
SSI Module 1 Present
Value Description
0
SSI module 1 is not present.
1
SSI module 1 is present.
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Bit/Field
Name
Type
Reset
0
P0
RO
0x1
Description
SSI Module 0 Present
Value Description
0
SSI module 0 is not present.
1
SSI module 0 is present.
278
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Tiva™ TM4C1230C3PM Microcontroller
Register 32: Inter-Integrated Circuit Peripheral Present (PPI2C), offset 0x320
The PPI2C register provides software information regarding the I2C modules.
Important: This register should be used to determine which I2C modules are implemented on this
microcontroller. However, to support legacy software, the DC2 register is available. A
read of the DC2 register correctly identifies if a legacy I2C module is present. Software
must use this register to determine if a module that is not supported by the DC2 register
is present.
Inter-Integrated Circuit Peripheral Present (PPI2C)
Base 0x400F.E000
Offset 0x320
Type RO, reset 0x0000.003F
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
8
7
6
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
Bit/Field
Name
Type
Reset
31:6
reserved
RO
0
5
P5
RO
0x1
RO
0
RO
0
RO
0
5
4
3
2
1
0
P5
P4
P3
P2
P1
P0
RO
1
RO
1
RO
1
RO
1
RO
1
RO
1
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
I2C Module 5 Present
Value Description
4
P4
RO
0x1
0
I2C module 5 is not present.
1
I2C module 5 is present.
I2C Module 4 Present
Value Description
3
P3
RO
0x1
0
I2C module 4 is not present.
1
I2C module 4 is present.
I2C Module 3 Present
Value Description
0
I2C module 3 is not present.
1
I2C module 3 is present.
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Bit/Field
Name
Type
Reset
2
P2
RO
0x1
Description
I2C Module 2 Present
Value Description
1
P1
RO
0x1
0
I2C module 2 is not present.
1
I2C module 2 is present.
I2C Module 1 Present
Value Description
0
P0
RO
0x1
0
I2C module 1 is not present.
1
I2C module 1 is present.
I2C Module 0 Present
Value Description
0
I2C module 0 is not present.
1
I2C module 0 is present.
280
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Tiva™ TM4C1230C3PM Microcontroller
Register 33: Universal Serial Bus Peripheral Present (PPUSB), offset 0x328
The PPUSB register provides software information regarding the USB module.
Important: This register should be used to determine if the USB module is implemented on this
microcontroller. However, to support legacy software, the DC6 register is available. A
read of the DC6 register correctly identifies if the USB module is present.
Universal Serial Bus Peripheral Present (PPUSB)
Base 0x400F.E000
Offset 0x328
Type RO, reset 0x0000.0000
31
30
29
28
27
26
25
24
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
8
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
23
22
21
20
19
18
17
16
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
7
6
5
4
3
2
1
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
reserved
Type
Reset
reserved
Type
Reset
Bit/Field
Name
Type
Reset
31:1
reserved
RO
0
0
P0
RO
0x0
RO
0
P0
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
USB Module Present
Value Description
0
USB module is not present.
1
USB module is present.
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System Control
Register 34: Controller Area Network Peripheral Present (PPCAN), offset 0x334
The PPCAN register provides software information regarding the CAN modules.
Important: This register should be used to determine which CAN modules are implemented on
this microcontroller. However, to support legacy software, the DC1 register is available.
A read of the DC1 register correctly identifies if a legacy CAN module is present.
Controller Area Network Peripheral Present (PPCAN)
Base 0x400F.E000
Offset 0x334
Type RO, reset 0x0000.0001
31
30
29
28
27
26
25
24
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
23
22
21
20
19
18
17
16
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
8
7
6
5
4
3
2
1
0
P1
P0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
1
reserved
Type
Reset
reserved
Type
Reset
Bit/Field
Name
Type
Reset
31:2
reserved
RO
0
1
P1
RO
0x0
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
CAN Module 1 Present
Value Description
0
P0
RO
0x1
0
CAN module 1 is not present.
1
CAN module 1 is present.
CAN Module 0 Present
Value Description
0
CAN module 0 is not present.
1
CAN module 0 is present.
282
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Tiva™ TM4C1230C3PM Microcontroller
Register 35: Analog-to-Digital Converter Peripheral Present (PPADC), offset
0x338
The PPADC register provides software information regarding the ADC modules.
Important: This register should be used to determine which ADC modules are implemented on
this microcontroller. However, to support legacy software, the DC1 register is available.
A read of the DC1 register correctly identifies if a legacy ADC module is present.
Analog-to-Digital Converter Peripheral Present (PPADC)
Base 0x400F.E000
Offset 0x338
Type RO, reset 0x0000.0003
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
RO
0
RO
0
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
Bit/Field
Name
Type
Reset
31:2
reserved
RO
0
1
P1
RO
0x1
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
1
0
P1
P0
RO
1
RO
1
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
ADC Module 1 Present
Value Description
0
P0
RO
0x1
0
ADC module 1 is not present.
1
ADC module 1 is present.
ADC Module 0 Present
Value Description
0
ADC module 0 is not present.
1
ADC module 0 is present.
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Register 36: Analog Comparator Peripheral Present (PPACMP), offset 0x33C
The PPACMP register provides software information regarding the analog comparator module.
Important: This register should be used to determine if the analog comparator module is
implemented on this microcontroller. However, to support legacy software, the DC2
register is available. A read of the DC2 register correctly identifies if the analog
comparator module is present.
Note that the Analog Comparator Peripheral Properties (ACMPPP) register indicates
how many analog comparator blocks are included in the module.
Analog Comparator Peripheral Present (PPACMP)
Base 0x400F.E000
Offset 0x33C
Type RO, reset 0x0000.0001
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
RO
0
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
8
7
6
5
4
3
2
1
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
Bit/Field
Name
Type
Reset
31:1
reserved
RO
0
0
P0
RO
0x1
RO
0
0
P0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
1
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
Analog Comparator Module Present
Value Description
0
Analog comparator module is not present.
1
Analog comparator module is present.
284
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Tiva™ TM4C1230C3PM Microcontroller
Register 37: Pulse Width Modulator Peripheral Present (PPPWM), offset 0x340
The PPPWM register provides software information regarding the PWM modules.
Important: This register should be used to determine which PWM modules are implemented on
this microcontroller. However, to support legacy software, the DC1 register is available.
A read of the DC1 register correctly identifies if the legacy PWM module is present.
Software must use this register to determine if a module that is not supported by the
DC1 register is present.
Pulse Width Modulator Peripheral Present (PPPWM)
Base 0x400F.E000
Offset 0x340
Type RO, reset 0x0000.0000
31
30
29
28
27
26
25
24
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
23
22
21
20
19
18
17
16
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
8
7
6
5
4
3
2
1
0
P1
P0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
reserved
Type
Reset
reserved
Type
Reset
Bit/Field
Name
Type
Reset
31:2
reserved
RO
0
1
P1
RO
0x0
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
PWM Module 1 Present
Value Description
0
P0
RO
0x0
0
PWM module 1 is not present.
1
PWM module 1 is present.
PWM Module 0 Present
Value Description
0
PWM module 0 is not present.
1
PWM module 0 is present.
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Register 38: Quadrature Encoder Interface Peripheral Present (PPQEI), offset
0x344
The PPQEI register provides software information regarding the QEI modules.
Important: This register should be used to determine which QEI modules are implemented on this
microcontroller. However, to support legacy software, the DC2 register is available. A
read of the DC2 register correctly identifies if a legacy QEI module is present.
Quadrature Encoder Interface Peripheral Present (PPQEI)
Base 0x400F.E000
Offset 0x344
Type RO, reset 0x0000.0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
RO
0
RO
0
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
Bit/Field
Name
Type
Reset
31:2
reserved
RO
0
1
P1
RO
0x0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
1
0
P1
P0
RO
0
RO
0
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
QEI Module 1 Present
Value Description
0
P0
RO
0x0
0
QEI module 1 is not present.
1
QEI module 1 is present.
QEI Module 0 Present
Value Description
0
QEI module 0 is not present.
1
QEI module 0 is present.
286
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Tiva™ TM4C1230C3PM Microcontroller
Register 39: EEPROM Peripheral Present (PPEEPROM), offset 0x358
The PPEEPROM register provides software information regarding the EEPROM module.
EEPROM Peripheral Present (PPEEPROM)
Base 0x400F.E000
Offset 0x358
Type RO, reset 0x0000.0001
31
30
29
28
27
26
25
24
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
8
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
23
22
21
20
19
18
17
16
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
7
6
5
4
3
2
1
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
1
reserved
Type
Reset
reserved
Type
Reset
Bit/Field
Name
Type
Reset
31:1
reserved
RO
0
0
P0
RO
0x1
RO
0
P0
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
EEPROM Module Present
Value Description
0
EEPROM module is not present.
1
EEPROM module is present.
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Register 40: 32/64-Bit Wide General-Purpose Timer Peripheral Present
(PPWTIMER), offset 0x35C
The PPWTIMER register provides software information regarding the 32/64-bit wide general-purpose
timer modules.
32/64-Bit Wide General-Purpose Timer Peripheral Present (PPWTIMER)
Base 0x400F.E000
Offset 0x35C
Type RO, reset 0x0000.003F
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
8
7
6
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
Bit/Field
Name
Type
Reset
31:6
reserved
RO
0
5
P5
RO
0x1
RO
0
RO
0
RO
0
5
4
3
2
1
0
P5
P4
P3
P2
P1
P0
RO
1
RO
1
RO
1
RO
1
RO
1
RO
1
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
32/64-Bit Wide General-Purpose Timer 5 Present
Value Description
4
P4
RO
0x1
0
32/64-bit wide general-purpose timer module 5 is not present.
1
32/64-bit wide general-purpose timer module 5 is present.
32/64-Bit Wide General-Purpose Timer 4 Present
Value Description
3
P3
RO
0x1
0
32/64-bit wide general-purpose timer module 4 is not present.
1
32/64-bit wide general-purpose timer module 4 is present.
32/64-Bit Wide General-Purpose Timer 3 Present
Value Description
2
P2
RO
0x1
0
32/64-bit wide general-purpose timer module 3 is not present.
1
32/64-bit wide general-purpose timer module 3 is present.
32/64-Bit Wide General-Purpose Timer 2 Present
Value Description
0
32/64-bit wide general-purpose timer module 2 is not present.
1
32/64-bit wide general-purpose timer module 2 is present.
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Bit/Field
Name
Type
Reset
1
P1
RO
0x1
Description
32/64-Bit Wide General-Purpose Timer 1 Present
Value Description
0
P0
RO
0x1
0
32/64-bit wide general-purpose timer module 1 is not present.
1
32/64-bit wide general-purpose timer module 1 is present.
32/64-Bit Wide General-Purpose Timer 0 Present
Value Description
0
32/64-bit wide general-purpose timer module 0 is not present.
1
32/64-bit wide general-purpose timer module 0 is present.
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System Control
Register 41: Watchdog Timer Software Reset (SRWD), offset 0x500
The SRWD register provides software the capability to reset the available watchdog modules. This
register provides the same capability as the legacy Software Reset Control n SRCRn registers
specifically for the watchdog modules and has the same bit polarity as the corresponding SRCRn
bits.
A peripheral is reset by software using a simple two-step process:
1. Software sets a bit (or bits) in the SRWD register. While the SRWD bit is 1, the peripheral is
held in reset.
2. Software completes the reset process by clearing the SRWD bit.
There may be latency from the clearing of the SRWD bit to when the peripheral is ready for use.
Software can check the corresponding PRWD bit to be sure.
Important: This register should be used to reset the watchdog modules. To support legacy software,
the SRCR0 register is available. Setting a bit in the SRCR0 register also resets the
corresponding module. Any bits that are changed by writing to the SRCR0 register can
be read back correctly when reading the SRCR0 register. If software uses this register
to reset a legacy peripheral (such as Watchdog 1), the write causes proper operation,
but the value of that bit is not reflected in the SRCR0 register. If software uses both
legacy and peripheral-specific register accesses, the peripheral-specific registers must
be accessed by read-modify-write operations that affect only peripherals that are not
present in the legacy registers. In this manner, both the peripheral-specific and legacy
registers have coherent information.
Watchdog Timer Software Reset (SRWD)
Base 0x400F.E000
Offset 0x500
Type RW, reset 0x0000.0000
31
30
29
28
27
26
25
24
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
23
22
21
20
19
18
17
16
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
8
7
6
5
4
3
2
1
0
R1
R0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RW
0
RW
0
reserved
Type
Reset
reserved
Type
Reset
Bit/Field
Name
Type
Reset
Description
31:2
reserved
RO
0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
1
R1
RW
0
Watchdog Timer 1 Software Reset
Value Description
0
Watchdog module 1 is not reset.
1
Watchdog module 1 is reset.
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Bit/Field
Name
Type
Reset
0
R0
RW
0
Description
Watchdog Timer 0 Software Reset
Value Description
0
Watchdog module 0 is not reset.
1
Watchdog module 0 is reset.
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System Control
Register 42: 16/32-Bit General-Purpose Timer Software Reset (SRTIMER),
offset 0x504
The SRTIMER register provides software the capability to reset the available 16/32-bit timer modules.
This register provides the same capability as the legacy Software Reset Control n SRCRn registers
specifically for the timer modules and has the same bit polarity as the corresponding SRCRn bits.
A peripheral is reset by software using a simple two-step process:
1. Software sets a bit (or bits) in the SRTIMER register. While the SRTIMER bit is 1, the peripheral
is held in reset.
2. Software completes the reset process by clearing the SRTIMER bit.
There may be latency from the clearing of the SRTIMER bit to when the peripheral is ready for use.
Software can check the corresponding PRTIMER bit to be sure.
Important: This register should be used to reset the timer modules. To support legacy software,
the SRCR1 register is available. Setting a bit in the SRCR1 register also resets the
corresponding module. Any bits that are changed by writing to the SRCR1 register can
be read back correctly when reading the SRCR1 register. Software must use this register
to reset modules that are not present in the legacy registers. If software uses this register
to reset a legacy peripheral (such as Timer 1), the write causes proper operation, but
the value of that bit is not reflected in the SRCR1 register. If software uses both legacy
and peripheral-specific register accesses, the peripheral-specific registers must be
accessed by read-modify-write operations that affect only peripherals that are not present
in the legacy registers. In this manner, both the peripheral-specific and legacy registers
have coherent information.
16/32-Bit General-Purpose Timer Software Reset (SRTIMER)
Base 0x400F.E000
Offset 0x504
Type RW, reset 0x0000.0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
8
7
6
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
5
4
3
2
1
0
R5
R4
R3
R2
R1
R0
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
Bit/Field
Name
Type
Reset
Description
31:6
reserved
RO
0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
5
R5
RW
0
16/32-Bit General-Purpose Timer 5 Software Reset
Value Description
0
16/32-bit general-purpose timer module 5 is not reset.
1
16/32-bit general-purpose timer module 5 is reset.
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Bit/Field
Name
Type
Reset
4
R4
RW
0
Description
16/32-Bit General-Purpose Timer 4 Software Reset
Value Description
3
R3
RW
0
0
16/32-bit general-purpose timer module 4 is not reset.
1
16/32-bit general-purpose timer module 4 is reset.
16/32-Bit General-Purpose Timer 3 Software Reset
Value Description
2
R2
RW
0
0
16/32-bit general-purpose timer module 3 is not reset.
1
16/32-bit general-purpose timer module 3 is reset.
16/32-Bit General-Purpose Timer 2 Software Reset
Value Description
1
R1
RW
0
0
16/32-bit general-purpose timer module 2 is not reset.
1
16/32-bit general-purpose timer module 2 is reset.
16/32-Bit General-Purpose Timer 1 Software Reset
Value Description
0
R0
RW
0
0
16/32-bit general-purpose timer module 1 is not reset.
1
16/32-bit general-purpose timer module 1 is reset.
16/32-Bit General-Purpose Timer 0 Software Reset
Value Description
0
16/32-bit general-purpose timer module 0 is not reset.
1
16/32-bit general-purpose timer module 0 is reset.
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System Control
Register 43: General-Purpose Input/Output Software Reset (SRGPIO), offset
0x508
The SRGPIO register provides software the capability to reset the available GPIO modules. This
register provides the same capability as the legacy Software Reset Control n SRCRn registers
specifically for the GPIO modules and has the same bit polarity as the corresponding SRCRn bits.
A peripheral is reset by software using a simple two-step process:
1. Software sets a bit (or bits) in the SRGPIO register. While the SRGPIO bit is 1, the peripheral
is held in reset.
2. Software completes the reset process by clearing the SRGPIO bit.
There may be latency from the clearing of the SRGPIO bit to when the peripheral is ready for use.
Software can check the corresponding PRGPIO bit to be sure.
Important: This register should be used to reset the GPIO modules. To support legacy software,
the SRCR2 register is available. Setting a bit in the SRCR2 register also resets the
corresponding module. Any bits that are changed by writing to the SRCR2 register can
be read back correctly when reading the SRCR2 register. Software must use this register
to reset modules that are not present in the legacy registers. If software uses this register
to reset a legacy peripheral (such as GPIO A), the write causes proper operation, but
the value of that bit is not reflected in the SRCR2 register. If software uses both legacy
and peripheral-specific register accesses, the peripheral-specific registers must be
accessed by read-modify-write operations that affect only peripherals that are not present
in the legacy registers. In this manner, both the peripheral-specific and legacy registers
have coherent information.
General-Purpose Input/Output Software Reset (SRGPIO)
Base 0x400F.E000
Offset 0x508
Type RW, reset 0x0000.0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
15
14
13
12
RO
0
RO
0
RO
0
RO
0
RO
0
11
10
9
8
7
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
6
5
4
3
2
1
0
R6
R5
R4
R3
R2
R1
R0
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
Bit/Field
Name
Type
Reset
Description
31:7
reserved
RO
0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
6
R6
RW
0
GPIO Port G Software Reset
Value Description
0
GPIO Port G is not reset.
1
GPIO Port G is reset.
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Bit/Field
Name
Type
Reset
5
R5
RW
0
Description
GPIO Port F Software Reset
Value Description
4
R4
RW
0
0
GPIO Port F is not reset.
1
GPIO Port F is reset.
GPIO Port E Software Reset
Value Description
3
R3
RW
0
0
GPIO Port E is not reset.
1
GPIO Port E is reset.
GPIO Port D Software Reset
Value Description
2
R2
RW
0
0
GPIO Port D is not reset.
1
GPIO Port D is reset.
GPIO Port C Software Reset
Value Description
1
R1
RW
0
0
GPIO Port C is not reset.
1
GPIO Port C is reset.
GPIO Port B Software Reset
Value Description
0
R0
RW
0
0
GPIO Port B is not reset.
1
GPIO Port B is reset.
GPIO Port A Software Reset
Value Description
0
GPIO Port A is not reset.
1
GPIO Port A is reset.
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System Control
Register 44: Micro Direct Memory Access Software Reset (SRDMA), offset
0x50C
The SRDMA register provides software the capability to reset the available μDMA module. This
register provides the same capability as the legacy Software Reset Control n SRCRn registers
specifically for the μDMA module and has the same bit polarity as the corresponding SRCRn bits.
A peripheral is reset by software using a simple two-step process:
1. Software sets a bit (or bits) in the SRDMA register. While the SRDMA bit is 1, the peripheral is
held in reset.
2. Software completes the reset process by clearing the SRDMA bit.
There may be latency from the clearing of the SRDMA bit to when the peripheral is ready for use.
Software can check the corresponding PRDMA bit to be sure.
Important: This register should be used to reset the μDMA module. To support legacy software,
the SRCR2 register is available. Setting the UDMA bit in the SRCR2 register also resets
the μDMA module. If the UDMA bit is set by writing to the SRCR2 register, it can be read
back correctly when reading the SRCR2 register. If software uses this register to reset
the μDMA module, the write causes proper operation, but the value of the UDMA bit is
not reflected in the SRCR2 register. If software uses both legacy and peripheral-specific
register accesses, the peripheral-specific registers must be accessed by
read-modify-write operations that affect only peripherals that are not present in the
legacy registers. In this manner, both the peripheral-specific and legacy registers have
coherent information.
Micro Direct Memory Access Software Reset (SRDMA)
Base 0x400F.E000
Offset 0x50C
Type RW, reset 0x0000.0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
RO
0
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
8
7
6
5
4
3
2
1
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
0
R0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RW
0
Bit/Field
Name
Type
Reset
Description
31:1
reserved
RO
0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0
R0
RW
0
μDMA Module Software Reset
Value Description
0
μDMA module is not reset.
1
μDMA module is reset.
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Register 45: Universal Asynchronous Receiver/Transmitter Software Reset
(SRUART), offset 0x518
The SRUART register provides software the capability to reset the available UART modules. This
register provides the same capability as the legacy Software Reset Control n SRCRn registers
specifically for the UART modules and has the same bit polarity as the corresponding SRCRn bits.
A peripheral is reset by software using a simple two-step process:
1. Software sets a bit (or bits) in the SRUART register. While the SRUART bit is 1, the peripheral
is held in reset.
2. Software completes the reset process by clearing the SRUART bit.
There may be latency from the clearing of the SRUART bit to when the peripheral is ready for use.
Software can check the corresponding PRUART bit to be sure.
Important: This register should be used to reset the UART modules. To support legacy software,
the SRCR1 register is available. Setting a bit in the SRCR1 register also resets the
corresponding module. Any bits that are changed by writing to the SRCR1 register can
be read back correctly when reading the SRCR1 register. Software must use this register
to reset modules that are not present in the legacy registers. If software uses this register
to reset a legacy peripheral (such as UART0), the write causes proper operation, but
the value of that bit is not reflected in the SRCR1 register. If software uses both legacy
and peripheral-specific register accesses, the peripheral-specific registers must be
accessed by read-modify-write operations that affect only peripherals that are not present
in the legacy registers. In this manner, both the peripheral-specific and legacy registers
have coherent information.
Universal Asynchronous Receiver/Transmitter Software Reset (SRUART)
Base 0x400F.E000
Offset 0x518
Type RW, reset 0x0000.0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
8
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
7
6
5
4
3
2
1
0
R7
R6
R5
R4
R3
R2
R1
R0
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
Bit/Field
Name
Type
Reset
Description
31:8
reserved
RO
0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
7
R7
RW
0
UART Module 7 Software Reset
Value Description
0
UART module 7 is not reset.
1
UART module 7 is reset.
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Bit/Field
Name
Type
Reset
6
R6
RW
0
Description
UART Module 6 Software Reset
Value Description
5
R5
RW
0
0
UART module 6 is not reset.
1
UART module 6 is reset.
UART Module 5 Software Reset
Value Description
4
R4
RW
0
0
UART module 5 is not reset.
1
UART module 5 is reset.
UART Module 4 Software Reset
Value Description
3
R3
RW
0
0
UART module 4 is not reset.
1
UART module 4 is reset.
UART Module 3 Software Reset
Value Description
2
R2
RW
0
0
UART module 3 is not reset.
1
UART module 3 is reset.
UART Module 2 Software Reset
Value Description
1
R1
RW
0
0
UART module 2 is not reset.
1
UART module 2 is reset.
UART Module 1 Software Reset
Value Description
0
R0
RW
0
0
UART module 1 is not reset.
1
UART module 1 is reset.
UART Module 0 Software Reset
Value Description
0
UART module 0 is not reset.
1
UART module 0 is reset.
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Tiva™ TM4C1230C3PM Microcontroller
Register 46: Synchronous Serial Interface Software Reset (SRSSI), offset
0x51C
The SRSSI register provides software the capability to reset the available SSI modules. This register
provides the same capability as the legacy Software Reset Control n SRCRn registers specifically
for the SSI modules and has the same bit polarity as the corresponding SRCRn bits.
A peripheral is reset by software using a simple two-step process:
1. Software sets a bit (or bits) in the SRSSI register. While the SRSSI bit is 1, the peripheral is
held in reset.
2. Software completes the reset process by clearing the SRSSI bit.
There may be latency from the clearing of the SRSSI bit to when the peripheral is ready for use.
Software can check the corresponding PRSSI bit to be sure.
Important: This register should be used to reset the SSI modules. To support legacy software, the
SRCR1 register is available. Setting a bit in the SRCR1 register also resets the
corresponding module. Any bits that are changed by writing to the SRCR1 register can
be read back correctly when reading the SRCR1 register. Software must use this register
to reset modules that are not present in the legacy registers. If software uses this register
to reset a legacy peripheral (such as SSI0), the write causes proper operation, but the
value of that bit is not reflected in the SRCR1 register. If software uses both legacy and
peripheral-specific register accesses, the peripheral-specific registers must be accessed
by read-modify-write operations that affect only peripherals that are not present in the
legacy registers. In this manner, both the peripheral-specific and legacy registers have
coherent information.
Synchronous Serial Interface Software Reset (SRSSI)
Base 0x400F.E000
Offset 0x51C
Type RW, reset 0x0000.0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
RO
0
RO
0
RO
0
RO
0
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
8
7
6
5
4
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
3
2
1
0
R3
R2
R1
R0
RW
0
RW
0
RW
0
RW
0
Bit/Field
Name
Type
Reset
Description
31:4
reserved
RO
0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
3
R3
RW
0
SSI Module 3 Software Reset
Value Description
0
SSI module 3 is not reset.
1
SSI module 3 is reset.
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Bit/Field
Name
Type
Reset
2
R2
RW
0
Description
SSI Module 2 Software Reset
Value Description
1
R1
RW
0
0
SSI module 2 is not reset.
1
SSI module 2 is reset.
SSI Module 1 Software Reset
Value Description
0
R0
RW
0
0
SSI module 1 is not reset.
1
SSI module 1 is reset.
SSI Module 0 Software Reset
Value Description
0
SSI module 0 is not reset.
1
SSI module 0 is reset.
300
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Tiva™ TM4C1230C3PM Microcontroller
Register 47: Inter-Integrated Circuit Software Reset (SRI2C), offset 0x520
The SRI2C register provides software the capability to reset the available I2C modules. This register
provides the same capability as the legacy Software Reset Control n SRCRn registers specifically
for the I2C modules and has the same bit polarity as the corresponding SRCRn bits.
A peripheral is reset by software using a simple two-step process:
1. Software sets a bit (or bits) in the SRI2C register. While the SRI2C bit is 1, the peripheral is
held in reset.
2. Software completes the reset process by clearing the SRI2C bit.
There may be latency from the clearing of the SRI2C bit to when the peripheral is ready for use.
Software can check the corresponding PRI2C bit to be sure.
Important: This register should be used to reset the I2C modules. To support legacy software, the
SRCR1 register is available. Setting a bit in the SRCR1 register also resets the
corresponding module. Any bits that are changed by writing to the SRCR1 register can
be read back correctly when reading the SRCR1 register. Software must use this register
to reset modules that are not present in the legacy registers. If software uses this register
to reset a legacy peripheral (such as I2C0), the write causes proper operation, but the
value of that bit is not reflected in the SRCR1 register. If software uses both legacy and
peripheral-specific register accesses, the peripheral-specific registers must be accessed
by read-modify-write operations that affect only peripherals that are not present in the
legacy registers. In this manner, both the peripheral-specific and legacy registers have
coherent information.
Inter-Integrated Circuit Software Reset (SRI2C)
Base 0x400F.E000
Offset 0x520
Type RW, reset 0x0000.0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
8
7
6
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
5
4
3
2
1
0
R5
R4
R3
R2
R1
R0
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
Bit/Field
Name
Type
Reset
Description
31:6
reserved
RO
0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
5
R5
RW
0
I2C Module 5 Software Reset
Value Description
0
I2C module 5 is not reset.
1
I2C module 5 is reset.
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Bit/Field
Name
Type
Reset
4
R4
RW
0
Description
I2C Module 4 Software Reset
Value Description
3
R3
RW
0
0
I2C module 4 is not reset.
1
I2C module 4 is reset.
I2C Module 3 Software Reset
Value Description
2
R2
RW
0
0
I2C module 3 is not reset.
1
I2C module 3 is reset.
I2C Module 2 Software Reset
Value Description
1
R1
RW
0
0
I2C module 2 is not reset.
1
I2C module 2 is reset.
I2C Module 1 Software Reset
Value Description
0
R0
RW
0
0
I2C module 1 is not reset.
1
I2C module 1 is reset.
I2C Module 0 Software Reset
Value Description
0
I2C module 0 is not reset.
1
I2C module 0 is reset.
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Register 48: Controller Area Network Software Reset (SRCAN), offset 0x534
The SRCAN register provides software the capability to reset the available CAN modules. This
register provides the same capability as the legacy Software Reset Control n SRCRn registers
specifically for the CAN modules and has the same bit polarity as the corresponding SRCRn bits.
A peripheral is reset by software using a simple two-step process:
1. Software sets a bit (or bits) in the SRCAN register. While the SRCAN bit is 1, the peripheral is
held in reset.
2. Software completes the reset process by clearing the SRCAN bit.
There may be latency from the clearing of the SRCAN bit to when the peripheral is ready for use.
Software can check the corresponding PRCAN bit to be sure.
Important: This register should be used to reset the CAN modules. To support legacy software,
the SRCR0 register is available. Setting a bit in the SRCR0 register also resets the
corresponding module. Any bits that are changed by writing to the SRCR0 register can
be read back correctly when reading the SRCR0 register. If software uses this register
to reset a legacy peripheral (such as CAN0), the write causes proper operation, but the
value of that bit is not reflected in the SRCR0 register. If software uses both legacy and
peripheral-specific register accesses, the peripheral-specific registers must be accessed
by read-modify-write operations that affect only peripherals that are not present in the
legacy registers. In this manner, both the peripheral-specific and legacy registers have
coherent information.
Controller Area Network Software Reset (SRCAN)
Base 0x400F.E000
Offset 0x534
Type RW, reset 0x0000.0000
31
30
29
28
27
26
25
24
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
8
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
23
22
21
20
19
18
17
16
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
7
6
5
4
3
2
1
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RW
0
reserved
Type
Reset
reserved
Type
Reset
RO
0
R0
Bit/Field
Name
Type
Reset
Description
31:1
reserved
RO
0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0
R0
RW
0
CAN Module 0 Software Reset
Value Description
0
CAN module 0 is not reset.
1
CAN module 0 is reset.
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Register 49: Analog-to-Digital Converter Software Reset (SRADC), offset 0x538
The SRADC register provides software the capability to reset the available ADC modules. This
register provides the same capability as the legacy Software Reset Control n SRCRn registers
specifically for the ADC modules and has the same bit polarity as the corresponding SRCRn bits.
A peripheral is reset by software using a simple two-step process:
1. Software sets a bit (or bits) in the SRADC register. While the SRADC bit is 1, the peripheral is
held in reset.
2. Software completes the reset process by clearing the SRADC bit.
There may be latency from the clearing of the SRADC bit to when the peripheral is ready for use.
Software can check the corresponding PRADC bit to be sure.
Important: This register should be used to reset the ADC modules. To support legacy software,
the SRCR0 register is available. Setting a bit in the SRCR0 register also resets the
corresponding module. Any bits that are changed by writing to the SRCR0 register can
be read back correctly when reading the SRCR0 register. If software uses this register
to reset a legacy peripheral (such as ADC0), the write causes proper operation, but the
value of that bit is not reflected in the SRCR0 register. If software uses both legacy and
peripheral-specific register accesses, the peripheral-specific registers must be accessed
by read-modify-write operations that affect only peripherals that are not present in the
legacy registers. In this manner, both the peripheral-specific and legacy registers have
coherent information.
Analog-to-Digital Converter Software Reset (SRADC)
Base 0x400F.E000
Offset 0x538
Type RW, reset 0x0000.0000
31
30
29
28
27
26
25
24
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
23
22
21
20
19
18
17
16
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
8
7
6
5
4
3
2
1
0
R1
R0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RW
0
RW
0
reserved
Type
Reset
reserved
Type
Reset
Bit/Field
Name
Type
Reset
Description
31:2
reserved
RO
0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
1
R1
RW
0
ADC Module 1 Software Reset
Value Description
0
ADC module 1 is not reset.
1
ADC module 1 is reset.
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Bit/Field
Name
Type
Reset
0
R0
RW
0
Description
ADC Module 0 Software Reset
Value Description
0
ADC module 0 is not reset.
1
ADC module 0 is reset.
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Register 50: Analog Comparator Software Reset (SRACMP), offset 0x53C
The SRACMP register provides software the capability to reset the available analog comparator
module. This register provides the same capability as the legacy Software Reset Control n SRCRn
registers specifically for the analog comparator module and has the same bit polarity as the
corresponding SRCRn bits.
A block is reset by software using a simple two-step process:
1. Software sets a bit (or bits) in the SRACMP register. While the SRACMP bit is 1, the module
is held in reset.
2. Software completes the reset process by clearing the SRACMP bit.
There may be latency from the clearing of the SRACMP bit to when the module is ready for use.
Software can check the corresponding PRACMP bit to be sure.
Important: This register should be used to reset the analog comparator module. To support legacy
software, the SRCR1 register is available. Setting any of the COMPn bits in the SRCR0
register also resets the analog comparator module. If any of the COMPn bits are set by
writing to the SRCR1 register, it can be read back correctly when reading the SRCR0
register. If software uses this register to reset the analog comparator module, the write
causes proper operation, but the value of R0 is not reflected by the COMPn bits in the
SRCR1 register. If software uses both legacy and peripheral-specific register accesses,
the peripheral-specific registers must be accessed by read-modify-write operations that
affect only peripherals that are not present in the legacy registers. In this manner, both
the peripheral-specific and legacy registers have coherent information.
Analog Comparator Software Reset (SRACMP)
Base 0x400F.E000
Offset 0x53C
Type RW, reset 0x0000.0000
31
30
29
28
27
26
25
24
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
8
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
23
22
21
20
19
18
17
16
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
7
6
5
4
3
2
1
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RW
0
reserved
Type
Reset
reserved
Type
Reset
RO
0
R0
Bit/Field
Name
Type
Reset
Description
31:1
reserved
RO
0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0
R0
RW
0
Analog Comparator Module 0 Software Reset
Value Description
0
Analog comparator module is not reset.
1
Analog comparator module is reset.
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Register 51: EEPROM Software Reset (SREEPROM), offset 0x558
The SREEPROM register provides software the capability to reset the available EEPROM module.
A peripheral is reset by software using a simple two-step process:
1. Software sets a bit (or bits) in the SREEPROM register. While the SREEPROM bit is 1, the
peripheral is held in reset.
2. Software completes the reset process by clearing the SREEPROM bit.
There may be latency from the clearing of the SREEPROM bit to when the peripheral is ready for
use. Software can check the corresponding PREEPROM bit to be sure.
EEPROM Software Reset (SREEPROM)
Base 0x400F.E000
Offset 0x558
Type RW, reset 0x0000.0000
31
30
29
28
27
26
25
24
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
8
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
23
22
21
20
19
18
17
16
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
7
6
5
4
3
2
1
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RW
0
reserved
Type
Reset
reserved
Type
Reset
RO
0
R0
Bit/Field
Name
Type
Reset
Description
31:1
reserved
RO
0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0
R0
RW
0
EEPROM Module Software Reset
Value Description
0
EEPROM module is not reset.
1
EEPROM module is reset.
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Register 52: 32/64-Bit Wide General-Purpose Timer Software Reset
(SRWTIMER), offset 0x55C
The SRWTIMER register provides software the capability to reset the available 32/64-bit wide timer
modules.
A peripheral is reset by software using a simple two-step process:
1. Software sets a bit (or bits) in the SRWTIMER register. While the SRWTIMER bit is 1, the
peripheral is held in reset.
2. Software completes the reset process by clearing the SRWTIMER bit.
There may be latency from the clearing of the SRWTIMER bit to when the peripheral is ready for
use. Software can check the corresponding PRWTIMER bit to be sure.
32/64-Bit Wide General-Purpose Timer Software Reset (SRWTIMER)
Base 0x400F.E000
Offset 0x55C
Type RW, reset 0x0000.0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
8
7
6
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
5
4
3
2
1
0
R5
R4
R3
R2
R1
R0
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
Bit/Field
Name
Type
Reset
Description
31:6
reserved
RO
0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
5
R5
RW
0
32/64-Bit Wide General-Purpose Timer 5 Software Reset
Value Description
4
R4
RW
0
0
32/64-bit wide general-purpose timer module 5 is not reset.
1
32/64-bit wide general-purpose timer module 5 is reset.
32/64-Bit Wide General-Purpose Timer 4 Software Reset
Value Description
3
R3
RW
0
0
32/64-bit wide general-purpose timer module 4 is not reset.
1
32/64-bit wide general-purpose timer module 4 is reset.
32/64-Bit Wide General-Purpose Timer 3 Software Reset
Value Description
0
32/64-bit wide general-purpose timer module 3 is not reset.
1
32/64-bit wide general-purpose timer module 3 is reset.
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Bit/Field
Name
Type
Reset
2
R2
RW
0
Description
32/64-Bit Wide General-Purpose Timer 2 Software Reset
Value Description
1
R1
RW
0
0
32/64-bit wide general-purpose timer module 2 is not reset.
1
32/64-bit wide general-purpose timer module 2 is reset.
32/64-Bit Wide General-Purpose Timer 1 Software Reset
Value Description
0
R0
RW
0
0
32/64-bit wide general-purpose timer module 1 is not reset.
1
32/64-bit wide general-purpose timer module 1 is reset.
32/64-Bit Wide General-Purpose Timer 0 Software Reset
Value Description
0
32/64-bit wide general-purpose timer module 0 is not reset.
1
32/64-bit wide general-purpose timer module 0 is reset.
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Register 53: Watchdog Timer Run Mode Clock Gating Control (RCGCWD),
offset 0x600
The RCGCWD register provides software the capability to enable and disable watchdog modules
in Run mode. When enabled, a module is provided a clock and accesses to module registers are
allowed. When disabled, the clock is disabled to save power and accesses to module registers
generate a bus fault. This register provides the same capability as the legacy Run Mode Clock
Gating Control Register n RCGCn registers specifically for the watchdog modules and has the
same bit polarity as the corresponding RCGCn bits.
Important: This register should be used to control the clocking for the watchdog modules. To
support legacy software, the RCGC0 register is available. A write to the RCGC0 register
also writes the corresponding bit in this register. Any bits that are changed by writing
to the RCGC0 register can be read back correctly with a read of the RCGC0 register.
If software uses this register to write a legacy peripheral (such as Watchdog 0), the
write causes proper operation, but the value of that bit is not reflected in the RCGC0
register. If software uses both legacy and peripheral-specific register accesses, the
peripheral-specific registers must be accessed by read-modify-write operations that
affect only peripherals that are not present in the legacy registers. In this manner, both
the peripheral-specific and legacy registers have coherent information.
Watchdog Timer Run Mode Clock Gating Control (RCGCWD)
Base 0x400F.E000
Offset 0x600
Type RW, reset 0x0000.0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
RO
0
RO
0
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
1
0
R1
R0
RW
0
RW
0
Bit/Field
Name
Type
Reset
Description
31:2
reserved
RO
0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
1
R1
RW
0
Watchdog Timer 1 Run Mode Clock Gating Control
Value Description
0
R0
RW
0
0
Watchdog module 1 is disabled.
1
Enable and provide a clock to Watchdog module 1 in Run mode.
Watchdog Timer 0 Run Mode Clock Gating Control
Value Description
0
Watchdog module 0 is disabled.
1
Enable and provide a clock to Watchdog module 0 in Run mode.
310
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Register 54: 16/32-Bit General-Purpose Timer Run Mode Clock Gating Control
(RCGCTIMER), offset 0x604
The RCGCTIMER register provides software the capability to enable and disable 16/32-bit timer
modules in Run mode. When enabled, a module is provided a clock and accesses to module registers
are allowed. When disabled, the clock is disabled to save power and accesses to module registers
generate a bus fault. This register provides the same capability as the legacy Run Mode Clock
Gating Control Register n RCGCn registers specifically for the timer modules and has the same
bit polarity as the corresponding RCGCn bits.
Important: This register should be used to control the clocking for the timer modules. To support
legacy software, the RCGC1 register is available. A write to the RCGC1 register also
writes the corresponding bit in this register. Any bits that are changed by writing to the
RCGC1 register can be read back correctly with a read of the RCGC1 register. Software
must use this register to support modules that are not present in the legacy registers.
If software uses this register to write a legacy peripheral (such as Timer 0), the write
causes proper operation, but the value of that bit is not reflected in the RCGC1 register.
If software uses both legacy and peripheral-specific register accesses, the
peripheral-specific registers must be accessed by read-modify-write operations that
affect only peripherals that are not present in the legacy registers. In this manner, both
the peripheral-specific and legacy registers have coherent information.
16/32-Bit General-Purpose Timer Run Mode Clock Gating Control (RCGCTIMER)
Base 0x400F.E000
Offset 0x604
Type RW, reset 0x0000.0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
8
7
6
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
5
4
3
2
1
0
R5
R4
R3
R2
R1
R0
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
Bit/Field
Name
Type
Reset
Description
31:6
reserved
RO
0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
5
R5
RW
0
16/32-Bit General-Purpose Timer 5 Run Mode Clock Gating Control
Value Description
0
16/32-bit general-purpose timer module 5 is disabled.
1
Enable and provide a clock to 16/32-bit general-purpose timer
module 5 in Run mode.
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Bit/Field
Name
Type
Reset
4
R4
RW
0
Description
16/32-Bit General-Purpose Timer 4 Run Mode Clock Gating Control
Value Description
3
R3
RW
0
0
16/32-bit general-purpose timer module 4 is disabled.
1
Enable and provide a clock to 16/32-bit general-purpose timer
module 4 in Run mode.
16/32-Bit General-Purpose Timer 3 Run Mode Clock Gating Control
Value Description
2
R2
RW
0
0
16/32-bit general-purpose timer module 3 is disabled.
1
Enable and provide a clock to 16/32-bit general-purpose timer
module 3 in Run mode.
16/32-Bit General-Purpose Timer 2 Run Mode Clock Gating Control
Value Description
1
R1
RW
0
0
16/32-bit general-purpose timer module 2 is disabled.
1
Enable and provide a clock to 16/32-bit general-purpose timer
module 2 in Run mode.
16/32-Bit General-Purpose Timer 1 Run Mode Clock Gating Control
Value Description
0
R0
RW
0
0
16/32-bit general-purpose timer module 1 is disabled.
1
Enable and provide a clock to 16/32-bit general-purpose timer
module 1 in Run mode.
16/32-Bit General-Purpose Timer 0 Run Mode Clock Gating Control
Value Description
0
16/32-bit general-purpose timer module 0 is disabled.
1
Enable and provide a clock to 16/32-bit general-purpose timer
module 0 in Run mode.
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Register 55: General-Purpose Input/Output Run Mode Clock Gating Control
(RCGCGPIO), offset 0x608
The RCGCGPIO register provides software the capability to enable and disable GPIO modules in
Run mode. When enabled, a module is provided a clock and accesses to module registers are
allowed. When disabled, the clock is disabled to save power and accesses to module registers
generate a bus fault. This register provides the same capability as the legacy Run Mode Clock
Gating Control Register n RCGCn registers specifically for the watchdog modules and has the
same bit polarity as the corresponding RCGCn bits.
Important: This register should be used to control the clocking for the GPIO modules. To support
legacy software, the RCGC2 register is available. A write to the RCGC2 register also
writes the corresponding bit in this register. Any bits that are changed by writing to the
RCGC2 register can be read back correctly with a read of the RCGC2 register. Software
must use this register to support modules that are not present in the legacy registers.
If software uses this register to write a legacy peripheral (such as GPIO A), the write
causes proper operation, but the value of that bit is not reflected in the RCGC2 register.
If software uses both legacy and peripheral-specific register accesses, the
peripheral-specific registers must be accessed by read-modify-write operations that
affect only peripherals that are not present in the legacy registers. In this manner, both
the peripheral-specific and legacy registers have coherent information.
General-Purpose Input/Output Run Mode Clock Gating Control (RCGCGPIO)
Base 0x400F.E000
Offset 0x608
Type RW, reset 0x0000.0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
15
14
13
12
RO
0
RO
0
RO
0
RO
0
RO
0
11
10
9
8
7
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
6
5
4
3
2
1
0
R6
R5
R4
R3
R2
R1
R0
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
Bit/Field
Name
Type
Reset
Description
31:7
reserved
RO
0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
6
R6
RW
0
GPIO Port G Run Mode Clock Gating Control
Value Description
5
R5
RW
0
0
GPIO Port G is disabled.
1
Enable and provide a clock to GPIO Port G in Run mode.
GPIO Port F Run Mode Clock Gating Control
Value Description
0
GPIO Port F is disabled.
1
Enable and provide a clock to GPIO Port F in Run mode.
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Bit/Field
Name
Type
Reset
4
R4
RW
0
Description
GPIO Port E Run Mode Clock Gating Control
Value Description
3
R3
RW
0
0
GPIO Port E is disabled.
1
Enable and provide a clock to GPIO Port E in Run mode.
GPIO Port D Run Mode Clock Gating Control
Value Description
2
R2
RW
0
0
GPIO Port D is disabled.
1
Enable and provide a clock to GPIO Port D in Run mode.
GPIO Port C Run Mode Clock Gating Control
Value Description
1
R1
RW
0
0
GPIO Port C is disabled.
1
Enable and provide a clock to GPIO Port C in Run mode.
GPIO Port B Run Mode Clock Gating Control
Value Description
0
R0
RW
0
0
GPIO Port B is disabled.
1
Enable and provide a clock to GPIO Port B in Run mode.
GPIO Port A Run Mode Clock Gating Control
Value Description
0
GPIO Port A is disabled.
1
Enable and provide a clock to GPIO Port A in Run mode.
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Register 56: Micro Direct Memory Access Run Mode Clock Gating Control
(RCGCDMA), offset 0x60C
The RCGCDMA register provides software the capability to enable and disable the μDMA module
in Run mode. When enabled, the module is provided a clock and accesses to module registers are
allowed. When disabled, the clock is disabled to save power and accesses to module registers
generate a bus fault. This register provides the same capability as the legacy Run Mode Clock
Gating Control Register n RCGCn registers specifically for the watchdog modules and has the
same bit polarity as the corresponding RCGCn bits.
Important: This register should be used to control the clocking for the μDMA module. To support
legacy software, the RCGC2 register is available. A write to the UDMA bit in the RCGC2
register also writes the R0 bit in this register. If the UDMA bit is changed by writing to the
RCGC2 register, it can be read back correctly with a read of the RCGC2 register. If
software uses this register to control the clock for the μDMA module, the write causes
proper operation, but the UDMA bit in the RCGC2 register does not reflect the value of
the R0 bit. If software uses both legacy and peripheral-specific register accesses, the
peripheral-specific registers must be accessed by read-modify-write operations that
affect only peripherals that are not present in the legacy registers. In this manner, both
the peripheral-specific and legacy registers have coherent information.
Micro Direct Memory Access Run Mode Clock Gating Control (RCGCDMA)
Base 0x400F.E000
Offset 0x60C
Type RW, reset 0x0000.0000
31
30
29
28
27
26
25
24
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
8
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
23
22
21
20
19
18
17
16
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
7
6
5
4
3
2
1
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RW
0
reserved
Type
Reset
reserved
Type
Reset
RO
0
R0
Bit/Field
Name
Type
Reset
Description
31:1
reserved
RO
0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0
R0
RW
0
μDMA Module Run Mode Clock Gating Control
Value Description
0
μDMA module is disabled.
1
Enable and provide a clock to the μDMA module in Run mode.
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Register 57: Universal Asynchronous Receiver/Transmitter Run Mode Clock
Gating Control (RCGCUART), offset 0x618
The RCGCUART register provides software the capability to enable and disable the UART modules
in Run mode. When enabled, a module is provided a clock and accesses to module registers are
allowed. When disabled, the clock is disabled to save power and accesses to module registers
generate a bus fault. This register provides the same capability as the legacy Run Mode Clock
Gating Control Register n RCGCn registers specifically for the watchdog modules and has the
same bit polarity as the corresponding RCGCn bits.
Important: This register should be used to control the clocking for the UART modules. To support
legacy software, the RCGC1 register is available. A write to the RCGC1 register also
writes the corresponding bit in this register. Any bits that are changed by writing to the
RCGC1 register can be read back correctly with a read of the RCGC1 register. Software
must use this register to support modules that are not present in the legacy registers.
If software uses this register to write a legacy peripheral (such as UART0), the write
causes proper operation, but the value of that bit is not reflected in the RCGC1 register.
If software uses both legacy and peripheral-specific register accesses, the
peripheral-specific registers must be accessed by read-modify-write operations that
affect only peripherals that are not present in the legacy registers. In this manner, both
the peripheral-specific and legacy registers have coherent information.
Universal Asynchronous Receiver/Transmitter Run Mode Clock Gating Control (RCGCUART)
Base 0x400F.E000
Offset 0x618
Type RW, reset 0x0000.0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
8
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
7
6
5
4
3
2
1
0
R7
R6
R5
R4
R3
R2
R1
R0
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
Bit/Field
Name
Type
Reset
Description
31:8
reserved
RO
0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
7
R7
RW
0
UART Module 7 Run Mode Clock Gating Control
Value Description
6
R6
RW
0
0
UART module 7 is disabled.
1
Enable and provide a clock to UART module 7 in Run mode.
UART Module 6 Run Mode Clock Gating Control
Value Description
0
UART module 6 is disabled.
1
Enable and provide a clock to UART module 6 in Run mode.
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Bit/Field
Name
Type
Reset
5
R5
RW
0
Description
UART Module 5 Run Mode Clock Gating Control
Value Description
4
R4
RW
0
0
UART module 5 is disabled.
1
Enable and provide a clock to UART module 5 in Run mode.
UART Module 4 Run Mode Clock Gating Control
Value Description
3
R3
RW
0
0
UART module 4 is disabled.
1
Enable and provide a clock to UART module 4 in Run mode.
UART Module 3 Run Mode Clock Gating Control
Value Description
2
R2
RW
0
0
UART module 3 is disabled.
1
Enable and provide a clock to UART module 3 in Run mode.
UART Module 2 Run Mode Clock Gating Control
Value Description
1
R1
RW
0
0
UART module 2 is disabled.
1
Enable and provide a clock to UART module 2 in Run mode.
UART Module 1 Run Mode Clock Gating Control
Value Description
0
R0
RW
0
0
UART module 1 is disabled.
1
Enable and provide a clock to UART module 1 in Run mode.
UART Module 0 Run Mode Clock Gating Control
Value Description
0
UART module 0 is disabled.
1
Enable and provide a clock to UART module 0 in Run mode.
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Register 58: Synchronous Serial Interface Run Mode Clock Gating Control
(RCGCSSI), offset 0x61C
The RCGCSSI register provides software the capability to enable and disable the SSI modules in
Run mode. When enabled, a module is provided a clock and accesses to module registers are
allowed. When disabled, the clock is disabled to save power and accesses to module registers
generate a bus fault. This register provides the same capability as the legacy Run Mode Clock
Gating Control Register n RCGCn registers specifically for the watchdog modules and has the
same bit polarity as the corresponding RCGCn bits.
Important: This register should be used to control the clocking for the SSI modules. To support
legacy software, the RCGC1 register is available. A write to the RCGC1 register also
writes the corresponding bit in this register. Any bits that are changed by writing to the
RCGC1 register can be read back correctly with a read of the RCGC1 register. Software
must use this register to support modules that are not present in the legacy registers.
If software uses this register to write a legacy peripheral (such as SSI0), the write causes
proper operation, but the value of that bit is not reflected in the RCGC1 register. If
software uses both legacy and peripheral-specific register accesses, the
peripheral-specific registers must be accessed by read-modify-write operations that
affect only peripherals that are not present in the legacy registers. In this manner, both
the peripheral-specific and legacy registers have coherent information.
Synchronous Serial Interface Run Mode Clock Gating Control (RCGCSSI)
Base 0x400F.E000
Offset 0x61C
Type RW, reset 0x0000.0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
RO
0
RO
0
RO
0
RO
0
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
8
7
6
5
4
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
3
2
1
0
R3
R2
R1
R0
RW
0
RW
0
RW
0
RW
0
Bit/Field
Name
Type
Reset
Description
31:4
reserved
RO
0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
3
R3
RW
0
SSI Module 3 Run Mode Clock Gating Control
Value Description
2
R2
RW
0
0
SSI module 3 is disabled.
1
Enable and provide a clock to SSI module 3 in Run mode.
SSI Module 2 Run Mode Clock Gating Control
Value Description
0
SSI module 2 is disabled.
1
Enable and provide a clock to SSI module 2 in Run mode.
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Bit/Field
Name
Type
Reset
1
R1
RW
0
Description
SSI Module 1 Run Mode Clock Gating Control
Value Description
0
R0
RW
0
0
SSI module 1 is disabled.
1
Enable and provide a clock to SSI module 1 in Run mode.
SSI Module 0 Run Mode Clock Gating Control
Value Description
0
SSI module 0 is disabled.
1
Enable and provide a clock to SSI module 0 in Run mode.
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System Control
Register 59: Inter-Integrated Circuit Run Mode Clock Gating Control
(RCGCI2C), offset 0x620
The RCGCI2C register provides software the capability to enable and disable the I2C modules in
Run mode. When enabled, a module is provided a clock and accesses to module registers are
allowed. When disabled, the clock is disabled to save power and accesses to module registers
generate a bus fault. This register provides the same capability as the legacy Run Mode Clock
Gating Control Register n RCGCn registers specifically for the watchdog modules and has the
same bit polarity as the corresponding RCGCn bits.
Important: This register should be used to control the clocking for the I2C modules. To support
legacy software, the RCGC1 register is available. A write to the RCGC1 register also
writes the corresponding bit in this register. Any bits that are changed by writing to the
RCGC1 register can be read back correctly with a read of the RCGC1 register. Software
must use this register to support modules that are not present in the legacy registers.
If software uses this register to write a legacy peripheral (such as I2C0), the write causes
proper operation, but the value of that bit is not reflected in the RCGC1 register. If
software uses both legacy and peripheral-specific register accesses, the
peripheral-specific registers must be accessed by read-modify-write operations that
affect only peripherals that are not present in the legacy registers. In this manner, both
the peripheral-specific and legacy registers have coherent information.
Inter-Integrated Circuit Run Mode Clock Gating Control (RCGCI2C)
Base 0x400F.E000
Offset 0x620
Type RW, reset 0x0000.0000
31
30
29
28
27
26
25
24
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
23
22
21
20
19
18
17
16
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
8
7
6
5
4
3
2
1
0
R5
R4
R3
R2
R1
R0
RO
0
RO
0
RO
0
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
reserved
Type
Reset
reserved
Type
Reset
RO
0
Bit/Field
Name
Type
Reset
Description
31:6
reserved
RO
0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
5
R5
RW
0
I2C Module 5 Run Mode Clock Gating Control
Value Description
4
R4
RW
0
0
I2C module 5 is disabled.
1
Enable and provide a clock to I2C module 5 in Run mode.
I2C Module 4 Run Mode Clock Gating Control
Value Description
0
I2C module 4 is disabled.
1
Enable and provide a clock to I2C module 4 in Run mode.
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Bit/Field
Name
Type
Reset
3
R3
RW
0
Description
I2C Module 3 Run Mode Clock Gating Control
Value Description
2
R2
RW
0
0
I2C module 3 is disabled.
1
Enable and provide a clock to I2C module 3 in Run mode.
I2C Module 2 Run Mode Clock Gating Control
Value Description
1
R1
RW
0
0
I2C module 2 is disabled.
1
Enable and provide a clock to I2C module 2 in Run mode.
I2C Module 1 Run Mode Clock Gating Control
Value Description
0
R0
RW
0
0
I2C module 1 is disabled.
1
Enable and provide a clock to I2C module 1 in Run mode.
I2C Module 0 Run Mode Clock Gating Control
Value Description
0
I2C module 0 is disabled.
1
Enable and provide a clock to I2C module 0 in Run mode.
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Register 60: Controller Area Network Run Mode Clock Gating Control
(RCGCCAN), offset 0x634
The RCGCCAN register provides software the capability to enable and disable the CAN modules
in Run mode. When enabled, a module is provided a clock and accesses to module registers are
allowed. When disabled, the clock is disabled to save power and accesses to module registers
generate a bus fault. This register provides the same capability as the legacy Run Mode Clock
Gating Control Register n RCGCn registers specifically for the watchdog modules and has the
same bit polarity as the corresponding RCGCn bits.
Important: This register should be used to control the clocking for the CAN modules. To support
legacy software, the RCGC0 register is available. A write to the RCGC0 register also
writes the corresponding bit in this register. Any bits that are changed by writing to the
RCGC0 register can be read back correctly with a read of the RCGC0 register. If software
uses this register to write a legacy peripheral (such as CAN0), the write causes proper
operation, but the value of that bit is not reflected in the RCGC0 register. If software
uses both legacy and peripheral-specific register accesses, the peripheral-specific
registers must be accessed by read-modify-write operations that affect only peripherals
that are not present in the legacy registers. In this manner, both the peripheral-specific
and legacy registers have coherent information.
Controller Area Network Run Mode Clock Gating Control (RCGCCAN)
Base 0x400F.E000
Offset 0x634
Type RW, reset 0x0000.0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
RO
0
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
8
7
6
5
4
3
2
1
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
0
R0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RW
0
Bit/Field
Name
Type
Reset
Description
31:1
reserved
RO
0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0
R0
RW
0
CAN Module 0 Run Mode Clock Gating Control
Value Description
0
CAN module 0 is disabled.
1
Enable and provide a clock to CAN module 0 in Run mode.
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Register 61: Analog-to-Digital Converter Run Mode Clock Gating Control
(RCGCADC), offset 0x638
The RCGCADC register provides software the capability to enable and disable the ADC modules
in Run mode. When enabled, a module is provided a clock and accesses to module registers are
allowed. When disabled, the clock is disabled to save power and accesses to module registers
generate a bus fault. This register provides the same capability as the legacy Run Mode Clock
Gating Control Register n RCGCn registers specifically for the watchdog modules and has the
same bit polarity as the corresponding RCGCn bits.
Important: This register should be used to control the clocking for the ADC modules. To support
legacy software, the RCGC0 register is available. A write to the RCGC0 register also
writes the corresponding bit in this register. Any bits that are changed by writing to the
RCGC0 register can be read back correctly with a read of the RCGC0 register. If software
uses this register to write a legacy peripheral (such as ADC0), the write causes proper
operation, but the value of that bit is not reflected in the RCGC0 register. If software
uses both legacy and peripheral-specific register accesses, the peripheral-specific
registers must be accessed by read-modify-write operations that affect only peripherals
that are not present in the legacy registers. In this manner, both the peripheral-specific
and legacy registers have coherent information.
Analog-to-Digital Converter Run Mode Clock Gating Control (RCGCADC)
Base 0x400F.E000
Offset 0x638
Type RW, reset 0x0000.0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
RO
0
RO
0
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
1
0
R1
R0
RW
0
RW
0
Bit/Field
Name
Type
Reset
Description
31:2
reserved
RO
0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
1
R1
RW
0
ADC Module 1 Run Mode Clock Gating Control
Value Description
0
R0
RW
0
0
ADC module 1 is disabled.
1
Enable and provide a clock to ADC module 1 in Run mode.
ADC Module 0 Run Mode Clock Gating Control
Value Description
0
ADC module 0 is disabled.
1
Enable and provide a clock to ADC module 0 in Run mode.
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Register 62: Analog Comparator Run Mode Clock Gating Control
(RCGCACMP), offset 0x63C
The RCGCACMP register provides software the capability to enable and disable the analog
comparator module in Run mode. When enabled, the module is provided a clock and accesses to
module registers are allowed. When disabled, the clock is disabled to save power and accesses to
module registers generate a bus fault. This register provides the same capability as the legacy Run
Mode Clock Gating Control Register n RCGCn registers specifically for the watchdog modules
and has the same bit polarity as the corresponding RCGCn bits.
Important: This register should be used to control the clocking for the analog comparator module.
To support legacy software, the RCGC1 register is available. Setting any of the COMPn
bits in the RCGC1 register also sets the R0 bit in this register. If any of the COMPn bits
are set by writing to the RCGC1 register, it can be read back correctly when reading
the RCGC1 register. If software uses this register to change the clocking for the analog
comparator module, the write causes proper operation, but the value R0 is not reflected
by the COMPn bits in the RCGC1 register. If software uses both legacy and
peripheral-specific register accesses, the peripheral-specific registers must be accessed
by read-modify-write operations that affect only peripherals that are not present in the
legacy registers. In this manner, both the peripheral-specific and legacy registers have
coherent information.
Analog Comparator Run Mode Clock Gating Control (RCGCACMP)
Base 0x400F.E000
Offset 0x63C
Type RW, reset 0x0000.0000
31
30
29
28
27
26
25
24
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
8
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
23
22
21
20
19
18
17
16
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
7
6
5
4
3
2
1
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RW
0
reserved
Type
Reset
reserved
Type
Reset
RO
0
R0
Bit/Field
Name
Type
Reset
Description
31:1
reserved
RO
0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0
R0
RW
0
Analog Comparator Module 0 Run Mode Clock Gating Control
Value Description
0
Analog comparator module is disabled.
1
Enable and provide a clock to the analog comparator module
in Run mode.
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Register 63: EEPROM Run Mode Clock Gating Control (RCGCEEPROM), offset
0x658
The RCGCEEPROM register provides software the capability to enable and disable the EEPROM
module in Run mode. When enabled, the module is provided a clock and accesses to module
registers are allowed. When disabled, the clock is disabled to save power and accesses to module
registers generate a bus fault.
EEPROM Run Mode Clock Gating Control (RCGCEEPROM)
Base 0x400F.E000
Offset 0x658
Type RW, reset 0x0000.0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
RO
0
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
8
7
6
5
4
3
2
1
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
0
R0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RW
0
Bit/Field
Name
Type
Reset
Description
31:1
reserved
RO
0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0
R0
RW
0
EEPROM Module Run Mode Clock Gating Control
Value Description
0
EEPROM module is disabled.
1
Enable and provide a clock to the EEPROM module in Run
mode.
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System Control
Register 64: 32/64-Bit Wide General-Purpose Timer Run Mode Clock Gating
Control (RCGCWTIMER), offset 0x65C
The RCGCWTIMER register provides software the capability to enable and disable 3264-bit timer
modules in Run mode. When enabled, a module is provided a clock and accesses to module registers
are allowed. When disabled, the clock is disabled to save power and accesses to module registers
generate a bus fault. This register provides the same capability as the legacy Run Mode Clock
Gating Control Register n RCGCn registers specifically for the timer modules and has the same
bit polarity as the corresponding RCGCn bits.
32/64-Bit Wide General-Purpose Timer Run Mode Clock Gating Control (RCGCWTIMER)
Base 0x400F.E000
Offset 0x65C
Type RW, reset 0x0000.0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
8
7
6
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
5
4
3
2
1
0
R5
R4
R3
R2
R1
R0
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
Bit/Field
Name
Type
Reset
Description
31:6
reserved
RO
0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
5
R5
RW
0
32/64-Bit Wide General-Purpose Timer 5 Run Mode Clock Gating Control
Value Description
4
R4
RW
0
0
32/64-bit wide general-purpose timer module 5 is disabled.
1
Enable and provide a clock to 32/64-bit wide general-purpose
timer module 5 in Run mode.
32/64-Bit Wide General-Purpose Timer 4 Run Mode Clock Gating Control
Value Description
3
R3
RW
0
0
32/64-bit wide general-purpose timer module 4 is disabled.
1
Enable and provide a clock to 32/64-bit wide general-purpose
timer module 4 in Run mode.
32/64-Bit Wide General-Purpose Timer 3 Run Mode Clock Gating Control
Value Description
0
32/64-bit wide general-purpose timer module 3 is disabled.
1
Enable and provide a clock to 32/64-bit wide general-purpose
timer module 3 in Run mode.
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Bit/Field
Name
Type
Reset
2
R2
RW
0
Description
32/64-Bit Wide General-Purpose Timer 2 Run Mode Clock Gating Control
Value Description
1
R1
RW
0
0
32/64-bit wide general-purpose timer module 2 is disabled.
1
Enable and provide a clock to 32/64-bit wide general-purpose
timer module 2 in Run mode.
32/64-Bit Wide General-Purpose Timer 1 Run Mode Clock Gating Control
Value Description
0
R0
RW
0
0
32/64-bit wide general-purpose timer module 1 is disabled.
1
Enable and provide a clock to 32/64-bit wide general-purpose
timer module 1 in Run mode.
32/64-Bit Wide General-Purpose Timer 0 Run Mode Clock Gating Control
Value Description
0
32/64-bit wide general-purpose timer module 0 is disabled.
1
Enable and provide a clock to 32/64-bit wide general-purpose
timer module 0 in Run mode.
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System Control
Register 65: Watchdog Timer Sleep Mode Clock Gating Control (SCGCWD),
offset 0x700
The SCGCWD register provides software the capability to enable and disable watchdog modules
in sleep mode. When enabled, a module is provided a clock. When disabled, the clock is disabled
to save power. This register provides the same capability as the legacy Sleep Mode Clock Gating
Control Register n SCGCn registers specifically for the watchdog modules and has the same bit
polarity as the corresponding SCGCn bits.
Important: This register should be used to control the clocking for the watchdog modules. To
support legacy software, the SCGC0 register is available. A write to the SCGC0 register
also writes the corresponding bit in this register. Any bits that are changed by writing
to the SCGC0 register can be read back correctly with a read of the SCGC0 register.
If software uses this register to write a legacy peripheral (such as Watchdog 0), the
write causes proper operation, but the value of that bit is not reflected in the SCGC0
register. If software uses both legacy and peripheral-specific register accesses, the
peripheral-specific registers must be accessed by read-modify-write operations that
affect only peripherals that are not present in the legacy registers. In this manner, both
the peripheral-specific and legacy registers have coherent information.
Watchdog Timer Sleep Mode Clock Gating Control (SCGCWD)
Base 0x400F.E000
Offset 0x700
Type RW, reset 0x0000.0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
RO
0
RO
0
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
1
0
S1
S0
RW
0
RW
0
Bit/Field
Name
Type
Reset
Description
31:2
reserved
RO
0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
1
S1
RW
0
Watchdog Timer 1 Sleep Mode Clock Gating Control
Value Description
0
S0
RW
0
0
Watchdog module 1 is disabled.
1
Enable and provide a clock to Watchdog module 1 in sleep
mode.
Watchdog Timer 0 Sleep Mode Clock Gating Control
Value Description
0
Watchdog module 0 is disabled.
1
Enable and provide a clock to Watchdog module 0 in sleep
mode.
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Register 66: 16/32-Bit General-Purpose Timer Sleep Mode Clock Gating Control
(SCGCTIMER), offset 0x704
The SCGCTIMER register provides software the capability to enable and disable 16/32-bit timer
modules in sleep mode. When enabled, a module is provided a clock. When disabled, the clock is
disabled to save power. This register provides the same capability as the legacy Sleep Mode Clock
Gating Control Register n SCGCn registers specifically for the timer modules and has the same
bit polarity as the corresponding SCGCn bits.
Important: This register should be used to control the clocking for the timer modules. To support
legacy software, the SCGC1 register is available. A write to the SCGC1 register also
writes the corresponding bit in this register. Any bits that are changed by writing to the
SCGC1 register can be read back correctly with a read of the SCGC1 register. Software
must use this register to support modules that are not present in the legacy registers.
If software uses this register to write a legacy peripheral (such as Timer 0), the write
causes proper operation, but the value of that bit is not reflected in the SCGC1 register.
If software uses both legacy and peripheral-specific register accesses, the
peripheral-specific registers must be accessed by read-modify-write operations that
affect only peripherals that are not present in the legacy registers. In this manner, both
the peripheral-specific and legacy registers have coherent information.
16/32-Bit General-Purpose Timer Sleep Mode Clock Gating Control (SCGCTIMER)
Base 0x400F.E000
Offset 0x704
Type RW, reset 0x0000.0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
8
7
6
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
5
4
3
2
1
0
S5
S4
S3
S2
S1
S0
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
Bit/Field
Name
Type
Reset
Description
31:6
reserved
RO
0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
5
S5
RW
0
16/32-Bit General-Purpose Timer 5 Sleep Mode Clock Gating Control
Value Description
4
S4
RW
0
0
16/32-bit general-purpose timer module 5 is disabled.
1
Enable and provide a clock to 16/32-bit general-purpose timer
module 5 in sleep mode.
16/32-Bit General-Purpose Timer 4 Sleep Mode Clock Gating Control
Value Description
0
16/32-bit general-purpose timer module 4 is disabled.
1
Enable and provide a clock to 16/32-bit general-purpose timer
module 4 in sleep mode.
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Bit/Field
Name
Type
Reset
3
S3
RW
0
Description
16/32-Bit General-Purpose Timer 3 Sleep Mode Clock Gating Control
Value Description
2
S2
RW
0
0
16/32-bit general-purpose timer module 3 is disabled.
1
Enable and provide a clock to 16/32-bit general-purpose timer
module 3 in sleep mode.
16/32-Bit General-Purpose Timer 2 Sleep Mode Clock Gating Control
Value Description
1
S1
RW
0
0
16/32-bit general-purpose timer module 2 is disabled.
1
Enable and provide a clock to 16/32-bit general-purpose timer
module 2 in sleep mode.
16/32-Bit General-Purpose Timer 1 Sleep Mode Clock Gating Control
Value Description
0
S0
RW
0
0
16/32-bit general-purpose timer module 1 is disabled.
1
Enable and provide a clock to 16/32-bit general-purpose timer
module 1 in sleep mode.
16/32-Bit General-Purpose Timer 0 Sleep Mode Clock Gating Control
Value Description
0
16/32-bit general-purpose timer module 0 is disabled.
1
Enable and provide a clock to 16/32-bit general-purpose timer
module 0 in sleep mode.
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Register 67: General-Purpose Input/Output Sleep Mode Clock Gating Control
(SCGCGPIO), offset 0x708
The SCGCGPIO register provides software the capability to enable and disable GPIO modules in
sleep mode. When enabled, a module is provided a clock. When disabled, the clock is disabled to
save power. This register provides the same capability as the legacy Sleep Mode Clock Gating
Control Register n SCGCn registers specifically for the watchdog modules and has the same bit
polarity as the corresponding SCGCn bits.
Important: This register should be used to control the clocking for the GPIO modules. To support
legacy software, the SCGC2 register is available. A write to the SCGC2 register also
writes the corresponding bit in this register. Any bits that are changed by writing to the
SCGC2 register can be read back correctly with a read of the SCGC2 register. Software
must use this register to support modules that are not present in the legacy registers.
If software uses this register to write a legacy peripheral (such as GPIO A), the write
causes proper operation, but the value of that bit is not reflected in the SCGC2 register.
If software uses both legacy and peripheral-specific register accesses, the
peripheral-specific registers must be accessed by read-modify-write operations that
affect only peripherals that are not present in the legacy registers. In this manner, both
the peripheral-specific and legacy registers have coherent information.
General-Purpose Input/Output Sleep Mode Clock Gating Control (SCGCGPIO)
Base 0x400F.E000
Offset 0x708
Type RW, reset 0x0000.0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
15
14
13
12
RO
0
RO
0
RO
0
RO
0
RO
0
11
10
9
8
7
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
6
5
4
3
2
1
0
S6
S5
S4
S3
S2
S1
S0
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
Bit/Field
Name
Type
Reset
Description
31:7
reserved
RO
0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
6
S6
RW
0
GPIO Port G Sleep Mode Clock Gating Control
Value Description
5
S5
RW
0
0
GPIO Port G is disabled.
1
Enable and provide a clock to GPIO Port G in sleep mode.
GPIO Port F Sleep Mode Clock Gating Control
Value Description
0
GPIO Port F is disabled.
1
Enable and provide a clock to GPIO Port F in sleep mode.
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Bit/Field
Name
Type
Reset
4
S4
RW
0
Description
GPIO Port E Sleep Mode Clock Gating Control
Value Description
3
S3
RW
0
0
GPIO Port E is disabled.
1
Enable and provide a clock to GPIO Port E in sleep mode.
GPIO Port D Sleep Mode Clock Gating Control
Value Description
2
S2
RW
0
0
GPIO Port D is disabled.
1
Enable and provide a clock to GPIO Port D in sleep mode.
GPIO Port C Sleep Mode Clock Gating Control
Value Description
1
S1
RW
0
0
GPIO Port C is disabled.
1
Enable and provide a clock to GPIO Port C in sleep mode.
GPIO Port B Sleep Mode Clock Gating Control
Value Description
0
S0
RW
0
0
GPIO Port B is disabled.
1
Enable and provide a clock to GPIO Port B in sleep mode.
GPIO Port A Sleep Mode Clock Gating Control
Value Description
0
GPIO Port A is disabled.
1
Enable and provide a clock to GPIO Port A in sleep mode.
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Register 68: Micro Direct Memory Access Sleep Mode Clock Gating Control
(SCGCDMA), offset 0x70C
The SCGCDMA register provides software the capability to enable and disable the μDMA module
in sleep mode. When enabled, a module is provided a clock. When disabled, the clock is disabled
to save power. This register provides the same capability as the legacy Sleep Mode Clock Gating
Control Register n SCGCn registers specifically for the watchdog modules and has the same bit
polarity as the corresponding SCGCn bits.
Important: This register should be used to control the clocking for the μDMA module. To support
legacy software, the SCGC2 register is available. A write to the UDMA bit in the SCGC2
register also writes the S0 bit in this register. If the UDMA bit is changed by writing to the
SCGC2 register, it can be read back correctly with a read of the SCGC2 register. If
software uses this register to control the clock for the μDMA module, the write causes
proper operation, but the UDMA bit in the SCGC2 register does not reflect the value of
the S0 bit. If software uses both legacy and peripheral-specific register accesses, the
peripheral-specific registers must be accessed by read-modify-write operations that
affect only peripherals that are not present in the legacy registers. In this manner, both
the peripheral-specific and legacy registers have coherent information.
Micro Direct Memory Access Sleep Mode Clock Gating Control (SCGCDMA)
Base 0x400F.E000
Offset 0x70C
Type RW, reset 0x0000.0000
31
30
29
28
27
26
25
24
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
8
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
23
22
21
20
19
18
17
16
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
7
6
5
4
3
2
1
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RW
0
reserved
Type
Reset
reserved
Type
Reset
RO
0
S0
Bit/Field
Name
Type
Reset
Description
31:1
reserved
RO
0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0
S0
RW
0
μDMA Module Sleep Mode Clock Gating Control
Value Description
0
μDMA module is disabled.
1
Enable and provide a clock to the μDMA module in sleep mode.
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System Control
Register 69: Universal Asynchronous Receiver/Transmitter Sleep Mode Clock
Gating Control (SCGCUART), offset 0x718
The SCGCUART register provides software the capability to enable and disable the UART modules
in sleep mode. When enabled, a module is provided a clock. When disabled, the clock is disabled
to save power. This register provides the same capability as the legacy Sleep Mode Clock Gating
Control Register n SCGCn registers specifically for the watchdog modules and has the same bit
polarity as the corresponding SCGCn bits.
Important: This register should be used to control the clocking for the UART modules. To support
legacy software, the SCGC1 register is available. A write to the SCGC1 register also
writes the corresponding bit in this register. Any bits that are changed by writing to the
SCGC1 register can be read back correctly with a read of the SCGC1 register. Software
must use this register to support modules that are not present in the legacy registers.
If software uses this register to write a legacy peripheral (such as UART0), the write
causes proper operation, but the value of that bit is not reflected in the SCGC1 register.
If software uses both legacy and peripheral-specific register accesses, the
peripheral-specific registers must be accessed by read-modify-write operations that
affect only peripherals that are not present in the legacy registers. In this manner, both
the peripheral-specific and legacy registers have coherent information.
Universal Asynchronous Receiver/Transmitter Sleep Mode Clock Gating Control (SCGCUART)
Base 0x400F.E000
Offset 0x718
Type RW, reset 0x0000.0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
8
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
7
6
5
4
3
2
1
0
S7
S6
S5
S4
S3
S2
S1
S0
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
Bit/Field
Name
Type
Reset
Description
31:8
reserved
RO
0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
7
S7
RW
0
UART Module 7 Sleep Mode Clock Gating Control
Value Description
6
S6
RW
0
0
UART module 7 is disabled.
1
Enable and provide a clock to UART module 7 in sleep mode.
UART Module 6 Sleep Mode Clock Gating Control
Value Description
0
UART module 6 is disabled.
1
Enable and provide a clock to UART module 6 in sleep mode.
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Bit/Field
Name
Type
Reset
5
S5
RW
0
Description
UART Module 5 Sleep Mode Clock Gating Control
Value Description
4
S4
RW
0
0
UART module 5 is disabled.
1
Enable and provide a clock to UART module 5 in sleep mode.
UART Module 4 Sleep Mode Clock Gating Control
Value Description
3
S3
RW
0
0
UART module 4 is disabled.
1
Enable and provide a clock to UART module 4 in sleep mode.
UART Module 3 Sleep Mode Clock Gating Control
Value Description
2
S2
RW
0
0
UART module 3 is disabled.
1
Enable and provide a clock to UART module 3 in sleep mode.
UART Module 2 Sleep Mode Clock Gating Control
Value Description
1
S1
RW
0
0
UART module 2 is disabled.
1
Enable and provide a clock to UART module 2 in sleep mode.
UART Module 1 Sleep Mode Clock Gating Control
Value Description
0
S0
RW
0
0
UART module 1 is disabled.
1
Enable and provide a clock to UART module 1 in sleep mode.
UART Module 0 Sleep Mode Clock Gating Control
Value Description
0
UART module 0 is disabled.
1
Enable and provide a clock to UART module 0 in sleep mode.
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System Control
Register 70: Synchronous Serial Interface Sleep Mode Clock Gating Control
(SCGCSSI), offset 0x71C
The SCGCSSI register provides software the capability to enable and disable the SSI modules in
sleep mode. When enabled, a module is provided a clock. When disabled, the clock is disabled to
save power. This register provides the same capability as the legacy Sleep Mode Clock Gating
Control Register n SCGCn registers specifically for the watchdog modules and has the same bit
polarity as the corresponding SCGCn bits.
Important: This register should be used to control the clocking for the SSI modules. To support
legacy software, the SCGC1 register is available. A write to the SCGC1 register also
writes the corresponding bit in this register. Any bits that are changed by writing to the
SCGC1 register can be read back correctly with a read of the SCGC1 register. Software
must use this register to support modules that are not present in the legacy registers.
If software uses this register to write a legacy peripheral (such as SSI0), the write causes
proper operation, but the value of that bit is not reflected in the SCGC1 register. If
software uses both legacy and peripheral-specific register accesses, the
peripheral-specific registers must be accessed by read-modify-write operations that
affect only peripherals that are not present in the legacy registers. In this manner, both
the peripheral-specific and legacy registers have coherent information.
Synchronous Serial Interface Sleep Mode Clock Gating Control (SCGCSSI)
Base 0x400F.E000
Offset 0x71C
Type RW, reset 0x0000.0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
RO
0
RO
0
RO
0
RO
0
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
8
7
6
5
4
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
3
2
1
0
S3
S2
S1
S0
RW
0
RW
0
RW
0
RW
0
Bit/Field
Name
Type
Reset
Description
31:4
reserved
RO
0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
3
S3
RW
0
SSI Module 3 Sleep Mode Clock Gating Control
Value Description
2
S2
RW
0
0
SSI module 3 is disabled.
1
Enable and provide a clock to SSI module 3 in sleep mode.
SSI Module 2 Sleep Mode Clock Gating Control
Value Description
0
SSI module 2 is disabled.
1
Enable and provide a clock to SSI module 2 in sleep mode.
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Bit/Field
Name
Type
Reset
1
S1
RW
0
Description
SSI Module 1 Sleep Mode Clock Gating Control
Value Description
0
S0
RW
0
0
SSI module 1 is disabled.
1
Enable and provide a clock to SSI module 1 in sleep mode.
SSI Module 0 Sleep Mode Clock Gating Control
Value Description
0
SSI module 0 is disabled.
1
Enable and provide a clock to SSI module 0 in sleep mode.
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System Control
Register 71: Inter-Integrated Circuit Sleep Mode Clock Gating Control
(SCGCI2C), offset 0x720
The SCGCI2C register provides software the capability to enable and disable the I2C modules in
sleep mode. When enabled, a module is provided a clock. When disabled, the clock is disabled to
save power. This register provides the same capability as the legacy Sleep Mode Clock Gating
Control Register n SCGCn registers specifically for the watchdog modules and has the same bit
polarity as the corresponding SCGCn bits.
Important: This register should be used to control the clocking for the I2C modules. To support
legacy software, the SCGC1 register is available. A write to the SCGC1 register also
writes the corresponding bit in this register. Any bits that are changed by writing to the
SCGC1 register can be read back correctly with a read of the SCGC1 register. Software
must use this register to support modules that are not present in the legacy registers.
If software uses this register to write a legacy peripheral (such as I2C0), the write causes
proper operation, but the value of that bit is not reflected in the SCGC1 register. If
software uses both legacy and peripheral-specific register accesses, the
peripheral-specific registers must be accessed by read-modify-write operations that
affect only peripherals that are not present in the legacy registers. In this manner, both
the peripheral-specific and legacy registers have coherent information.
Inter-Integrated Circuit Sleep Mode Clock Gating Control (SCGCI2C)
Base 0x400F.E000
Offset 0x720
Type RW, reset 0x0000.0000
31
30
29
28
27
26
25
24
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
23
22
21
20
19
18
17
16
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
8
7
6
5
4
3
2
1
0
S5
S4
S3
S2
S1
S0
RO
0
RO
0
RO
0
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
reserved
Type
Reset
reserved
Type
Reset
RO
0
Bit/Field
Name
Type
Reset
Description
31:6
reserved
RO
0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
5
S5
RW
0
I2C Module 5 Sleep Mode Clock Gating Control
Value Description
4
S4
RW
0
0
I2C module 5 is disabled.
1
Enable and provide a clock to I2C module 5 in sleep mode.
I2C Module 4 Sleep Mode Clock Gating Control
Value Description
0
I2C module 4 is disabled.
1
Enable and provide a clock to I2C module 4 in sleep mode.
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Bit/Field
Name
Type
Reset
3
S3
RW
0
Description
I2C Module 3 Sleep Mode Clock Gating Control
Value Description
2
S2
RW
0
0
I2C module 3 is disabled.
1
Enable and provide a clock to I2C module 3 in sleep mode.
I2C Module 2 Sleep Mode Clock Gating Control
Value Description
1
S1
RW
0
0
I2C module 2 is disabled.
1
Enable and provide a clock to I2C module 2 in sleep mode.
I2C Module 1 Sleep Mode Clock Gating Control
Value Description
0
S0
RW
0
0
I2C module 1 is disabled.
1
Enable and provide a clock to I2C module 1 in sleep mode.
I2C Module 0 Sleep Mode Clock Gating Control
Value Description
0
I2C module 0 is disabled.
1
Enable and provide a clock to I2C module 0 in sleep mode.
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System Control
Register 72: Controller Area Network Sleep Mode Clock Gating Control
(SCGCCAN), offset 0x734
The SCGCCAN register provides software the capability to enable and disable the CAN modules
in sleep mode. When enabled, a module is provided a clock. When disabled, the clock is disabled
to save power. This register provides the same capability as the legacy Sleep Mode Clock Gating
Control Register n SCGCn registers specifically for the watchdog modules and has the same bit
polarity as the corresponding SCGCn bits.
Important: This register should be used to control the clocking for the CAN modules. To support
legacy software, the SCGC0 register is available. A write to the SCGC0 register also
writes the corresponding bit in this register. Any bits that are changed by writing to the
SCGC0 register can be read back correctly with a read of the SCGC0 register. If software
uses this register to write a legacy peripheral (such as CAN0), the write causes proper
operation, but the value of that bit is not reflected in the SCGC0 register. If software
uses both legacy and peripheral-specific register accesses, the peripheral-specific
registers must be accessed by read-modify-write operations that affect only peripherals
that are not present in the legacy registers. In this manner, both the peripheral-specific
and legacy registers have coherent information.
Controller Area Network Sleep Mode Clock Gating Control (SCGCCAN)
Base 0x400F.E000
Offset 0x734
Type RW, reset 0x0000.0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
RO
0
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
8
7
6
5
4
3
2
1
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
0
S0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RW
0
Bit/Field
Name
Type
Reset
Description
31:1
reserved
RO
0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0
S0
RW
0
CAN Module 0 Sleep Mode Clock Gating Control
Value Description
0
CAN module 0 is disabled.
1
Enable and provide a clock to CAN module 0 in sleep mode.
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Register 73: Analog-to-Digital Converter Sleep Mode Clock Gating Control
(SCGCADC), offset 0x738
The SCGCADC register provides software the capability to enable and disable the ADC modules
in sleep mode. When enabled, a module is provided a clock. When disabled, the clock is disabled
to save power. This register provides the same capability as the legacy Sleep Mode Clock Gating
Control Register n SCGCn registers specifically for the watchdog modules and has the same bit
polarity as the corresponding SCGCn bits.
Important: This register should be used to control the clocking for the ADC modules. To support
legacy software, the SCGC0 register is available. A write to the SCGC0 register also
writes the corresponding bit in this register. Any bits that are changed by writing to the
SCGC0 register can be read back correctly with a read of the SCGC0 register. If software
uses this register to write a legacy peripheral (such as ADC0), the write causes proper
operation, but the value of that bit is not reflected in the SCGC0 register. If software
uses both legacy and peripheral-specific register accesses, the peripheral-specific
registers must be accessed by read-modify-write operations that affect only peripherals
that are not present in the legacy registers. In this manner, both the peripheral-specific
and legacy registers have coherent information.
Analog-to-Digital Converter Sleep Mode Clock Gating Control (SCGCADC)
Base 0x400F.E000
Offset 0x738
Type RW, reset 0x0000.0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
RO
0
RO
0
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
1
0
S1
S0
RW
0
RW
0
Bit/Field
Name
Type
Reset
Description
31:2
reserved
RO
0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
1
S1
RW
0
ADC Module 1 Sleep Mode Clock Gating Control
Value Description
0
S0
RW
0
0
ADC module 1 is disabled.
1
Enable and provide a clock to ADC module 1 in sleep mode.
ADC Module 0 Sleep Mode Clock Gating Control
Value Description
0
ADC module 0 is disabled.
1
Enable and provide a clock to ADC module 0 in sleep mode.
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System Control
Register 74: Analog Comparator Sleep Mode Clock Gating Control
(SCGCACMP), offset 0x73C
The SCGCACMP register provides software the capability to enable and disable the analog
comparator module in sleep mode. When enabled, a module is provided a clock. When disabled,
the clock is disabled to save power. This register provides the same capability as the legacy Sleep
Mode Clock Gating Control Register n SCGCn registers specifically for the watchdog modules
and has the same bit polarity as the corresponding SCGCn bits.
Important: This register should be used to control the clocking for the analog comparator module.
To support legacy software, the SCGC1 register is available. Setting any of the COMPn
bits in the SCGC1 register also sets the S0 bit in this register. If any of the COMPn bits
are set by writing to the SCGC1 register, it can be read back correctly when reading
the SCGC1 register. If software uses this register to change the clocking for the analog
comparator module, the write causes proper operation, but the value S0 is not reflected
by the COMPn bits in the SCGC1 register. If software uses both legacy and
peripheral-specific register accesses, the peripheral-specific registers must be accessed
by read-modify-write operations that affect only peripherals that are not present in the
legacy registers. In this manner, both the peripheral-specific and legacy registers have
coherent information.
Analog Comparator Sleep Mode Clock Gating Control (SCGCACMP)
Base 0x400F.E000
Offset 0x73C
Type RW, reset 0x0000.0000
31
30
29
28
27
26
25
24
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
8
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
23
22
21
20
19
18
17
16
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
7
6
5
4
3
2
1
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RW
0
reserved
Type
Reset
reserved
Type
Reset
RO
0
S0
Bit/Field
Name
Type
Reset
Description
31:1
reserved
RO
0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0
S0
RW
0
Analog Comparator Module 0 Sleep Mode Clock Gating Control
Value Description
0
Analog comparator module is disabled.
1
Enable and provide a clock to the analog comparator module
in sleep mode.
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Tiva™ TM4C1230C3PM Microcontroller
Register 75: EEPROM Sleep Mode Clock Gating Control (SCGCEEPROM),
offset 0x758
The SCGCEEPROM register provides software the capability to enable and disable the EEPROM
module in sleep mode. When enabled, a module is provided a clock. When disabled, the clock is
disabled to save power.
EEPROM Sleep Mode Clock Gating Control (SCGCEEPROM)
Base 0x400F.E000
Offset 0x758
Type RW, reset 0x0000.0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
RO
0
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
8
7
6
5
4
3
2
1
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
0
S0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RW
0
Bit/Field
Name
Type
Reset
Description
31:1
reserved
RO
0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0
S0
RW
0
EEPROM Module Sleep Mode Clock Gating Control
Value Description
0
EEPROM module is disabled.
1
Enable and provide a clock to the EEPROM module in sleep
mode.
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System Control
Register 76: 32/64-Bit Wide General-Purpose Timer Sleep Mode Clock Gating
Control (SCGCWTIMER), offset 0x75C
The SCGCWTIMER register provides software the capability to enable and disable 3264-bit timer
modules in sleep mode. When enabled, a module is provided a clock. When disabled, the clock is
disabled to save power. This register provides the same capability as the legacy Sleep Mode Clock
Gating Control Register n SCGCn registers specifically for the timer modules and has the same
bit polarity as the corresponding SCGCn bits.
32/64-Bit Wide General-Purpose Timer Sleep Mode Clock Gating Control (SCGCWTIMER)
Base 0x400F.E000
Offset 0x75C
Type RW, reset 0x0000.0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
8
7
6
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
5
4
3
2
1
0
S5
S4
S3
S2
S1
S0
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
Bit/Field
Name
Type
Reset
Description
31:6
reserved
RO
0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
5
S5
RW
0
32/64-Bit Wide General-Purpose Timer 5 Sleep Mode Clock Gating
Control
Value Description
4
S4
RW
0
0
32/64-bit wide general-purpose timer module 5 is disabled.
1
Enable and provide a clock to 32/64-bit wide general-purpose
timer module 5 in sleep mode.
32/64-Bit Wide General-Purpose Timer 4 Sleep Mode Clock Gating
Control
Value Description
3
S3
RW
0
0
32/64-bit wide general-purpose timer module 4 is disabled.
1
Enable and provide a clock to 32/64-bit wide general-purpose
timer module 4 in sleep mode.
32/64-Bit Wide General-Purpose Timer 3 Sleep Mode Clock Gating
Control
Value Description
0
32/64-bit wide general-purpose timer module 3 is disabled.
1
Enable and provide a clock to 32/64-bit wide general-purpose
timer module 3 in sleep mode.
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Bit/Field
Name
Type
Reset
2
S2
RW
0
Description
32/64-Bit Wide General-Purpose Timer 2 Sleep Mode Clock Gating
Control
Value Description
1
S1
RW
0
0
32/64-bit wide general-purpose timer module 2 is disabled.
1
Enable and provide a clock to 32/64-bit wide general-purpose
timer module 2 in sleep mode.
32/64-Bit Wide General-Purpose Timer 1 Sleep Mode Clock Gating
Control
Value Description
0
S0
RW
0
0
32/64-bit wide general-purpose timer module 1 is disabled.
1
Enable and provide a clock to 32/64-bit wide general-purpose
timer module 1 in sleep mode.
32/64-Bit Wide General-Purpose Timer 0 Sleep Mode Clock Gating
Control
Value Description
0
32/64-bit wide general-purpose timer module 0 is disabled.
1
Enable and provide a clock to 32/64-bit wide general-purpose
timer module 0 in sleep mode.
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System Control
Register 77: Watchdog Timer Deep-Sleep Mode Clock Gating Control
(DCGCWD), offset 0x800
The DCGCWD register provides software the capability to enable and disable watchdog modules
in deep-sleep mode. When enabled, a module is provided a clock. When disabled, the clock is
disabled to save power. This register provides the same capability as the legacy Deep-Sleep Mode
Clock Gating Control Register n DCGCn registers specifically for the watchdog modules and has
the same bit polarity as the corresponding DCGCn bits.
Important: This register should be used to control the clocking for the watchdog modules. To
support legacy software, the DCGC0 register is available. A write to the DCGC0 register
also writes the corresponding bit in this register. Any bits that are changed by writing
to the DCGC0 register can be read back correctly with a read of the DCGC0 register.
If software uses this register to write a legacy peripheral (such as Watchdog 0), the
write causes proper operation, but the value of that bit is not reflected in the DCGC0
register. If software uses both legacy and peripheral-specific register accesses, the
peripheral-specific registers must be accessed by read-modify-write operations that
affect only peripherals that are not present in the legacy registers. In this manner, both
the peripheral-specific and legacy registers have coherent information.
Watchdog Timer Deep-Sleep Mode Clock Gating Control (DCGCWD)
Base 0x400F.E000
Offset 0x800
Type RW, reset 0x0000.0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
RO
0
RO
0
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
1
0
D1
D0
RW
0
RW
0
Bit/Field
Name
Type
Reset
Description
31:2
reserved
RO
0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
1
D1
RW
0
Watchdog Timer 1 Deep-Sleep Mode Clock Gating Control
Value Description
0
D0
RW
0
0
Watchdog module 1 is disabled.
1
Enable and provide a clock to Watchdog module 1 in deep-sleep
mode.
Watchdog Timer 0 Deep-Sleep Mode Clock Gating Control
Value Description
0
Watchdog module 0 is disabled.
1
Enable and provide a clock to Watchdog module 0 in deep-sleep
mode.
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Tiva™ TM4C1230C3PM Microcontroller
Register 78: 16/32-Bit General-Purpose Timer Deep-Sleep Mode Clock Gating
Control (DCGCTIMER), offset 0x804
The DCGCTIMER register provides software the capability to enable and disable 16/32-bit timer
modules in deep-sleep mode. When enabled, a module is provided a clock. When disabled, the
clock is disabled to save power. This register provides the same capability as the legacy Deep-Sleep
Mode Clock Gating Control Register n DCGCn registers specifically for the timer modules and
has the same bit polarity as the corresponding DCGCn bits.
Important: This register should be used to control the clocking for the timer modules. To support
legacy software, the DCGC1 register is available. A write to the DCGC1 register also
writes the corresponding bit in this register. Any bits that are changed by writing to the
DCGC1 register can be read back correctly with a read of the DCGC1 register. Software
must use this register to support modules that are not present in the legacy registers.
If software uses this register to write a legacy peripheral (such as Timer 0), the write
causes proper operation, but the value of that bit is not reflected in the DCGC1 register.
If software uses both legacy and peripheral-specific register accesses, the
peripheral-specific registers must be accessed by read-modify-write operations that
affect only peripherals that are not present in the legacy registers. In this manner, both
the peripheral-specific and legacy registers have coherent information.
16/32-Bit General-Purpose Timer Deep-Sleep Mode Clock Gating Control (DCGCTIMER)
Base 0x400F.E000
Offset 0x804
Type RW, reset 0x0000.0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
8
7
6
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
5
4
3
2
1
0
D5
D4
D3
D2
D1
D0
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
Bit/Field
Name
Type
Reset
Description
31:6
reserved
RO
0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
5
D5
RW
0
16/32-Bit General-Purpose Timer 5 Deep-Sleep Mode Clock Gating
Control
Value Description
0
16/32-bit general-purpose timer module 5 is disabled.
1
Enable and provide a clock to 16/32-bit general-purpose timer
module 5 in deep-sleep mode.
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System Control
Bit/Field
Name
Type
Reset
4
D4
RW
0
Description
16/32-Bit General-Purpose Timer 4 Deep-Sleep Mode Clock Gating
Control
Value Description
3
D3
RW
0
0
16/32-bit general-purpose timer module 4 is disabled.
1
Enable and provide a clock to 16/32-bit general-purpose timer
module 4 in deep-sleep mode.
16/32-Bit General-Purpose Timer 3 Deep-Sleep Mode Clock Gating
Control
Value Description
2
D2
RW
0
0
16/32-bit general-purpose timer module 3 is disabled.
1
Enable and provide a clock to 16/32-bit general-purpose timer
module 3 in deep-sleep mode.
16/32-Bit General-Purpose Timer 2 Deep-Sleep Mode Clock Gating
Control
Value Description
1
D1
RW
0
0
16/32-bit general-purpose timer module 2 is disabled.
1
Enable and provide a clock to 16/32-bit general-purpose timer
module 2 in deep-sleep mode.
16/32-Bit General-Purpose Timer 1 Deep-Sleep Mode Clock Gating
Control
Value Description
0
D0
RW
0
0
16/32-bit general-purpose timer module 1 is disabled.
1
Enable and provide a clock to 16/32-bit general-purpose timer
module 1 in deep-sleep mode.
16/32-Bit General-Purpose Timer 0 Deep-Sleep Mode Clock Gating
Control
Value Description
0
16/32-bit general-purpose timer module 0 is disabled.
1
Enable and provide a clock to 16/32-bit general-purpose timer
module 0 in deep-sleep mode.
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Tiva™ TM4C1230C3PM Microcontroller
Register 79: General-Purpose Input/Output Deep-Sleep Mode Clock Gating
Control (DCGCGPIO), offset 0x808
The DCGCGPIO register provides software the capability to enable and disable GPIO modules in
deep-sleep mode. When enabled, a module is provided a clock. When disabled, the clock is disabled
to save power. This register provides the same capability as the legacy Deep-Sleep Mode Clock
Gating Control Register n DCGCn registers specifically for the watchdog modules and has the
same bit polarity as the corresponding DCGCn bits.
Important: This register should be used to control the clocking for the GPIO modules. To support
legacy software, the DCGC2 register is available. A write to the DCGC2 register also
writes the corresponding bit in this register. Any bits that are changed by writing to the
DCGC2 register can be read back correctly with a read of the DCGC2 register. Software
must use this register to support modules that are not present in the legacy registers.
If software uses this register to write a legacy peripheral (such as GPIO A), the write
causes proper operation, but the value of that bit is not reflected in the DCGC2 register.
If software uses both legacy and peripheral-specific register accesses, the
peripheral-specific registers must be accessed by read-modify-write operations that
affect only peripherals that are not present in the legacy registers. In this manner, both
the peripheral-specific and legacy registers have coherent information.
General-Purpose Input/Output Deep-Sleep Mode Clock Gating Control (DCGCGPIO)
Base 0x400F.E000
Offset 0x808
Type RW, reset 0x0000.0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
15
14
13
12
RO
0
RO
0
RO
0
RO
0
RO
0
11
10
9
8
7
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
6
5
4
3
2
1
0
D6
D5
D4
D3
D2
D1
D0
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
Bit/Field
Name
Type
Reset
Description
31:7
reserved
RO
0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
6
D6
RW
0
GPIO Port G Deep-Sleep Mode Clock Gating Control
Value Description
5
D5
RW
0
0
GPIO Port G is disabled.
1
Enable and provide a clock to GPIO Port G in deep-sleep mode.
GPIO Port F Deep-Sleep Mode Clock Gating Control
Value Description
0
GPIO Port F is disabled.
1
Enable and provide a clock to GPIO Port F in deep-sleep mode.
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System Control
Bit/Field
Name
Type
Reset
4
D4
RW
0
Description
GPIO Port E Deep-Sleep Mode Clock Gating Control
Value Description
3
D3
RW
0
0
GPIO Port E is disabled.
1
Enable and provide a clock to GPIO Port E in deep-sleep mode.
GPIO Port D Deep-Sleep Mode Clock Gating Control
Value Description
2
D2
RW
0
0
GPIO Port D is disabled.
1
Enable and provide a clock to GPIO Port D in deep-sleep mode.
GPIO Port C Deep-Sleep Mode Clock Gating Control
Value Description
1
D1
RW
0
0
GPIO Port C is disabled.
1
Enable and provide a clock to GPIO Port C in deep-sleep mode.
GPIO Port B Deep-Sleep Mode Clock Gating Control
Value Description
0
D0
RW
0
0
GPIO Port B is disabled.
1
Enable and provide a clock to GPIO Port B in deep-sleep mode.
GPIO Port A Deep-Sleep Mode Clock Gating Control
Value Description
0
GPIO Port A is disabled.
1
Enable and provide a clock to GPIO Port A in deep-sleep mode.
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Tiva™ TM4C1230C3PM Microcontroller
Register 80: Micro Direct Memory Access Deep-Sleep Mode Clock Gating
Control (DCGCDMA), offset 0x80C
The DCGCDMA register provides software the capability to enable and disable the μDMA module
in deep-sleep mode. When enabled, a module is provided a clock. When disabled, the clock is
disabled to save power. This register provides the same capability as the legacy Deep-Sleep Mode
Clock Gating Control Register n DCGCn registers specifically for the watchdog modules and has
the same bit polarity as the corresponding DCGCn bits.
Important: This register should be used to control the clocking for the μDMA module. To support
legacy software, the DCGC2 register is available. A write to the UDMA bit in the DCGC2
register also writes the D0 bit in this register. If the UDMA bit is changed by writing to the
DCGC2 register, it can be read back correctly with a read of the DCGC2 register. If
software uses this register to control the clock for the μDMA module, the write causes
proper operation, but the UDMA bit in the DCGC2 register does not reflect the value of
the D0 bit. If software uses both legacy and peripheral-specific register accesses, the
peripheral-specific registers must be accessed by read-modify-write operations that
affect only peripherals that are not present in the legacy registers. In this manner, both
the peripheral-specific and legacy registers have coherent information.
Micro Direct Memory Access Deep-Sleep Mode Clock Gating Control (DCGCDMA)
Base 0x400F.E000
Offset 0x80C
Type RW, reset 0x0000.0000
31
30
29
28
27
26
25
24
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
8
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
23
22
21
20
19
18
17
16
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
7
6
5
4
3
2
1
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RW
0
reserved
Type
Reset
reserved
Type
Reset
RO
0
D0
Bit/Field
Name
Type
Reset
Description
31:1
reserved
RO
0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0
D0
RW
0
μDMA Module Deep-Sleep Mode Clock Gating Control
Value Description
0
μDMA module is disabled.
1
Enable and provide a clock to the μDMA module in deep-sleep
mode.
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System Control
Register 81: Universal Asynchronous Receiver/Transmitter Deep-Sleep Mode
Clock Gating Control (DCGCUART), offset 0x818
The DCGCUART register provides software the capability to enable and disable the UART modules
in deep-sleep mode. When enabled, a module is provided a clock. When disabled, the clock is
disabled to save power. This register provides the same capability as the legacy Deep-Sleep Mode
Clock Gating Control Register n DCGCn registers specifically for the watchdog modules and has
the same bit polarity as the corresponding DCGCn bits.
Important: This register should be used to control the clocking for the UART modules. To support
legacy software, the DCGC1 register is available. A write to the DCGC1 register also
writes the corresponding bit in this register. Any bits that are changed by writing to the
DCGC1 register can be read back correctly with a read of the DCGC1 register. Software
must use this register to support modules that are not present in the legacy registers.
If software uses this register to write a legacy peripheral (such as UART0), the write
causes proper operation, but the value of that bit is not reflected in the DCGC1 register.
If software uses both legacy and peripheral-specific register accesses, the
peripheral-specific registers must be accessed by read-modify-write operations that
affect only peripherals that are not present in the legacy registers. In this manner, both
the peripheral-specific and legacy registers have coherent information.
Universal Asynchronous Receiver/Transmitter Deep-Sleep Mode Clock Gating Control (DCGCUART)
Base 0x400F.E000
Offset 0x818
Type RW, reset 0x0000.0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
8
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
7
6
5
4
3
2
1
0
D7
D6
D5
D4
D3
D2
D1
D0
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
Bit/Field
Name
Type
Reset
Description
31:8
reserved
RO
0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
7
D7
RW
0
UART Module 7 Deep-Sleep Mode Clock Gating Control
Value Description
6
D6
RW
0
0
UART module 7 is disabled.
1
Enable and provide a clock to UART module 7 in deep-sleep
mode.
UART Module 6 Deep-Sleep Mode Clock Gating Control
Value Description
0
UART module 6 is disabled.
1
Enable and provide a clock to UART module 6 in deep-sleep
mode.
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Bit/Field
Name
Type
Reset
5
D5
RW
0
Description
UART Module 5 Deep-Sleep Mode Clock Gating Control
Value Description
4
D4
RW
0
0
UART module 5 is disabled.
1
Enable and provide a clock to UART module 5 in deep-sleep
mode.
UART Module 4 Deep-Sleep Mode Clock Gating Control
Value Description
3
D3
RW
0
0
UART module 4 is disabled.
1
Enable and provide a clock to UART module 4 in deep-sleep
mode.
UART Module 3 Deep-Sleep Mode Clock Gating Control
Value Description
2
D2
RW
0
0
UART module 3 is disabled.
1
Enable and provide a clock to UART module 3 in deep-sleep
mode.
UART Module 2 Deep-Sleep Mode Clock Gating Control
Value Description
1
D1
RW
0
0
UART module 2 is disabled.
1
Enable and provide a clock to UART module 2 in deep-sleep
mode.
UART Module 1 Deep-Sleep Mode Clock Gating Control
Value Description
0
D0
RW
0
0
UART module 1 is disabled.
1
Enable and provide a clock to UART module 1 in deep-sleep
mode.
UART Module 0 Deep-Sleep Mode Clock Gating Control
Value Description
0
UART module 0 is disabled.
1
Enable and provide a clock to UART module 0 in deep-sleep
mode.
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System Control
Register 82: Synchronous Serial Interface Deep-Sleep Mode Clock Gating
Control (DCGCSSI), offset 0x81C
The DCGCSSI register provides software the capability to enable and disable the SSI modules in
deep-sleep mode. When enabled, a module is provided a clock. When disabled, the clock is disabled
to save power. This register provides the same capability as the legacy Deep-Sleep Mode Clock
Gating Control Register n DCGCn registers specifically for the watchdog modules and has the
same bit polarity as the corresponding DCGCn bits.
Important: This register should be used to control the clocking for the SSI modules. To support
legacy software, the DCGC1 register is available. A write to the DCGC1 register also
writes the corresponding bit in this register. Any bits that are changed by writing to the
DCGC1 register can be read back correctly with a read of the DCGC1 register. Software
must use this register to support modules that are not present in the legacy registers.
If software uses this register to write a legacy peripheral (such as SSI0), the write causes
proper operation, but the value of that bit is not reflected in the DCGC1 register. If
software uses both legacy and peripheral-specific register accesses, the
peripheral-specific registers must be accessed by read-modify-write operations that
affect only peripherals that are not present in the legacy registers. In this manner, both
the peripheral-specific and legacy registers have coherent information.
Synchronous Serial Interface Deep-Sleep Mode Clock Gating Control (DCGCSSI)
Base 0x400F.E000
Offset 0x81C
Type RW, reset 0x0000.0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
RO
0
RO
0
RO
0
RO
0
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
8
7
6
5
4
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
3
2
1
0
D3
D2
D1
D0
RW
0
RW
0
RW
0
RW
0
Bit/Field
Name
Type
Reset
Description
31:4
reserved
RO
0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
3
D3
RW
0
SSI Module 3 Deep-Sleep Mode Clock Gating Control
Value Description
2
D2
RW
0
0
SSI module 3 is disabled.
1
Enable and provide a clock to SSI module 3 in deep-sleep mode.
SSI Module 2 Deep-Sleep Mode Clock Gating Control
Value Description
0
SSI module 2 is disabled.
1
Enable and provide a clock to SSI module 2 in deep-sleep mode.
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Bit/Field
Name
Type
Reset
1
D1
RW
0
Description
SSI Module 1 Deep-Sleep Mode Clock Gating Control
Value Description
0
D0
RW
0
0
SSI module 1 is disabled.
1
Enable and provide a clock to SSI module 1 in deep-sleep mode.
SSI Module 0 Deep-Sleep Mode Clock Gating Control
Value Description
0
SSI module 0 is disabled.
1
Enable and provide a clock to SSI module 0 in deep-sleep mode.
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System Control
Register 83: Inter-Integrated Circuit Deep-Sleep Mode Clock Gating Control
(DCGCI2C), offset 0x820
The DCGCI2C register provides software the capability to enable and disable the I2C modules in
deep-sleep mode. When enabled, a module is provided a clock. When disabled, the clock is disabled
to save power. This register provides the same capability as the legacy Deep-Sleep Mode Clock
Gating Control Register n DCGCn registers specifically for the watchdog modules and has the
same bit polarity as the corresponding DCGCn bits.
Important: This register should be used to control the clocking for the I2C modules. To support
legacy software, the DCGC1 register is available. A write to the DCGC1 register also
writes the corresponding bit in this register. Any bits that are changed by writing to the
DCGC1 register can be read back correctly with a read of the DCGC1 register. Software
must use this register to support modules that are not present in the legacy registers.
If software uses this register to write a legacy peripheral (such as I2C0), the write causes
proper operation, but the value of that bit is not reflected in the DCGC1 register. If
software uses both legacy and peripheral-specific register accesses, the
peripheral-specific registers must be accessed by read-modify-write operations that
affect only peripherals that are not present in the legacy registers. In this manner, both
the peripheral-specific and legacy registers have coherent information.
Inter-Integrated Circuit Deep-Sleep Mode Clock Gating Control (DCGCI2C)
Base 0x400F.E000
Offset 0x820
Type RW, reset 0x0000.0000
31
30
29
28
27
26
25
24
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
23
22
21
20
19
18
17
16
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
8
7
6
5
4
3
2
1
0
D5
D4
D3
D2
D1
D0
RO
0
RO
0
RO
0
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
reserved
Type
Reset
reserved
Type
Reset
RO
0
Bit/Field
Name
Type
Reset
Description
31:6
reserved
RO
0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
5
D5
RW
0
I2C Module 5 Deep-Sleep Mode Clock Gating Control
Value Description
4
D4
RW
0
0
I2C module 5 is disabled.
1
Enable and provide a clock to I2C module 5 in deep-sleep mode.
I2C Module 4 Deep-Sleep Mode Clock Gating Control
Value Description
0
I2C module 4 is disabled.
1
Enable and provide a clock to I2C module 4 in deep-sleep mode.
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Bit/Field
Name
Type
Reset
3
D3
RW
0
Description
I2C Module 3 Deep-Sleep Mode Clock Gating Control
Value Description
2
D2
RW
0
0
I2C module 3 is disabled.
1
Enable and provide a clock to I2C module 3 in deep-sleep mode.
I2C Module 2 Deep-Sleep Mode Clock Gating Control
Value Description
1
D1
RW
0
0
I2C module 2 is disabled.
1
Enable and provide a clock to I2C module 2 in deep-sleep mode.
I2C Module 1 Deep-Sleep Mode Clock Gating Control
Value Description
0
D0
RW
0
0
I2C module 1 is disabled.
1
Enable and provide a clock to I2C module 1 in deep-sleep mode.
I2C Module 0 Deep-Sleep Mode Clock Gating Control
Value Description
0
I2C module 0 is disabled.
1
Enable and provide a clock to I2C module 0 in deep-sleep mode.
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System Control
Register 84: Controller Area Network Deep-Sleep Mode Clock Gating Control
(DCGCCAN), offset 0x834
The DCGCCAN register provides software the capability to enable and disable the CAN modules
in deep-sleep mode. When enabled, a module is provided a clock. When disabled, the clock is
disabled to save power. This register provides the same capability as the legacy Deep-Sleep Mode
Clock Gating Control Register n DCGCn registers specifically for the watchdog modules and has
the same bit polarity as the corresponding DCGCn bits.
Important: This register should be used to control the clocking for the CAN modules. To support
legacy software, the DCGC0 register is available. A write to the DCGC0 register also
writes the corresponding bit in this register. Any bits that are changed by writing to the
DCGC0 register can be read back correctly with a read of the DCGC0 register. If software
uses this register to write a legacy peripheral (such as CAN0), the write causes proper
operation, but the value of that bit is not reflected in the DCGC0 register. If software
uses both legacy and peripheral-specific register accesses, the peripheral-specific
registers must be accessed by read-modify-write operations that affect only peripherals
that are not present in the legacy registers. In this manner, both the peripheral-specific
and legacy registers have coherent information.
Controller Area Network Deep-Sleep Mode Clock Gating Control (DCGCCAN)
Base 0x400F.E000
Offset 0x834
Type RW, reset 0x0000.0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
RO
0
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
8
7
6
5
4
3
2
1
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
0
D0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RW
0
Bit/Field
Name
Type
Reset
Description
31:1
reserved
RO
0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0
D0
RW
0
CAN Module 0 Deep-Sleep Mode Clock Gating Control
Value Description
0
CAN module 0 is disabled.
1
Enable and provide a clock to CAN module 0 in deep-sleep
mode.
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Tiva™ TM4C1230C3PM Microcontroller
Register 85: Analog-to-Digital Converter Deep-Sleep Mode Clock Gating
Control (DCGCADC), offset 0x838
The DCGCADC register provides software the capability to enable and disable the ADC modules
in deep-sleep mode. When enabled, a module is provided a clock. When disabled, the clock is
disabled to save power. This register provides the same capability as the legacy Deep-Sleep Mode
Clock Gating Control Register n DCGCn registers specifically for the watchdog modules and has
the same bit polarity as the corresponding DCGCn bits.
Important: This register should be used to control the clocking for the ADC modules. To support
legacy software, the DCGC0 register is available. A write to the DCGC0 register also
writes the corresponding bit in this register. Any bits that are changed by writing to the
DCGC0 register can be read back correctly with a read of the DCGC0 register. If software
uses this register to write a legacy peripheral (such as ADC0), the write causes proper
operation, but the value of that bit is not reflected in the DCGC0 register. If software
uses both legacy and peripheral-specific register accesses, the peripheral-specific
registers must be accessed by read-modify-write operations that affect only peripherals
that are not present in the legacy registers. In this manner, both the peripheral-specific
and legacy registers have coherent information.
Analog-to-Digital Converter Deep-Sleep Mode Clock Gating Control (DCGCADC)
Base 0x400F.E000
Offset 0x838
Type RW, reset 0x0000.0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
RO
0
RO
0
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
1
0
D1
D0
RW
0
RW
0
Bit/Field
Name
Type
Reset
Description
31:2
reserved
RO
0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
1
D1
RW
0
ADC Module 1 Deep-Sleep Mode Clock Gating Control
Value Description
0
D0
RW
0
0
ADC module 1 is disabled.
1
Enable and provide a clock to ADC module 1 in deep-sleep
mode.
ADC Module 0 Deep-Sleep Mode Clock Gating Control
Value Description
0
ADC module 0 is disabled.
1
Enable and provide a clock to ADC module 0 in deep-sleep
mode.
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System Control
Register 86: Analog Comparator Deep-Sleep Mode Clock Gating Control
(DCGCACMP), offset 0x83C
The DCGCACMP register provides software the capability to enable and disable the analog
comparator module in deep-sleep mode. When enabled, a module is provided a clock. When
disabled, the clock is disabled to save power. This register provides the same capability as the
legacy Deep-Sleep Mode Clock Gating Control Register n DCGCn registers specifically for the
watchdog modules and has the same bit polarity as the corresponding DCGCn bits.
Important: This register should be used to control the clocking for the analog comparator module.
To support legacy software, the DCGC1 register is available. Setting any of the COMPn
bits in the DCGC1 register also sets the D0 bit in this register. If any of the COMPn bits
are set by writing to the DCGC1 register, it can be read back correctly when reading
the DCGC1 register. If software uses this register to change the clocking for the analog
comparator module, the write causes proper operation, but the value D0 is not reflected
by the COMPn bits in the DCGC1 register. If software uses both legacy and
peripheral-specific register accesses, the peripheral-specific registers must be accessed
by read-modify-write operations that affect only peripherals that are not present in the
legacy registers. In this manner, both the peripheral-specific and legacy registers have
coherent information.
Analog Comparator Deep-Sleep Mode Clock Gating Control (DCGCACMP)
Base 0x400F.E000
Offset 0x83C
Type RW, reset 0x0000.0000
31
30
29
28
27
26
25
24
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
8
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
23
22
21
20
19
18
17
16
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
7
6
5
4
3
2
1
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RW
0
reserved
Type
Reset
reserved
Type
Reset
RO
0
D0
Bit/Field
Name
Type
Reset
Description
31:1
reserved
RO
0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0
D0
RW
0
Analog Comparator Module 0 Deep-Sleep Mode Clock Gating Control
Value Description
0
Analog comparator module is disabled.
1
Enable and provide a clock to the analog comparator module
in deep-sleep mode.
360
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Tiva™ TM4C1230C3PM Microcontroller
Register 87: EEPROM Deep-Sleep Mode Clock Gating Control (DCGCEEPROM),
offset 0x858
The DCGCEEPROM register provides software the capability to enable and disable the EEPROM
module in deep-sleep mode. When enabled, a module is provided a clock. When disabled, the clock
is disabled to save power.
EEPROM Deep-Sleep Mode Clock Gating Control (DCGCEEPROM)
Base 0x400F.E000
Offset 0x858
Type RW, reset 0x0000.0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
RO
0
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
8
7
6
5
4
3
2
1
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
0
D0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RW
0
Bit/Field
Name
Type
Reset
Description
31:1
reserved
RO
0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0
D0
RW
0
EEPROM Module Deep-Sleep Mode Clock Gating Control
Value Description
0
EEPROM module is disabled.
1
Enable and provide a clock to the EEPROM module in
deep-sleep mode.
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System Control
Register 88: 32/64-Bit Wide General-Purpose Timer Deep-Sleep Mode Clock
Gating Control (DCGCWTIMER), offset 0x85C
The DCGCWTIMER register provides software the capability to enable and disable 32/64-bit wide
timer modules in deep-sleep mode. When enabled, a module is provided a clock. When disabled,
the clock is disabled to save power. This register provides the same capability as the legacy
Deep-Sleep Mode Clock Gating Control Register n DCGCn registers specifically for the timer
modules and has the same bit polarity as the corresponding DCGCn bits.
32/64-Bit Wide General-Purpose Timer Deep-Sleep Mode Clock Gating Control (DCGCWTIMER)
Base 0x400F.E000
Offset 0x85C
Type RW, reset 0x0000.0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
8
7
6
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
5
4
3
2
1
0
D5
D4
D3
D2
D1
D0
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
Bit/Field
Name
Type
Reset
Description
31:6
reserved
RO
0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
5
D5
RW
0
32/64-Bit Wide General-Purpose Timer 5 Deep-Sleep Mode Clock Gating
Control
Value Description
4
D4
RW
0
0
32/64-bit wide general-purpose timer module 5 is disabled.
1
Enable and provide a clock to 32/64-bit wide general-purpose
timer module 5 in deep-sleep mode.
32/64-Bit Wide General-Purpose Timer 4 Deep-Sleep Mode Clock Gating
Control
Value Description
3
D3
RW
0
0
32/64-bit wide general-purpose timer module 4 is disabled.
1
Enable and provide a clock to 32/64-bit wide general-purpose
timer module 4 in deep-sleep mode.
32/64-Bit Wide General-Purpose Timer 3 Deep-Sleep Mode Clock Gating
Control
Value Description
0
32/64-bit wide general-purpose timer module 3 is disabled.
1
Enable and provide a clock to 32/64-bit wide general-purpose
timer module 3 in deep-sleep mode.
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Tiva™ TM4C1230C3PM Microcontroller
Bit/Field
Name
Type
Reset
2
D2
RW
0
Description
32/64-Bit Wide General-Purpose Timer 2 Deep-Sleep Mode Clock Gating
Control
Value Description
1
D1
RW
0
0
32/64-bit wide general-purpose timer module 2 is disabled.
1
Enable and provide a clock to 32/64-bit wide general-purpose
timer module 2 in deep-sleep mode.
32/64-Bit Wide General-Purpose Timer 1 Deep-Sleep Mode Clock Gating
Control
Value Description
0
D0
RW
0
0
32/64-bit wide general-purpose timer module 1 is disabled.
1
Enable and provide a clock to 32/64-bit wide general-purpose
timer module 1 in deep-sleep mode.
32/64-Bit Wide General-Purpose Timer 0 Deep-Sleep Mode Clock Gating
Control
Value Description
0
32/64-bit wide general-purpose timer module 0 is disabled.
1
Enable and provide a clock to 32/64-bit wide general-purpose
timer module 0 in deep-sleep mode.
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System Control
Register 89: Watchdog Timer Peripheral Ready (PRWD), offset 0xA00
The PRWD register indicates whether the watchdog modules are ready to be accessed by software
following a change in status of power, Run mode clocking, or reset. A Run mode clocking change
is initiated if the corresponding RCGCWD bit is changed. A reset change is initiated if the
corresponding SRWD bit is changed from 0 to 1.
The PRWD bit is cleared on any of the above events and is not set again until the module is
completely powered, enabled, and internally reset.
Watchdog Timer Peripheral Ready (PRWD)
Base 0x400F.E000
Offset 0xA00
Type RO, reset 0x0000.0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
RO
0
RO
0
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
1
0
R1
R0
RO
0
RO
0
Bit/Field
Name
Type
Reset
Description
31:2
reserved
RO
0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
1
R1
RO
0
Watchdog Timer 1 Peripheral Ready
Value Description
0
R0
RO
0
0
Watchdog module 1 is not ready for access. It is unclocked,
unpowered, or in the process of completing a reset sequence.
1
Watchdog module 1 is ready for access.
Watchdog Timer 0 Peripheral Ready
Value Description
0
Watchdog module 0 is not ready for access. It is unclocked,
unpowered, or in the process of completing a reset sequence.
1
Watchdog module 0 is ready for access.
364
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Tiva™ TM4C1230C3PM Microcontroller
Register 90: 16/32-Bit General-Purpose Timer Peripheral Ready (PRTIMER),
offset 0xA04
The PRTIMER register indicates whether the timer modules are ready to be accessed by software
following a change in status of power, Run mode clocking, or reset. A Run mode clocking change
is initiated if the corresponding RCGCTIMER bit is changed. A reset change is initiated if the
corresponding SRTIMER bit is changed from 0 to 1.
The PRTIMER bit is cleared on any of the above events and is not set again until the module is
completely powered, enabled, and internally reset.
16/32-Bit General-Purpose Timer Peripheral Ready (PRTIMER)
Base 0x400F.E000
Offset 0xA04
Type RO, reset 0x0000.0000
31
30
29
28
27
26
25
24
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
23
22
21
20
19
18
17
16
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
8
7
6
5
4
3
2
1
0
R5
R4
R3
R2
R1
R0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
reserved
Type
Reset
reserved
Type
Reset
RO
0
Bit/Field
Name
Type
Reset
Description
31:6
reserved
RO
0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
5
R5
RO
0
16/32-Bit General-Purpose Timer 5 Peripheral Ready
Value Description
4
R4
RO
0
0
16/32-bit timer module 5 is not ready for access. It is unclocked,
unpowered, or in the process of completing a reset sequence.
1
16/32-bit timer module 5 is ready for access.
16/32-Bit General-Purpose Timer 4 Peripheral Ready
Value Description
3
R3
RO
0
0
16/32-bit timer module 4 is not ready for access. It is unclocked,
unpowered, or in the process of completing a reset sequence.
1
16/32-bit timer module 4 is ready for access.
16/32-Bit General-Purpose Timer 3 Peripheral Ready
Value Description
0
16/32-bit timer module 3 is not ready for access. It is unclocked,
unpowered, or in the process of completing a reset sequence.
1
16/32-bit timer module 3 is ready for access.
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System Control
Bit/Field
Name
Type
Reset
2
R2
RO
0
Description
16/32-Bit General-Purpose Timer 2 Peripheral Ready
Value Description
1
R1
RO
0
0
16/32-bit timer module 2 is not ready for access. It is unclocked,
unpowered, or in the process of completing a reset sequence.
1
16/32-bit timer module 2 is ready for access.
16/32-Bit General-Purpose Timer 1 Peripheral Ready
Value Description
0
R0
RO
0
0
16/32-bit timer module 1 is not ready for access. It is unclocked,
unpowered, or in the process of completing a reset sequence.
1
16/32-bit timer module 1 is ready for access.
16/32-Bit General-Purpose Timer 0 Peripheral Ready
Value Description
0
16/32-bit timer module 0 is not ready for access. It is unclocked,
unpowered, or in the process of completing a reset sequence.
1
16/32-bit timer module 0 is ready for access.
366
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Tiva™ TM4C1230C3PM Microcontroller
Register 91: General-Purpose Input/Output Peripheral Ready (PRGPIO), offset
0xA08
The PRGPIO register indicates whether the GPIO modules are ready to be accessed by software
following a change in status of power, Run mode clocking, or reset. A Run mode clocking change
is initiated if the corresponding RCGCGPIO bit is changed. A reset change is initiated if the
corresponding SRGPIO bit is changed from 0 to 1.
The PRGPIO bit is cleared on any of the above events and is not set again until the module is
completely powered, enabled, and internally reset.
General-Purpose Input/Output Peripheral Ready (PRGPIO)
Base 0x400F.E000
Offset 0xA08
Type RO, reset 0x0000.0000
31
30
29
28
27
26
25
24
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
23
22
21
20
19
18
17
16
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
8
7
6
5
4
3
2
1
0
R6
R5
R4
R3
R2
R1
R0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
reserved
Type
Reset
reserved
Type
Reset
RO
0
Bit/Field
Name
Type
Reset
Description
31:7
reserved
RO
0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
6
R6
RO
0
GPIO Port G Peripheral Ready
Value Description
5
R5
RO
0
0
GPIO Port G is not ready for access. It is unclocked, unpowered,
or in the process of completing a reset sequence.
1
GPIO Port G is ready for access.
GPIO Port F Peripheral Ready
Value Description
4
R4
RO
0
0
GPIO Port F is not ready for access. It is unclocked, unpowered,
or in the process of completing a reset sequence.
1
GPIO Port F is ready for access.
GPIO Port E Peripheral Ready
Value Description
0
GPIO Port E is not ready for access. It is unclocked, unpowered,
or in the process of completing a reset sequence.
1
GPIO Port E is ready for access.
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System Control
Bit/Field
Name
Type
Reset
3
R3
RO
0
Description
GPIO Port D Peripheral Ready
Value Description
2
R2
RO
0
0
GPIO Port D is not ready for access. It is unclocked, unpowered,
or in the process of completing a reset sequence.
1
GPIO Port D is ready for access.
GPIO Port C Peripheral Ready
Value Description
1
R1
RO
0
0
GPIO Port C is not ready for access. It is unclocked, unpowered,
or in the process of completing a reset sequence.
1
GPIO Port C is ready for access.
GPIO Port B Peripheral Ready
Value Description
0
R0
RO
0
0
GPIO Port B is not ready for access. It is unclocked, unpowered,
or in the process of completing a reset sequence.
1
GPIO Port B is ready for access.
GPIO Port A Peripheral Ready
Value Description
0
GPIO Port A is not ready for access. It is unclocked, unpowered,
or in the process of completing a reset sequence.
1
GPIO Port A is ready for access.
368
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Texas Instruments-Production Data
Tiva™ TM4C1230C3PM Microcontroller
Register 92: Micro Direct Memory Access Peripheral Ready (PRDMA), offset
0xA0C
The PRDMA register indicates whether the μDMA module is ready to be accessed by software
following a change in status of power, Run mode clocking, or reset. A Run mode clocking change
is initiated if the corresponding RCGCDMA bit is changed. A reset change is initiated if the
corresponding SRDMA bit is changed from 0 to 1.
The PRDMA bit is cleared on any of the above events and is not set again until the module is
completely powered, enabled, and internally reset.
Micro Direct Memory Access Peripheral Ready (PRDMA)
Base 0x400F.E000
Offset 0xA0C
Type RO, reset 0x0000.0000
31
30
29
28
27
26
25
24
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
8
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
23
22
21
20
19
18
17
16
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
7
6
5
4
3
2
1
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
reserved
Type
Reset
reserved
Type
Reset
RO
0
R0
Bit/Field
Name
Type
Reset
Description
31:1
reserved
RO
0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0
R0
RO
0
μDMA Module Peripheral Ready
Value Description
0
The μDMA module is not ready for access. It is unclocked,
unpowered, or in the process of completing a reset sequence.
1
The μDMA module is ready for access.
June 12, 2014
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System Control
Register 93: Universal Asynchronous Receiver/Transmitter Peripheral Ready
(PRUART), offset 0xA18
The PRUART register indicates whether the UART modules are ready to be accessed by software
following a change in status of power, Run mode clocking, or reset. A Run mode clocking change
is initiated if the corresponding RCGCUART bit is changed. A reset change is initiated if the
corresponding SRUART bit is changed from 0 to 1.
The PRUART bit is cleared on any of the above events and is not set again until the module is
completely powered, enabled, and internally reset.
Universal Asynchronous Receiver/Transmitter Peripheral Ready (PRUART)
Base 0x400F.E000
Offset 0xA18
Type RO, reset 0x0000.0000
31
30
29
28
27
26
25
24
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
23
22
21
20
19
18
17
16
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
8
7
6
5
4
3
2
1
0
R7
R6
R5
R4
R3
R2
R1
R0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
reserved
Type
Reset
reserved
Type
Reset
RO
0
Bit/Field
Name
Type
Reset
Description
31:8
reserved
RO
0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
7
R7
RO
0
UART Module 7 Peripheral Ready
Value Description
6
R6
RO
0
0
UART module 7 is not ready for access. It is unclocked,
unpowered, or in the process of completing a reset sequence.
1
UART module 7 is ready for access.
UART Module 6 Peripheral Ready
Value Description
5
R5
RO
0
0
UART module 6 is not ready for access. It is unclocked,
unpowered, or in the process of completing a reset sequence.
1
UART module 6 is ready for access.
UART Module 5 Peripheral Ready
Value Description
0
UART module 5 is not ready for access. It is unclocked,
unpowered, or in the process of completing a reset sequence.
1
UART module 5 is ready for access.
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Tiva™ TM4C1230C3PM Microcontroller
Bit/Field
Name
Type
Reset
4
R4
RO
0
Description
UART Module 4 Peripheral Ready
Value Description
3
R3
RO
0
0
UART module 4 is not ready for access. It is unclocked,
unpowered, or in the process of completing a reset sequence.
1
UART module 4 is ready for access.
UART Module 3 Peripheral Ready
Value Description
2
R2
RO
0
0
UART module 3 is not ready for access. It is unclocked,
unpowered, or in the process of completing a reset sequence.
1
UART module 3 is ready for access.
UART Module 2 Peripheral Ready
Value Description
1
R1
RO
0
0
UART module 2 is not ready for access. It is unclocked,
unpowered, or in the process of completing a reset sequence.
1
UART module 2 is ready for access.
UART Module 1 Peripheral Ready
Value Description
0
R0
RO
0
0
UART module 1 is not ready for access. It is unclocked,
unpowered, or in the process of completing a reset sequence.
1
UART module 1 is ready for access.
UART Module 0 Peripheral Ready
Value Description
0
UART module 0 is not ready for access. It is unclocked,
unpowered, or in the process of completing a reset sequence.
1
UART module 0 is ready for access.
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System Control
Register 94: Synchronous Serial Interface Peripheral Ready (PRSSI), offset
0xA1C
The PRSSI register indicates whether the SSI modules are ready to be accessed by software
following a change in status of power, Run mode clocking, or reset. A Run mode clocking change
is initiated if the corresponding RCGCSSI bit is changed. A reset change is initiated if the
corresponding SRSSI bit is changed from 0 to 1.
The PRSSI bit is cleared on any of the above events and is not set again until the module is
completely powered, enabled, and internally reset.
Synchronous Serial Interface Peripheral Ready (PRSSI)
Base 0x400F.E000
Offset 0xA1C
Type RO, reset 0x0000.0000
31
30
29
28
27
26
25
24
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
23
22
21
20
19
18
17
16
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
8
7
6
5
4
3
2
1
0
R3
R2
R1
R0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
reserved
Type
Reset
reserved
Type
Reset
Bit/Field
Name
Type
Reset
Description
31:4
reserved
RO
0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
3
R3
RO
0
SSI Module 3 Peripheral Ready
Value Description
2
R2
RO
0
0
SSI module 3 is not ready for access. It is unclocked,
unpowered, or in the process of completing a reset sequence.
1
SSI module 3 is ready for access.
SSI Module 2 Peripheral Ready
Value Description
1
R1
RO
0
0
SSI module 2 is not ready for access. It is unclocked,
unpowered, or in the process of completing a reset sequence.
1
SSI module 2 is ready for access.
SSI Module 1 Peripheral Ready
Value Description
0
SSI module 1 is not ready for access. It is unclocked,
unpowered, or in the process of completing a reset sequence.
1
SSI module 1 is ready for access.
372
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Tiva™ TM4C1230C3PM Microcontroller
Bit/Field
Name
Type
Reset
0
R0
RO
0
Description
SSI Module 0 Peripheral Ready
Value Description
0
SSI module 0 is not ready for access. It is unclocked,
unpowered, or in the process of completing a reset sequence.
1
SSI module 0 is ready for access.
June 12, 2014
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System Control
Register 95: Inter-Integrated Circuit Peripheral Ready (PRI2C), offset 0xA20
The PRI2C register indicates whether the I2C modules are ready to be accessed by software following
a change in status of power, Run mode clocking, or reset. A Run mode clocking change is initiated
if the corresponding RCGCI2C bit is changed. A reset change is initiated if the corresponding SRI2C
bit is changed from 0 to 1.
The PRI2C bit is cleared on any of the above events and is not set again until the module is
completely powered, enabled, and internally reset.
Inter-Integrated Circuit Peripheral Ready (PRI2C)
Base 0x400F.E000
Offset 0xA20
Type RO, reset 0x0000.0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
8
7
6
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
5
4
3
2
1
0
R5
R4
R3
R2
R1
R0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
Bit/Field
Name
Type
Reset
Description
31:6
reserved
RO
0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
5
R5
RO
0
I2C Module 5 Peripheral Ready
Value Description
4
R4
RO
0
0
I2C module 5 is not ready for access. It is unclocked, unpowered,
or in the process of completing a reset sequence.
1
I2C module 5 is ready for access.
I2C Module 4 Peripheral Ready
Value Description
3
R3
RO
0
0
I2C module 4 is not ready for access. It is unclocked, unpowered,
or in the process of completing a reset sequence.
1
I2C module 4 is ready for access.
I2C Module 3 Peripheral Ready
Value Description
0
I2C module 3 is not ready for access. It is unclocked, unpowered,
or in the process of completing a reset sequence.
1
I2C module 3 is ready for access.
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Bit/Field
Name
Type
Reset
2
R2
RO
0
Description
I2C Module 2 Peripheral Ready
Value Description
1
R1
RO
0
0
I2C module 2 is not ready for access. It is unclocked, unpowered,
or in the process of completing a reset sequence.
1
I2C module 2 is ready for access.
I2C Module 1 Peripheral Ready
Value Description
0
R0
RO
0
0
I2C module 1 is not ready for access. It is unclocked, unpowered,
or in the process of completing a reset sequence.
1
I2C module 1 is ready for access.
I2C Module 0 Peripheral Ready
Value Description
0
I2C module 0 is not ready for access. It is unclocked, unpowered,
or in the process of completing a reset sequence.
1
I2C module 0 is ready for access.
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System Control
Register 96: Controller Area Network Peripheral Ready (PRCAN), offset 0xA34
The PRCAN register indicates whether the CAN modules are ready to be accessed by software
following a change in status of power, Run mode clocking, or reset. A Run mode clocking change
is initiated if the corresponding RCGCCAN bit is changed. A reset change is initiated if the
corresponding SRCAN bit is changed from 0 to 1.
The PRCAN bit is cleared on any of the above events and is not set again until the module is
completely powered, enabled, and internally reset.
Controller Area Network Peripheral Ready (PRCAN)
Base 0x400F.E000
Offset 0xA34
Type RO, reset 0x0000.0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
RO
0
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
8
7
6
5
4
3
2
1
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
0
R0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
Bit/Field
Name
Type
Reset
Description
31:1
reserved
RO
0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0
R0
RO
0
CAN Module 0 Peripheral Ready
Value Description
0
CAN module 0 is not ready for access. It is unclocked,
unpowered, or in the process of completing a reset sequence.
1
CAN module 0 is ready for access.
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Register 97: Analog-to-Digital Converter Peripheral Ready (PRADC), offset
0xA38
The PRADC register indicates whether the ADC modules are ready to be accessed by software
following a change in status of power, Run mode clocking, or reset. A Run mode clocking change
is initiated if the corresponding RCGCADC bit is changed. A reset change is initiated if the
corresponding SRADC bit is changed from 0 to 1.
The PRADC bit is cleared on any of the above events and is not set again until the module is
completely powered, enabled, and internally reset.
Analog-to-Digital Converter Peripheral Ready (PRADC)
Base 0x400F.E000
Offset 0xA38
Type RO, reset 0x0000.0000
31
30
29
28
27
26
25
24
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
23
22
21
20
19
18
17
16
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
8
7
6
5
4
3
2
1
0
R1
R0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
reserved
Type
Reset
reserved
Type
Reset
Bit/Field
Name
Type
Reset
Description
31:2
reserved
RO
0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
1
R1
RO
0
ADC Module 1 Peripheral Ready
Value Description
0
R0
RO
0
0
ADC module 1 is not ready for access. It is unclocked,
unpowered, or in the process of completing a reset sequence.
1
ADC module 1 is ready for access.
ADC Module 0 Peripheral Ready
Value Description
0
ADC module 0 is not ready for access. It is unclocked,
unpowered, or in the process of completing a reset sequence.
1
ADC module 0 is ready for access.
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Register 98: Analog Comparator Peripheral Ready (PRACMP), offset 0xA3C
The PRACMP register indicates whether the analog comparator module is ready to be accessed
by software following a change in status of power, Run mode clocking, or reset. A Run mode clocking
change is initiated if the corresponding RCGCACMP bit is changed. A reset change is initiated if
the corresponding SRACMP bit is changed from 0 to 1.
The PRACMP bit is cleared on any of the above events and is not set again until the module is
completely powered, enabled, and internally reset.
Analog Comparator Peripheral Ready (PRACMP)
Base 0x400F.E000
Offset 0xA3C
Type RO, reset 0x0000.0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
RO
0
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
8
7
6
5
4
3
2
1
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
0
R0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
Bit/Field
Name
Type
Reset
Description
31:1
reserved
RO
0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0
R0
RO
0
Analog Comparator Module 0 Peripheral Ready
Value Description
0
The analog comparator module is not ready for access. It is
unclocked, unpowered, or in the process of completing a reset
sequence.
1
The analog comparator module is ready for access.
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Register 99: EEPROM Peripheral Ready (PREEPROM), offset 0xA58
The PREEPROM register indicates whether the EEPROM module is ready to be accessed by
software following a change in status of power, Run mode clocking, or reset. A Run mode clocking
change is initiated if the corresponding RCGCEEPROM bit is changed. A reset change is initiated
if the corresponding SREEPROM bit is changed from 0 to 1.
The PREEPROM bit is cleared on any of the above events and is not set again until the module is
completely powered, enabled, and internally reset.
EEPROM Peripheral Ready (PREEPROM)
Base 0x400F.E000
Offset 0xA58
Type RO, reset 0x0000.0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
RO
0
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
8
7
6
5
4
3
2
1
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
0
R0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
Bit/Field
Name
Type
Reset
Description
31:1
reserved
RO
0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0
R0
RO
0
EEPROM Module Peripheral Ready
Value Description
0
The EEPROM module is not ready for access. It is unclocked,
unpowered, or in the process of completing a reset sequence.
1
The EEPROM module is ready for access.
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System Control
Register 100: 32/64-Bit Wide General-Purpose Timer Peripheral Ready
(PRWTIMER), offset 0xA5C
The PRWTIMER register indicates whether the timer modules are ready to be accessed by software
following a change in status of power, Run mode clocking, or reset. A Run mode clocking change
is initiated if the corresponding RCGCWTIMER bit is changed. A reset change is initiated if the
corresponding SRWTIMER bit is changed from 0 to 1.
The PRWTIMER bit is cleared on any of the above events and is not set again until the module is
completely powered, enabled, and internally reset.
32/64-Bit Wide General-Purpose Timer Peripheral Ready (PRWTIMER)
Base 0x400F.E000
Offset 0xA5C
Type RO, reset 0x0000.0000
31
30
29
28
27
26
25
24
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
23
22
21
20
19
18
17
16
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
8
7
6
5
4
3
2
1
0
R5
R4
R3
R2
R1
R0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
reserved
Type
Reset
reserved
Type
Reset
RO
0
Bit/Field
Name
Type
Reset
Description
31:6
reserved
RO
0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
5
R5
RO
0
32/64-Bit Wide General-Purpose Timer 5 Peripheral Ready
Value Description
4
R4
RO
0
0
32/64-bit wide timer module 5 is not ready for access. It is
unclocked, unpowered, or in the process of completing a reset
sequence.
1
32/64-bit wide timer module 5 is ready for access.
32/64-Bit Wide General-Purpose Timer 4 Peripheral Ready
Value Description
3
R3
RO
0
0
32/64-bit wide timer module 4 is not ready for access. It is
unclocked, unpowered, or in the process of completing a reset
sequence.
1
32/64-bit wide timer module 4 is ready for access.
32/64-Bit Wide General-Purpose Timer 3 Peripheral Ready
Value Description
0
32/64-bit wide timer module 3 is not ready for access. It is
unclocked, unpowered, or in the process of completing a reset
sequence.
1
32/64-bit wide timer module 3 is ready for access.
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Bit/Field
Name
Type
Reset
2
R2
RO
0
Description
32/64-Bit Wide General-Purpose Timer 2 Peripheral Ready
Value Description
1
R1
RO
0
0
32/64-bit wide timer module 2 is not ready for access. It is
unclocked, unpowered, or in the process of completing a reset
sequence.
1
32/64-bit wide timer module 2 is ready for access.
32/64-Bit Wide General-Purpose Timer 1 Peripheral Ready
Value Description
0
R0
RO
0
0
32/64-bit wide timer module 1 is not ready for access. It is
unclocked, unpowered, or in the process of completing a reset
sequence.
1
32/64-bit wide timer module 1 is ready for access.
32/64-Bit Wide General-Purpose Timer 0 Peripheral Ready
Value Description
5.6
0
32/64-bit wide timer module 0 is not ready for access. It is
unclocked, unpowered, or in the process of completing a reset
sequence.
1
32/64-bit wide timer module 0 is ready for access.
System Control Legacy Register Descriptions
All addresses given are relative to the System Control base address of 0x400F.E000.
Important: Register in this section are provided for legacy software support only; registers in
“System Control Register Descriptions” on page 220 should be used instead.
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Register 101: Device Capabilities 0 (DC0), offset 0x008
This legacy register is predefined by the part and can be used to verify features.
Important: This register is provided for legacy software support only.
The Flash Size (FSIZE) and SRAM Size (SSIZE) registers should be used to determine
this microcontroller's memory sizes. A read of DC0 correctly identifies legacy memory
sizes but software must use FSIZE and SSIZE for memory sizes that are not listed
below.
Device Capabilities 0 (DC0)
Base 0x400F.E000
Offset 0x008
Type RO, reset 0x002F.000F
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
SRAMSZ
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
1
RO
0
RO
1
RO
1
RO
1
RO
1
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
RO
0
RO
0
RO
0
RO
1
RO
1
RO
1
RO
1
FLASHSZ
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
Bit/Field
Name
Type
Reset
Description
31:16
SRAMSZ
RO
0x2F
SRAM Size
Indicates the size of the on-chip SRAM.
Value Description
0x7
2 KB of SRAM
0xF
4 KB of SRAM
0x17 6 KB of SRAM
0x1F 8 KB of SRAM
0x2F 12 KB of SRAM
0x3F 16 KB of SRAM
0x4F 20 KB of SRAM
0x5F 24 KB of SRAM
0x7F 32 KB of SRAM
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Bit/Field
Name
Type
Reset
Description
15:0
FLASHSZ
RO
0xF
Flash Size
Indicates the size of the on-chip Flash memory.
Value Description
0x3
8 KB of Flash
0x7
16 KB of Flash
0xF
32 KB of Flash
0x1F 64 KB of Flash
0x2F 96 KB of Flash
0x3F 128 KB of Flash
0x5F 192 KB of Flash
0x7F 256 KB of Flash
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Register 102: Device Capabilities 1 (DC1), offset 0x010
This register is predefined by the part and can be used to verify features. If any bit is clear in this
register, the module is not present. The corresponding bit in the RCGC0, SCGC0, DCGC0, and the
peripheral-specific RCGC, SCGC, and DCGC registers cannot be set.
Important: This register is provided for legacy software support only.
The Peripheral Present registers should be used to determine which modules are
implemented on this microcontroller. A read of DC1 correctly identifies if a legacy module
is present but software must use the Peripheral Present registers to determine if a
module is present that is not supported by the DCn registers.
Likewise, the ADC Peripheral Properties (ADCPP) register should be used to determine
the maximum ADC sample rate and whether the temperature sensor is present. However,
to support legacy software, the MAXADCnSPD fields and the TEMPSNS bit are available.
A read of DC1 correctly identifies the maximum ADC sample rate for legacy rates and
whether the temperature sensor is present.
Device Capabilities 1 (DC1)
Base 0x400F.E000
Offset 0x010
Type RO, reset 0x1103.2FBF
31
30
29
reserved
Type
Reset
28
WDT1
26
24
23
22
20
19
18
16
CAN1
CAN0
PWM1
PWM0
ADC1
ADC0
RO
1
RO
0
RO
0
RO
0
RO
1
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
1
RO
1
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
MPU
HIB
TEMPSNS
PLL
WDT0
SWO
SWD
JTAG
RO
0
RO
0
RO
1
RO
0
RO
1
RO
1
RO
1
RO
1
RO
1
RO
1
MAXADC1SPD
MAXADC0SPD
RO
1
RO
1
RO
1
Bit/Field
Name
Type
Reset
31:29
reserved
RO
0
28
WDT1
RO
0x1
RO
1
reserved
17
RO
0
RO
0
reserved
21
RO
0
RO
1
reserved
25
RO
0
MINSYSDIV
Type
Reset
27
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
Watchdog Timer1 Present
When set, indicates that watchdog timer 1 is present.
27:26
reserved
RO
0
25
CAN1
RO
0x0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
CAN Module 1 Present
When set, indicates that CAN unit 1 is present.
24
CAN0
RO
0x1
CAN Module 0 Present
When set, indicates that CAN unit 0 is present.
23:22
reserved
RO
0
21
PWM1
RO
0x0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
PWM Module 1 Present
When set, indicates that the PWM module is present.
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Bit/Field
Name
Type
Reset
20
PWM0
RO
0x0
Description
PWM Module 0 Present
When set, indicates that the PWM module is present.
19:18
reserved
RO
0
17
ADC1
RO
0x1
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
ADC Module 1 Present
When set, indicates that ADC module 1 is present.
16
ADC0
RO
0x1
ADC Module 0 Present
When set, indicates that ADC module 0 is present
15:12
MINSYSDIV
RO
0x2
System Clock Divider
Minimum 4-bit divider value for system clock. The reset value is
hardware-dependent. See the RCC register for how to change the
system clock divisor using the SYSDIV bit.
Value Description
11:10
MAXADC1SPD
RO
0x3
0x1
Reserved
0x2
Specifies an 80-MHz CPU clock with a PLL divider of 2.5.
0x3
Specifies a 50-MHz CPU clock with a PLL divider of 4.
0x4
Specifies a 40-MHz CPU clock with a PLL divider of 5.
0x7
Specifies a 25-MHz clock with a PLL divider of 8.
0x9
Specifies a 20-MHz clock with a PLL divider of 10.
Max ADC1 Speed
This field indicates the maximum rate at which the ADC samples data.
Value Description
9:8
MAXADC0SPD
RO
0x3
0x3
1M samples/second
0x2
500K samples/second
0x1
250K samples/second
0x0
125K samples/second
Max ADC0 Speed
This field indicates the maximum rate at which the ADC samples data.
Value Description
7
MPU
RO
0x1
0x3
1M samples/second
0x2
500K samples/second
0x1
250K samples/second
0x0
125K samples/second
MPU Present
When set, indicates that the Cortex-M4F Memory Protection Unit (MPU)
module is present. See the "Cortex-M4F Peripherals" chapter for details
on the MPU.
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Bit/Field
Name
Type
Reset
6
HIB
RO
0x0
Description
Hibernation Module Present
When set, indicates that the Hibernation module is present.
5
TEMPSNS
RO
0x1
Temp Sensor Present
When set, indicates that the on-chip temperature sensor is present.
4
PLL
RO
0x1
PLL Present
When set, indicates that the on-chip Phase Locked Loop (PLL) is
present.
3
WDT0
RO
0x1
Watchdog Timer 0 Present
When set, indicates that watchdog timer 0 is present.
2
SWO
RO
0x1
SWO Trace Port Present
When set, indicates that the Serial Wire Output (SWO) trace port is
present.
1
SWD
RO
0x1
SWD Present
When set, indicates that the Serial Wire Debugger (SWD) is present.
0
JTAG
RO
0x1
JTAG Present
When set, indicates that the JTAG debugger interface is present.
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Register 103: Device Capabilities 2 (DC2), offset 0x014
This register is predefined by the part and can be used to verify features. If any bit is clear in this
register, the module is not present. The corresponding bit in the RCGC1, SCGC1, DCGC1, and the
peripheral-specific RCGC, SCGC, and DCGC registers registers cannot be set.
Important: This register is provided for legacy software support only.
The Peripheral Present registers should be used to determine which modules are
implemented on this microcontroller. A read of DC2 correctly identifies if a legacy module
is present but software must use the Peripheral Present registers to determine if a
module is present that is not supported by the DCn registers.
Note that the Analog Comparator Peripheral Present (PPACMP) register identifies
whether the analog comparator module is present. The Analog Comparator Peripheral
Properties (ACMPPP) register indicates how many analog comparator blocks are
present in the module.
Device Capabilities 2 (DC2)
Base 0x400F.E000
Offset 0x014
Type RO, reset 0x030F.F037
Type
Reset
Type
Reset
31
30
29
28
27
26
25
24
reserved
EPI0
reserved
I2S0
reserved
COMP2
COMP1
COMP0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
1
15
14
13
12
11
10
I2C1HS
I2C1
I2C0HS
I2C0
RO
1
RO
1
RO
1
RO
1
reserved
RO
0
RO
0
23
22
RO
1
RO
0
RO
0
RO
0
RO
0
9
8
7
6
5
QEI1
QEI0
RO
0
RO
0
Bit/Field
Name
Type
Reset
31
reserved
RO
0
30
EPI0
RO
0x0
21
20
19
18
17
16
TIMER3
TIMER2
TIMER1
TIMER0
RO
1
RO
1
RO
1
RO
1
4
3
2
1
0
SSI1
SSI0
reserved
UART2
UART1
UART0
RO
1
RO
1
RO
0
RO
1
RO
1
RO
1
reserved
reserved
RO
0
RO
0
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
EPI Module 0 Present
When set, indicates that EPI module 0 is present.
29
reserved
RO
0
28
I2S0
RO
0x0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
I2S Module 0 Present
When set, indicates that I2S module 0 is present.
27
reserved
RO
0
26
COMP2
RO
0x0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
Analog Comparator 2 Present
When set, indicates that analog comparator 2 is present.
25
COMP1
RO
0x1
Analog Comparator 1 Present
When set, indicates that analog comparator 1 is present.
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Bit/Field
Name
Type
Reset
24
COMP0
RO
0x1
Description
Analog Comparator 0 Present
When set, indicates that analog comparator 0 is present.
23:20
reserved
RO
0
19
TIMER3
RO
0x1
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
Timer Module 3 Present
When set, indicates that General-Purpose Timer module 3 is present.
18
TIMER2
RO
0x1
Timer Module 2 Present
When set, indicates that General-Purpose Timer module 2 is present.
17
TIMER1
RO
0x1
Timer Module 1 Present
When set, indicates that General-Purpose Timer module 1 is present.
16
TIMER0
RO
0x1
Timer Module 0 Present
When set, indicates that General-Purpose Timer module 0 is present.
15
I2C1HS
RO
0x1
I2C Module 1 Speed
When set, indicates that I2C module 1 can operate in high-speed mode.
14
I2C1
RO
0x1
I2C Module 1 Present
When set, indicates that I2C module 1 is present.
13
I2C0HS
RO
0x1
I2C Module 0 Speed
When set, indicates that I2C module 0 can operate in high-speed mode.
12
I2C0
RO
0x1
I2C Module 0 Present
When set, indicates that I2C module 0 is present.
11:10
reserved
RO
0
9
QEI1
RO
0x0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
QEI Module 1 Present
When set, indicates that QEI module 1 is present.
8
QEI0
RO
0x0
QEI Module 0 Present
When set, indicates that QEI module 0 is present.
7:6
reserved
RO
0
5
SSI1
RO
0x1
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
SSI Module 1 Present
When set, indicates that SSI module 1 is present.
4
SSI0
RO
0x1
SSI Module 0 Present
When set, indicates that SSI module 0 is present.
3
reserved
RO
0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
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Bit/Field
Name
Type
Reset
2
UART2
RO
0x1
Description
UART Module 2 Present
When set, indicates that UART module 2 is present.
1
UART1
RO
0x1
UART Module 1 Present
When set, indicates that UART module 1 is present.
0
UART0
RO
0x1
UART Module 0 Present
When set, indicates that UART module 0 is present.
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System Control
Register 104: Device Capabilities 3 (DC3), offset 0x018
This register is predefined by the part and can be used to verify features. If any bit is clear in this
register, the feature is not present.
Important: This register is provided for legacy software support only.
For some modules, the peripheral-resident Peripheral Properties registers should be
used to determine which pins are available on this microcontroller. A read of DC3
correctly identifies if a legacy pin is present but software must use the Peripheral
Properties registers to determine if a pin is present that is not supported by the DCn
registers.
Device Capabilities 3 (DC3)
Base 0x400F.E000
Offset 0x018
Type RO, reset 0xBFFF.0FC0
Type
Reset
Type
Reset
31
30
29
28
27
26
25
24
32KHZ
reserved
CCP5
CCP4
CCP3
CCP2
CCP1
CCP0
RO
1
RO
0
RO
1
RO
1
RO
1
RO
1
RO
1
RO
1
13
12
10
9
15
14
PWMFAULT
C2O
RO
0
RO
0
C2PLUS C2MINUS
RO
0
RO
0
11
C1O
C1PLUS C1MINUS
RO
1
RO
1
RO
1
Bit/Field
Name
Type
Reset
31
32KHZ
RO
0x1
23
8
C0O
22
21
20
19
18
17
16
ADC0AIN7 ADC0AIN6 ADC0AIN5 ADC0AIN4 ADC0AIN3 ADC0AIN2 ADC0AIN1 ADC0AIN0
RO
1
RO
1
7
6
C0PLUS C0MINUS
RO
1
RO
1
RO
1
RO
1
RO
1
RO
1
RO
1
RO
1
5
4
3
2
1
0
PWM5
PWM4
PWM3
PWM2
PWM1
PWM0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
1
Description
32KHz Input Clock Available
When set, indicates an even CCP pin is present and can be used as a
32-KHz input clock.
Note:
30
reserved
RO
0
29
CCP5
RO
0x1
The GPTMPP register does not provide this information.
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
T2CCP1 Pin Present
When set, indicates that Capture/Compare/PWM pin T2CCP1 is present.
Note:
28
CCP4
RO
0x1
The GPTMPP register does not provide this information.
T2CCP0 Pin Present
When set, indicates that Capture/Compare/PWM pin T2CCP0 is present.
Note:
27
CCP3
RO
0x1
The GPTMPP register does not provide this information.
T1CCP1 Pin Present
When set, indicates that Capture/Compare/PWM pin T1CCP1 is present.
Note:
26
CCP2
RO
0x1
The GPTMPP register does not provide this information.
T1CCP0 Pin Present
When set, indicates that Capture/Compare/PWM pin T1CCP0 is present.
Note:
The GPTMPP register does not provide this information.
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Bit/Field
Name
Type
Reset
25
CCP1
RO
0x1
Description
T0CCP1 Pin Present
When set, indicates that Capture/Compare/PWM pin T0CCP1 is present.
Note:
24
CCP0
RO
0x1
The GPTMPP register does not provide this information.
T0CCP0 Pin Present
When set, indicates that Capture/Compare/PWM pin T0CCP0 is present.
Note:
23
ADC0AIN7
RO
0x1
The GPTMPP register does not provide this information.
ADC Module 0 AIN7 Pin Present
When set, indicates that ADC module 0 input pin 7 is present.
Note:
22
ADC0AIN6
RO
0x1
The CH field in the ADCPP register provides this information.
ADC Module 0 AIN6 Pin Present
When set, indicates that ADC module 0 input pin 6 is present.
Note:
21
ADC0AIN5
RO
0x1
The CH field in the ADCPP register provides this information.
ADC Module 0 AIN5 Pin Present
When set, indicates that ADC module 0 input pin 5 is present.
Note:
20
ADC0AIN4
RO
0x1
The CH field in the ADCPP register provides this information.
ADC Module 0 AIN4 Pin Present
When set, indicates that ADC module 0 input pin 4 is present.
Note:
19
ADC0AIN3
RO
0x1
The CH field in the ADCPP register provides this information.
ADC Module 0 AIN3 Pin Present
When set, indicates that ADC module 0 input pin 3 is present.
Note:
18
ADC0AIN2
RO
0x1
The CH field in the ADCPP register provides this information.
ADC Module 0 AIN2 Pin Present
When set, indicates that ADC module 0 input pin 2 is present.
Note:
17
ADC0AIN1
RO
0x1
The CH field in the ADCPP register provides this information.
ADC Module 0 AIN1 Pin Present
When set, indicates that ADC module 0 input pin 1 is present.
Note:
16
ADC0AIN0
RO
0x1
The CH field in the ADCPP register provides this information.
ADC Module 0 AIN0 Pin Present
When set, indicates that ADC module 0 input pin 0 is present.
Note:
15
PWMFAULT
RO
0x0
The CH field in the ADCPP register provides this information.
PWM Fault Pin Present
When set, indicates that a PWM Fault pin is present. See DC5 for
specific Fault pins on this device.
Note:
14
C2O
RO
0x0
The FCNT field in the PWMPP register provides this
information.
C2o Pin Present
When set, indicates that the analog comparator 2 output pin is present.
Note:
The C2O bit in the ACMPPP register provides this information.
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Bit/Field
Name
Type
Reset
13
C2PLUS
RO
0x0
Description
C2+ Pin Present
When set, indicates that the analog comparator 2 (+) input pin is present.
Note:
12
C2MINUS
RO
0x0
This pin is present when analog comparator 2 is present.
C2- Pin Present
When set, indicates that the analog comparator 2 (-) input pin is present.
Note:
11
C1O
RO
0x1
This pin is present when analog comparator 2 is present.
C1o Pin Present
When set, indicates that the analog comparator 1 output pin is present.
Note:
10
C1PLUS
RO
0x1
The C1O bit in the ACMPPP register provides this information.
C1+ Pin Present
When set, indicates that the analog comparator 1 (+) input pin is present.
Note:
9
C1MINUS
RO
0x1
This pin is present when analog comparator 1 is present.
C1- Pin Present
When set, indicates that the analog comparator 1 (-) input pin is present.
Note:
8
C0O
RO
0x1
This pin is present when analog comparator 1 is present.
C0o Pin Present
When set, indicates that the analog comparator 0 output pin is present.
Note:
7
C0PLUS
RO
0x1
The C0O bit in the ACMPPP register provides this information.
C0+ Pin Present
When set, indicates that the analog comparator 0 (+) input pin is present.
Note:
6
C0MINUS
RO
0x1
This pin is present when analog comparator 0 is present.
C0- Pin Present
When set, indicates that the analog comparator 0 (-) input pin is present.
Note:
5
PWM5
RO
0x0
This pin is present when analog comparator 0 is present.
PWM5 Pin Present
When set, indicates that the PWM pin 5 is present.
Note:
4
PWM4
RO
0x0
The GCNT field in the PWMPP register provides this
information.
PWM4 Pin Present
When set, indicates that the PWM pin 4 is present.
Note:
3
PWM3
RO
0x0
The GCNT field in the PWMPP register provides this
information.
PWM3 Pin Present
When set, indicates that the PWM pin 3 is present.
Note:
The GCNT field in the PWMPP register provides this
information.
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Bit/Field
Name
Type
Reset
2
PWM2
RO
0x0
Description
PWM2 Pin Present
When set, indicates that the PWM pin 2 is present.
Note:
1
PWM1
RO
0x0
The GCNT field in the PWMPP register provides this
information.
PWM1 Pin Present
When set, indicates that the PWM pin 1 is present.
Note:
0
PWM0
RO
0x0
The GCNT field in the PWMPP register provides this
information.
PWM0 Pin Present
When set, indicates that the PWM pin 0 is present.
Note:
The GCNT field in the PWMPP register provides this
information.
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System Control
Register 105: Device Capabilities 4 (DC4), offset 0x01C
This register is predefined by the part and can be used to verify features. If any bit is clear in this
register, the module is not present. The corresponding bit in the RCGC2, SCGC2, DCGC2, and the
peripheral-specific RCGC, SCGC, and DCGC registers registers cannot be set.
Important: This register is provided for legacy software support only.
The Peripheral Present registers should be used to determine which modules are
implemented on this microcontroller. A read of DC4 correctly identifies if a legacy module
is present but software must use the Peripheral Present registers to determine if a
module is present that is not supported by the DCn registers.
The peripheral-resident Peripheral Properties registers should be used to determine
which pins and features are available on this microcontroller. A read of DC4 correctly
identifies if a legacy pin or feature is present. Software must use the Peripheral Properties
registers to determine if a pin or feature is present that is not supported by the DCn
registers.
Device Capabilities 4 (DC4)
Base 0x400F.E000
Offset 0x01C
Type RO, reset 0x0004.F07F
Type
Reset
Type
Reset
31
30
29
28
27
26
25
reserved
EPHY0
reserved
EMAC0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
CCP7
CCP6
UDMA
ROM
RO
1
RO
1
RO
1
RO
1
reserved
RO
0
23
22
20
19
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
1
RO
0
RO
0
8
7
6
5
4
3
2
1
0
GPIOJ
RO
0
GPIOH
GPIOG
GPIOF
GPIOE
GPIOD
GPIOC
GPIOB
GPIOA
RO
0
RO
1
RO
1
RO
1
RO
1
RO
1
RO
1
RO
1
E1588
reserved
RO
0
24
RO
0
Bit/Field
Name
Type
Reset
31
reserved
RO
0
30
EPHY0
RO
0x0
21
reserved
18
17
PICAL
16
reserved
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
Ethernet PHY Layer 0 Present
When set, indicates that Ethernet PHY layer 0 is present.
29
reserved
RO
0
28
EMAC0
RO
0x0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
Ethernet MAC Layer 0 Present
When set, indicates that Ethernet MAC layer 0 is present.
27:25
reserved
RO
0
24
E1588
RO
0x0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
1588 Capable
When set, indicates that Ethernet MAC layer 0 is 1588 capable.
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Bit/Field
Name
Type
Reset
23:19
reserved
RO
0
18
PICAL
RO
0x1
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
PIOSC Calibrate
When set, indicates that the PIOSC can be calibrated by software.
17:16
reserved
RO
0
15
CCP7
RO
0x1
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
T3CCP1 Pin Present
When set, indicates that Capture/Compare/PWM pin T3CCP1 is present.
Note:
14
CCP6
RO
0x1
The GPTMPP register does not provide this information.
T3CCP0 Pin Present
When set, indicates that Capture/Compare/PWM pin T3CCP0 is present.
Note:
13
UDMA
RO
0x1
The GPTMPP register does not provide this information.
Micro-DMA Module Present
When set, indicates that the micro-DMA module present.
12
ROM
RO
0x1
Internal Code ROM Present
When set, indicates that internal code ROM is present.
11:9
reserved
RO
0
8
GPIOJ
RO
0x0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
GPIO Port J Present
When set, indicates that GPIO Port J is present.
7
GPIOH
RO
0x0
GPIO Port H Present
When set, indicates that GPIO Port H is present.
6
GPIOG
RO
0x1
GPIO Port G Present
When set, indicates that GPIO Port G is present.
5
GPIOF
RO
0x1
GPIO Port F Present
When set, indicates that GPIO Port F is present.
4
GPIOE
RO
0x1
GPIO Port E Present
When set, indicates that GPIO Port E is present.
3
GPIOD
RO
0x1
GPIO Port D Present
When set, indicates that GPIO Port D is present.
2
GPIOC
RO
0x1
GPIO Port C Present
When set, indicates that GPIO Port C is present.
1
GPIOB
RO
0x1
GPIO Port B Present
When set, indicates that GPIO Port B is present.
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Bit/Field
Name
Type
Reset
0
GPIOA
RO
0x1
Description
GPIO Port A Present
When set, indicates that GPIO Port A is present.
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Register 106: Device Capabilities 5 (DC5), offset 0x020
This register is predefined by the part and can be used to verify PWM features. If any bit is clear in
this register, the module is not present.
Important: This register is provided for legacy software support only.
The PWM Peripheral Properties (PWMPP) register should be used to determine what
pins and features are available on PWM modules. A read of this register correctly
identifies if a legacy pin or feature is present. Software must use the PWMPP register
to determine if a pin or feature that is not supported by the DCn registers is present.
Device Capabilities 5 (DC5)
Base 0x400F.E000
Offset 0x020
Type RO, reset 0x0000.0000
31
30
29
28
reserved
Type
Reset
27
26
25
24
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
8
reserved
Type
Reset
RO
0
RO
0
23
RO
0
RO
0
RO
0
RO
0
RO
0
Bit/Field
Name
Type
Reset
31:28
reserved
RO
0
27
PWMFAULT3
RO
0x0
RO
0
22
reserved
PWMFAULT3 PWMFAULT2 PWMFAULT1 PWMFAULT0
RO
0
21
20
19
18
PWMEFLT PWMESYNC
RO
0
RO
0
RO
0
17
16
reserved
RO
0
RO
0
RO
0
RO
0
7
6
5
4
3
2
1
0
PWM7
PWM6
PWM5
PWM4
PWM3
PWM2
PWM1
PWM0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
PWM Fault 3 Pin Present
When set, indicates that the PWM Fault 3 pin is present.
26
PWMFAULT2
RO
0x0
PWM Fault 2 Pin Present
When set, indicates that the PWM Fault 2 pin is present.
25
PWMFAULT1
RO
0x0
PWM Fault 1 Pin Present
When set, indicates that the PWM Fault 1 pin is present.
24
PWMFAULT0
RO
0x0
PWM Fault 0 Pin Present
When set, indicates that the PWM Fault 0 pin is present.
23:22
reserved
RO
0
21
PWMEFLT
RO
0x0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
PWM Extended Fault Active
When set, indicates that the PWM Extended Fault feature is active.
20
PWMESYNC
RO
0x0
PWM Extended SYNC Active
When set, indicates that the PWM Extended SYNC feature is active.
19:8
reserved
RO
0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
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System Control
Bit/Field
Name
Type
Reset
7
PWM7
RO
0x0
Description
PWM7 Pin Present
When set, indicates that the PWM pin 7 is present.
6
PWM6
RO
0x0
PWM6 Pin Present
When set, indicates that the PWM pin 6 is present.
5
PWM5
RO
0x0
PWM5 Pin Present
When set, indicates that the PWM pin 5 is present.
4
PWM4
RO
0x0
PWM4 Pin Present
When set, indicates that the PWM pin 4 is present.
3
PWM3
RO
0x0
PWM3 Pin Present
When set, indicates that the PWM pin 3 is present.
2
PWM2
RO
0x0
PWM2 Pin Present
When set, indicates that the PWM pin 2 is present.
1
PWM1
RO
0x0
PWM1 Pin Present
When set, indicates that the PWM pin 1 is present.
0
PWM0
RO
0x0
PWM0 Pin Present
When set, indicates that the PWM pin 0 is present.
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Register 107: Device Capabilities 6 (DC6), offset 0x024
This register is predefined by the part and can be used to verify features. If any bit is clear in this
register, the module is not present. The corresponding bit in the RCGC0, SCGC0, and DCGC0
registers cannot be set.
Important: This register is provided for legacy software support only.
The USB Peripheral Properties (USBPP) register should be used to determine what
features are available on the USB module. A read of this register correctly identifies if
a legacy feature is present. Software must use the USBPP register to determine if a
pin or feature that is not supported by the DCn registers is present.
Device Capabilities 6 (DC6)
Base 0x400F.E000
Offset 0x024
Type RO, reset 0x0000.0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
RO
0
RO
0
RO
0
RO
0
RO
0
4
3
2
1
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
10
9
8
7
6
5
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
USB0PHY
RO
0
Bit/Field
Name
Type
Reset
31:5
reserved
RO
0
4
USB0PHY
RO
0x0
RO
0
RO
0
RO
0
RO
0
RO
0
reserved
RO
0
RO
0
0
USB0
RO
0
RO
0
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
USB Module 0 PHY Present
When set, indicates that the USB module 0 PHY is present.
3:2
reserved
RO
0
1:0
USB0
RO
0x0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
USB Module 0 Present
This field indicates that USB module 0 is present and specifies its
capability.
sysValue Description
0x0
NA
USB0 is not present.
0x1
DEVICE
USB0 is Device Only.
0x2
HOST
USB0 is Device or Host.
0x3
OTG
USB0 is OTG.
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System Control
Register 108: Device Capabilities 7 (DC7), offset 0x028
This register is predefined by the part and can be used to verify μDMA channel features. A 1 indicates
the channel is available on this device; a 0 that the channel is only available on other devices in the
family. Channels can have multiple assignments, see “Channel Assignments” on page 508 for more
information.
Important: This register is provided for legacy software support only. The DMACHANS bit field in
the DMA Status (DMASTAT) register indicates the number of DMA channels.
Device Capabilities 7 (DC7)
Base 0x400F.E000
Offset 0x028
Type RO, reset 0xFFFF.FFFF
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
reserved DMACH30 DMACH29 DMACH28 DMACH27 DMACH26 DMACH25 DMACH24 DMACH23 DMACH22 DMACH21 DMACH20 DMACH19 DMACH18 DMACH17 DMACH16
Type
Reset
RO
1
RO
1
RO
1
RO
1
RO
1
RO
1
RO
1
RO
1
RO
1
RO
1
RO
1
RO
1
RO
1
RO
1
RO
1
RO
1
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
DMACH15 DMACH14 DMACH13 DMACH12 DMACH11 DMACH10 DMACH9 DMACH8 DMACH7 DMACH6 DMACH5 DMACH4 DMACH3 DMACH2 DMACH1 DMACH0
Type
Reset
RO
1
RO
1
RO
1
RO
1
RO
1
RO
1
RO
1
Bit/Field
Name
Type
Reset
31
reserved
RO
0x1
RO
1
RO
1
RO
1
RO
1
RO
1
RO
1
RO
1
RO
1
RO
1
Description
DMA Channel 31
When set, indicates μDMA channel 31 is available.
30
DMACH30
RO
0x1
DMA Channel 30
When set, indicates μDMA channel 30 is available.
29
DMACH29
RO
0x1
DMA Channel 29
When set, indicates μDMA channel 29 is available.
28
DMACH28
RO
0x1
DMA Channel 28
When set, indicates μDMA channel 28 is available.
27
DMACH27
RO
0x1
DMA Channel 27
When set, indicates μDMA channel 27 is available.
26
DMACH26
RO
0x1
DMA Channel 26
When set, indicates μDMA channel 26 is available.
25
DMACH25
RO
0x1
DMA Channel 25
When set, indicates μDMA channel 25 is available.
24
DMACH24
RO
0x1
DMA Channel 24
When set, indicates μDMA channel 24 is available.
23
DMACH23
RO
0x1
DMA Channel 23
When set, indicates μDMA channel 23 is available.
22
DMACH22
RO
0x1
DMA Channel 22
When set, indicates μDMA channel 22 is available.
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Tiva™ TM4C1230C3PM Microcontroller
Bit/Field
Name
Type
Reset
21
DMACH21
RO
0x1
Description
DMA Channel 21
When set, indicates μDMA channel 21 is available.
20
DMACH20
RO
0x1
DMA Channel 20
When set, indicates μDMA channel 20 is available.
19
DMACH19
RO
0x1
DMA Channel 19
When set, indicates μDMA channel 19 is available.
18
DMACH18
RO
0x1
DMA Channel 18
When set, indicates μDMA channel 18 is available.
17
DMACH17
RO
0x1
DMA Channel 17
When set, indicates μDMA channel 17 is available.
16
DMACH16
RO
0x1
DMA Channel 16
When set, indicates μDMA channel 16 is available.
15
DMACH15
RO
0x1
DMA Channel 15
When set, indicates μDMA channel 15 is available.
14
DMACH14
RO
0x1
DMA Channel 14
When set, indicates μDMA channel 14 is available.
13
DMACH13
RO
0x1
DMA Channel 13
When set, indicates μDMA channel 13 is available.
12
DMACH12
RO
0x1
DMA Channel 12
When set, indicates μDMA channel 12 is available.
11
DMACH11
RO
0x1
DMA Channel 11
When set, indicates μDMA channel 11 is available.
10
DMACH10
RO
0x1
DMA Channel 10
When set, indicates μDMA channel 10 is available.
9
DMACH9
RO
0x1
DMA Channel 9
When set, indicates μDMA channel 9 is available.
8
DMACH8
RO
0x1
DMA Channel 8
When set, indicates μDMA channel 8 is available.
7
DMACH7
RO
0x1
DMA Channel 7
When set, indicates μDMA channel 7 is available.
6
DMACH6
RO
0x1
DMA Channel 6
When set, indicates μDMA channel 6 is available.
5
DMACH5
RO
0x1
DMA Channel 5
When set, indicates μDMA channel 5 is available.
4
DMACH4
RO
0x1
DMA Channel 4
When set, indicates μDMA channel 4 is available.
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System Control
Bit/Field
Name
Type
Reset
3
DMACH3
RO
0x1
Description
DMA Channel 3
When set, indicates μDMA channel 3 is available.
2
DMACH2
RO
0x1
DMA Channel 2
When set, indicates μDMA channel 2 is available.
1
DMACH1
RO
0x1
DMA Channel 1
When set, indicates μDMA channel 1 is available.
0
DMACH0
RO
0x1
DMA Channel 0
When set, indicates μDMA channel 0 is available.
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Register 109: Device Capabilities 8 (DC8), offset 0x02C
This register is predefined by the part and can be used to verify features.
Important: This register is provided for legacy software support only.
The ADC Peripheral Properties (ADCPP) register should be used to determine how
many input channels are available on the ADC module. A read of this register correctly
identifies if legacy channels are present but software must use the ADCPP register to
determine if a channel is present that is not supported by the DCn registers.
Device Capabilities 8 (DC8)
Base 0x400F.E000
Offset 0x02C
Type RO, reset 0x0FFF.0FFF
Type
Reset
Type
Reset
31
30
29
28
27
26
ADC1AIN15
ADC1AIN14
ADC1AIN13
ADC1AIN12
ADC1AIN11
ADC1AIN10
RO
0
RO
0
RO
0
RO
0
RO
1
RO
1
15
14
13
12
11
10
ADC0AIN15
ADC0AIN14
ADC0AIN13
ADC0AIN12
ADC0AIN11
ADC0AIN10
RO
0
RO
0
RO
0
RO
0
RO
1
RO
1
25
24
23
22
21
20
19
18
17
16
ADC1AIN9 ADC1AIN8 ADC1AIN7 ADC1AIN6 ADC1AIN5 ADC1AIN4 ADC1AIN3 ADC1AIN2 ADC1AIN1 ADC1AIN0
RO
1
RO
1
RO
1
RO
1
RO
1
RO
1
RO
1
RO
1
RO
1
RO
1
9
8
7
6
5
4
3
2
1
0
ADC0AIN9 ADC0AIN8 ADC0AIN7 ADC0AIN6 ADC0AIN5 ADC0AIN4 ADC0AIN3 ADC0AIN2 ADC0AIN1 ADC0AIN0
RO
1
Bit/Field
Name
Type
Reset
31
ADC1AIN15
RO
0x0
RO
1
RO
1
RO
1
RO
1
RO
1
RO
1
RO
1
RO
1
RO
1
Description
ADC Module 1 AIN15 Pin Present
When set, indicates that ADC module 1 input pin 15 is present.
30
ADC1AIN14
RO
0x0
ADC Module 1 AIN14 Pin Present
When set, indicates that ADC module 1 input pin 14 is present.
29
ADC1AIN13
RO
0x0
ADC Module 1 AIN13 Pin Present
When set, indicates that ADC module 1 input pin 13 is present.
28
ADC1AIN12
RO
0x0
ADC Module 1 AIN12 Pin Present
When set, indicates that ADC module 1 input pin 12 is present.
27
ADC1AIN11
RO
0x1
ADC Module 1 AIN11 Pin Present
When set, indicates that ADC module 1 input pin 11 is present.
26
ADC1AIN10
RO
0x1
ADC Module 1 AIN10 Pin Present
When set, indicates that ADC module 1 input pin 10 is present.
25
ADC1AIN9
RO
0x1
ADC Module 1 AIN9 Pin Present
When set, indicates that ADC module 1 input pin 9 is present.
24
ADC1AIN8
RO
0x1
ADC Module 1 AIN8 Pin Present
When set, indicates that ADC module 1 input pin 8 is present.
23
ADC1AIN7
RO
0x1
ADC Module 1 AIN7 Pin Present
When set, indicates that ADC module 1 input pin 7 is present.
22
ADC1AIN6
RO
0x1
ADC Module 1 AIN6 Pin Present
When set, indicates that ADC module 1 input pin 6 is present.
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Bit/Field
Name
Type
Reset
21
ADC1AIN5
RO
0x1
Description
ADC Module 1 AIN5 Pin Present
When set, indicates that ADC module 1 input pin 5 is present.
20
ADC1AIN4
RO
0x1
ADC Module 1 AIN4 Pin Present
When set, indicates that ADC module 1 input pin 4 is present.
19
ADC1AIN3
RO
0x1
ADC Module 1 AIN3 Pin Present
When set, indicates that ADC module 1 input pin 3 is present.
18
ADC1AIN2
RO
0x1
ADC Module 1 AIN2 Pin Present
When set, indicates that ADC module 1 input pin 2 is present.
17
ADC1AIN1
RO
0x1
ADC Module 1 AIN1 Pin Present
When set, indicates that ADC module 1 input pin 1 is present.
16
ADC1AIN0
RO
0x1
ADC Module 1 AIN0 Pin Present
When set, indicates that ADC module 1 input pin 0 is present.
15
ADC0AIN15
RO
0x0
ADC Module 0 AIN15 Pin Present
When set, indicates that ADC module 0 input pin 15 is present.
14
ADC0AIN14
RO
0x0
ADC Module 0 AIN14 Pin Present
When set, indicates that ADC module 0 input pin 14 is present.
13
ADC0AIN13
RO
0x0
ADC Module 0 AIN13 Pin Present
When set, indicates that ADC module 0 input pin 13 is present.
12
ADC0AIN12
RO
0x0
ADC Module 0 AIN12 Pin Present
When set, indicates that ADC module 0 input pin 12 is present.
11
ADC0AIN11
RO
0x1
ADC Module 0 AIN11 Pin Present
When set, indicates that ADC module 0 input pin 11 is present.
10
ADC0AIN10
RO
0x1
ADC Module 0 AIN10 Pin Present
When set, indicates that ADC module 0 input pin 10 is present.
9
ADC0AIN9
RO
0x1
ADC Module 0 AIN9 Pin Present
When set, indicates that ADC module 0 input pin 9 is present.
8
ADC0AIN8
RO
0x1
ADC Module 0 AIN8 Pin Present
When set, indicates that ADC module 0 input pin 8 is present.
7
ADC0AIN7
RO
0x1
ADC Module 0 AIN7 Pin Present
When set, indicates that ADC module 0 input pin 7 is present.
6
ADC0AIN6
RO
0x1
ADC Module 0 AIN6 Pin Present
When set, indicates that ADC module 0 input pin 6 is present.
5
ADC0AIN5
RO
0x1
ADC Module 0 AIN5 Pin Present
When set, indicates that ADC module 0 input pin 5 is present.
4
ADC0AIN4
RO
0x1
ADC Module 0 AIN4 Pin Present
When set, indicates that ADC module 0 input pin 4 is present.
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Bit/Field
Name
Type
Reset
3
ADC0AIN3
RO
0x1
Description
ADC Module 0 AIN3 Pin Present
When set, indicates that ADC module 0 input pin 3 is present.
2
ADC0AIN2
RO
0x1
ADC Module 0 AIN2 Pin Present
When set, indicates that ADC module 0 input pin 2 is present.
1
ADC0AIN1
RO
0x1
ADC Module 0 AIN1 Pin Present
When set, indicates that ADC module 0 input pin 1 is present.
0
ADC0AIN0
RO
0x1
ADC Module 0 AIN0 Pin Present
When set, indicates that ADC module 0 input pin 0 is present.
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System Control
Register 110: Software Reset Control 0 (SRCR0), offset 0x040
This register allows individual modules to be reset. Writes to this register are masked by the bits in
the Device Capabilities 1 (DC1) register.
Important: This register is provided for legacy software support only.
The peripheral-specific Software Reset registers (such as SRWD) should be used to
reset specific peripherals. A write to this legacy register also writes the corresponding
bit in the peripheral-specific register. Any bits that are changed by writing to this legacy
register can be read back correctly with a read of this register. Software must use the
peripheral-specific registers to support modules that are not present in the legacy
registers. If software uses a peripheral-specific register to write a legacy peripheral
(such as Watchdog 1), the write causes proper operation, but the value of that bit is not
reflected in this register. If software uses both legacy and peripheral-specific register
accesses, the peripheral-specific registers must be accessed by read-modify-write
operations that affect only peripherals that are not present in the legacy registers. In
this manner, both the peripheral-specific and legacy registers have coherent information.
Software Reset Control 0 (SRCR0)
Base 0x400F.E000
Offset 0x040
Type RO, reset 0x0000.0000
31
30
29
reserved
Type
Reset
28
27
WDT1
26
25
reserved
24
23
22
21
CAN0
20
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
8
7
6
5
4
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
19
18
reserved
RO
0
RO
0
3
2
WDT0
RO
0
Bit/Field
Name
Type
Reset
31:29
reserved
RO
0
28
WDT1
RO
0x0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
17
16
ADC1
ADC0
RO
0
RO
0
1
0
reserved
RO
0
RO
0
RO
0
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
WDT1 Reset Control
When this bit is set, Watchdog Timer module 1 is reset. All internal data
is lost and the registers are returned to their reset states. This bit must
be manually cleared after being set.
27:25
reserved
RO
0
24
CAN0
RO
0x0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
CAN0 Reset Control
When this bit is set, CAN module 0 is reset. All internal data is lost and
the registers are returned to their reset states. This bit must be manually
cleared after being set.
23:18
reserved
RO
0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
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Bit/Field
Name
Type
Reset
17
ADC1
RO
0x0
Description
ADC1 Reset Control
When this bit is set, ADC module 1 is reset. All internal data is lost and
the registers are returned to their reset states. This bit must be manually
cleared after being set.
16
ADC0
RO
0x0
ADC0 Reset Control
When this bit is set, ADC module 0 is reset. All internal data is lost and
the registers are returned to their reset states. This bit must be manually
cleared after being set.
15:4
reserved
RO
0
3
WDT0
RO
0x0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
WDT0 Reset Control
When this bit is set, Watchdog Timer module 0 is reset. All internal data
is lost and the registers are returned to their reset states. This bit must
be manually cleared after being set.
2:0
reserved
RO
0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
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System Control
Register 111: Software Reset Control 1 (SRCR1), offset 0x044
This register allows individual modules to be reset. Writes to this register are masked by the bits in
the Device Capabilities 2 (DC2) register.
Important: This register is provided for legacy software support only.
The peripheral-specific Software Reset registers (such as SRTIMER) should be used
to reset specific peripherals. A write to this register also writes the corresponding bit in
the peripheral-specific register. Any bits that are changed by writing to this register can
be read back correctly with a read of this register. Software must use the
peripheral-specific registers to support modules that are not present in the legacy
registers. If software uses a peripheral-specific register to write a legacy peripheral
(such as TIMER0), the write causes proper operation, but the value of that bit is not
reflected in this register. If software uses both legacy and peripheral-specific register
accesses, the peripheral-specific registers must be accessed by read-modify-write
operations that affect only peripherals that are not present in the legacy registers. In
this manner, both the peripheral-specific and legacy registers have coherent information.
Note that the Software Reset Analog Comparator (SRACMP) register has only one
bit to set the analog comparator module. Resetting the module resets all the blocks. If
any of the COMPn bits are set, the entire analog comparator module is reset. It is not
possible to reset the blocks individually.
Software Reset Control 1 (SRCR1)
Base 0x400F.E000
Offset 0x044
Type RO, reset 0x0000.0000
31
30
29
RO
0
RO
0
RO
0
15
14
reserved
RO
0
28
27
26
25
24
RO
0
RO
0
RO
0
COMP1
COMP0
RO
0
13
12
11
10
9
I2C1
reserved
I2C0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
reserved
Type
Reset
Type
Reset
23
22
RO
0
RO
0
RO
0
Name
Type
Reset
31:26
reserved
RO
0
25
COMP1
RO
0x0
20
19
18
17
16
RO
0
RO
0
TIMER3
TIMER2
TIMER1
TIMER0
RO
0
RO
0
RO
0
RO
0
8
7
6
5
4
3
2
1
0
RO
0
RO
0
RO
0
SSI1
SSI0
reserved
UART2
UART1
UART0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
reserved
reserved
Bit/Field
21
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
Analog Comp 1 Reset Control
When this bit is set, Analog Comparator module 1 is reset. All internal
data is lost and the registers are returned to their reset states. This bit
must be manually cleared after being set.
24
COMP0
RO
0x0
Analog Comp 0 Reset Control
When this bit is set, Analog Comparator module 0 is reset. All internal
data is lost and the registers are returned to their reset states. This bit
must be manually cleared after being set.
23:20
reserved
RO
0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
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Tiva™ TM4C1230C3PM Microcontroller
Bit/Field
Name
Type
Reset
19
TIMER3
RO
0x0
Description
Timer 3 Reset Control
Timer 3 Reset Control. When this bit is set, General-Purpose Timer
module 3 is reset. All internal data is lost and the registers are returned
to their reset states. This bit must be manually cleared after being set.
18
TIMER2
RO
0x0
Timer 2 Reset Control
When this bit is set, General-Purpose Timer module 2 is reset. All internal
data is lost and the registers are returned to their reset states. This bit
must be manually cleared after being set.
17
TIMER1
RO
0x0
Timer 1 Reset Control
When this bit is set, General-Purpose Timer module 1 is reset. All internal
data is lost and the registers are returned to their reset states. This bit
must be manually cleared after being set.
16
TIMER0
RO
0x0
Timer 0 Reset Control
When this bit is set, General-Purpose Timer module 0 is reset. All internal
data is lost and the registers are returned to their reset states. This bit
must be manually cleared after being set.
15
reserved
RO
0
14
I2C1
RO
0x0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
I2C1 Reset Control
When this bit is set, I2C module 1 is reset. All internal data is lost and
the registers are returned to their reset states. This bit must be manually
cleared after being set.
13
reserved
RO
0
12
I2C0
RO
0x0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
I2C0 Reset Control
When this bit is set, I2C module 0 is reset. All internal data is lost and
the registers are returned to their reset states. This bit must be manually
cleared after being set.
11:6
reserved
RO
0
5
SSI1
RO
0x0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
SSI1 Reset Control
When this bit is set, SSI module 1 is reset. All internal data is lost and
the registers are returned to their reset states. This bit must be manually
cleared after being set.
4
SSI0
RO
0x0
SSI0 Reset Control
When this bit is set, SSI module 0 is reset. All internal data is lost and
the registers are returned to their reset states. This bit must be manually
cleared after being set.
3
reserved
RO
0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
June 12, 2014
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System Control
Bit/Field
Name
Type
Reset
2
UART2
RO
0x0
Description
UART2 Reset Control
When this bit is set, UART module 2 is reset. All internal data is lost and
the registers are returned to their reset states. This bit must be manually
cleared after being set.
1
UART1
RO
0x0
UART1 Reset Control
When this bit is set, UART module 1 is reset. All internal data is lost and
the registers are returned to their reset states. This bit must be manually
cleared after being set.
0
UART0
RO
0x0
UART0 Reset Control
When this bit is set, UART module 0 is reset. All internal data is lost and
the registers are returned to their reset states. This bit must be manually
cleared after being set.
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Tiva™ TM4C1230C3PM Microcontroller
Register 112: Software Reset Control 2 (SRCR2), offset 0x048
This register allows individual modules to be reset. Writes to this register are masked by the bits in
the Device Capabilities 4 (DC4) register.
Important: This register is provided for legacy software support only.
The peripheral-specific Software Reset registers (such as SRDMA) should be used to
reset specific peripherals. A write to this legacy register also writes the corresponding
bit in the peripheral-specific register. Any bits that are changed by writing to this register
can be read back correctly with a read of this register. Software must use the
peripheral-specific registers to support modules that are not present in the legacy
registers. If software uses a peripheral-specific register to write a legacy peripheral
(such as the μDMA), the write causes proper operation, but the value of that bit is not
reflected in this register. If software uses both legacy and peripheral-specific register
accesses, the peripheral-specific registers must be accessed by read-modify-write
operations that affect only peripherals that are not present in the legacy registers. In
this manner, both the peripheral-specific and legacy registers have coherent information.
Software Reset Control 2 (SRCR2)
Base 0x400F.E000
Offset 0x048
Type RO, reset 0x0000.0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
reserved
Type
Reset
RO
0
RO
0
15
14
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
13
12
11
10
9
8
7
UDMA
RO
0
reserved
RO
0
RO
0
RO
0
RO
0
Bit/Field
Name
Type
Reset
31:14
reserved
RO
0
13
UDMA
RO
0x0
RO
0
RO
0
6
5
4
3
2
1
0
GPIOG
GPIOF
GPIOE
GPIOD
GPIOC
GPIOB
GPIOA
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
Micro-DMA Reset Control
When this bit is set, uDMA module is reset. All internal data is lost and
the registers are returned to their reset states. This bit must be manually
cleared after being set.
12:7
reserved
RO
0
6
GPIOG
RO
0x0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
Port G Reset Control
When this bit is set, Port G module is reset. All internal data is lost and
the registers are returned to their reset states. This bit must be manually
cleared after being set.
5
GPIOF
RO
0x0
Port F Reset Control
When this bit is set, Port F module is reset. All internal data is lost and
the registers are returned to their reset states. This bit must be manually
cleared after being set.
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Bit/Field
Name
Type
Reset
4
GPIOE
RO
0x0
Description
Port E Reset Control
When this bit is set, Port E module is reset. All internal data is lost and
the registers are returned to their reset states. This bit must be manually
cleared after being set.
3
GPIOD
RO
0x0
Port D Reset Control
When this bit is set, Port D module is reset. All internal data is lost and
the registers are returned to their reset states. This bit must be manually
cleared after being set.
2
GPIOC
RO
0x0
Port C Reset Control
When this bit is set, Port C module is reset. All internal data is lost and
the registers are returned to their reset states. This bit must be manually
cleared after being set.
1
GPIOB
RO
0x0
Port B Reset Control
When this bit is set, Port B module is reset. All internal data is lost and
the registers are returned to their reset states. This bit must be manually
cleared after being set.
0
GPIOA
RO
0x0
Port A Reset Control
When this bit is set, Port A module is reset. All internal data is lost and
the registers are returned to their reset states. This bit must be manually
cleared after being set.
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Register 113: Run Mode Clock Gating Control Register 0 (RCGC0), offset
0x100
This register controls the clock gating logic in normal Run mode. Each bit controls a clock enable
for a given interface, function, or module. If set, the module receives a clock and functions. Otherwise,
the module is unclocked and disabled (saving power). If the module is unclocked, reads or writes
to the module generate a bus fault. The reset state of these bits is 0 (unclocked) unless otherwise
noted, so that all functional modules are disabled. It is the responsibility of software to enable the
ports necessary for the application. Note that these registers may contain more bits than there are
interfaces, functions, or modules to control. This configuration is implemented to assure reasonable
code compatibility with other family and future parts. RCGC0 is the clock configuration register for
running operation, SCGC0 for Sleep operation, and DCGC0 for Deep-Sleep operation. Setting the
ACG bit in the Run-Mode Clock Configuration (RCC) register specifies that the system uses sleep
modes. Note that there must be a delay of 3 system clocks after a module clock is enabled before
any registers in that module are accessed.
Important: This register is provided for legacy software support only.
The peripheral-specific Run Mode Clock Gating Control registers (such as RCGCWD)
should be used to reset specific peripherals. A write to this legacy register also writes
the corresponding bit in the peripheral-specific register. Any bits that are changed by
writing to this register can be read back correctly with a read of this register. Software
must use the peripheral-specific registers to support modules that are not present in
the legacy registers. If software uses a peripheral-specific register to write a legacy
peripheral (such as Watchdog 1), the write causes proper operation, but the value of
that bit is not reflected in this register. If software uses both legacy and peripheral-specific
register accesses, the peripheral-specific registers must be accessed by
read-modify-write operations that affect only peripherals that are not present in the
legacy registers. In this manner, both the peripheral-specific and legacy registers have
coherent information.
Likewise, the ADC Peripheral Configuration (ADCPC) register should be used to
configure the ADC sample rate. However, to support legacy software, the MAXADCnSPD
fields are available. A write to these legacy fields also writes the corresponding field in
the peripheral-specific register. If a field is changed by writing to this register, it can be
read back correctly with a read of this register. Software must use the peripheral-specific
registers to support rates that are not available in this register. If software uses a
peripheral-specific register to set the ADC rate, the write causes proper operation, but
the value of that field is not reflected in this register. If software uses both legacy and
peripheral-specific register accesses, the peripheral-specific registers must be accessed
by read-modify-write operations that affect only peripherals that are not present in the
legacy registers. In this manner, both the peripheral-specific and legacy registers have
coherent information.
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System Control
Run Mode Clock Gating Control Register 0 (RCGC0)
Base 0x400F.E000
Offset 0x100
Type RO, reset 0x0000.0040
31
30
29
reserved
Type
Reset
28
WDT1
26
25
23
22
21
19
18
16
ADC1
ADC0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
reserved
reserved
RO
0
RO
0
RO
0
RO
1
MAXADC1SPD
MAXADC0SPD
RO
0
RO
0
RO
0
Bit/Field
Name
Type
Reset
31:29
reserved
RO
0
28
WDT1
RO
0x0
RO
0
reserved
17
RO
0
RO
0
CAN0
20
RO
0
RO
0
reserved
24
RO
0
reserved
Type
Reset
27
reserved
RO
0
RO
0
WDT0
RO
0
reserved
RO
0
RO
0
RO
0
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
WDT1 Clock Gating Control
This bit controls the clock gating for the Watchdog Timer module 1. If
set, the module receives a clock and functions. Otherwise, the module
is unclocked and disabled. If the module is unclocked, a read or write
to the module generates a bus fault.
27:25
reserved
RO
0
24
CAN0
RO
0x0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
CAN0 Clock Gating Control
This bit controls the clock gating for CAN module 0. If set, the module
receives a clock and functions. Otherwise, the module is unclocked and
disabled. If the module is unclocked, a read or write to the module
generates a bus fault.
23:18
reserved
RO
0
17
ADC1
RO
0x0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
ADC1 Clock Gating Control
This bit controls the clock gating for SAR ADC module 1. If set, the
module receives a clock and functions. Otherwise, the module is
unclocked and disabled. If the module is unclocked, a read or write to
the module generates a bus fault.
16
ADC0
RO
0x0
ADC0 Clock Gating Control
This bit controls the clock gating for ADC module 0. If set, the module
receives a clock and functions. Otherwise, the module is unclocked and
disabled. If the module is unclocked, a read or write to the module
generates a bus fault.
15:12
reserved
RO
0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
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Bit/Field
Name
Type
Reset
11:10
MAXADC1SPD
RO
0x0
Description
ADC1 Sample Speed
This field sets the rate at which ADC module 1 samples data. You cannot
set the rate higher than the maximum rate. You can set the sample rate
by setting the MAXADC1SPD bit as follows (all other encodings are
reserved):
Value Description
9:8
MAXADC0SPD
RO
0x0
0x0
125K samples/second
0x1
250K samples/second
0x2
500K samples/second
0x3
1M samples/second
ADC0 Sample Speed
This field sets the rate at which ADC0 samples data. You cannot set
the rate higher than the maximum rate. You can set the sample rate by
setting the MAXADC0SPD bit as follows (all other encodings are reserved):
Value Description
0x0
125K samples/second
0x1
250K samples/second
0x2
500K samples/second
0x3
1M samples/second
7
reserved
RO
0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
6
reserved
RO
0x1
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
5:4
reserved
RO
0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
3
WDT0
RO
0x0
WDT0 Clock Gating Control
This bit controls the clock gating for the Watchdog Timer module 0. If
set, the module receives a clock and functions. Otherwise, the module
is unclocked and disabled. If the module is unclocked, a read or write
to the module generates a bus fault.
2:0
reserved
RO
0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
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System Control
Register 114: Run Mode Clock Gating Control Register 1 (RCGC1), offset
0x104
This register controls the clock gating logic in normal Run mode. Each bit controls a clock enable
for a given interface, function, or module. If set, the module receives a clock and functions. Otherwise,
the module is unclocked and disabled (saving power). If the module is unclocked, reads or writes
to the module generate a bus fault. The reset state of these bits is 0 (unclocked) unless otherwise
noted, so that all functional modules are disabled. It is the responsibility of software to enable the
ports necessary for the application. Note that these registers may contain more bits than there are
interfaces, functions, or modules to control. This configuration is implemented to assure reasonable
code compatibility with other family and future parts. RCGC1 is the clock configuration register for
running operation, SCGC1 for Sleep operation, and DCGC1 for Deep-Sleep operation. Setting the
ACG bit in the Run-Mode Clock Configuration (RCC) register specifies that the system uses sleep
modes. Note that there must be a delay of 3 system clocks after a module clock is enabled before
any registers in that module are accessed.
Important: This register is provided for legacy software support only.
The peripheral-specific Run Mode Clock Gating Control registers (such as RCGCTIMER)
should be used to reset specific peripherals. A write to this legacy register also writes
the corresponding bit in the peripheral-specific register. Any bits that are changed by
writing to this register can be read back correctly with a read of this register. Software
must use the peripheral-specific registers to support modules that are not present in
the legacy registers. If software uses a peripheral-specific register to write a legacy
peripheral (such as Timer 0), the write causes proper operation, but the value of that
bit is not reflected in this register. If software uses both legacy and peripheral-specific
register accesses, the peripheral-specific registers must be accessed by
read-modify-write operations that affect only peripherals that are not present in the
legacy registers. In this manner, both the peripheral-specific and legacy registers have
coherent information.
Run Mode Clock Gating Control Register 1 (RCGC1)
Base 0x400F.E000
Offset 0x104
Type RO, reset 0x0000.0000
31
30
29
RO
0
RO
0
RO
0
15
14
reserved
RO
0
28
27
26
25
24
RO
0
RO
0
RO
0
COMP1
COMP0
RO
0
13
12
11
10
9
I2C1
reserved
I2C0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
reserved
Type
Reset
Type
Reset
23
22
RO
0
RO
0
RO
0
Name
Type
Reset
31:26
reserved
RO
0
20
19
18
17
16
RO
0
RO
0
TIMER3
TIMER2
TIMER1
TIMER0
RO
0
RO
0
RO
0
RO
0
8
7
6
5
4
3
2
1
0
RO
0
RO
0
RO
0
SSI1
SSI0
reserved
UART2
UART1
UART0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
reserved
reserved
Bit/Field
21
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
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Bit/Field
Name
Type
Reset
25
COMP1
RO
0x0
Description
Analog Comparator 1 Clock Gating
This bit controls the clock gating for analog comparator 1. If set, the
module receives a clock and functions. Otherwise, the module is
unclocked and disabled. If the module is unclocked, a read or write to
the module generates a bus fault.
24
COMP0
RO
0x0
Analog Comparator 0 Clock Gating
This bit controls the clock gating for analog comparator 0. If set, the
module receives a clock and functions. Otherwise, the module is
unclocked and disabled. If the module is unclocked, a read or write to
the module generates a bus fault.
23:20
reserved
RO
0
19
TIMER3
RO
0x0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
Timer 3 Clock Gating Control
This bit controls the clock gating for General-Purpose Timer module 3.
If set, the module receives a clock and functions. Otherwise, the module
is unclocked and disabled. If the module is unclocked, a read or write
to the module generates a bus fault.
18
TIMER2
RO
0x0
Timer 2 Clock Gating Control
This bit controls the clock gating for General-Purpose Timer module 2.
If set, the module receives a clock and functions. Otherwise, the module
is unclocked and disabled. If the module is unclocked, a read or write
to the module generates a bus fault.
17
TIMER1
RO
0x0
Timer 1 Clock Gating Control
This bit controls the clock gating for General-Purpose Timer module 1.
If set, the module receives a clock and functions. Otherwise, the module
is unclocked and disabled. If the module is unclocked, a read or write
to the module generates a bus fault.
16
TIMER0
RO
0x0
Timer 0 Clock Gating Control
This bit controls the clock gating for General-Purpose Timer module 0.
If set, the module receives a clock and functions. Otherwise, the module
is unclocked and disabled. If the module is unclocked, a read or write
to the module generates a bus fault.
15
reserved
RO
0
14
I2C1
RO
0x0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
I2C1 Clock Gating Control
This bit controls the clock gating for I2C module 1. If set, the module
receives a clock and functions. Otherwise, the module is unclocked and
disabled. If the module is unclocked, a read or write to the module
generates a bus fault.
13
reserved
RO
0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
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System Control
Bit/Field
Name
Type
Reset
12
I2C0
RO
0x0
Description
I2C0 Clock Gating Control
This bit controls the clock gating for I2C module 0. If set, the module
receives a clock and functions. Otherwise, the module is unclocked and
disabled. If the module is unclocked, a read or write to the module
generates a bus fault.
11:6
reserved
RO
0
5
SSI1
RO
0x0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
SSI1 Clock Gating Control
This bit controls the clock gating for SSI module 1. If set, the module
receives a clock and functions. Otherwise, the module is unclocked and
disabled. If the module is unclocked, a read or write to the module
generates a bus fault.
4
SSI0
RO
0x0
SSI0 Clock Gating Control
This bit controls the clock gating for SSI module 0. If set, the module
receives a clock and functions. Otherwise, the module is unclocked and
disabled. If the module is unclocked, a read or write to the module
generates a bus fault.
3
reserved
RO
0
2
UART2
RO
0x0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
UART2 Clock Gating Control
This bit controls the clock gating for UART module 2. If set, the module
receives a clock and functions. Otherwise, the module is unclocked and
disabled. If the module is unclocked, a read or write to the module
generates a bus fault.
1
UART1
RO
0x0
UART1 Clock Gating Control
This bit controls the clock gating for UART module 1. If set, the module
receives a clock and functions. Otherwise, the module is unclocked and
disabled. If the module is unclocked, a read or write to the module
generates a bus fault.
0
UART0
RO
0x0
UART0 Clock Gating Control
This bit controls the clock gating for UART module 0. If set, the module
receives a clock and functions. Otherwise, the module is unclocked and
disabled. If the module is unclocked, a read or write to the module
generates a bus fault.
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Register 115: Run Mode Clock Gating Control Register 2 (RCGC2), offset
0x108
This register controls the clock gating logic in normal Run mode. Each bit controls a clock enable
for a given interface, function, or module. If set, the module receives a clock and functions. Otherwise,
the module is unclocked and disabled (saving power). If the module is unclocked, reads or writes
to the module generate a bus fault. The reset state of these bits is 0 (unclocked) unless otherwise
noted, so that all functional modules are disabled. It is the responsibility of software to enable the
ports necessary for the application. Note that these registers may contain more bits than there are
interfaces, functions, or modules to control. This configuration is implemented to assure reasonable
code compatibility with other family and future parts. RCGC2 is the clock configuration register for
running operation, SCGC2 for Sleep operation, and DCGC2 for Deep-Sleep operation. Setting the
ACG bit in the Run-Mode Clock Configuration (RCC) register specifies that the system uses sleep
modes. Note that there must be a delay of 3 system clocks after a module clock is enabled before
any registers in that module are accessed.
Important: This register is provided for legacy software support only.
The peripheral-specific Run Mode Clock Gating Control registers (such as RCGCDMA)
should be used to reset specific peripherals. A write to this legacy register also writes
the corresponding bit in the peripheral-specific register. Any bits that are changed by
writing to this register can be read back correctly with a read of this register. Software
must use the peripheral-specific registers to support modules that are not present in
the legacy registers. If software uses a peripheral-specific register to write a legacy
peripheral (such as the μDMA), the write causes proper operation, but the value of that
bit is not reflected in this register. If software uses both legacy and peripheral-specific
register accesses, the peripheral-specific registers must be accessed by
read-modify-write operations that affect only peripherals that are not present in the
legacy registers. In this manner, both the peripheral-specific and legacy registers have
coherent information.
Run Mode Clock Gating Control Register 2 (RCGC2)
Base 0x400F.E000
Offset 0x108
Type RO, reset 0x0000.0000
31
30
29
28
27
26
25
24
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
RO
0
RO
0
RO
0
RO
0
23
22
21
20
19
18
17
16
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
8
7
6
5
4
3
2
1
0
GPIOG
GPIOF
GPIOE
GPIOD
GPIOC
GPIOB
GPIOA
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
reserved
Type
Reset
reserved
Type
Reset
RO
0
RO
0
UDMA
RO
0
reserved
Bit/Field
Name
Type
Reset
31:14
reserved
RO
0
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
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System Control
Bit/Field
Name
Type
Reset
13
UDMA
RO
0x0
Description
Micro-DMA Clock Gating Control
This bit controls the clock gating for micro-DMA. If set, the module
receives a clock and functions. Otherwise, the module is unclocked and
disabled. If the module is unclocked, a read or write to the module
generates a bus fault.
12:7
reserved
RO
0
6
GPIOG
RO
0x0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
Port G Clock Gating Control
This bit controls the clock gating for Port G. If set, the module receives
a clock and functions. Otherwise, the module is unclocked and disabled.
If the module is unclocked, a read or write to the module generates a
bus fault.
5
GPIOF
RO
0x0
Port F Clock Gating Control
This bit controls the clock gating for Port F. If set, the module receives
a clock and functions. Otherwise, the module is unclocked and disabled.
If the module is unclocked, a read or write to the module generates a
bus fault.
4
GPIOE
RO
0x0
Port E Clock Gating Control
Port E Clock Gating Control. This bit controls the clock gating for Port
E. If set, the module receives a clock and functions. Otherwise, the
module is unclocked and disabled. If the module is unclocked, a read
or write to the module generates a bus fault.
3
GPIOD
RO
0x0
Port D Clock Gating Control
Port D Clock Gating Control. This bit controls the clock gating for Port
D. If set, the module receives a clock and functions. Otherwise, the
module is unclocked and disabled. If the module is unclocked, a read
or write to the module generates a bus fault.
2
GPIOC
RO
0x0
Port C Clock Gating Control
This bit controls the clock gating for Port C. If set, the module receives
a clock and functions. Otherwise, the module is unclocked and disabled.
If the module is unclocked, a read or write to the module generates a
bus fault.
1
GPIOB
RO
0x0
Port B Clock Gating Control
This bit controls the clock gating for Port B. If set, the module receives
a clock and functions. Otherwise, the module is unclocked and disabled.
If the module is unclocked, a read or write to the module generates a
bus fault.
0
GPIOA
RO
0x0
Port A Clock Gating Control
This bit controls the clock gating for Port A. If set, the module receives
a clock and functions. Otherwise, the module is unclocked and disabled.
If the module is unclocked, a read or write to the module generates a
bus fault.
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Register 116: Sleep Mode Clock Gating Control Register 0 (SCGC0), offset
0x110
This register controls the clock gating logic in Sleep mode. Each bit controls a clock enable for a
given interface, function, or module. If set, the module receives a clock and functions. Otherwise,
the module is unclocked and disabled (saving power). If the module is unclocked, reads or writes
to the module generate a bus fault. The reset state of these bits is 0 (unclocked) unless otherwise
noted, so that all functional modules are disabled. It is the responsibility of software to enable the
ports necessary for the application. Note that these registers may contain more bits than there are
interfaces, functions, or modules to control. This configuration is implemented to assure reasonable
code compatibility with other family and future parts. RCGC0 is the clock configuration register for
running operation, SCGC0 for Sleep operation, and DCGC0 for Deep-Sleep operation. Setting the
ACG bit in the Run-Mode Clock Configuration (RCC) register specifies that the system uses sleep
modes.
Important: This register is provided for legacy software support only.
The peripheral-specific Sleep Mode Clock Gating Control registers (such as SCGCWD)
should be used to reset specific peripherals. A write to this legacy register also writes
the corresponding bit in the peripheral-specific register. Any bits that are changed by
writing to this register can be read back correctly with a read of this register. Software
must use the peripheral-specific registers to support modules that are not present in
the legacy registers. If software uses a peripheral-specific register to write a legacy
peripheral (such as Watchdog 1), the write causes proper operation, but the value of
that bit is not reflected in this register. If software uses both legacy and peripheral-specific
register accesses, the peripheral-specific registers must be accessed by
read-modify-write operations that affect only peripherals that are not present in the
legacy registers. In this manner, both the peripheral-specific and legacy registers have
coherent information.
Sleep Mode Clock Gating Control Register 0 (SCGC0)
Base 0x400F.E000
Offset 0x110
Type RO, reset 0x0000.0040
31
30
29
reserved
Type
Reset
28
27
26
WDT1
25
reserved
24
23
22
21
CAN0
19
18
reserved
17
16
ADC1
ADC0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
reserved
Type
Reset
20
reserved
RO
0
Bit/Field
Name
Type
Reset
31:29
reserved
RO
0
28
WDT1
RO
0x0
RO
1
reserved
RO
0
RO
0
WDT0
RO
0
reserved
RO
0
RO
0
RO
0
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
WDT1 Clock Gating Control
This bit controls the clock gating for Watchdog Timer module 1. If set,
the module receives a clock and functions. Otherwise, the module is
unclocked and disabled. If the module is unclocked, a read or write to
the module generates a bus fault.
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Bit/Field
Name
Type
Reset
27:25
reserved
RO
0
24
CAN0
RO
0x0
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
CAN0 Clock Gating Control
This bit controls the clock gating for CAN module 0. If set, the module
receives a clock and functions. Otherwise, the module is unclocked and
disabled. If the module is unclocked, a read or write to the module
generates a bus fault.
23:18
reserved
RO
0
17
ADC1
RO
0x0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
ADC1 Clock Gating Control
This bit controls the clock gating for ADC module 1. If set, the module
receives a clock and functions. Otherwise, the module is unclocked and
disabled. If the module is unclocked, a read or write to the module
generates a bus fault.
16
ADC0
RO
0x0
ADC0 Clock Gating Control
This bit controls the clock gating for ADC module 0. If set, the module
receives a clock and functions. Otherwise, the module is unclocked and
disabled. If the module is unclocked, a read or write to the module
generates a bus fault.
15:7
reserved
RO
0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
6
reserved
RO
0x1
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
5:4
reserved
RO
0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
3
WDT0
RO
0x0
WDT0 Clock Gating Control
This bit controls the clock gating for the Watchdog Timer module 0. If
set, the module receives a clock and functions. Otherwise, the module
is unclocked and disabled. If the module is unclocked, a read or write
to the module generates a bus fault.
2:0
reserved
RO
0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
422
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Tiva™ TM4C1230C3PM Microcontroller
Register 117: Sleep Mode Clock Gating Control Register 1 (SCGC1), offset
0x114
This register controls the clock gating logic in Sleep mode. Each bit controls a clock enable for a
given interface, function, or module. If set, the module receives a clock and functions. Otherwise,
the module is unclocked and disabled (saving power). If the module is unclocked, reads or writes
to the module generate a bus fault. The reset state of these bits is 0 (unclocked) unless otherwise
noted, so that all functional modules are disabled. It is the responsibility of software to enable the
ports necessary for the application. Note that these registers may contain more bits than there are
interfaces, functions, or modules to control. This configuration is implemented to assure reasonable
code compatibility with other family and future parts. RCGC1 is the clock configuration register for
running operation, SCGC1 for Sleep operation, and DCGC1 for Deep-Sleep operation. Setting the
ACG bit in the Run-Mode Clock Configuration (RCC) register specifies that the system uses sleep
modes.
Important: This register is provided for legacy software support only.
The peripheral-specific Sleep Mode Clock Gating Control registers (such as
SCGCTIMER) should be used to reset specific peripherals. A write to this legacy register
also writes the corresponding bit in the peripheral-specific register. Any bits that are
changed by writing to this register can be read back correctly with a read of this register.
Software must use the peripheral-specific registers to support modules that are not
present in the legacy registers. If software uses a peripheral-specific register to write a
legacy peripheral (such as Timer 0), the write causes proper operation, but the value
of that bit is not reflected in this register. If software uses both legacy and
peripheral-specific register accesses, the peripheral-specific registers must be accessed
by read-modify-write operations that affect only peripherals that are not present in the
legacy registers. In this manner, both the peripheral-specific and legacy registers have
coherent information.
Sleep Mode Clock Gating Control Register 1 (SCGC1)
Base 0x400F.E000
Offset 0x114
Type RO, reset 0x0000.0000
31
30
29
RO
0
RO
0
RO
0
15
14
reserved
RO
0
28
27
26
25
24
RO
0
RO
0
RO
0
COMP1
COMP0
RO
0
13
12
11
10
9
I2C1
reserved
I2C0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
reserved
Type
Reset
Type
Reset
23
22
RO
0
RO
0
RO
0
Name
Type
Reset
31:26
reserved
RO
0
25
COMP1
RO
0x0
20
19
18
17
16
RO
0
RO
0
TIMER3
TIMER2
TIMER1
TIMER0
RO
0
RO
0
RO
0
RO
0
8
7
6
5
4
3
2
1
0
RO
0
RO
0
RO
0
SSI1
SSI0
reserved
UART2
UART1
UART0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
reserved
reserved
Bit/Field
21
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
Analog Comparator 1 Clock Gating
This bit controls the clock gating for analog comparator 1. If set, the
module receives a clock and functions. Otherwise, the module is
unclocked and disabled. If the module is unclocked, a read or write to
the module generates a bus fault.
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Bit/Field
Name
Type
Reset
24
COMP0
RO
0x0
Description
Analog Comparator 0 Clock Gating
This bit controls the clock gating for analog comparator 0. If set, the
module receives a clock and functions. Otherwise, the module is
unclocked and disabled. If the module is unclocked, a read or write to
the module generates a bus fault.
23:20
reserved
RO
0
19
TIMER3
RO
0x0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
Timer 3 Clock Gating Control
This bit controls the clock gating for General-Purpose Timer module 3.
If set, the module receives a clock and functions. Otherwise, the module
is unclocked and disabled. If the module is unclocked, a read or write
to the module generates a bus fault.
18
TIMER2
RO
0x0
Timer 2 Clock Gating Control
This bit controls the clock gating for General-Purpose Timer module 2.
If set, the module receives a clock and functions. Otherwise, the module
is unclocked and disabled. If the module is unclocked, a read or write
to the module generates a bus fault.
17
TIMER1
RO
0x0
Timer 1 Clock Gating Control
This bit controls the clock gating for General-Purpose Timer module 1.
If set, the module receives a clock and functions. Otherwise, the module
is unclocked and disabled. If the module is unclocked, a read or write
to the module generates a bus fault.
16
TIMER0
RO
0x0
Timer 0 Clock Gating Control
This bit controls the clock gating for General-Purpose Timer module 0.
If set, the module receives a clock and functions. Otherwise, the module
is unclocked and disabled. If the module is unclocked, a read or write
to the module generates a bus fault.
15
reserved
RO
0
14
I2C1
RO
0x0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
I2C1 Clock Gating Control
This bit controls the clock gating for I2C module 1. If set, the module
receives a clock and functions. Otherwise, the module is unclocked and
disabled. If the module is unclocked, a read or write to the module
generates a bus fault.
13
reserved
RO
0
12
I2C0
RO
0x0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
I2C0 Clock Gating Control
This bit controls the clock gating for I2C module 0. If set, the module
receives a clock and functions. Otherwise, the module is unclocked and
disabled. If the module is unclocked, a read or write to the module
generates a bus fault.
11:6
reserved
RO
0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
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Bit/Field
Name
Type
Reset
5
SSI1
RO
0x0
Description
SSI1 Clock Gating Control
This bit controls the clock gating for SSI module 1. If set, the module
receives a clock and functions. Otherwise, the module is unclocked and
disabled. If the module is unclocked, a read or write to the module
generates a bus fault.
4
SSI0
RO
0x0
SSI0 Clock Gating Control
This bit controls the clock gating for SSI module 0. If set, the module
receives a clock and functions. Otherwise, the module is unclocked and
disabled. If the module is unclocked, a read or write to the module
generates a bus fault.
3
reserved
RO
0
2
UART2
RO
0x0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
UART2 Clock Gating Control
This bit controls the clock gating for UART module 2. If set, the module
receives a clock and functions. Otherwise, the module is unclocked and
disabled. If the module is unclocked, a read or write to the module
generates a bus fault.
1
UART1
RO
0x0
UART1 Clock Gating Control
This bit controls the clock gating for UART module 1. If set, the module
receives a clock and functions. Otherwise, the module is unclocked and
disabled. If the module is unclocked, a read or write to the module
generates a bus fault.
0
UART0
RO
0x0
UART0 Clock Gating Control
This bit controls the clock gating for UART module 0. If set, the module
receives a clock and functions. Otherwise, the module is unclocked and
disabled. If the module is unclocked, a read or write to the module
generates a bus fault.
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System Control
Register 118: Sleep Mode Clock Gating Control Register 2 (SCGC2), offset
0x118
This register controls the clock gating logic in Sleep mode. Each bit controls a clock enable for a
given interface, function, or module. If set, the module receives a clock and functions. Otherwise,
the module is unclocked and disabled (saving power). If the module is unclocked, reads or writes
to the module generate a bus fault. The reset state of these bits is 0 (unclocked) unless otherwise
noted, so that all functional modules are disabled. It is the responsibility of software to enable the
ports necessary for the application. Note that these registers may contain more bits than there are
interfaces, functions, or modules to control. This configuration is implemented to assure reasonable
code compatibility with other family and future parts. RCGC2 is the clock configuration register for
running operation, SCGC2 for Sleep operation, and DCGC2 for Deep-Sleep operation. Setting the
ACG bit in the Run-Mode Clock Configuration (RCC) register specifies that the system uses sleep
modes.
Important: This register is provided for legacy software support only.
The peripheral-specific Sleep Mode Clock Gating Control registers (such as SCGCDMA)
should be used to reset specific peripherals. A write to this legacy register also writes
the corresponding bit in the peripheral-specific register. Any bits that are changed by
writing to this register can be read back correctly with a read of this register. Software
must use the peripheral-specific registers to support modules that are not present in
the legacy registers. If software uses a peripheral-specific register to write a legacy
peripheral (such as the μDMA), the write causes proper operation, but the value of that
bit is not reflected in this register. If software uses both legacy and peripheral-specific
register accesses, the peripheral-specific registers must be accessed by
read-modify-write operations that affect only peripherals that are not present in the
legacy registers. In this manner, both the peripheral-specific and legacy registers have
coherent information.
Sleep Mode Clock Gating Control Register 2 (SCGC2)
Base 0x400F.E000
Offset 0x118
Type RO, reset 0x0000.0000
31
30
29
28
27
26
25
24
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
RO
0
RO
0
RO
0
RO
0
23
22
21
20
19
18
17
16
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
8
7
6
5
4
3
2
1
0
GPIOG
GPIOF
GPIOE
GPIOD
GPIOC
GPIOB
GPIOA
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
reserved
Type
Reset
reserved
Type
Reset
RO
0
RO
0
UDMA
RO
0
reserved
Bit/Field
Name
Type
Reset
31:14
reserved
RO
0
13
UDMA
RO
0x0
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
Micro-DMA Clock Gating Control
This bit controls the clock gating for micro-DMA. If set, the module
receives a clock and functions. Otherwise, the module is unclocked and
disabled. If the module is unclocked, a read or write to the module
generates a bus fault.
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Bit/Field
Name
Type
Reset
12:7
reserved
RO
0
6
GPIOG
RO
0x0
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
Port G Clock Gating Control
This bit controls the clock gating for Port G. If set, the module receives
a clock and functions. Otherwise, the module is unclocked and disabled.
If the module is unclocked, a read or write to the module generates a
bus fault.
5
GPIOF
RO
0x0
Port F Clock Gating Control
This bit controls the clock gating for Port F. If set, the module receives
a clock and functions. Otherwise, the module is unclocked and disabled.
If the module is unclocked, a read or write to the module generates a
bus fault.
4
GPIOE
RO
0x0
Port E Clock Gating Control
Port E Clock Gating Control. This bit controls the clock gating for Port
E. If set, the module receives a clock and functions. Otherwise, the
module is unclocked and disabled. If the module is unclocked, a read
or write to the module generates a bus fault.
3
GPIOD
RO
0x0
Port D Clock Gating Control
Port D Clock Gating Control. This bit controls the clock gating for Port
D. If set, the module receives a clock and functions. Otherwise, the
module is unclocked and disabled. If the module is unclocked, a read
or write to the module generates a bus fault.
2
GPIOC
RO
0x0
Port C Clock Gating Control
This bit controls the clock gating for Port C. If set, the module receives
a clock and functions. Otherwise, the module is unclocked and disabled.
If the module is unclocked, a read or write to the module generates a
bus fault.
1
GPIOB
RO
0x0
Port B Clock Gating Control
This bit controls the clock gating for Port B. If set, the module receives
a clock and functions. Otherwise, the module is unclocked and disabled.
If the module is unclocked, a read or write to the module generates a
bus fault.
0
GPIOA
RO
0x0
Port A Clock Gating Control
This bit controls the clock gating for Port A. If set, the module receives
a clock and functions. Otherwise, the module is unclocked and disabled.
If the module is unclocked, a read or write to the module generates a
bus fault.
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System Control
Register 119: Deep Sleep Mode Clock Gating Control Register 0 (DCGC0),
offset 0x120
This register controls the clock gating logic in Deep-Sleep mode. Each bit controls a clock enable
for a given interface, function, or module. If set, the module receives a clock and functions. Otherwise,
the module is unclocked and disabled (saving power). If the module is unclocked, reads or writes
to the module generate a bus fault. The reset state of these bits is 0 (unclocked) unless otherwise
noted, so that all functional modules are disabled. It is the responsibility of software to enable the
ports necessary for the application. Note that these registers may contain more bits than there are
interfaces, functions, or modules to control. This configuration is implemented to assure reasonable
code compatibility with other family and future parts. RCGC0 is the clock configuration register for
running operation, SCGC0 for Sleep operation, and DCGC0 for Deep-Sleep operation. Setting the
ACG bit in the Run-Mode Clock Configuration (RCC) register specifies that the system uses sleep
modes.
Important: This register is provided for legacy software support only.
The peripheral-specific Deep Sleep Mode Clock Gating Control registers (such as
DCGCWD) should be used to reset specific peripherals. A write to this legacy register
also writes the corresponding bit in the peripheral-specific register. Any bits that are
changed by writing to this register can be read back correctly with a read of this register.
Software must use the peripheral-specific registers to support modules that are not
present in the legacy registers. If software uses a peripheral-specific register to write a
legacy peripheral (such as Watchdog 1), the write causes proper operation, but the
value of that bit is not reflected in this register. If software uses both legacy and
peripheral-specific register accesses, the peripheral-specific registers must be accessed
by read-modify-write operations that affect only peripherals that are not present in the
legacy registers. In this manner, both the peripheral-specific and legacy registers have
coherent information.
Deep Sleep Mode Clock Gating Control Register 0 (DCGC0)
Base 0x400F.E000
Offset 0x120
Type RO, reset 0x0000.0040
31
30
29
reserved
Type
Reset
28
27
26
WDT1
25
reserved
24
23
22
21
CAN0
19
18
reserved
17
16
ADC1
ADC0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
reserved
Type
Reset
20
reserved
RO
0
Bit/Field
Name
Type
Reset
31:29
reserved
RO
0
28
WDT1
RO
0x0
RO
1
reserved
RO
0
RO
0
WDT0
RO
0
reserved
RO
0
RO
0
RO
0
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
WDT1 Clock Gating Control
This bit controls the clock gating for the Watchdog Timer module 1. If
set, the module receives a clock and functions. Otherwise, the module
is unclocked and disabled. If the module is unclocked, a read or write
to the module generates a bus fault.
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Bit/Field
Name
Type
Reset
27:25
reserved
RO
0
24
CAN0
RO
0x0
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
CAN0 Clock Gating Control
This bit controls the clock gating for CAN module 0. If set, the module
receives a clock and functions. Otherwise, the module is unclocked and
disabled. If the module is unclocked, a read or write to the module
generates a bus fault.
23:18
reserved
RO
0
17
ADC1
RO
0x0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
ADC1 Clock Gating Control
This bit controls the clock gating for ADC module 1. If set, the module
receives a clock and functions. Otherwise, the module is unclocked and
disabled. If the module is unclocked, a read or write to the module
generates a bus fault.
16
ADC0
RO
0x0
ADC0 Clock Gating Control
This bit controls the clock gating for ADC module 0. If set, the module
receives a clock and functions. Otherwise, the module is unclocked and
disabled. If the module is unclocked, a read or write to the module
generates a bus fault.
15:7
reserved
RO
0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
6
reserved
RO
0x1
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
5:4
reserved
RO
0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
3
WDT0
RO
0x0
WDT0 Clock Gating Control
This bit controls the clock gating for the Watchdog Timer module 0. If
set, the module receives a clock and functions. Otherwise, the module
is unclocked and disabled. If the module is unclocked, a read or write
to the module generates a bus fault.
2:0
reserved
RO
0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
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System Control
Register 120: Deep-Sleep Mode Clock Gating Control Register 1 (DCGC1),
offset 0x124
This register controls the clock gating logic in Deep-Sleep mode. Each bit controls a clock enable
for a given interface, function, or module. If set, the module receives a clock and functions. Otherwise,
the module is unclocked and disabled (saving power). If the module is unclocked, reads or writes
to the module generate a bus fault. The reset state of these bits is 0 (unclocked) unless otherwise
noted, so that all functional modules are disabled. It is the responsibility of software to enable the
ports necessary for the application. Note that these registers may contain more bits than there are
interfaces, functions, or modules to control. This configuration is implemented to assure reasonable
code compatibility with other family and future parts. RCGC1 is the clock configuration register for
running operation, SCGC1 for Sleep operation, and DCGC1 for Deep-Sleep operation. Setting the
ACG bit in the Run-Mode Clock Configuration (RCC) register specifies that the system uses sleep
modes.
Important: This register is provided for legacy software support only.
The peripheral-specific Deep Sleep Mode Clock Gating Control registers (such as
DCGCTIMER) should be used to reset specific peripherals. A write to this legacy register
also writes the corresponding bit in the peripheral-specific register. Any bits that are
changed by writing to this register can be read back correctly with a read of this register.
Software must use the peripheral-specific registers to support modules that are not
present in the legacy registers. If software uses a peripheral-specific register to write a
legacy peripheral (such as Timer 0), the write causes proper operation, but the value
of that bit is not reflected in this register. If software uses both legacy and
peripheral-specific register accesses, the peripheral-specific registers must be accessed
by read-modify-write operations that affect only peripherals that are not present in the
legacy registers. In this manner, both the peripheral-specific and legacy registers have
coherent information.
Deep-Sleep Mode Clock Gating Control Register 1 (DCGC1)
Base 0x400F.E000
Offset 0x124
Type RO, reset 0x0000.0000
31
30
29
RO
0
RO
0
RO
0
15
14
reserved
RO
0
28
27
26
25
24
RO
0
RO
0
RO
0
COMP1
COMP0
RO
0
13
12
11
10
9
I2C1
reserved
I2C0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
reserved
Type
Reset
Type
Reset
23
22
RO
0
RO
0
RO
0
Name
Type
Reset
31:26
reserved
RO
0
25
COMP1
RO
0x0
20
19
18
17
16
RO
0
RO
0
TIMER3
TIMER2
TIMER1
TIMER0
RO
0
RO
0
RO
0
RO
0
8
7
6
5
4
3
2
1
0
RO
0
RO
0
RO
0
SSI1
SSI0
reserved
UART2
UART1
UART0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
reserved
reserved
Bit/Field
21
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
Analog Comparator 1 Clock Gating
This bit controls the clock gating for analog comparator 1. If set, the
module receives a clock and functions. Otherwise, the module is
unclocked and disabled. If the module is unclocked, a read or write to
the module generates a bus fault.
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Texas Instruments-Production Data
Tiva™ TM4C1230C3PM Microcontroller
Bit/Field
Name
Type
Reset
24
COMP0
RO
0x0
Description
Analog Comparator 0 Clock Gating
This bit controls the clock gating for analog comparator 0. If set, the
module receives a clock and functions. Otherwise, the module is
unclocked and disabled. If the module is unclocked, a read or write to
the module generates a bus fault.
23:20
reserved
RO
0
19
TIMER3
RO
0x0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
Timer 3 Clock Gating Control
This bit controls the clock gating for General-Purpose Timer module 3.
If set, the module receives a clock and functions. Otherwise, the module
is unclocked and disabled. If the module is unclocked, a read or write
to the module generates a bus fault.
18
TIMER2
RO
0x0
Timer 2 Clock Gating Control
This bit controls the clock gating for General-Purpose Timer module 2.
If set, the module receives a clock and functions. Otherwise, the module
is unclocked and disabled. If the module is unclocked, a read or write
to the module generates a bus fault.
17
TIMER1
RO
0x0
Timer 1 Clock Gating Control
This bit controls the clock gating for General-Purpose Timer module 1.
If set, the module receives a clock and functions. Otherwise, the module
is unclocked and disabled. If the module is unclocked, a read or write
to the module generates a bus fault.
16
TIMER0
RO
0x0
Timer 0 Clock Gating Control
This bit controls the clock gating for General-Purpose Timer module 0.
If set, the module receives a clock and functions. Otherwise, the module
is unclocked and disabled. If the module is unclocked, a read or write
to the module generates a bus fault.
15
reserved
RO
0
14
I2C1
RO
0x0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
I2C1 Clock Gating Control
This bit controls the clock gating for I2C module 1. If set, the module
receives a clock and functions. Otherwise, the module is unclocked and
disabled. If the module is unclocked, a read or write to the module
generates a bus fault.
13
reserved
RO
0
12
I2C0
RO
0x0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
I2C0 Clock Gating Control
This bit controls the clock gating for I2C module 0. If set, the module
receives a clock and functions. Otherwise, the module is unclocked and
disabled. If the module is unclocked, a read or write to the module
generates a bus fault.
11:6
reserved
RO
0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
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System Control
Bit/Field
Name
Type
Reset
5
SSI1
RO
0x0
Description
SSI1 Clock Gating Control
This bit controls the clock gating for SSI module 1. If set, the module
receives a clock and functions. Otherwise, the module is unclocked and
disabled. If the module is unclocked, a read or write to the module
generates a bus fault.
4
SSI0
RO
0x0
SSI0 Clock Gating Control
This bit controls the clock gating for SSI module 0. If set, the module
receives a clock and functions. Otherwise, the module is unclocked and
disabled. If the module is unclocked, a read or write to the module
generates a bus fault.
3
reserved
RO
0
2
UART2
RO
0x0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
UART2 Clock Gating Control
This bit controls the clock gating for UART module 2. If set, the module
receives a clock and functions. Otherwise, the module is unclocked and
disabled. If the module is unclocked, a read or write to the module
generates a bus fault.
1
UART1
RO
0x0
UART1 Clock Gating Control
This bit controls the clock gating for UART module 1. If set, the module
receives a clock and functions. Otherwise, the module is unclocked and
disabled. If the module is unclocked, a read or write to the module
generates a bus fault.
0
UART0
RO
0x0
UART0 Clock Gating Control
This bit controls the clock gating for UART module 0. If set, the module
receives a clock and functions. Otherwise, the module is unclocked and
disabled. If the module is unclocked, a read or write to the module
generates a bus fault.
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Texas Instruments-Production Data
Tiva™ TM4C1230C3PM Microcontroller
Register 121: Deep Sleep Mode Clock Gating Control Register 2 (DCGC2),
offset 0x128
This register controls the clock gating logic in Deep-Sleep mode. Each bit controls a clock enable
for a given interface, function, or module. If set, the module receives a clock and functions. Otherwise,
the module is unclocked and disabled (saving power). If the module is unclocked, reads or writes
to the module generate a bus fault. The reset state of these bits is 0 (unclocked) unless otherwise
noted, so that all functional modules are disabled. It is the responsibility of software to enable the
ports necessary for the application. Note that these registers may contain more bits than there are
interfaces, functions, or modules to control. This configuration is implemented to assure reasonable
code compatibility with other family and future parts. RCGC2 is the clock configuration register for
running operation, SCGC2 for Sleep operation, and DCGC2 for Deep-Sleep operation. Setting the
ACG bit in the Run-Mode Clock Configuration (RCC) register specifies that the system uses sleep
modes.
Important: This register is provided for legacy software support only.
The peripheral-specific Deep Sleep Mode Clock Gating Control registers (such as
DCGCDMA) should be used to reset specific peripherals. A write to this legacy register
also writes the corresponding bit in the peripheral-specific register. Any bits that are
changed by writing to this register can be read back correctly with a read of this register.
Software must use the peripheral-specific registers to support modules that are not
present in the legacy registers. If software uses a peripheral-specific register to write a
legacy peripheral (such as the μDMA), the write causes proper operation, but the value
of that bit is not reflected in this register. If software uses both legacy and
peripheral-specific register accesses, the peripheral-specific registers must be accessed
by read-modify-write operations that affect only peripherals that are not present in the
legacy registers. In this manner, both the peripheral-specific and legacy registers have
coherent information.
Deep Sleep Mode Clock Gating Control Register 2 (DCGC2)
Base 0x400F.E000
Offset 0x128
Type RO, reset 0x0000.0000
31
30
29
28
27
26
25
24
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
RO
0
RO
0
RO
0
RO
0
23
22
21
20
19
18
17
16
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
8
7
6
5
4
3
2
1
0
GPIOG
GPIOF
GPIOE
GPIOD
GPIOC
GPIOB
GPIOA
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
reserved
Type
Reset
reserved
Type
Reset
RO
0
RO
0
UDMA
RO
0
reserved
Bit/Field
Name
Type
Reset
31:14
reserved
RO
0
13
UDMA
RO
0x0
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
Micro-DMA Clock Gating Control
This bit controls the clock gating for micro-DMA. If set, the module
receives a clock and functions. Otherwise, the module is unclocked and
disabled. If the module is unclocked, a read or write to the module
generates a bus fault.
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System Control
Bit/Field
Name
Type
Reset
12:7
reserved
RO
0
6
GPIOG
RO
0x0
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
Port G Clock Gating Control
This bit controls the clock gating for Port G. If set, the module receives
a clock and functions. Otherwise, the module is unclocked and disabled.
If the module is unclocked, a read or write to the module generates a
bus fault.
5
GPIOF
RO
0x0
Port F Clock Gating Control
This bit controls the clock gating for Port F. If set, the module receives
a clock and functions. Otherwise, the module is unclocked and disabled.
If the module is unclocked, a read or write to the module generates a
bus fault.
4
GPIOE
RO
0x0
Port E Clock Gating Control
Port E Clock Gating Control. This bit controls the clock gating for Port
E. If set, the module receives a clock and functions. Otherwise, the
module is unclocked and disabled. If the module is unclocked, a read
or write to the module generates a bus fault.
3
GPIOD
RO
0x0
Port D Clock Gating Control
Port D Clock Gating Control. This bit controls the clock gating for Port
D. If set, the module receives a clock and functions. Otherwise, the
module is unclocked and disabled. If the module is unclocked, a read
or write to the module generates a bus fault.
2
GPIOC
RO
0x0
Port C Clock Gating Control
This bit controls the clock gating for Port C. If set, the module receives
a clock and functions. Otherwise, the module is unclocked and disabled.
If the module is unclocked, a read or write to the module generates a
bus fault.
1
GPIOB
RO
0x0
Port B Clock Gating Control
This bit controls the clock gating for Port B. If set, the module receives
a clock and functions. Otherwise, the module is unclocked and disabled.
If the module is unclocked, a read or write to the module generates a
bus fault.
0
GPIOA
RO
0x0
Port A Clock Gating Control
This bit controls the clock gating for Port A. If set, the module receives
a clock and functions. Otherwise, the module is unclocked and disabled.
If the module is unclocked, a read or write to the module generates a
bus fault.
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Texas Instruments-Production Data
Tiva™ TM4C1230C3PM Microcontroller
Register 122: Device Capabilities 9 (DC9), offset 0x190
This register is predefined by the part and can be used to verify ADC digital comparator features.
Important: This register is provided for legacy software support only.
The ADC Peripheral Properties (ADCPP) register should be used to determine how
many digital comparators are available on the ADC module. A read of this register
correctly identifies if legacy comparators are present. Software must use the ADCPP
register to determine if a comparator that is not supported by the DCn registers is
present.
Device Capabilities 9 (DC9)
Base 0x400F.E000
Offset 0x190
Type RO, reset 0x00FF.00FF
31
30
29
28
27
26
25
24
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
8
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
23
22
21
20
19
18
17
16
ADC1DC7 ADC1DC6 ADC1DC5 ADC1DC4 ADC1DC3 ADC1DC2 ADC1DC1 ADC1DC0
RO
1
RO
1
RO
1
RO
1
RO
1
RO
1
RO
1
RO
1
7
6
5
4
3
2
1
0
ADC0DC7 ADC0DC6 ADC0DC5 ADC0DC4 ADC0DC3 ADC0DC2 ADC0DC1 ADC0DC0
RO
0
RO
0
RO
0
Bit/Field
Name
Type
Reset
31:24
reserved
RO
0
23
ADC1DC7
RO
0x1
RO
0
RO
1
RO
1
RO
1
RO
1
RO
1
RO
1
RO
1
RO
1
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
ADC1 DC7 Present
When set, indicates that ADC module 1 Digital Comparator 7 is present.
22
ADC1DC6
RO
0x1
ADC1 DC6 Present
When set, indicates that ADC module 1 Digital Comparator 6 is present.
21
ADC1DC5
RO
0x1
ADC1 DC5 Present
When set, indicates that ADC module 1 Digital Comparator 5 is present.
20
ADC1DC4
RO
0x1
ADC1 DC4 Present
When set, indicates that ADC module 1 Digital Comparator 4 is present.
19
ADC1DC3
RO
0x1
ADC1 DC3 Present
When set, indicates that ADC module 1 Digital Comparator 3 is present.
18
ADC1DC2
RO
0x1
ADC1 DC2 Present
When set, indicates that ADC module 1 Digital Comparator 2 is present.
17
ADC1DC1
RO
0x1
ADC1 DC1 Present
When set, indicates that ADC module 1 Digital Comparator 1 is present.
16
ADC1DC0
RO
0x1
ADC1 DC0 Present
When set, indicates that ADC module 1 Digital Comparator 0 is present.
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System Control
Bit/Field
Name
Type
Reset
15:8
reserved
RO
0
7
ADC0DC7
RO
0x1
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
ADC0 DC7 Present
When set, indicates that ADC module 0 Digital Comparator 7 is present.
6
ADC0DC6
RO
0x1
ADC0 DC6 Present
When set, indicates that ADC module 0 Digital Comparator 6 is present.
5
ADC0DC5
RO
0x1
ADC0 DC5 Present
When set, indicates that ADC module 0 Digital Comparator 5 is present.
4
ADC0DC4
RO
0x1
ADC0 DC4 Present
When set, indicates that ADC module 0 Digital Comparator 4 is present.
3
ADC0DC3
RO
0x1
ADC0 DC3 Present
When set, indicates that ADC module 0 Digital Comparator 3 is present.
2
ADC0DC2
RO
0x1
ADC0 DC2 Present
When set, indicates that ADC module 0 Digital Comparator 2 is present.
1
ADC0DC1
RO
0x1
ADC0 DC1 Present
When set, indicates that ADC module 0 Digital Comparator 1 is present.
0
ADC0DC0
RO
0x1
ADC0 DC0 Present
When set, indicates that ADC module 0 Digital Comparator 0 is present.
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Tiva™ TM4C1230C3PM Microcontroller
Register 123: Non-Volatile Memory Information (NVMSTAT), offset 0x1A0
This register is predefined by the part and can be used to verify features.
Important: This register is provided for legacy software support only.
The ROM Third-Party Software (ROMSWMAP) register should be used to determine
the presence of third-party software in the on-chip ROM on this microcontroller. A read
of the TPSW bit in this register correctly identifies the presence of legacy third-party
software. Software should use the ROMSWMAP register for software that is not on
legacy devices.
Non-Volatile Memory Information (NVMSTAT)
Base 0x400F.E000
Offset 0x1A0
Type RO, reset 0x0000.0001
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
RO
0
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
8
7
6
5
4
3
2
1
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
Bit/Field
Name
Type
Reset
31:1
reserved
RO
0
0
FWB
RO
0x1
RO
0
0
FWB
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
1
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
32 Word Flash Write Buffer Available
When set, indicates that the 32 word Flash memory write buffer feature
is available.
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Texas Instruments-Production Data
System Exception Module
6
System Exception Module
This module is an AHB peripheral that handles system-level Cortex-M4 FPU exceptions. For functions
with registers mapped into this aperture, if the function is not available on a device, then all writes
to the associated registers are ignored and reads return zeros.
6.1
Functional Description
The System Exception module provides control and status of the system-level interrupts. All the
interrupt events are ORed together before being sent to the interrupt controller, so the System
Exception module can only generate a single interrupt request to the controller at any given time.
Software can service multiple interrupt events in a single interrupt service routine by reading the
System Exception Masked Interrupt Status (SYSEXCMIS) register. The interrupt events that can
trigger a controller-level interrupt are defined in the System Exception Interrupt Mask (SYSEXCIM)
register by setting the corresponding interrupt mask bits. If interrupts are not used, the raw interrupt
status is always visible via the System Exception Raw Interrupt Status (SYSEXCRIS) register.
Interrupts are always cleared (for both the SYSEXCMIS and SYSEXCRIS registers) by writing a 1
to the corresponding bit in the System Exception Interrupt Clear (SYSEXCIC) register.
6.2
Register Map
Table 6-1 on page 438 lists the System Exception module registers. The offset listed is a hexadecimal
increment to the register's address, relative to the System Exception base address of 0x400F.9000.
Note:
Spaces in the System Exception register space that are not used are reserved for future or
internal use. Software should not modify any reserved memory address.
Table 6-1. System Exception Register Map
Offset
Name
0x000
See
page
Type
Reset
SYSEXCRIS
RO
0x0000.0000
System Exception Raw Interrupt Status
439
0x004
SYSEXCIM
RW
0x0000.0000
System Exception Interrupt Mask
441
0x008
SYSEXCMIS
RO
0x0000.0000
System Exception Masked Interrupt Status
443
0x00C
SYSEXCIC
W1C
0x0000.0000
System Exception Interrupt Clear
445
6.3
Description
Register Descriptions
All addresses given are relative to the System Exception base address of 0x400F.9000.
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Texas Instruments-Production Data
Tiva™ TM4C1230C3PM Microcontroller
Register 1: System Exception Raw Interrupt Status (SYSEXCRIS), offset 0x000
The SYSEXCRIS register is the raw interrupt status register. On a read, this register gives the
current raw status value of the corresponding interrupt. A write has no effect.
System Exception Raw Interrupt Status (SYSEXCRIS)
Base 0x400F.9000
Offset 0x000
Type RO, reset 0x0000.0000
31
30
29
28
27
26
25
24
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
23
22
21
20
19
18
17
16
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
8
7
6
5
4
3
2
1
0
FPIOCRIS
FPDZCRIS
FPIDCRIS
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
reserved
Type
Reset
reserved
Type
Reset
RO
0
FPIXCRIS
Bit/Field
Name
Type
Reset
31:6
reserved
RO
0x0000.00
5
FPIXCRIS
RO
0
RO
0
FPOFCRIS FPUFCRIS
RO
0
RO
0
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
Floating-Point Inexact Exception Raw Interrupt Status
Value Description
0
No interrupt
1
A floating-point inexact exception has occurred.
This bit is cleared by writing a 1 to the IXCIC bit in the SYSEXCIC
register.
4
FPOFCRIS
RO
0
Floating-Point Overflow Exception Raw Interrupt Status
Value Description
0
No interrupt
1
A floating-point overflow exception has occurred.
This bit is cleared by writing a 1 to the OFCIC bit in the SYSEXCIC
register.
3
FPUFCRIS
RO
0
Floating-Point Underflow Exception Raw Interrupt Status
Value Description
0
No interrupt
1
A floating-point underflow exception has occurred.
This bit is cleared by writing a 1 to the UFCIC bit in the SYSEXCIC
register.
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Texas Instruments-Production Data
System Exception Module
Bit/Field
Name
Type
Reset
2
FPIOCRIS
RO
0
Description
Floating-Point Invalid Operation Raw Interrupt Status
Value Description
0
No interrupt
1
A floating-point invalid operation exception has occurred.
This bit is cleared by writing a 1 to the IOCIC bit in the SYSEXCIC
register.
1
FPDZCRIS
RO
0
Floating-Point Divide By 0 Exception Raw Interrupt Status
Value Description
0
No interrupt
1
A floating-point divide by 0 exception has occurred.
This bit is cleared by writing a 1 to the DZCIC bit in the SYSEXCIC
register.
0
FPIDCRIS
RO
0
Floating-Point Input Denormal Exception Raw Interrupt Status
Value Description
0
No interrupt
1
A floating-point input denormal exception has occurred.
This bit is cleared by writing a 1 to the IDCIC bit in the SYSEXCIC
register.
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Texas Instruments-Production Data
Tiva™ TM4C1230C3PM Microcontroller
Register 2: System Exception Interrupt Mask (SYSEXCIM), offset 0x004
The SYSEXCIM register is the interrupt mask set/clear register.
On a read, this register gives the current value of the mask on the relevant interrupt. Setting a bit
allows the corresponding raw interrupt signal to be routed to the interrupt controller. Clearing a bit
prevents the raw interrupt signal from being sent to the interrupt controller.
System Exception Interrupt Mask (SYSEXCIM)
Base 0x400F.9000
Offset 0x004
Type RW, reset 0x0000.0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
5
4
3
2
1
0
reserved
Type
Reset
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
15
14
13
12
11
10
9
8
7
6
reserved
Type
Reset
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
FPIXCIM FPOFCIM FPUFCIM FPIOCIM FPDZCIM FPIDCIM
RW
0
Bit/Field
Name
Type
Reset
31:6
reserved
RW
0x0000.00
5
FPIXCIM
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
Floating-Point Inexact Exception Interrupt Mask
Value Description
4
FPOFCIM
RW
0
0
The FPIXCRIS interrupt is suppressed and not sent to the
interrupt controller.
1
An interrupt is sent to the interrupt controller when the
FPISCRIS bit in the SYSEXCRIS register is set.
Floating-Point Overflow Exception Interrupt Mask
Value Description
3
FPUFCIM
RW
0
0
The FPOFCIS interrupt is suppressed and not sent to the
interrupt controller.
1
An interrupt is sent to the interrupt controller when the
FPOFCRIS bit in the SYSEXCRIS register is set.
Floating-Point Underflow Exception Interrupt Mask
Value Description
0
The FPUFCRIS interrupt is suppressed and not sent to the
interrupt controller.
1
An interrupt is sent to the interrupt controller when the
FPUFCRIS bit in the SYSEXCRIS register is set.
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Bit/Field
Name
Type
Reset
2
FPIOCIM
RW
0
Description
Floating-Point Invalid Operation Interrupt Mask
Value Description
1
FPDZCIM
RW
0
0
The FPIOCRIS interrupt is suppressed and not sent to the
interrupt controller.
1
An interrupt is sent to the interrupt controller when the
FPIOCRIS bit in the SYSEXCRIS register is set.
Floating-Point Divide By 0 Exception Interrupt Mask
Value Description
0
FPIDCIM
RW
0
0
The FPDZCRIS interrupt is suppressed and not sent to the
interrupt controller.
1
An interrupt is sent to the interrupt controller when the
FPDZCRIS bit in the SYSEXCRIS register is set.
Floating-Point Input Denormal Exception Interrupt Mask
Value Description
0
The FPIDCRIS interrupt is suppressed and not sent to the
interrupt controller.
1
An interrupt is sent to the interrupt controller when the
FPIDCRIS bit in the SYSEXCRIS register is set.
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Register 3: System Exception Masked Interrupt Status (SYSEXCMIS), offset
0x008
The SYSEXCMIS register is the masked interrupt status register. On a read, this register gives the
current masked status value of the corresponding interrupt. A write has no effect.
System Exception Masked Interrupt Status (SYSEXCMIS)
Base 0x400F.9000
Offset 0x008
Type RO, reset 0x0000.0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
5
4
3
2
1
0
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
8
7
6
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
FPIXCMIS FPOFCMIS FPUFCMIS FPIOCMIS FPDZCMIS FPIDCMIS
RO
0
Bit/Field
Name
Type
Reset
31:6
reserved
RO
0x0000.00
5
FPIXCMIS
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
Floating-Point Inexact Exception Masked Interrupt Status
Value Description
0
An interrupt has not occurred or is masked.
1
An unmasked interrupt was signaled due to an inexact
exception.
This bit is cleared by writing a 1 to the FPIXCIC bit in the SYSEXCIC
register.
4
FPOFCMIS
RO
0
Floating-Point Overflow Exception Masked Interrupt Status
Value Description
0
An interrupt has not occurred or is masked.
1
An unmasked interrupt was signaled due to an overflow
exception.
This bit is cleared by writing a 1 to the FPOFCIC bit in the SYSEXCIC
register.
3
FPUFCMIS
RO
0
Floating-Point Underflow Exception Masked Interrupt Status
Value Description
0
An interrupt has not occurred or is masked.
1
An unmasked interrupt was signaled due to an underflow
exception.
This bit is cleared by writing a 1 to the FPUFCIC bit in the SYSEXCIC
register.
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Bit/Field
Name
Type
Reset
2
FPIOCMIS
RO
0
Description
Floating-Point Invalid Operation Masked Interrupt Status
Value Description
0
An interrupt has not occurred or is masked.
1
An unmasked interrupt was signaled due to an invalid operation.
This bit is cleared by writing a 1 to the FPIOCIC bit in the SYSEXCIC
register.
1
FPDZCMIS
RO
0
Floating-Point Divide By 0 Exception Masked Interrupt Status
Value Description
0
An interrupt has not occurred or is masked.
1
An unmasked interrupt was signaled due to a divide by 0
exception.
This bit is cleared by writing a 1 to the FPDZCIC bit in the SYSEXCIC
register.
0
FPIDCMIS
RO
0
Floating-Point Input Denormal Exception Masked Interrupt Status
Value Description
0
An interrupt has not occurred or is masked.
1
An unmasked interrupt was signaled due to an input denormal
exception.
This bit is cleared by writing a 1 to the FPIDCIC bit in the SYSEXCIC
register.
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Register 4: System Exception Interrupt Clear (SYSEXCIC), offset 0x00C
The SYSEXCIC register is the interrupt clear register. On a write of 1, the corresponding interrupt
(both raw interrupt and masked interrupt, if enabled) is cleared. A write of 0 has no effect.
System Exception Interrupt Clear (SYSEXCIC)
Base 0x400F.9000
Offset 0x00C
Type W1C, reset 0x0000.0000
31
30
29
28
27
26
25
24
W1C
0
W1C
0
W1C
0
W1C
0
W1C
0
W1C
0
W1C
0
W1C
0
15
14
13
12
11
10
9
W1C
0
W1C
0
W1C
0
W1C
0
W1C
0
W1C
0
23
22
21
20
19
18
17
16
W1C
0
W1C
0
W1C
0
W1C
0
W1C
0
W1C
0
W1C
0
W1C
0
8
7
6
5
4
3
2
1
0
W1C
0
W1C
0
W1C
0
reserved
Type
Reset
reserved
Type
Reset
W1C
0
FPIXCIC FPOFCIC FPUFCIC FPIOCIC FPDZCIC FPIDCIC
Bit/Field
Name
Type
Reset
31:6
reserved
W1C
0x0000.00
5
FPIXCIC
W1C
0
W1C
0
W1C
0
W1C
0
W1C
0
W1C
0
W1C
0
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
Floating-Point Inexact Exception Interrupt Clear
Writing a 1 to this bit clears the FPIXCRIS bit in the SYSEXCRIS register
and the FPIXCMIS bit in the SYSEXCMIS register.
4
FPOFCIC
W1C
0
Floating-Point Overflow Exception Interrupt Clear
Writing a 1 to this bit clears the FPOFCRIS bit in the SYSEXCRIS register
and the FPOFCMIS bit in the SYSEXCMIS register.
3
FPUFCIC
W1C
0
Floating-Point Underflow Exception Interrupt Clear
Writing a 1 to this bit clears the FPUFCRIS bit in the SYSEXCRIS register
and the FPUFCMIS bit in the SYSEXCMIS register.
2
FPIOCIC
W1C
0
Floating-Point Invalid Operation Interrupt Clear
Writing a 1 to this bit clears the FPIOCRIS bit in the SYSEXCRIS register
and the FPIOCMIS bit in the SYSEXCMIS register.
1
FPDZCIC
W1C
0
Floating-Point Divide By 0 Exception Interrupt Clear
Writing a 1 to this bit clears the FPDZCRIS bit in the SYSEXCRIS register
and the FPDZCMIS bit in the SYSEXCMIS register.
0
FPIDCIC
W1C
0
Floating-Point Input Denormal Exception Interrupt Clear
Writing a 1 to this bit clears the FPIDCRIS bit in the SYSEXCRIS register
and the FPIDCMIS bit in the SYSEXCMIS register.
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7
Internal Memory
The TM4C1230C3PM microcontroller comes with 12 KB of bit-banded SRAM, internal ROM, 32 KB
of Flash memory, and 2KB of EEPROM. The Flash memory controller provides a user-friendly
interface, making Flash memory programming a simple task. Flash memory is organized in 1-KB
independently erasable blocks and memory protection can be applied to the Flash memory on a
2-KB block basis. The EEPROM module provides a well-defined register interface to support accesses
to the EEPROM with both a random access style of read and write as well as a rolling or sequential
access scheme. A password model allows the application to lock one or more EEPROM blocks to
control access on 16-word boundaries.
7.1
Block Diagram
Figure 7-1 on page 446 illustrates the internal SRAM, ROM, and Flash memory blocks and control
logic. The dashed boxes in the figure indicate registers residing in the System Control module.
Figure 7-1. Internal Memory Block Diagram
ROM Control
RMCTL
ROM Array
ROMSWMAP
Flash Control
Icode Bus
FMA
FMD
Cortex-M4F
Dcode Bus
FMC
FCRIS
Flash Array
FCIM
System
Bus
FCMISC
FSIZE
SSIZE
Flash Write Buffer
FMC2
FWBVAL
FWBn
32 words
Bridge
FlashFMPRE
Protection
FMPPE
FMPREn
FMPPEn
User Registers
BOOTCFG
SRAM Array
USER_REG0
USER_REG1
USER_REG2
USER_REG3
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Figure 7-2 on page 447 illustrates the internal EEPROM block and control logic. The EEPROM block
is connected to the AHB bus.
Figure 7-2. EEPROM Block Diagram
EEPROM Control
EESIZE
EEPROM Array
Security
Block 0
Program
EEBLOCK
Block 1
EEOFFSET
Block 2
EERDWR
Block 3
EERDWRINC
...
EEDONE
Block n
EESUPP
EEUNLOCK
EEPROT
EEPASS0
EEPASS1
EEPASS2
EEINT
EEHIDE
EEDBGME
EEPROMPP
7.2
Functional Description
This section describes the functionality of the SRAM, ROM, Flash, and EEPROM memories.
Note:
7.2.1
The μDMA controller can transfer data to and from the on-chip SRAM. However, because
the Flash memory and ROM are located on a separate internal bus, it is not possible to
transfer data from the Flash memory or ROM with the μDMA controller.
SRAM
The internal SRAM of the TM4C1230C3PM device is located at address 0x2000.0000 of the device
memory map. To reduce the number of time consuming read-modify-write (RMW) operations, ARM
provides bit-banding technology in the processor. With a bit-band-enabled processor, certain regions
in the memory map (SRAM and peripheral space) can use address aliases to access individual bits
in a single, atomic operation. The bit-band base is located at address 0x2200.0000.
The bit-band alias is calculated by using the formula:
bit-band alias = bit-band base + (byte offset * 32) + (bit number * 4)
For example, if bit 3 at address 0x2000.1000 is to be modified, the bit-band alias is calculated as:
0x2200.0000 + (0x1000 * 32) + (3 * 4) = 0x2202.000C
With the alias address calculated, an instruction performing a read/write to address 0x2202.000C
allows direct access to only bit 3 of the byte at address 0x2000.1000.
For details about bit-banding, see “Bit-Banding” on page 83.
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Note:
7.2.2
The SRAM is implemented using two 32-bit wide SRAM banks (separate SRAM arrays).
The banks are partitioned such that one bank contains all even words (the even bank) and
the other contains all odd words (the odd bank). A write access that is followed immediately
by a read access to the same bank incurs a stall of a single clock cycle. However, a write
to one bank followed by a read of the other bank can occur in successive clock cycles
without incurring any delay.
ROM
The internal ROM of the TM4C1230C3PM device is located at address 0x0100.0000 of the device
memory map. Detailed information on the ROM contents can be found in the Tiva™ C Series
TM4C123x ROM User’s Guide (literature number SPMU367).
The ROM contains the following components:
■ TivaWare™ Boot Loader and vector table
■ TivaWare Peripheral Driver Library (DriverLib) release for product-specific peripherals and
interfaces
■ Advanced Encryption Standard (AES) cryptography tables
■ Cyclic Redundancy Check (CRC) error detection functionality
The boot loader is used as an initial program loader (when the Flash memory is empty) as well as
an application-initiated firmware upgrade mechanism (by calling back to the boot loader). The
Peripheral Driver Library APIs in ROM can be called by applications, reducing Flash memory
requirements and freeing the Flash memory to be used for other purposes (such as additional
features in the application). Advance Encryption Standard (AES) is a publicly defined encryption
standard used by the U.S. Government and Cyclic Redundancy Check (CRC) is a technique to
validate if a block of data has the same contents as when previously checked.
7.2.2.1
Boot Loader Overview
The TivaWare Boot Loader is used to download code to the Flash memory of a device without the
use of a debug interface. When the core is reset, the user has the opportunity to direct the core to
execute the ROM Boot Loader or the application in Flash memory by using any GPIO signal in Ports
A-H as configured in the Boot Configuration (BOOTCFG) register (see page 502).
At reset, the following sequence is performed:
1. The BOOTCFG register is read. If the EN bit is clear, the ROM Boot Loader is executed.
2. In the ROM Boot Loader, the status of the specified GPIO pin is compared with the specified
polarity. If the status matches the specified polarity, the ROM is mapped to address 0x0000.0000
and execution continues out of the ROM Boot Loader.
3. If the EN bit is set or the status doesn't match the specified polarity, the data at address
0x0000.0004 is read, and if the data at this address is 0xFFFF.FFFF, the ROM is mapped to
address 0x0000.0000 and execution continues out of the ROM Boot Loader.
4. If there is data at address 0x0000.0004 that is not 0xFFFF.FFFF, the stack pointer (SP) is loaded
from Flash memory at address 0x0000.0000 and the program counter (PC) is loaded from
address 0x0000.0004. The user application begins executing.
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The boot loader uses a simple packet interface to provide synchronous communication with the
device. The speed of the boot loader is determined by the internal oscillator (PIOSC) frequency as
it does not enable the PLL. The following serial interfaces can be used:
■ UART0
■ SSI0
■ I2C0
■ USB
The data format and communication protocol are identical for the UART0, SSI0, and I2C0 interfaces.
Note:
The Flash-memory-resident version of the boot loader also supports CAN.
See the TivaWare™ Boot Loader for C Series User's Guide (literature number SPMU301) for
information on the boot loader software. The USB boot loader uses the standard Device Firmware
Upgrade USB device class.
Considerations When Using the UART Boot Loader in ROM
U0Tx is not driven by the ROM boot loader until the auto-bauding process has completed. If U0Tx
is floating during this time, the receiver it is connected to may see transitions on the signal, which
could be interpreted by its UART as valid characters. To handle this situation, put a pull-up or
pull-down on U0Tx, providing a defined state for the signal until the ROM boot loader begins driving
U0Tx. A pull-up is preferred as it indicates that the UART is idle, rather than a pull-down, which
indicates a break condition.
7.2.2.2
TivaWare Peripheral Driver Library
The TivaWare Peripheral Driver Library contains a file called driverlib/rom.h that assists with
calling the peripheral driver library functions in the ROM. The detailed description of each function
is available in the Tiva™ C Series TM4C123x ROM User’s Guide (literature number SPMU367).
See the "Using the ROM" chapter of the TivaWare™ Peripheral Driver Library for C Series User's
Guide (literature number SPMU298) for more details on calling the ROM functions and using
driverlib/rom.h. The driverlib/rom_map.h header file is also provided to aid portability
when using different Tiva™ C Series devices which might have a different subset of DriverLib
functions in ROM. The driverlib/rom_map.h header file uses build-time labels to route function
calls to the ROM if those functions are available on a given device, otherwise, it routes to
Flash-resident versions of the functions.
A table at the beginning of the ROM points to the entry points for the APIs that are provided in the
ROM. Accessing the API through these tables provides scalability; while the API locations may
change in future versions of the ROM, the API tables will not. The tables are split into two levels;
the main table contains one pointer per peripheral which points to a secondary table that contains
one pointer per API that is associated with that peripheral. The main table is located at 0x0100.0010,
right after the Cortex-M4F vector table in the ROM.
DriverLib functions are described in detail in the TivaWare™ Peripheral Driver Library for C Series
User's Guide (literature number SPMU298).
Additional APIs are available for graphics and USB functions, but are not preloaded into ROM. The
TivaWare Graphics Library provides a set of graphics primitives and a widget set for creating graphical
user interfaces on Tiva™ C Series microcontroller-based boards that have a graphical display (for
more information, see the TivaWare™ Graphics Library for C Series User's Guide (literature number
SPMU300)).
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7.2.2.3
Advanced Encryption Standard (AES) Cryptography Tables
AES is a strong encryption method with reasonable performance and size. AES is fast in both
hardware and software, is fairly easy to implement, and requires little memory. AES is ideal for
applications that can use prearranged keys, such as setup during manufacturing or configuration.
Four data tables used by the XySSL AES implementation are provided in the ROM. The first is the
forward S-box substitution table, the second is the reverse S-box substitution table, the third is the
forward polynomial table, and the final is the reverse polynomial table. See the Tiva™ C Series
TM4C123x ROM User’s Guide (literature number SPMU367) for more information on AES.
7.2.2.4
Cyclic Redundancy Check (CRC) Error Detection
The CRC technique can be used to validate correct receipt of messages (nothing lost or modified
in transit), to validate data after decompression, to validate that Flash memory contents have not
been changed, and for other cases where the data needs to be validated. A CRC is preferred over
a simple checksum (for example, XOR all bits) because it catches changes more readily. See the
Tiva™ C Series TM4C123x ROM User’s Guide (literature number SPMU367) for more information
on CRC.
7.2.3
Flash Memory
At system clock speeds of 40 MHz and below, the Flash memory is read in a single cycle. The Flash
memory is organized as a set of 1-KB blocks that can be individually erased. An individual 32-bit
word can be programmed to change bits from 1 to 0. In addition, a write buffer provides the ability
to program 32 continuous words in Flash memory in half the time of programming the words
individually. Erasing a block causes the entire contents of the block to be reset to all 1s. The 1-KB
blocks are paired into sets of 2-KB blocks that can be individually protected. The protection allows
blocks to be marked as read-only or execute-only, providing different levels of code protection.
Read-only blocks cannot be erased or programmed, protecting the contents of those blocks from
being modified. Execute-only blocks cannot be erased or programmed and can only be read by the
controller instruction fetch mechanism, protecting the contents of those blocks from being read by
either the controller or a debugger.
7.2.3.1
Prefetch Buffer
The Flash memory controller has a prefetch buffer that is automatically used when the CPU frequency
is greater than 40 MHz. In this mode, the Flash memory operates at half of the system clock. The
prefetch buffer fetches two 32-bit words per clock allowing instructions to be fetched with no wait
states while code is executing linearly. The fetch buffer includes a branch speculation mechanism
that recognizes a branch and avoids extra wait states by not reading the next word pair. Also, short
loop branches often stay in the buffer. As a result, some branches can be executed with no wait
states. Other branches incur a single wait state.
7.2.3.2
Flash Memory Protection
The user is provided two forms of Flash memory protection per 2-KB Flash memory block in one
pair of 32-bit wide registers. The policy for each protection form is controlled by individual bits (per
policy per block) in the FMPPEn and FMPREn registers.
■ Flash Memory Protection Program Enable (FMPPEn): If a bit is set, the corresponding block
may be programmed (written) or erased. If a bit is cleared, the corresponding block may not be
changed.
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■ Flash Memory Protection Read Enable (FMPREn): If a bit is set, the corresponding block may
be executed or read by software or debuggers. If a bit is cleared, the corresponding block may
only be executed, and contents of the memory block are prohibited from being read as data.
The policies may be combined as shown in Table 7-1 on page 451.
Table 7-1. Flash Memory Protection Policy Combinations
FMPPEn
FMPREn
0
0
Protection
Execute-only protection. The block may only be executed and may not be written or erased.
This mode is used to protect code.
1
0
The block may be written, erased or executed, but not read. This combination is unlikely to
be used.
0
1
Read-only protection. The block may be read or executed but may not be written or erased.
This mode is used to lock the block from further modification while allowing any read or
execute access.
1
1
No protection. The block may be written, erased, executed or read.
A Flash memory access that attempts to read a read-protected block (FMPREn bit is set) is prohibited
and generates a bus fault. A Flash memory access that attempts to program or erase a
program-protected block (FMPPEn bit is set) is prohibited and can optionally generate an interrupt
(by setting the AMASK bit in the Flash Controller Interrupt Mask (FCIM) register) to alert software
developers of poorly behaving software during the development and debug phases.
The factory settings for the FMPREn and FMPPEn registers are a value of 1 for all implemented
banks. These settings create a policy of open access and programmability. The register bits may
be changed by clearing the specific register bit. The changes are effective immediately, but are not
permanent until the register is committed (saved), at which point the bit change is permanent. If a
bit is changed from a 1 to a 0 and not committed, it may be restored by executing a power-on reset
sequence. The changes are committed using the Flash Memory Control (FMC) register. Details
on programming these bits are discussed in “Non-Volatile Register Programming” on page 454.
7.2.3.3
Execute-Only Protection
Execute-only protection prevents both modification and visibility to a protected flash block. This
mode is intended to be used in situations where a device requires debug capability, yet portions of
the application space must be protected from external access. An example of this is a company
who wishes to sell Tiva™ C Series devices with their proprietary software preprogrammed, yet allow
the end user to add custom code to an unprotected region of the flash (such as a motor control
module with a customizable motor configuration section in flash).
Literal data introduces a complication to the protection mechanism. When C code is compiled and
linked, literal data (constants, and so on) is typically placed in the text section, between functions,
by the compiler. The literal data is accessed at run time through the use of the LDR instruction,
which loads the data from memory using a PC-relative memory address. The execution of the LDR
instruction generates a read transaction across the Cortex-M3's DCode bus, which is subject to the
execute-only protection mechanism. If the accessed block is marked as execute only, the transaction
is blocked, and the processor is prevented from loading the constant data and, therefore, inhibiting
correct execution. Therefore, using execute-only protection requires that literal data be handled
differently. There are three ways to address this:
1. Use a compiler that allows literal data to be collected into a separate section that is put into one
or more read-enabled flash blocks. Note that the LDR instruction may use a PC-relative
address–-in which case the literal pool cannot be located outside the span of the offset–-or the
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software may reserve a register to point to the base address of the literal pool and the LDR
offset is relative to the beginning of the pool.
2. Use a compiler that generates literal data from arithmetic instruction immediate data and
subsequent computation.
3. Use method 1 or 2, but in assembly language, if the compiler does not support either method.
7.2.3.4
Read-Only Protection
Read-only protection prevents the contents of the flash block from being re-programmed, while still
allowing the content to be read by processor or the debug interface. Note that if a FMPREn bit is
cleared, all read accesses to the Flash memory block are disallowed, including any data accesses.
Care must be taken not to store required data in a Flash memory block that has the associated
FMPREn bit cleared.
The read-only mode does not prevent read access to the stored program, but it does provide
protection against accidental (or malicious) erasure or programming. Read-only is especially useful
for utilities like the boot loader when the debug interface is permanently disabled. In such
combinations, the boot loader, which provides access control to the Flash memory, is protected
from being erased or modified.
7.2.3.5
Permanently Disabling Debug
For extremely sensitive applications, the debug interface to the processor and peripherals can be
permanently disabled, blocking all accesses to the device through the JTAG or SWD interfaces.
With the debug interface disabled, it is still possible to perform standard IEEE instructions (such as
boundary scan operations), but access to the processor and peripherals is blocked.
The DBG0 and DBG1 bits of the Boot Configuration (BOOTCFG) register control whether the debug
interface is turned on or off.
The debug interface should not be permanently disabled without providing some mechanism–-such
as the boot loader–-to provide customer-installable updates or bug fixes. Disabling the debug
interface is permanent and cannot be reversed.
7.2.3.6
Interrupts
The Flash memory controller can generate interrupts when the following conditions are observed:
■ Programming Interrupt - signals when a program or erase action is complete.
■ Access Interrupt - signals when a program or erase action has been attempted on a 2-kB block
of memory that is protected by its corresponding FMPPEn bit.
The interrupt events that can trigger a controller-level interrupt are defined in the Flash Controller
Masked Interrupt Status (FCMIS) register (see page 471) by setting the corresponding MASK bits.
If interrupts are not used, the raw interrupt status is always visible via the Flash Controller Raw
Interrupt Status (FCRIS) register (see page 468).
Interrupts are always cleared (for both the FCMIS and FCRIS registers) by writing a 1 to the
corresponding bit in the Flash Controller Masked Interrupt Status and Clear (FCMISC) register
(see page 473).
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7.2.3.7
Flash Memory Programming
The Tiva™ C Series devices provide a user-friendly interface for Flash memory programming. All
erase/program operations are handled via three registers: Flash Memory Address (FMA), Flash
Memory Data (FMD), and Flash Memory Control (FMC). Note that if the debug capabilities of the
microcontroller have been deactivated, resulting in a "locked" state, a recovery sequence must be
performed in order to reactivate the debug module. See “Recovering a "Locked"
Microcontroller” on page 191.
During a Flash memory operation (write, page erase, or mass erase) access to the Flash memory
is inhibited. As a result, instruction and literal fetches are held off until the Flash memory operation
is complete. If instruction execution is required during a Flash memory operation, the code that is
executing must be placed in SRAM and executed from there while the flash operation is in progress.
Note:
When programming Flash memory, the following characteristics of the memory must be
considered:
■ Only an erase can change bits from 0 to 1.
■ A write can only change bits from 1 to 0. If the write attempts to change a 0 to a 1, the
write fails and no bits are changed.
■ A flash operation can be started before entering the Sleep or Deep-Sleep mode (using
the wait for interrupt instruction, WFI). It can also be completed while in Sleep or
Deep-Sleep. If the Flash program/erase event comes in succession to EEPROM access,
the Flash event gets completed after waking from Sleep/Deep-Sleep and is started after
the wake-up.
7.2.3.8
Basic Program / Erase Operations
To program a 32-bit word
1. Write source data to the FMD register.
2. Write the target address to the FMA register.
3. Write the Flash memory write key and the WRITE bit to the FMC register. Depending on the
value of the KEY bit in the BOOTCFG register, the value 0xA442 or 0x71D5 must be written
into the WRKEY field for a Flash memory write to occur.
4. Poll the FMC register until the WRITE bit is cleared.
To perform an erase of a 1-KB page
1. Write the page address to the FMA register.
2. Write the Flash memory write key and the ERASE bit to the FMC register. Depending on the
value of the KEY bit in the BOOTCFG register, the value 0xA442 or 0x71D5 must be written
into the WRKEY field for a Flash memory write to occur.
3. Poll the FMC register until the ERASE bit is cleared or, alternatively, enable the programming
interrupt using the PMASK bit in the FCIM register.
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To perform a mass erase of the Flash memory
1. Write the Flash memory write key and the MERASE bit to the FMC register. Depending on the
value of the KEY bit in the BOOTCFG register, the value 0xA442 or 0x71D5 must be written
into the WRKEY field for a Flash memory write to occur.
2. Poll the FMC register until the MERASE bit is cleared or, alternatively, enable the programming
interrupt using the PMASK bit in the FCIM register.
7.2.3.9
32-Word Flash Memory Write Buffer
A 32-word write buffer provides the capability to perform faster write accesses to the Flash memory
by programming 2 32-bit words at a time, allowing 32 words to be programmed in the same time
as 16 would take using the method described above. The data for the buffered write is written to
the Flash Write Buffer (FWBn) registers.
The registers are 32-word aligned with Flash memory, and therefore the register FWB0 corresponds
with the address in FMA where bits [6:0] of FMA are all 0. FWB1 corresponds with the address in
FMA + 0x4 and so on. Only the FWBn registers that have been updated since the previous buffered
Flash memory write operation are written. The Flash Write Buffer Valid (FWBVAL) register shows
which registers have been written since the last buffered Flash memory write operation. This register
contains a bit for each of the 32 FWBn registers, where bit[n] of FWBVAL corresponds to FWBn.
The FWBn register has been updated if the corresponding bit in the FWBVAL register is set.
To program 32 words with a single buffered Flash memory write operation
1. Write the source data to the FWBn registers.
2. Write the target address to the FMA register. This must be a 32-word aligned address (that is,
bits [6:0] in FMA must be 0s).
3. Write the Flash memory write key and the WRBUF bit to the FMC2 register. Depending on the
value of the KEY bit in the BOOTCFG register, the value 0xA442 or 0x71D5 must be written
into the WRKEY field for a Flash memory write to occur.
4. Poll the FMC2 register until the WRBUF bit is cleared or wait for the PMIS interrupt to be signaled.
7.2.3.10
Non-Volatile Register Programming
Note:
The Boot Configuration (BOOTCFG) register requires a POR before the committed
changes take effect.
This section discusses how to update the registers shown in Table 7-2 on page 455 that are resident
within the Flash memory itself. These registers exist in a separate space from the main Flash memory
array and are not affected by an ERASE or MASS ERASE operation. With the exception of the Boot
Configuration (BOOTCFG) register, the settings in these registers can be written, their functions
verified, and their values read back before they are committed, at which point they become
non-volatile. If a value in one of these registers has not been committed, a power-on reset restores
the last committed value or the default value if the register has never been committed. Other types
of reset have no effect. Once the register contents are committed, the only way to restore the factory
default values is to perform the sequence described in “Recovering a "Locked"
Microcontroller” on page 191.
To write to a non-volatile register:
■ Bits can only be changed from 1 to 0.
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■ For all registers except the BOOTCFG register, write the data to the register address provided
in the register description. For the BOOTCFG register, write the data to the FMD register.
■ The registers can be read to verify their contents. To verify what is to be stored in the BOOTCFG
register, read the FMD register. Reading the BOOTCFG register returns the previously committed
value or the default value if the register has never been committed.
■ The new values are effectively immediately for all registers except BOOTCFG, as the new value
for the register is not stored in the register until it has been committed.
■ Prior to committing the register value, a power-on reset restores the last committed value or the
default value if the register has never been committed.
To commit a new value to a non-volatile register:
■ Write the data as described above.
■ Write to the FMA register the value shown in Table 7-2 on page 455.
■ Write the Flash memory write key and set the COMT bit in the FMC register. These values must
be written to the FMC register at the same time.
■ Committing a non-volatile register has the same timing as a write to regular Flash memory,
defined by TPROG64, as shown in Table 20-23 on page 1079. Software can poll the COMT bit in the
FMC register to determine when the operation is complete, or an interrupt can be enabled by
setting the PMASK bit in the FCIM register.
■ When committing the BOOTCFG register, the INVDRIS bit in the FCRIS register is set if a bit
that has already been committed as a 0 is attempted to be committed as a 1.
■ Once the value has been committed, a power-on reset has no effect on the register contents.
■ Changes to the BOOTCFG register are effective after the next power-on reset.
■ Once the NW bit has been changed to 0 and committed, further changes to the BOOTCFG register
are not allowed.
Important: After being committed, these registers can only be restored to their factory default values
by performing the sequence described in “Recovering a "Locked"
Microcontroller” on page 191. The mass erase of the main Flash memory array caused
by the sequence is performed prior to restoring these registers.
Table 7-2. User-Programmable Flash Memory Resident Registers
Register to be Committed
FMA Value
Data Source
FMPRE0
0x0000.0000
FMPRE0
FMPPE0
0x0000.0001
FMPPE0
USER_REG0
0x8000.0000
USER_REG0
USER_REG1
0x8000.0001
USER_REG1
USER_REG2
0x8000.0002
USER_REG2
USER_REG3
0x8000.0003
USER_REG3
BOOTCFG
0x7510.0000
FMD
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7.2.4
EEPROM
The TM4C1230C3PM microcontroller includes an EEPROM with the following features:
■ 2Kbytes of memory accessible as 512 32-bit words
■ 32 blocks of 16 words (64 bytes) each
■ Built-in wear leveling
■ Access protection per block
■ Lock protection option for the whole peripheral as well as per block using 32-bit to 96-bit unlock
codes (application selectable)
■ Interrupt support for write completion to avoid polling
■ Endurance of 500K writes (when writing at fixed offset in every alternate page in circular fashion)
to 15M operations (when cycling through two pages ) per each 2-page block.
7.2.4.1
Functional Description
The EEPROM module provides a well-defined register interface to support accesses to the EEPROM
with both a random access style of read and write as well as a rolling or sequential access scheme.
A protection mechanism allows locking EEPROM blocks to prevent writes under a set of
circumstances as well as reads under the same or different circumstances. The password model
allows the application to lock one or more EEPROM blocks to control access on 16-word boundaries.
Important: The configuration of the system clock must not be changed while an EEPROM operation
is in process. Software must wait until the WORKING bit in the EEPROM Done Status
(EEDONE) register is clear before making any changes to the system clock.
Blocks
There are 32 blocks of 16 words each in the EEPROM. Bytes and half-words can be read, and
these accesses do not have to occur on a word boundary. The entire word is read and any unneeded
data is simply ignored. They are writable only on a word basis. To write a byte, it is necessary to
read the word value, modify the appropriate byte, and write the word back.
Each block is addressable as an offset within the EEPROM, using a block select register. Each
word is offset addressable within the selected block.
The current block is selected by the EEPROM Current Block (EEBLOCK) register. The current
offset is selected and checked for validity by the EEPROM Current Offset (EEOFFSET) register.
The application may write the EEOFFSET register any time, and it is also automatically incremented
when the EEPROM Read-Write with Increment (EERDWRINC) register is accessed. However,
the EERDWRINC register does not increment the block number, but instead wraps within the block.
Blocks are individually protectable. Attempts to read from a block for which the application does not
have permission return 0xFFFF.FFFF. Attempts to write into a block for which the application does
not have permission results in an error in the EEDONE register.
Timing Considerations
After enabling or resetting the EEPROM module, software must wait until the WORKING bit in the
EEDONE register is clear before accessing any EEPROM registers.
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In the event that there are Flash memory writes or erases and EEPROM writes active, it is possible
for the EEPROM process to be interrupted by the Flash memory write/erase and then continue after
the Flash memory write is completed. This action may change the amount of time that the EEPROM
operation takes.
EEPROM operations must be completed before entering Sleep or Deep-Sleep mode. Ensure the
EEPROM operations have completed by checking the EEPROM Done Status (EEDONE) register
before issuing a WFI instruction to enter Sleep or Deep-Sleep.
Reads of words within a block are at direct speed, which means that wait states are automatically
generated if the system clock is faster than the speed of the EEPROM. The read access time is
specified in Table 20-24 on page 1079.
Writing the EEOFFSET register also does not incur any penalties.
Writing the EEBLOCK register is not delayed, but any attempt to access data within that block is
delayed by 4 clocks after writing EEBLOCK. This time is used to load block specific information.
Writes to words within a block are delayed by a variable amount of time. The application may use
an interrupt to be notified when the write is done, or alternatively poll for the done status in the
EEDONE register. The variability ranges from the write timing of the EEPROM to the erase timing
of EEPROM, where the erase timing is less than the write timing of most external EEPROMs.
Locking and Passwords
The EEPROM can be locked at both the module level and the block level. The lock is controlled by
a password that is stored in the EEPROM Password (EEPASSn) registers and can be any 32-bit
to 96-bit value other than all 1s. Block 0 is the master block, the password for block 0 protects the
control registers as well as all other blocks. Each block can be further protected with a password
for that block.
If a password is registered for block 0, then the whole module is locked at reset. The locking behavior
is such that blocks 1 to 31 are inaccessible until block 0 is unlocked, and block 0 follows the rules
defined by its protection bits. As a result, the EEBLOCK register cannot be changed from 0 until
block 0 is unlocked.
A password registered with any block, including block 0, allows for protection rules that control
access of that block based on whether it is locked or unlocked. Generally, the lock can be used to
prevent write accesses when locked or can prevent read and write accesses when locked.
All password-protected blocks are locked at reset. To unlock a block, the correct password value
must be written to the EEPROM Unlock (EEUNLOCK) register by writing to it one to three times
to form the 32-bit, 64-bit, or 96-bit password registered using the EEPASSn register. The value
used to configure the EEPASS0 register must always be written last. For example, for a 96-bit
password, the value used to configure the EEPASS2 register must be written first, followed by the
EEPASS1 and the EEPASS0 register values. A block or the module may be re-locked by writing
0xFFFF.FFFF to the EEUNLOCK register because 0xFFFF.FFFF is not a valid password.
Protection and Access Control
The protection bits provide discrete control of read and write access for each block which allows
various protection models per block, including:
■ Without password: Readable and writable at any time. This mode is the default when there is
no password.
■ Without password: Readable but not writable.
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■ With password: Readable, but only writable when unlocked by the password. This mode is the
default when there is a password.
■ With password: Readable or writable only when unlocked.
■ With password: Readable only when unlocked, not writable.
Additionally, access protection may be applied based on the processor mode. This configuration
allows for supervisor-only access or supervisor and user access, which is the default. Supervisor-only
access mode also prevents access by the µDMA and Debugger.
Additionally, the master block may be used to control access protection for the protection mechanism
itself. If access control for block 0 is for supervisor only, then the whole module may only be accessed
in supervisor mode. In addition, the protection level for block 0 sets the minimum protection level
for the entire EEPROM. For example, if the PROT field in the EEPROT register is configured to 0x1
for block 0, then block 1 could be configured with the PROT field to be 0x1, 0x2, or 0x3, but not 0x0.
Note that for blocks 1 to 31, they are inaccessible for read or write if block 0 has a password and it
is not unlocked. If block 0 has a master password, then the strictest protection defined for block 0
or an individual block is implemented on the remaining blocks.
Hidden Blocks
Hiding provides a temporary form of protection. Every block except block 0 can be hidden, which
prevents all accesses until the next reset.
This mechanism can allow a boot or initialization routine to access some data which is then made
inaccessible to all further accesses. Because boot and initialization routines control the capabilities
of the application, hidden blocks provide a powerful isolation of the data when debug is disabled.
A typical use model would be to have the initialization code store passwords, keys, and/or hashes
to use for verification of the rest of the application. Once performed, the block is then hidden and
made inaccessible until the next reset which then re-enters the initialization code.
Power and Reset Safety
Once the EEDONE register indicates that a location has been successfully written, the data is
retained until that location is written again. There is no power or reset race after the EEDONE register
indicates a write has completed.
Interrupt Control
The EEPROM module allows for an interrupt when a write completes to eliminate the need for
polling. The interrupt can be used to drive an application ISR which can then write more words or
verify completion. The interrupt mechanism is used any time the EEDONE register goes from working
to done, whether because of an error or the successful completion of a program or erase operation.
This interrupt mechanism works for data writes, writes to password and protection registers, forced
erase by the EEPROM Support Control and Status (EESUPP) register, and mass erase using
the EEPROM Debug Mass Erase (EEDGBME) register. The EEPROM interrupt is signaled to the
core using the Flash memory interrupt vector. Software can determine that the source of the interrupt
was the EEPROM by examining bit 2 of the Flash Controller Masked Interrupt Status and Clear
(FCMISC) register.
Theory of Operation
The EEPROM operates using a traditional Flash bank model which implements EEPROM-type
cells, but uses sector erase. Additionally, words are replicated in the pages to allow 500K+ erase
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cycles when needed, which means that each word has a latest version. As a result, a write creates
a new version of the word in a new location, making the previous value obsolete.
Each sector contains two blocks. Each block contains locations for the active copy plus six redundant
copies. Passwords, protection bits, and control data are all stored in the pages.
When a page runs out of room to store the latest version of a word, a copy buffer is used. The copy
buffer copies the latest words of each block. The original page is then erased. Finally, the copy
buffer contents are copied back to the page. This mechanism ensures that data cannot be lost due
to power down, even during an operation. The EEPROM mechanism properly tracks all state
information to provide complete safety and protection. Although it should not normally be possible,
errors during programming can occur in certain circumstances, for example, the voltage rail dropping
during programming. In these cases, the EESUPP register can be used to finish an operation as
described in the section called “Error During Programming” on page 459.
Manual Copy Buffer Erase
The copy buffer is only used when a main block is full because a word has been written seven times
and there is no more room to store its latest version. In this situation, the latest versions of all the
words in the block are copied to the copy buffer, allowing the main block to be erased safely, providing
power down safety. If the copy buffer itself is full, then it must first be erased, which adds extra time.
By performing a manual erase of the copy buffer, this overhead does not occur during a future write
access. The EREQ bit in the EESUPP register is set if the copy buffer must be erased. If so, the
START bit can be written by the application to force the erase at a more convenient time. The
EEDONE and EEINT registers can be used to detect completion.
Debug Mass Erase
The EEPROM debug mass erase allows the developer to mass erase the EEPROM. For the mass
erase to occur correctly, there can be no active EEPROM operations. After the last EEPROM
operation, the application must ensure that no EEPROM registers are updated, including modifying
the EEBLOCK and the EEOFFSET registers without doing an actual read or write operation. To
hold off these operations, the application should reset the EEPROM module by setting the R0 bit in
the EEPROM Software Reset (SREEPROM) register, wait until WORKING bit in the EEPROM Done
Status (EEDONE) register is clear, and then enable the debug mass erase by setting the ME bit in
the EEPROM Debug Mass Erase (EEDBGME) register.
Error During Programming
Operations such as data-write, password set, protection set, and copy buffer erase may perform
multiple operations. For example, a normal write performs two underlying writes: the control word
write and the data write. If the control word writes but the data fails (for example, due to a voltage
drop), the overall write fails with indication provided in the EEDONE register. Failure and the corrective
action is broken down by the type of operation:
■ If a normal write fails such that the control word is written but the data fails to write, the safe
course of action is to retry the operation once the system is otherwise stable, for example, when
the voltage is stabilized. After the retry, the control word and write data are advanced to the next
location.
■ If a password or protection write fails, the safe course of action is to retry the operation once the
system is otherwise stable. In the event that multi-word passwords may be written outside of a
manufacturing or bring-up mode, care must be taken to ensure all words are written in immediate
succession. If not, then partial password unlock would need to be supported to recover.
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■ If the word write requires the block to be written to the copy buffer, then it is possible to fail or
lose power during the subsequent operations. A control word mechanism is used to track what
step the EEPROM was in if a failure occurs. If not completed, the EESUPP register indicates
the partial completion, and the EESUPP START bit can be written to allow it to continue to
completion.
■ If a copy buffer erase fails or power is lost while erasing, the EESUPP register indicates it is not
complete and allows it to be restarted
After a reset and prior to writing any data to the EEPROM, software must read the EESUPP register
and check for the presence of any error condition which may indicate that a write or erase was in
progress when the system was reset due to a voltage drop. If either the PRETRY or ERETRY bits are
set, the peripheral should be reset by setting and then clearing the R0 bit in the EEPROM Software
Reset (SREEPROM) register and waiting for the WORKING bit in the EEDONE register to clear
before again checking the EESUPP register for error indicators. This procedure should allow the
EEPROM to recover from the write or erase error. In very isolated cases, the EESUPP register may
continue to register an error after this operation, in which case the reset should be repeated. After
recovery, the application should rewrite the data which was being programmed when the initial
failure occurred.
Soft Reset Handling
The following soft resets should not be asserted during an EEPROM program or erase operation:
■ Software reset (SYSRESREQ)
■ Software peripheral reset
■ Watchdog reset
■ MOSC failure reset
The WORKING bit of the EEDONE register can be checked before the reset is asserted to see if an
EEPROM program or erase operation is occurring. Soft resets may occur when using a debugger
and should be avoided during an EEPROM operation. A reset such as the Watchdog reset can be
mapped to an external reset using a GPIO, or Hibernate can be entered, if time is not a concern.
Endurance
Endurance is per meta-block which is 2 blocks. Endurance is measured in two ways:
1. To the application, it is the number of writes that can be performed.
2. To the microcontroller, it is the number of erases that can be performed on the meta-block.
Because of the second measure, the number of writes depends on how the writes are performed.
For example:
■ One word can be written more than 500K times, but, these writes impact the meta-block that the
word is within. As a result, writing one word 500K times, then trying to write a nearby word 500K
times is not assured to work. To ensure success, the words should be written more in parallel.
■ All words can be written in a sweep with a total of more than 500K sweeps which updates all
words more than 500K times.
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■ Different words can be written such that any or all words can be written more than 500K times
when write counts per word stay about the same. For example, offset 0 could be written 3 times,
then offset 1 could be written 2 times, then offset 2 is written 4 times, then offset 1 is written
twice, then offset 0 is written again. As a result, all 3 offsets would have 4 writes at the end of
the sequence. This kind of balancing within 7 writes maximizes the endurance of different words
within the same meta-block.
7.2.4.2
EEPROM Initialization and Configuration
Before writing to any EEPROM registers, the clock to the EEPROM module must be enabled through
the EEPROM Run Mode Clock Gating Control (RCGCEEPROM) register (see page 325) and the
following initialization steps must be executed:
1. Insert delay (6 cycles plus function call overhead).
2. Poll the WORKING bit in the EEPROM Done Status (EEDONE) register until it is clear, indicating
that the EEPROM has completed its power-on initialization. When WORKING=0, continue.
3. Read the PRETRY and ERETRY bits in the EEPROM Support Control and Status (EESUPP)
register. If either of the bits are set, return an error, else continue.
4. Reset the EEPROM module using the EEPROM Software Reset (SREEPROM) register at
offset 0x558 in the System Control register space.
5. Insert delay (6 cycles plus function call overhead).
6. Poll the WORKING bit in the EEPROM Done Status (EEDONE) register to determine when it is
clear. When WORKING=0, continue.
7. Read the PRETRY and ERETRY bits in the EESUPP register. If either of the bits are set, return
an error, else the EEPROM initialization is complete and software may use the peripheral as
normal.
Important: Failure to perform these initialization steps after a reset may lead to incorrect operation
or permanent data loss if the EEPROM is later written.
If the PRETRY or ERETRY bits are set in the EESUPP register, the EEPROM was unable
to recover its state. If power is stable when this occurs, this indicates a fatal error and
is likely an indication that the EEPROM memory has exceeded its specified lifetime
write/erase specification. If the supply voltage is unstable when this return code is
observed, retrying the operation once the voltage is stabilized may clear the error.
The EEPROM initialization function code is named EEPROMinit( ) in TivaWare, which can be
downloaded from http://www.ti.com/tivaware.
7.3
Register Map
Table 7-3 on page 462 lists the ROM Controller register and the Flash memory and control registers.
The offset listed is a hexadecimal increment to the particular memory controller's base address.
The Flash memory register offsets are relative to the Flash memory control base address of
0x400F.D000. The EEPROM registers are relative to the EEPROM base address of 0x400A.F000.
The ROM and Flash memory protection register offsets are relative to the System Control base
address of 0x400F.E000.
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Table 7-3. Flash Register Map
Offset
Name
Type
Reset
See
page
Description
Flash Memory Registers (Flash Control Offset)
0x000
FMA
RW
0x0000.0000
Flash Memory Address
464
0x004
FMD
RW
0x0000.0000
Flash Memory Data
465
0x008
FMC
RW
0x0000.0000
Flash Memory Control
466
0x00C
FCRIS
RO
0x0000.0000
Flash Controller Raw Interrupt Status
468
0x010
FCIM
RW
0x0000.0000
Flash Controller Interrupt Mask
471
0x014
FCMISC
RW1C
0x0000.0000
Flash Controller Masked Interrupt Status and Clear
473
0x020
FMC2
RW
0x0000.0000
Flash Memory Control 2
476
0x030
FWBVAL
RW
0x0000.0000
Flash Write Buffer Valid
477
0x100 0x17C
FWBn
RW
0x0000.0000
Flash Write Buffer n
478
0xFC0
FSIZE
RO
0x0000.000F
Flash Size
479
0xFC4
SSIZE
RO
0x0000.002F
SRAM Size
480
0xFCC
ROMSWMAP
RO
0x0000.0000
ROM Software Map
481
EEPROM Registers (EEPROM Control Offset)
0x000
EESIZE
RO
0x0020.0200
EEPROM Size Information
482
0x004
EEBLOCK
RW
0x0000.0000
EEPROM Current Block
483
0x008
EEOFFSET
RW
0x0000.0000
EEPROM Current Offset
484
0x010
EERDWR
RW
-
EEPROM Read-Write
485
0x014
EERDWRINC
RW
-
EEPROM Read-Write with Increment
486
0x018
EEDONE
RO
0x0000.0000
EEPROM Done Status
487
0x01C
EESUPP
RW
-
EEPROM Support Control and Status
489
0x020
EEUNLOCK
RW
-
EEPROM Unlock
491
0x030
EEPROT
RW
0x0000.0000
EEPROM Protection
492
0x034
EEPASS0
RW
-
EEPROM Password
494
0x038
EEPASS1
RW
-
EEPROM Password
494
0x03C
EEPASS2
RW
-
EEPROM Password
494
0x040
EEINT
RW
0x0000.0000
EEPROM Interrupt
495
0x050
EEHIDE
RW
0x0000.0000
EEPROM Block Hide
496
0x080
EEDBGME
RW
0x0000.0000
EEPROM Debug Mass Erase
497
0xFC0
EEPROMPP
RO
0x0000.001F
EEPROM Peripheral Properties
498
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Table 7-3. Flash Register Map (continued)
Offset
Name
Reset
Description
See
page
RW1C
-
ROM Control
499
Type
Memory Registers (System Control Offset)
0x0F0
RMCTL
0x130
FMPRE0
RW
0xFFFF.FFFF
Flash Memory Protection Read Enable 0
500
0x200
FMPRE0
RW
0xFFFF.FFFF
Flash Memory Protection Read Enable 0
500
0x134
FMPPE0
RW
0xFFFF.FFFF
Flash Memory Protection Program Enable 0
501
0x400
FMPPE0
RW
0xFFFF.FFFF
Flash Memory Protection Program Enable 0
501
0x1D0
BOOTCFG
RO
0xFFFF.FFFE
Boot Configuration
502
0x1E0
USER_REG0
RW
0xFFFF.FFFF
User Register 0
505
0x1E4
USER_REG1
RW
0xFFFF.FFFF
User Register 1
505
0x1E8
USER_REG2
RW
0xFFFF.FFFF
User Register 2
505
0x1EC
USER_REG3
RW
0xFFFF.FFFF
User Register 3
505
7.4
Flash Memory Register Descriptions (Flash Control Offset)
This section lists and describes the Flash Memory registers, in numerical order by address offset.
Registers in this section are relative to the Flash control base address of 0x400F.D000.
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Register 1: Flash Memory Address (FMA), offset 0x000
During a single word write operation, this register contains a 4-byte-aligned address and specifies
where the data is written. During a write operation that uses the write buffer, this register contains
a 128-byte (32-word) aligned address that specifies the start of the 32-word block to be written.
During erase operations, this register contains a 1 KB-aligned CPU byte address and specifies
which block is erased. Note that the alignment requirements must be met by software or the results
of the operation are unpredictable.
Flash Memory Address (FMA)
Base 0x400F.D000
Offset 0x000
Type RW, reset 0x0000.0000
31
30
29
28
27
26
25
24
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
8
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
23
22
21
20
19
18
17
16
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
7
6
5
4
3
2
1
0
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
reserved
Type
Reset
reserved
Type
Reset
RO
0
OFFSET
RW
0
Bit/Field
Name
Type
Reset
Description
31:15
reserved
RO
0x0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
14:0
OFFSET
RW
0x0
Address Offset
Address offset in Flash memory where operation is performed, except
for non-volatile registers (see “Non-Volatile Register
Programming” on page 454 for details on values for this field).
464
June 12, 2014
Texas Instruments-Production Data
Tiva™ TM4C1230C3PM Microcontroller
Register 2: Flash Memory Data (FMD), offset 0x004
This register contains the data to be written during the programming cycle. This register is not used
during erase cycles.
Flash Memory Data (FMD)
Base 0x400F.D000
Offset 0x004
Type RW, reset 0x0000.0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
DATA
Type
Reset
DATA
Type
Reset
Bit/Field
Name
Type
31:0
DATA
RW
Reset
Description
0x0000.0000 Data Value
Data value for write operation.
June 12, 2014
465
Texas Instruments-Production Data
Internal Memory
Register 3: Flash Memory Control (FMC), offset 0x008
When this register is written, the Flash memory controller initiates the appropriate access cycle for
the location specified by the Flash Memory Address (FMA) register (see page 464). If the access
is a write access, the data contained in the Flash Memory Data (FMD) register (see page 465) is
written to the specified address.
This register must be the final register written and initiates the memory operation. The four control
bits in the lower byte of this register are used to initiate memory operations.
Care must be taken not to set multiple control bits as the results of such an operation are
unpredictable.
Flash Memory Control (FMC)
Base 0x400F.D000
Offset 0x008
Type RW, reset 0x0000.0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
WO
0
WO
0
WO
0
WO
0
WO
0
WO
0
WO
0
WO
0
WO
0
WO
0
WO
0
WO
0
WO
0
WO
0
WO
0
WO
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
COMT
MERASE
ERASE
WRITE
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RW
0
RW
0
RW
0
RW
0
WRKEY
Type
Reset
reserved
Type
Reset
Bit/Field
Name
Type
Reset
31:16
WRKEY
WO
0x0000
Description
Flash Memory Write Key
This field contains a write key, which is used to minimize the incidence
of accidental Flash memory writes. Depending on the value of the KEY
bit in the BOOTCFG register, the value 0xA442 or 0x71D5 must be
written into this field for a Flash memory write to occur. Writes to the
FMC register without this WRKEY value are ignored. A read of this field
returns the value 0.
15:4
reserved
RO
0x00
3
COMT
RW
0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
Commit Register Value
This bit is used to commit writes to Flash-memory-resident registers
and to monitor the progress of that process.
Value Description
0
A write of 0 has no effect on the state of this bit.
When read, a 0 indicates that the previous commit access is
complete.
1
Set this bit to commit (write) the register value to a
Flash-memory-resident register.
When read, a 1 indicates that the previous commit access is
not complete.
See “Non-Volatile Register Programming” on page 454 for more
information on programming Flash-memory-resident registers.
466
June 12, 2014
Texas Instruments-Production Data
Tiva™ TM4C1230C3PM Microcontroller
Bit/Field
Name
Type
Reset
2
MERASE
RW
0
Description
Mass Erase Flash Memory
This bit is used to mass erase the Flash main memory and to monitor
the progress of that process.
Value Description
0
A write of 0 has no effect on the state of this bit.
When read, a 0 indicates that the previous mass erase operation
is complete.
1
Set this bit to erase the Flash main memory.
When read, a 1 indicates that the previous mass erase operation
is not complete.
For information on erase time, see “Flash Memory and
EEPROM” on page 1079.
1
ERASE
RW
0
Erase a Page of Flash Memory
This bit is used to erase a page of Flash memory and to monitor the
progress of that process.
Value Description
0
A write of 0 has no effect on the state of this bit.
When read, a 0 indicates that the previous page erase operation
is complete.
1
Set this bit to erase the Flash memory page specified by the
contents of the FMA register.
When read, a 1 indicates that the previous page erase operation
is not complete.
For information on erase time, see “Flash Memory and
EEPROM” on page 1079.
0
WRITE
RW
0
Write a Word into Flash Memory
This bit is used to write a word into Flash memory and to monitor the
progress of that process.
Value Description
0
A write of 0 has no effect on the state of this bit.
When read, a 0 indicates that the previous write update
operation is complete.
1
Set this bit to write the data stored in the FMD register into the
Flash memory location specified by the contents of the FMA
register.
When read, a 1 indicates that the write update operation is not
complete.
For information on programming time, see “Flash Memory and
EEPROM” on page 1079.
June 12, 2014
467
Texas Instruments-Production Data
Internal Memory
Register 4: Flash Controller Raw Interrupt Status (FCRIS), offset 0x00C
This register indicates that the Flash memory controller has an interrupt condition. An interrupt is
sent to the interrupt controller only if the corresponding FCIM register bit is set.
Flash Controller Raw Interrupt Status (FCRIS)
Base 0x400F.D000
Offset 0x00C
Type RO, reset 0x0000.0000
31
30
29
28
27
26
25
24
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
23
22
21
20
19
18
17
16
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
8
7
6
5
4
3
2
1
0
ERIS
PRIS
ARIS
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
reserved
Type
Reset
reserved
Type
Reset
RO
0
RO
0
PROGRIS reserved
RO
0
RO
0
ERRIS
INVDRIS VOLTRIS
RO
0
RO
0
RO
0
reserved
Bit/Field
Name
Type
Reset
Description
31:14
reserved
RO
0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value