Texas Instruments | DMVA3 and DMVA4 DaVinci Digital Media Processor (Rev. B) | Datasheet | Texas Instruments DMVA3 and DMVA4 DaVinci Digital Media Processor (Rev. B) Datasheet

Texas Instruments DMVA3 and DMVA4 DaVinci Digital Media Processor (Rev. B) Datasheet
DMVA3, DMVA4
www.ti.com
SPRS872B – MAY 2013 – REVISED DECEMBER 2013
DMVA3 and DMVA4 DaVinci™ Digital Media Processor
Check for Samples: DMVA3
1 High-Performance System-on-Chip (SoC)
1.1
Features
1234
• High-Performance DaVinci Digital Media
Processors
– Up to 970-MHz ARM® Cortex™-A8 RISC
Processor
– Up to 1940 ARM Cortex-A8 MIPS
• ARM Cortex-A8 Core
– ARMv7 Architecture
• In-Order, Dual-Issue, Superscalar
Processor Core
• NEON™ Multimedia Architecture
• Supports Integer and Floating Point
• Jazelle® RCT Execution Environment
• ARM Cortex-A8 Memory Architecture
– 32KB of Instruction and Data Caches
– 256KB of L2 Cache with ECC
– 64KB of RAM, 48KB of Boot ROM
• 256KB of On-Chip Memory Controller (OCMC)
RAM
• Imaging Subsystem (ISS)
– Camera Sensor Connection
• Parallel Connection for Raw (up to 16-Bit)
and BT.656/BT.1120 (8- or 16-Bit)
• CSI2 Serial Connection
– Image Sensor Interface (ISIF) for Handling
Image and Video Data From the Camera
Sensor
– Image Pipe Interface (IPIPEIF) for Image and
Video Data Connection Between Camera
Sensor, ISIF, IPIPE, and DRAM
– Image Pipe (IPIPE) for Real-Time Image and
Video Processing
– Resizer
• Resizing Image and Video From 1/16x to
8x
• Generating Two Different Resizing
Outputs Concurrently
• Hardware 3A Engine (H3A) for Generating
Key Statistics for 3A (AE, AWB, and AF)
Control
• Vision Coprocessor
• Face Detect (FD) Engine
– Hardware Face Detection for up to 35 Faces
Per Frame
• Programmable High-Definition Video Image
Coprocessing (HDVICP v2) Engine
– Encode, Decode, Transcode Operations
– H.264 BP/MP/HP, MPEG-2, VC-1, MPEG-4
SP/ASP, JPEG/MJPEG
– Fourth-Generation Motion-Compensated
Noise Filter
• Media Controller
– Controls the HDVPSS, HDVICP2, Vision
Coprocessor, and ISS
• Endianness
– ARM Instructions and Data – Little Endian
• HD Video Processing Subsystem (HDVPSS)
– Two 165-MHz HD Video Capture Inputs
• One 16- or 24-Bit Input, Splittable Into
Dual 8-Bit SD Capture Ports
• One 8-, 16-, or 24-Bit HD Input and 8-Bit
SD Input Capture Port
– Two 165-MHz HD Video Display Outputs
• One 16-, 24-, or 30-Bit and One 16- or 24Bit Output
– Component HD Analog Output
– Composite Analog Output
– Digital HDMI 1.3 Transmitter with Integrated
PHY
– Advanced Video Processing Features Such
as Scan, Format, and Rate Conversion
– Three Graphics Layers and Compositors
• 32-Bit DDR2, DDR3, and DDR3L SDRAM
Interface
– Supports up to 400 MHz for DDR2, 533 MHz
for DDR3, and 533 MHz for DDR3L
– Up to Two x 16 Devices, 2GB of Total
Address Space
– Dynamic Memory Manager (DMM)
• Programmable Multi-Zone Memory
Mapping
• Enables Efficient 2D Block Accesses
• Supports Tiled Objects in 0°, 90°, 180°, or
1
2
3
4
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Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Device/BIOS, XDS are trademarks of Texas Instruments.
Skype is a trademark of Skype.
All other trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date. Products conform to
specifications per the terms of the Texas Instruments standard warranty. Production
processing does not necessarily include testing of all parameters.
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DMVA3, DMVA4
SPRS872B – MAY 2013 – REVISED DECEMBER 2013
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270° Orientation and Mirroring
• General-Purpose Memory Controller (GPMC)
– 8- or 16-Bit Multiplexed Address and Data
Bus
– 512MB of Total Address Space Divided
Among up to 8 Chip Selects
– Glueless Interface to NOR Flash, NAND
Flash (BCH/Hamming Error Code Detection),
SRAM and Pseudo-SRAM
– Error Locator Module (ELM) Outside of
GPMC to Provide up to 16-Bit or 512-Byte
Hardware ECC for NAND
– Flexible Asynchronous Protocol Control for
Interface to FPGA, CPLD, ASICs, and More
• Enhanced Direct Memory Access (EDMA)
Controller
– Four Transfer Controllers
– 64 Independent DMA Channels
– 8 QDMA Channels
• Ethernet Switch with Dual 10-, 100-, or
1000-Mbps External Interfaces (EMAC
Software)
– IEEE 802.3 Compliant (3.3-V I/O Only)
– MII/RMII/GMII/RGMII Media Independent
Interfaces
– Management Data I/O (MDIO) Module
– Reset Isolation
– IEEE 1588 Time-Stamping and Industrial
Ethernet Protocols
• Dual USB 2.0 Ports with Integrated PHYs
– USB2.0 High- and Full-Speed Clients
– USB2.0 High-, Full-, and Low-Speed Hosts
– Supports End Points 0-15
• One PCI Express 2.0 Port with Integrated PHY
– Single Port with 1 Lane at 5.0 GT/s
– Configurable as Root Complex or Endpoint
• Eight 32-Bit General-Purpose Timers
(Timer1–8)
• One System Watchdog Timer (WDT0)
• Three Configurable UART/IrDA/CIR Modules
– UART0 with Modem Control Signals
– Supports up to 3.6864 Mbps
– SIR, MIR, FIR (4.0 MBAUD), and CIR
• Four Serial Peripheral Interfaces (SPIs) (up to
48 MHz)
– Each with Four Chip Selects
• Three MMC/SD/SDIO Serial Interfaces (up to
48 MHz)
– Supporting up to 1-, 4-, or 8-Bit Modes
2
• Dual Controller Area Network (DCAN) Module
– CAN Version 2 Part A, B
• Four Inter-Integrated Circuit (I2C Bus™) Ports
• Two Multichannel Audio Serial Ports (McASP)
– Six Serializer Transmit and Receive Ports
– Two Serializer Transmit and Receive Ports
– DIT-Capable For S/PDIF (All Ports)
• Four Audio Tracking Logic (ATL) Modules
• One Serial ATA (SATA) 3.0 Gbps Controller
with Integrated PHY
– Direct Interface to 1 Hard Disk Drive
– Hardware-Assisted Native Command
Queuing (NCQ) from up to 32 Entries
– Supports Port Multiplier and CommandBased Switching
• Real-Time Clock (RTC)
– One-Time or Periodic Interrupt Generation
• Up to 125 General-Purpose I/O (GPIO) Pins
• One Spin Lock Module with up to 128 Hardware
Semaphores
• One Mailbox Module with 12 Mailboxes
• On-Chip ARM ROM Bootloader (RBL)
• Power, Reset, and Clock Management
– SmartReflex™ Technology (Level 2b)
– Multiple Independent Core Power Domains
– Multiple Independent Core Voltage Domains
– Support for Multiple Operating Points per
Voltage Domain
– Clock Enable and Disable Control for
Subsystems and Peripherals
• 32KB of Embedded Trace Buffer™ (ETB™) and
5-pin Trace Interface for Debug
• IEEE 1149.1 (JTAG) Compatible
• 609-Pin Pb-Free BGA Package (AAR Suffix),
0.8-mm Effective Pitch with Via Channel
Technology to Reduce PCB Cost (0.5-mm Ball
Spacing)
• 45-nm CMOS Technology
• 1.8- and 3.3-V Dual Voltage Buffers for General
I/O
High-Performance System-on-Chip (SoC)
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1.2
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SPRS872B – MAY 2013 – REVISED DECEMBER 2013
Applications
Intelligent IP Cameras with Video Analytics Solution
Intelligent Video Encoders and Video Surveillance DVRs
HD Video Conferencing - Skype™ Endpoints
Digital Signage
Media Players and Adapters
Mobile Medical Imaging
Network Projectors
Home Audio and Video Equipment
Embedded Vision
Portable Medical Imaging and Diagnostics and Patient Monitoring
Remote Media Display
Thin Clients
Network Attached Storage
Camcorders
Digital Scanner
Video Doorbells
Webcams
Digital Photo Frames
Digital Video Recorders (DVR)
Network Video Recorders (NVR)
Digital Video Servers (DVS)
Car Black Box Digital Video Recorder
Portable Digital Video Recorder
Intrusion Control Panels with Video
Access Control Panels with Video
High-Performance System-on-Chip (SoC)
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1.3
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Description
DMVA3 and DMVA4 DaVinci Digital Media Processors are a highly integrated, cost-effective, low-power,
programmable platform that leverages TI’s DaVinci processor technology to meet the processing needs of
multichannel Digital Video Recorders (DVR), Network Video Recorders (NVR), HD Video Conferencing Skype endpoints, IP Netcam, Digital Signage, Media Players and Adapters, Mobile Medical Imaging,
Network Projectors, Home Audio and Video Equipment, and similar devices in SD, HD, and 4K x 2K
resolutions. The Programmable High-Definition Video Image Processor of the device supports 1080p60 or
more than 8 channels of D1 real time H.264BP/MP/HP video encode or decode. The included best-inclass H.264 encoder provides high-quality video encode for the lowest possible bit rate under all
conditions, reducing valuable storage space to a minimum. In addition, the device also supports other
video codecs such as MJPEG, MPEG-2, and MPEG-4. The device provides a full set of video
preprocessing and postprocessing functions to ensure the best video quality. The low power consumption
and high performance of the device makes it particularly suitable for portable and automotive applications.
The DMVA3/4 are uniquely capable of running the Fourth-Generation Motion-Compensated Noise Filtering
technology of TI.
The device enables original-equipment manufacturers (OEMs) and original-design manufacturers (ODMs)
to quickly bring to market devices featuring robust operating systems support, rich user interfaces, and
high processing performance through the maximum flexibility of a fully integrated mixed processor
solution. The device also combines programmable video and audio processing with a highly integrated
peripheral set.
The device processors include a high-definition video and imaging coprocessor 2 (HDVICP2), to off-load
many video and imaging processing tasks for common video and imaging algorithms. In addition, the
devices include a custom vision coprocessor with an available suite of TI-developed video analytics
functions. Programmability is provided by an ARM Cortex-A8 RISC CPU with NEON extension and highdefinition video and imaging coprocessors. The ARM lets developers separate control functions from A/V
algorithms programmed on coprocessors, thus reducing the complexity of the system software. The ARM
Cortex-A8 32-bit RISC processor with NEON floating-point extension includes: 32KB of instruction cache;
32KB of data cache; 256KB of L2 cache with ECC; 48KB of boot ROM; and 64KB of RAM.
The rich peripheral set provides the ability to control external peripheral devices and communicate with
external processors. For details on each peripheral, see the related sections in this document and the
associated peripheral reference guides. The peripheral set includes: HD Video Processing Subsystem;
Dual-Port Gigabit Ethernet MACs (10/100/1000 Mbps) (Ethernet Switch) with MII/RMII/GMII/RGMII and
MDIO interface supporting IEEE 1588 Time-Stamping, and Industrial Ethernet Protocols; two USB ports
with integrated 2.0 PHY; PCIe x1 GEN2-Compliant interface; two serializer McASP audio serial ports (with
DIT mode); three UARTs with IrDA and CIR support; four SPI serial interfaces; a CSI2 serial connection;
three MMC/SD/SDIO serial interfaces; four I2C master and slave interfaces; a parallel camera interface
(CAM); a vision coprocessor; up to 125 general-purpose I/Os (GPIOs); eight 32-bit general-purpose
timers; system watchdog timer; DDR2/DDR3/DDR3L SDRAM interface; flexible 8- or 16-bit asynchronous
memory interface; two Controller Area Network (DCAN) modules; one Serial ATA (SATA) 3.0 Gbps
controller with integrated PHY; a Spin Lock; and Mailbox.
Additionally, TI provides a complete set of development tools for the ARM which include C compilers and
a Microsoft® Windows® debugger interface for visibility into source code execution.
4
High-Performance System-on-Chip (SoC)
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1.4
SPRS872B – MAY 2013 – REVISED DECEMBER 2013
Functional Block Diagram
Figure 1-1 shows the functional block diagram of the device.
RAM
64 KB
Noise Filtering Engine
Boot ROM
48 KB
Media Controller Subsystem
256 KB L2 Cache
with ECC
Face Detect (FD)
32 KB
D-Cache
Vision Coprocessor
32 KB
I-Cache
High Definition Video Image
Coprocessor (HDVICP)
NEON
FPU
256 KB On-Chip RAM
ARM Subsystem
CortexTM -A8
CPU
Video Processing
Subsystem
Imaging
Subsystem
Video Capture
Parallel Cam Input
Display Processing
CSI2 Serial Input
HD OSD
SD OSD
IPIPE
HD VENC
SD VENC
Resizer
SD DAC
H3A
HDMI Xmt
ICE Crusher
HD DAC (3)
System Interconnect
Peripherals
Miscellaneous
Real-Time
Clock
PRCM
GP Timer (8)
JTAG
GPIO (4)
Watchdog
Timer
Spinlock
Serial Interfaces
McASP
(2)
DDR2/3
32-bit
SPI (4)
I2C (4)
DCAN (2)
UART (3)
Connectivity
Program/Data Storage
GPMC
+
ELM
SATA
3 Gbp/s
(1 Drive)
EDMA
System Control
EMAC
(R)(G)MII
(2)
MDIO
USB 2.0
Ctrl/PHY
(2)
PCIe 2.0
(One x1
Port)
MMC/SD/
SDIO
(3)
Mailbox
Figure 1-1. Functional Block Diagram
High-Performance System-on-Chip (SoC)
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......... 1
............................................. 1
1.2
Applications .......................................... 3
1.3
Description ........................................... 4
1.4
Functional Block Diagram ........................... 5
Revision History .............................................. 7
2 Device Overview ........................................ 8
2.1
Device Comparison .................................. 8
2.2
Device Characteristics ............................... 8
2.3
Device Compatibility ................................ 10
1
7.2
1.1
..............................................
...........................................
7.5
Interrupts ..........................................
Peripheral Information and Timings .............
8.1
Parameter Information ............................
4
5
6
Reset
139
7.4
Clocking
147
164
Recommended Clock and Control Signal Transition
Behavior ........................................... 165
8.3
Audio Tracking Logic (ATL)
166
8.4
Controller Area Network Interface (DCAN)
167
......................... 12
................................ 12
2.7
Face Detect (FD) Overview ........................ 12
2.8
Spinlock Module Overview ......................... 13
2.9
Mailbox Module Overview .......................... 14
2.10 Memory Map Summary ............................. 15
Device Pins ............................................. 22
3.1
Pin Maps ........................................... 22
3.2
Pin Assignments .................................... 33
3.3
Terminal Functions ................................. 63
Device Configurations .............................. 110
4.1
Control Module Registers ......................... 110
4.2
Boot Modes ....................................... 110
4.3
Pin Multiplexing Control ........................... 116
4.4
Handling Unused Pins ............................ 119
4.5
DeBugging Considerations ........................ 119
System Interconnect ................................ 121
Device Operating Conditions ...................... 125
6.1
Absolute Maximum Ratings ....................... 125
6.2
Recommended Operating Conditions ............. 126
6.3
Reliability Data .................................... 128
8.6
Media Controller Overview
8.7
2.6
HDVICP2 Overview
8.8
8.9
Power, Reset, Clocking, and Interrupts
.........
131
Power, Reset and Clock Management (PRCM)
Module ............................................ 131
176
185
General-Purpose Memory Controller (GPMC) and
Error Location Module (ELM) ..................... 187
8.12
Inter-Integrated Circuit (I2C)
213
8.13
Imaging Subsystem (ISS)
216
8.17
8.18
8.19
8.20
8.21
......................
.........................
DDR2/DDR3/DDR3L Memory Controller ..........
Multichannel Audio Serial Port (McASP) ..........
221
255
MultiMedia Card/Secure Digital/Secure Digital Input
Output (MMC/SD/SDIO) ........................... 260
Peripheral Component Interconnect Express (PCIe)
..................................................... 262
.....................
Serial Peripheral Interface (SPI) ..................
Timers .............................................
Serial ATA Controller (SATA)
265
268
274
Universal Asynchronous Receiver/Transmitter
(UART) ............................................ 276
....................
.............
9.1
Device Support ....................................
9.2
Documentation Support ...........................
9.3
Community Resources ............................
Mechanical ............................................
10.1 Thermal Data for the AAR ........................
10.2 Packaging Information ............................
8.22
10
169
172
High-Definition Multimedia Interface (HDMI) ...... 202
High-Definition Video Processing Subsystem
(HDVPSS) ......................................... 205
8.15
8.16
Electrical Characteristics Over Recommended
Ranges of Supply Voltage and Operating
Temperature (Unless Otherwise Noted) .......... 129
.......................
.......
EDMA .............................................
Emulation Features and Capability ...............
Ethernet MAC Switch (EMAC SW) ................
General-Purpose Input/Output (GPIO) ............
8.10
8.11
8.14
9
161
164
8.2
2.5
7.1
6
8
7.3
8.5
6.4
7
Features
ARM® Cortex™-A8 Microprocessor Unit
(Processor) Subsystem Overview .................. 10
2.4
3
Power .............................................. 131
High-Performance System-on-Chip (SoC)
Universal Serial Bus (USB2.0)
278
Device and Documentation Support
280
Contents
280
282
282
283
283
283
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Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Revision History
SEE
ADDITIONS/MODIFICATIONS/DELETIONS
Added support for 4K x 2K resolution:
•
Section 1.3, Description
•
Section 2.6, HDVICP2 Overview
•
Section 8.13, Imaging Subsystem (ISS)
Global
Added notes specifying OPP100 is supported only on commercial temperature devices to:
•
Section 6.2, Recommended Operating Conditions
•
Section 6.3, Reliability Data
•
Section 7.2.2.1, Dynamic Voltage Frequency Scaling
•
Table 7-3, Device Operating Points (OPPs)
•
Table 7-4, Supported OPP Combinations
Added information on extended temperature to:
•
Section 6.1, Absolute Maximum Ratings
•
Section 6.2, Recommended Operating Conditions
•
Figure 9-1, Device Nomenclature
Power, Reset,
Clocking, and
Interrupts
Changed OPP100 speed from 500 to 600 MHz for ARM Cortex-A8 in Table 7-3, Device Operating Points
(OPPs).
Removed requirement that the maximum voltage difference between CVDD and any other CVDD_x voltage
domain must be < 150 mV.
•
Table 7-4, Supported OPP Combinations
Contents
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DMVA3, DMVA4
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2 Device Overview
2.1
Device Comparison
2.2
Device Characteristics
Table 2-1 provides an overview of the DMVA3/4 DaVinci™ Digital Media Processors, which includes
significant features of the device, including the capacity of on-chip RAM, peripherals, and the package
type with pin count.
Table 2-1. Characteristics of the Processor
HARDWARE FEATURES
DMVA3/4
HD Video Processing Subsystem (HDVPSS)
1 16-/24-bit HD Capture Port or
2 8-bit SD Capture Ports
and
1 8/16/24-bit HD Input Port
and
1 8-bit SD Input Port
and
1 16-/24-/30-bit HD Display Port
or 1 HDMI 1.3 Transmitter
and
1 16-/24-bit HD Display Port
and
1 SD Video DAC
and
3 HD Video DACs
1 Parallel Camera Input for Raw (up to 16bit)
and BT.656/BT.1120 (8/16-bit)
and 1 CSI2 Serial Input
Imaging Subsystem (ISS)
DDR2/3 Memory Controller
16-/32-bit Bus Width
Asynchronous (8-/16-bit bus width)
RAM, NOR, NAND
GPMC + ELM
64 Independent Channels
8 QDMA Channels
EDMA
10/100/1000 Ethernet MAC Switch with Management Data
Input/Output (MDIO)
Peripherals
2 (Supports High- and Full-Speed as a
Device and
High-, Full-, and Low-Speed as a Host)
USB 2.0
PCI Express 2.0
1 Port (5.0 GT/s lane)
Not all peripherals
pins are available at
the same time (for
Timers
more details, see the
Device Configurations
section).
8 (32-bit General purpose)
and
1 (System Watchdog)
3 (with SIR, MIR, FIR, CIR support and
RTS/CTS flow control)
(UART0 Supports Modem Interface)
UART
SPI
4 (Each supporting up to 4 slave devices)
1 (1-bit or 4-bit or 8-bit modes)
and
1 (8-bit mode) or
2 (1-bit or 4-bit modes)
MMC/SD/SDIO
I2C
4 Master or Slave
Media Controller
Controls HDVPSS, HDVICP2, and ISS
2 (6/2 Serializers, each with
Transmit/Receive and DIT capability)
McASP
Controller Area Network (DCAN)
8
1 (with 2 MII/RMII/GMII/RGMII)
Device Overview
2
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Table 2-1. Characteristics of the Processor (continued)
HARDWARE FEATURES
DMVA3/4
Serial ATA (SATA) 3.0 Gbps
1 (Supports 1 Hard Disk Drive)
RTC
1
GPIO
Up to 125 pins
Spinlock Module
1 (up to 128 H/W Semaphores)
Mailbox Module
On-Chip Memory
1 (with 12 Mailboxes)
Size (Bytes)
640KB RAM, 48KB ROM
Organization
ARM
32KB I-cache
32KB D-cache
256KB L2 Cache with ECC
64KB RAM
48KB Boot ROM
ADDITIONAL SHARED MEMORY
256KB On-chip RAM
JTAG BSDL ID
DEVICE_ID Register (address location: 0x4814 0600)
CPU Frequency
MHz
Cycle Time
ns
Core Logic (V)
Voltage
ARM® Cortex™-A8 up to 970 MHz
ARM® Cortex™ -A8 1.03 ns
DEEP SLEEP,
OPP100, OPP120,
Turbo
I/O (V)
Package
16 x 16 mm
Process Technology
μm
Product Status
(1)
(1)
see Section 8.6.3.1, JTAG ID (JTAGID)
Register Description
0.83 V – 1.35 V
1.35 V, 1.5 V, 1.8 V, 3.3 V
609-Pin BGA (AAR) [with Via Channel™
Technology]
0.045 μm
Product Preview (PP),
Advance Information (AI),
or Production Data (PD)
PD
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not necessarily include testing of all parameters.
Device Overview
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2.3
Device Compatibility
2.4
ARM® Cortex™-A8 Microprocessor Unit (Processor) Subsystem Overview
The ARM® Cortex™-A8 Subsystem is designed to allow the ARM Cortex-A8 master control of the device.
In general, the ARM Cortex-A8 is responsible for configuration and control of the various subsystems,
peripherals, and external memories.
The ARM Cortex-A8 Subsystem includes the following features:
• ARM Cortex-A8 RISC processor:
– ARMv7 ISA plus Thumb2™, JazelleX™, and Media Extensions
– NEON™ Floating-Point Unit
– Enhanced Memory Management Unit (MMU)
– Little Endian
– 32KB L1 Instruction Cache
– 32KB L1 Data Cache
– 256KB L2 Cache with Error Correction Code (ECC)
• CoreSight Embedded Trace Module (ETM)
• ARM Cortex-A8 Interrupt Controller (AINTC)
• Embedded PLL Controller (PLL_ARM)
• 64KB Internal RAM
• 48KB Internal Public ROM
Figure 2-1 shows the ARM Cortex-A8 Subsystem for the device.
DEVOSC
L3
PLL_ARM
128
System Events
DMM
128 128
128
128
32
128
32
ARM Cortex-A8
Interrupt Controller
(AINTC)
64
48KB ROM
64
64KB RAM
ARM Cortex-A8
128
Trace
32KB L1I$ 32KB L1D$
256KB L2$
ETM
NEON
Arbiter
Debug
ICECrusher
Figure 2-1. ARM Cortex-A8 Subsystem
2.4.1
ARM Cortex-A8 RISC Processor
The ARM Cortex-A8 processor is a member of ARM Cortex family of general-purpose microprocessors.
This processor is targeted at multi-tasking applications where full memory management, high
performance, low die size, and low power are all important. The ARM Cortex-A8 processor supports the
ARM debug architecture and includes logic to assist in both hardware and software debug. The ARM
Cortex-A8 processor has a Harvard architecture and provides a complete high-performance subsystem,
including:
• ARM Cortex-A8 Integer Core
• Superscalar ARMv7 Instruction Set
• Thumb-2 Instruction Set
• Jazelle RCT Acceleration
• CP14 Debug Coprocessor
10
Device Overview
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•
•
•
•
•
•
•
•
2.4.2
SPRS872B – MAY 2013 – REVISED DECEMBER 2013
CP15 System Control Coprocessor
NEON 64-/128-bit Hybrid SIMD Engine for Multimedia
Enhanced VFPv3 Floating-Point Coprocessor
Enhanced Memory Management Unit (MMU)
Separate Level-1 Instruction and Data Caches
Integrated Level-2 Cache with ECC Support
128-bit Interconnect with Level 3 Fast (L3) System Memories and Peripherals
Embedded Trace Module (ETM).
Embedded Trace Module (ETM)
To support real-time trace, the ARM Cortex-A8 processor provides an interface to enable connection of an
embedded trace module (ETM). The ETM consists of two parts:
• The Trace port which provides real-time trace capability for the ARM Cortex-A8.
• Triggering facilities that provide trigger resources, which include address and data comparators,
counter, and sequencers.
The ARM Cortex-A8 trace port is not pinned out and is, instead, only connected to the system-level
Embedded Trace Buffer (ETB). The ETB has a 32KB buffer memory. ETB enabled debug tools are
required to read/interpret the captured trace data.
2.4.3
ARM Cortex-A8 Interrupt Controller (AINTC)
The ARM Cortex-A8 subsystem contains an interrupt controller (AINTC) that prioritizes all service requests
from the system peripherals and generates either IRQ or FIQ to the ARM Cortex-A8 processor.
2.4.4
ARM Cortex-A8 PLL (PLL_ARM)
The ARM Cortex-A8 subsystem contains an embedded PLL Controller (PLL_ARM) for generating the
subsystem’s clocks from the device Clock input.
2.4.5
ARM Processor Interconnect
The ARM Cortex-A8 processor is connected through the arbiter to the L3 interconnect port. The L3
interconnect port is 128-bits wide and provides access to the other device modules.
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Media Controller Overview
The Media Controller has the responsibility of managing the HDVPSS, HDVICP2, and ISS modules.
2.6
HDVICP2 Overview
The HDVICP2 is a Video Encoder/Decoder hardware accelerator supporting a range of encode, decode,
and transcode operations for most major video codec standards. The main video Codec standards
supported in hardware are MPEG1/2/4 ASP/SP, H.264 BL/MP/HP, VC-1 SP/MP/AP, RV9/10, AVS-1.0,
and ON2 VP6.2/VP7.
Supports up to 4K x 2K @ 15fps, 12Mpixels @ 10fps, 20Mpixels @ 6fps, and so on.
The HDVICP2 hardware accelerator is composed of the following elements:
• Motion estimation acceleration engine
• Loop filter acceleration engine
• Sequencer, including its memories and an interrupt controller
• Intra-prediction estimation engine
• Calculation engine
• Motion compensation engine
• Entropy coder/decoder
• Video Direct Memory Access (DMA)
• Synchronization boxes
• Shared L2 controller
• Local interconnect
2.7
Face Detect (FD) Overview
The device Face Detection (FD) module performs face detection and tracking within a picture stored in
memory. This module is typically used for video encoding, face-based priority auto-focusing, or red-eye
removal. The FD module supports QVGA resolution inputs stored in DRR memory in 8-bit Luma format. In
addition, it uses 51.25KB of DDR for its working memory.
The FD module supports the following features:
• Input image:
– QVGA Input Image Size (H x V = 320 x 240)
– 8-bit Gray Scale Data (0x00 = Black and 0xFF = White)
12
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•
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Detection Capabilities:
– Face Inclination of ±45°
– Face Direction:
• Up/Down: ±30°
• Left/Right: ±60°
– Supported Detection Directions:
• 0° Faces are Vertical
• +90° Faces are Rotated Right by 90°
• -90° Faces are Rotated Left by 90°
• Supported Minimum Face Sizes of 20, 25, 32 or 40 Pixels
– Supported Detection Start Positions:
• X = 0 to 160
• Y = 0 to 120
– Supported Detection Area Sizes:
• X = 160 to 320
• Y = 120 to 240
– Provides Size, Position, Angle, and Confidence Level for Each Face
Spinlock Module Overview
The Spinlock module provides hardware assistance for synchronizing the processes running on multiple
processors in the device:
• ARM Cortex-A8 processor
• Media Controller
The Spinlock module implements 128 spinlocks (or hardware semaphores) that provide an efficient way to
perform a lock operation of a device resource using a single read-access, avoiding the need for a readmodify-write bus transfer of which the programmable cores are not capable.
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Mailbox Module Overview
The device Mailbox module facilitates communication between the ARM Cortex-A8 and the Media
Controller. It consists of twelve mailboxes, each supporting a 1-way communication between two of the
above processors. The sender sends information to the receiver by writing a message to the mailbox
registers. Interrupt signaling is used to notify the receiver that a message has been queued or to notify the
sender about an overflow situation.
The Mailbox module supports the following features (see Figure 2-2):
• 12 mailboxes
• Flexible mailbox-to-processor assignment scheme
• Four-message FIFO depth for each message queue
• 32-bit message width
• Message reception and queue-not-full notification using interrupts
• Three interrupts (one to ARM Cortex-A8 and two to Media Controller)
Mailbox Module
Mailbox
Mailbox
Mailbox
Mailbox
Mailbox
Mailbox
Mailbox
Mailbox
Mailbox
Mailbox
Mailbox
Mailbox
L4
Interconnect
Interrupt
ARM Cortex-A8
Interrupt
Interrupt
Media Controller
Figure 2-2. Mailbox Module Block Diagram
14
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2.10 Memory Map Summary
The device has multiple on-chip memories associated with its processor and subsystems. To help simplify
software development a unified memory map is used where possible to maintain a consistent view of
device resources across all bus masters.
2.10.1 L3 Memory Map
Table 2-2 shows the L3 memory map for all system masters (including Cortex-A8).
For more details on the interconnect topology and connectivity across the L3 and L4 interconnects, see
Section 5.
Table 2-2. L3 Memory Map
START ADDRESS
(HEX)
END ADDRESS
(HEX)
SIZE
DESCRIPTION
0x0000_0000
0x00FF_FFFF
16MB
Reserved (BOOTROM)
0x1000_0000
0x1FFF_FFFF
496MB
General Purpose Memory Controller (GPMC)
External Memory Space
0x2000_0000
0x2FFF_FFFF
256MB
PCIe
0x3000_0000
0x3FFF_FFFF
256MB
Reserved
0x4000_0000
0x4001_FFFF
128KB
Reserved
0x4002_0000
0x4002_BFFF
48KB
ARM Cortex-A8 ROM
(Accessible by ARM Cortex-A8 only)
0x4002_C000
0x402E_FFFF
2832KB
Reserved
0x402F_0000
0x402F_03FF
1KB
Reserved
0x402F_0400
0x402F_FFFF
64KB - 1KB
ARM Cortex-A8 RAM
(Accessible by ARM Cortex-A8 only)
0x4030_0000
0x4033_FFFF
256KB
OCMC SRAM
0x4034_0000
0x407F_FFFF
4864KB
Reserved
0x4080_0000
0x4083_FFFF
256KB
Reserved
0x4084_0000
0x40DF_FFFF
5888KB
Reserved
0x40E0_0000
0x40E0_7FFF
32KB
Reserved
0x40E0_8000
0x40EF_FFFF
992KB
Reserved
0x40F0_0000
0x40F0_7FFF
32KB
Reserved
0x40F0_8000
0x40FF_FFFF
992KB
Reserved
0x4100_0000
0x41FF_FFFF
16MB
Reserved
0x4200_0000
0x43FF_FFFF
32MB
Reserved
0x4400_0000
0x443F_FFFF
4MB
L3 Fast configuration registers
0x4440_0000
0x447F_FFFF
4MB
L3 Mid configuration registers
0x4480_0000
0x44BF_FFFF
4MB
L3 Slow configuration registers
0x44C0_0000
0x45FF_FFFF
20MB
Reserved
0x4600_0000
0x463F_FFFF
4MB
McASP0 Data Peripheral Registers
0x4640_0000
0x467F_FFFF
4MB
McASP1 Data Peripheral Registers
0x4680_0000
0x46BF_FFFF
4MB
Reserved
0x46C0_0000
0x46FF_FFFF
4MB
HDMI
0x4700_0000
0x473F_FFFF
4MB
Reserved
0x4740_0000
0x477F_FFFF
4MB
USB
0x4780_0000
0x4780_FFFF
64KB
Reserved
0x4781_0000
0x4781_1FFF
8KB
MMC/SD/SDIO2 Peripheral Registers
0x4781_2000
0x47BF_FFFF
4MB - 72KB
Reserved
0x47C0_0000
0x47FF FFFF
4MB
Reserved
0x47C0_0000
0x47C0_BFFF
48KB
Reserved
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Table 2-2. L3 Memory Map (continued)
16
START ADDRESS
(HEX)
END ADDRESS
(HEX)
SIZE
0x47C0_C000
0x47C0_C3FF
1KB
Reserved
0x47C0_C400
0x47C0_C7FF
1KB
DDR PHY Registers
0x47C0_C800
0x47C0_CBFF
1KB
Reserved
0x47C0_CC00
0x47C0_CFFF
1KB
Reserved
0x47C0_D000
0x47FF FFFF
4052KB
Reserved
0x4800_0000
0x48FF_FFFF
16MB
L4 Slow Peripheral Domain
(see Table 2-4)
0x4900_0000
0x490F_FFFF
1MB
EDMA TPCC Registers
0x4910_0000
0x497F_FFFF
7MB
Reserved
0x4980_0000
0x498F_FFFF
1MB
EDMA TPTC0 Registers
DESCRIPTION
0x4990_0000
0x499F_FFFF
1MB
EDMA TPTC1 Registers
0x49A0_0000
0x49AF_FFFF
1MB
EDMA TPTC2 Registers
0x49B0_0000
0x49BF_FFFF
1MB
EDMA TPTC3 Registers
0x49C0_0000
0x49FF_FFFF
4MB
Reserved
0x4A00_0000
0x4AFF_FFFF
16MB
L4 Fast Peripheral Domain
(see Table 2-3)
0x4B00_0000
0x4BFF_FFFF
16MB
Emulation Subsystem
0x4C00_0000
0x4CFF_FFFF
16MB
DDR Registers
0x4D00_0000
0x4DFF_FFFF
16MB
Reserved
0x4E00_0000
0x4FFF_FFFF
32MB
DDR DMM Registers
0x5000_0000
0x50FF_FFFF
16MB
GPMC Registers
0x5100_0000
0x51FF_FFFF
16MB
PCIE Registers
0x5200_0000
0x54FF_FFFF
48MB
Reserved
0x5500_0000
0x55FF_FFFF
16MB
Media Controller
0x5600_0000
0x56FF_FFFF
16MB
Reserved
0x5700_0000
0x57FF_FFFF
16MB
Reserved
0x5800_0000
0x58FF_FFFF
16MB
HDVICP2 Configuration
0x5900_0000
0x59FF_FFFF
16MB
HDVICP2 SL2
0x5A00_0000
0x5BFF_FFFF
32MB
Reserved
0x5C00_0000
0x5DFF_FFFF
32MB
ISS
0x5E00_0000
0x5FFF_FFFF
32MB
Reserved
0x6000_0000
0x7FFF_FFFF
512MB
DDR DMM Tiler Window (see Table 2-5)
0x8000_0000
0xFFFF_FFFF
2GB
DDR
0x1 0000 0000
0x1 FFFF FFFF
4GB
DDR DMM Tiler Extended Address Map
(ISS and HDVPSS only) [see Table 2-5]
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2.10.2 L4 Memory Map
The L4 Fast Peripheral Domain and L4 Slow Peripheral Domain regions of the memory maps above are
broken out into Table 2-3 and Table 2-4.
For more details on the interconnect topology and connectivity across the L3 and L4 interconnects, see ,
System Interconnect.
2.10.2.1 L4 Fast Peripheral Memory Map
Table 2-3. L4 Fast Peripheral Memory Map
Cortex-A8 and L3 Masters
END ADDRESS
(HEX)
SIZE
0x4A00_0000
0x4A00_07FF
2KB
L4 Fast Configuration - Address/Protection (AP)
0x4A00_0800
0x4A00_0FFF
2KB
L4 Fast Configuration - Link Agent (LA)
0x4A00_1000
0x4A00_13FF
1KB
L4 Fast Configuration - Initiator Port (IP0)
0x4A00_1400
0x4A00_17FF
1KB
L4 Fast Configuration - Initiator Port (IP1)
0x4A00_1800
0x4A00_1FFF
2KB
Reserved
0x4A00_2000
0x4A07_FFFF
504KB
Reserved
0x4A08_0000
0x4A09_FFFF
128KB
Reserved
0x4A0A_0000
0x4A0A_0FFF
4KB
Reserved
0x4A0A_E000
0x4A0F_FFFF
380KB
Reserved
0x4A10_0000
0x4A10_7FFF
32KB
EMAC SW Peripheral Registers
0x4A10_8000
0x4A10_8FFF
4KB
EMAC SW Interconnect Registers
0x4A14_0000
0x4A14_FFFF
64KB
SATA0 Peripheral Registers
SATA0 Interconnect Registers
START ADDRESS
(HEX)
DEVICE NAME
0x4A15_0000
0x4A15_0FFF
4KB
0x4A15_1000
0x4A17_FFFF
188KB
Reserved
0x4A18_0000
0x4A1A_1FFF
136KB
Reserved
0x4A1A_2000
0x4A1A_3FFF
8KB
Reserved
0x4A1A_4000
0x4A1A_4FFF
4KB
Reserved
0x4A1A_5000
0x4A1A_5FFF
4KB
Reserved
0x4A1A_6000
0x4A1A_6FFF
4KB
Reserved
0x4A1A_7000
0x4A1A_7FFF
4KB
Reserved
0x4A1A_8000
0x4A1A_9FFF
8KB
Reserved
0x4A1A_A000
0x4A1A_AFFF
4KB
Reserved
0x4A1A_B000
0x4A1A_BFFF
4KB
Reserved
0x4A1A_C000
0x4A1A_CFFF
4KB
Reserved
0x4A1A_D000
0x4A1A_DFFF
4KB
Reserved
0x4A1A_E000
0x4A1A_FFFF
8KB
Reserved
0x4A1B_0000
0x4A1B_0FFF
4KB
Reserved
0x4A1B_1000
0x4A1B_1FFF
4KB
Reserved
0x4A1B_2000
0x4A1B_2FFF
4KB
Reserved
0x4A1B_6000
0x4A1B_6FFF
4KB
Reserved
0x4A1B_4000
0x4AFF_FFFF
14632KB
Reserved
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2.10.2.2 L4 Slow Peripheral Memory Map
Table 2-4. L4 Slow Peripheral Memory Map
Cortex-A8 and L3 Masters
18
START ADDRESS
(HEX)
END ADDRESS
(HEX)
SIZE
DEVICE NAME
0x4800_0000
0x4800_07FF
2KB
L4 Slow Configuration – Address/Protection (AP)
0x4800_0800
0x4800_0FFF
2KB
L4 Slow Configuration – Link Agent (LA)
0x4800_1000
0x4800_13FF
1KB
L4 Slow Configuration – Initiator Port (IP0)
0x4800_1400
0x4800_17FF
1KB
L4 Slow Configuration – Initiator Port (IP1)
0x4800_1800
0x4800_1FFF
2KB
Reserved
0x4800_2000
0x4800_7FFF
24KB
Reserved
0x4800_8000
0x4800_8FFF
32KB
Reserved
0x4801_0000
0x4801_0FFF
4KB
Reserved
0x4801_1000
0x4801_1FFF
4KB
Reserved
0x4801_2000
0x4801_FFFF
56KB
Reserved
0x4802_0000
0x4802_0FFF
4KB
UART0 Peripheral Registers
0x4802_1000
0x4802_1FFF
4KB
UART0 Interconnect Registers
0x4802_2000
0x4802_2FFF
4KB
UART1 Peripheral Registers
0x4802_3000
0x4802_3FFF
4KB
UART1 Interconnect Registers
0x4802_4000
0x4802_4FFF
4KB
UART2 Peripheral Registers
0x4802_5000
0x4802_5FFF
4KB
UART2 Interconnect Registers
0x4802_6000
0x4802_7FFF
8KB
Reserved
0x4802_8000
0x4802_8FFF
4KB
I2C0 Peripheral Registers
0x4802_9000
0x4802_9FFF
4KB
I2C0 Interconnect Registers
0x4802_A000
0x4802_AFFF
4KB
I2C1 Peripheral Registers
0x4802_B000
0x4802_BFFF
4KB
I2C1 Interconnect Registers
0x4802_C000
0x4802_DFFF
8KB
Reserved
0x4802_E000
0x4802_EFFF
4KB
TIMER1 Peripheral Registers
0x4802_F000
0x4802_FFFF
4KB
TIMER1 Interconnect Registers
0x4803_0000
0x4803_0FFF
4KB
SPI0 Peripheral Registers
0x4803_1000
0x4803_1FFF
4KB
SPI0 Interconnect Registers
0x4803_2000
0x4803_2FFF
4KB
GPIO0 Peripheral Registers
0x4803_3000
0x4803_3FFF
4KB
GPIO0 Interconnect Registers
0x4803_4000
0x4803_7FFF
16KB
Reserved
0x4803_8000
0x4803_9FFF
8KB
McASP0 CFG Peripheral Registers
0x4803_A000
0x4803_AFFF
4KB
McASP0 CFG Interconnect Registers
0x4803_B000
0x4803_BFFF
4KB
Reserved
0x4803_C000
0x4803_DFFF
8KB
McASP1 CFG Peripheral Registers
0x4803_E000
0x4803_EFFF
4KB
McASP1 CFG Interconnect Registers
0x4803_F000
0x4803_FFFF
4KB
Reserved
0x4804_0000
0x4804_0FFF
4KB
TIMER2 Peripheral Registers
0x4804_1000
0x4804_1FFF
4KB
TIMER2 Interconnect Registers
0x4804_2000
0x4804_2FFF
4KB
TIMER3 Peripheral Registers
0x4804_3000
0x4804_3FFF
4KB
TIMER3 Interconnect Registers
0x4804_4000
0x4804_4FFF
4KB
TIMER4 Peripheral Registers
0x4804_5000
0x4804_5FFF
4KB
TIMER4 Interconnect Registers
0x4804_6000
0x4804_6FFF
4KB
TIMER5 Peripheral Registers
0x4804_7000
0x4804_7FFF
4KB
TIMER5 Interconnect Registers
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Table 2-4. L4 Slow Peripheral Memory Map (continued)
Cortex-A8 and L3 Masters
START ADDRESS
(HEX)
END ADDRESS
(HEX)
SIZE
DEVICE NAME
0x4804_8000
0x4804_8FFF
4KB
TIMER6 Peripheral Registers
0x4804_9000
0x4804_9FFF
4KB
TIMER6 Interconnect Registers
0x4804_A000
0x4804_AFFF
4KB
TIMER7 Peripheral Registers
0x4804_B000
0x4804_BFFF
4KB
TIMER7 Interconnect Registers
0x4804_C000
0x4804_CFFF
4KB
GPIO1 Peripheral Registers
0x4804_D000
0x4804_DFFF
4KB
GPIO1 Interconnect Registers
0x4804_E000
0x4804_FFFF
8KB
Reserved
0x4805_0000
0x4805_1FFF
8KB
Reserved
0x4805_2000
0x4805_2FFF
4KB
Reserved
0x4805_3000
0x4805_FFFF
52KB
Reserved
0x4806_0000
0x4806_FFFF
64KB
MMC/SD/SDIO0 Peripheral Registers
0x4807_0000
0x4807_0FFF
4KB
MMC/SD/SDIO0 Interconnect Registers
0x4807_1000
0x4807_FFFF
60KB
Reserved
0x4808_0000
0x4808_FFFF
64KB
ELM Peripheral Registers
0x4809_0000
0x4809_0FFF
4KB
ELM Interconnect Registers
0x4809_1000
0x4809_FFFF
60KB
Reserved
0x480A_0000
0x480A_FFFF
64KB
Reserved
0x480B_0000
0x480B_0FFF
4KB
Reserved
0x480B_1000
0x480B_FFFF
60KB
Reserved
0x480C_0000
0x480C_0FFF
4KB
RTC Peripheral Registers
0x480C_1000
0x480C_1FFF
4KB
RTC Interconnect Registers
0x480C_2000
0x480C_3FFF
8KB
Reserved
0x480C_4000
0x480C_7FFF
16KB
Reserved
0x480C_8000
0x480C_8FFF
4KB
Mailbox Peripheral Registers
0x480C_9000
0x480C_9FFF
4KB
Mailbox Interconnect Registers
0x480C_A000
0x480C_AFFF
4KB
Spinlock Peripheral Registers
0x480C_B000
0x480C_BFFF
4KB
Spinlock Interconnect Registers
0x480C_C000
0x480F_FFFF
208KB
Reserved
0x4810_0000
0x4811_FFFF
128KB
HDVPSS Peripheral Registers
0x4812_0000
0x4812_0FFF
4KB
HDVPSS Interconnect Registers
0x4812_1000
0x4812_1FFF
4KB
Reserved
0x4812_2000
0x4812_2FFF
4KB
HDMI Peripheral Registers
HDMI Interconnect Registers
0x4812_3000
0x4812_3FFF
4KB
0x4812_4000
0x4813_FFFF
112KB
Reserved
0x4814_0000
0x4815_FFFF
128KB
Control Module Peripheral Registers
0x4816_0000
0x4816_0FFF
4KB
0x4816_1000
0x4817_FFFF
124KB
Control Module Interconnect Registers
Reserved
0x4818_0000
0x4818_2FFF
12KB
PRCM Peripheral Registers
0x4818_3000
0x4818_3FFF
4KB
PRCM Interconnect Registers
0x4818_4000
0x4818_7FFF
16KB
Reserved
0x4818_8000
0x4818_8FFF
4KB
SmartReflex0 Peripheral Registers
0x4818_9000
0x4818_9FFF
4KB
SmartReflex0 Interconnect Registers
0x4818_A000
0x4818_AFFF
4KB
SmartReflex1 Peripheral Registers
0x4818_B000
0x4818_BFFF
4KB
SmartReflex1 Interconnect Registers
0x4818_C000
0x4818_CFFF
4KB
OCP Watchpoint Peripheral Registers
0x4818_D000
0x4818_DFFF
4KB
OCP Watchpoint Interconnect Registers
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Table 2-4. L4 Slow Peripheral Memory Map (continued)
Cortex-A8 and L3 Masters
20
START ADDRESS
(HEX)
END ADDRESS
(HEX)
SIZE
DEVICE NAME
0x4818_E000
0x4818_EFFF
4KB
Reserved
0x4818_F000
0x4818_FFFF
4KB
Reserved
0x4819_0000
0x4819_3FFF
16KB
Reserved
0x4819_4000
0x4819_BFFF
32KB
Reserved
0x4819_C000
0x481F_FFFF
400KB
Reserved
0x4819_C000
0x4819_CFFF
4KB
I2C2 Peripheral Registers
0x4819_D000
0x4819_DFFF
4KB
I2C2 Interconnect Registers
0x4819_E000
0x4819_EFFF
4KB
I2C3 Peripheral Registers
0x4819_F000
0x4819_FFFF
4KB
I2C3 Interconnect Registers
0x481A_0000
0x481A_0FFF
4KB
SPI1 Peripheral Registers
0x481A_1000
0x481A_1FFF
4KB
SPI1 Interconnect Registers
0x481A_2000
0x481A_2FFF
4KB
SPI2 Peripheral Registers
0x481A_3000
0x481A_3FFF
4KB
SPI2 Interconnect Registers
0x481A_4000
0x481A_4FFF
4KB
SPI3 Peripheral Registers
0x481A_5000
0x481A_5FFF
4KB
SPI3 Interconnect Registers
0x481A_6000
0x481A_6FFF
4KB
Reserved
0x481A_7000
0x481A_7FFF
4KB
Reserved
0x481A_8000
0x481A_8FFF
4KB
Reserved
0x481A_9000
0x481A_9FFF
4KB
Reserved
0x481A_A000
0x481A_AFFF
4KB
Reserved
0x481A_B000
0x481A_BFFF
4KB
Reserved
0x481A_C000
0x481A_CFFF
4KB
GPIO2 Peripheral Registers
0x481A_D000
0x481A_DFFF
4KB
GPIO2 Interconnect Registers
0x481A_E000
0x481A_EFFF
4KB
GPIO3 Peripheral Registers
0x481A_F000
0x481A_FFFF
4KB
GPIO3 Interconnect Registers
0x481B_0000
0x481B_FFFF
64KB
Reserved
0x481C_0000
0x481C_0FFF
4KB
Reserved
0x481C_1000
0x481C_1FFF
4KB
TIMER8 Peripheral Registers
0x481C_2000
0x481C_2FFF
4KB
TIMER8 Interconnect Registers
0x481C_3000
0x481C_3FFF
4KB
SYNCTIMER32K Peripheral Registers
0x481C_4000
0x481C_4FFF
4KB
SYNCTIMER32K Interconnect Registers
0x481C_5000
0x481C_5FFF
4KB
PLLSS Peripheral Registers
0x481C_6000
0x481C_6FFF
4KB
PLLSS Interconnect Registers
0x481C_7000
0x481C_7FFF
4KB
WDT0 Peripheral Registers
0x481C_8000
0x481C_8FFF
4KB
WDT0 Interconnect Registers
0x481C_9000
0x481C_9FFF
8KB
Reserved
0x481C_A000
0x481C_BFFF
8KB
Reserved
0x481C_C000
0x481C_DFFF
8KB
DCAN0 Peripheral Registers
0x481C_E000
0x481C_FFFF
8KB
DCAN0 Interconnect Registers
0x481D_0000
0x481D_1FFF
8KB
DCAN1 Peripheral Registers
0x481D_2000
0x481D_3FFF
8KB
DCAN1 Interconnect Registers
0x481D_4000
0x481D_5FFF
8KB
Reserved
0x481D_6000
0x481D_6FFF
4KB
Reserved
0x481D_7000
0x481D_7FFF
4KB
Reserved
0x481D_8000
0x481E_7FFF
64KB
MMC/SD/SDIO1 Peripheral Registers
0x481E_8000
0x481E_8FFF
4KB
MMC/SD/SDIO1 Interconnect Registers
Device Overview
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Table 2-4. L4 Slow Peripheral Memory Map (continued)
Cortex-A8 and L3 Masters
(1)
START ADDRESS
(HEX)
END ADDRESS
(HEX)
SIZE
DEVICE NAME
0x481E_9000
0x481F_FFFF
52KB
Reserved
0x4820_0000
0x4820_0FFF
4KB
Interrupt controller (1)
0x4820_1000
0x4823_FFFF
252KB
0x4824_0000
0x4824_0FFF
4KB
0x4824_1000
0x4827_FFFF
252KB
0x4828_0000
0x4828_0FFF
4KB
0x4828_1000
0x482F_FFFF
508KB
Reserved (1)
0x4830_0000
0x48FF_FFFF
13MB
Reserved
Reserved (1)
MPUSS config register (1)
Reserved (1)
SSM (1)
These regions decoded internally by the Cortex™-A8 Subsystem and are not physically part of the L4 Slow. They are included here only
for reference when considering the Cortex™-A8 Memory Map. For Masters other than the Cortex-A8 these regions are reserved.
2.10.3 DDR DMM TILER Extended Addressing Map
The Tiler includes an additional 4-GBytes of addressing range, enabled by a 33rd address bit, to access
the frame buffer in rotated and mirrored views. shows the details of the Tiler Extended Address Mapping.
This entirety of this additional range is only accessible to the HDVPSS and ISS subsystems. However,
other masters can access any one single view through the 512-MB Tiler region in the base 4GByte
address memory map.
Table 2-5. DDR DMM TILER Extended Address Mapping
BLOCK NAME
START ADDRESS
(HEX)
END ADDRESS
(HEX)
SIZE
Tiler View 0
0x1 0000_0000
0x1 1FFF_FFFF
512MB
Natural 0° View
Tiler View 1
0x1 2000_0000
0x1 3FFF_FFFF
512MB
0° with Vertical Mirror
View
Tiler View 2
0x1 4000_0000
0x1 5FFF_FFFF
512MB
0° with Horizontal Mirror
View
Tiler View 3
0x1 6000_0000
0x1 7FFF_FFFF
512MB
180° View
Tiler View 4
0x1 8000_0000
0x1 9FFF_FFFF
512MB
90° with Vertical Mirror
View
DESCRIPTION
Tiler View 5
0x1 A000_0000
0x1 BFFF_FFFF
512MB
270° View
Tiler View 6
0x1 C000_0000
0x1 DFFF_FFFF
512MB
90° View
Tiler View 7
0x1 E000_0000
0x1 FFFF_FFFF
512MB
90° with Horizontal Mirror
View
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3 Device Pins
3.1
Pin Maps
The following tables show the top view of the package pin assignments in eight pin maps.
22
Device Pins
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Table 3-1. AAR Ball Map [Section Top_Left - Top View]
A
B
VSS
VOUT[0]_R_CR[9]
VOUT[0]_R_CR[8]
VOUT[0]_R_CR[7]
VOUT[0]_R_CR[5]
VOUT[0]_R_CR[4]
C
D
E
UART0_RTS
UART0_DCD
UART0_CTS
UART0_DTR
F
31
30
VOUT[0]_R_CR[6]
DEVOSC_MXI
29
UART0_DSR
28
VOUT[0]_R_CR[3]
VOUT[0]_R_CR[2]
UART0_TXD
VOUT[0]_G_Y_YC[4]
27
VOUT[0]_G_Y_YC[9]
VOUT[0]_G_Y_YC[8]
VOUT[0]_G_Y_YC[6]
VOUT[0]_G_Y_YC[5]
VOUT[0]_G_Y_YC[3]
VOUT[0]_G_Y_YC[7]
VOUT[0]_G_Y_YC[2]
VSS
VSS
VSS
USB1_ID
USB1_VBUSIN
VOUT[0]_B_CB_C[9]
VOUT[0]_B_CB_C[8]
VOUT[0]_B_CB_C[7]
VOUT[0]_B_CB_C[2]
USB1_DP
USB1_DM
26
25
24
23
22
USB0_VBUSIN
21
USB0_DP
USB0_DM
USB1_CE
VOUT[0]_B_CB_C[3]
VSS
VOUT[0]_HSYNC
USB0_ID
USB0_CE
VOUT[0]_AVID
VSSA_USB
VOUT[0]_VSYNC
VSS
20
19
EMU1
18
EMU0
VIN[0]A_D[0]
VIN[0]A_D[1]
VIN[0]A_D[2]
VIN[0]A_D[3]
VIN[0]A_D[4]
DVDD
VIN[0]A_D[5]
VIN[0]A_D[8]_BD[0]
VIN[0]A_D[9]_BD[1]
DVDD
VIN[0]A_D[10]_BD[2]
DVDD
17
16
Ball Map Position
1
2
3
4
5
6
7
8
9
10
Device Pins
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Table 3-2. AAR Ball Map [Section Top_Left_Middle - Top View]
G
H
J
K
L
PCIE_TXN0
PCIE_TXP0
PCIE_RXP0
SATA0_RXN0
M
DEVOSC_MXO
SERDES_CLKN
VSSA_DEVOSC
SERDES_CLKP
PCIE_RXN0
SPI[0]_SCS[0]
RSV40
SPI[1]_SCS[0]
SPI[1]_SCLK
SPI[0]_SCS[1]
RSV3
SPI[0]_D[0]
RSV54
VSS
RSV1
SPI[0]_D[1]
SPI[1]_D[1]
VSS
VSS
UART0_RXD
VDDA_PCIE_1P8
VSS
RSV39
RSV0
VDDA_1P8
VSS
RSV2
VOUT[0]_B_CB_C[6]
LDOCAP_SERDESCLK
VSS
VOUT[0]_B_CB_C[5]
VOUT[0]_B_CB_C[4]
31
30
SATA0_RXP0
29
28
27
26
25
24
23
USB0_DRVVBUS
22
VOUT[0]_CLK
UART2_RXD
21
UART2_TXD
20
VSS
VIN[0]A_D[7]
LDOCAP_ARMRAM
VIN[0]A_D[6]
VDDA_USB_3P3
VDDA_USB0_1P8
VDDA_ARMPLL_1P8
VDDA_USB_3P3
19
LDOCAP_ARM
18
CVDD_ARM
17
RSV4
VIN[0]A_D[11]_BD[3]
VDDA_USB1_1P8
CVDD_ARM
CVDD_ARM
CVDD_ARM
RSV5
VIN[0]A_D[13]_BD[5]
VIN[0]A_D[12]_BD[4]
VDDA_HDDAC_1P1
VSS
VSS
16
Ball Map Position
24
1
2
3
4
5
6
7
8
9
10
Device Pins
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Table 3-3. AAR Ball Map [Section Top_Middle_Middle - Top View]
N
P
SATA0_TXP0
RSV31
SATA0_TXN0
RSV43
R
T
U
TMS
AUXOSC_MXO
RSV33
VSSA_AUXOSC
RTCK
TCLK
SD1_DAT[2]_SDRW
TDI
DVDD
DEVOSC_WAKE
VDDA_SATA0_1P8
I2C[0]_SCL
DVDD
UART0_RIN
DVDD
TDO
VDDA_1P8
DVDD_SD
DVDD_SD
SPI[0]_SCLK
I2C[0]_SDA
TRST
VDDA_HDVICPPLL_1P8
VSS
V
31
30
RSV32
AUXOSC_MXI
29
28
27
26
25
24
23
SPI[1]_D[0]
VDDA_1P8
22
VDDA_1P8
LDOCAP_RAM1
21
VDDS_OSC0_1P8
VSS
VSS
CVDD_HDVICP
CVDD_HDVICP
VDDS_OSC1_1P8
VSS
VSS
CVDD_HDVICP
CVDD_HDVICP
20
VSSA_USB
19
VSSA_USB
VSS
18
VSS
VSS
CVDD
VSS
VSS
CVDD
CVDD
CVDD
CVDD
CVDD
17
VSS
16
VSS
VSS
Ball Map Position
1
2
3
4
5
6
7
8
9
10
Device Pins
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Table 3-4. AAR Ball Map [Section Top_Right_Middle - Top View]
W
Y
AA
AB
AC
SD0_DAT[6]
MCA[0]_AXR[3]
SD0_CLK
SD0_DAT[7]
AD
SD1_DAT[0]
SD0_DAT[2]_SDRW
SD1_CLK
SD0_DAT[3]
SD1_DAT[1]_SDIRQ
SD1_CMD
SD0_CMD
MCA[1]_ACLKR
VSS
SD0_DAT[0]
MCA[0]_ACLKX
SD1_DAT[3]
VSS
MCA[0]_AXR[5]
VSS
SD0_DAT[1]_SDIRQ
MCA[0]_AXR[4]
31
30
MCA[0]_ACLKR
29
28
27
26
25
VSS
VSS
VSS
LDOCAP_HDVICPRAM
MCA[1]_AFSR
VSS
MCA[1]_ACLKX
DDR[0]_A[10]
24
23
LDOCAP_HDVICP
22
CVDD_HDVICP
MCA[1]_AXR[0]
MCA[1]_AFSX
MCA[1]_AXR[1]
DDR[0]_CS[0]
DDR[0]_A[1]
21
20
CVDD
CVDD
DDR[0]_RST
CVDD
CVDD
VDDA_DDRPLL_1P8
DDR[0]_CKE
19
DDR[0]_D[29]
DDR[0]_D[28]
18
VSS
DVDD_DDR[0]
DVDD_DDR[0]
DVDD_DDR[0]
DVDD_DDR[0]
17
VSS
VSS
VSS
VSS
VSS
VSS
16
DDR[0]_D[23]
DDR[0]_D[22]
Ball Map Position
26
1
2
3
4
5
6
7
8
9
10
Device Pins
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Table 3-5. AAR Ball Map [Section Top_Right - Top View]
AE
AF
MCA[0]_AXR[1]
AUD_CLKIN0
MCA[0]_AXR[2]
MCA[0]_AFSR
MCA[0]_AFSX
MCA[0]_AXR[0]
AG
AH
AJ
NMI
CLKIN32
POR
RSTOUT_WD_OUT
AK
AL
31
VSS
30
AUD_CLKIN2
DDR[0]_A[6]
DDR[0]_VTP
DDR[0]_A[9]
DDR[0]_A[8]
29
RESET
28
VSS
DDR[0]_A[4]
27
VSS
AUD_CLKIN1
DDR[0]_A[5]
DDR[0]_A[3]
DDR[0]_CLK
DDR[0]_CLK
DDR[0]_BA[0]
DDR[0]_WE
26
VSS
25
VSS
VSS
VSS
DDR[0]_BA[2]
DDR[0]_RAS
DDR[0]_CAS
VSS
VSS
VSS
RSV34
RSV35
DDR[0]_A[11]
DDR[0]_A[0]
VSS
DDR[0]_BA[1]
DDR[0]_A[7]
DDR[0]_A[12]
DDR[0]_A[2]
DDR[0]_A[13]
DDR[0]_A[14]
24
23
22
DDR[0]_A[15]
21
RSV42
DDR[0]_ODT[0]
DDR[0]_DQS[3]
20
VSS
VSS
DDR[0]_D[31]
VSS
DDR[0]_D[30]
DDR[0]_DQS[3]
VSS
DDR[0]_D[27]
VSS
DDR[0]_D[26]
DDR[0]_D[25]
DDR[0]_D[24]
19
18
DDR[0]_DQM[3]
VREFSSTL_DDR[0]
DDR[0]_DQS[2]
DDR[0]_DQS[2]
17
16
DVDD_DDR[0]
DVDD_DDR[0]
DDR[0]_D[21]
DVDD_DDR[0]
DDR[0]_D[20]
DDR[0]_D[19]
Ball Map Position
1
2
3
4
5
6
7
8
9
10
Device Pins
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Table 3-6. AAR Ball Map [Section Bottom_Left - Top View]
A
B
C
D
E
F
HDMI_CLKP
HDMI_CLKN
HDMI_DN0
HDMI_DP0
HDMI_DN1
VIN[0]A_VSYNC
VIN[0]A_HSYNC
DVDD_C
VIN[0]A_D[14]_BD[6]
HDMI_DN2
HDMI_DP1
VIN[0]A_DE
DVDD_C
VIN[0]A_D[17]
DVDD_C
HDMI_DP2
TV_RSET
15
14
13
12
11
10
TV_VFB0
9
HDDAC_A
TV_OUT0
VIN[0]A_CLK
HDDAC_VSYNC
HDDAC_HSYNC
VIN[0]A_D[20]
HDDAC_B
HDDAC_C
VSSA_VDAC
VSS
VSS
VSS
HDDAC_VREF
VIN[0]A_D[21]
VIN[0]A_D[19]
VSS
VSS
VIN[0]B_DE
VOUT[1]_B_CB_C[1]
VOUT[1]_VSYNC
VOUT[1]_CLK
VOUT[1]_B_CB_C[4]
8
7
6
VIN[0]A_D[22]
HDDAC_IREF
VIN[0]A_D[23]
VIN[0]A_DE
5
4
VIN[0]A_FLD
3
VIN[0]B_FLD
VOUT[0]_FLD
VOUT[1]_G_Y_YC[1]
VOUT[1]_G_Y_YC[0]
2
VOUT[1]_R_CR[0]
I2C[1]_SCL
VOUT[1]_R_CR[1]
I2C[1]_SDA
VOUT[1]_HSYNC
VOUT[1]_B_CB_C[3]
1
VSS
VOUT[1]_AVID
Ball Map Position
28
1
2
3
4
5
6
7
8
9
10
Device Pins
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Table 3-7. AAR Ball Map [Section Bottom_Left_Middle - Top View]
G
H
J
K
L
M
15
VDDA_HDDACREF_1P8
14
VDDA_VDAC_1P8
VDDA_HDMI_1P8
VDDA_HDDAC_1P8
CVDD_ARM
VDDA_VIDPLL_1P8
CVDD_ARM
13
DVDD_C
VIN[0]A_D[15]_BD[7]
DVDD_C
VIN[0]B_CLK
VIN[0]A_FLD
12
VOUT[1]_R_CR[6]
11
VIN[0]A_D[16]
VOUT[1]_R_CR[5]
VIN[0]A_D[18]
VOUT[1]_R_CR[7]
10
VOUT[1]_FLD
9
VSSA_HDMI
VOUT[1]_B_CB_C[0]
VOUT[1]_G_Y_YC[7]
VSS
VSSA_HDMI
VOUT[1]_G_Y_YC[4]
VOUT[1]_B_CB_C[2]
VSS
VSS
VSS
DVDD
VSS
VOUT[1]_G_Y_YC[3]
VOUT[1]_R_CR[2]
DVDD
VSS
VOUT[1]_B_CB_C[9]
DVDD
GPMC_A[19]
VSS
VOUT[1]_G_Y_YC[6]
VOUT[1]_R_CR[3]
DVDD
VOUT[1]_B_CB_C[8]
VOUT[1]_B_CB_C[7]
VOUT[1]_G_Y_YC[8]
GPMC_A[18]
VOUT[1]_B_CB_C[6]
VOUT[1]_R_CR[4]
VOUT[1]_G_Y_YC[2]
GPMC_A[17]
8
7
6
5
4
3
2
VOUT[1]_R_CR[8]
VOUT[1]_R_CR[9]
VOUT[1]_G_Y_YC[5]
VOUT[1]_G_Y_YC[9]
1
VOUT[1]_B_CB_C[5]
GPMC_A[16]
Ball Map Position
1
2
3
4
5
6
7
8
9
10
Device Pins
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Table 3-8. AAR Ball Map [Section Bottom_Middle_Middle - Top View]
N
P
R
T
U
V
CVDD
CVDD
VSS
CVDD
CVDD
VSS
VSS
VSS
VSS
VSSA_CSI2
15
14
VSS
13
VSS
CVDD
12
VSS
VSS
VSS
CVDD
CVDD
VSS
VSS
VSS
CVDD
CVDD
LDOCAP_RAM0
VDDA_AUDIOPLL_1P8
GPMC_D[3]
CSI2_DY[4]
11
DVDD
10
DVDD
VDDA_1P8
9
GPMC_A[20]
VDDA_1P8
VDDA_1P8
GPMC_A[23]
GPMC_D[9]
DVDD_GPMC
DVDD_GPMC
GPMC_D[10]
DVDD_GPMC
DVDD_GPMC
GPMC_D[5]
GPMC_D[11]
DVDD_GPMC
GPMC_D[12]
GPMC_D[6]
GPMC_D[13]
GPMC_D[7]
GPMC_D[14]
GPMC_D[8]
8
7
6
5
4
3
2
GPMC_A[22]
GPMC_D[15]
1
GPMC_A[21]
CSI2_DX[4]
Ball Map Position
30
1
2
3
4
5
6
7
8
9
10
Device Pins
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SPRS872B – MAY 2013 – REVISED DECEMBER 2013
Table 3-9. AAR Ball Map [Section Bottom_Right_Middle - Top View]
W
Y
AA
AB
AC
AD
VSS
DVDD_DDR[0]
DVDD_DDR[0]
DDR[0]_D[18]
DVDD_DDR[0]
15
14
CVDD
CVDD
VSS
CVDD
CVDD
VSS
13
DDR[0]_D[13]
12
GPMC_CS[1]
DDR[0]_D[11]
GPMC_ ADV _ALE
LDOCAP_RAM2
DDR[0]_D[10]
11
VDDA_L3L4_1P8
GPMC_BE[1]
10
VDDA_CSI2_1P8
9
GPMC_D[4]
GPMC_CLK
GPMC_CS[0]
DDR[0]_D[5]
8
GPMC_WAIT[0]
GPMC_OE_RE
SD2_DAT[2]_SDRW
RSV41
DVDD_RGMII
DVDD_RGMII
VSSA_CSI2
VSS
GPMC_D[0]
DVDD_RGMII
SD2_SCLK
VSS
DVDD_RGMII
GPMC_WE
SD2_DAT[1]_SDIRQ
VSS
GPMC_D[1]
DVDD_RGMII
SD2_DAT[0]
VSS
GPMC_D[2]
GPMC_ BE[0] _CLE
GPMC_CS[2]
VSS
CSI2_DX[3]
CSI2_DY[2]
CSI2_DY[0]
SD2_DAT[4]
7
6
5
4
3
2
CSI2_DX[2]
CSI2_DX[0]
CSI2_DX[1]
CSI2_DY[1]
1
CSI2_DY[3]
SD2_DAT[3]
Ball Map Position
1
2
3
4
5
6
7
8
9
10
Device Pins
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Table 3-10. AAR Ball Map [Section Bottom_Right - Top View]
AE
AF
AG
AH
AJ
AK
AL
DVDD_DDR[0]
DDR[0]_D[17]
DVDD_DDR[0]
DDR[0]_D[16]
DDR[0]_DQM[2]
DDR[0]_DQS[1]
DDR[0]_DQS[1]
DDR[0]_D[15]
DDR[0]_D[14]
15
14
13
DDR[0]_D[12]
12
VSS
VSS
DDR[0]_D[9]
VSS
DDR[0]_D[8]
DDR[0]_DQM[1]
DDR[0]_D[7]
DDR[0]_D[6]
VSS
DDR[0]_D[4]
DDR[0]_D[3]
DDR[0]_DQS[0]
DDR[0]_DQS[0]
11
10
DDR[0]_D[2]
9
VSS
8
DDR[0]_D[0]
DDR[0]_DQM[0]
VSS
EMAC[0]_MTXEN/
EMAC[1]_RGRXD[2]
EMAC[0]_MTXD[7]/
EMAC[1]_RGTXD[3]
EMAC[0]_MTXD[6]/
EMAC[1]_RGRXD[0]
EMAC[0]_MTXD[5]/
EMAC[1]_RGTXC
EMAC[0]_MTXD[4]/
EMAC[1]_RGTXD[2]
VSS
VSS
VSS
VSS
EMAC[0]_MTXD[1]/
EMAC[1]_RGTXD[1]
EMAC[0]_MTXD[2]/
EMAC[1]_RGTXCTL
EMAC[0]_MRXDV/
EMAC[1]_RGRXD[1]
EMAC[0]_MTXD[0]/
EMAC[1]_RGRXD[3]
EMAC[0]_GMTCLK/
EMAC[1]_RGRXC
EMAC[0]_MRXD[7]/
EMAC[0]_RGTXD[1]
EMAC[0]_MRXD[6]/
EMAC[0]_RGTXD[2]
7
6
VSS
GPMC_CS[4]
5
VSS
4
DDR[0]_D[1]
EMAC[0]_MTXD[3]/
EMAC[1]_RGTXD[0]
EMAC[0]_MTCLK/
EMAC[0]_RGRXC
SD2_DAT[7]
MDIO
EMAC[0]_MRXD[5]/
EMAC[0]_RGTXD[3]
3
2
SD2_DAT[6]
GPMC_CS[3]
MDCLK
EMAC[0]_MCRS/
EMAC[0]_RGRXD[2]
EMAC_RMREFCLK
EMAC[0]_MCOL/
EMAC[0]_RGRXCTL
1
SD2_DAT[5]
EMAC[0]_MRXER/
EMAC[0]_RGTXCTL
EMAC[0]_MRXD[4]/
EMAC[0]_RGRXD[3]
EMAC[0]_MRXD[3]/
EMAC[1]_RGRXCTL
EMAC[0]_MRXD[2]/
EMAC[0]_RGRXD[1]
EMAC[0]_MRXD[0]/
EMAC[0]_RGTXD[0]
EMAC[0]_MRXD[1]/
EMAC[0]_RGRXD[0]
EMAC[0]_MRCLK/
EMAC[0]_RGTXC
VSS
Ball Map Position
32
1
2
3
4
5
6
7
8
9
10
Device Pins
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3.2
SPRS872B – MAY 2013 – REVISED DECEMBER 2013
Pin Assignments
The following table provides a summary of the device signal ball assignments and characteristics.
1. BALL NUMBER: Package ball number(s) associated with each signal(s).
2. BALL NAME: The name of the package ball or terminal.
Note: The table does not take into account subsystem terminal multiplexing options.
3. SIGNAL NAME: The signal name for that ball in the mode being used.
4. PINCNTL REGISTER NAME AND ADDRESS: The name and address of the register that controls the
pin’s internal pull-up/down resistors and multiplexing options.
5. PINCNTL DEFAULT VALUE: The default value of the PINCNTL after reset.
6. MODE: The setting of the MUXMODE[10:0] bits in the associated PINCNTL register that selects this
multiplexed signal option.
7. TYPE: Signal direction
– I = Input
– O = Output
– I/O = Input/Output
– D = Open drain
– DS = Differential
– A = Analog
– PWR = Power
– GND = Ground
8. DSIS: The deselected input state (DSIS) indicates the state driven on the peripheral input (logic "0",
logic "1", or "PIN" level) when the peripheral pin function is not selected by any of the PINCNTLx
registers.
– 0: Logic 0 driven on the peripheral's input signal port.
– 1: Logic 1 driven on the peripheral's input signal port.
– PIN: The value on the pin is driven to the peripheral's input signal port.
9. BALL RESET STATE: The state of the ball during device reset.
– 0: The buffer drives VOL (pulldown/pullup resistor not activated)
0(PD): The buffer drives VOL with an active pulldown resistor
– 1: The buffer drives VOH (pulldown/pullup resistor not activated)
1(PU): The buffer drives VOH with an active pullup resistor
– Z: High-impedance.
– L: High-impedance with an active pulldown resistor
– H : High-impedance with an active pullup resistor
10. BALL RESET REL. STATE: The state of the ball following the device coming out of reset.
– 0: The buffer drives VOL (pulldown/pullup resistor not activated)
0(PD): The buffer drives VOL with an active pulldown resistor
– 1: The buffer drives VOH (pulldown/pullup resistor not activated)
1(PU): The buffer drives VOH with an active pullup resistor
– Z: High-impedance.
– L: High-impedance with an active pulldown resistor
– H : High-impedance with an active pullup resistor
11. POWER: The voltage supply that powers the terminal’s I/O buffers.
12. HYS: Indicates if the input buffer is with hysteresis.
13. BUFFER TYPE: Drive strength of the associated output buffer.
Device Pins
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Table 3-11. Ball Characteristics (AAR Package)
BALL NUMBER [1]
AF31
BALL NAME [2]
AUD_CLKIN0
SIGNAL NAME [3]
AUD_CLKIN0
AUD_CLKIN1
PIN
I/O
PIN
ATL_CLKOUT1
0x10
O
PIN
ATL_CLKOUT0
0x20
O
PIN
USB1_DRVVBUS
0x80
O
PIN
0x01
I
PIN
0x04
I/O
PIN
ATL_CLKOUT2
0x10
O
PIN
EDMA_EVT3
0x20
I
PIN
TIM2_IO
0x40
I/O
PIN
GP0[8]
0x80
I/O
PIN
0x01
I
PIN
0x10
O
PIN
EDMA_EVT2
0x20
I
PIN
TIM3_IO
0x40
I/O
PIN
GP0[9]
0x80
I/O
PIN
MCA[1]_AHCLKX
AG30
AUD_CLKIN2
TYPE [7] DSIS [8]
I
AUD_CLKIN2
ATL_CLKOUT3
PINCNTL15 /
0x4814 0838
PINCNTL16 /
0x4814 083C
0x000C 0000
MODE
[6]
0x04
AUD_CLKIN1
PINCNTL14 /
0x4814 0834
PINCNTL
DEFAULT
VALUE[5]
0x01
MCA[0]_AHCLKX
AF27
PINCNTL
REGISTER NAME
AND ADDRESS[4]
0x000C 0000
0x000C 0000
BALL
RESET
STATE [9]
BALL
RESET
REL.
STATE [10]
POWER [11]
L
L
DVDD
L
L
DVDD
L
L
DVDD
V30
AUXOSC_MXI
AUXOSC_MXI
NA /
NA
NA
0x01
I
NA
NA
NA
VDDS_OSC1_1P8
U31
AUXOSC_MXO
AUXOSC_MXO
NA /
NA
NA
0x01
O
NA
NA
NA
VDDS_OSC1_1P8
AJ31
CLKIN32
CLKIN32
PINCNTL259 /
0x4814 0C08
0x0004 0000
0x01
I
PIN
L
L
DVDD
0x04
O
PIN
TIM3_IO
0x40
I/O
PIN
GP3[31]
0x80
I/O
PIN
CLKOUT0
AB2
CSI2_DX[0]
CSI2_DX[0]
NA /
NA
NA
0x01
I
NA
NA
NA
VDDA_CSI2_1P8
AA1
CSI2_DX[1]
CSI2_DX[1]
NA /
NA
NA
0x01
I
NA
NA
NA
VDDA_CSI2_1P8
AA2
CSI2_DX[2]
CSI2_DX[2]
NA /
NA
NA
0x01
I
NA
NA
NA
VDDA_CSI2_1P8
W2
CSI2_DX[3]
CSI2_DX[3]
NA /
NA
NA
0x01
I
NA
NA
NA
VDDA_CSI2_1P8
V1
CSI2_DX[4]
CSI2_DX[4]
NA /
NA
NA
0x01
I
NA
NA
NA
VDDA_CSI2_1P8
AC2
CSI2_DY[0]
CSI2_DY[0]
NA /
NA
NA
0x01
I
NA
NA
NA
VDDA_CSI2_1P8
AB1
CSI2_DY[1]
CSI2_DY[1]
NA /
NA
NA
0x01
I
NA
NA
NA
VDDA_CSI2_1P8
Y2
CSI2_DY[2]
CSI2_DY[2]
NA /
NA
NA
0x01
I
NA
NA
NA
VDDA_CSI2_1P8
34
Device Pins
HYS [12]
BUFFER
TYPE [13]
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SPRS872B – MAY 2013 – REVISED DECEMBER 2013
Table 3-11. Ball Characteristics (AAR Package) (continued)
BALL NUMBER [1]
BALL NAME [2]
SIGNAL NAME [3]
PINCNTL
REGISTER NAME
AND ADDRESS[4]
PINCNTL
DEFAULT
VALUE[5]
MODE
[6]
TYPE [7] DSIS [8]
BALL
RESET
STATE [9]
BALL
RESET
REL.
STATE [10]
POWER [11]
W1
CSI2_DY[3]
CSI2_DY[3]
NA /
NA
NA
0x01
I
NA
NA
NA
VDDA_CSI2_1P8
V2
CSI2_DY[4]
CSI2_DY[4]
NA /
NA
NA
0x01
I
NA
NA
NA
VDDA_CSI2_1P8
P15, P17, R15,
R17, T13, T17,
T18, U11, U12,
U15, U17, V11,
V12, V15, V17,
W13, W14, W19,
W20, Y13, Y14,
Y19, Y20
CVDD
CVDD
NA /
NA
NA
NA
PWR
NA
NA
NA
NA
K17, L17, L18,
M13, M14, M17
CVDD_ARM
CVDD_ARM
NA /
NA
NA
NA
PWR
NA
NA
NA
NA
U20, U21, V20,
V21, W22
CVDD_HDVICP
CVDD_HDVICP
NA /
NA
NA
NA
PWR
NA
NA
NA
NA
AL24
DDR[0]_A[0]
DDR[0]_A[0]
NA /
NA
NA
0x01
O
NA
H
1
DVDD_DDR[0]
AC22
DDR[0]_A[1]
DDR[0]_A[1]
NA /
NA
NA
0x01
O
NA
H
1
DVDD_DDR[0]
AJ23
DDR[0]_A[2]
DDR[0]_A[2]
NA /
NA
NA
0x01
O
NA
H
1
DVDD_DDR[0]
AJ27
DDR[0]_A[3]
DDR[0]_A[3]
NA /
NA
NA
0x01
O
NA
H
1
DVDD_DDR[0]
AK28
DDR[0]_A[4]
DDR[0]_A[4]
NA /
NA
NA
0x01
O
NA
H
1
DVDD_DDR[0]
AH27
DDR[0]_A[5]
DDR[0]_A[5]
NA /
NA
NA
0x01
O
NA
H
1
DVDD_DDR[0]
AK30
DDR[0]_A[6]
DDR[0]_A[6]
NA /
NA
NA
0x01
O
NA
H
1
DVDD_DDR[0]
AG23
DDR[0]_A[7]
DDR[0]_A[7]
NA /
NA
NA
0x01
O
NA
H
1
DVDD_DDR[0]
AL29
DDR[0]_A[8]
DDR[0]_A[8]
NA /
NA
NA
0x01
O
NA
H
1
DVDD_DDR[0]
AK29
DDR[0]_A[9]
DDR[0]_A[9]
NA /
NA
NA
0x01
O
NA
H
1
DVDD_DDR[0]
AD23
DDR[0]_A[10]
DDR[0]_A[10]
NA /
NA
NA
0x01
O
NA
H
1
DVDD_DDR[0]
AK24
DDR[0]_A[11]
DDR[0]_A[11]
NA /
NA
NA
0x01
O
NA
H
1
DVDD_DDR[0]
AH23
DDR[0]_A[12]
DDR[0]_A[12]
NA /
NA
NA
0x01
O
NA
H
1
DVDD_DDR[0]
AK23
DDR[0]_A[13]
DDR[0]_A[13]
NA /
NA
NA
0x01
O
NA
H
1
DVDD_DDR[0]
AL23
DDR[0]_A[14]
DDR[0]_A[14]
NA /
NA
NA
0x01
O
NA
H
1
DVDD_DDR[0]
AK22
DDR[0]_A[15]
DDR[0]_A[15]
NA /
NA
NA
0x01
O
NA
H
1
DVDD_DDR[0]
HYS [12]
BUFFER
TYPE [13]
Device Pins
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Table 3-11. Ball Characteristics (AAR Package) (continued)
BALL NUMBER [1]
BALL NAME [2]
SIGNAL NAME [3]
PINCNTL
REGISTER NAME
AND ADDRESS[4]
PINCNTL
DEFAULT
VALUE[5]
MODE
[6]
TYPE [7] DSIS [8]
BALL
RESET
STATE [9]
BALL
RESET
REL.
STATE [10]
POWER [11]
AK26
DDR[0]_BA[0]
DDR[0]_BA[0]
NA /
NA
NA
0x01
O
NA
H
1
DVDD_DDR[0]
AF23
DDR[0]_BA[1]
DDR[0]_BA[1]
NA /
NA
NA
0x01
O
NA
H
1
DVDD_DDR[0]
AH25
DDR[0]_BA[2]
DDR[0]_BA[2]
NA /
NA
NA
0x01
O
NA
H
1
DVDD_DDR[0]
AK25
DDR[0]_CAS
DDR[0]_CAS
NA /
NA
NA
0x01
O
NA
H
1
DVDD_DDR[0]
AD20
DDR[0]_CKE
DDR[0]_CKE
NA /
NA
NA
0x01
O
NA
L
L
DVDD_DDR[0]
AL27
DDR[0]_CLK
DDR[0]_CLK
NA /
NA
NA
0x01
O
NA
L
0
DVDD_DDR[0]
AK27
DDR[0]_CLK
DDR[0]_CLK
NA /
NA
NA
0x01
O
NA
H
1
DVDD_DDR[0]
AB21
DDR[0]_CS[0]
DDR[0]_CS[0]
NA /
NA
NA
0x01
O
NA
H
1
DVDD_DDR[0]
AL9
DDR[0]_D[0]
DDR[0]_D[0]
NA /
NA
NA
0x01
I/O
NA
L
L
DVDD_DDR[0]
AK9
DDR[0]_D[1]
DDR[0]_D[1]
NA /
NA
NA
0x01
I/O
NA
L
L
DVDD_DDR[0]
AK10
DDR[0]_D[2]
DDR[0]_D[2]
NA /
NA
NA
0x01
I/O
NA
L
L
DVDD_DDR[0]
AJ11
DDR[0]_D[3]
DDR[0]_D[3]
NA /
NA
NA
0x01
I/O
NA
L
L
DVDD_DDR[0]
AH11
DDR[0]_D[4]
DDR[0]_D[4]
NA /
NA
NA
0x01
I/O
NA
L
L
DVDD_DDR[0]
AD9
DDR[0]_D[5]
DDR[0]_D[5]
NA /
NA
NA
0x01
I/O
NA
L
L
DVDD_DDR[0]
AF11
DDR[0]_D[6]
DDR[0]_D[6]
NA /
NA
NA
0x01
I/O
NA
L
L
DVDD_DDR[0]
AL12
DDR[0]_D[7]
DDR[0]_D[7]
NA /
NA
NA
0x01
I/O
NA
L
L
DVDD_DDR[0]
AJ12
DDR[0]_D[8]
DDR[0]_D[8]
NA /
NA
NA
0x01
I/O
NA
L
L
DVDD_DDR[0]
AG12
DDR[0]_D[9]
DDR[0]_D[9]
NA /
NA
NA
0x01
I/O
NA
L
L
DVDD_DDR[0]
AD12
DDR[0]_D[10]
DDR[0]_D[10]
NA /
NA
NA
0x01
I/O
NA
L
L
DVDD_DDR[0]
AB12
DDR[0]_D[11]
DDR[0]_D[11]
NA /
NA
NA
0x01
I/O
NA
L
L
DVDD_DDR[0]
AK13
DDR[0]_D[12]
DDR[0]_D[12]
NA /
NA
NA
0x01
I/O
NA
L
L
DVDD_DDR[0]
AC13
DDR[0]_D[13]
DDR[0]_D[13]
NA /
NA
NA
0x01
I/O
NA
L
L
DVDD_DDR[0]
AL14
DDR[0]_D[14]
DDR[0]_D[14]
NA /
NA
NA
0x01
I/O
NA
L
L
DVDD_DDR[0]
36
Device Pins
HYS [12]
BUFFER
TYPE [13]
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SPRS872B – MAY 2013 – REVISED DECEMBER 2013
Table 3-11. Ball Characteristics (AAR Package) (continued)
BALL NUMBER [1]
BALL NAME [2]
SIGNAL NAME [3]
PINCNTL
REGISTER NAME
AND ADDRESS[4]
PINCNTL
DEFAULT
VALUE[5]
MODE
[6]
TYPE [7] DSIS [8]
BALL
RESET
STATE [9]
BALL
RESET
REL.
STATE [10]
POWER [11]
AK14
DDR[0]_D[15]
DDR[0]_D[15]
NA /
NA
NA
0x01
I/O
NA
L
L
DVDD_DDR[0]
AH15
DDR[0]_D[16]
DDR[0]_D[16]
NA /
NA
NA
0x01
I/O
NA
L
L
DVDD_DDR[0]
AF15
DDR[0]_D[17]
DDR[0]_D[17]
NA /
NA
NA
0x01
I/O
NA
L
L
DVDD_DDR[0]
AD15
DDR[0]_D[18]
DDR[0]_D[18]
NA /
NA
NA
0x01
I/O
NA
L
L
DVDD_DDR[0]
AK16
DDR[0]_D[19]
DDR[0]_D[19]
NA /
NA
NA
0x01
I/O
NA
L
L
DVDD_DDR[0]
AJ16
DDR[0]_D[20]
DDR[0]_D[20]
NA /
NA
NA
0x01
I/O
NA
L
L
DVDD_DDR[0]
AG16
DDR[0]_D[21]
DDR[0]_D[21]
NA /
NA
NA
0x01
I/O
NA
L
L
DVDD_DDR[0]
AD16
DDR[0]_D[22]
DDR[0]_D[22]
NA /
NA
NA
0x01
I/O
NA
L
L
DVDD_DDR[0]
AC16
DDR[0]_D[23]
DDR[0]_D[23]
NA /
NA
NA
0x01
I/O
NA
L
L
DVDD_DDR[0]
AK19
DDR[0]_D[24]
DDR[0]_D[24]
NA /
NA
NA
0x01
I/O
NA
L
L
DVDD_DDR[0]
AJ19
DDR[0]_D[25]
DDR[0]_D[25]
NA /
NA
NA
0x01
I/O
NA
L
L
DVDD_DDR[0]
AH19
DDR[0]_D[26]
DDR[0]_D[26]
NA /
NA
NA
0x01
I/O
NA
L
L
DVDD_DDR[0]
AF19
DDR[0]_D[27]
DDR[0]_D[27]
NA /
NA
NA
0x01
I/O
NA
L
L
DVDD_DDR[0]
AD19
DDR[0]_D[28]
DDR[0]_D[28]
NA /
NA
NA
0x01
I/O
NA
L
L
DVDD_DDR[0]
AC19
DDR[0]_D[29]
DDR[0]_D[29]
NA /
NA
NA
0x01
I/O
NA
L
L
DVDD_DDR[0]
AJ20
DDR[0]_D[30]
DDR[0]_D[30]
NA /
NA
NA
0x01
I/O
NA
L
L
DVDD_DDR[0]
AG20
DDR[0]_D[31]
DDR[0]_D[31]
NA /
NA
NA
0x01
I/O
NA
L
L
DVDD_DDR[0]
AL8
DDR[0]_DQM[0]
DDR[0]_DQM[0]
NA /
NA
NA
0x01
O
NA
H
1
DVDD_DDR[0]
AK12
DDR[0]_DQM[1]
DDR[0]_DQM[1]
NA /
NA
NA
0x01
O
NA
H
1
DVDD_DDR[0]
AJ15
DDR[0]_DQM[2]
DDR[0]_DQM[2]
NA /
NA
NA
0x01
O
NA
H
1
DVDD_DDR[0]
AK18
DDR[0]_DQM[3]
DDR[0]_DQM[3]
NA /
NA
NA
0x01
O
NA
H
1
DVDD_DDR[0]
AL11
DDR[0]_DQS[0]
DDR[0]_DQS[0]
NA /
NA
NA
0x01
I/O
NA
L
0
DVDD_DDR[0]
AK11
DDR[0]_DQS[0]
DDR[0]_DQS[0]
NA /
NA
NA
0x01
I/O
NA
H
1
DVDD_DDR[0]
HYS [12]
BUFFER
TYPE [13]
Device Pins
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DMVA3, DMVA4
SPRS872B – MAY 2013 – REVISED DECEMBER 2013
www.ti.com
Table 3-11. Ball Characteristics (AAR Package) (continued)
BALL NUMBER [1]
BALL NAME [2]
SIGNAL NAME [3]
PINCNTL
REGISTER NAME
AND ADDRESS[4]
PINCNTL
DEFAULT
VALUE[5]
MODE
[6]
TYPE [7] DSIS [8]
BALL
RESET
STATE [9]
BALL
RESET
REL.
STATE [10]
POWER [11]
AK15
DDR[0]_DQS[1]
DDR[0]_DQS[1]
NA /
NA
NA
0x01
I/O
NA
H
1
DVDD_DDR[0]
AL15
DDR[0]_DQS[1]
DDR[0]_DQS[1]
NA /
NA
NA
0x01
I/O
NA
L
0
DVDD_DDR[0]
AL17
DDR[0]_DQS[2]
DDR[0]_DQS[2]
NA /
NA
NA
0x01
I/O
NA
L
0
DVDD_DDR[0]
AK17
DDR[0]_DQS[2]
DDR[0]_DQS[2]
NA /
NA
NA
0x01
I/O
NA
H
1
DVDD_DDR[0]
AK20
DDR[0]_DQS[3]
DDR[0]_DQS[3]
NA /
NA
NA
0x01
I/O
NA
H
1
DVDD_DDR[0]
AL20
DDR[0]_DQS[3]
DDR[0]_DQS[3]
NA /
NA
NA
0x01
I/O
NA
L
0
DVDD_DDR[0]
AL21
DDR[0]_ODT[0]
DDR[0]_ODT[0]
NA /
NA
NA
0x01
O
NA
L
0
DVDD_DDR[0]
AJ25
DDR[0]_RAS
DDR[0]_RAS
NA /
NA
NA
0x01
O
NA
H
1
DVDD_DDR[0]
AA20
DDR[0]_RST
DDR[0]_RST
NA /
NA
NA
0x01
O
NA
L
0
DVDD_DDR[0]
AL30
DDR[0]_VTP
DDR[0]_VTP
NA /
NA
NA
0x01
I
NA
NA
NA
DVDD_DDR[0]
AL26
DDR[0]_WE
DDR[0]_WE
NA /
NA
NA
0x01
O
NA
H
1
DVDD_DDR[0]
F30
DEVOSC_MXI
DEV_CLKIN
NA /
NA
NA
0x01
I
NA
NA
NA
VDDS_OSC0_1P8
0x01
I
NA
DEVOSC_MXI
G31
DEVOSC_MXO
DEVOSC_MXO
NA /
NA
NA
0x01
O
NA
NA
NA
VDDS_OSC0_1P8
U28
DEVOSC_WAKE
DEVOSC_WAKE
PINCNTL7 /
0x4814 0818
0x000E 0000
0x01
I
1
H
H
DVDD_SD
0x02
I/O
1
TIM5_IO
0x40
I/O
PIN
GP1[7]
0x80
I/O
PIN
SPI[1]_SCS[1]
D16, E17, F16, L5, DVDD
M4, M6, M7, N10,
N11, T26, T28, U27
DVDD
NA /
NA
NA
NA
PWR
NA
NA
NA
NA
D12, E13, F12,
G12, G13
DVDD_C
NA /
NA
NA
NA
PWR
NA
NA
NA
NA
AB14, AB15, AB17, DVDD_DDR[0]
AB18, AC15, AC17,
AC18, AE15, AE16,
AF16, AG15, AH16
DVDD_DDR[0]
NA /
NA
NA
NA
PWR
NA
NA
NA
NA
R5, R7, T4, T6, T7
DVDD_GPMC
DVDD_GPMC
NA /
NA
NA
NA
PWR
NA
NA
NA
NA
W5, W7, Y4, Y6, Y7 DVDD_RGMII
DVDD_RGMII
NA /
NA
NA
NA
PWR
NA
NA
NA
NA
T25, U25
DVDD_SD
NA /
NA
NA
NA
PWR
NA
NA
NA
NA
38
DVDD_C
DVDD_SD
Device Pins
HYS [12]
BUFFER
TYPE [13]
Copyright © 2013, Texas Instruments Incorporated
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SPRS872B – MAY 2013 – REVISED DECEMBER 2013
Table 3-11. Ball Characteristics (AAR Package) (continued)
BALL NUMBER [1]
AL6
AH1
AH2
AK1
AJ6
AK2
AL2
AL3
BALL NAME [2]
EMAC[0]_GMTCLK/
EMAC[1]_RGRXC
EMAC[0]_MCOL/
EMAC[0]_RGRXCTL
EMAC[0]_MCRS/
EMAC[0]_RGRXD[2]
EMAC[0]_MRCLK/
EMAC[0]_RGTXC
EMAC[0]_MRXDV/
EMAC[1]_RGRXD[1]
EMAC[0]_MRXD[0]/
EMAC[0]_RGTXD[0]
EMAC[0]_MRXD[1]/
EMAC[0]_RGRXD[0]
EMAC[0]_MRXD[2]/
EMAC[0]_RGRXD[1]
SIGNAL NAME [3]
EMAC[0]_GMTCLK/
EMAC[1]_RGRXC
PINCNTL
REGISTER NAME
AND ADDRESS[4]
TYPE [7] DSIS [8]
I/O
PIN
GPMC_A[6]
0x10
O
PIN
SPI[2]_D[1]
0x20
I/O
PIN
0x01
I
0
VIN[1]B_D[1]
0x02
I
PIN
EMAC[0]_RMRXD[0]
0x04
I
PIN
GP3[24]
0x80
I/O
PIN
0x01
I
0
VIN[1]B_D[2]
0x02
I
PIN
EMAC[0]_RMRXD[1]
0x04
I
PIN
GP3[25]
0x80
I/O
PIN
0x01
I/O
0
VIN[1]B_D[4]
0x02
I
PIN
EMAC[0]_RMCRSDV
0x04
I
0
SPI[3]_SCS[2]
0x20
I/O
1
GP3[27]
0x80
I/O
PIN
0x01
I/O
0
GPMC_A[5]
0x10
O
PIN
SPI[2]_SCLK
0x20
I/O
1
0x01
I/O
PIN
VIN[1]B_D[5]
0x02
I
PIN
EMAC[0]_RMTXD[0]
0x04
O
PIN
GP3[28]
0x80
I/O
PIN
0x01
I/O
PIN
VIN[1]B_D[6]
0x02
I
PIN
EMAC[0]_RMTXD[1]
0x04
O
PIN
GP3[29]
0x80
I/O
PIN
0x01
I/O
PIN
VIN[1]B_D[7]
0x02
I
PIN
EMAC[0]_RMTXEN
0x04
O
PIN
GP3[30]
0x80
I/O
PIN
EMAC[0]_MCRS/
EMAC[0]_RGRXD[2]
EMAC[0]_MRCLK/
EMAC[0]_RGTXC
EMAC[0]_MRXDV/
EMAC[1]_RGRXD[1]
EMAC[0]_MRXD[0]/
EMAC[0]_RGTXD[0]
EMAC[0]_MRXD[1]/
EMAC[0]_RGRXD[0]
EMAC[0]_MRXD[2]/
EMAC[0]_RGRXD[1]
PINCNTL236 /
0x4814 0BAC
PINCNTL237 /
0x4814 0BB0
PINCNTL239 /
0x4814 0BB8
PINCNTL248 /
0x4814 0BDC
PINCNTL240 /
0x4814 0BBC
PINCNTL241 /
0x4814 0BC0
PINCNTL242 /
0x4814 0BC4
0x0004 0000
MODE
[6]
0x01
EMAC[0]_MCOL/
EMAC[0]_RGRXCTL
PINCNTL249 /
0x4814 0BE0
PINCNTL
DEFAULT
VALUE[5]
0x000C 0000
0x000C 0000
0x000C 0000
0x0004 0000
0x0004 0000
0x0004 0000
0x0004 0000
BALL
RESET
STATE [9]
BALL
RESET
REL.
STATE [10]
POWER [11]
L
L
DVDD_RGMII
L
L
DVDD_RGMII
L
L
DVDD_RGMII
L
L
DVDD_RGMII
L
L
DVDD_RGMII
L
L
DVDD_RGMII
L
L
DVDD_RGMII
L
L
DVDD_RGMII
HYS [12]
BUFFER
TYPE [13]
Device Pins
Copyright © 2013, Texas Instruments Incorporated
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DMVA3, DMVA4
SPRS872B – MAY 2013 – REVISED DECEMBER 2013
www.ti.com
Table 3-11. Ball Characteristics (AAR Package) (continued)
BALL NUMBER [1]
AK3
BALL NAME [2]
EMAC[0]_MRXD[3]/
EMAC[1]_RGRXCTL
AK4
EMAC[0]_MRXD[4]/
EMAC[0]_RGRXD[3]
AJ4
EMAC[0]_MRXD[5]/
EMAC[0]_RGTXD[3]
AL5
EMAC[0]_MRXD[6]/
EMAC[0]_RGTXD[2]
AK5
EMAC[0]_MRXD[7]/
EMAC[0]_RGTXD[1]
SIGNAL NAME [3]
EMAC[0]_MRXD[3]/
EMAC[1]_RGRXCTL
PINCNTL
REGISTER NAME
AND ADDRESS[4]
0x0004 0000
PIN
GPMC_A[27]
0x04
O
PIN
GPMC_A[26]
0x08
O
PIN
GPMC_A[0]
0x10
O
PIN
0x01
I/O
PIN
0x10
O
PIN
0x01
I/O
PIN
0x10
O
PIN
0x01
I/O
PIN
0x10
O
PIN
0x01
I/O
PIN
GPMC_A[4]
0x10
O
PIN
SPI[2]_SCS[3]
0x20
I/O
1
0x01
I/O
0
VIN[1]B_D[3]
0x02
I
PIN
EMAC[0]_RMRXER
0x04
I
0
GP3[26]
0x80
I/O
PIN
0x01
I/O
0
VIN[1]B_D[0]
0x02
I
PIN
SPI[3]_SCS[3]
0x20
I/O
1
I2C[2]_SDA
0x40
I/O
1
GP3[23]
0x80
I/O
PIN
0x01
I/O
PIN
GPMC_A[7]
0x10
O
PIN
SPI[2]_D[0]
0x20
I/O
PIN
0x01
I/O
PIN
0x10
O
PIN
0x01
I/O
PIN
EMAC[1]_RMRXD[0]
0x02
I
PIN
GPMC_A[9]
0x10
O
PIN
PINCNTL244 /
0x4814 0BCC
0x0004 0000
EMAC[0]_MRXD[5]/
EMAC[0]_RGTXD[3]
PINCNTL245 /
0x4814 0BD0
0x0004 0000
PINCNTL246 /
0x4814 0BD4
0x0004 0000
PINCNTL247 /
0x4814 0BD8
0x0004 0000
GPMC_A[2]
EMAC[0]_MRXD[6]/
EMAC[0]_RGTXD[2]
GPMC_A[3]
AG4
AK6
EMAC[0]_MRXER/
EMAC[0]_RGTXCTL
EMAC[0]_MTCLK/
EMAC[0]_RGRXC
EMAC[0]_MTXD[0]/
EMAC[1]_RGRXD[3]
AJ7
EMAC[0]_MTXD[1]/
EMAC[1]_RGTXD[1]
AK7
EMAC[0]_MTXD[2]/
EMAC[1]_RGTXCTL
EMAC[0]_MRXD[7]/
EMAC[0]_RGTXD[1]
EMAC[0]_MRXER/
EMAC[0]_RGTXCTL
EMAC[0]_MTCLK/
EMAC[0]_RGRXC
EMAC[0]_MTXD[0]/
EMAC[1]_RGRXD[3]
EMAC[0]_MTXD[1]/
EMAC[1]_RGTXD[1]
PINCNTL238 /
0x4814 0BB4
PINCNTL235 /
0x4814 0BA8
PINCNTL250 /
0x4814 0BE4
0x000C 0000
0x000C 0000
0x0004 0000
PINCNTL251 /
0x4814 0BE8
0x0004 0000
PINCNTL252 /
0x4814 0BEC
0x0004 0000
GPMC_A[8]
40
TYPE [7] DSIS [8]
I/O
GPMC_A[1]
AJ2
MODE
[6]
0x01
EMAC[0]_MRXD[4]/
EMAC[0]_RGRXD[3]
PINCNTL243 /
0x4814 0BC8
PINCNTL
DEFAULT
VALUE[5]
EMAC[0]_MTXD[2]/
EMAC[1]_RGTXCTL
Device Pins
BALL
RESET
STATE [9]
BALL
RESET
REL.
STATE [10]
POWER [11]
L
L
DVDD_RGMII
L
L
DVDD_RGMII
L
L
DVDD_RGMII
L
L
DVDD_RGMII
L
L
DVDD_RGMII
L
L
DVDD_RGMII
L
L
DVDD_RGMII
L
L
DVDD_RGMII
L
L
DVDD_RGMII
L
L
DVDD_RGMII
HYS [12]
BUFFER
TYPE [13]
Copyright © 2013, Texas Instruments Incorporated
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DMVA3, DMVA4
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SPRS872B – MAY 2013 – REVISED DECEMBER 2013
Table 3-11. Ball Characteristics (AAR Package) (continued)
BALL NUMBER [1]
AE4
AK8
AJ8
AH8
AG8
AF8
AG1
BALL NAME [2]
EMAC[0]_MTXD[3]/
EMAC[1]_RGTXD[0]
EMAC[0]_MTXD[4]/
EMAC[1]_RGTXD[2]
EMAC[0]_MTXD[5]/
EMAC[1]_RGTXC
EMAC[0]_MTXD[6]/
EMAC[1]_RGRXD[0]
EMAC[0]_MTXD[7]/
EMAC[1]_RGTXD[3]
EMAC[0]_MTXEN/
EMAC[1]_RGRXD[2]
EMAC_RMREFCLK
SIGNAL NAME [3]
EMAC[0]_MTXD[3]/
EMAC[1]_RGTXD[0]
PINCNTL
REGISTER NAME
AND ADDRESS[4]
TYPE [7] DSIS [8]
I/O
PIN
EMAC[1]_RMRXD[1]
0x02
I
PIN
GPMC_A[10]
0x10
O
PIN
0x01
I/O
PIN
EMAC[1]_RMRXER
0x02
I
0
GPMC_A[11]
0x10
O
PIN
0x01
I/O
PIN
EMAC[1]_RMCRSDV
0x02
I
0
GPMC_A[12]
0x10
O
PIN
UART1_RXD
0x20
I
1
0x01
I/O
PIN
EMAC[1]_RMTXD[0]
0x02
O
PIN
GPMC_A[13]
0x10
O
PIN
UART1_TXD
0x20
O
PIN
0x01
I/O
PIN
EMAC[1]_RMTXD[1]
0x02
O
PIN
GPMC_A[14]
0x10
O
PIN
UART1_CTS
0x20
I/O
1
0x01
I/O
PIN
EMAC[1]_RMTXEN
0x02
O
PIN
GPMC_A[15]
0x10
O
PIN
UART1_RTS
0x20
O
PIN
0x01
I/O
PIN
0x40
I/O
PIN
EMAC[0]_MTXD[5]/
EMAC[1]_RGTXC
EMAC[0]_MTXD[6]/
EMAC[1]_RGRXD[0]
EMAC[0]_MTXD[7]/
EMAC[1]_RGTXD[3]
EMAC[0]_MTXEN/
EMAC[1]_RGRXD[2]
EMAC_RMREFCLK
TIM2_IO
PINCNTL254 /
0x4814 0BF4
PINCNTL255 /
0x4814 0BF8
PINCNTL256 /
0x4814 0BFC
PINCNTL257 /
0x4814 0C00
PINCNTL258 /
0x4814 0C04
0x0004 0000
MODE
[6]
0x01
EMAC[0]_MTXD[4]/
EMAC[1]_RGTXD[2]
PINCNTL253 /
0x4814 0BF0
PINCNTL
DEFAULT
VALUE[5]
0x0004 0000
0x0004 0000
0x0004 0000
0x0004 0000
0x0004 0000
PINCNTL232 /
0x4814 0B9C
0x0004 0000
GP1[10]
BALL
RESET
STATE [9]
BALL
RESET
REL.
STATE [10]
POWER [11]
L
L
DVDD_RGMII
L
L
DVDD_RGMII
L
L
DVDD_RGMII
L
L
DVDD_RGMII
L
L
DVDD_RGMII
L
L
DVDD_RGMII
L
L
DVDD_RGMII
0x80
I/O
PIN
A18
EMU0
EMU0
NA /
NA
NA
0x01
I/O
NA
H
H
DVDD
B19
EMU1
EMU1
NA /
NA
NA
0x01
I/O
NA
H
H
DVDD
M1
GPMC_A[16]
GPMC_A[16]
PINCNTL105 /
0x4814 09A0
0x0004 0000
0x01
O
PIN
L
L
DVDD_GPMC
0x80
I/O
PIN
PINCNTL106 /
0x4814 09A4
0x0004 0000
0x01
O
PIN
L
L
DVDD_GPMC
0x80
I/O
PIN
GP2[5]
M2
GPMC_A[17]
GPMC_A[17]
GP2[6]
HYS [12]
BUFFER
TYPE [13]
Device Pins
Copyright © 2013, Texas Instruments Incorporated
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DMVA3, DMVA4
SPRS872B – MAY 2013 – REVISED DECEMBER 2013
www.ti.com
Table 3-11. Ball Characteristics (AAR Package) (continued)
BALL NUMBER [1]
M3
BALL NAME [2]
GPMC_A[18]
SIGNAL NAME [3]
GPMC_A[18]
PINCNTL
REGISTER NAME
AND ADDRESS[4]
PINCNTL
DEFAULT
VALUE[5]
0x0004 0000
O
PIN
0x40
I/O
PIN
PINCNTL108 /
0x4814 09AC
0x0004 0000
0x80
I/O
PIN
0x01
O
PIN
0x40
I/O
PIN
PINCNTL109 /
0x4814 09B0
0x0006 0000
0x80
I/O
PIN
0x01
O
PIN
0x04
I/O
1
PINCNTL110 /
0x4814 09B4
0x0004 0000
0x80
I/O
PIN
0x01
O
PIN
0x04
I/O
PIN
PINCNTL111 /
0x4814 09B8
0x0006 0000
0x80
I/O
PIN
0x01
O
PIN
0x04
I/O
PIN
HDMI_CEC
0x10
I/O
1
TIM4_IO
0x40
I/O
PIN
GP1[17]
0x80
I/O
PIN
0x01
O
PIN
0x04
I/O
1
HDMI_HPDET
0x10
I
0
TIM5_IO
0x40
I/O
PIN
GP1[18]
0x80
I/O
PIN
0x01
O
PIN
0x02
O
PIN
TIM5_IO
0x40
I/O
PIN
GP1[28]
0x80
I/O
PIN
0x01
O
PIN
0x02
O
PIN
EDMA_EVT1
0x20
I
PIN
TIM7_IO
0x40
I/O
PIN
GP1[30]
0x80
I/O
PIN
0x01
O
PIN
0x02
O
PIN
EDMA_EVT2
0x20
I
PIN
TIM6_IO
0x40
I/O
PIN
GP1[29]
0x80
I/O
PIN
GP1[13]
M5
GPMC_A[19]
GPMC_A[19]
TIM3_IO
GP1[14]
N9
GPMC_A[20]
GPMC_A[20]
SPI[2]_SCS[1]
GP1[15]
N1
GPMC_A[21]
GPMC_A[21]
SPI[2]_D[0]
GP1[16]
N2
GPMC_A[22]
GPMC_A[22]
SPI[2]_D[1]
R8
GPMC_A[23]
GPMC_A[23]
SPI[2]_SCLK
AA10
GPMC_ADV_ALE
GPMC_ADV_ALE
GPMC_CS[6]
Y11
GPMC_BE[1]
GPMC_BE[1]
GPMC_A[24]
Y3
GPMC_BE[0]_CLE
GPMC_BE[0]_CLE
GPMC_A[25]
42
TYPE [7] DSIS [8]
0x01
TIM2_IO
PINCNTL107 /
0x4814 09A8
MODE
[6]
PINCNTL112 /
0x4814 09BC
PINCNTL128 /
0x4814 09FC
PINCNTL132 /
0x4814 0A0C
PINCNTL131 /
0x4814 0A08
0x0004 0000
0x0006 0000
0x0004 0000
0x0004 0000
Device Pins
BALL
RESET
STATE [9]
BALL
RESET
REL.
STATE [10]
POWER [11]
L
L
DVDD_GPMC
L
L
DVDD_GPMC
H
H
DVDD_GPMC
L
L
DVDD_GPMC
H
H
DVDD_GPMC
L
L
DVDD_GPMC
H
H
DVDD_GPMC
L
L
DVDD_GPMC
L
L
DVDD_GPMC
HYS [12]
BUFFER
TYPE [13]
Copyright © 2013, Texas Instruments Incorporated
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DMVA3, DMVA4
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SPRS872B – MAY 2013 – REVISED DECEMBER 2013
Table 3-11. Ball Characteristics (AAR Package) (continued)
BALL NUMBER [1]
AB9
BALL NAME [2]
GPMC_CLK
SIGNAL NAME [3]
GPMC_CLK
GPMC_CS[0]
AA12
GPMC_CS[1]
0
O
PIN
GPMC_WAIT[1]
0x08
I
1
CLKOUT1
0x10
O
PIN
EDMA_EVT3
0x20
I
PIN
TIM4_IO
0x40
I/O
PIN
GP1[27]
0x80
I/O
PIN
0x01
O
PIN
0x80
I/O
PIN
0x01
O
PIN
0x02
O
PIN
0x80
I/O
PIN
0x01
O
PIN
0x02
O
PIN
0x80
I/O
PIN
0x01
O
PIN
0x02
I
0
SPI[2]_SCS[0]
0x04
I/O
1
GP1[26]
0x80
I/O
PIN
0x01
O
PIN
0x02
O
1
0x80
I/O
PIN
0x01
I/O
PIN
0x80
I
PIN
0x01
I/O
PIN
0x80
I
PIN
0x01
I/O
PIN
0x80
I
PIN
0x01
I/O
PIN
0x80
I
PIN
0x01
I/O
PIN
0x80
I
PIN
0x01
I/O
PIN
0x80
I
PIN
0x01
I/O
PIN
0x80
I
PIN
0x01
I/O
PIN
0x80
I
PIN
GPMC_CS[1]
GPMC_A[25]
PINCNTL122 /
0x4814 09E4
0x0006 0000
PINCNTL123 /
0x4814 09E8
0x0006 0000
PINCNTL124 /
0x4814 09EC
0x0006 0000
PINCNTL125 /
0x4814 09F0
0x0006 0000
GP1[24]
AC3
GPMC_CS[2]
GPMC_CS[2]
GPMC_A[24]
GP1[25]
AF2
GPMC_CS[3]
GPMC_CS[3]
VIN[1]B_CLK
AG6
GPMC_CS[4]
GPMC_CS[4]
SD2_CMD
PINCNTL126 /
0x4814 09F4
0x0006 0000
PINCNTL89 /
0x4814 0960
0x0005 0000
PINCNTL90 /
0x4814 0964
0x0005 0000
PINCNTL91 /
0x4814 0968
0x0005 0000
PINCNTL92 /
0x4814 096C
0x0005 0000
PINCNTL93 /
0x4814 0970
0x0005 0000
PINCNTL94 /
0x4814 0974
0x0005 0000
PINCNTL95 /
0x4814 0978
0x0005 0000
PINCNTL96 /
0x4814 097C
0x0005 0000
GP1[8]
W6
GPMC_D[0]
GPMC_D[0]
BTMODE[0]
W4
GPMC_D[1]
GPMC_D[1]
BTMODE[1]
W3
GPMC_D[2]
GPMC_D[2]
BTMODE[2]
U2
GPMC_D[3]
GPMC_D[3]
BTMODE[3]
W9
GPMC_D[4]
GPMC_D[4]
BTMODE[4]
T5
GPMC_D[5]
GPMC_D[5]
BTMODE[5]
T3
GPMC_D[6]
GPMC_D[6]
BTMODE[6]
T2
GPMC_D[7]
TYPE [7] DSIS [8]
O
GP1[23]
0x0006 0000
MODE
[6]
0x02
GPMC_CS[0]
PINCNTL127 /
0x4814 09F8
PINCNTL
DEFAULT
VALUE[5]
0x01
GPMC_CS[5]
AC9
PINCNTL
REGISTER NAME
AND ADDRESS[4]
GPMC_D[7]
BTMODE[7]
BALL
RESET
STATE [9]
BALL
RESET
REL.
STATE [10]
POWER [11]
H
H
DVDD_GPMC
H
H
DVDD_GPMC
H
H
DVDD_GPMC
H
H
DVDD_RGMII
H
H
DVDD_RGMII
H
H
DVDD_RGMII
Z
Z
DVDD_GPMC
Z
Z
DVDD_GPMC
Z
Z
DVDD_GPMC
Z
Z
DVDD_GPMC
Z
Z
DVDD_GPMC
Z
Z
DVDD_GPMC
Z
Z
DVDD_GPMC
Z
Z
DVDD_GPMC
HYS [12]
BUFFER
TYPE [13]
Device Pins
Copyright © 2013, Texas Instruments Incorporated
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43
DMVA3, DMVA4
SPRS872B – MAY 2013 – REVISED DECEMBER 2013
www.ti.com
Table 3-11. Ball Characteristics (AAR Package) (continued)
BALL NUMBER [1]
T1
BALL NAME [2]
GPMC_D[8]
SIGNAL NAME [3]
GPMC_D[8]
BTMODE[8]
T8
GPMC_D[9]
GPMC_D[9]
BTMODE[9]
R6
GPMC_D[10]
GPMC_D[10]
BTMODE[10]
R4
GPMC_D[11]
GPMC_D[11]
BTMODE[11]
R3
GPMC_D[12]
GPMC_D[12]
BTMODE[12]
R2
GPMC_D[13]
GPMC_D[13]
BTMODE[13]
R1
GPMC_D[14]
GPMC_D[14]
BTMODE[14]
P2
GPMC_D[15]
GPMC_D[15]
BTMODE[15]
PINCNTL
REGISTER NAME
AND ADDRESS[4]
PINCNTL
DEFAULT
VALUE[5]
PINCNTL97 /
0x4814 0980
0x0005 0000
PINCNTL98 /
0x4814 0984
0x0005 0000
PINCNTL99 /
0x4814 0988
0x0005 0000
PINCNTL100 /
0x4814 098C
0x0005 0000
PINCNTL101 /
0x4814 0990
0x0005 0000
PINCNTL102 /
0x4814 0994
0x0005 0000
PINCNTL103 /
0x4814 0998
0x0005 0000
PINCNTL104 /
0x4814 099C
0x0005 0000
MODE
[6]
TYPE [7] DSIS [8]
0x01
I/O
PIN
0x80
I
PIN
0x01
I/O
PIN
0x80
I
PIN
0x01
I/O
PIN
0x80
I
PIN
0x01
I/O
PIN
0x80
I
PIN
0x01
I/O
PIN
0x80
I
PIN
0x01
I/O
PIN
0x80
I
PIN
0x01
I/O
PIN
0x80
I
PIN
0x01
I/O
PIN
0x80
I
PIN
BALL
RESET
STATE [9]
BALL
RESET
REL.
STATE [10]
POWER [11]
Z
Z
DVDD_GPMC
Z
Z
DVDD_GPMC
Z
Z
DVDD_GPMC
Z
Z
DVDD_GPMC
Z
Z
DVDD_GPMC
Z
Z
DVDD_GPMC
Z
Z
DVDD_GPMC
Z
Z
DVDD_GPMC
Y8
GPMC_OE_RE
GPMC_OE_RE
PINCNTL129 /
0x4814 0A00
0x0006 0000
0x01
O
PIN
H
H
DVDD_GPMC
W8
GPMC_WAIT[0]
GPMC_WAIT[0]
PINCNTL133 /
0x4814 0A10
0x0006 0000
0x01
I
1
H
H
DVDD_GPMC
0x02
O
PIN
EDMA_EVT0
0x20
I
PIN
GP1[31]
0x80
I/O
PIN
GPMC_A[26]
Y5
GPMC_WE
GPMC_WE
PINCNTL130 /
0x4814 0A04
0x0006 0000
0x01
O
PIN
H
H
DVDD_GPMC
A9
HDDAC_A
HDDAC_A
NA /
NA
NA
0x01
O
NA
NA
NA
VDDA_VDAC_1P8
A8
HDDAC_B
HDDAC_B
NA /
NA
NA
0x01
O
NA
NA
NA
VDDA_VDAC_1P8
B8
HDDAC_C
HDDAC_C
NA /
NA
NA
0x01
O
NA
NA
NA
VDDA_VDAC_1P8
E9
HDDAC_HSYNC
HDDAC_HSYNC
NA /
NA
NA
0x01
O
NA
L
L
DVDD
B6
HDDAC_IREF
HDDAC_IREF
NA /
NA
NA
0x01
I/O
NA
NA
NA
VDDA_VDAC_1P8
B7
HDDAC_VREF
HDDAC_VREF
NA /
NA
NA
0x01
I
NA
NA
NA
VDDA_VDAC_1P8
D9
HDDAC_VSYNC
HDDAC_VSYNC
NA /
NA
NA
0x01
O
NA
L
L
DVDD
B15
HDMI_CLKN
HDMI_CLKN
NA /
NA
NA
0x01
O
NA
NA
NA
VDDA_HDMI_1P8
A15
HDMI_CLKP
HDMI_CLKP
NA /
NA
NA
0x01
O
NA
NA
NA
VDDA_HDMI_1P8
44
Device Pins
HYS [12]
BUFFER
TYPE [13]
Copyright © 2013, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: DMVA3
DMVA3, DMVA4
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SPRS872B – MAY 2013 – REVISED DECEMBER 2013
Table 3-11. Ball Characteristics (AAR Package) (continued)
BALL NUMBER [1]
BALL NAME [2]
SIGNAL NAME [3]
PINCNTL
REGISTER NAME
AND ADDRESS[4]
PINCNTL
DEFAULT
VALUE[5]
MODE
[6]
TYPE [7] DSIS [8]
BALL
RESET
STATE [9]
BALL
RESET
REL.
STATE [10]
POWER [11]
A14
HDMI_DN0
HDMI_DN0
NA /
NA
NA
0x01
O
NA
NA
NA
VDDA_HDMI_1P8
B13
HDMI_DN1
HDMI_DN1
NA /
NA
NA
0x01
O
NA
NA
NA
VDDA_HDMI_1P8
A12
HDMI_DN2
HDMI_DN2
NA /
NA
NA
0x01
O
NA
NA
NA
VDDA_HDMI_1P8
B14
HDMI_DP0
HDMI_DP0
NA /
NA
NA
0x01
O
NA
NA
NA
VDDA_HDMI_1P8
B12
HDMI_DP1
HDMI_DP1
NA /
NA
NA
0x01
O
NA
NA
NA
VDDA_HDMI_1P8
A11
HDMI_DP2
HDMI_DP2
NA /
NA
NA
0x01
O
NA
NA
NA
VDDA_HDMI_1P8
T27
I2C[0]_SCL
I2C[0]_SCL
PINCNTL263 /
0x4814 0C18
0x000C 0000
0x01
I/O
PIN
H
H
DVDD
T24
I2C[0]_SDA
I2C[0]_SDA
PINCNTL264 /
0x4814 0C1C
0x000C 0000
0x01
I/O
PIN
H
H
DVDD
D2
I2C[1]_SCL
I2C[1]_SCL
PINCNTL78 /
0x4814 0934
0x000E 0000
0x01
I/O
1
H
H
DVDD
0x02
I/O
1
PINCNTL79 /
0x4814 0938
0x000E 0000
0x01
I/O
1
H
H
DVDD
0x02
I/O
1
HDMI_SCL
D1
I2C[1]_SDA
I2C[1]_SDA
HDMI_SDA
J19
LDOCAP_ARM
LDOCAP_ARM
NA /
NA
NA
NA
A
NA
NA
NA
NA
K20
LDOCAP_ARMRAM
LDOCAP_ARMRAM
NA /
NA
NA
NA
A
NA
NA
NA
NA
W23
LDOCAP_HDVICP
LDOCAP_HDVICP
NA /
NA
NA
NA
A
NA
NA
NA
NA
Y24
LDOCAP_HDVICPRAM
LDOCAP_HDVICPRAM
NA /
NA
NA
NA
A
NA
NA
NA
NA
U9
LDOCAP_RAM0
LDOCAP_RAM0
NA /
NA
NA
NA
A
NA
NA
NA
NA
T22
LDOCAP_RAM1
LDOCAP_RAM1
NA /
NA
NA
NA
A
NA
NA
NA
NA
AB10
LDOCAP_RAM2
LDOCAP_RAM2
NA /
NA
NA
NA
A
NA
NA
NA
NA
M24
LDOCAP_SERDESCLK
LDOCAP_SERDESCLK
NA /
NA
NA
NA
A
NA
NA
NA
NA
AD30
MCA[0]_ACLKR
MCA[0]_ACLKR
PINCNTL19 /
0x4814 0848
0x0004 0000
0x01
I/O
0
L
L
DVDD
AD28
MCA[0]_ACLKX
MCA[0]_ACLKX
PINCNTL17 /
0x4814 0840
0x0004 0000
0x01
I/O
PIN
L
L
DVDD
AF30
MCA[0]_AFSR
MCA[0]_AFSR
PINCNTL20 /
0x4814 084C
0x000C 0000
0x01
I/O
0
L
L
DVDD
AE29
MCA[0]_AFSX
MCA[0]_AFSX
PINCNTL18 /
0x4814 0844
0x000C 0000
0x01
I/O
PIN
L
L
DVDD
AF29
MCA[0]_AXR[0]
MCA[0]_AXR[0]
PINCNTL21 /
0x4814 0850
0x000C 0000
0x01
I/O
PIN
L
L
DVDD
HYS [12]
BUFFER
TYPE [13]
Device Pins
Copyright © 2013, Texas Instruments Incorporated
Submit Documentation Feedback
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45
DMVA3, DMVA4
SPRS872B – MAY 2013 – REVISED DECEMBER 2013
www.ti.com
Table 3-11. Ball Characteristics (AAR Package) (continued)
BALL NUMBER [1]
AE31
BALL NAME [2]
MCA[0]_AXR[1]
SIGNAL NAME [3]
MCA[0]_AXR[1]
I2C[3]_SCL
AE30
MCA[0]_AXR[2]
MCA[0]_AXR[2]
I2C[3]_SDA
PINCNTL
REGISTER NAME
AND ADDRESS[4]
PINCNTL
DEFAULT
VALUE[5]
PINCNTL22 /
0x4814 0854
0x000E 0000
PINCNTL23 /
0x4814 0858
0x000E 0000
MODE
[6]
TYPE [7] DSIS [8]
0x01
I/O
PIN
0x20
I/O
1
0x01
I/O
PIN
0x20
I/O
1
BALL
RESET
STATE [9]
BALL
RESET
REL.
STATE [10]
POWER [11]
H
H
DVDD
H
H
DVDD
AC31
MCA[0]_AXR[3]
MCA[0]_AXR[3]
PINCNTL24 /
0x4814 085C
0x000C 0000
0x01
I/O
PIN
L
L
DVDD
AD26
MCA[0]_AXR[4]
MCA[0]_AXR[4]
PINCNTL25 /
0x4814 0860
0x000C 0000
0x01
I/O
PIN
L
L
DVDD
AD27
MCA[0]_AXR[5]
MCA[0]_AXR[5]
PINCNTL26 /
0x4814 0864
0x000C 0000
0x01
I/O
PIN
L
L
DVDD
AD29
MCA[1]_ACLKR
MCA[1]_ACLKR
PINCNTL33 /
0x4814 0880
0x0004 0000
0x01
I/O
0
L
L
DVDD
AC23
MCA[1]_ACLKX
MCA[1]_ACLKX
PINCNTL31 /
0x4814 0878
0x0004 0000
0x01
I/O
PIN
L
L
DVDD
AC24
MCA[1]_AFSR
MCA[1]_AFSR
PINCNTL34 /
0x4814 0884
0x000C 0000
0x01
I/O
0
L
L
DVDD
AB22
MCA[1]_AFSX
MCA[1]_AFSX
PINCNTL32 /
0x4814 087C
0x000C 0000
0x01
I/O
PIN
L
L
DVDD
Y22
MCA[1]_AXR[0]
MCA[1]_AXR[0]
PINCNTL35 /
0x4814 0888
0x000E 0000
0x01
I/O
PIN
H
H
DVDD
0x02
I/O
PIN
PINCNTL36 /
0x4814 088C
0x000E 0000
0x01
I/O
PIN
H
H
DVDD
0x02
I/O
PIN
PINCNTL233 /
0x4814 0BA0
0x000E 0000
0x01
O
PIN
H
H
DVDD_RGMII
0x80
I/O
PIN
PINCNTL234 /
0x4814 0BA4
0x000E 0000
0x01
I/O
1
H
H
DVDD_RGMII
0x80
I/O
PIN
SD0_DAT[4]
Y21
MCA[1]_AXR[1]
MCA[1]_AXR[1]
SD0_DAT[5]
AG2
MDCLK
MDCLK
GP1[11]
AG3
MDIO
MDIO
GP1[12]
AH31
NMI
NMI
PINCNTL261 /
0x4814 0C10
0x000E 0000
0x01
I
PIN
H
H
DVDD
J30
PCIE_RXN0
PCIE_RXN0
NA /
NA
NA
0x01
I
NA
NA
NA
VDDA_PCIE_1P8
K30
PCIE_RXP0
PCIE_RXP0
NA /
NA
NA
0x01
I
NA
NA
NA
VDDA_PCIE_1P8
K31
PCIE_TXN0
PCIE_TXN0
NA /
NA
NA
0x01
O
NA
NA
NA
VDDA_PCIE_1P8
L31
PCIE_TXP0
PCIE_TXP0
NA /
NA
NA
0x01
O
NA
NA
NA
VDDA_PCIE_1P8
AH30
POR
POR
NA /
NA
NA
0x01
I
NA
NA
NA
DVDD
AH29
RESET
RESET
PINCNTL260 /
0x4814 0C0C
0x000E 0000
0x01
I
PIN
H
H
DVDD
AJ30
RSTOUT_WD_OUT
RSTOUT_WD_OUT
PINCNTL262 /
0x4814 0C14
0x0005 0001
0x01
O
PIN
L
Z
DVDD
J25
RSV0
RSV0
NA
NA
NA
NA
NA
NA
46
Device Pins
HYS [12]
BUFFER
TYPE [13]
Copyright © 2013, Texas Instruments Incorporated
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Product Folder Links: DMVA3
DMVA3, DMVA4
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SPRS872B – MAY 2013 – REVISED DECEMBER 2013
Table 3-11. Ball Characteristics (AAR Package) (continued)
BALL NUMBER [1]
BALL NAME [2]
SIGNAL NAME [3]
PINCNTL
REGISTER NAME
AND ADDRESS[4]
PINCNTL
DEFAULT
VALUE[5]
MODE
[6]
TYPE [7] DSIS [8]
BALL
RESET
STATE [9]
BALL
RESET
REL.
STATE [10]
POWER [11]
H27
RSV1
RSV1
NA /
NA
NA
NA
NA
NA
NA
NA
NA
H24
RSV2
RSV2
NA /
NA
NA
NA
NA
NA
NA
NA
NA
H28
RSV3
RSV3
NA /
NA
NA
NA
NA
NA
NA
NA
NA
P31
RSV31
RSV31
NA /
NA
NA
NA
NA
NA
NA
NA
NA
R30
RSV32
RSV32
NA /
NA
NA
NA
NA
NA
NA
NA
NA
T30
RSV33
RSV33
NA /
NA
NA
NA
NA
NA
NA
NA
NA
AH24
RSV34
RSV34
NA /
NA
NA
NA
NA
NA
NA
NA
NA
AJ24
RSV35
RSV35
NA /
NA
NA
NA
NA
NA
NA
NA
NA
H25
RSV39
RSV39
NA /
NA
NA
NA
NA
NA
NA
NA
NA
G17
RSV4
RSV4
NA /
NA
NA
NA
PWR
NA
NA
NA
NA
H29
RSV40
RSV40
NA /
NA
NA
NA
NA
NA
NA
NA
NA
AD8
RSV41
RSV41
NA
NA
NA
NA
NA
NA
AK21
RSV42
RSV42
NA /
NA
NA
0x01
O
NA
L
0
NA
P30
RSV43
RSV43
NA /
NA
NA
NA
NA
NA
NA
NA
NA
G16
RSV5
RSV5
NA /
NA
NA
NA
PWR
NA
NA
NA
NA
M28
RSV54
RSV54
NA /
NA
NA
NA
PWR
NA
NA
NA
NA
N29
RTCK
RTCK
NA /
NA
NA
0x01
O
NA
H
Z
DVDD
L30
SATA0_RXN0
SATA0_RXN0
NA /
NA
NA
0x01
I
NA
NA
NA
VDDA_SATA0_1P8
M30
SATA0_RXP0
SATA0_RXP0
NA /
NA
NA
0x01
I
NA
NA
NA
VDDA_SATA0_1P8
N30
SATA0_TXN0
SATA0_TXN0
NA /
NA
NA
0x01
O
NA
NA
NA
VDDA_SATA0_1P8
N31
SATA0_TXP0
SATA0_TXP0
NA /
NA
NA
0x01
O
NA
NA
NA
VDDA_SATA0_1P8
AB30
SD0_CLK
SD0_CLK
PINCNTL8 /
0x4814 081C
0x0006 0000
0x01
O
1
H
H
DVDD_SD
0x80
I/O
PIN
GP0[1]
HYS [12]
BUFFER
TYPE [13]
Device Pins
Copyright © 2013, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: DMVA3
47
DMVA3, DMVA4
SPRS872B – MAY 2013 – REVISED DECEMBER 2013
www.ti.com
Table 3-11. Ball Characteristics (AAR Package) (continued)
BALL NUMBER [1]
AA29
BALL NAME [2]
SD0_CMD
SIGNAL NAME [3]
SD0_CMD
SD1_CMD
PINCNTL
REGISTER NAME
AND ADDRESS[4]
PINCNTL
DEFAULT
VALUE[5]
PINCNTL9 /
0x4814 0820
0x000E 0000
PINCNTL10 /
0x4814 0824
0x000E 0000
PINCNTL13 /
0x4814 0830
0x000E 0000
PINCNTL41 /
0x4814 08A0
0x000E 0000
PINCNTL42 /
0x4814 08A4
0x000E 0000
PINCNTL11 /
0x4814 0828
0x000E 0000
PINCNTL12 /
0x4814 082C
0x000E 0000
GP0[2]
AA28
SD0_DAT[0]
SD0_DAT[0]
SD1_DAT[4]
GP0[3]
Y30
SD0_DAT[3]
SD0_DAT[3]
SD1_DAT[7]
GP0[6]
AB31
SD0_DAT[6]
SD0_DAT[6]
GP0[12]
AC30
SD0_DAT[7]
SD0_DAT[7]
GP0[13]
AA26
SD0_DAT[1]_SDIRQ
SD0_DAT[1]_SDIRQ
SD1_DAT[5]
GP0[4]
Y31
SD0_DAT[2]_SDRW
SD0_DAT[2]_SDRW
SD1_DAT[6]
GP0[5]
MODE
[6]
TYPE [7] DSIS [8]
0x01
O
1
0x02
O
1
0x80
I/O
PIN
0x01
I/O
PIN
0x02
I/O
PIN
0x80
I/O
PIN
0x01
I/O
PIN
0x02
I/O
PIN
0x80
I/O
PIN
0x02
I/O
PIN
0x80
I/O
PIN
0x02
I/O
PIN
0x80
I/O
PIN
0x01
I/O
PIN
0x02
I/O
PIN
0x80
I/O
PIN
0x01
I/O
PIN
0x02
I/O
PIN
BALL
RESET
STATE [9]
BALL
RESET
REL.
STATE [10]
POWER [11]
H
H
DVDD_SD
H
H
DVDD_SD
H
H
DVDD_SD
H
H
DVDD_SD
H
H
DVDD_SD
H
H
DVDD_SD
H
H
DVDD_SD
0x80
I/O
PIN
W30
SD1_CLK
SD1_CLK
PINCNTL1 /
0x4814 0800
0x0006 0000
0x01
O
PIN
H
H
DVDD_SD
Y29
SD1_CMD
SD1_CMD
PINCNTL2 /
0x4814 0804
0x000E 0000
0x01
O
1
H
H
DVDD_SD
0x80
I/O
PIN
GP0[0]
W31
SD1_DAT[0]
SD1_DAT[0]
PINCNTL3 /
0x4814 0808
0x000E 0000
0x01
I/O
PIN
H
H
DVDD_SD
Y27
SD1_DAT[3]
SD1_DAT[3]
PINCNTL6 /
0x4814 0814
0x000E 0000
0x01
I/O
PIN
H
H
DVDD_SD
AA30
SD1_DAT[1]_SDIRQ
SD1_DAT[1]_SDIRQ
PINCNTL4 /
0x4814 080C
0x000E 0000
0x01
I/O
PIN
H
H
DVDD_SD
U29
SD1_DAT[2]_SDRW
SD1_DAT[2]_SDRW
PINCNTL5 /
0x4814 0810
0x000E 0000
0x01
I/O
PIN
H
H
DVDD_SD
AC4
SD2_DAT[0]
SD2_DAT[0]
PINCNTL120 /
0x4814 09DC
0x0006 0000
0x01
O
PIN
H
H
DVDD_RGMII
0x02
O
PIN
0x80
I/O
PIN
PINCNTL117 /
0x4814 09D0
0x0006 0000
0x01
I/O
PIN
H
H
DVDD_RGMII
0x02
O
PIN
0x80
I/O
PIN
GPMC_A[4]
GP1[14]
AD1
SD2_DAT[3]
SD2_DAT[3]
GPMC_A[1]
GP2[5]
48
Device Pins
HYS [12]
BUFFER
TYPE [13]
Copyright © 2013, Texas Instruments Incorporated
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DMVA3, DMVA4
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SPRS872B – MAY 2013 – REVISED DECEMBER 2013
Table 3-11. Ball Characteristics (AAR Package) (continued)
BALL NUMBER [1]
AD2
BALL NAME [2]
SD2_DAT[4]
SIGNAL NAME [3]
SD2_DAT[4]
SD2_DAT[5]
PIN
O
PIN
GPMC_A[23]
0x04
O
PIN
GPMC_CS[7]
0x08
O
PIN
EDMA_EVT0
0x20
I
PIN
TIM7_IO
0x40
I/O
PIN
GP1[22]
0x80
I/O
PIN
0x01
I/O
PIN
0x02
O
PIN
GPMC_A[22]
0x04
O
PIN
TIM6_IO
0x40
I/O
PIN
GP1[21]
0x80
I/O
PIN
0x01
I/O
PIN
0x02
O
PIN
GPMC_A[21]
0x04
O
PIN
UART2_TXD
0x20
O
PIN
GP1[20]
0x80
I/O
PIN
0x01
I/O
PIN
0x02
O
PIN
GPMC_A[20]
0x04
O
PIN
UART2_RXD
0x20
I
1
GP1[19]
0x80
I/O
PIN
0x01
I/O
PIN
0x02
O
PIN
0x80
I/O
PIN
0x01
I/O
PIN
0x02
O
PIN
0x80
I/O
PIN
0x01
I/O
1
0x80
I/O
PIN
GPMC_A[26]
AE2
SD2_DAT[6]
SD2_DAT[6]
GPMC_A[25]
AE3
SD2_DAT[7]
SD2_DAT[7]
GPMC_A[24]
AC5
SD2_DAT[1]_SDIRQ
SD2_DAT[1]_SDIRQ
GPMC_A[3]
PINCNTL114 /
0x4814 09C4
PINCNTL113 /
0x4814 09C0
0x0006 0000
0x0006 0000
0x0006 0000
PINCNTL119 /
0x4814 09D8
0x0006 0000
PINCNTL118 /
0x4814 09D4
0x0006 0000
PINCNTL121 /
0x4814 09E0
0x0006 0000
GP1[13]
AC8
SD2_DAT[2]_SDRW
SD2_DAT[2]_SDRW
GPMC_A[2]
GP2[6]
AC6
SD2_SCLK
TYPE [7] DSIS [8]
I/O
PINCNTL115 /
0x4814 09C8
0x0006 0000
MODE
[6]
0x02
SD2_DAT[5]
PINCNTL116 /
0x4814 09CC
PINCNTL
DEFAULT
VALUE[5]
0x01
GPMC_A[27]
AE1
PINCNTL
REGISTER NAME
AND ADDRESS[4]
SD2_SCLK
GP1[15]
BALL
RESET
STATE [9]
BALL
RESET
REL.
STATE [10]
POWER [11]
H
H
DVDD_RGMII
H
H
DVDD_RGMII
H
H
DVDD_RGMII
H
H
DVDD_RGMII
H
H
DVDD_RGMII
H
H
DVDD_RGMII
H
H
DVDD_RGMII
H31
SERDES_CLKN
SERDES_CLKN
NA /
NA
NA
0x01
I
NA
NA
NA
VDDA_SATA0_1P8
H30
SERDES_CLKP
SERDES_CLKP
NA /
NA
NA
0x01
I
NA
NA
NA
VDDA_SATA0_1P8
J28
SPI[0]_D[0]
SPI[0]_D[0]
PINCNTL84 /
0x4814 094C
0x0006 0000
0x01
I/O
PIN
H
H
DVDD
J27
SPI[0]_D[1]
SPI[0]_D[1]
PINCNTL83 /
0x4814 0948
0x0006 0000
0x01
I/O
PIN
H
H
DVDD
N24
SPI[0]_SCLK
SPI[0]_SCLK
PINCNTL82 /
0x4814 0944
0x0006 0000
0x01
I/O
PIN
H
H
DVDD
HYS [12]
BUFFER
TYPE [13]
Device Pins
Copyright © 2013, Texas Instruments Incorporated
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49
DMVA3, DMVA4
SPRS872B – MAY 2013 – REVISED DECEMBER 2013
www.ti.com
Table 3-11. Ball Characteristics (AAR Package) (continued)
BALL NUMBER [1]
BALL NAME [2]
SIGNAL NAME [3]
PINCNTL
REGISTER NAME
AND ADDRESS[4]
PINCNTL
DEFAULT
VALUE[5]
MODE
[6]
TYPE [7] DSIS [8]
BALL
RESET
STATE [9]
BALL
RESET
REL.
STATE [10]
POWER [11]
G29
SPI[0]_SCS[0]
SPI[0]_SCS[0]
PINCNTL81 /
0x4814 0940
0x0006 0000
0x01
I/O
PIN
H
H
DVDD
G28
SPI[0]_SCS[1]
SPI[0]_SCS[1]
PINCNTL80 /
0x4814 093C
0x0006 0000
0x01
I/O
1
H
H
DVDD
0x02
I
1
SATA0_ACT0_LED
0x04
O
PIN
EDMA_EVT1
0x20
I
PIN
TIM4_IO
0x40
I/O
PIN
GP1[6]
0x80
I/O
PIN
0x01
I/O
PIN
H
H
DVDD
0x80
I/O
PIN
0x01
I/O
PIN
H
H
DVDD
0x80
I/O
PIN
0x01
I/O
PIN
H
H
DVDD
0x80
I/O
PIN
0x01
I/O
PIN
H
H
DVDD
0x80
I/O
PIN
SD1_SDCD
N23
SPI[1]_D[0]
SPI[1]_D[0]
GP1[26]
M27
SPI[1]_D[1]
SPI[1]_D[1]
GP1[18]
M29
SPI[1]_SCLK
SPI[1]_SCLK
GP1[17]
J29
SPI[1]_SCS[0]
SPI[1]_SCS[0]
GP1[16]
PINCNTL88 /
0x4814 095C
0x0006 0000
PINCNTL87 /
0x4814 0958
0x0006 0000
PINCNTL86 /
0x4814 0954
0x0006 0000
PINCNTL85 /
0x4814 0950
0x0006 0000
T29
TCLK
TCLK
NA /
NA
NA
0x01
I
NA
H
H
DVDD
N28
TDI
TDI
NA /
NA
NA
0x01
I
NA
H
H
DVDD
U26
TDO
TDO
NA /
NA
NA
0x01
O
NA
H
H
DVDD
T31
TMS
TMS
NA /
NA
NA
0x01
I
NA
H
H
DVDD
U24
TRST
TRST
NA /
NA
NA
0x01
I
NA
L
L
DVDD
B9
TV_OUT0
TV_OUT0
NA /
NA
NA
0x01
O
NA
NA
NA
VDDA_VDAC_1P8
B11
TV_RSET
TV_RSET
NA /
NA
NA
0x01
A
NA
NA
NA
VDDA_VDAC_1P8
B10
TV_VFB0
TV_VFB0
NA /
NA
NA
0x01
O
NA
NA
NA
VDDA_VDAC_1P8
D30
UART0_CTS
UART0_CTS
PINCNTL72 /
0x4814 091C
0x000E 0000
0x01
I/O
1
H
H
DVDD
0x08
I/O
1
SPI[1]_SCS[3]
0x10
I/O
1
SD0_SDCD
0x40
I
1
0x01
I
1
H
H
DVDD
0x10
I/O
1
I2C[2]_SCL
0x20
I/O
1
SD1_POW
0x40
O
PIN
GP1[2]
0x80
I/O
PIN
DCAN1_TX
E31
UART0_DCD
UART0_DCD
SPI[0]_SCS[3]
50
PINCNTL74 /
0x4814 0924
0x000E 0000
Device Pins
HYS [12]
BUFFER
TYPE [13]
Copyright © 2013, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: DMVA3
DMVA3, DMVA4
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SPRS872B – MAY 2013 – REVISED DECEMBER 2013
Table 3-11. Ball Characteristics (AAR Package) (continued)
BALL NUMBER [1]
E29
BALL NAME [2]
UART0_DSR
SIGNAL NAME [3]
UART0_DSR
UART0_DTR
1
I/O
1
I2C[2]_SDA
0x20
I/O
1
SD1_SDWP
0x40
I
0
GP1[3]
0x80
I/O
PIN
0x01
O
PIN
0x04
O
PIN
0x80
I/O
PIN
0x01
I
1
0x04
I
1
0x80
I/O
PIN
0x01
O
PIN
0x08
I/O
1
SPI[1]_SCS[2]
0x10
I/O
1
SD2_SDCD
0x40
I
1
PINCNTL76 /
0x4814 092C
0x000E 0000
PINCNTL77 /
0x4814 0930
0x000E 0000
PINCNTL73 /
0x4814 0920
0x000E 0000
GP1[4]
N26
UART0_RIN
UART0_RIN
UART1_RXD
GP1[5]
D31
UART0_RTS
TYPE [7] DSIS [8]
I
UART1_TXD
0x000E 0000
MODE
[6]
0x10
UART0_DTR
PINCNTL75 /
0x4814 0928
PINCNTL
DEFAULT
VALUE[5]
0x01
SPI[0]_SCS[2]
E30
PINCNTL
REGISTER NAME
AND ADDRESS[4]
UART0_RTS
DCAN1_RX
BALL
RESET
STATE [9]
BALL
RESET
REL.
STATE [10]
POWER [11]
H
H
DVDD
H
H
DVDD
H
H
DVDD
H
H
DVDD
J26
UART0_RXD
UART0_RXD
PINCNTL70 /
0x4814 0914
0x000E 0000
0x01
I
PIN
H
H
DVDD
E28
UART0_TXD
UART0_TXD
PINCNTL71 /
0x4814 0918
0x000E 0000
0x01
O
PIN
H
H
DVDD
L22
UART2_RXD
DCAN0_RX
PINCNTL69 /
0x4814 0910
0x000E 0000
0x01
I/O
1
H
H
DVDD
0x02
I
1
I2C[3]_SCL
0x20
I/O
1
GP1[1]
0x80
I/O
PIN
0x01
I/O
1
H
H
DVDD
0x02
O
PIN
I2C[3]_SDA
0x20
I/O
1
GP1[0]
0x80
I/O
PIN
UART2_RXD
M21
UART2_TXD
DCAN0_TX
UART2_TXD
PINCNTL68 /
0x4814 090C
0x000E 0000
B20
USB0_CE
USB0_CE
NA /
NA
NA
0x01
O
NA
NA
NA
VDDA_USB_3P3
B21
USB0_DM
USB0_DM
NA /
NA
NA
0x01
I/O
NA
NA
NA
VDDA_USB_3P3
A21
USB0_DP
USB0_DP
NA /
NA
NA
0x01
I/O
NA
NA
NA
VDDA_USB_3P3
K23
USB0_DRVVBUS
USB0_DRVVBUS
PINCNTL270 /
0x4814 0C34
0x000C 0000
0x01
O
PIN
L
L
DVDD
0x02
I/O
PIN
GP0[7]
A20
USB0_ID
USB0_ID
NA /
NA
NA
0x01
I
NA
NA
NA
VDDA_USB_3P3
B22
USB0_VBUSIN
USB0_VBUSIN
NA /
NA
NA
0x01
I
NA
NA
NA
VDDA_USB_3P3
C21
USB1_CE
USB1_CE
NA /
NA
NA
0x01
O
NA
NA
NA
VDDA_USB_3P3
HYS [12]
BUFFER
TYPE [13]
Device Pins
Copyright © 2013, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: DMVA3
51
DMVA3, DMVA4
SPRS872B – MAY 2013 – REVISED DECEMBER 2013
www.ti.com
Table 3-11. Ball Characteristics (AAR Package) (continued)
BALL NUMBER [1]
BALL NAME [2]
SIGNAL NAME [3]
PINCNTL
REGISTER NAME
AND ADDRESS[4]
PINCNTL
DEFAULT
VALUE[5]
MODE
[6]
TYPE [7] DSIS [8]
BALL
RESET
STATE [9]
BALL
RESET
REL.
STATE [10]
POWER [11]
B23
USB1_DM
USB1_DM
NA /
NA
NA
0x01
I/O
NA
NA
NA
VDDA_USB_3P3
A23
USB1_DP
USB1_DP
NA /
NA
NA
0x01
I/O
NA
NA
NA
VDDA_USB_3P3
A24
USB1_ID
USB1_ID
NA /
NA
NA
0x01
I
NA
NA
NA
VDDA_USB_3P3
B24
USB1_VBUSIN
USB1_VBUSIN
NA /
NA
NA
0x01
I
NA
NA
NA
VDDA_USB_3P3
M25, N22, N25,
P23, R9, T10, T9
VDDA_1P8
VDDA_1P8
NA /
NA
NA
NA
PWR
NA
NA
NA
NA
L19
VDDA_ARMPLL_1P8
VDDA_ARMPLL_1P8
NA /
NA
NA
NA
PWR
NA
NA
NA
NA
V9
VDDA_AUDIOPLL_1P8
VDDA_AUDIOPLL_1P8
NA /
NA
NA
NA
PWR
NA
NA
NA
NA
W10
VDDA_CSI2_1P8
VDDA_CSI2_1P8
NA /
NA
NA
NA
PWR
NA
NA
NA
NA
AA19
VDDA_DDRPLL_1P8
VDDA_DDRPLL_1P8
NA /
NA
NA
NA
PWR
NA
NA
NA
NA
L15
VDDA_HDDACREF_1P8
VDDA_HDDACREF_1P8
NA /
NA
NA
NA
PWR
NA
NA
NA
NA
K16
VDDA_HDDAC_1P1
VDDA_HDDAC_1P1
NA /
NA
NA
NA
PWR
NA
NA
NA
NA
L14
VDDA_HDDAC_1P8
VDDA_HDDAC_1P8
NA /
NA
NA
NA
PWR
NA
NA
NA
NA
K14
VDDA_HDMI_1P8
VDDA_HDMI_1P8
NA /
NA
NA
NA
PWR
NA
NA
NA
NA
T23
VDDA_HDVICPPLL_1P8
VDDA_HDVICPPLL_1P8
NA /
NA
NA
NA
PWR
NA
NA
NA
NA
W11
VDDA_L3L4_1P8
VDDA_L3L4PLL_1P8
NA /
NA
NA
NA
PWR
NA
NA
NA
NA
M26
VDDA_PCIE_1P8
VDDA_PCIE_1P8
NA /
NA
NA
NA
PWR
NA
NA
NA
NA
N27
VDDA_SATA0_1P8
VDDA_SATA0_1P8
NA /
NA
NA
NA
PWR
NA
NA
NA
NA
K19
VDDA_USB0_1P8
VDDA_USB0_1P8
NA /
NA
NA
NA
PWR
NA
NA
NA
NA
J17
VDDA_USB1_1P8
VDDA_USB1_1P8
NA /
NA
NA
NA
PWR
NA
NA
NA
NA
M19, M20
VDDA_USB_3P3
VDDA_USB_3P3
NA /
NA
NA
NA
PWR
NA
NA
NA
NA
J14
VDDA_VDAC_1P8
VDDA_VDAC_1P8
NA /
NA
NA
NA
PWR
NA
NA
NA
NA
L13
VDDA_VIDPLL_1P8
VDDA_VIDPLL_1P8
NA /
NA
NA
NA
PWR
NA
NA
NA
NA
P21
VDDS_OSC0_1P8
VDDS_OSC0_1P8
NA /
NA
NA
NA
PWR
NA
NA
NA
NA
52
Device Pins
HYS [12]
BUFFER
TYPE [13]
Copyright © 2013, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: DMVA3
DMVA3, DMVA4
www.ti.com
SPRS872B – MAY 2013 – REVISED DECEMBER 2013
Table 3-11. Ball Characteristics (AAR Package) (continued)
BALL NUMBER [1]
BALL NAME [2]
SIGNAL NAME [3]
PINCNTL
REGISTER NAME
AND ADDRESS[4]
PINCNTL
DEFAULT
VALUE[5]
MODE
[6]
TYPE [7] DSIS [8]
BALL
RESET
STATE [9]
BALL
RESET
REL.
STATE [10]
POWER [11]
P20
VDDS_OSC1_1P8
VDDS_OSC1_1P8
NA /
NA
NA
NA
PWR
NA
NA
NA
NA
C9
VIN[0]A_CLK
VIN[0]A_CLK
PINCNTL137 /
0x4814 0A20
0x000C 0000
0x01
I
0
L
L
DVDD
0x80
I/O
PIN
PINCNTL140 /
0x4814 0A2C
0x000C 0000
0x01
I
PIN
L
L
DVDD
0x80
I/O
PIN
PINCNTL141 /
0x4814 0A30
0x000C 0000
0x01
I
PIN
L
L
DVDD
0x80
I/O
PIN
PINCNTL142 /
0x4814 0A34
0x000C 0000
0x01
I
PIN
L
L
DVDD
0x80
I/O
PIN
PINCNTL143 /
0x4814 0A38
0x000C 0000
0x01
I
PIN
L
L
DVDD
0x80
I/O
PIN
PINCNTL144 /
0x4814 0A3C
0x000C 0000
0x01
I
PIN
L
L
DVDD
0x80
I/O
PIN
PINCNTL145 /
0x4814 0A40
0x000C 0000
0x01
I
PIN
L
L
DVDD
0x80
I/O
PIN
PINCNTL146 /
0x4814 0A44
0x000C 0000
0x01
I
PIN
L
L
DVDD
0x80
I/O
PIN
PINCNTL147 /
0x4814 0A48
0x000C 0000
0x01
I
PIN
L
L
DVDD
0x80
I/O
PIN
PINCNTL156 /
0x4814 0A6C
0x000E 0000
0x01
I
PIN
H
H
DVDD_C
0x02
I
PIN
I2C[2]_SCL
0x20
I/O
1
GP0[10]
0x80
I/O
PIN
0x01
I
PIN
L
L
DVDD_C
0x02
I
PIN
EMAC[1]_RMRXER
0x08
I
0
GP0[11]
0x80
I/O
PIN
0x01
I
PIN
H
H
DVDD_C
0x02
I
PIN
EMAC[1]_RMRXD[1]
0x08
I
PIN
I2C[3]_SCL
0x20
I/O
1
GP0[12]
0x80
I/O
PIN
0x01
I
PIN
H
H
DVDD_C
0x02
I
PIN
EMAC[1]_RMRXD[0]
0x08
I
PIN
I2C[3]_SDA
0x20
I/O
1
GP0[13]
0x80
I/O
PIN
GP2[2]
B18
VIN[0]A_D[0]
VIN[0]A_D[0]
GP1[11]
A17
VIN[0]A_D[1]
VIN[0]A_D[1]
GP1[12]
B17
VIN[0]A_D[2]
VIN[0]A_D[2]
GP2[7]
C17
VIN[0]A_D[3]
VIN[0]A_D[3]
GP2[8]
D17
VIN[0]A_D[4]
VIN[0]A_D[4]
GP2[9]
F17
VIN[0]A_D[5]
VIN[0]A_D[5]
GP2[10]
L20
VIN[0]A_D[6]
VIN[0]A_D[6]
GP2[11]
H20
VIN[0]A_D[7]
VIN[0]A_D[7]
GP2[12]
K11
VIN[0]A_D[16]
VIN[0]A_D[16]
CAM_D[8]
E12
VIN[0]A_D[17]
VIN[0]A_D[17]
CAM_D[9]
K10
VIN[0]A_D[18]
VIN[0]A_D[18]
CAM_D[10]
D7
VIN[0]A_D[19]
VIN[0]A_D[19]
CAM_D[11]
PINCNTL157 /
0x4814 0A70
PINCNTL158 /
0x4814 0A74
PINCNTL159 /
0x4814 0A78
0x000C 0000
0x000E 0000
0x000E 0000
HYS [12]
BUFFER
TYPE [13]
Device Pins
Copyright © 2013, Texas Instruments Incorporated
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DMVA3, DMVA4
SPRS872B – MAY 2013 – REVISED DECEMBER 2013
www.ti.com
Table 3-11. Ball Characteristics (AAR Package) (continued)
BALL NUMBER [1]
F9
BALL NAME [2]
VIN[0]A_D[20]
SIGNAL NAME [3]
VIN[0]A_D[20]
VIN[0]A_D[21]
PIN
I
PIN
EMAC[1]_RMCRSDV
0x08
I
0
SPI[3]_SCS[0]
0x20
I/O
1
GP0[14]
0x80
I/O
PIN
0x01
I
PIN
0x02
I
PIN
EMAC[1]_RMTXD[0]
0x08
O
PIN
SPI[3]_SCLK
0x20
I/O
1
GP0[15]
0x80
I/O
PIN
0x01
I
PIN
0x02
I
PIN
EMAC[1]_RMTXD[1]
0x08
O
PIN
SPI[3]_D[1]
0x20
I/O
PIN
GP0[16]
0x80
I/O
PIN
0x01
I
PIN
0x02
I
PIN
EMAC[1]_RMTXEN
0x08
O
PIN
SPI[3]_D[0]
0x20
I/O
PIN
GP0[17]
0x80
I/O
PIN
0x01
I
0
0x10
I
0
I2C[2]_SDA
0x40
I/O
1
GP2[0]
0x80
I/O
PIN
0x01
I
0
0x02
I
PIN
0x80
I/O
PIN
0x01
I
PIN
0x80
I/O
PIN
0x01
I
PIN
0x20
I
0
0x80
I/O
PIN
0x01
I
PIN
0x20
I/O
PIN
0x80
I/O
PIN
0x01
I
PIN
0x20
I/O
0
0x80
I/O
PIN
CAM_D[13]
A6
VIN[0]A_D[22]
VIN[0]A_D[22]
CAM_D[14]
A5
VIN[0]A_D[23]
VIN[0]A_D[23]
CAM_D[15]
C12
VIN[0]A_DE
VIN[0]A_DE
VIN[0]B_HSYNC
B5
VIN[0]A_DE
VIN[0]A_DE
CAM_D[7]
PINCNTL162 /
0x4814 0A84
PINCNTL163 /
0x4814 0A88
PINCNTL135 /
0x4814 0A18
0x0004 0000
0x0004 0000
0x0004 0000
0x000E 0000
PINCNTL164 /
0x4814 0A8C
0x0006 0000
PINCNTL150 /
0x4814 0A54
0x000C 0000
PINCNTL151 /
0x4814 0A58
0x000C 0000
PINCNTL152 /
0x4814 0A5C
0x0004 0000
PINCNTL153 /
0x4814 0A60
0x000C 0000
GP0[18]
E16
VIN[0]A_D[10]_BD[2]
VIN[0]A_D[10]_BD[2]
GP2[15]
H17
VIN[0]A_D[11]_BD[3]
VIN[0]A_D[11]_BD[3]
CAM_WE
GP2[16]
J16
VIN[0]A_D[12]_BD[4]
VIN[0]A_D[12]_BD[4]
CLKOUT1
GP2[17]
H16
VIN[0]A_D[13]_BD[5]
VIN[0]A_D[13]_BD[5]
CAM_RESET
GP2[18]
54
TYPE [7] DSIS [8]
I
PINCNTL161 /
0x4814 0A80
0x000C 0000
MODE
[6]
0x02
VIN[0]A_D[21]
PINCNTL160 /
0x4814 0A7C
PINCNTL
DEFAULT
VALUE[5]
0x01
CAM_D[12]
C7
PINCNTL
REGISTER NAME
AND ADDRESS[4]
Device Pins
BALL
RESET
STATE [9]
BALL
RESET
REL.
STATE [10]
POWER [11]
L
L
DVDD_C
L
L
DVDD_C
L
L
DVDD_C
L
L
DVDD_C
H
H
DVDD
H
H
DVDD_C
L
L
DVDD
L
L
DVDD
L
L
DVDD
L
L
DVDD
HYS [12]
BUFFER
TYPE [13]
Copyright © 2013, Texas Instruments Incorporated
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DMVA3, DMVA4
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SPRS872B – MAY 2013 – REVISED DECEMBER 2013
Table 3-11. Ball Characteristics (AAR Package) (continued)
BALL NUMBER [1]
F13
BALL NAME [2]
VIN[0]A_D[14]_BD[6]
SIGNAL NAME [3]
VIN[0]A_D[14]_BD[6]
PINCNTL
REGISTER NAME
AND ADDRESS[4]
PINCNTL
DEFAULT
VALUE[5]
0x000C 0000
I
PIN
0x20
O
PIN
PINCNTL155 /
0x4814 0A68
0x000C 0000
0x80
I/O
PIN
0x01
I
PIN
0x20
O
PIN
PINCNTL148 /
0x4814 0A4C
0x000C 0000
0x80
I/O
PIN
0x01
I
PIN
0x80
I/O
PIN
PINCNTL149 /
0x4814 0A50
0x000C 0000
0x01
I
PIN
0x80
I/O
PIN
PINCNTL136 /
0x4814 0A1C
0x000E 0000
0x01
I
0
0x10
I
0
I2C[2]_SCL
0x40
I/O
1
GP2[1]
0x80
I/O
PIN
0x01
I
0
0x02
I
PIN
0x80
I/O
PIN
0x01
I
0
0x80
I/O
PIN
0x01
I
0
0x80
I/O
PIN
0x01
I
0
0x20
O
PIN
0x80
I/O
PIN
0x01
I
0
0x02
I
PIN
0x80
I/O
PIN
0x01
I
0
0x02
I
PIN
0x80
I/O
PIN
0x01
O
PIN
0x02
O
PIN
SPI[3]_SCLK
0x10
I/O
1
TIM7_IO
0x40
I/O
PIN
GP2[21]
0x80
I/O
PIN
0x01
O
PIN
0x02
I/O
1
0x80
I/O
PIN
GP2[19]
H13
VIN[0]A_D[15]_BD[7]
VIN[0]A_D[15]_BD[7]
CAM_SHUTTER
GP2[20]
B16
VIN[0]A_D[8]_BD[0]
VIN[0]A_D[8]_BD[0]
GP2[13]
C16
VIN[0]A_D[9]_BD[1]
VIN[0]A_D[9]_BD[1]
GP2[14]
J13
VIN[0]A_FLD
VIN[0]A_FLD
VIN[0]B_VSYNC
B4
VIN[0]A_FLD
VIN[0]A_FLD
CAM_D[5]
PINCNTL166 /
0x4814 0A94
0x0006 0000
PINCNTL138 /
0x4814 0A24
0x000E 0000
PINCNTL139 /
0x4814 0A28
0x000E 0000
PINCNTL134 /
0x4814 0A14
0x0004 0000
PINCNTL165 /
0x4814 0A90
0x0006 0000
PINCNTL167 /
0x4814 0A98
0x0006 0000
PINCNTL179 /
0x4814 0AC8
0x000C 0000
GP0[20]
D13
VIN[0]A_HSYNC
VIN[0]A_HSYNC
GP2[3]
C13
VIN[0]A_VSYNC
VIN[0]A_VSYNC
GP2[4]
H12
VIN[0]B_CLK
VIN[0]B_CLK
CLKOUT0
GP1[9]
C5
VIN[0]B_DE
VIN[0]B_DE
CAM_D[6]
GP0[19]
A3
VIN[0]B_FLD
VIN[0]B_FLD
CAM_D[4]
GP0[21]
C20
VOUT[0]_AVID
VOUT[0]_AVID
VOUT[0]_FLD
F24
VOUT[0]_B_CB_C[2]
TYPE [7] DSIS [8]
0x01
CAM_STROBE
PINCNTL154 /
0x4814 0A64
MODE
[6]
VOUT[0]_B_CB_C[2]
EMU2
GP2[22]
PINCNTL180 /
0x4814 0ACC
0x000C 0000
BALL
RESET
STATE [9]
BALL
RESET
REL.
STATE [10]
POWER [11]
L
L
DVDD
L
L
DVDD
L
L
DVDD
L
L
DVDD
H
H
DVDD
H
H
DVDD_C
H
H
DVDD
H
H
DVDD
L
L
DVDD
H
H
DVDD_C
H
H
DVDD_C
L
L
DVDD
L
L
DVDD
HYS [12]
BUFFER
TYPE [13]
Device Pins
Copyright © 2013, Texas Instruments Incorporated
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Product Folder Links: DMVA3
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DMVA3, DMVA4
SPRS872B – MAY 2013 – REVISED DECEMBER 2013
www.ti.com
Table 3-11. Ball Characteristics (AAR Package) (continued)
BALL NUMBER [1]
D21
BALL NAME [2]
VOUT[0]_B_CB_C[3]
SIGNAL NAME [3]
VOUT[0]_B_CB_C[3]
GP2[23]
PINCNTL
REGISTER NAME
AND ADDRESS[4]
PINCNTL
DEFAULT
VALUE[5]
PINCNTL181 /
0x4814 0AD0
0x000C 0000
MODE
[6]
TYPE [7] DSIS [8]
0x01
O
PIN
0x80
I/O
PIN
BALL
RESET
STATE [9]
BALL
RESET
REL.
STATE [10]
POWER [11]
L
L
DVDD
J23
VOUT[0]_B_CB_C[4]
VOUT[0]_B_CB_C[4]
PINCNTL182 /
0x4814 0AD4
0x000C 0000
0x01
O
PIN
L
L
DVDD
H23
VOUT[0]_B_CB_C[5]
VOUT[0]_B_CB_C[5]
PINCNTL183 /
0x4814 0AD8
0x000C 0000
0x01
O
PIN
L
L
DVDD
J24
VOUT[0]_B_CB_C[6]
VOUT[0]_B_CB_C[6]
PINCNTL184 /
0x4814 0ADC
0x000C 0000
0x01
O
PIN
L
L
DVDD
E24
VOUT[0]_B_CB_C[7]
VOUT[0]_B_CB_C[7]
PINCNTL185 /
0x4814 0AE0
0x000C 0000
0x01
O
PIN
L
L
DVDD
D24
VOUT[0]_B_CB_C[8]
VOUT[0]_B_CB_C[8]
PINCNTL186 /
0x4814 0AE4
0x000C 0000
0x01
O
PIN
L
L
DVDD
C24
VOUT[0]_B_CB_C[9]
VOUT[0]_B_CB_C[9]
PINCNTL187 /
0x4814 0AE8
0x000C 0000
0x01
O
PIN
L
L
DVDD
K22
VOUT[0]_CLK
VOUT[0]_CLK
PINCNTL176 /
0x4814 0ABC
0x000C 0000
0x01
O
PIN
L
L
DVDD
B3
VOUT[0]_FLD
VOUT[0]_FLD
PINCNTL175 /
0x4814 0AB8
0x0004 0000
0x01
O
PIN
L
L
DVDD_C
0x02
I
0
GPMC_A[12]
0x10
O
PIN
UART2_RTS
0x20
O
PIN
GP2[02]
0x80
I/O
PIN
0x01
O
PIN
L
L
DVDD
0x02
I/O
1
0x80
I/O
PIN
0x01
O
PIN
L
L
DVDD
0x80
I/O
PIN
CAM_PCLK
C25
VOUT[0]_G_Y_YC[2]
VOUT[0]_G_Y_YC[2]
EMU3
PINCNTL188 /
0x4814 0AEC
0x000C 0000
PINCNTL189 /
0x4814 0AF0
0x000C 0000
GP2[24]
C26
VOUT[0]_G_Y_YC[3]
VOUT[0]_G_Y_YC[3]
GP2[25]
E26
VOUT[0]_G_Y_YC[4]
VOUT[0]_G_Y_YC[4]
PINCNTL190 /
0x4814 0AF4
0x000C 0000
0x01
O
PIN
L
L
DVDD
B26
VOUT[0]_G_Y_YC[5]
VOUT[0]_G_Y_YC[5]
PINCNTL191 /
0x4814 0AF8
0x000C 0000
0x01
O
PIN
L
L
DVDD
A26
VOUT[0]_G_Y_YC[6]
VOUT[0]_G_Y_YC[6]
PINCNTL192 /
0x4814 0AFC
0x000C 0000
0x01
O
PIN
L
L
DVDD
B25
VOUT[0]_G_Y_YC[7]
VOUT[0]_G_Y_YC[7]
PINCNTL193 /
0x4814 0B00
0x000C 0000
0x01
O
PIN
L
L
DVDD
B27
VOUT[0]_G_Y_YC[8]
VOUT[0]_G_Y_YC[8]
PINCNTL194 /
0x4814 0B04
0x000C 0000
0x01
O
PIN
L
L
DVDD
A27
VOUT[0]_G_Y_YC[9]
VOUT[0]_G_Y_YC[9]
PINCNTL195 /
0x4814 0B08
0x000C 0000
0x01
O
PIN
L
L
DVDD
F21
VOUT[0]_HSYNC
VOUT[0]_HSYNC
PINCNTL177 /
0x4814 0AC0
0x000C 0000
0x01
O
PIN
L
L
DVDD
C28
VOUT[0]_R_CR[2]
VOUT[0]_R_CR[2]
PINCNTL196 /
0x4814 0B0C
0x000C 0000
0x01
O
PIN
L
L
DVDD
0x02
I/O
1
0x80
I/O
PIN
EMU4
GP2[26]
56
Device Pins
HYS [12]
BUFFER
TYPE [13]
Copyright © 2013, Texas Instruments Incorporated
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DMVA3, DMVA4
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SPRS872B – MAY 2013 – REVISED DECEMBER 2013
Table 3-11. Ball Characteristics (AAR Package) (continued)
BALL NUMBER [1]
B28
BALL NAME [2]
VOUT[0]_R_CR[3]
SIGNAL NAME [3]
VOUT[0]_R_CR[3]
GP2[27]
PINCNTL
REGISTER NAME
AND ADDRESS[4]
PINCNTL
DEFAULT
VALUE[5]
PINCNTL197 /
0x4814 0B10
0x000C 0000
MODE
[6]
TYPE [7] DSIS [8]
0x01
O
PIN
0x80
I/O
PIN
BALL
RESET
STATE [9]
BALL
RESET
REL.
STATE [10]
POWER [11]
L
L
DVDD
B29
VOUT[0]_R_CR[4]
VOUT[0]_R_CR[4]
PINCNTL198 /
0x4814 0B14
0x000C 0000
0x01
O
PIN
L
L
DVDD
A29
VOUT[0]_R_CR[5]
VOUT[0]_R_CR[5]
PINCNTL199 /
0x4814 0B18
0x000C 0000
0x01
O
PIN
L
L
DVDD
C30
VOUT[0]_R_CR[6]
VOUT[0]_R_CR[6]
PINCNTL200 /
0x4814 0B1C
0x000C 0000
0x01
O
PIN
L
L
DVDD
B30
VOUT[0]_R_CR[7]
VOUT[0]_R_CR[7]
PINCNTL201 /
0x4814 0B20
0x000C 0000
0x01
O
PIN
L
L
DVDD
A30
VOUT[0]_R_CR[8]
VOUT[0]_R_CR[8]
PINCNTL202 /
0x4814 0B24
0x000C 0000
0x01
O
PIN
L
L
DVDD
B31
VOUT[0]_R_CR[9]
VOUT[0]_R_CR[9]
PINCNTL203 /
0x4814 0B28
0x000C 0000
0x01
O
PIN
L
L
DVDD
E20
VOUT[0]_VSYNC
VOUT[0]_VSYNC
PINCNTL178 /
0x4814 0AC4
0x000C 0000
0x01
O
PIN
L
L
DVDD
F1
VOUT[1]_AVID
VOUT[1]_AVID
PINCNTL207 /
0x4814 0B38
0x0004 0000
0x01
O
PIN
L
L
DVDD
0x02
I
0
VIN[1]A_CLK
0x04
I
0
TIM6_IO
0x40
I/O
PIN
GP2[31]
0x80
I/O
PIN
0x01
O
PIN
H
H
DVDD_C
0x02
I/O
0
GPMC_A[10]
0x10
O
PIN
UART2_TXD
0x20
O
PIN
GP0[27]
0x80
I/O
PIN
0x01
O
PIN
L
L
DVDD_C
0x02
I/O
0
GPMC_A[9]
0x10
O
PIN
UART2_RXD
0x20
I
1
GP0[26]
0x80
I/O
PIN
0x01
O
PIN
H
H
DVDD
0x02
O
PIN
VIN[1]A_D[7]
0x04
I
PIN
HDMI_CEC
0x10
I/O
1
SPI[2]_D[0]
0x20
I/O
PIN
GP3[30]
0x80
I/O
PIN
EMAC[1]_MRXER
H9
VOUT[1]_B_CB_C[0]
VOUT[1]_B_CB_C[0]
CAM_VS
D5
VOUT[1]_B_CB_C[1]
VOUT[1]_B_CB_C[1]
CAM_HS
M8
VOUT[1]_B_CB_C[2]
VOUT[1]_B_CB_C[2]
GPMC_A[0]
PINCNTL173 /
0x4814 0AB0
PINCNTL172 /
0x4814 0AAC
PINCNTL231 /
0x4814 0B98
0x0006 0000
0x0004 0000
0x0006 0000
HYS [12]
BUFFER
TYPE [13]
Device Pins
Copyright © 2013, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: DMVA3
57
DMVA3, DMVA4
SPRS872B – MAY 2013 – REVISED DECEMBER 2013
www.ti.com
Table 3-11. Ball Characteristics (AAR Package) (continued)
BALL NUMBER [1]
F2
BALL NAME [2]
VOUT[1]_B_CB_C[3]
SIGNAL NAME [3]
VOUT[1]_B_CB_C[3]
VOUT[1]_B_CB_C[4]
PIN
I
0
VIN[1]A_D[0]
0x04
I
PIN
GP3[0]
0x80
I/O
PIN
0x01
O
PIN
0x02
I
PIN
VIN[1]A_D[1]
0x04
I
PIN
GP3[1]
0x80
I/O
PIN
0x01
O
PIN
0x02
I
PIN
VIN[1]A_D[2]
0x04
I
PIN
GP3[2]
0x80
I/O
PIN
0x01
O
PIN
0x02
I
PIN
VIN[1]A_D[3]
0x04
I
PIN
GP3[3]
0x80
I/O
PIN
0x01
O
PIN
0x02
I
PIN
VIN[1]A_D[4]
0x04
I
PIN
GP3[4]
0x80
I/O
PIN
0x01
O
PIN
0x02
I
PIN
VIN[1]A_D[5]
0x04
I
PIN
I2C[3]_SCL
0x20
I/O
1
GP3[5]
0x80
I/O
PIN
0x01
O
PIN
0x02
I
PIN
VIN[1]A_D[6]
0x04
I
PIN
I2C[3]_SDA
0x20
I/O
1
GP3[6]
0x80
I/O
PIN
0x01
O
PIN
0x02
I
0
VIN[1]A_HSYNC
0x04
I
0
GP2[28]
0x80
I/O
PIN
EMAC[1]_MRXD[0]
G1
VOUT[1]_B_CB_C[5]
VOUT[1]_B_CB_C[5]
EMAC[1]_MRXD[1]
G2
VOUT[1]_B_CB_C[6]
VOUT[1]_B_CB_C[6]
EMAC[1]_MRXD[2]
H3
VOUT[1]_B_CB_C[7]
VOUT[1]_B_CB_C[7]
EMAC[1]_MRXD[3]
G3
VOUT[1]_B_CB_C[8]
VOUT[1]_B_CB_C[8]
EMAC[1]_MRXD[4]
H5
VOUT[1]_B_CB_C[9]
VOUT[1]_B_CB_C[9]
EMAC[1]_MRXD[5]
D3
VOUT[1]_CLK
VOUT[1]_CLK
EMAC[1]_MTCLK
58
TYPE [7] DSIS [8]
O
PINCNTL209 /
0x4814 0B40
PINCNTL210 /
0x4814 0B44
PINCNTL211 /
0x4814 0B48
PINCNTL212 /
0x4814 0B4C
PINCNTL213 /
0x4814 0B50
PINCNTL214 /
0x4814 0B54
PINCNTL204 /
0x4814 0B2C
0x0004 0000
MODE
[6]
0x02
VOUT[1]_B_CB_C[4]
PINCNTL208 /
0x4814 0B3C
PINCNTL
DEFAULT
VALUE[5]
0x01
EMAC[1]_MRCLK
F3
PINCNTL
REGISTER NAME
AND ADDRESS[4]
0x0004 0000
0x0004 0000
0x0004 0000
0x0004 0000
0x0004 0000
0x0004 0000
0x0004 0000
Device Pins
BALL
RESET
STATE [9]
BALL
RESET
REL.
STATE [10]
POWER [11]
L
L
DVDD
L
L
DVDD
L
L
DVDD
L
L
DVDD
L
L
DVDD
L
L
DVDD
L
L
DVDD
L
L
DVDD
HYS [12]
BUFFER
TYPE [13]
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Table 3-11. Ball Characteristics (AAR Package) (continued)
BALL NUMBER [1]
J10
BALL NAME [2]
VOUT[1]_FLD
SIGNAL NAME [3]
VOUT[1]_FLD
VOUT[1]_G_Y_YC[0]
PIN
I/O
0
CAM_WE
0x04
I
0
GPMC_A[11]
0x10
O
PIN
UART2_CTS
0x20
I/O
1
GP0[28]
0x80
I/O
PIN
0x01
O
PIN
0x02
I
PIN
GPMC_A[6]
0x10
O
PIN
GP0[23]
0x80
I/O
PIN
0x01
O
PIN
0x02
I
PIN
GPMC_A[5]
0x10
O
PIN
GP0[22]
0x80
I/O
PIN
0x01
O
PIN
0x02
O
PIN
VIN[1]A_D[21]
0x04
I
PIN
HDMI_SCL
0x10
I/O
1
SPI[2]_SCS[2]
0x20
I/O
1
I2C[2]_SCL
0x40
I/O
1
GP3[20]
0x80
I/O
PIN
0x01
O
PIN
0x02
I
PIN
VIN[1]A_D[8]
0x04
I
PIN
GP3[7]
0x80
I/O
PIN
0x01
O
PIN
0x02
I
PIN
VIN[1]A_D[9]
0x04
I
PIN
GP3[8]
0x80
I/O
PIN
0x01
O
PIN
0x02
I
0
VIN[1]A_D[10]
0x04
I
PIN
GP3[9]
0x80
I/O
PIN
0x01
O
PIN
0x02
O
PIN
VIN[1]A_D[11]
0x04
I
PIN
GP3[10]
0x80
I/O
PIN
CAM_D[2]
A2
VOUT[1]_G_Y_YC[1]
VOUT[1]_G_Y_YC[1]
CAM_D[3]
L2
VOUT[1]_G_Y_YC[2]
VOUT[1]_G_Y_YC[2]
GPMC_A[13]
H6
VOUT[1]_G_Y_YC[3]
VOUT[1]_G_Y_YC[3]
EMAC[1]_MRXD[6]
J8
VOUT[1]_G_Y_YC[4]
VOUT[1]_G_Y_YC[4]
EMAC[1]_MRXD[7]
J1
VOUT[1]_G_Y_YC[5]
VOUT[1]_G_Y_YC[5]
EMAC[1]_MRXDV
H4
VOUT[1]_G_Y_YC[6]
TYPE [7] DSIS [8]
O
VOUT[1]_G_Y_YC[6]
EMAC[1]_GMTCLK
PINCNTL169 /
0x4814 0AA0
PINCNTL168 /
0x4814 0A9C
PINCNTL228 /
0x4814 0B8C
PINCNTL215 /
0x4814 0B58
PINCNTL216 /
0x4814 0B5C
PINCNTL217 /
0x4814 0B60
PINCNTL218 /
0x4814 0B64
0x0004 0000
MODE
[6]
0x02
VOUT[1]_G_Y_YC[0]
PINCNTL174 /
0x4814 0AB4
PINCNTL
DEFAULT
VALUE[5]
0x01
CAM_FLD
B2
PINCNTL
REGISTER NAME
AND ADDRESS[4]
0x0004 0000
0x0006 0000
0x0006 0000
0x0004 0000
0x0004 0000
0x0004 0000
0x0004 0000
BALL
RESET
STATE [9]
BALL
RESET
REL.
STATE [10]
POWER [11]
L
L
DVDD_C
L
L
DVDD_C
H
H
DVDD_C
H
H
DVDD
L
L
DVDD
L
L
DVDD
L
L
DVDD
L
L
DVDD
HYS [12]
BUFFER
TYPE [13]
Device Pins
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Table 3-11. Ball Characteristics (AAR Package) (continued)
BALL NUMBER [1]
J9
BALL NAME [2]
VOUT[1]_G_Y_YC[7]
SIGNAL NAME [3]
VOUT[1]_G_Y_YC[7]
VOUT[1]_G_Y_YC[8]
PIN
O
PIN
VIN[1]A_D[12]
0x04
I
PIN
GP3[11]
0x80
I/O
PIN
0x01
O
PIN
0x02
O
PIN
VIN[1]A_D[13]
0x04
I
PIN
GP3[12]
0x80
I/O
PIN
0x01
O
PIN
0x02
O
PIN
VIN[1]A_D[14]
0x04
I
PIN
GP3[13]
0x80
I/O
PIN
0x01
O
PIN
0x02
I
0
VIN[1]A_VSYNC
0x04
I
0
SPI[3]_D[1]
0x10
I/O
PIN
GP2[29]
0x80
I/O
PIN
0x01
O
PIN
0x02
I
PIN
GPMC_A[8]
0x10
O
PIN
GP0[25]
0x80
I/O
PIN
0x01
O
PIN
0x02
I
PIN
GPMC_A[7]
0x10
O
PIN
GP0[24]
0x80
I/O
PIN
0x01
O
PIN
0x02
O
PIN
VIN[1]A_D[23]
0x04
I
PIN
HDMI_HPDET
0x10
I
0
SPI[2]_D[1]
0x20
I/O
PIN
GP3[22]
0x80
I/O
PIN
0x01
O
PIN
0x02
O
PIN
VIN[1]A_D[22]
0x04
I
PIN
HDMI_SDA
0x10
I/O
1
SPI[2]_SCLK
0x20
I/O
1
I2C[2]_SDA
0x40
I/O
1
GP3[21]
0x80
I/O
PIN
EMAC[1]_MTXD[1]
K1
VOUT[1]_G_Y_YC[9]
VOUT[1]_G_Y_YC[9]
EMAC[1]_MTXD[2]
E2
VOUT[1]_HSYNC
VOUT[1]_HSYNC
EMAC[1]_MCOL
C2
VOUT[1]_R_CR[0]
VOUT[1]_R_CR[0]
CAM_D[0]
C1
VOUT[1]_R_CR[1]
VOUT[1]_R_CR[1]
CAM_D[1]
L6
VOUT[1]_R_CR[2]
VOUT[1]_R_CR[2]
GPMC_A[15]
L4
VOUT[1]_R_CR[3]
VOUT[1]_R_CR[3]
GPMC_A[14]
60
TYPE [7] DSIS [8]
O
PINCNTL220 /
0x4814 0B6C
PINCNTL221 /
0x4814 0B70
PINCNTL205 /
0x4814 0B30
PINCNTL171 /
0x4814 0AA8
PINCNTL170 /
0x4814 0AA4
PINCNTL230 /
0x4814 0B94
PINCNTL229 /
0x4814 0B90
0x0004 0000
MODE
[6]
0x02
VOUT[1]_G_Y_YC[8]
PINCNTL219 /
0x4814 0B68
PINCNTL
DEFAULT
VALUE[5]
0x01
EMAC[1]_MTXD[0]
L3
PINCNTL
REGISTER NAME
AND ADDRESS[4]
0x0004 0000
0x0004 0000
0x0004 0000
0x0004 0000
0x0004 0000
0x0004 0000
0x0006 0000
Device Pins
BALL
RESET
STATE [9]
BALL
RESET
REL.
STATE [10]
POWER [11]
L
L
DVDD
L
L
DVDD
L
L
DVDD
L
L
DVDD
L
L
DVDD_C
L
L
DVDD_C
L
L
DVDD
H
H
DVDD
HYS [12]
BUFFER
TYPE [13]
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SPRS872B – MAY 2013 – REVISED DECEMBER 2013
Table 3-11. Ball Characteristics (AAR Package) (continued)
BALL NUMBER [1]
H2
BALL NAME [2]
VOUT[1]_R_CR[4]
SIGNAL NAME [3]
VOUT[1]_R_CR[4]
VOUT[1]_R_CR[5]
PIN
O
PIN
VIN[1]A_D[15]
0x04
I
PIN
SPI[3]_SCS[1]
0x20
I/O
1
GP3[14]
0x80
I/O
PIN
0x01
O
PIN
0x02
O
PIN
VIN[1]A_D[16]
0x04
I
PIN
SPI[3]_SCLK
0x20
I/O
1
GP3[15]
0x80
I/O
PIN
0x01
O
PIN
0x02
O
PIN
VIN[1]A_D[17]
0x04
I
PIN
SPI[3]_D[1]
0x20
I/O
PIN
GP3[16]
0x80
I/O
PIN
0x01
O
PIN
0x02
O
PIN
VIN[1]A_D[18]
0x04
I
PIN
SPI[3]_D[0]
0x20
I/O
PIN
GP3[17]
0x80
I/O
PIN
0x01
O
PIN
0x02
O
PIN
VIN[1]A_D[19]
0x04
I
PIN
GP3[18]
0x80
I/O
PIN
0x01
O
PIN
0x02
O
PIN
VIN[1]A_D[20]
0x04
I
PIN
GP3[19]
0x80
I/O
PIN
0x01
O
PIN
0x02
I
0
VIN[1]A_FLD
0x04
I
0
VIN[1]A_DE
0x08
I
0
SPI[3]_D[0]
0x10
I/O
PIN
GP2[30]
0x80
I/O
PIN
NA
PWR
NA
EMAC[1]_MTXD[4]
L12
VOUT[1]_R_CR[6]
VOUT[1]_R_CR[6]
EMAC[1]_MTXD[5]
M10
VOUT[1]_R_CR[7]
VOUT[1]_R_CR[7]
EMAC[1]_MTXD[6]
J2
VOUT[1]_R_CR[8]
VOUT[1]_R_CR[8]
EMAC[1]_MTXD[7]
K2
VOUT[1]_R_CR[9]
VOUT[1]_R_CR[9]
EMAC[1]_MTXEN
F5
VOUT[1]_VSYNC
VOUT[1]_VSYNC
EMAC[1]_MCRS
AL18
VREFSSTL_DDR[0]
TYPE [7] DSIS [8]
O
VREFSSTL_DDR[0]
PINCNTL223 /
0x4814 0B78
PINCNTL224 /
0x4814 0B7C
PINCNTL225 /
0x4814 0B80
PINCNTL226 /
0x4814 0B84
PINCNTL227 /
0x4814 0B88
PINCNTL206 /
0x4814 0B34
NA /
NA
0x0004 0000
MODE
[6]
0x02
VOUT[1]_R_CR[5]
PINCNTL222 /
0x4814 0B74
PINCNTL
DEFAULT
VALUE[5]
0x01
EMAC[1]_MTXD[3]
M11
PINCNTL
REGISTER NAME
AND ADDRESS[4]
0x0004 0000
0x0004 0000
0x0004 0000
0x0004 0000
0x0004 0000
0x0004 0000
NA
BALL
RESET
STATE [9]
BALL
RESET
REL.
STATE [10]
POWER [11]
L
L
DVDD
L
L
DVDD
L
L
DVDD
L
L
DVDD
L
L
DVDD
L
L
DVDD
L
L
DVDD
NA
NA
DVDD_DDR[0]
HYS [12]
BUFFER
TYPE [13]
Device Pins
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Table 3-11. Ball Characteristics (AAR Package) (continued)
BALL NUMBER [1]
BALL NAME [2]
SIGNAL NAME [3]
PINCNTL
REGISTER NAME
AND ADDRESS[4]
PINCNTL
DEFAULT
VALUE[5]
MODE
[6]
TYPE [7] DSIS [8]
BALL
RESET
STATE [9]
BALL
RESET
REL.
STATE [10]
POWER [11]
A1, A31, AA13,
VSS
AA14, AA15, AA16,
AA17, AA18, AA27,
AC25, AD24, AD25,
AD3, AD4, AD5,
AD6, AD7, AE12,
AE19, AE20, AE23,
AE24, AE25, AE26,
AE27, AE28, AE5,
AE6, AE7, AE8,
AE9, AF12, AF20,
AF24, AF25, AF7,
AG11, AG19,
AG24, AG25, AG7,
AH12, AH20, AH7,
AL1, AL31, D25,
D8, E21, E25, E7,
E8, F20, F25, F7,
F8, G20, G23, G24,
G25, G26, G27,
G4, G5, G6, G7,
G8, H26, H7, J7,
L16, M16, N13,
N14, N16, N17,
P11, P12, P14,
P18, R11, R12,
R14, R18, R20,
R21, T11, T12,
T14, T15, T16, T19,
T20, T21, U14,
U18, U23, V18,
W16, W17, Y16,
Y17, Y25, Y26, Y28
VSS
NA /
NA
NA
NA
GND
NA
NA
NA
NA
U30
VSSA_AUXOSC
VSSA_AUXOSC
NA /
NA
NA
NA
GND
NA
NA
NA
NA
AC7, V14
VSSA_CSI2
VSSA_CSI2
NA /
NA
NA
NA
GND
NA
NA
NA
NA
G30
VSSA_DEVOSC
VSSA_DEVOSC
NA /
NA
NA
NA
GND
NA
NA
NA
NA
G9, H8
VSSA_HDMI
VSSA_HDMI
NA /
NA
NA
NA
GND
NA
NA
NA
NA
D20, N19, N20
VSSA_USB
VSSA_USB
NA /
NA
NA
NA
GND
NA
NA
NA
NA
C8
VSSA_VDAC
VSSA_VDAC
NA /
NA
NA
NA
GND
NA
NA
NA
NA
62
Device Pins
HYS [12]
BUFFER
TYPE [13]
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3.3
SPRS872B – MAY 2013 – REVISED DECEMBER 2013
Terminal Functions
The terminal functions tables identify the external signal names, the associated pin (ball) numbers along with the mechanical package designator,
the pin type, whether the pin has any internal pullup or pulldown resistors, and a functional pin description. For more detailed information on device
configurations, peripheral selection, and multiplexed/shared pin see Device Configurations section.
(1) SIGNAL NAME: The signal name
(2) DESCRIPTION: Description of the signal
(3) TYPE: Ball type for this specific function:
– I = Input
– O = Output
– I/O = Input/Output
– D = Open drain
– DS = Differential
– A = Analog
(4) BALL: Package ball location
3.3.1
Audio Tracking Logic (ATL)
Table 3-12. ATL Terminal Functions
SIGNAL NAME [1]
DESCRIPTION [2]
TYPE [3]
AAR BALL [4]
ATL_CLKOUT0
Audio Tracking Logic Clock 0 Output
O
AF31
ATL_CLKOUT1
Audio Tracking Logic Clock 1 Output
O
AF31
ATL_CLKOUT2
Audio Tracking Logic Clock 2 Output
O
AF27
ATL_CLKOUT3
Audio Tracking Logic Clock 3 Output
O
AG30
Device Pins
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3.3.2
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Boot Configuration
Table 3-13. Boot Configuration Terminal Functions
SIGNAL NAME [1]
DESCRIPTION [2]
TYPE [3]
AAR BALL [4]
BTMODE[0]
Boot Mode Selection 0. ARM Cortex-A8 Boot Mode
I
Configuration Bits. This pin is multiplexed between ARM
Cortex-A8 boot mode and the General-Purpose Memory
Controller (GPMC) peripheral functions. At reset, the boot
mode inputs BTMODE[4:0] are sampled to determine the
ARM boot configuration. For more details on the types of
boot modes supported, see Section 4.2, Boot Modes, of
this document, along with the ROM Code Memory and
Peripheral Booting chapter of the device Technical
Reference Manual. After reset, this pin functions as
GPMC multiplexed data/address pin 0 (GPMC_D[0]).
W6
BTMODE[1]
Boot Mode Selection 1. ARM Cortex-A8 Boot Mode
I
Configuration Bits. This pin is multiplexed between ARM
Cortex-A8 boot mode and the General-Purpose Memory
Controller (GPMC) peripheral functions. At reset, the boot
mode inputs BTMODE[4:0] are sampled to determine the
ARM boot configuration. For more details on the types of
boot modes supported, see Section 4.2, Boot Modes, of
this document, along with the ROM Code Memory and
Peripheral Booting chapter of the device Technical
Reference Manual. After reset, this pin functions as
GPMC multiplexed data/address pin 1 (GPMC_D[1]).
W4
BTMODE[2]
Boot Mode Selection 2. ARM Cortex-A8 Boot Mode
I
Configuration Bits. This pin is multiplexed between ARM
Cortex-A8 boot mode and the General-Purpose Memory
Controller (GPMC) peripheral functions. At reset, the boot
mode inputs BTMODE[4:0] are sampled to determine the
ARM boot configuration. For more details on the types of
boot modes supported, see Section 4.2, Boot Modes, of
this document, along with the ROM Code Memory and
Peripheral Booting chapter of the device Technical
Reference Manual. After reset, this pin functions as
GPMC multiplexed data/address pin 2 (GPMC_D[2]).
W3
BTMODE[3]
Boot Mode Selection 3. ARM Cortex-A8 Boot Mode
I
Configuration Bits. This pin is multiplexed between ARM
Cortex-A8 boot mode and the General-Purpose Memory
Controller (GPMC) peripheral functions. At reset, the boot
mode inputs BTMODE[4:0] are sampled to determine the
ARM boot configuration. For more details on the types of
boot modes supported, see Section 4.2, Boot Modes, of
this document, along with the ROM Code Memory and
Peripheral Booting chapter of the device Technical
Reference Manual. After reset, this pin functions as
GPMC multiplexed data/address pin 3 (GPMC_D[3]).
U2
BTMODE[4]
Boot Mode Selection 4. ARM Cortex-A8 Boot Mode
I
Configuration Bits. This pin is multiplexed between ARM
Cortex-A8 boot mode and the General-Purpose Memory
Controller (GPMC) peripheral functions. At reset, the boot
mode inputs BTMODE[4:0] are sampled to determine the
ARM boot configuration. For more details on the types of
boot modes supported, see Section 4.2, Boot Modes, of
this document, along with the ROM Code Memory and
Peripheral Booting chapter of the device Technical
Reference Manual. After reset, this pin functions as
GPMC multiplexed data/address pin 4 (GPMC_D[4]).
W9
BTMODE[5]
Boot Mode Selection 5. Reserved Boot Pin. This pin is
multiplexed between ARM Cortex-A8 boot mode and
General-Purpose Memory Controller (GPMC) peripheral
functions. For proper device operation at reset, this pin
should be externally pulled low. After reset, this pin
functions as GPMC multiplexed data/address pin 5
(GPMC_D[5]).
T5
64
Device Pins
I
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SPRS872B – MAY 2013 – REVISED DECEMBER 2013
Table 3-13. Boot Configuration Terminal Functions (continued)
SIGNAL NAME [1]
DESCRIPTION [2]
TYPE [3]
AAR BALL [4]
BTMODE[6]
Boot Mode Selection 6. Reserved Boot Pin. This pin is
multiplexed between ARM Cortex-A8 boot mode and
General-Purpose Memory Controller (GPMC) peripheral
functions. For proper device operation at reset, this pin
should be externally pulled low. After reset, this pin
functions as GPMC multiplexed data/address pin 6
(GPMC_D[6]).
I
T3
BTMODE[7]
Boot Mode Selection 7. RGMII Internal Delay Selection.
This pin is multiplexed between ARM Cortex-A8 boot
mode and General-Purpose Memory Controller (GPMC)
peripheral functions. At reset, BTMODE[7] is sampled to
determine the RGMII Internal Delay Selection:
•
0 = Internal Delay Enabled
•
1 = Internal Delay Disabled
After reset, this pin functions as GPMC multiplexed
data/address pin 7 (GPMC_D[7]).
I
T2
BTMODE[8]
Boot Mode Selection 8. Ethernet PHY Configuration. This I
pin is multiplexed between ARM Cortex-A8 boot mode
and General-Purpose Memory Controller (GPMC)
peripheral functions. At reset, when EMAC bootmode is
selected (see Table 4-1), BTMODE[9:8] pins are sampled
to determine the function of the Ethernet PHY Mode
selection:
•
00 = MII (GMII)
•
01 = RMII
•
10 = RGMII
•
11 = Reserved
For more detailed information on the EMAC PHY boot
modes and the EMAC pin functions selected, see Section
4.2.6, Ethernet PHY Mode Selection. After reset, this pin
functions as GPMC multiplexed data/address pin 8
(GPMC_D[8]).
T1
BTMODE[9]
Boot Mode Selection 9. Ethernet PHY Configuration. This I
pin is multiplexed between ARM Cortex-A8 boot mode
and General-Purpose Memory Controller (GPMC)
peripheral functions. At reset, when EMAC bootmode is
selected (see Table 4-1), BTMODE[9:8] pins are sampled
to determine the function of the Ethernet PHY Mode
selection:
•
00 = MII (GMII)
•
01 = RMII
•
10 = RGMII
•
11 = Reserved
For more detailed information on the EMAC PHY boot
modes and the EMAC pin functions selected, see Section
4.2.6, Ethernet PHY Mode Selection. After reset, this pin
functions as GPMC multiplexed data/address pin 9
(GPMC_D[9]).
T8
BTMODE[10]
Boot Mode Selection 10. XIP (NOR) on GPMC
I
Configuration. This pin is multiplexed between ARM
Cortex-A8 boot mode and General-Purpose Memory
Controller (GPMC) peripheral functions. At reset, when
the XIP (MUX0), XIP (MUX1), XIP w/ WAiT (MUX0) or
XIP w/ WAiT (MUX1) bootmode is selected (see Table 41), BTMODE[10] is sampled to select between GPMC pin
muxing options A or B shown in Table 4-2, XIP (on
GPMC) Boot Options [Muxed or Non-Muxed].
•
0 = GPMC Option A
•
1 = GPMC Option B
After reset, this pin functions as GPMC multiplexed
data/address pin 10 (GPMC_D[10]).
R6
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Table 3-13. Boot Configuration Terminal Functions (continued)
SIGNAL NAME [1]
DESCRIPTION [2]
TYPE [3]
AAR BALL [4]
BTMODE[11]
Boot Mode Selection 11. RSTOUT_WD_OUT
Configuration. This pin is multiplexed between ARM
Cortex-A8 boot mode and General-Purpose Memory
Controller (GPMC) peripheral functions. At reset,
BTMODE[11] is sampled to determine the function of the
RSTOUT_WD_OUT pin:
•
0 = RSTOUT is asserted when a Watchdog Timer
reset, POR, RESET, or Emulation/Software-Global
Cold/Warm reset occurs
•
1 = RSTOUT_WD_OUT is asserted only when a
Watchdog Timer reset occurs
After reset, this pin functions as GPMC multiplexed
data/address pin 11 (GPMC_D[11]).
I
R4
BTMODE[12]
Boot Mode Selection 12. GPMC CS0 default Data Bus
I
Width input. This pin is multiplexed between ARM CortexA8 boot mode and General-Purpose Memory Controller
(GPMC) peripheral functions. At reset, BTMODE[12] is
sampled to determine the GPMC CS0 bus width:
•
0 = 8-bit data bus
•
1 = 16-bit data bus
After reset, this pin functions as GPMC multiplexed
data/address pin 12 (GPMC_D[12]).
R3
BTMODE[13]
Boot Mode Selection 13. GPMC CS0 default
Address/Data multiplexing mode input. This pin is
multiplexed between ARM Cortex-A8 boot mode and
General-Purpose Memory Controller (GPMC) peripheral
functions. At reset, BTMODE[14:13] are sampled to
determine the GPMC CS0 Address/Data multiplexing:
•
00 = Not muxed
•
01 = A/A/D muxed
•
10 = A/D muxed
•
11 = Reserved
After reset, this pin functions as GPMC multiplexed
data/address pin 13 (GPMC_D[13]).
I
R2
BTMODE[14]
Boot Mode Selection 14. GPMC CS0 default
Address/Data multiplexing mode input. This pin is
multiplexed between ARM Cortex-A8 boot mode and
General-Purpose Memory Controller (GPMC) peripheral
functions. At reset, BTMODE[14:13] are sampled to
determine the GPMC CS0 Address/Data multiplexing:
•
00 = Not muxed
•
01 = A/A/D muxed
•
10 = A/D muxed
•
11 = Reserved
After reset, this pin functions as GPMC multiplexed
data/address pin 14 (GPMC_D[14]).
I
R1
BTMODE[15]
Boot Mode Selection 15. GPMC CS0 default GPMC_Wait I
enable input. This pin is multiplexed between ARM
Cortex-A8 boot mode and General-Purpose Memory
Controller (GPMC) peripheral functions. At reset,
BTMODE[15] is sampled to determine the GPMC CS0
Wait enable:
•
0 = Wait disabled
•
1 = Wait enabled
After reset, this pin functions as GPMC multiplexed
data/address pin 15 (GPMC_D[15]).
P2
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3.3.3
SPRS872B – MAY 2013 – REVISED DECEMBER 2013
CSI2 Interface (I/F) Signals
Table 3-14. CSI2 I/F Terminal Functions
SIGNAL NAME [1]
DESCRIPTION [2]
TYPE [3]
AAR BALL [4]
CSI2_DX[0]
CSI2 Camera lane 0 differential pair input. When CSI2 is
not used these pins can be left unconnected.
I
AB2
CSI2_DX[1]
CSI2 Camera lane 1 differential pair input. When CSI2 is
not used these pins can be left unconnected.
I
AA1
CSI2_DX[2]
CSI2 Camera lane 2 differential pair input. When CSI2 is
not used these pins can be left unconnected.
I
AA2
CSI2_DX[3]
CSI2 Camera lane 3 differential pair input. When CSI2 is
not used these pins can be left unconnected.
I
W2
CSI2_DX[4]
CSI2 Camera lane 4 differential pair input. When CSI2 is
not used these pins can be left unconnected.
I
V1
CSI2_DY[0]
CSI2 Camera lane 0 differential pair input. When CSI2 is
not used these pins can be left unconnected.
I
AC2
CSI2_DY[1]
CSI2 Camera lane 1 differential pair input. When CSI2 is
not used these pins can be left unconnected.
I
AB1
CSI2_DY[2]
CSI2 Camera lane 2 differential pair input. When CSI2 is
not used these pins can be left unconnected.
I
Y2
CSI2_DY[3]
CSI2 Camera lane 3 differential pair input. When CSI2 is
not used these pins can be left unconnected.
I
W1
CSI2_DY[4]
CSI2 Camera lane 4 differential pair input. When CSI2 is
not used these pins can be left unconnected.
I
V2
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Camera Interface (I/F)
Table 3-15. Camera I/F Terminal Functions
SIGNAL NAME [1]
DESCRIPTION [2]
TYPE [3]
AAR BALL [4]
CAM_D[0]
Camera data input
I
C2
CAM_D[1]
Camera data input
I
C1
CAM_D[2]
Camera data input
I
B2
CAM_D[3]
Camera data input
I
A2
CAM_D[4]
Camera data input
I
A3
CAM_D[5]
Camera data input
I
B4
CAM_D[6]
Camera data input
I
C5
CAM_D[7]
Camera data input
I
B5
CAM_D[8]
Camera data input
I
K11
CAM_D[9]
Camera data input
I
E12
CAM_D[10]
Camera data input
I
K10
CAM_D[11]
Camera data input
I
D7
CAM_D[12]
Camera data input
I
F9
CAM_D[13]
Camera data input
I
C7
CAM_D[14]
Camera data input
I
A6
CAM_D[15]
Camera data input
I
A5
CAM_FLD
Camera Field Identification input
I/O
J10
CAM_HS
Camera Horizontal Synchronization
I/O
D5
CAM_PCLK
Camera Pixel Clock
I
B3
CAM_RESET
Camera Reset. Used for Strobe Synchronization
I/O
H16
CAM_SHUTTER
Camera Mechanical Shutter Control Signal
O
H13
CAM_STROBE
Camera Flash Strobe Control Signal
O
F13
CAM_VS
Camera Vertical Synchronization
I/O
H9
CAM_WE
Camera Write Enable
I
H17, J10
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3.3.5
SPRS872B – MAY 2013 – REVISED DECEMBER 2013
Controller Area Network (DCAN) Modules (DCAN0, DCAN1)
Table 3-16. DCAN Terminal Functions
SIGNAL NAME [1]
DESCRIPTION [2]
TYPE [3]
AAR BALL [4]
DCAN0_RX
DCAN0 receive data pin
I/O
L22
DCAN0_TX
DCAN0 transmit data pin
I/O
M21
DCAN1_RX
DCAN1 receive data pin
I/O
D31
DCAN1_TX
DCAN1 transmit data pin
I/O
D30
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DDR2/DDR3/DDR3L Memory Controller
Table 3-17. DDR2/DDR3/DDR3L Memory Controller 0 Terminal Functions
SIGNAL NAME [1]
DESCRIPTION [2]
TYPE [3]
AAR BALL [4]
DDR[0]_A[0]
DDR[0] Address Bus
O
AL24
DDR[0]_A[1]
DDR[0] Address Bus
O
AC22
DDR[0]_A[2]
DDR[0] Address Bus
O
AJ23
DDR[0]_A[3]
DDR[0] Address Bus
O
AJ27
DDR[0]_A[4]
DDR[0] Address Bus
O
AK28
DDR[0]_A[5]
DDR[0] Address Bus
O
AH27
DDR[0]_A[6]
DDR[0] Address Bus
O
AK30
DDR[0]_A[7]
DDR[0] Address Bus
O
AG23
DDR[0]_A[8]
DDR[0] Address Bus
O
AL29
DDR[0]_A[9]
DDR[0] Address Bus
O
AK29
DDR[0]_A[10]
DDR[0] Address Bus
O
AD23
DDR[0]_A[11]
DDR[0] Address Bus
O
AK24
DDR[0]_A[12]
DDR[0] Address Bus
O
AH23
DDR[0]_A[13]
DDR[0] Address Bus
O
AK23
DDR[0]_A[14]
DDR[0] Address Bus
O
AL23
DDR[0]_A[15]
DDR[0] Address Bus
O
AK22
DDR[0]_BA[0]
DDR[0] Bank Address outputs
O
AK26
DDR[0]_BA[1]
DDR[0] Bank Address outputs
O
AF23
DDR[0]_BA[2]
DDR[0] Bank Address outputs
O
AH25
DDR[0]_CAS
DDR[0] Column Address Strobe output
O
AK25
DDR[0]_CKE
DDR[0] Clock Enable
O
AD20
DDR[0]_CLK
DDR[0] Negative Clock
O
AK27
DDR[0]_CLK
DDR[0] Clock
O
AL27
DDR[0]_CS[0]
DDR[0] Chip Select
O
AB21
DDR[0]_D[0]
DDR[0] Data Bus
I/O
AL9
DDR[0]_D[1]
DDR[0] Data Bus
I/O
AK9
DDR[0]_D[2]
DDR[0] Data Bus
I/O
AK10
DDR[0]_D[3]
DDR[0] Data Bus
I/O
AJ11
DDR[0]_D[4]
DDR[0] Data Bus
I/O
AH11
DDR[0]_D[5]
DDR[0] Data Bus
I/O
AD9
DDR[0]_D[6]
DDR[0] Data Bus
I/O
AF11
DDR[0]_D[7]
DDR[0] Data Bus
I/O
AL12
DDR[0]_D[8]
DDR[0] Data Bus
I/O
AJ12
DDR[0]_D[9]
DDR[0] Data Bus
I/O
AG12
DDR[0]_D[10]
DDR[0] Data Bus
I/O
AD12
DDR[0]_D[11]
DDR[0] Data Bus
I/O
AB12
DDR[0]_D[12]
DDR[0] Data Bus
I/O
AK13
DDR[0]_D[13]
DDR[0] Data Bus
I/O
AC13
DDR[0]_D[14]
DDR[0] Data Bus
I/O
AL14
DDR[0]_D[15]
DDR[0] Data Bus
I/O
AK14
DDR[0]_D[16]
DDR[0] Data Bus
I/O
AH15
DDR[0]_D[17]
DDR[0] Data Bus
I/O
AF15
DDR[0]_D[18]
DDR[0] Data Bus
I/O
AD15
DDR[0]_D[19]
DDR[0] Data Bus
I/O
AK16
DDR[0]_D[20]
DDR[0] Data Bus
I/O
AJ16
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Table 3-17. DDR2/DDR3/DDR3L Memory Controller 0 Terminal Functions (continued)
SIGNAL NAME [1]
DESCRIPTION [2]
TYPE [3]
AAR BALL [4]
DDR[0]_D[21]
DDR[0] Data Bus
I/O
AG16
DDR[0]_D[22]
DDR[0] Data Bus
I/O
AD16
DDR[0]_D[23]
DDR[0] Data Bus
I/O
AC16
DDR[0]_D[24]
DDR[0] Data Bus
I/O
AK19
DDR[0]_D[25]
DDR[0] Data Bus
I/O
AJ19
DDR[0]_D[26]
DDR[0] Data Bus
I/O
AH19
DDR[0]_D[27]
DDR[0] Data Bus
I/O
AF19
DDR[0]_D[28]
DDR[0] Data Bus
I/O
AD19
DDR[0]_D[29]
DDR[0] Data Bus
I/O
AC19
DDR[0]_D[30]
DDR[0] Data Bus
I/O
AJ20
DDR[0]_D[31]
DDR[0] Data Bus
I/O
AG20
DDR[0]_DQM[0]
Data Mask for lower byte data bus DDR[0]_D[7:0]
O
AL8
DDR[0]_DQM[1]
Data Mask for DDR[0]_D[15:8]
O
AK12
DDR[0]_DQM[2]
Data Mask for DDR[0]_D[23:16]
O
AJ15
DDR[0]_DQM[3]
Data Mask for upper byte data bus DDR[0]_D[31:24]
O
AK18
DDR[0]_DQS[0]
Data Strobe for lower byte data bus DDR[0]_D[7:0]
I/O
AL11
DDR[0]_DQS[0]
Complimentary data strobe for lower byte data bus
DDR[0]_D[7:0]
I/O
AK11
DDR[0]_DQS[1]
Complimentary data strobe for DDR[0]_D[15:8]
I/O
AK15
DDR[0]_DQS[1]
Data Strobe for DDR[0]_D[15:8]
I/O
AL15
DDR[0]_DQS[2]
Data Strobe for DDR[0]_D[23:16]
I/O
AL17
DDR[0]_DQS[2]
Complimentary data strobe for DDR[0]_D[23:16]
I/O
AK17
DDR[0]_DQS[3]
Complimentary data strobe for upper byte data bus
DDR[0]_D[31:24]
I/O
AK20
DDR[0]_DQS[3]
Data Strobe for upper byte data bus DDR[0]_D[31:24]
I/O
AL20
DDR[0]_ODT[0]
DDR[0] On-Die Termination for Chip Select 0
O
AL21
DDR[0]_RAS
DDR[0] Row Address Strobe output
O
AJ25
DDR[0]_RST
DDR[0] Reset output
O
AA20
DDR[0]_VTP
DDR VTP Compensation Resistor Connection
I
AL30
DDR[0]_WE
DDR[0] Write Enable
O
AL26
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EDMA
Table 3-18. EDMA Terminal Functions
SIGNAL NAME [1]
DESCRIPTION [2]
TYPE [3]
AAR BALL [4]
EDMA_EVT0
External EDMA Event 0
I
AD2, W8
EDMA_EVT1
External EDMA Event 1
I
G28, Y11
EDMA_EVT2
External EDMA Event 2
I
AG30, Y3
EDMA_EVT3
External EDMA Event 3
I
AB9, AF27
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3.3.8
3.3.8.1
SPRS872B – MAY 2013 – REVISED DECEMBER 2013
EMAC [(R)(G)MII Modes] and MDIO
EMAC
Table 3-19. EMAC Terminal Functions [(R)(G)MII]
SIGNAL NAME [1]
DESCRIPTION [2]
TYPE [3]
AAR BALL [4]
EMAC[0]_GMTCLK/EMAC[1]_RGRXC
GMII Source Asynchronous Transmit Clock / RGMII
Receive Clock
I/O
AL6
EMAC[0]_MCOL/EMAC[0]_RGRXCTL
[G]MII Collision Detect (Sense) input / RGMII Receive
Control
I
AH1
EMAC[0]_MCRS/EMAC[0]_RGRXD[2]
[G]MII Carrier Sense input / RGMII Receive Data
I
AH2
EMAC[0]_MRCLK/EMAC[0]_RGTXC
[G]MII Receive Clock / RGMII Transmit Clock
I/O
AK1
EMAC[0]_MRXDV/EMAC[1]_RGRXD[1]
[G]MII Receive Data Valid input / RGMII Receive Data
I/O
AJ6
EMAC[0]_MRXD[0]/EMAC[0]_RGTXD[0]
[G]MII Receive Data / RGMII Transmit Data
I/O
AK2
EMAC[0]_MRXD[1]/EMAC[0]_RGRXD[0]
[G]MII Receive Data / RGMII Receive Data
I/O
AL2
EMAC[0]_MRXD[2]/EMAC[0]_RGRXD[1]
[G]MII Receive Data / RGMII Receive Data
I/O
AL3
EMAC[0]_MRXD[3]/EMAC[1]_RGRXCTL
[G]MII Receive Data / RGMII Receive Control
I/O
AK3
EMAC[0]_MRXD[4]/EMAC[0]_RGRXD[3]
[G]MII Receive Data / RGMII Receive Data
I/O
AK4
EMAC[0]_MRXD[5]/EMAC[0]_RGTXD[3]
[G]MII Receive Data / RGMII Transmit Data
I/O
AJ4
EMAC[0]_MRXD[6]/EMAC[0]_RGTXD[2]
[G]MII Receive Data / RGMII Transmit Data
I/O
AL5
EMAC[0]_MRXD[7]/EMAC[0]_RGTXD[1]
[G]MII Receive Data / RGMII Transmit Data
I/O
AK5
EMAC[0]_MRXER/EMAC[0]_RGTXCTL
[G]MII Receive Data Error input / RGMII Transmit Enable
I/O
AJ2
EMAC[0]_MTCLK/EMAC[0]_RGRXC
[G]MII Transmit Clock input / RGMII Receive Clock
I/O
AG4
EMAC[0]_MTXD[0]/EMAC[1]_RGRXD[3]
[G]MII Transmit Data / RGMII Receive Data
I/O
AK6
EMAC[0]_MTXD[1]/EMAC[1]_RGTXD[1]
[G]MII Transmit Data / RGMII Transmit Data
I/O
AJ7
EMAC[0]_MTXD[2]/EMAC[1]_RGTXCTL
[G]MII Transmit Data / RGMII Trasmit Enable
I/O
AK7
EMAC[0]_MTXD[3]/EMAC[1]_RGTXD[0]
[G]MII Transmit Data / RGMII Transmit Data
I/O
AE4
EMAC[0]_MTXD[4]/EMAC[1]_RGTXD[2]
[G]MII Transmit Data / RGMII Transmit Data
I/O
AK8
EMAC[0]_MTXD[5]/EMAC[1]_RGTXC
[G]MII Transmit Data / RGMII Transmit Clock
I/O
AJ8
EMAC[0]_MTXD[6]/EMAC[1]_RGRXD[0]
[G]MII Transmit Data / RGMII Receive Data
I/O
AH8
EMAC[0]_MTXD[7]/EMAC[1]_RGTXD[3]
[G]MII Transmit Data / RGMII Transmit Data
I/O
AG8
EMAC[0]_MTXEN/EMAC[1]_RGRXD[2]
[G]MII Transmit Data Enable output / RGMII Receive
Data
I/O
AF8
EMAC[0]_RMCRSDV
RMII Carrier Sense input
I
AK1
EMAC[0]_RMRXD[0]
RMII Receive Data
I
AH1
EMAC[0]_RMRXD[1]
RMII Receive Data
I
AH2
EMAC[0]_RMRXER
RMII Receive Data Error input
I
AJ2
EMAC[0]_RMTXD[0]
RMII Transmit Data
O
AK2
EMAC[0]_RMTXD[1]
RMII Transmit Data
O
AL2
EMAC[0]_RMTXEN
RMII Transmit Data Enable output
O
AL3
EMAC[1]_GMTCLK
GMII Source Asynchronous Transmit Clock
O
H4
EMAC[1]_MCOL
[G]MII Collision Detect (Sense) input
I
E2
EMAC[1]_MCRS
[G]MII Carrier Sense input
I
F5
EMAC[1]_MRCLK
[G]MII Receive Clock
I
F2
EMAC[1]_MRXD[0]
[G]MII Receive Data
I
F3
EMAC[1]_MRXD[1]
[G]MII Receive Data
I
G1
EMAC[1]_MRXD[2]
[G]MII Receive Data
I
G2
EMAC[1]_MRXD[3]
[G]MII Receive Data
I
H3
EMAC[1]_MRXD[4]
[G]MII Receive Data
I
G3
EMAC[1]_MRXD[5]
[G]MII Receive Data
I
H5
EMAC[1]_MRXD[6]
[G]MII Receive Data
I
H6
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Table 3-19. EMAC Terminal Functions [(R)(G)MII] (continued)
SIGNAL NAME [1]
DESCRIPTION [2]
TYPE [3]
AAR BALL [4]
EMAC[1]_MRXD[7]
[G]MII Receive Data
I
J8
EMAC[1]_MRXDV
[G]MII Receive Data Valid input
I
J1
EMAC[1]_MRXER
[G]MII Receive Data Error input
I
F1
EMAC[1]_MTCLK
[G]MII Transmit Clock input
I
D3
EMAC[1]_MTXD[0]
[G]MII Transmit Data
O
J9
EMAC[1]_MTXD[1]
[G]MII Transmit Data
O
L3
EMAC[1]_MTXD[2]
[G]MII Transmit Data
O
K1
EMAC[1]_MTXD[3]
[G]MII Transmit Data
O
H2
EMAC[1]_MTXD[4]
[G]MII Transmit Data
O
M11
EMAC[1]_MTXD[5]
[G]MII Transmit Data
O
L12
EMAC[1]_MTXD[6]
[G]MII Transmit Data
O
M10
EMAC[1]_MTXD[7]
[G]MII Transmit Data
O
J2
EMAC[1]_MTXEN
[G]MII Transmit Data Enable output
O
K2
EMAC[1]_RMCRSDV
RMII Carrier Sense input
I
AJ8, F9
EMAC[1]_RMRXD[0]
RMII Receive Data
I
AK7, D7
EMAC[1]_RMRXD[1]
RMII Receive Data
I
AE4, K10
EMAC[1]_RMRXER
RMII Receive Data Error input
I
AK8, E12
EMAC[1]_RMTXD[0]
RMII Transmit Data
O
AH8, C7
EMAC[1]_RMTXD[1]
RMII Transmit Data
O
A6, AG8
EMAC[1]_RMTXEN
RMII Transmit Data Enable output
O
A5, AF8
EMAC_RMREFCLK
RMII Reference Clock
I/O
AG1
3.3.8.2
MDIO
Table 3-20. MDIO Terminal Functions
SIGNAL NAME [1]
DESCRIPTION [2]
TYPE [3]
AAR BALL [4]
MDCLK
Management Data Serial Clock output
O
AG2
MDIO
Management Data I/O
I/O
AG3
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3.3.9
SPRS872B – MAY 2013 – REVISED DECEMBER 2013
GPMC
Table 3-21. GPMC Terminal Functions
SIGNAL NAME [1]
DESCRIPTION [2]
TYPE [3]
AAR BALL [4]
GPMC_A[0]
GPMC Address 0
O
AK3, M8
GPMC_A[1]
GPMC Address 1
O
AD1, AK4
GPMC_A[2]
GPMC Address 2
O
AC8, AJ4
GPMC_A[3]
GPMC Address 3
O
AC5, AL5
GPMC_A[4]
GPMC Address 4
O
AC4, AK5
GPMC_A[5]
GPMC Address 5
O
A2, AJ6
GPMC_A[6]
GPMC Address 6
O
AL6, B2
GPMC_A[7]
GPMC Address 7
O
AK6, C1
GPMC_A[8]
GPMC Address 8
O
AJ7, C2
GPMC_A[9]
GPMC Address 9
O
AK7, D5
GPMC_A[10]
GPMC Address 10
O
AE4, H9
GPMC_A[11]
GPMC Address 11
O
AK8, J10
GPMC_A[12]
GPMC Address 12
O
AJ8, B3
GPMC_A[13]
GPMC Address 13
O
AH8, L2
GPMC_A[14]
GPMC Address 14
O
AG8, L4
GPMC_A[15]
GPMC Address 15
O
AF8, L6
GPMC_A[16]
GPMC Address 16
O
M1
GPMC_A[17]
GPMC Address 17
O
M2
GPMC_A[18]
GPMC Address 18
O
M3
GPMC_A[19]
GPMC Address 19
O
M5
GPMC_A[20]
GPMC Address 20
O
AE3, N9
GPMC_A[21]
GPMC Address 21
O
AE2, N1
GPMC_A[22]
GPMC Address 22
O
AE1, N2
GPMC_A[23]
GPMC Address 23
O
AD2, R8
GPMC_A[24]
GPMC Address 24
O
AC3, AE3, Y11
GPMC_A[25]
GPMC Address 25
O
AA12, AE2, Y3
GPMC_A[26]
GPMC Address 26
O
AE1, AK3, W8
GPMC_A[27]
GPMC Address 27
O
AD2, AK3
GPMC_ADV_ALE
GPMC Address Valid output or Address Latch Enable
output
O
AA10
GPMC_BE[1]
GPMC Upper Byte Enable output
O
Y11
GPMC_BE[0]_CLE
GPMC Lower Byte Enable output or Command Latch
Enable output
O
Y3
GPMC_CLK
GPMC Clock output
O
AB9
GPMC_CS[0]
GPMC Chip Select 0
O
AC9
GPMC_CS[1]
GPMC Chip Select 1
O
AA12
GPMC_CS[2]
GPMC Chip Select 2
O
AC3
GPMC_CS[3]
GPMC Chip Select 3
O
AF2
GPMC_CS[4]
GPMC Chip Select 4
O
AG6
GPMC_CS[5]
GPMC Chip Select 5
O
AB9
GPMC_CS[6]
GPMC Chip Select 6
O
AA10
GPMC_CS[7]
GPMC Chip Select 7
O
AD2
GPMC_D[0]
GPMC Multiplexed Data/Address I/O
I/O
W6
GPMC_D[1]
GPMC Multiplexed Data/Address I/O
I/O
W4
GPMC_D[2]
GPMC Multiplexed Data/Address I/O
I/O
W3
GPMC_D[3]
GPMC Multiplexed Data/Address I/O
I/O
U2
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Table 3-21. GPMC Terminal Functions (continued)
SIGNAL NAME [1]
DESCRIPTION [2]
TYPE [3]
AAR BALL [4]
GPMC_D[4]
GPMC Multiplexed Data/Address I/O
I/O
W9
GPMC_D[5]
GPMC Multiplexed Data/Address I/O
I/O
T5
GPMC_D[6]
GPMC Multiplexed Data/Address I/O
I/O
T3
GPMC_D[7]
GPMC Multiplexed Data/Address I/O
I/O
T2
GPMC_D[8]
GPMC Multiplexed Data/Address I/O
I/O
T1
GPMC_D[9]
GPMC Multiplexed Data/Address I/O
I/O
T8
GPMC_D[10]
GPMC Multiplexed Data/Address I/O
I/O
R6
GPMC_D[11]
GPMC Multiplexed Data/Address I/O
I/O
R4
GPMC_D[12]
GPMC Multiplexed Data/Address I/O
I/O
R3
GPMC_D[13]
GPMC Multiplexed Data/Address I/O
I/O
R2
GPMC_D[14]
GPMC Multiplexed Data/Address I/O
I/O
R1
GPMC_D[15]
GPMC Multiplexed Data/Address I/O
I/O
P2
GPMC_OE_RE
GPMC Output Enable output
O
Y8
GPMC_WAIT[0]
GPMC Wait input 0
I
W8
GPMC_WAIT[1]
GPMC Wait input 1
I
AB9
GPMC_WE
GPMC Write Enable output
O
Y5
76
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3.3.10 General-Purpose Input/Outputs (GPIOs)
3.3.10.1 GP0
Table 3-22. GP0 Terminal Functions
SIGNAL NAME [1]
DESCRIPTION [2]
TYPE [3]
AAR BALL [4]
GP0[0]
Interrupt-Capable General-Purpose Input/Output (I/O)
I/O
Y29
GP0[1]
Interrupt-Capable General-Purpose Input/Output (I/O)
I/O
AB30
GP0[2]
Interrupt-Capable General-Purpose Input/Output (I/O)
I/O
AA29
GP0[3]
Interrupt-Capable General-Purpose Input/Output (I/O)
I/O
AA28
GP0[4]
Interrupt-Capable General-Purpose Input/Output (I/O)
I/O
AA26
GP0[5]
Interrupt-Capable General-Purpose Input/Output (I/O)
I/O
Y31
GP0[6]
Interrupt-Capable General-Purpose Input/Output (I/O)
I/O
Y30
GP0[7]
Interrupt-Capable General-Purpose Input/Output (I/O)
I/O
K23
GP0[8]
Interrupt-Capable General-Purpose Input/Output (I/O)
I/O
AF27
GP0[9]
Interrupt-Capable General-Purpose Input/Output (I/O)
I/O
AG30
GP0[10]
Interrupt-Capable General-Purpose Input/Output (I/O)
I/O
K11
GP0[11]
Interrupt-Capable General-Purpose Input/Output (I/O)
I/O
E12
GP0[12]
Interrupt-Capable General-Purpose Input/Output (I/O)
I/O
AB31, K10
GP0[13]
Interrupt-Capable General-Purpose Input/Output (I/O)
I/O
AC30, D7
GP0[14]
Interrupt-Capable General-Purpose Input/Output (I/O)
I/O
F9
GP0[15]
Interrupt-Capable General-Purpose Input/Output (I/O)
I/O
C7
GP0[16]
Interrupt-Capable General-Purpose Input/Output (I/O)
I/O
A6
GP0[17]
Interrupt-Capable General-Purpose Input/Output (I/O)
I/O
A5
GP0[18]
Interrupt-Capable General-Purpose Input/Output (I/O)
I/O
B5
GP0[19]
Interrupt-Capable General-Purpose Input/Output (I/O)
I/O
C5
GP0[20]
Interrupt-Capable General-Purpose Input/Output (I/O)
I/O
B4
GP0[21]
Interrupt-Capable General-Purpose Input/Output (I/O)
I/O
A3
GP0[22]
Interrupt-Capable General-Purpose Input/Output (I/O)
I/O
A2
GP0[23]
Interrupt-Capable General-Purpose Input/Output (I/O)
I/O
B2
GP0[24]
Interrupt-Capable General-Purpose Input/Output (I/O)
I/O
C1
GP0[25]
Interrupt-Capable General-Purpose Input/Output (I/O)
I/O
C2
GP0[26]
Interrupt-Capable General-Purpose Input/Output (I/O)
I/O
D5
GP0[27]
Interrupt-Capable General-Purpose Input/Output (I/O)
I/O
H9
GP0[28]
Interrupt-Capable General-Purpose Input/Output (I/O)
I/O
J10
3.3.10.2 GP1
Table 3-23. GP1 Terminal Functions
SIGNAL NAME [1]
DESCRIPTION [2]
TYPE [3]
AAR BALL [4]
GP1[0]
Interrupt-Capable General-Purpose Input/Output (I/O)
I/O
M21
GP1[1]
Interrupt-Capable General-Purpose Input/Output (I/O)
I/O
L22
GP1[2]
Interrupt-Capable General-Purpose Input/Output (I/O)
I/O
E31
GP1[3]
Interrupt-Capable General-Purpose Input/Output (I/O)
I/O
E29
GP1[4]
Interrupt-Capable General-Purpose Input/Output (I/O)
I/O
E30
GP1[5]
Interrupt-Capable General-Purpose Input/Output (I/O)
I/O
N26
GP1[6]
Interrupt-Capable General-Purpose Input/Output (I/O)
I/O
G28
GP1[7]
Interrupt-Capable General-Purpose Input/Output (I/O)
I/O
U28
GP1[8]
Interrupt-Capable General-Purpose Input/Output (I/O)
I/O
AG6
GP1[9]
Interrupt-Capable General-Purpose Input/Output (I/O)
I/O
H12
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Table 3-23. GP1 Terminal Functions (continued)
SIGNAL NAME [1]
DESCRIPTION [2]
TYPE [3]
AAR BALL [4]
GP1[10]
Interrupt-Capable General-Purpose Input/Output (I/O)
I/O
AG1
GP1[11]
Interrupt-Capable General-Purpose Input/Output (I/O)
I/O
AG2, B18
GP1[12]
Interrupt-Capable General-Purpose Input/Output (I/O)
I/O
A17, AG3
GP1[13]
Interrupt-Capable General-Purpose Input/Output (I/O)
I/O
AC5, M3
GP1[14]
Interrupt-Capable General-Purpose Input/Output (I/O)
I/O
AC4, M5
GP1[15]
Interrupt-Capable General-Purpose Input/Output (I/O)
I/O
AC6, N9
GP1[16]
Interrupt-Capable General-Purpose Input/Output (I/O)
I/O
J29, N1
GP1[17]
Interrupt-Capable General-Purpose Input/Output (I/O)
I/O
M29, N2
GP1[18]
Interrupt-Capable General-Purpose Input/Output (I/O)
I/O
M27, R8
GP1[19]
Interrupt-Capable General-Purpose Input/Output (I/O)
I/O
AE3
GP1[20]
Interrupt-Capable General-Purpose Input/Output (I/O)
I/O
AE2
GP1[21]
Interrupt-Capable General-Purpose Input/Output (I/O)
I/O
AE1
GP1[22]
Interrupt-Capable General-Purpose Input/Output (I/O)
I/O
AD2
GP1[23]
Interrupt-Capable General-Purpose Input/Output (I/O)
I/O
AC9
GP1[24]
Interrupt-Capable General-Purpose Input/Output (I/O)
I/O
AA12
GP1[25]
Interrupt-Capable General-Purpose Input/Output (I/O)
I/O
AC3
GP1[26]
Interrupt-Capable General-Purpose Input/Output (I/O)
I/O
AF2, N23
GP1[27]
Interrupt-Capable General-Purpose Input/Output (I/O)
I/O
AB9
GP1[28]
Interrupt-Capable General-Purpose Input/Output (I/O)
I/O
AA10
GP1[29]
Interrupt-Capable General-Purpose Input/Output (I/O)
I/O
Y3
GP1[30]
Interrupt-Capable General-Purpose Input/Output (I/O)
I/O
Y11
GP1[31]
Interrupt-Capable General-Purpose Input/Output (I/O)
I/O
W8
3.3.10.3 GP2
Table 3-24. GP2 Terminal Functions
SIGNAL NAME [1]
DESCRIPTION [2]
TYPE [3]
AAR BALL [4]
GP2[0]
Interrupt-Capable General-Purpose Input/Output (I/O)
I/O
C12
GP2[1]
Interrupt-Capable General-Purpose Input/Output (I/O)
I/O
J13
GP2[2]
Interrupt-Capable General-Purpose Input/Output (I/O)
I/O
C9
GP2[02]
Interrupt-Capable General-Purpose Input/Output (I/O)
I/O
B3
GP2[3]
Interrupt-Capable General-Purpose Input/Output (I/O)
I/O
D13
GP2[4]
Interrupt-Capable General-Purpose Input/Output (I/O)
I/O
C13
GP2[5]
Interrupt-Capable General-Purpose Input/Output (I/O)
I/O
AD1, M1
GP2[6]
Interrupt-Capable General-Purpose Input/Output (I/O)
I/O
AC8, M2
GP2[7]
Interrupt-Capable General-Purpose Input/Output (I/O)
I/O
B17
GP2[8]
Interrupt-Capable General-Purpose Input/Output (I/O)
I/O
C17
GP2[9]
Interrupt-Capable General-Purpose Input/Output (I/O)
I/O
D17
GP2[10]
Interrupt-Capable General-Purpose Input/Output (I/O)
I/O
F17
GP2[11]
Interrupt-Capable General-Purpose Input/Output (I/O)
I/O
L20
GP2[12]
Interrupt-Capable General-Purpose Input/Output (I/O)
I/O
H20
GP2[13]
Interrupt-Capable General-Purpose Input/Output (I/O)
I/O
B16
GP2[14]
Interrupt-Capable General-Purpose Input/Output (I/O)
I/O
C16
GP2[15]
Interrupt-Capable General-Purpose Input/Output (I/O)
I/O
E16
GP2[16]
Interrupt-Capable General-Purpose Input/Output (I/O)
I/O
H17
GP2[17]
Interrupt-Capable General-Purpose Input/Output (I/O)
I/O
J16
GP2[18]
Interrupt-Capable General-Purpose Input/Output (I/O)
I/O
H16
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Table 3-24. GP2 Terminal Functions (continued)
SIGNAL NAME [1]
DESCRIPTION [2]
TYPE [3]
AAR BALL [4]
GP2[19]
Interrupt-Capable General-Purpose Input/Output (I/O)
I/O
F13
GP2[20]
Interrupt-Capable General-Purpose Input/Output (I/O)
I/O
H13
GP2[21]
Interrupt-Capable General-Purpose Input/Output (I/O)
I/O
C20
GP2[22]
Interrupt-Capable General-Purpose Input/Output (I/O)
I/O
F24
GP2[23]
Interrupt-Capable General-Purpose Input/Output (I/O)
I/O
D21
GP2[24]
Interrupt-Capable General-Purpose Input/Output (I/O)
I/O
C25
GP2[25]
Interrupt-Capable General-Purpose Input/Output (I/O)
I/O
C26
GP2[26]
Interrupt-Capable General-Purpose Input/Output (I/O)
I/O
C28
GP2[27]
Interrupt-Capable General-Purpose Input/Output (I/O)
I/O
B28
GP2[28]
Interrupt-Capable General-Purpose Input/Output (I/O)
I/O
D3
GP2[29]
Interrupt-Capable General-Purpose Input/Output (I/O)
I/O
E2
GP2[30]
Interrupt-Capable General-Purpose Input/Output (I/O)
I/O
F5
GP2[31]
Interrupt-Capable General-Purpose Input/Output (I/O)
I/O
F1
3.3.10.4 GP3
Table 3-25. GP3 Terminal Functions
SIGNAL NAME [1]
DESCRIPTION [2]
TYPE [3]
AAR BALL [4]
GP3[0]
Interrupt-Capable General-Purpose Input/Output (I/O)
I/O
F2
GP3[1]
Interrupt-Capable General-Purpose Input/Output (I/O)
I/O
F3
GP3[2]
Interrupt-Capable General-Purpose Input/Output (I/O)
I/O
G1
GP3[3]
Interrupt-Capable General-Purpose Input/Output (I/O)
I/O
G2
GP3[4]
Interrupt-Capable General-Purpose Input/Output (I/O)
I/O
H3
GP3[5]
Interrupt-Capable General-Purpose Input/Output (I/O)
I/O
G3
GP3[6]
Interrupt-Capable General-Purpose Input/Output (I/O)
I/O
H5
GP3[7]
Interrupt-Capable General-Purpose Input/Output (I/O)
I/O
H6
GP3[8]
Interrupt-Capable General-Purpose Input/Output (I/O)
I/O
J8
GP3[9]
Interrupt-Capable General-Purpose Input/Output (I/O)
I/O
J1
GP3[10]
Interrupt-Capable General-Purpose Input/Output (I/O)
I/O
H4
GP3[11]
Interrupt-Capable General-Purpose Input/Output (I/O)
I/O
J9
GP3[12]
Interrupt-Capable General-Purpose Input/Output (I/O)
I/O
L3
GP3[13]
Interrupt-Capable General-Purpose Input/Output (I/O)
I/O
K1
GP3[14]
Interrupt-Capable General-Purpose Input/Output (I/O)
I/O
H2
GP3[15]
Interrupt-Capable General-Purpose Input/Output (I/O)
I/O
M11
GP3[16]
Interrupt-Capable General-Purpose Input/Output (I/O)
I/O
L12
GP3[17]
Interrupt-Capable General-Purpose Input/Output (I/O)
I/O
M10
GP3[18]
Interrupt-Capable General-Purpose Input/Output (I/O)
I/O
J2
GP3[19]
Interrupt-Capable General-Purpose Input/Output (I/O)
I/O
K2
GP3[20]
Interrupt-Capable General-Purpose Input/Output (I/O)
I/O
L2
GP3[21]
Interrupt-Capable General-Purpose Input/Output (I/O)
I/O
L4
GP3[22]
Interrupt-Capable General-Purpose Input/Output (I/O)
I/O
L6
GP3[23]
Interrupt-Capable General-Purpose Input/Output (I/O)
I/O
AG4
GP3[24]
Interrupt-Capable General-Purpose Input/Output (I/O)
I/O
AH1
GP3[25]
Interrupt-Capable General-Purpose Input/Output (I/O)
I/O
AH2
GP3[26]
Interrupt-Capable General-Purpose Input/Output (I/O)
I/O
AJ2
GP3[27]
Interrupt-Capable General-Purpose Input/Output (I/O)
I/O
AK1
GP3[28]
Interrupt-Capable General-Purpose Input/Output (I/O)
I/O
AK2
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Table 3-25. GP3 Terminal Functions (continued)
SIGNAL NAME [1]
DESCRIPTION [2]
TYPE [3]
AAR BALL [4]
GP3[29]
Interrupt-Capable General-Purpose Input/Output (I/O)
I/O
AL2
GP3[30]
Interrupt-Capable General-Purpose Input/Output (I/O)
I/O
AL3, M8
GP3[31]
Interrupt-Capable General-Purpose Input/Output (I/O)
I/O
AJ31
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3.3.11 Ground Pins (VSS)
Table 3-26. Ground Terminal Functions
SIGNAL NAME [1]
DESCRIPTION [2]
TYPE [3]
GND
AAR BALL [4]
VSS
Ground (GND)
VSSA_AUXOSC
Supply Ground for Auxiliary Oscillator. If internal oscillator GND
is bypassed, this pin should be connected to ground.
U30
VSSA_CSI2
Analog GND for CSI2. Connect to ground even if the
CSI2 is not being used.
AC7, V14
VSSA_DEVOSC
Supply Ground for DEV Oscillator. If the internal oscillator GND
is bypassed, this pin should be connected to ground.
G30
VSSA_HDMI
Analog GND for HDMI. For proper device operation, this
pin must always be connected to ground, even if HDMI is
not being used.
GND
G9, H8
VSSA_USB
Analog GND for USB0 and USB1. For proper device
operation, this pin must always be connected to ground,
even if USB is not being used.
GND
D20, N19, N20
VSSA_VDAC
Analog GND for VDAC. For proper device operation, this GND
pin must always be connected to ground, even if VDAC is
not being used.
GND
A1, A31, AA13, AA14,
AA15, AA16, AA17,
AA18, AA27, AC25,
AD24, AD25, AD3,
AD4, AD5, AD6, AD7,
AE12, AE19, AE20,
AE23, AE24, AE25,
AE26, AE27, AE28,
AE5, AE6, AE7, AE8,
AE9, AF12, AF20,
AF24, AF25, AF7,
AG11, AG19, AG24,
AG25, AG7, AH12,
AH20, AH7, AL1,
AL31, D25, D8, E21,
E25, E7, E8, F20,
F25, F7, F8, G20,
G23, G24, G25, G26,
G27, G4, G5, G6, G7,
G8, H26, H7, J7, L16,
M16, N13, N14, N16,
N17, P11, P12, P14,
P18, R11, R12, R14,
R18, R20, R21, T11,
T12, T14, T15, T16,
T19, T20, T21, U14,
U18, U23, V18, W16,
W17, Y16, Y17, Y25,
Y26, Y28
C8
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3.3.12 HDMI
Table 3-27. HDMI Terminal Functions
SIGNAL NAME [1]
DESCRIPTION [2]
TYPE [3]
AAR BALL [4]
HDMI_CEC
HDMI Consumer Electronics Control I/O
I/O
M8, N2
HDMI_CLKN
HDMI Clock Output. When the HDMI PHY is powered
down, this pin should be left unconnected.
O
B15
HDMI_CLKP
HDMI Clock Output. When the HDMI PHY is powered
down, this pin should be left unconnected.
O
A15
HDMI_DN0
HDMI Data 0 output. When the HDMI PHY is powered
down, this pin should be left unconnected.
O
A14
HDMI_DN1
HDMI Data 1 output. When the HDMI PHY is powered
down, this pin should be left unconnected.
O
B13
HDMI_DN2
HDMI Data 2 output. When the HDMI PHY is powered
down, this pin should be left unconnected.
O
A12
HDMI_DP0
HDMI Data 0 output. When the HDMI PHY is powered
down, this pin should be left unconnected.
O
B14
HDMI_DP1
HDMI Data 1 output. When the HDMI PHY is powered
down, this pin should be left unconnected.
O
B12
HDMI_DP2
HDMI Data 2 output. When the HDMI PHY is powered
down, this pin should be left unconnected.
O
A11
HDMI_HPDET
HDMI Hot Plug Detect Input
I
L6, R8
HDMI_SCL
HDMI I2C Serial Clock Output
I/O
D2, L2
HDMI_SDA
HDMI I2C Serial Data I/O
I/O
D1, L4
82
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3.3.13 I2C
Table 3-28. I2C Terminal Functions
SIGNAL NAME [1]
DESCRIPTION [2]
TYPE [3]
AAR BALL [4]
I2C[0]_SCL
I2C[0] Clock I/O. For proper device operation, this pin
must be pulled up via external resistor.
I/O
T27
I2C[0]_SDA
I2C[0] Data I/O. For proper device operation, this pin
must be pulled up via external resistor.
I/O
T24
I2C[1]_SCL
I2C[1] Clock I/O. For proper device operation in I2C
mode, this pin must be pulled up via external resistor.
I/O
D2
I2C[1]_SDA
I2C[1] Data I/O. For proper device operation in I2C mode, I/O
this pin must be pulled up via external resistor.
D1
I2C[2]_SCL
I2C[2] Clock I/O. For proper device operation in I2C
mode, this pin must be pulled up via external resistor.
E31, J13, K11, L2
I2C[2]_SDA
I2C[2] Data I/O. For proper device operation in I2C mode, I/O
this pin must be pulled up via external resistor.
AG4, C12, E29, L4
I2C[3]_SCL
I2C[3] Clock I/O. For proper device operation in I2C
mode, this pin must be pulled up via external resistor.
I/O
AE31, G3, K10, L22
I2C[3]_SDA
I2C[3] Data I/O. For proper device operation in I2C mode, I/O
this pin must be pulled up via external resistor.
AE30, D7, H5, M21
I/O
Device Pins
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3.3.14 McASP
3.3.14.1 McASP0
Table 3-29. McASP0 Terminal Functions
SIGNAL NAME [1]
DESCRIPTION [2]
TYPE [3]
AAR BALL [4]
MCA[0]_ACLKR
McASP0 Receive Bit Clock I/O
I/O
AD30
MCA[0]_ACLKX
McASP0 Transmit Bit Clock I/O
I/O
AD28
MCA[0]_AFSR
McASP0 Receive Frame Sync I/O
I/O
AF30
MCA[0]_AFSX
McASP0 Transmit Frame Sync I/O
I/O
AE29
MCA[0]_AHCLKX
McASP0 Transmit High-Frequency Master Clock I/O
I/O
AF31
MCA[0]_AXR[0]
McASP0 Transmit/Receive Data I/O
I/O
AF29
MCA[0]_AXR[1]
McASP0 Transmit/Receive Data I/O
I/O
AE31
MCA[0]_AXR[2]
McASP0 Transmit/Receive Data I/O
I/O
AE30
MCA[0]_AXR[3]
McASP0 Transmit/Receive Data I/O
I/O
AC31
MCA[0]_AXR[4]
McASP0 Transmit/Receive Data I/O
I/O
AD26
MCA[0]_AXR[5]
McASP0 Transmit/Receive Data I/O
I/O
AD27
3.3.14.2 McASP1
Table 3-30. McASP1 Terminal Functions
SIGNAL NAME [1]
DESCRIPTION [2]
TYPE [3]
AAR BALL [4]
MCA[1]_ACLKR
McASP1 Receive Bit Clock I/O
I/O
AD29
MCA[1]_ACLKX
McASP1 Transmit Bit Clock I/O
I/O
AC23
MCA[1]_AFSR
McASP1 Receive Frame Sync I/O
I/O
AC24
MCA[1]_AFSX
McASP1 Transmit Frame Sync I/O
I/O
AB22
MCA[1]_AHCLKX
McASP1 Transmit High-Frequency Master Clock I/O
I/O
AF27
MCA[1]_AXR[0]
McASP1 Transmit/Receive Data I/O
I/O
Y22
MCA[1]_AXR[1]
McASP1 Transmit/Receive Data I/O
I/O
Y21
84
Device Pins
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3.3.15 Oscillator/PLL, Audio Reference Clocks, and Clock Generator
3.3.15.1
Audio Reference Clocks
Table 3-31. Audio Reference Clocks Terminal Functions
SIGNAL NAME [1]
DESCRIPTION [2]
TYPE [3]
AAR BALL [4]
AUD_CLKIN0
Audio Reference Clock 0 for Audio Peripherals
I
AF31
AUD_CLKIN1
Audio Reference Clock 1 for Audio Peripherals
I
AF27
AUD_CLKIN2
Audio Reference Clock 2 for Audio Peripherals
I
AG30
3.3.15.2 CLOCK GENERATOR
Table 3-32. Clock Generator Terminal Functions
SIGNAL NAME [1]
DESCRIPTION [2]
TYPE [3]
AAR BALL [4]
CLKOUT0
Device Clock output 0. Can be used as a system clock
for other devices.
O
AJ31, H12
CLKOUT1
Device Clock output 1. Can be used as a system clock
for other devices.
O
AB9, J16
3.3.15.3 OSCILLATOR/PLL
Table 3-33. Oscillator/PLL Terminal Functions
SIGNAL NAME [1]
DESCRIPTION [2]
TYPE [3]
AAR BALL [4]
AUXOSC_MXI
Auxiliary Crystal input [Optional Audio/Video Reference
Crystal Input]. Crystal connection to internal oscillator for
auxiliary clock. Functions as AUX_CLKIN clock input
when an external oscillator is used. If neither a crystal or
external clock is used, this pin should be connected to
ground.
I
V30
AUXOSC_MXO
Auxiliary Crystal output [Optional Audio/Video Reference
Crystal Output]. When auxiliary oscillator is BYPASSED,
leave this pin unconnected.
O
U31
CLKIN32
RTC Clock input. Optional 32.768 KHz clock for RTC
reference.
I
AJ31
DEVOSC_MXI
Device Crystal input. Crystal connection to internal
oscillator for system clock. Functions as DEV_CLKIN
clock input when an external oscillator is used.
I
F30
DEVOSC_MXO
Device Crystal output. Crystal connection to internal
oscillator for system clock. When device oscillator is
BYPASSED, leave this pin unconnected.
O
G31
DEVOSC_WAKE
Oscillator Wake-up input
I
U28
DEV_CLKIN
Clock input when an external oscillator is used
I
F30
Device Pins
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3.3.16 PCI Express (PCIe)
Table 3-34. PCI Express (PCIe) Terminal Functions
SIGNAL NAME [1]
DESCRIPTION [2]
TYPE [3]
AAR BALL [4]
PCIE_RXN0
PCIE Receive Data Lane 0. When the PCIe SERDES are I
powered down, these pins should be left unconnected.
J30
PCIE_RXP0
PCIE Receive Data Lane 0. When the PCIe SERDES are I
powered down, these pins should be left unconnected.
K30
PCIE_TXN0
PCIE Transmit Data Lane 0. When the PCIe SERDES
are powered down, these pins should be left
unconnected.
O
K31
PCIE_TXP0
PCIE Transmit Data Lane 0. When the PCIe SERDES
are powered down, these pins should be left
unconnected.
O
L31
SERDES_CLKN
PCIE Serdes Reference Clock Inputs and optional SATA
Reference Clock Inputs. When PCIe is not used, and
these pins are not used as optional SATA Reference
Clock Inputs, these pins can be left unconnected.
I
H31
SERDES_CLKP
PCIE Serdes Reference Clock Inputs and optional SATA
Reference Clock Inputs. When PCIe is not used, and
these pins are not used as optional SATA Reference
Clock Inputs, these pins can be left unconnected.
I
H30
86
Device Pins
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3.3.17 Reserved Pins
Table 3-35. Reserved Terminal Functions
SIGNAL NAME [1]
DESCRIPTION [2]
TYPE [3]
AAR BALL [4]
RSV0
Reserved. Leave unconnected, do not connect to power
or ground.
J25
RSV1
Reserved. Leave unconnected, do not connect to power
or ground.
H27
RSV2
Reserved. Leave unconnected, do not connect to power
or ground.
H24
RSV3
Reserved. Leave unconnected, do not connect to power
or ground.
H28
RSV31
Reserved. Leave unconnected, do not connect to power
or ground.
P31
RSV32
Reserved. Leave unconnected, do not connect to power
or ground.
R30
RSV33
Reserved. Leave unconnected, do not connect to power
or ground.
T30
RSV34
Reserved. Leave unconnected, do not connect to power
or ground.
AH24
RSV35
Reserved. Leave unconnected, do not connect to power
or ground.
AJ24
RSV39
Reserved. Leave unconnected, do not connect to power
or ground.
H25
RSV4
Reserved. Leave unconnected, do not connect to power
or ground.
RSV40
Reserved. Leave unconnected, do not connect to power
or ground.
H29
RSV41
Reserved. Leave unconnected, do not connect to power
or ground.
AD8
RSV42
Reserved. Leave unconnected, do not connect to power
or ground.
RSV43
Reserved. Leave unconnected, do not connect to power
or ground.
RSV5
Reserved. Leave unconnected, do not connect to power
or ground.
PWR
G16
RSV54
For proper device operation, this pin must always be
connected to a 1.8-V Power Supply.
PWR
M28
PWR
O
G17
AK21
P30
Device Pins
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3.3.18 Reset, Interrupts, and JTAG Interface
3.3.18.1 Interupts
Table 3-36. Interrupts Terminal Functions
SIGNAL NAME [1]
NMI
DESCRIPTION [2]
TYPE [3]
Non-Maskable Interrupt input
I
AAR BALL [4]
AH31
3.3.18.2 JTAG
Table 3-37. JTAG Terminal Functions
SIGNAL NAME [1]
DESCRIPTION [2]
TYPE [3]
AAR BALL [4]
EMU0
Emulator pin 0
I/O
A18
EMU1
Emulator pin 1
I/O
B19
EMU2
Emulator pin 2
I/O
F24
EMU3
Emulator pin 3
I/O
C25
EMU4
Emulator pin 4
I/O
C28
RTCK
JTAG return clock output. The internal pullup (IPU) is
enabled for this pin when the device is in reset and the
IPU is disabled (DIS) when reset is released.
O
N29
TCLK
JTAG test clock input
I
T29
TDI
JTAG test data input
I
N28
TDO
JTAG test port data output
O
U26
TMS
JTAG test port mode select input. For proper operation,
do not oppose the IPU on this pin.
I
T31
TRST
JTAG test port reset input
I
U24
3.3.18.3 Reset
Table 3-38. Reset Terminal Functions
SIGNAL NAME [1]
DESCRIPTION [2]
TYPE [3]
AAR BALL [4]
POR
Power-On Reset input
I
AH30
RESET
Device Reset input
I
AH29
RSTOUT_WD_OUT
Reset output (RSTOUT) or watchdog out (WD_OUT). If
this pin is unused, it can be left unconnected.
O
AJ30
88
Device Pins
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3.3.19 SD Signals (MMC/SD/SDIO)
3.3.19.1 SD0
Table 3-39. SD0 Terminal Functions
SIGNAL NAME [1]
DESCRIPTION [2]
TYPE [3]
AAR BALL [4]
SD0_CLK
SD0 Clock output
O
AB30
SD0_CMD
SD0 Command output
O
AA29
SD0_DAT[0]
SD0 Data0 I/O. Functions as data bit 0 for 4-/8-bit SD
mode and single data bit for 1-bit SD mode.
I/O
AA28
SD0_DAT[3]
SD0 Data3 I/O. Functions as data bit 3 for 4-/8-bit SD
mode.
I/O
Y30
SD0_DAT[4]
SD0 Data4 I/O. Functions as data bit 4 for 8-bit SD
mode.
I/O
Y22
SD0_DAT[5]
SD0 Data5 I/O. Functions as data bit 5 for 8-bit SD
mode.
I/O
Y21
SD0_DAT[6]
SD0 Data6 I/O. Functions as data bit 6 for 8-bit SD
mode.
I/O
AB31
SD0_DAT[7]
SD0 Data7 I/O. Functions as data bit 7 for 8-bit SD
mode.
I/O
AC30
SD0_DAT[1]_SDIRQ
SD0 Data1 I/O. Functions as data bit 1 for 4-/8-bit SD
mode and as an IRQ input for 1-bit SD mode.
I/O
AA26
SD0_DAT[2]_SDRW
SD0 Data2 I/O. Functions as data bit 2 for 4-/8-bit SD
mode and as a Read Wait input for 1-bit SD mode.
I/O
Y31
SD0_SDCD
SD0 Card Detect input
I
D30
3.3.19.2 SD1
Table 3-40. SD1Terminal Functions
SIGNAL NAME [1]
DESCRIPTION [2]
TYPE [3]
AAR BALL [4]
SD1_CLK
SD1 Clock output
O
W30
SD1_CMD
SD1 Command output
O
AA29, Y29
SD1_DAT[0]
SD1 Data0 I/O. Functions as data bit 0 for 4-/8-bit SD
mode and single data bit for 1-bit SD mode.
I/O
W31
SD1_DAT[3]
SD1 Data3 I/O. Functions as data bit 3 for 4-/8-bit SD
mode.
I/O
Y27
SD1_DAT[4]
SD1 Data4 I/O. Functions as data bit 4 for 8-bit SD
mode.
I/O
AA28
SD1_DAT[5]
SD1 Data5 I/O. Functions as data bit 5 for 8-bit SD
mode.
I/O
AA26
SD1_DAT[6]
SD1 Data6 I/O. Functions as data bit 6 for 8-bit SD
mode.
I/O
Y31
SD1_DAT[7]
SD1 Data7 I/O. Functions as data bit 7 for 8-bit SD
mode.
I/O
Y30
SD1_DAT[1]_SDIRQ
SD1 Data1 I/O. Functions as data bit 1 for 4-/8-bit SD
mode and as an IRQ input for 1-bit SD mode.
I/O
AA30
SD1_DAT[2]_SDRW
SD1 Data2 I/O. Functions as data bit 2 for 4-/8-bit SD
mode and as a Read Wait input for 1-bit SD mode.
I/O
U29
SD1_POW
SD1 Card Power Enable output
O
E31
SD1_SDCD
SD1 Card Detect input
I
G28
SD1_SDWP
SD1 Card Write Protect input
I
E29
Device Pins
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3.3.19.3 SD2
Table 3-41. SD2Terminal Functions
SIGNAL NAME [1]
DESCRIPTION [2]
TYPE [3]
AAR BALL [4]
SD2_CMD
SD2 Command output
O
AG6
SD2_DAT[0]
SD2 Data0 I/O. Functions as data bit 0 for 4-/8-bit SD
mode and single data bit for 1-bit SD mode.
O
AC4
SD2_DAT[3]
SD2 Data3 I/O. Functions as data bit 3 for 4-/8-bit SD
mode.
I/O
AD1
SD2_DAT[4]
SD2 Data4 I/O. Functions as data bit 4 for 8-bit SD
mode.
I/O
AD2
SD2_DAT[5]
SD2 Data5 I/O. Functions as data bit 5 for 8-bit SD
mode.
I/O
AE1
SD2_DAT[6]
SD2 Data6 I/O. Functions as data bit 6 for 8-bit SD
mode.
I/O
AE2
SD2_DAT[7]
SD2 Data7 I/O. Functions as data bit 7 for 8-bit SD
mode.
I/O
AE3
SD2_DAT[1]_SDIRQ
SD2 Data1 I/O. Functions as data bit 1 for 4-/8-bit SD
mode and as an IRQ input for 1-bit SD mode.
I/O
AC5
SD2_DAT[2]_SDRW
SD2 Data2 I/O. Functions as data bit 2 for 4-/8-bit SD
mode and as a Read Wait input for 1-bit SD mode.
I/O
AC8
SD2_SCLK
SD2 Clock output
I/O
AC6
SD2_SDCD
SD2 Card Detect input
I
D31
90
Device Pins
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3.3.20 SPI
3.3.20.1 SPI 0
Table 3-42. SPI 0 Terminal Functions
SIGNAL NAME [1]
DESCRIPTION [2]
TYPE [3]
AAR BALL [4]
SPI[0]_D[0]
SPI Data I/O. Can be configured as either MISO or
MOSI.
I/O
J28
SPI[0]_D[1]
SPI Data I/O. Can be configured as either MISO or
MOSI.
I/O
J27
SPI[0]_SCLK
SPI Clock I/O
I/O
N24
SPI[0]_SCS[0]
SPI Chip Select I/O
I/O
G29
SPI[0]_SCS[1]
SPI Chip Select I/O
I/O
G28
SPI[0]_SCS[2]
SPI Chip Select I/O
I/O
E29
SPI[0]_SCS[3]
SPI Chip Select I/O
I/O
E31
3.3.20.2 SPI 1
Table 3-43. SPI 1 Terminal Functions
SIGNAL NAME [1]
DESCRIPTION [2]
TYPE [3]
AAR BALL [4]
SPI[1]_D[0]
SPI Data I/O. Can be configured as either MISO or
MOSI.
I/O
N23
SPI[1]_D[1]
SPI Data I/O. Can be configured as either MISO or
MOSI.
I/O
M27
SPI[1]_SCLK
SPI Clock I/O
I/O
M29
SPI[1]_SCS[0]
SPI Chip Select I/O
I/O
J29
SPI[1]_SCS[1]
SPI Chip Select I/O
I/O
U28
SPI[1]_SCS[2]
SPI Chip Select I/O
I/O
D31
SPI[1]_SCS[3]
SPI Chip Select I/O
I/O
D30
3.3.20.3 SPI 2
Table 3-44. SPI 2 Terminal Functions
SIGNAL NAME [1]
DESCRIPTION [2]
TYPE [3]
AAR BALL [4]
SPI[2]_D[0]
SPI Data I/O. Can be configured as either MISO or
MOSI.
I/O
AK6, M8, N1
SPI[2]_D[1]
SPI Data I/O. Can be configured as either MISO or
MOSI.
I/O
AL6, L6, N2
SPI[2]_SCLK
SPI Clock I/O
I/O
AJ6, L4, R8
SPI[2]_SCS[0]
SPI Chip Select I/O
I/O
AF2
SPI[2]_SCS[1]
SPI Chip Select I/O
I/O
N9
SPI[2]_SCS[2]
SPI Chip Select I/O
I/O
L2
SPI[2]_SCS[3]
SPI Chip Select I/O
I/O
AK5
3.3.20.4 SPI 3
Table 3-45. SPI 3 Terminal Functions
SIGNAL NAME [1]
DESCRIPTION [2]
TYPE [3]
AAR BALL [4]
SPI[3]_D[0]
SPI Data I/O. Can be configured as either MISO or
MOSI.
I/O
A5, F5, M10
SPI[3]_D[1]
SPI Data I/O. Can be configured as either MISO or
MOSI.
I/O
A6, E2, L12
Device Pins
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Table 3-45. SPI 3 Terminal Functions (continued)
SIGNAL NAME [1]
DESCRIPTION [2]
TYPE [3]
AAR BALL [4]
SPI[3]_SCLK
SPI Clock I/O
I/O
C20, C7, M11
SPI[3]_SCS[0]
SPI Chip Select I/O
I/O
F9
SPI[3]_SCS[1]
SPI Chip Select I/O
I/O
H2
SPI[3]_SCS[2]
SPI Chip Select I/O
I/O
AK1
SPI[3]_SCS[3]
SPI Chip Select I/O
I/O
AG4
92
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3.3.21 Serial ATA (SATA) Signals
3.3.21.1 SATA0
Table 3-46. Serial ATA 0 (SATA0) Terminal Functions
SIGNAL NAME [1]
DESCRIPTION [2]
TYPE [3]
O
AAR BALL [4]
SATA0_ACT0_LED
Serial ATA Disk 0 Activity LED Output
G28
SATA0_RXN0
Serial ATA Data0 Receive. When the SATA SERDES are I
powered down, these pins should be left unconnected.
L30
SATA0_RXP0
Serial ATA Data0 Receive. When the SATA SERDES are I
powered down, these pins should be left unconnected.
M30
SATA0_TXN0
Serial ATA Data0 Transmit. When the SATA SERDES
are powered down, these pins should be left
unconnected.
O
N30
SATA0_TXP0
Serial ATA Data0 Transmit. When the SATA SERDES
are powered down, these pins should be left
unconnected.
O
N31
Device Pins
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3.3.22 Supply Voltages
Table 3-47. Supply Voltages Terminal Functions
SIGNAL NAME [1]
DESCRIPTION [2]
TYPE [3]
AAR BALL [4]
CVDD
Variable Voltage Supply for the CORE_L Core Logic
Voltage Domain
PWR
P15, P17, R15, R17,
T13, T17, T18, U11,
U12, U15, U17, V11,
V12, V15, V17, W13,
W14, W19, W20, Y13,
Y14, Y19, Y20
CVDD_ARM
Variable Voltage Supply for the ARM_L Core Logic
Voltage Domain. For actual voltage supply ranges, see
Recommended Operating Conditions.
PWR
K17, L17, L18, M13,
M14, M17
CVDD_HDVICP
Variable Voltage Supply for the HDVICP_L Core Logic
Voltage Domain. For actual voltage supply ranges, see
Recommended Operating Conditions.
PWR
U20, U21, V20, V21,
W22
DVDD
3.3 V/1.8 V Power Supply for General I/Os
PWR
D16, E17, F16, L5,
M4, M6, M7, N10,
N11, T26, T28, U27
DVDD_C
3.3 V/1.8 V Power Supply for Camera I/F I/Os. For proper PWR
device operation, this pin must always be connected to a
DVDD Power Supply, even if the Camera I/F is not being
used.
D12, E13, F12, G12,
G13
DVDD_DDR[0]
1.35 V/1.5 V/1.8 V Power Supply for DDR[0] I/Os
PWR
AB14, AB15, AB17,
AB18, AC15, AC17,
AC18, AE15, AE16,
AF16, AG15, AH16
DVDD_GPMC
3.3 V/1.8 V Power Supply for GPMC I/Os. For proper
device operation, this pin must always be connected to a
DVDD Power Supply, even if the GPMC is not being
used.
PWR
R5, R7, T4, T6, T7
DVDD_RGMII
3.3 V/1.8 V Power Supply for RGMII I/Os. For proper
device operation, this pin must always be connected to a
DVDD Power Supply, even if the RGMII is not being
used.
PWR
W5, W7, Y4, Y6, Y7
DVDD_SD
3.3 V/1.8 V Power Supply for MMC/SD/SDIO I/Os. For
PWR
proper device operation, this pin must always be
connected to a DVDD Power Supply, even if the interface
is not being used.
T25, U25
LDOCAP_ARM
ARM Cortex-A8 VBB LDO output. This pin must always
be connected via a 1-uF capacitor to VSS.
A
J19
LDOCAP_ARMRAM
ARM Cortex-A8 RAM LDO output. This pin must always
be connected via a 1-uF capacitor to VSS.
A
K20
LDOCAP_HDVICP
HDVICP2 VBB LDO output.This pin must always be
connected via a 1-uF capacitor to VSS.
A
W23
LDOCAP_HDVICPRAM
HDVICP2 RAM LDO output. This pin must always be
connected via a 1-uF capacitor to VSS.
A
Y24
LDOCAP_RAM0
CORE RAM0 LDO output. This pin must always be
connected via a 1-uF capacitor to VSS.
A
U9
LDOCAP_RAM1
CORE RAM1 LDO output. This pin must always be
connected via a 1-uF capacitor to VSS.
A
T22
LDOCAP_RAM2
CORE RAM2 LDO output. This pin must always be
connected via a 1-uF capacitor to VSS.
A
AB10
LDOCAP_SERDESCLK
SERDES_CLKP/N Pins LDO output. This pin must
always be connected via a 1-uF capacitor to VSS.
A
M24
VDDA_1P8
1.8 V Power Supply for on-chip LDOs and I/O biasing
PWR
M25, N22, N25, P23,
R9, T10, T9
VDDA_ARMPLL_1P8
1.8 V Analog Power Supply for PLL_ARM
PWR
L19
VDDA_AUDIOPLL_1P8
1.8 V Analog Power Supply for PLL_AUDIO and
PWR
PLL_HDVPSS. For proper device operation, this pin must
always be connected to a 1.8-V Power Supply.
94
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Table 3-47. Supply Voltages Terminal Functions (continued)
SIGNAL NAME [1]
DESCRIPTION [2]
TYPE [3]
AAR BALL [4]
VDDA_CSI2_1P8
1.8 V Analog Power Supply for CSI2. For proper device
operation, this pin must always be connected to a 1.8-V
Power Supply, even if the CSI2 is not being used.
PWR
W10
VDDA_DDRPLL_1P8
1.8 V Analog Power Supply for PLL_DDR
PWR
AA19
VDDA_HDDACREF_1P8
1.8 V Reference Power Supply for HDDAC. For proper
device operation, this pin must always be connected to a
1.8-V Power Supply, even if the HDDAC is not being
used.
PWR
L15
VDDA_HDDAC_1P1
1.1 V Power Supply for HD-DAC Digital Logic. For proper PWR
device operation, this pin must always be connected to a
1.1-V Power Supply, or if the HD-DAC is not being used
it can be connected to a power supply in the range of
0.9–1.35 V (same level as other core voltages).
K16
VDDA_HDDAC_1P8
1.8 V Power Supply for HDDAC Analog Circuit. For
proper device operation, this pin must always be
connected to a 1.8-V Power Supply, even if the HDDAC
is not being used.
PWR
L14
VDDA_HDMI_1P8
1.8 V Analog Power Supply for HDMI. For proper device
operation, this pin must always be connected to a 1.8-V
Power Supply, even if the HDMI is not being used.
PWR
K14
VDDA_HDVICPPLL_1P8
1.8 V Analog Power Supply for PLL_HDVICP. For proper
device operation, this pin must always be connected to a
1.8-V Power Supply, even if the HDVICP2 is not being
used.
PWR
T23
VDDA_L3L4PLL_1P8
1.8 V Analog Power Supply for PLL_L3L4
PWR
W11
VDDA_PCIE_1P8
1.8 V Analog Power Supply for PCIe. For proper device
operation, this pin must always be connected to a 1.8-V
Power Supply, even if the PCIe is not being used.
PWR
M26
VDDA_SATA0_1P8
1.8 V Analog Power Supply for SATA0. For proper device PWR
operation, this pin must always be connected to a 1.8-V
Power Supply, even if the SATA0 is not being used.
N27
VDDA_USB0_1P8
1.8 V Analog Power Supply for USB0. For proper device
operation, this pin must always be connected to a 1.8-V
Power Supply, even if the USB0 is not being used.
PWR
K19
VDDA_USB1_1P8
1.8 V Analog Power Supply for USB1 .For proper device
operation, this pin must always be connected to a 1.8-V
Power Supply, even if the USB1 is not being used.
PWR
J17
VDDA_USB_3P3
3.3 V Analog Power Supply for USB0 and USB1. For
proper device operation, this pin must always be
connected to a 3.3-V Power Supply, even if USB0 and
USB1 are not being used.
PWR
M19, M20
VDDA_VDAC_1P8
1.8 V Reference Power Supply for VDAC. For proper
device operation, this pin must always be connected to a
1.8-V Power Supply, even if the VDAC is not being used.
PWR
J14
VDDA_VIDPLL_1P8
1.8 V Analog Power Supply for PLL_VIDEO0 and
PLL_VIDEO1. For proper device operation, this pin must
always be connected to a 1.8-V Power Supply.
PWR
L13
VDDS_OSC0_1P8
Oscillator0 IO secondary supply and LJCB LDO supply
PWR
P21
VDDS_OSC1_1P8
Oscillator1 IO secondary power supply
PWR
P20
VREFSSTL_DDR[0]
Reference Power Supply DDR[0]
PWR
AL18
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3.3.23 Timer
Table 3-48. Timer Terminal Functions
SIGNAL NAME [1]
DESCRIPTION [2]
TYPE [3]
AAR BALL [4]
TIM2_IO
Timer 2 capture event input or PWM output
I/O
AF27, AG1, M3
TIM3_IO
Timer 3 capture event input or PWM output
I/O
AG30, AJ31, M5
TIM4_IO
Timer 4 capture event input or PWM output
I/O
AB9, G28, N2
TIM5_IO
Timer 5 capture event input or PWM output
I/O
AA10, R8, U28
TIM6_IO
Timer 6 capture event input or PWM output
I/O
AE1, F1, Y3
TIM7_IO
Timer 7 capture event input or PWM output
I/O
AD2, C20, Y11
96
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3.3.24 UART
3.3.24.1 UART0
Table 3-49. UART0 Terminal Functions
SIGNAL NAME [1]
DESCRIPTION [2]
TYPE [3]
AAR BALL [4]
UART0_CTS
UART0 Clear to Send Input. Functions as SD transceiver
control output in IrDA and CIR modes.
I/O
D30
UART0_DCD
UART0 Data Carrier Detect Input
I
E31
UART0_DSR
UART0 Data Set Ready Input
I
E29
UART0_DTR
UART0 Data Terminal Ready Output
O
E30
UART0_RIN
UART0 Ring Indicator Input
I
N26
UART0_RTS
UART0 Request to Send Output. Indicates module is
ready to receive data. Functions as transmit data output
in IrDA modes.
O
D31
UART0_RXD
UART0 Receive Data Input. Functions as IrDA receive
input in IrDA modes and CIR receive input in CIR mode.
I
J26
UART0_TXD
UART0 Transmit Data Output. Functions as CIR transmit
output in CIR mode.
O
E28
3.3.24.2 UART1
Table 3-50. UART1 Terminal Functions
SIGNAL NAME [1]
DESCRIPTION [2]
TYPE [3]
AAR BALL [4]
UART1_CTS
UART1 Clear to Send Input. Functions as SD transceiver
control output in IrDA and CIR modes.
I/O
AG8
UART1_RTS
UART1 Request to Send Output. Indicates module is
ready to receive data. Functions as transmit data output
in IrDA modes.
O
AF8
UART1_RXD
UART1 Receive Data Input. Functions as IrDA receive
input in IrDA modes and CIR receive input in CIR mode.
(N26:MUX0, AJ8:MUX1)
I
AJ8, N26
UART1_TXD
UART1 Transmit Data Output. Functions as CIR transmit
output in CIR mode. (E30:MUX0, AH8:MUX1)
O
AH8, E30
3.3.24.3 UART2
Table 3-51. UART2 Terminal Functions
SIGNAL NAME [1]
DESCRIPTION [2]
TYPE [3]
AAR BALL [4]
UART2_CTS
UART2 Clear to Send Input. Functions as SD transceiver
control output in IrDA and CIR modes.
I/O
J10
UART2_RTS
UART2 Request to Send Output. Indicates module is
ready to receive data. Functions as transmit data output
in IrDA modes.
O
B3
UART2_RXD
UART2 Receive Data Input. Functions as IrDA receive
input in IrDA modes and CIR receive input in CIR mode.
(D5:MUX0, L22:MUX1, AE3:MUX3)
I
AE3, D5, L22
UART2_TXD
UART2 Transmit Data Output. Functions as CIR transmit
output in CIR mode. (H9:MUX0, M21:MUX1, AE2:MUX3)
O
AE2, H9, M21
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3.3.25 USB
3.3.25.1 USB0
Table 3-52. USB0 Terminal Functions
SIGNAL NAME [1]
DESCRIPTION [2]
TYPE [3]
AAR BALL [4]
USB0_CE
USB0 charger enable. When the USB0 PHY is powered
down, this pin should be left unconnected.
O
B20
USB0_DM
USB0 bidirectional data differential signal pair
[plus/minus]. When the USB0 PHY is powered down, this
pin should be left unconnected.
I/O
B21
USB0_DP
USB0 bidirectional data differential signal pair
[plus/minus]. When the USB0 PHY is powered down, this
pin should be left unconnected.
I/O
A21
USB0_DRVVBUS
USB0 Contoller VBUS Control ouput. When this pin is
used as USB0_DRVVBUS and the USB0 Controller is
operating as a Host, this signal is used by the USB0
Controller to enable the external VBUS charge pump.
When the USB0 PHY is powered down, this pin should
be left unconnected.
O
K23
USB0_ID
USB0 identification input. When the USB0 PHY is
powered down, this pin should be left unconnected.
I
A20
USB0_VBUSIN
5-V USB0 VBUS comparator input. This analog input pin
senses the level of the USB VBUS voltage and should
connect directly to the USB VBUS voltage. When the
USB0 PHY is powered down, this pin should be left
unconnected.
I
B22
3.3.25.2 USB1
Table 3-53. USB1 Terminal Functions
SIGNAL NAME [1]
DESCRIPTION [2]
TYPE [3]
AAR BALL [4]
USB1_CE
USB1 charger enable. When the USB1 PHY is powered
down, this pin should be left unconnected.
O
C21
USB1_DM
USB1 bidirectional data differential signal pair
[plus/minus]. When the USB1 PHY is powered down, this
pin should be left unconnected.
I/O
B23
USB1_DP
USB1 bidirectional data differential signal pair
[plus/minus]. When the USB1 PHY is powered down, this
pin should be left unconnected.
I/O
A23
USB1_DRVVBUS
USB1 Contoller VBUS Control ouput. When this pin is
used as USB1_DRVVBUS and the USB1 Controller is
operating as a Host, this signal is used by the USB1
Controller to enable the external VBUS charge pump.
When the USB1 PHY is powered down, this pin should
be left unconnected.
O
AF31
USB1_ID
USB1 identification input. When the USB1 PHY is
powered down, this pin should be left unconnected.
I
A24
USB1_VBUSIN
5-V USB1 VBUS comparator input. This analog input pin
senses the level of the USB VBUS voltage and should
connect directly to the USB VBUS voltage. When the
USB1 PHY is powered down, this pin should be left
unconnected.
I
B24
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3.3.26 Video Input (Digital)
3.3.26.1 Video Input 0 (Digital)
Table 3-54. Video Input 0 (Digital) Terminal Functions
SIGNAL NAME [1]
DESCRIPTION [2]
TYPE [3]
AAR BALL [4]
VIN[0]A_CLK
Video Input 0 Port A Clock input. Input clock for 8-bit, 16bit, or 24-bit Port A video capture.
I
C9
VIN[0]A_D[0]
Video Input 0 Data inputs. For 16-bit capture, D[7:0] are
Cb/Cr Port A inputs. For 8-bit capture, D[7:0] are Port A
YCbCr data inputs. For RGB capture, D[7:0] are B data
inputs.
I
B18
VIN[0]A_D[1]
Video Input 0 Data inputs. For 16-bit capture, D[7:0] are
Cb/Cr Port A inputs. For 8-bit capture, D[7:0] are Port A
YCbCr data inputs. For RGB capture, D[7:0] are B data
inputs.
I
A17
VIN[0]A_D[2]
Video Input 0 Data inputs. For 16-bit capture, D[7:0] are
Cb/Cr Port A inputs. For 8-bit capture, D[7:0] are Port A
YCbCr data inputs. For RGB capture, D[7:0] are B data
inputs.
I
B17
VIN[0]A_D[3]
Video Input 0 Data inputs. For 16-bit capture, D[7:0] are
Cb/Cr Port A inputs. For 8-bit capture, D[7:0] are Port A
YCbCr data inputs. For RGB capture, D[7:0] are B data
inputs.
I
C17
VIN[0]A_D[4]
Video Input 0 Data inputs. For 16-bit capture, D[7:0] are
Cb/Cr Port A inputs. For 8-bit capture, D[7:0] are Port A
YCbCr data inputs. For RGB capture, D[7:0] are B data
inputs.
I
D17
VIN[0]A_D[5]
Video Input 0 Data inputs. For 16-bit capture, D[7:0] are
Cb/Cr Port A inputs. For 8-bit capture, D[7:0] are Port A
YCbCr data inputs. For RGB capture, D[7:0] are B data
inputs.
I
F17
VIN[0]A_D[6]
Video Input 0 Data inputs. For 16-bit capture, D[7:0] are
Cb/Cr Port A inputs. For 8-bit capture, D[7:0] are Port A
YCbCr data inputs. For RGB capture, D[7:0] are B data
inputs.
I
L20
VIN[0]A_D[7]
Video Input 0 Data inputs. For 16-bit capture, D[7:0] are
Cb/Cr Port A inputs. For 8-bit capture, D[7:0] are Port A
YCbCr data inputs. For RGB capture, D[7:0] are B data
inputs.
I
H20
VIN[0]A_D[16]
Video Input 0 Data inputs. For RGB capture, D[23:16] are I
R data inputs.
K11
VIN[0]A_D[17]
Video Input 0 Data inputs. For RGB capture, D[23:16] are I
R data inputs.
E12
VIN[0]A_D[18]
Video Input 0 Data inputs. For RGB capture, D[23:16] are I
R data inputs.
K10
VIN[0]A_D[19]
Video Input 0 Data inputs. For RGB capture, D[23:16] are I
R data inputs.
D7
VIN[0]A_D[20]
Video Input 0 Data inputs. For RGB capture, D[23:16] are I
R data inputs.
F9
VIN[0]A_D[21]
Video Input 0 Data inputs. For RGB capture, D[23:16] are I
R data inputs.
C7
VIN[0]A_D[22]
Video Input 0 Data inputs. For RGB capture, D[23:16] are I
R data inputs.
A6
VIN[0]A_D[23]
Video Input 0 Data inputs. For RGB capture, D[23:16] are I
R data inputs.
A5
VIN[0]A_DE
Video Input 0 Port A Data Enable input. Discrete data
valid signal for Port A RGB capture mode or YCbCr
capture without embedded syncs (BT.601 modes).
B5, C12
I
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Table 3-54. Video Input 0 (Digital) Terminal Functions (continued)
SIGNAL NAME [1]
DESCRIPTION [2]
TYPE [3]
AAR BALL [4]
VIN[0]A_D[10]_BD[2]
Video Input 0 Data inputs. For 16-bit capture, D[15:8] are
Y Port A inputs. For 8-bit capture, D[15:8] are Port B
YCbCr data inputs. For RGB capture, D[15:8] are G data
inputs.
I
E16
VIN[0]A_D[11]_BD[3]
Video Input 0 Data inputs. For 16-bit capture, D[15:8] are
Y Port A inputs. For 8-bit capture, D[15:8] are Port B
YCbCr data inputs. For RGB capture, D[15:8] are G data
inputs.
I
H17
VIN[0]A_D[12]_BD[4]
Video Input 0 Data inputs. For 16-bit capture, D[15:8] are
Y Port A inputs. For 8-bit capture, D[15:8] are Port B
YCbCr data inputs. For RGB capture, D[15:8] are G data
inputs.
I
J16
VIN[0]A_D[13]_BD[5]
Video Input 0 Data inputs. For 16-bit capture, D[15:8] are
Y Port A inputs. For 8-bit capture, D[15:8] are Port B
YCbCr data inputs. For RGB capture, D[15:8] are G data
inputs.
I
H16
VIN[0]A_D[14]_BD[6]
Video Input 0 Data inputs. For 16-bit capture, D[15:8] are
Y Port A inputs. For 8-bit capture, D[15:8] are Port B
YCbCr data inputs. For RGB capture, D[15:8] are G data
inputs.
I
F13
VIN[0]A_D[15]_BD[7]
Video Input 0 Data inputs. For 16-bit capture, D[15:8] are
Y Port A inputs. For 8-bit capture, D[15:8] are Port B
YCbCr data inputs. For RGB capture, D[15:8] are G data
inputs.
I
H13
VIN[0]A_D[8]_BD[0]
Video Input 0 Data inputs. For 16-bit capture, D[15:8] are
Y Port A inputs. For 8-bit capture, D[15:8] are Port B
YCbCr data inputs. For RGB capture, D[15:8] are G data
inputs.
I
B16
VIN[0]A_D[9]_BD[1]
Video Input 0 Data inputs. For 16-bit capture, D[15:8] are
Y Port A inputs. For 8-bit capture, D[15:8] are Port B
YCbCr data inputs. For RGB capture, D[15:8] are G data
inputs.
I
C16
VIN[0]A_FLD
Video Input 0 Port A Field ID input. Discrete field
identification signal for Port A RGB capture mode or
YCbCr capture without embedded syncs (BT.601
modes).
I
B4, J13
VIN[0]A_HSYNC
Video Input 0 Port A Horizontal Sync0 input. Discrete
horizontal synchronization signal for Port A RGB capture
mode or YCbCr capture without embedded syncs
(BT.601 modes).
I
D13
VIN[0]A_VSYNC
Video Input 0 Port A Vertical Sync0 input. Discrete
vertical synchronization signal for Port A RGB capture
mode or YCbCr capture without embedded syncs
(BT.601 modes).
I
C13
VIN[0]B_CLK
Video Input 0 Port B Clock input. Input clock for 8-bit Port I
B video capture. This signal is not used in 16-bit and 24bit capture modes.
H12
VIN[0]B_DE
Video Input 0 Port B Data Enable input. Discrete data
valid signal for Port B RGB capture mode or YCbCr
capture without embedded syncs (BT.601 modes).
I
C5
VIN[0]B_FLD
Video Input 0 Port B Field ID input. Discrete field
I
identification signal for Port B 8-bit YCbCr capture without
embedded syncs (BT.601 modes). Not used in RGB or
16-bit YCbCr capture modes.
A3
VIN[0]B_HSYNC
Video Input 0 Port B Horizontal Sync input. Discrete
horizontal synchronization signal for Port B 8-bit YCbCr
capture without embedded syncs (BT.601 modes). Not
used in RGB or 16-bit YCbCr capture modes.
I
C12
VIN[0]B_VSYNC
Video Input 0 Port B Vertical Sync1 input. Discrete
vertical synchronization signal for Port B 8-bit YCbCr
capture without embedded syncs (BT.601 modes). Not
used in RGB or 16-bit YCbCr capture modes.
I
J13
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3.3.26.2 Video Input 1 (Digital)
Table 3-55. Video Input 1 (Digital) Terminal Functions
SIGNAL NAME [1]
DESCRIPTION [2]
TYPE [3]
AAR BALL [4]
VIN[1]A_CLK
Video Input 1 Port A Clock input. Input clock for 8-bit, 16bit, or 24-bit Port A video capture. Input data is sampled
on the CLK0 edge.
I
F1
VIN[1]A_D[0]
Video Input 1 Data inputs. For 16-bit capture, D[7:0] are
Cb/Cr Port A inputs. For 8-bit capture, D[7:0] are Port A
YCbCr data inputs. For RGB capture, D[7:0] are B Port A
data inputs.
I
F2
VIN[1]A_D[1]
Video Input 1 Data inputs. For 16-bit capture, D[7:0] are
Cb/Cr Port A inputs. For 8-bit capture, D[7:0] are Port A
YCbCr data inputs. For RGB capture, D[7:0] are B Port A
data inputs.
I
F3
VIN[1]A_D[2]
Video Input 1 Data inputs. For 16-bit capture, D[7:0] are
Cb/Cr Port A inputs. For 8-bit capture, D[7:0] are Port A
YCbCr data inputs. For RGB capture, D[7:0] are B Port A
data inputs.
I
G1
VIN[1]A_D[3]
Video Input 1 Data inputs. For 16-bit capture, D[7:0] are
Cb/Cr Port A inputs. For 8-bit capture, D[7:0] are Port A
YCbCr data inputs. For RGB capture, D[7:0] are B Port A
data inputs.
I
G2
VIN[1]A_D[4]
Video Input 1 Data inputs. For 16-bit capture, D[7:0] are
Cb/Cr Port A inputs. For 8-bit capture, D[7:0] are Port A
YCbCr data inputs. For RGB capture, D[7:0] are B Port A
data inputs.
I
H3
VIN[1]A_D[5]
Video Input 1 Data inputs. For 16-bit capture, D[7:0] are
Cb/Cr Port A inputs. For 8-bit capture, D[7:0] are Port A
YCbCr data inputs. For RGB capture, D[7:0] are B Port A
data inputs.
I
G3
VIN[1]A_D[6]
Video Input 1 Data inputs. For 16-bit capture, D[7:0] are
Cb/Cr Port A inputs. For 8-bit capture, D[7:0] are Port A
YCbCr data inputs. For RGB capture, D[7:0] are B Port A
data inputs.
I
H5
VIN[1]A_D[7]
Video Input 1 Data inputs. For 16-bit capture, D[7:0] are
Cb/Cr Port A inputs. For 8-bit capture, D[7:0] are Port A
YCbCr data inputs. For RGB capture, D[7:0] are B Port A
data inputs.
I
M8
VIN[1]A_D[8]
Video Input 1 Data inputs. For 16-bit capture, [15:8] are Y I
Port A inputs. For RGB capture, D[15:8] are G Port A
data inputs.
H6
VIN[1]A_D[9]
Video Input 1 Data inputs. For 16-bit capture, [15:8] are Y I
Port A inputs. For RGB capture, D[15:8] are G Port A
data inputs.
J8
VIN[1]A_D[10]
Video Input 1 Data inputs. For 16-bit capture, [15:8] are Y I
Port A inputs. For RGB capture, D[15:8] are G Port A
data inputs.
J1
VIN[1]A_D[11]
Video Input 1 Data inputs. For 16-bit capture, [15:8] are Y I
Port A inputs. For RGB capture, D[15:8] are G Port A
data inputs.
H4
VIN[1]A_D[12]
Video Input 1 Data inputs. For 16-bit capture, [15:8] are Y I
Port A inputs. For RGB capture, D[15:8] are G Port A
data inputs.
J9
VIN[1]A_D[13]
Video Input 1 Data inputs. For 16-bit capture, [15:8] are Y I
Port A inputs. For RGB capture, D[15:8] are G Port A
data inputs.
L3
VIN[1]A_D[14]
Video Input 1 Data inputs. For 16-bit capture, [15:8] are Y I
Port A inputs. For RGB capture, D[15:8] are G Port A
data inputs.
K1
VIN[1]A_D[15]
Video Input 1 Data inputs. For 16-bit capture, [15:8] are Y I
Port A inputs. For RGB capture, D[15:8] are G Port A
data inputs.
H2
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Table 3-55. Video Input 1 (Digital) Terminal Functions (continued)
SIGNAL NAME [1]
DESCRIPTION [2]
TYPE [3]
AAR BALL [4]
VIN[1]A_D[16]
Video Input 1 Data inputs. For RGB capture, D[23:16] are I
R Port A data inputs.
M11
VIN[1]A_D[17]
Video Input 1 Data inputs. For RGB capture, D[23:16] are I
R Port A data inputs.
L12
VIN[1]A_D[18]
Video Input 1 Data inputs. For RGB capture, D[23:16] are I
R Port A data inputs.
M10
VIN[1]A_D[19]
Video Input 1 Data inputs. For RGB capture, D[23:16] are I
R Port A data inputs.
J2
VIN[1]A_D[20]
Video Input 1 Data inputs. For RGB capture, D[23:16] are I
R Port A data inputs.
K2
VIN[1]A_D[21]
Video Input 1 Data inputs. For RGB capture, D[23:16] are I
R Port A data inputs.
L2
VIN[1]A_D[22]
Video Input 1 Data inputs. For RGB capture, D[23:16] are I
R Port A data inputs.
L4
VIN[1]A_D[23]
Video Input 1 Data inputs. For RGB capture, D[23:16] are I
R Port A data inputs.
L6
VIN[1]A_DE
Video Input 1 Port A Data Enable input. Discrete data
valid signal for Port A YCbCr capture modes without
embedded syncs (BT.601 modes).
I
F5
VIN[1]A_FLD
Video Input 1 Port A Field ID input. Discrete field
identification signal for Port A YCbCr capture modes
without embedded syncs (BT.601 modes).
I
F5
VIN[1]A_HSYNC
Video Input 1 Port A Horizontal Sync input. Discrete
horizontal synchronization signal for Port A YCbCr
capture modes without embedded syncs (BT.601
modes).
I
D3
VIN[1]A_VSYNC
Video Input 1 Port A Vertical Sync input. Discrete vertical
synchronization signal for Port A YCbCr capture modes
without embedded syncs (BT.601 modes).
I
E2
VIN[1]B_CLK
Video Input 1 Port B Clock input. Input clock for 8-bit Port I
B video capture. Input data is sampled on the CLK1
edge. This signal is not used in 16-bit and 24-bit capture
modes.
AF2
VIN[1]B_D[0]
Video Input Port B Data inputs. For 8-bit capture,
B_D[7:0] are Port B YCbCr data inputs.
I
AG4
VIN[1]B_D[1]
Video Input Port B Data inputs. For 8-bit capture,
B_D[7:0] are Port B YCbCr data inputs.
I
AH1
VIN[1]B_D[2]
Video Input Port B Data inputs. For 8-bit capture,
B_D[7:0] are Port B YCbCr data inputs.
I
AH2
VIN[1]B_D[3]
Video Input Port B Data inputs. For 8-bit capture,
B_D[7:0] are Port B YCbCr data inputs.
I
AJ2
VIN[1]B_D[4]
Video Input Port B Data inputs. For 8-bit capture,
B_D[7:0] are Port B YCbCr data inputs.
I
AK1
VIN[1]B_D[5]
Video Input Port B Data inputs. For 8-bit capture,
B_D[7:0] are Port B YCbCr data inputs.
I
AK2
VIN[1]B_D[6]
Video Input Port B Data inputs. For 8-bit capture,
B_D[7:0] are Port B YCbCr data inputs.
I
AL2
VIN[1]B_D[7]
Video Input Port B Data inputs. For 8-bit capture,
B_D[7:0] are Port B YCbCr data inputs.
I
AL3
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3.3.27 Video Output (Analog, TV)
Table 3-56. Video Output (Analog, TV) Terminal Functions
SIGNAL NAME [1]
DESCRIPTION [2]
TYPE [3]
AAR BALL [4]
HDDAC_A
Analog HD Video DAC (G/Y). This pin should be
connected to ground through a 165-ohm resistor.
O
A9
HDDAC_B
Analog HD Video DAC (B/Pb). This pin should be
connected to ground through a 165-ohm resistor.
O
A8
HDDAC_C
Analog HD Video DAC (R/Pr). This pin should be
connected to ground through a 165-ohm resistor.
O
B8
HDDAC_HSYNC
Analog HD Video DAC Discrete HSYNC Output
O
E9
HDDAC_IREF
Video DAC reference current. When the video DACs are
used, this pin should be connected to ground through a
2.67K-ohm resistor. When the video DACs are powered
down, this pin should be left unconnected.
I/O
B6
HDDAC_VREF
Video DAC reference voltage. When the video DACs are
powered down, this pin should be left unconnected.
I
B7
HDDAC_VSYNC
Analog HD Video DAC Discrete VSYNC Output
O
D9
TV_OUT0
Composite Amplifier Output. In Normal mode (internal
amplifier used), this pin drives the 75-Ohm TV load. An
external resistor (Rout) should be connected between
this pin and the TV_VFB0 pin and be placed as close to
the pins as possible. The nominal value of Rout is 2700
Ohm. In TVOUT Bypass mode (internal amplifier not
used), this pin is not used. When this pin is not used or
the TV output is powered-down, this pin should be left
unconnected.
O
B9
TV_RSET
TV Input Reference Current Setting. An external resistor A
(Rset) should be connected between this pin and
VSSA_VDAC to set the reference current of the video
DAC. The value of the resistor depends on the mode of
operation. In Normal mode (internal amplifier used), the
nominal value for Rset is 4700 Ohm. In TVOUT Bypass
mode (internal amplifier not used), the nominal value for
Rset is 10000 Ohm. When the TV output is not used, this
pin should be connected to ground (VSS).
B11
TV_VFB0
Composite Feedback. In Normal mode (internal amplifier O
used), this pin acts as the buffer feedback node. An
external resistor (Rout) should be connected between
this pin and the TV_OUT0 pin. In TVOUT Bypass mode
(internal amplifier not used), this pin acts as the direct
Video DAC output and should be connected to ground
through a load resistor (Rload) and to an external video
amplifier. The nominal value of Rload is 1500 Ohm.
When this pin is not used or the TV output is powereddown, this pin should be left unconnected.
B10
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3.3.28 Video Output (Digital)
3.3.28.1 Video Output 0 (Digital)
Table 3-57. Video Output 0 (Digital) Terminal Functions
SIGNAL NAME [1]
DESCRIPTION [2]
TYPE [3]
AAR BALL [4]
VOUT[0]_AVID
Video Output Active Video output. This is the discrete
active video indicator output. This signal is not used for
embedded sync modes.
O
C20
VOUT[0]_B_CB_C[2]
Video Output Data. These signals represent the 8 MSBs
of B/Cb/C video data. For RGB mode they are blue data
bits, for YUV444 mode they are Cb (Chroma) data bits,
for Y/C mode they are multiplexed Cb/Cr (Chroma) data
bits and for BT.656 mode they are unused.
O
F24
VOUT[0]_B_CB_C[3]
Video Output Data. These signals represent the 8 MSBs
of B/Cb/C video data. For RGB mode they are blue data
bits, for YUV444 mode they are Cb (Chroma) data bits,
for Y/C mode they are multiplexed Cb/Cr (Chroma) data
bits and for BT.656 mode they are unused.
O
D21
VOUT[0]_B_CB_C[4]
Video Output Data. These signals represent the 8 MSBs
of B/Cb/C video data. For RGB mode they are blue data
bits, for YUV444 mode they are Cb (Chroma) data bits,
for Y/C mode they are multiplexed Cb/Cr (Chroma) data
bits and for BT.656 mode they are unused.
O
J23
VOUT[0]_B_CB_C[5]
Video Output Data. These signals represent the 8 MSBs
of B/Cb/C video data. For RGB mode they are blue data
bits, for YUV444 mode they are Cb (Chroma) data bits,
for Y/C mode they are multiplexed Cb/Cr (Chroma) data
bits and for BT.656 mode they are unused.
O
H23
VOUT[0]_B_CB_C[6]
Video Output Data. These signals represent the 8 MSBs
of B/Cb/C video data. For RGB mode they are blue data
bits, for YUV444 mode they are Cb (Chroma) data bits,
for Y/C mode they are multiplexed Cb/Cr (Chroma) data
bits and for BT.656 mode they are unused.
O
J24
VOUT[0]_B_CB_C[7]
Video Output Data. These signals represent the 8 MSBs
of B/Cb/C video data. For RGB mode they are blue data
bits, for YUV444 mode they are Cb (Chroma) data bits,
for Y/C mode they are multiplexed Cb/Cr (Chroma) data
bits and for BT.656 mode they are unused.
O
E24
VOUT[0]_B_CB_C[8]
Video Output Data. These signals represent the 8 MSBs
of B/Cb/C video data. For RGB mode they are blue data
bits, for YUV444 mode they are Cb (Chroma) data bits,
for Y/C mode they are multiplexed Cb/Cr (Chroma) data
bits and for BT.656 mode they are unused.
O
D24
VOUT[0]_B_CB_C[9]
Video Output Data. These signals represent the 8 MSBs
of B/Cb/C video data. For RGB mode they are blue data
bits, for YUV444 mode they are Cb (Chroma) data bits,
for Y/C mode they are multiplexed Cb/Cr (Chroma) data
bits and for BT.656 mode they are unused.
O
C24
VOUT[0]_CLK
Video Output Clock output
O
K22
VOUT[0]_FLD
Video Output Field ID output. This is the discrete field
O
identification output. This signal is not used for embedded
sync modes.
B3, C20
VOUT[0]_G_Y_YC[2]
Video Output Data. These signals represent the 8 MSBs
of G/Y/YC video data. For RGB mode they are green
data bits, for YUV444 mode they are Y data bits, for Y/C
mode they are Y (Luma) data bits and for BT.656 mode
they are multiplexed Y/Cb/Cr (Luma and Chroma) data
bits.
C25
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Table 3-57. Video Output 0 (Digital) Terminal Functions (continued)
SIGNAL NAME [1]
DESCRIPTION [2]
TYPE [3]
AAR BALL [4]
VOUT[0]_G_Y_YC[3]
Video Output Data. These signals represent the 8 MSBs
of G/Y/YC video data. For RGB mode they are green
data bits, for YUV444 mode they are Y data bits, for Y/C
mode they are Y (Luma) data bits and for BT.656 mode
they are multiplexed Y/Cb/Cr (Luma and Chroma) data
bits.
O
C26
VOUT[0]_G_Y_YC[4]
Video Output Data. These signals represent the 8 MSBs
of G/Y/YC video data. For RGB mode they are green
data bits, for YUV444 mode they are Y data bits, for Y/C
mode they are Y (Luma) data bits and for BT.656 mode
they are multiplexed Y/Cb/Cr (Luma and Chroma) data
bits.
O
E26
VOUT[0]_G_Y_YC[5]
Video Output Data. These signals represent the 8 MSBs
of G/Y/YC video data. For RGB mode they are green
data bits, for YUV444 mode they are Y data bits, for Y/C
mode they are Y (Luma) data bits and for BT.656 mode
they are multiplexed Y/Cb/Cr (Luma and Chroma) data
bits.
O
B26
VOUT[0]_G_Y_YC[6]
Video Output Data. These signals represent the 8 MSBs
of G/Y/YC video data. For RGB mode they are green
data bits, for YUV444 mode they are Y data bits, for Y/C
mode they are Y (Luma) data bits and for BT.656 mode
they are multiplexed Y/Cb/Cr (Luma and Chroma) data
bits.
O
A26
VOUT[0]_G_Y_YC[7]
Video Output Data. These signals represent the 8 MSBs
of G/Y/YC video data. For RGB mode they are green
data bits, for YUV444 mode they are Y data bits, for Y/C
mode they are Y (Luma) data bits and for BT.656 mode
they are multiplexed Y/Cb/Cr (Luma and Chroma) data
bits.
O
B25
VOUT[0]_G_Y_YC[8]
Video Output Data. These signals represent the 8 MSBs
of G/Y/YC video data. For RGB mode they are green
data bits, for YUV444 mode they are Y data bits, for Y/C
mode they are Y (Luma) data bits and for BT.656 mode
they are multiplexed Y/Cb/Cr (Luma and Chroma) data
bits.
O
B27
VOUT[0]_G_Y_YC[9]
Video Output Data. These signals represent the 8 MSBs
of G/Y/YC video data. For RGB mode they are green
data bits, for YUV444 mode they are Y data bits, for Y/C
mode they are Y (Luma) data bits and for BT.656 mode
they are multiplexed Y/Cb/Cr (Luma and Chroma) data
bits.
O
A27
VOUT[0]_HSYNC
Video Output Horizontal Sync output. This is the discrete
horizontal synchronization output. This signal is not used
for embedded sync modes.
O
F21
VOUT[0]_R_CR[2]
Video Output Data. These signals represent the 8 MSBs O
of R/Cr video data. For RGB mode they are red data bits,
for YUV444 mode they are Cr (Chroma) data bits, for Y/C
mode and BT.656 modes they are unused.
C28
VOUT[0]_R_CR[3]
Video Output Data. These signals represent the 8 MSBs O
of R/Cr video data. For RGB mode they are red data bits,
for YUV444 mode they are Cr (Chroma) data bits, for Y/C
mode and BT.656 modes they are unused.
B28
VOUT[0]_R_CR[4]
Video Output Data. These signals represent the 8 MSBs O
of R/Cr video data. For RGB mode they are red data bits,
for YUV444 mode they are Cr (Chroma) data bits, for Y/C
mode and BT.656 modes they are unused.
B29
VOUT[0]_R_CR[5]
Video Output Data. These signals represent the 8 MSBs O
of R/Cr video data. For RGB mode they are red data bits,
for YUV444 mode they are Cr (Chroma) data bits, for Y/C
mode and BT.656 modes they are unused.
A29
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Table 3-57. Video Output 0 (Digital) Terminal Functions (continued)
SIGNAL NAME [1]
DESCRIPTION [2]
TYPE [3]
AAR BALL [4]
VOUT[0]_R_CR[6]
Video Output Data. These signals represent the 8 MSBs O
of R/Cr video data. For RGB mode they are red data bits,
for YUV444 mode they are Cr (Chroma) data bits, for Y/C
mode and BT.656 modes they are unused.
C30
VOUT[0]_R_CR[7]
Video Output Data. These signals represent the 8 MSBs O
of R/Cr video data. For RGB mode they are red data bits,
for YUV444 mode they are Cr (Chroma) data bits, for Y/C
mode and BT.656 modes they are unused.
B30
VOUT[0]_R_CR[8]
Video Output Data. These signals represent the 8 MSBs O
of R/Cr video data. For RGB mode they are red data bits,
for YUV444 mode they are Cr (Chroma) data bits, for Y/C
mode and BT.656 modes they are unused.
A30
VOUT[0]_R_CR[9]
Video Output Data. These signals represent the 8 MSBs O
of R/Cr video data. For RGB mode they are red data bits,
for YUV444 mode they are Cr (Chroma) data bits, for Y/C
mode and BT.656 modes they are unused.
B31
VOUT[0]_VSYNC
Video Output Vertical Sync output. This is the discrete
O
vertical synchronization output. This signal is not used for
embedded sync modes.
E20
3.3.28.2 Video Output 1 (Digital)
Table 3-58. Video Output 1 (Digital) Terminal Functions
SIGNAL NAME [1]
DESCRIPTION [2]
TYPE [3]
AAR BALL [4]
VOUT[1]_AVID
Video Output Active Video output. This is the discrete
active video indicator output. This signal is not used for
embedded sync modes.
O
F1
VOUT[1]_B_CB_C[0]
Video Output Data. These signals represent the 2 LSBs
O
of B/Cb/C video data for 10-bit, 20-bit, and 30-bit video
modes (VOUT[1] only). For RGB mode they are blue data
bits, for YUV444 mode they are Cb (Chroma) data bits,
for Y/C mode they are multiplexed Cb/Cr (Chroma) data
bits and for BT.656 mode they are unused. These signals
are not used in 16/24-bit modes.
H9
VOUT[1]_B_CB_C[1]
Video Output Data. These signals represent the 2 LSBs
O
of B/Cb/C video data for 10-bit, 20-bit, and 30-bit video
modes (VOUT[1] only). For RGB mode they are blue data
bits, for YUV444 mode they are Cb (Chroma) data bits,
for Y/C mode they are multiplexed Cb/Cr (Chroma) data
bits and for BT.656 mode they are unused. These signals
are not used in 16/24-bit modes.
D5
VOUT[1]_B_CB_C[2]
Video Output Data. These signals represent the 8 MSBs
of B/Cb/C video data. For RGB mode they are blue data
bits, for YUV444 mode they are Cb (Chroma) data bits,
for Y/C mode they are multiplexed Cb/Cr (Chroma) data
bits and for BT.656 mode they are unused.
O
M8
VOUT[1]_B_CB_C[3]
Video Output Data. These signals represent the 8 MSBs
of B/Cb/C video data. For RGB mode they are blue data
bits, for YUV444 mode they are Cb (Chroma) data bits,
for Y/C mode they are multiplexed Cb/Cr (Chroma) data
bits and for BT.656 mode they are unused.
O
F2
VOUT[1]_B_CB_C[4]
Video Output Data. These signals represent the 8 MSBs
of B/Cb/C video data. For RGB mode they are blue data
bits, for YUV444 mode they are Cb (Chroma) data bits,
for Y/C mode they are multiplexed Cb/Cr (Chroma) data
bits and for BT.656 mode they are unused.
O
F3
VOUT[1]_B_CB_C[5]
Video Output Data. These signals represent the 8 MSBs
of B/Cb/C video data. For RGB mode they are blue data
bits, for YUV444 mode they are Cb (Chroma) data bits,
for Y/C mode they are multiplexed Cb/Cr (Chroma) data
bits and for BT.656 mode they are unused.
O
G1
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Table 3-58. Video Output 1 (Digital) Terminal Functions (continued)
SIGNAL NAME [1]
DESCRIPTION [2]
TYPE [3]
AAR BALL [4]
VOUT[1]_B_CB_C[6]
Video Output Data. These signals represent the 8 MSBs
of B/Cb/C video data. For RGB mode they are blue data
bits, for YUV444 mode they are Cb (Chroma) data bits,
for Y/C mode they are multiplexed Cb/Cr (Chroma) data
bits and for BT.656 mode they are unused.
O
G2
VOUT[1]_B_CB_C[7]
Video Output Data. These signals represent the 8 MSBs
of B/Cb/C video data. For RGB mode they are blue data
bits, for YUV444 mode they are Cb (Chroma) data bits,
for Y/C mode they are multiplexed Cb/Cr (Chroma) data
bits and for BT.656 mode they are unused.
O
H3
VOUT[1]_B_CB_C[8]
Video Output Data. These signals represent the 8 MSBs
of B/Cb/C video data. For RGB mode they are blue data
bits, for YUV444 mode they are Cb (Chroma) data bits,
for Y/C mode they are multiplexed Cb/Cr (Chroma) data
bits and for BT.656 mode they are unused.
O
G3
VOUT[1]_B_CB_C[9]
Video Output Data. These signals represent the 8 MSBs
of B/Cb/C video data. For RGB mode they are blue data
bits, for YUV444 mode they are Cb (Chroma) data bits,
for Y/C mode they are multiplexed Cb/Cr (Chroma) data
bits and for BT.656 mode they are unused.
O
H5
VOUT[1]_CLK
Video Output Clock output
O
D3
VOUT[1]_FLD
Video Output Field ID output. This is the discrete field
O
identification output. This signal is not used for embedded
sync modes.
J10
VOUT[1]_G_Y_YC[0]
Video Output Data. These signals represent the 2 LSBs
of G/Y/YC video data for 10-bit, 20-bit, and 30-bit video
modes (VOUT[1] only). For RGB mode they are green
data bits, for YUV444 mode they are Y data bits, for Y/C
mode they are Y (Luma) data bits and for BT.656 mode
they are multiplexed Y/Cb/Cr (Luma and Chroma) data
bits. These signals are not used in 8/16/24-bit modes.
O
B2
VOUT[1]_G_Y_YC[1]
Video Output Data. These signals represent the 2 LSBs
of G/Y/YC video data for 10-bit, 20-bit, and 30-bit video
modes (VOUT[1] only). For RGB mode they are green
data bits, for YUV444 mode they are Y data bits, for Y/C
mode they are Y (Luma) data bits and for BT.656 mode
they are multiplexed Y/Cb/Cr (Luma and Chroma) data
bits. These signals are not used in 8/16/24-bit modes.
O
A2
VOUT[1]_G_Y_YC[2]
Video Output Data. These signals represent the 8 MSBs
of G/Y/YC video data. For RGB mode they are green
data bits, for YUV444 mode they are Y data bits, for Y/C
mode they are Y (Luma) data bits and for BT.656 mode
they are multiplexed Y/Cb/Cr (Luma and Chroma) data
bits.
O
L2
VOUT[1]_G_Y_YC[3]
Video Output Data. These signals represent the 8 MSBs
of G/Y/YC video data. For RGB mode they are green
data bits, for YUV444 mode they are Y data bits, for Y/C
mode they are Y (Luma) data bits and for BT.656 mode
they are multiplexed Y/Cb/Cr (Luma and Chroma) data
bits.
O
H6
VOUT[1]_G_Y_YC[4]
Video Output Data. These signals represent the 8 MSBs
of G/Y/YC video data. For RGB mode they are green
data bits, for YUV444 mode they are Y data bits, for Y/C
mode they are Y (Luma) data bits and for BT.656 mode
they are multiplexed Y/Cb/Cr (Luma and Chroma) data
bits.
O
J8
VOUT[1]_G_Y_YC[5]
Video Output Data. These signals represent the 8 MSBs
of G/Y/YC video data. For RGB mode they are green
data bits, for YUV444 mode they are Y data bits, for Y/C
mode they are Y (Luma) data bits and for BT.656 mode
they are multiplexed Y/Cb/Cr (Luma and Chroma) data
bits.
O
J1
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Table 3-58. Video Output 1 (Digital) Terminal Functions (continued)
SIGNAL NAME [1]
DESCRIPTION [2]
TYPE [3]
AAR BALL [4]
VOUT[1]_G_Y_YC[6]
Video Output Data. These signals represent the 8 MSBs
of G/Y/YC video data. For RGB mode they are green
data bits, for YUV444 mode they are Y data bits, for Y/C
mode they are Y (Luma) data bits and for BT.656 mode
they are multiplexed Y/Cb/Cr (Luma and Chroma) data
bits.
O
H4
VOUT[1]_G_Y_YC[7]
Video Output Data. These signals represent the 8 MSBs
of G/Y/YC video data. For RGB mode they are green
data bits, for YUV444 mode they are Y data bits, for Y/C
mode they are Y (Luma) data bits and for BT.656 mode
they are multiplexed Y/Cb/Cr (Luma and Chroma) data
bits.
O
J9
VOUT[1]_G_Y_YC[8]
Video Output Data. These signals represent the 8 MSBs
of G/Y/YC video data. For RGB mode they are green
data bits, for YUV444 mode they are Y data bits, for Y/C
mode they are Y (Luma) data bits and for BT.656 mode
they are multiplexed Y/Cb/Cr (Luma and Chroma) data
bits.
O
L3
VOUT[1]_G_Y_YC[9]
Video Output Data. These signals represent the 8 MSBs
of G/Y/YC video data. For RGB mode they are green
data bits, for YUV444 mode they are Y data bits, for Y/C
mode they are Y (Luma) data bits and for BT.656 mode
they are multiplexed Y/Cb/Cr (Luma and Chroma) data
bits.
O
K1
VOUT[1]_HSYNC
Video Output Horizontal Sync output. This is the discrete
horizontal synchronization output. This signal is not used
for embedded sync modes.
O
E2
VOUT[1]_R_CR[0]
Video Output Data. These signals represent the 2 LSBs
of R/Cr video data for 30-bit video modes. For RGB
mode they are red data bits, for YUV444 mode they are
Cr (Chroma) data bits, for Y/C mode and BT.656 modes
they are unused. These signals are not used in 24-bit
mode.
O
C2
VOUT[1]_R_CR[1]
Video Output Data. These signals represent the 2 LSBs
of R/Cr video data for 30-bit video modes. For RGB
mode they are red data bits, for YUV444 mode they are
Cr (Chroma) data bits, for Y/C mode and BT.656 modes
they are unused. These signals are not used in 24-bit
mode.
O
C1
VOUT[1]_R_CR[2]
Video Output Data. These signals represent the 8 MSBs O
of R/Cr video data. For RGB mode they are red data bits,
for YUV444 mode they are Cr (Chroma) data bits, for Y/C
mode and BT.656 modes they are unused.
L6
VOUT[1]_R_CR[3]
Video Output Data. These signals represent the 8 MSBs O
of R/Cr video data. For RGB mode they are red data bits,
for YUV444 mode they are Cr (Chroma) data bits, for Y/C
mode and BT.656 modes they are unused.
L4
VOUT[1]_R_CR[4]
Video Output Data. These signals represent the 8 MSBs O
of R/Cr video data. For RGB mode they are red data bits,
for YUV444 mode they are Cr (Chroma) data bits, for Y/C
mode and BT.656 modes they are unused.
H2
VOUT[1]_R_CR[5]
Video Output Data. These signals represent the 8 MSBs O
of R/Cr video data. For RGB mode they are red data bits,
for YUV444 mode they are Cr (Chroma) data bits, for Y/C
mode and BT.656 modes they are unused.
M11
VOUT[1]_R_CR[6]
Video Output Data. These signals represent the 8 MSBs O
of R/Cr video data. For RGB mode they are red data bits,
for YUV444 mode they are Cr (Chroma) data bits, for Y/C
mode and BT.656 modes they are unused.
L12
VOUT[1]_R_CR[7]
Video Output Data. These signals represent the 8 MSBs O
of R/Cr video data. For RGB mode they are red data bits,
for YUV444 mode they are Cr (Chroma) data bits, for Y/C
mode and BT.656 modes they are unused.
M10
108
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Table 3-58. Video Output 1 (Digital) Terminal Functions (continued)
SIGNAL NAME [1]
DESCRIPTION [2]
TYPE [3]
AAR BALL [4]
VOUT[1]_R_CR[8]
Video Output Data. These signals represent the 8 MSBs O
of R/Cr video data. For RGB mode they are red data bits,
for YUV444 mode they are Cr (Chroma) data bits, for Y/C
mode and BT.656 modes they are unused.
J2
VOUT[1]_R_CR[9]
Video Output Data. These signals represent the 8 MSBs O
of R/Cr video data. For RGB mode they are red data bits,
for YUV444 mode they are Cr (Chroma) data bits, for Y/C
mode and BT.656 modes they are unused.
K2
VOUT[1]_VSYNC
Video Output Vertical Sync output. This is the discrete
O
vertical synchronization output. This signal is not used for
embedded sync modes.
F5
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4 Device Configurations
4.1
Control Module Registers
4.2
Boot Modes
The state of the device after boot is determined by sampling the input states of the BTMODE[15:0] pins
when device reset (POR or RESET) is de-asserted. The sampled values are latched into the
CONTROL_STATUS register, which is part of the Control Module. The BTMODE[15:11] values determine
the following system boot settings:
• RSTOUT_WD_OUT Control
• GPMC CS0 Default Data Bus Width, Wait Enable, and Address/Data Multiplexing
For additional details on BTMODE[15:11] pin functions, see Table 3-13, Boot Configuration Terminal
Functions.
The BTMODE[4:0] values determine the boot mode order according to Table 4-1, Boot Mode Order. The
1st boot mode listed for each BTMODE[4:0] configuration is executed as the primary boot mode. If the
primary boot mode fails, the 2nd, 3rd, and 4th boot modes are executed in that order until a successful
boot is completed.
The BTMODE[6:5] pins are RESERVED and should be pulled down as indicated in Table 3-13, Boot
Configuration Terminal Functions.
When the EMAC bootmode is selected (see Table 4-1), the sampled value from BTMODE[9:8] pins are
used to determine the Ethernet PHY Mode selection (see Table 4-7) and the BTMODE[7] pin is used for
RGMII Internal Delay selection (see Table 4-8).
When the XIP (MUX0), XIP (MUX1), XIP w/ WAiT (MUX0) or XIP w/ WAiT (MUX1) bootmode is selected
(see Table 4-1), the sampled value from BTMODE[10] pin is used to select between GPMC pin muxing
options shown in Table 4-2, XIP (on GPMC) Boot Options [Muxed or Non-Muxed].
For more detailed information on booting the device, including which pins are used for each boot mode,
see the ROM Code Memory and Peripheral Booting chapter in the device-specific Technical Reference
Manual.
110
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Table 4-1. Boot Mode Order
BTMODE[4:0]
1st
2nd
3rd
4th
00000
RESERVED
RESERVED
RESERVED
RESERVED
00001
UART
XIP w/WAIT (MUX0) (1) (2)
MMC
SPI
00010
UART
SPI
NAND
NANDI2C
00011
UART
SPI
XIP (MUX0) (1) (2)
MMC
SPI
NAND
NANDI2C
RESERVED
00100
00101
RESERVED
RESERVED
RESERVED
00110
RESERVED
RESERVED
RESERVED
RESERVED
00111
EMAC (3)
MMC
SPI
XIP (MUX1) (1) (2)
01000
PCIE_32 (4)
RESERVED
RESERVED
RESERVED
01001
PCIE_64
(4)
RESERVED
RESERVED
RESERVED
01010
RESERVED
RESERVED
RESERVED
RESERVED
01011
RESERVED
RESERVED
RESERVED
RESERVED
01100
RESERVED
RESERVED
RESERVED
RESERVED
01101
RESERVED
RESERVED
RESERVED
RESERVED
01110
RESERVED
RESERVED
RESERVED
RESERVED
01111
Fast XIP (MUX0) (1)
UART
EMAC (3)
PCIE_64 (4)
(3)
10000
(2)
(3)
(4)
XIP (MUX1)
(1) (2)
UART
EMAC
10001
XIP w/WAIT (MUX1) (1) (2)
UART
EMAC (3)
MMC
10010
NAND
NANDI2C
SPI
UART
10011
NAND
NANDI2C
MMC
UART
10100
NAND
NANDI2C
SPI
EMAC (3)
10101
NANDI2C
MMC
EMAC (3)
UART
10110
SPI
MMC
UART
EMAC (3)
10111
MMC
SPI
UART
MMC
EMAC (3)
(4)
RESERVED
11000
SPI
MMC
PCIE_32
11001
SPI
MMC
PCIE_64 (4)
RESERVED
MMC
11010
(1)
EMAC
(3)
XIP (MUX0)
(1) (2)
UART
SPI
11011
XIP w/WAIT (MUX0) (1) (2)
UART
SPI
MMC
11100
RESERVED
RESERVED
RESERVED
RESERVED
11101
RESERVED
RESERVED
RESERVED
RESERVED
11110
RESERVED
RESERVED
RESERVED
RESERVED
11111
Fast XIP (MUX0) (1)
EMAC (3)
UART
PCIE_32 (4)
GPMC CS0 eXecute In Place (XIP) boot for NOR/OneNAND/ROM. MUX0/1 refers to the multiplexing option for the GPMC_A[12:0] pins.
For more detailed information on booting the device, including which pins are used for each boot mode, see the ROM Code Memory
and Peripheral Booting chapter in the device-specific Technical Reference Manual.
When the XIP (MUX0), XIP (MUX1), XIP w/ WAiT (MUX0) or XIP w/ WAiT (MUX1) bootmode is selected, the sampled value from
BTMODE[10] pin is used to select between GPMC pin configuration options shown in Table 4-2, XIP (on GPMC) Boot Options.
When the EMAC bootmode is selected, the sampled value from BTMODE[9:8] pins are used to determine the Ethernet PHY Mode
Selection (see Table 4-7).
When the PCIe bootmode is selected (PCIE_32 or PCI_64), the sampled value from BTMODE[15:12] pins are used to determine the
addressing options. For more detailed information on the PCIe addressing options, see the ROM Code Memory and Peripheral Booting
chapter in the device-specific Technical Reference Manual.
4.2.1
XIP (NOR) Boot Options
Table 4-2 shows the XIP (NOR) boot mode GPMC pin configuration options (Option A: BTMODE[10] = 0
and Option B: BTMODE[10] = 1). For Option B, the pull state on select pins is reconfigured to IPD and
remains IPD after boot until the user software reconfigures it. In Table 4-2, GPMC_A[1:12] are configured
only for Non-Muxed NOR flash. In the case of Muxed NOR Flash, GPMC_D[15:0] act as both address and
data lines so configuration of GPMC_A[1:12] in XIP_Mux0 mode and XIP_Mux1 mode doesn't apply for a
Muxed NOR flash and those pins are not configured by Boot ROM.
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Table 4-2. XIP (on GPMC) Boot Options
CONTROLLED I/O FUNCTION DURING XIP (NOR) BOOT
SIGNAL NAME
PIN NO.
OTHER CONDITIONS
BTMODE[10] = 0 [OPTION A]
PIN FUNCTION
GPMC_CS[0]/*
GPMC_ADV_ALE/*
AC9
AA10
BTMODE[14:13] = 01b or 10b (Mux)
BTMODE[10] = 1 [OPTION B]
PULL
STATE
PIN FUNCTION
PULL
STATE
GPMC_CS[0]
IPU
GPMC_CS[0]
IPU
GPMC_ADV_ALE
IPU
GPMC_ADV_ALE
IPU
BTMODE[14:13] = 00b (Non-Mux)
Default
GPMC_OE_RE
Y8
GPMC_OE_RE
IPU
GPMC_OE_RE
IPU
GPMC_BE[0]_CLE/GPMC_A[25]/*
Y3
GPMC_BE[0]_CLE
IPD
Default
IPD
GPMC_BE[1]/GPMC_A[24]/*
Y11
Default
IPD
Default
IPD
GPMC_WE
Y5
GPMC_WE
IPU
GPMC_WE
IPU
GPMC_WAIT[0]
IPU
GPMC_WAIT[0]
W8
GPMC_WAIT[0]/GPMC_A[26]/*
GPMC_CLK/*
GPMC_D[15:0]/*
*/GPMC_A[27]/GPMC_A[26]/GPMC_A[0]/*
BTMODE[15] = 1b (WAIT Used/Enabled)
BTMODE[15] = 0b (WAIT Not
Used/Disabled)
AB9
P2, R1, R2, R3, R4, R6, T8, T1,
T2, T3, T5, W9, U2, W3, W4,
W6
AK3
BTMODE[12] = 0b (8-bit Mode)
IPU
Default
IPD (1)
GPMC_CLK
IPU
Default
IPU
GPMC_D[15:0]
Off
GPMC_D[15:0]
Off
GPMC_A[0]
IPD
GPMC_A[0]
IPD
BTMODE[12] = 1b (16-bit Mode)
Default
*/GPMC_A[1:12]/*
AK4, AJ4, AL5, AK5, AJ6, AL6,
AK6, AJ7, AK7, AE4, AK8, AJ8
XIP_MUX0 Mode
GPMC_A[1:12]
IPD
GPMC_A[1:12]
XIP_MUX1 Mode
Default
IPD
Default
IPD
*/GPMC_A[1:12]/* (M1)
AD1, AC8, AC5, AC4, A2, B2,
C1, C2, D5, H9, J10, B3
XIP_MUX0 Mode
Default
Default
Default
Default
XIP_MUX1 Mode
GPMC_A[1:12]
Default
GPMC_A[1:12]
Default
*/GPMC_A[13:15]/* (M0)
AH8, AG8, AF8
*/GPMC_A[0]/* (M1)
*/GPMC_A[13]/* (M1)
*/GPMC_A[14]/* (M1)
*/GPMC_A[15]/* (M1)
M8
BTMODE[12] = 0b (8-bit Mode)
IPD
Default
IPD
Default
IPD
Default
IPU
Default
IPU
Default
IPU
Default
BTMODE[12] = 1b (16-bit Mode)
L2
BTMODE[14:13] = 01b or 10b (Mux)
L4
BTMODE[14:13] = 01b or 10b (Mux)
IPU
IPD (1)
BTMODE[14:13] = 00b (Non-Mux)
Default
IPU
Default
IPU
IPD (1)
BTMODE[14:13] = 00b (Non-Mux)
L6
Default
IPD
Default
GPMC_A[16:19]/*
M1, M2, M3, M5
Default
IPD
Default
IPD
GPMC_A[20] (M0)
N9
Default
IPU
Default
IPD (1)
GPMC_A[21] (M0)
N1
Default
IPD
Default
IPD
GPMC_A[22] (M0)
N2
Default
IPU
Default
IPD (1)
GPMC_A[23] (M0)
R8
Default
IPD
Default
IPD
(1)
112
IPD
After initial power-up the internal pullup (IPU) will be at its default configuration of IPU. During the boot ROM execution, the pull state is reconfigured to IPD and it remains IPD after boot
until the user software reconfigures it.
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Table 4-2. XIP (on GPMC) Boot Options (continued)
CONTROLLED I/O FUNCTION DURING XIP (NOR) BOOT
SIGNAL NAME
PIN NO.
OTHER CONDITIONS
BTMODE[10] = 0 [OPTION A]
PIN FUNCTION
BTMODE[10] = 1 [OPTION B]
PULL
STATE
PIN FUNCTION
PULL
STATE
*/GPMC_A[24]/GPMC_A[20]/*
AE3
Default
IPU
Default
IPD (1)
*/GPMC_A[25]/GPMC_A[21]/*
AE2
Default
IPU
Default
IPD (1)
*/GPMC_A[26]/GPMC_A[22]/*
AE1
Default
IPU
Default
IPD (1)
*/GPMC_A[27]/GPMC_A[23]/*
AD2
Default
IPU
Default
IPU
GPMC_A[24] (M1)
AC3
Default
IPU
Default
IPU
GPMC_A[25] (M1)
AA12
Default
IPU
Default
IPU
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NAND Flash Boot
Table 4-3 lists the device pins that are configured by the ROM for the NAND Flash boot mode.
NOTE: Table 4-3 lists the configuration of the GPMC_CLK pin (pin mux and pull state) in NAND
bootmodes.
The NAND flash memory is not XIP and requires shadowing before the code can be executed.
Table 4-3. Pins Used in NAND FLASH Bootmode
(1)
4.2.3
SIGNAL NAME
PIN NO.
TYPE
GPMC_CS[0]/*
AC9
O
GPMC_ADV_ALE/*
AA10
O
GPMC_OE_RE
Y8
O
GPMC_BE[0]_CLE/GPMC_A[25]/*
Y3
O
GPMC_BE[1]/GPMC_A[24]/*
Y11
O
GPMC_WE
Y5
O
GPMC_WAIT[0]/GPMC_A[26]/* (1)
W8
I
GPMC_CLK/*
AB9
I/O
GPMC_D[15:0]/*
P2, R1, R2, R3,
R4, R6, T8, T1, T2,
T3, T5, W9, U2,
W3, W4, W6
I/O
OTHER
CONDITIONS
BTMODE[12] = 0b
(8-bit Mode)
BTMODE[12] = 1b
(16-bit Mode)
BTMODE[14:13] =
00b (GPMC CS0
not muxed)
BTMODE[15] = 0b
(wait disabled)
GPMC_CLK/* is not configured in BTMODE[10] = 1 [OPTION B]
NAND I2C Boot (I2C EEPROM)
Table 4-4 lists the device pins that are configured by the ROM for the NAND I2C boot mode.
Table 4-4. Pins Used in NAND I2C Bootmode
SIGNAL NAME
4.2.4
PIN NO.
TYPE
I2C[0]_SCL
T27
I/O
I2C[0]_SDA
T24
I/O
MMC/SD Cards Boot
Table 4-5 lists the device pins that are configured by the ROM for the MMC/SD boot mode.
Table 4-5. Pins Used in MMC/SD Bootmode
SIGNAL NAME
114
PIN NO.
TYPE
SD1_CLK
W30
I/O
SD1_CMD/GP0[0] [MUX0]
Y29
I/O
SD1_DAT[0]
W31
I/O
SD1_DAT[1]_SDIRQ
AA30
I/O
SD_DAT[2]_SDRW
U29
I/O
SD1_DAT[3]
Y27
I/O
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SPI Boot
Table 4-6 lists the device pins that are configured by the ROM for the SPI boot mode.
Table 4-6. Pins Used in SPI Bootmode
SIGNAL NAME
4.2.6
PIN NO.
TYPE
SPI[0]_SCS[0]
G29
I/O
SPI[0]_D[0] (MISO)
J28
I/O
SPI[0]_D[1] (MOSI)
J27
I/O
SPI[0]_SCLK
N24
I/O
Ethernet PHY Mode Selection
When the EMAC bootmode is selected, via the BTMODE[4:0] pins (see Table 4-1), Table 4-7 shows the
sampled value of BTMODE[9:8] pins and the Ethernet PHY Mode selection.
Table 4-9 shows the signal names (pin functions) and the associated pin numbers selected in each
particular EMAC mode.
Table 4-7. EMAC PHY Mode Selection
BTMODE[9:8]
ETHERNET PHY MODE
SELECTION
00b
MII/GMII
01b
RMII
10b
RGMII
11b
RESERVED
Table 4-8. RGMII Internal Delay Selection
BTMODE[7]
RGMII INTERNAL DELAY
SELECTION
0b
Internal Delay Enabled
1b
Internal Delay Disabled
Table 4-9. Pins Used in EMAC[0] MII/GMII, RGMII, and RMII Boot Modes
PIN NO.
AG1
SIGNAL NAMES
MII/GMII
TYPE
DEFAULT
RGMII
TYPE
DEFAULT
RMII
TYPE
EMAC_RMREFCLK
Output
only
AH1
EMAC[0]_MCOL
I
EMAC[0]_RGRXCTL
I
EMAC[0]_RMRXD[0]
I
AH2
EMAC[0]_MCRS
I
EMAC[0]_RGRXD[2]
I
EMAC[0]_RMRXD[1]
I
AL6
EMAC[0]_GMTCLK
O
DEFAULT
AK1
EMAC[0]_MRCLK
I
EMAC[0]_RGTXC
O
EMAC[0]_RMCRSDV
I
AK2
EMAC[0]_MRXD[0]
I
EMAC[0]_RGTXD[0]
O
EMAC[0]_RMTXD[0]
O
AL2
EMAC[0]_MRXD[1]
I
EMAC[0]_RGRXD[0]
I
EMAC[0]_RMTXD[1]
O
I
EMAC[0]_RMTXEN
O
DEFAULT
AL3
EMAC[0]_MRXD[2]
I
EMAC[0]_RGRXD[1]
AK3
EMAC[0]_MRXD[3]
I
DEFAULT
AK4
EMAC[0]_MRXD[4]
I
EMAC[0]_RGRXD[3]
I
DEFAULT
AJ4
EMAC[0]_MRXD[5]
I
EMAC[0]_RGTXD[3]
O
DEFAULT
AL5
EMAC[0]_MRXD[6]
I
EMAC[0]_RGTXD[2]
O
DEFAULT
DEFAULT
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Table 4-9. Pins Used in EMAC[0] MII/GMII, RGMII, and RMII Boot Modes (continued)
SIGNAL NAMES
PIN NO.
4.2.7
MII/GMII
TYPE
RGMII
TYPE
RMII
AK5
EMAC[0]_MRXD[7]
I
EMAC[0]_RGTXD[1]
O
DEFAULT
AJ6
EMAC[0]_MRXDV
I
DEFAULT
AJ2
EMAC[0]_MRXER
I
EMAC[0]_RGTXCTL
O
EMAC[0]_RMRXER
I
DEFAULT
TYPE
DEFAULT
AG4
EMAC[0]_MTCLK
I
EMAC[0]_RGRXC
AK6
EMAC[0]_MTXD[0]
O
DEFAULT
DEFAULT
AJ7
EMAC[0]_MTXD[1]
O
DEFAULT
DEFAULT
AK7
EMAC[0]_MTXD[2]
O
DEFAULT
DEFAULT
AE4
EMAC[0]_MTXD[3]
O
DEFAULT
DEFAULT
AK8
EMAC[0]_MTXD[4]
O
DEFAULT
DEFAULT
AJ8
EMAC[0]_MTXD[5]
O
DEFAULT
DEFAULT
I
AH8
EMAC[0]_MTXD[6]
O
DEFAULT
DEFAULT
AG8
EMAC[0]_MTXD[7]
O
DEFAULT
DEFAULT
AF8
EMAC[0]_MTXEN
O
DEFAULT
DEFAULT
AG2
MDCLK
O
MDCLK
O
MDCLK
O
AG3
MDIO
I/O
MDIO
I/O
MDIO
I/O
PCIe Bootmode (PCIE_32 and PCIE_64)
Table 4-10 lists the device pins that are configured by the ROM for the PCIe boot mode.
Table 4-10. Pins Used in PCIe Bootmode
SIGNAL NAME
4.2.8
PIN NO.
TYPE
PCIE_TXP0
L31
O
PCIE_TXN0
K31
O
PCIE_RXP0
K30
I
PCIE_RXN0
J30
I
SERDES_CLKP
H30
I
SERDES_CLKN
H31
I
UART Bootmode
Table 4-11 lists the device pins that are configured by the ROM for the UART boot mode.
Table 4-11. Pins Used in UART Bootmode
SIGNAL NAME
4.3
PIN NO.
TYPE
UART0_RXD
J26
I
UART0_TXD
E28
O
Pin Multiplexing Control
Device level pin multiplexing is controlled on a pin-by-pin basis by the MUXMODE bits of the PINCNTL1 –
PINCNTL270 registers in the Control Module.
Pin multiplexing selects which one of several peripheral pin functions controls the pin's I/O buffer output
data values. Table 4-12 shows the peripheral pin functions associated with each MUXMODE setting for all
multiplexed pins. The default pin multiplexing control for almost every pin is to select MUXMODE = 0x0, in
which case the pin's I/O buffer is 3-stated.
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In most cases, the input from each pin is routed to all of the peripherals that share the pin, regardless of
the MUXMODE setting. However, in some cases a constant "0" or "1" value is routed to the associated
peripheral when its peripheral function is not selected to control any output pin. For more details on the
De-Selected Input State (DSIS), see the columns of each Terminal Functions table (Section 3.3, Terminal
Functions).
Some peripheral pin functions can be routed to more than one device pin. These types of peripheral pin
functions are called Multimuxed and may have different Switching Characteristics and Timing
Requirements for each device pin option.
For more detailed information on the Pin Control 1 through Pin Control 270 (PINCNTLx) registers
breakout, see Figure 4-1 and Table 4-12.
Figure 4-1. PINCNTL1 – PINCNTL270 (PINCNTLx) Registers Breakout
31
24
23
20
RESERVED
RESERVED
R - 0000 0000
R - 0000
15
8
19
18
17
16
RSV
RSV
PLLTY
PESE
L
PLLU
DEN
R/W
7
0
RESERVED
MUXMODE[7:0]
R - 0000 0000
R/W - 0000 0000
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 4-12. PINCNTL1 – PINCNTL270 (PINCNTLx) Registers Bit Descriptions
Bit
31:20
Field
Description
RESERVED
Reserved. Read only, writes have no effect.
19
RSV
Reserved. This bit must always be written with the
reset (default) value.
18
RSV
Reserved. This field must always be written as "1".
17
PLLTYPSEL
16
PLLUDEN
0 = PU/PD enabled
1 = PU/PD disabled
15:8
RESERVED
Reserved. Read only, writes have no effect.
7:0
MUXMODE[7:0]
Pullup/Pulldown Type Selection bit
0 = Pulldown (PD) selected
1 = Pullup (PU) selected
Pullup/Pulldown Enable bit
Comments
For PINCNTLx register reset value
examples, see Table 4-13,
PNICNTLx Register Reset Value
Examples.
For the full register reset values of all
PINCNTLx registers.
MUXMODE Selection bits
These bits select the multiplexed mode pin function
settings. Values other than those are illegal.
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Table 4-13. PINCNTLx Register Reset Value Examples
HEX
ADDRESS
RANGE
PINCNTLx
REGISTER
NAME
Bits 31:24
Bits 23:20
Bit 19
Bit 18
Bit 17
Bit 16
Bits 15:8
Bits 7:0
REGISTER
RESET
VALUE
RESERVED
RESERVED
RESERVED
RXACTIVE
PLLTYPESEL
PLLUDEN
RESERVED
MUXMODE[7:0]
0x4814 0800
PINCNTL1
00h
0h
0
1
1
0
00h
00h
0x0006 0000
0x4814 0804
PINCNTL2
00h
0h
1
1
1
0
00h
00h
0x000E 0000
0x4814 0808
PINCNTL3
00h
0h
1
1
1
0
00h
00h
0x000E 0000
0x4814 0C34
PINCNTL270
00h
0h
1
1
0
0
00h
00h
0x000C 0000
…
118
Device Configurations
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4.4
SPRS872B – MAY 2013 – REVISED DECEMBER 2013
Handling Unused Pins
When device signal pins are unused in the system, they can be left unconnected unless otherwise noted
in the Terminal Functions tables (see Section 3.3). For unused input pins, the internal pull resistor should
be enabled, or an external pull resistor should be used, to prevent floating inputs. All supply pins must
always be connected to the correct voltage, even when their associated signal pins are unused.
4.5
4.5.1
DeBugging Considerations
Pullup/Pulldown Resistors
Proper board design should ensure that input pins to the device always be at a valid logic level and not
floating. This may be achieved via pullup/pulldown resistors. The device features internal pullup (IPU) and
internal pulldown (IPD) resistors on most pins to eliminate the need, unless otherwise noted, for external
pullup/pulldown resistors.
An external pullup/pulldown resistor needs to be used in the following situations:
• Boot Configuration Pins: If the pin is both routed out and 3-stated (not driven), an external
pullup/pulldown resistor is strongly recommended, even if the IPU/IPD matches the desired
value/state.
• Other Input Pins: If the IPU/IPD does not match the desired value/state, use an external
pullup/pulldown resistor to pull the signal to the opposite rail.
For the boot configuration pins (listed in Section 3.3, Boot Configuration Terminal Functions), if they are
both routed out and 3-stated (not driven), it is strongly recommended that an external pullup/pulldown
resistor be implemented. Although, internal pullup/pulldown resistors exist on these pins and they may
match the desired configuration value, providing external connectivity can help ensure that valid logic
levels are latched on these device boot configuration pins. In addition, applying external pullup/pulldown
resistors on the boot and configuration pins adds convenience to the user in debugging and flexibility in
switching operating modes.
Tips for choosing an external pullup/pulldown resistor:
• Consider the total amount of current that may pass through the pullup or pulldown resistor. Make sure
to include the leakage currents of all the devices connected to the net, as well as any internal pullup or
pulldown resistors.
• Decide a target value for the net. For a pulldown resistor, this should be below the lowest VIL level of
all inputs connected to the net. For a pullup resistor, this should be above the highest VIH level of all
inputs on the net. A reasonable choice would be to target the VOL or VOH levels for the logic family of
the limiting device; which, by definition, have margin to the VIL and VIH levels.
• Select a pullup/pulldown resistor with the largest possible value; but, which can still ensure that the net
will reach the target pulled value when maximum current from all devices on the net is flowing through
the resistor. The current to be considered includes leakage current plus, any other internal and
external pullup/pulldown resistors on the net.
• For bidirectional nets, there is an additional consideration which sets a lower limit on the resistance
value of the external resistor. Verify that the resistance is small enough that the weakest output buffer
can drive the net to the opposite logic level (including margin).
• Remember to include tolerances when selecting the resistor value.
• For pullup resistors, also remember to include tolerances on the DVDD rail.
For most systems, a 1-kΩ resistor can be used to oppose the IPU/IPD while meeting the above criteria.
Users should confirm this resistor value is correct for their specific application.
For most systems, a 20-kΩ resistor can be used to compliment the IPU/IPD on the boot and configuration
pins while meeting the above criteria. Users should confirm this resistor value is correct for their specific
application.
Device Configurations
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For most systems, a 20-kΩ resistor can also be used as an external PU/PD on the pins that have
IPUs/IPDs disabled and require an external PU/PD resistor while still meeting the above criteria. Users
should confirm this resistor value is correct for their specific application.
For more detailed information on input current (II), and the low-/high-level input voltages (VIL and VIH) for
the device, see Section 6.4, Electrical Characteristics Over Recommended Ranges of Supply Voltage and
Operating Temperature.
For the internal pullup/pulldown resistors for all device pins, see the peripheral/system-specific terminal
functions table.
120
Device Configurations
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SPRS872B – MAY 2013 – REVISED DECEMBER 2013
5 System Interconnect
The device’s various processors, subsystems, and peripherals are interconnected through a switch fabric
architecture. The switch fabric is composed of an L3 and L4 interconnect, a switched central resource
(SCR), and multiple bridges (for an overview, see Figure 5-1). Not all Initiators in the switch fabric are
connected to all Target peripherals. The supported initiator and target connections are designated by a "X"
in Table 5-1, Target/Initiator Connectivity.
EDMATC RD 0/1
EDMATC WR 0/1
ARM Cortex
A8
64b
128b
L3F
Initiators
L3F
Initiators
L3F
Initiators
L3F
Initiators
EDMATC RD 2/3
EDMATC WR 2/3
HDVICP2
HDVPSS (2 I/F)
ISS
PCIe
MEDIACTL
EMAC SW
SATA0
FD
DAP
JTAG
USB2.0 (2 I/F)
128b
1 I/F
8 I/F
64b
128b
4 I/F
2 I/F
32b
4 I/F
L3F/L3Mid
Interconnect
200 MHz (Note 1)
2 I/F
128b
DMM
1 I/F
128b
3 I/F
128b
64b
3 I/F
L3S Interconnect
100 MHz (Note 1)
10 I/F
32b
L3F
Targets
L3F
Targets
L3F
Targets
HDVICP2 SL2
PCIe
MEDIACTL
OCMC SRAM
ISS
MMCSD 2
HDVICP 2 CFG
EDMATC 0/1/2/3
EDMACC
DEBUGSS
DDR
32b
2 I/F
32b
L4F
Interconnect
200MHz
(Note 1)
2 I/F
32b
5 I/F
32b
L3S
Targets
MCASP 0/1 Data
GPMC
HDMI
USB
2 I/F
32b
L4S
Interconnect
100MHz
(Note1)
44 I/F
32b
L4F Targets
L4S Targets
EMAC SW
SATA0
UART 0/1/2
I2C 0/1/2/3
DMTimer 1/2/3/4/5/6/7/8
SPI 0/1/2/3
GPIO 0/1/2/3
McASP 0/1 CFG
MMCSD 0/1
ELM
RTC
WDT 0/1
Mailbox
Spinlock
HDVPSS
HDMIPHY
PLLSS
Control Module
PRCM
SmartReflex 0/1
DCAN 0/1
OCPWP
SYNCTIMER32K
Note 1: The frequencies specified are for 100% OPP.
Figure 5-1. System Interconnect
System Interconnect
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Table 5-1. L3 Master/Slave Connectivity
Imaging SS
X
USB2.0 CFG
L4 HS Periph Port 0
X
OCMC RAM
HDMI 1.3 Tx Audio
X
EDMA TPCC
McASP 0/1
X
EDMA TPTC0 - 3 CFG
PCIe Gen2 Slave
X
L3 Registers
GPMC
X
L4 Std Periph Port 1
Media Controller
X
L4 Std Periph Port 0
HDVICP2 Hst
X
L4 HS Periph Port 1
HDVICP2 SL2
ARM M1 (128-bit)
EDMA DMM ELLA
EDMA DMM Tiler/Lisa1
SLAVES
EDMA DMM Tiler/Lisa0
MASTERS
SD2
X
X
X
X
X
X
X
X
ARM M2 (64-bit)
X
HDVICP2 VDMA
X
HDVPSS Mstr0
X
HDVPSS Mstr1
X
X
X
X
X
X
X
SATA0
X
X
X
EMAC SW
X
X
USB2.0 DMA
X
X
USB2.0 Queue Mgr
X
X
PCIe Gen2
X
X
X
Media Controller
X
X
X
DeBug Access Port (DAP)
X
X
X
EDMA TPTC0 RD
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
EDMA TPTC0 WR
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
EDMA TPTC1 RD
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
EDMA TPTC1 WR
X
EDMA TPTC2 RD
X
EDMA TPTC2 WR
X
X
X
X
X
X
X
X
EDMA TPTC3 RD
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
EDMA TPTC3 WR
X
ISS
X
X
FACE DET I/F
X
X
122
System Interconnect
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The L4 interconnect is a non-blocking peripheral interconnect that provides low-latency access to a large
number of low-bandwidth, physically-dispersed target cores. The L4 can handle incoming traffic from up to
four initiators and can distribute those communication requests to and collect related responses from up to
63 targets.
The device provides two interfaces with L3 interconnect for high-speed and standard peripherals.
Table 5-2. L4 Peripheral Connectivity (1)
MASTERS
L4 PERIPHERALS
ARM Cortex-A8
M2 (64-bit)
EDMA TPTC0
EDMA TPTC1
EDMA TPTC2
EDMA TPTC3
PCIe
EMAC SW
Port0
Port1
Port0
Port1
Port0
Port1
SATA0
Port0
Port1
Port0
Port1
Port0
Port1
I2C0
Port0
Port1
Port0
Port1
Port0
Port1
I2C1
Port0
Port1
Port0
Port1
Port0
Port1
I2C2
Port0
Port1
Port0
Port1
Port0
Port1
I2C3
Port0
Port1
Port0
Port1
Port0
Port1
SPI0
Port0
Port1
Port0
Port1
Port0
Port1
SPI1
Port0
Port1
Port0
Port1
Port0
Port1
SPI2
Port0
Port1
Port0
Port1
Port0
Port1
SPI3
Port0
Port1
Port0
Port1
Port0
Port1
UART0
Port0
Port1
Port0
Port1
Port0
Port1
UART1
Port0
Port1
Port0
Port1
Port0
Port1
UART2
Port0
Port1
Port0
Port1
Port0
Port1
Timer1
Port0
Port1
Port0
Port1
Port0
Port1
Timer2
Port0
Port1
Port0
Port1
Port0
Port1
Timer3
Port0
Port1
Port0
Port1
Port0
Port1
Timer4
Port0
Port1
Port0
Port1
Port0
Port1
Timer5
Port0
Port1
Port0
Port1
Port0
Port1
Timer6
Port0
Port1
Port0
Port1
Port0
Port1
Timer7
Port0
Port1
Port0
Port1
Port0
Port1
Timer8
Port0
Port1
Port0
Port1
Port0
Port1
GPIO0
Port0
Port1
Port0
Port1
Port0
Port1
GPIO1
Port0
Port1
Port0
Port1
Port0
Port1
MMC/SD0/SDIO
Port0
Port1
Port0
Port1
Port0
Port1
MMC/SD1/SDIO
Port0
Port1
Port0
Port1
Port0
Port1
MMC/SD2/SDIO
Port0
Port1
Port0
Port1
Port0
Port1
WDT0
Port0
Port1
Port0
Port1
Port0
Port1
RTC
Port0
Port1
Port0
Port1
Port0
Port1
SmartReflex0
Port0
SmartReflex1
Port0
Mailbox
Port0
Spinlock
Port0
HDVPSS
Port0
Port1
Port0
Port1
Port0
Port1
PLLSS
Port0
Port1
Control/Top Regs (Control
Module)
Port0
Port1
PRCM
Port0
Port1
L4 Fast Peripherals Port 0/1
L4 Slow Peripherals Port 0/1
(1)
X, Port0, Port1 = Connection exists.
System Interconnect
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Table 5-2. L4 Peripheral Connectivity(1) (continued)
MASTERS
L4 PERIPHERALS
ARM Cortex-A8
M2 (64-bit)
EDMA TPTC0
EDMA TPTC1
EDMA TPTC2
EDMA TPTC3
PCIe
ELM
Port0
Port1
HDMIPHY
Port0
Port1
DCAN0/1
Port0
OCPWP
Port0
McASP0 CFG
Port1
Port0
Port1
Port0
Port0
Port1
Port0
Port1
Port0
Port1
McASP1 CFG
Port0
Port1
Port0
Port1
Port0
Port1
SYNCTIMER32K
Port0
Port1
Port0
Port1
Port0
Port1
124
Port1
Port0
System Interconnect
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6 Device Operating Conditions
6.1
Absolute Maximum Ratings
Supply voltage ranges (Steady
State):
(1) (2)
Core (CVDD, CVDD_ARM, CVDD_HDVICP)
-0.3 V to 1.5 V
HD-DAC Digital Logic, 1.1V (VDDA_HDDAC_1P1)
-0.5 V to 1.5 V
I/O, 1.8 V (DVDD_DDR[0], VDDA_1P8, VDDA_ARMPLL_1P8,
VDDA_VIDPLL_1P8, VDDA_AUDIOPLL_1P8, VDDA_DDRPLL_1P8,
VDDA_L3L4PLL_1P8, VDDA_PCIE_1P8, VDDA_SATA0_1P8,
VDDA_HDMI_1P8, VDDA_USB0_1P8, VDDA_USB1_1P8,
VDDA_VDAC_1P8, VDDA_CSI2_1P8, VDDA_HDDACREF_1P8,
VDDA_HDDAC_1P8, VDDA_HDVICPPLL_1P8, VDDS_OSC0_1P8,
VDDS_OSC1_1P8)
-0.3 V to 2.1 V
I/O 3.3 V (DVDD, DVDD_GPMC, DVDD_RGMII, DVDD_SD, DVDD_C)
-0.3 V to 4.0 V
DDR Reference Voltage (VREFSSTL_DDR[0])
-0.3 V to DVDD_DDR[0] +
0.3 V
V I/O, 1.35-V pins (Transient Overshoot/Undershoot)
30% of DVDD_DDR[0] for
up to 30% of the signal
period
V I/O, 1.5-V pins (Steady State)
-0.3 V to DVDD_DDR[0] +
0.3 V
V I/O, 1.5-V pins (Transient Overshoot/Undershoot)
30% of DVDD_DDR[0] for
up to 30% of the signal
period
V I/O, 1.8-V pins (Steady State)
-0.3 V to DVDD + 0.3 V
-0.3 V to DVDD_x + 0.3 V
Input and Output voltage ranges:
V I/O, 1.8-V pins (Transient Overshoot/Undershoot)
V I/O, 3.3-V pins (Steady State)
Commercial Temperature (default)
Extended temperature
Latch-up Performance
(1)
(2)
(3)
(4)
(5)
(6)
(6)
25% of DVDDx for up to
30% of the signal period
0°C to 95°C
-40°C to 95°C
Storage temperature range, Tstg:
Component-Level
Electrostatic Discharge (ESD)
Stress Voltage (3)
25% of DVDDx for up to
30% of the signal period
-0.3 V to DVDD + 0.3 V
-0.3 V to DVDD_x + 0.3 V
V I/O, 3.3-V pins (Transient Overshoot/Undershoot)
Operating junction temperature
range, TJ:
-0.3 V to 1.1 V
V I/O, 1.35-V pins (Steady State)
-55°C to 150°C
ESD-HBM (Human Body Model) (4)
ESD-CDM (Charged-Device Model)
±1000 V
(5)
±250 V
Class II (105ºC)
50 mA
Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating
conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
All voltage values are with respect to their associated VSS or VSSA_x.
Electrostatic discharge (ESD) to measure device sensitivity or immunity to damage caused by electrostatic discharges into the device.
Level listed is the passing level per ANSI/ESDA/JEDEC JS-001. JEDEC document JEP155 states that 500 V HBM allows safe
manufacturing with a standard ESD control process, and manufacturing with less than 500 V HBM is possible if necessary precautions
are taken. Pins listed as 1000 V may actually have higher performance.
Level listed is the passing level per EIA-JEDEC JESD22-C101E. JEDEC document JEP157 states that 250 V CDM allows safe
manufacturing with a standard ESD control process, and manufacturing with less than 250 V CDM is possible if necessary precautions
are taken. Pins listed as 250 V may actually have higher performance.
Based on JEDEC JESD78D [IC Latch-Up Test].
Device Operating Conditions
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Recommended Operating Conditions
PARAMETER
MIN
NOM
MAX
1.28
1.35
1.42
120% OPP
1.14
1.20
1.26
100% OPP (1)
1.05
1.10
1.16
1.28
1.35
1.42
120% OPP
1.14
1.20
1.26
100% OPP (1)
1.05
1.10
1.16
1.28
1.35
1.42
120% OPP
1.14
1.20
1.26
100% OPP (1)
1.05
1.10
1.16
DVDD
Supply voltage, I/O, standard
pins (2)
3.3 V
3.14
3.3
3.47
1.8 V
1.71
1.8
1.89
DVDD_GPMC
Supply voltage, I/O, GPMC pin
group
3.3 V
3.14
3.3
3.47
1.8 V
1.71
1.8
1.89
DVDD_RGMII
Supply voltage, I/O, RGMII pin
group
3.3 V
3.14
3.3
3.47
1.8 V
1.71
1.8
1.89
DVDD_SD
Supply voltage, I/O, SD pin
group
3.3 V
3.14
3.3
3.47
1.8 V
1.71
1.8
1.89
Supply voltage, I/O, C pin group
3.3 V
3.14
3.3
3.47
1.8 V
1.71
1.8
1.89
DDR2
1.71
1.8
1.89
DDR3
1.43
1.5
1.58
DDR3L
1.28
1.35
1.42
3.14
3.3
3.47
V
1.71
1.8
1.89
V
1.05
1.1
1.15
V
Supply voltage, Core (Scalable)
DVFS only, No AVS
CVDD
CVDD_ARM
Supply voltage, Core ARM
(Scalable)
Supply voltage, Core, HDVICP2
CVDD_HDVICP (Scalable)
DVDD_C
Supply voltage, I/O, DDR[0]
DVDD_DDR[0]
OPP_Turbo
OPP_Turbo
OPP_Turbo
VDDA_USB_3P Supply voltage, I/O, Analog, USB 3.3 V
3
VDDA_1P8
VDDA_x_1P8
VDDS_x_1P8
VDDA_HDDAC
_1P1
VREFSSTL_DDR[0]
USBx_VBUSIN
(3)
126
Supply voltage, I/O, Analog, HD-DAC 1.1 V
Supply Ground (VSS, VSSA_HDMI, VSSA_USB,
VSSA_VDAC, VSSA_DEVOSC (3), VSSA_AUXOSC (3))
VSS
(1)
(2)
Supply Voltage, I/O, Analog, (VDDA_1P8,
VDDA_ARMPLL_1P8, VDDA_VIDPLL_1P8,
VDDA_AUDIOPLL_1P8, VDDA_DDRPLL_1P8,
VDDA_L3L4PLL_1P8, VDDA_PCIE_1P8,
VDDA_SATA0_1P8, VDDA_HDMI_1P8,
VDDA_USB0_1P8, VDDA_USB1_1P8,
VDDA_VDAC_1P8, VDDA_CSI2_1P8,
VDDA_HDDACREF_1P8, VDDA_HDDAC_1P8,
VDDA_HDVICPPLL_1P8, VDDS_OSC0_1P8,
VDDS_OSC1_1P8)
Note: HDMI, USB0/1, and VDAC relative to their
respective VSSA.
IO Reference Voltage, (VREFSSTL_DDR[0])
0
UNIT
V
V
V
V
V
V
V
V
V
V
0.49 *
DVDD_DDR[0]
0.50 *
DVDD_DDR[0]
0.51 *
DVDD_DDR[0]
V
4.75
5
5.25
V
USBx VBUS Comparator Input
OPP100 is currently supported only on commercial temperature devices.
LVCMOS pins are all I/O pins powered by DVDD, DVDD_GPMC, DVDD_RGMII, DVDD_SD, DVDD_C supplies except for I2C[0] and
I2C[1] pins.
When using the internal Oscillators, the oscillator grounds (VSSA_DEVOSC, VSSA_AUXOSC) must be kept separate from other
grounds and connected directly to the crystal load capacitor ground.
Device Operating Conditions
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Recommended Operating Conditions (continued)
PARAMETER
MIN
High-level input voltage, LVCMOS (JTAG[TCK] pins), 3.3
V (2)
High-level input voltage, JTAG[TCK], 3.3 V
2.15
V
High-level input voltage, JTAG[TCK], 1.8 V
1.45
V
0.7DVDD
V
0.65DVDDx
V
High-level input voltage, DDR[0] signals in DDR2 mode
VREFSSTL_DDR[x]
+ 0.125
V
High-level input voltage, DDR[0] signals in DDR3 mode
VREFSSTL_DDR[x]
+ 0.1
V
High-level input voltage, DDR[0] signals in DDR3L mode
VREFSSTL_DDR[x]
+ 0.09
V
High-level input voltage, LVCMOS (2), 1.8 V
Low-level input voltage, JTAG[TCK]
Low-level input voltage, I2C (I2C[0] and I2C[1])
Low-level input voltage, LVCMOS
(2)
V
0.3DVDDx
V
0.35DVDDx
V
V
Low-level input voltage, DDR[0] signals in DDR3 mode
VREFSSTL_DDR[x]
- 0.1
V
Low-level input voltage, DDR[0] signals in DDR3L mode
VREFSSTL_DDR[x]
- 0.09
V
Low-level output current
IOL
6 mA I/O buffers
-6
mA
DDR[0] buffer @ 50-Ω
impedance setting
-8
mA
6 mA I/O buffers
6
mA
DDR[0] buffer @ 50-Ω
impedance setting
8
mA
VID
Differential input voltage (SERDES_CLKN/P), [AC coupled]
tt
Transition time, 10% - 90%, All inputs (unless otherwise
specified in the Electrical Data/Timing sections of each
peripheral)
TJ
Operating junction temperature
range (5)
(5)
V
VREFSSTL_DDR[x]
- 0.125
High-level output current
, 1.8 V
0.8
0.45
Low-level input voltage, DDR[0] signals in DDR2 mode
IOH
(4)
UNIT
V
Low-level input voltage, LVCMOS (2), 3.3 V
VIL
MAX
2
High-level input voltage, I2C (I2C[0] and I2C[1])
VIH
NOM
0.250
2.0
V
0.25P or 10 (4)
ns
Commercial
Temperature (default)
0
95
°C
Extended temperature
-40
95
°C
Whichever is smaller. P = the period of the applied signal. Maintaining transition times as fast as possible is recommended to improve
noise immunity on input signals.
For more detailed information on estimating junction temps within systems, see the IC Package Thermal Metrics Application Report
(Literature Number: SPRA953).
Device Operating Conditions
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Reliability Data (1)
6.3
The information in this table is provided solely for convenience and does not extend or modify the warranty provided under
TI's standard terms and conditions for TI semiconductor products.
CVDD (2)
CVDD_ARM (2)
CVDD_HDVICP (2)
Commercial
Junction Temp.
(TJ)
Turbo
1.35 V ± 5%
1.35 V ± 5%
1.35 V ± 5%
95ºC
59K
OPP120
1.20 V ± 5%
1.20 V ± 5%
1.20 V ± 5%
95ºC
100K
OPP100 (4)
1.10 V ± 5%
1.10 V ± 5%
1.10 V ± 5%
95ºC
100K
Operating Condition
(1)
(2)
(3)
(4)
128
Lifetime (POH) (3)
Logic functions and parameter values are not ensured out of the range specified in the recommended operating conditions. The above
notations cannot be deemed a warranty or deemed to extend or modify the warranty under TI's standard terms and conditions for TI
semiconductor products.
Voltage specification at the device package pin.
Power-on-hours (POH) represent device operation under the specified nominal conditions continuously for the duration of the calculated
lifetime. If actual application results in a system that operates at conditions less than the limits, the resulting POH may increase.
OPP100 is currently supported only on commercial temperature devices.
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6.4
SPRS872B – MAY 2013 – REVISED DECEMBER 2013
Electrical Characteristics Over Recommended Ranges of Supply Voltage and
Operating Temperature (Unless Otherwise Noted)
PARAMETER
VOH
VOL
TEST CONDITIONS (1)
MIN
MAX
2.8
VDDA_USB_3P
3
High speed: USBx_DM and
USBx_DP
360
440
UNIT
V
mV
High-level output voltage,
LVCMOS (2) (3.3-V I/O)
3.3 V, DVDDx = MIN,
IOH = MAX
2.4
V
High-level output voltage,
LVCMOS (2) (1.8-V I/O)
1.8 V, DVDDx = MIN,
IOH = MAX
1.26
V
High-level output voltage,
DDR[0] signals in DDR2
mode
1.8 V, IOL = 6mA, 50
ohm load
DVDD_DDR[0] 0.4
V
HIgh-level output voltage,
DDR[0] signals in DDR3
mode
1.5 V, IOL = 6mA, 50
ohm load
DVDD_DDR[0] 0.4
V
HIgh-level output voltage,
DDR[0] signals in DDR3L
mode
1.35 V, IOL = 6mA, 50
ohm load
DVDD_DDR[0] 0.4
V
Low/Full speed: USBx_DM
and USBx_DP
0.0
0.3
V
High speed: USBx_DM and
USBx_DP
-10
10
mV
Low-level output voltage,
LVCMOS (2) (3.3-V I/O)
3.3 V, DVDDx = MAX,
IOL = MAX
0.4
V
Low-level output voltage,
LVCMOS (2) (1.8-V I/O)
1.8 V, DVDDx = MAX,
IOL = MAX
0.4
V
Low-level output voltage, I2C 1.8/3.3 V, IOL = 4mA
(I2C[0], I2C[1])
0.4
V
Low-level output voltage,
DDR[0] signals in DDR2
mode
1.8 V, IOL = 6mA, 50
ohm load
0.4
V
Low-level output voltage,
DDR[0] signals in DDR3
mode
1.5 V, IOL = 6mA, 50
ohm load
0.4
V
Low-level output voltage,
DDR[0] signals in DDR3L
mode
1.35 V, IOL = 6mA, 50
ohm load
0.4
V
1.5
V
LDOs (applies to all
LDOCAP_x pins)
(1)
(2)
TYP
Low/Full speed: USBx_DM
and USBx_DP
For test conditions shown as MIN, MAX, or TYP, use the appropriate value specified in the recommended operating conditions table.
LVCMOS pins are all I/O pins powered by DVDD, DVDD_GPMC, DVDD_RGMII, DVDD_SD, DVDD_C supplies except for I2C[0] and
I2C[1] pins.
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Electrical Characteristics Over Recommended Ranges of Supply Voltage and Operating Temperature
(Unless Otherwise Noted) (continued)
PARAMETER
(2)
Input current, LVCMOS ,
3.3 V mode
Input current, LVCMOS (2),
1.8 V mode
II (3)
Input current, I2C (I2C[0],
I2C[1])
IOZ
(5)
I/O Off-state output current
TEST CONDITIONS (1)
MIN
0 < VI < DVDDx, 3.3 V
pull disabled
-20
0 < VI < DVDDx, 3.3 V
pulldown enabled (4)
20
0 < VI < DVDDx, 3.3 V
pullup enabled (4)
-20
0 < VI < DVDDx, 1.8 V
pull disabled
-5
0 < VI < DVDDx, 1.8 V
pulldown enabled (4)
50
0 < VI < DVDDx, 1.8 V
pullup enabled (4)
-50
3.3 V mode
1.8 V mode
TYP
MAX
UNIT
20
µA
100
300
µA
-100
-300
µA
5
µA
100
200
µA
-100
-200
µA
-20
20
µA
-5
5
µA
3.3 V mode, pull
enabled
-300
300
µA
3.3 V mode, pull
disabled
-20
20
µA
1.8 V mode, pull
enabled
-200
200
µA
1.8 V mode, pull
disabled
-5
5
µA
CI
Input capacitance
LVCMOS (2)
12
pF
Co
Output capacitance
LVCMOS (2)
12
pF
(3)
(4)
(5)
130
II applies to input-only pins and bi-directional pins. For input-only pins, II indicates the input leakage current. For bi-directional pins, II
indicates the input leakage current and off-state (Hi-Z) output leakage current.
Applies only to pins with an internal pullup (IPU) or pulldown (IPD) resistor.
IOZ applies to output-only pins, indicating off-state (Hi-Z) output leakage current.
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7 Power, Reset, Clocking, and Interrupts
7.1
Power, Reset and Clock Management (PRCM) Module
The PRCM module is the centralized management module for the power, reset, and clock control signals
of the device. It interfaces with all the components on the device for power, clock, and reset management
through power-control signals. It integrates enhanced features to allow the device to adapt energy
consumption dynamically, according to changing application and performance requirements. The
innovative hardware architecture allows a substantial reduction in leakage current.
The PRCM module is composed of two main entities:
• Power reset manager (PRM): Handles the power, reset, wake-up management, and system clock
source control (oscillator)
• Clock manager (CM): Handles the clock generation, distribution, and management.
For more details on the PRCM, see the Power, Reset, and Clock Management (PRCM) Module chapter in
the device-specific Technical Reference Manual.
7.2
Power
7.2.1
Voltage and Power Domains
Every Module within the device belongs to a Core Logic Voltage Domain, Memory Voltage Domain, and a
Power Domain (see Table 7-1).
Table 7-1. Voltage and Power Domains
CORE LOGIC
VOLTAGE DOMAIN
MEMORY VOLTAGE
DOMAIN
ARM_L
ARM_M
7.2.1.1
CORE_L
CORE_M
HDVICP_L
HDVICP_M
POWER
DOMAIN
MODULE(S)
ARM Cortex-A8 Subsystem, SmartReflex Sensor 0
ALWAYS ON
ATL, HDMI, DCAN0/1, DMM, EDMA, ELM, DDR,
EMAC Switch, GPIO Banks 0/1/2/3, GPMC,
I2C0/1/2/3, IPC, MCASP0/1, OCMC SRAM, PRCM,
RTC, SATA0, SD/MMC0/1/2, SPI01/2/3,
Timer1/2/3/4/5/6/7/8, UART0/1/2, USB0/1, WDT0,
System Interconnect, JTAG, Media Controller, ISS,
SmartReflex Control Module 0/1, SmartReflex Sensor
1
HDVPSS
HDVPSS, SD-DAC, HD-DAC
HDVICP
HDVICP2, SmartReflex Sensor 2
Core Logic Voltage Domains
The device contains three Core Logic Voltage Domains. These domains define groups of Modules that
share the same supply voltage for their core logic. Each Core Logic Voltage Domain is powered by a
dedicated supply voltage rail that can be independently scaled using SmartReflex technology to trade off
power versus performance. Table 7-2 shows the mapping between the Core Logic Voltage Domains and
their associated supply pins.
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Table 7-2. Core Logic Voltage Domains and Supply Pin Associations
CORE LOGIC
VOLTAGE DOMAIN
SUPPLY PIN NAME
ARM_L
CVDD_ARM
CORE_L
CVDD
HDVICP_L
CVDD_HDVICP
Note: A regulated supply voltage must be supplied to each Core Logic Voltage Domain at all times,
regardless of the Core Logic Power Domain states.
7.2.1.2
Power Domains
The device contains four Power Domains which supply power to both the Core Logic and SRAM within
their associated modules. Each Power Domain, except for the ALWAYS ON domain, has an internal
power switch that can completely remove power from that domain. All power switches are turned "OFF" by
default after reset, and software can individually turn them "ON/OFF" via Control Module registers.
Note: All Modules within a Power Domain are unavailable when the domain is powered "OFF". For
instructions on powering "ON/OFF" the Power domains, see the Power, Reset, and Clock Management
(PRCM) Module chapter of the device-specific Technical Reference Manual.
7.2.2
SmartReflex™ [Currently Not Supported]
The device contains SmartReflex modules that help to minimize power consumption on the Core Logic
Voltage Domains by using external variable-voltage power supplies. Based on the device process,
temperature, and desired performance, the SmartReflex modules advise the host processor to raise or
lower the supply voltage to each domain for minimal power consumption.
The communication link between the host processor and the external regulators is a system-level decision
and can be accomplished using GPIOs, I2C, SPI, or other methods. The following sections briefly
describe the two major techniques employed by SmartReflex: Dynamic Voltage Frequency Scaling
(DVFS) and Adaptive Voltage Scaling (AVS).
7.2.2.1
Dynamic Voltage Frequency Scaling (DVFS) [Currently Supports Only Discrete OPPs]
Each device Core Logic Voltage Domain can be run independently at one of several Operating
Performance Points (OPPs). An OPP for a specific Core Logic Voltage Domain is defined by: (1)
maximum frequencies of operation for Modules within the Domain and (2) an associated supply voltage
range. Trading off power versus performance, OPPs with lower maximum frequencies also have lower
voltage ranges for power savings.
The OPP for a domain can be changed in real-time without requiring a reset. This feature is called
Dynamic Voltage Frequency Scaling (DVFS) Table 7-3 contains a list of voltage ranges and maximum
module frequencies for the OPPs of each Core Logic Voltage Domain.
NOTE
Not all devices support all OPP frequencies.
OPP100 is currently supported only on commercial temperature devices.
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Table 7-3. Device Operating Points (OPPs)
CORE LOGIC VOLTAGE DOMAINS
(1)
(2)
ARM
HDVICP2
CORE
OPP
Cortex A8
(MHz)
HDVICP2
HDVPSS
(MHz)
ISS
(MHz)
Media Ctlr.
(MHz)
L3/L4,
Core
(MHz)
DDR
(MHz) (1)
100%(1.1 V) (2)
600
220
200
400
200
200
400
120% (1.2 V)
(DMVA3)
720
290
200
400
200
200
400
Turbo (1.35 V)
(DMVA4)
970
410
240
480
240
240
533
All DDR access must be suspended prior to changing the DDR frequency of operation.
OPP100 is currently supported only on commercial temperature devices.
Although the OPP for each Core Logic Voltage Domain is independently selectable, not all combinations
of OPPs are supported. Table 7-4 marks the supported ARM OPPs for a given CORE OPP.
Table 7-4. Supported OPP Combinations (1)
ARM
CORE
Turbo
Turbo
X
OPP100 (2)
X
X
OPP120
OPP100 (2)
(1)
(2)
7.2.2.2
HDVICP2
OPP120
Turbo
OPP120
OPP100 (2)
X
X
X
X
X
"X" denotes supported combinations.
OPP100 is currently supported only on commercial temperature devices.
Adaptive Voltage Scaling [Currently Not Supported]
As mentioned in Section 7.2.2.1, Dynamic Voltage Frequency Scaling (DVFS) above, every OPP has an
associated voltage range. Based on the silicon process, temperature, and chosen OPP, the SmartReflex
modules guide software in adjusting the Core Logic Voltage Domain supply voltage (CVDD) within these
ranges. This technique is called Adaptive Voltage Scaling (AVS). AVS occurs continuously and in realtime, helping to minimize power consumption in response to changing operating conditions.
7.2.3
Memory Power Management
In order to reduce SRAM leakage, many SRAM blocks can be switched from ACTIVE mode to
SHUTDOWN mode. When SRAM is put in SHUTDOWN mode, the voltage supplied to it is automatically
removed and all data in that SRAM is lost.
All SRAM located in a switchable power domain (all domains except ALWAYS_ON) automatically enters
SHUTDOWN mode whenever its associated power domain goes into the "OFF" state. The SRAM returns
to the ACTIVE state when the corresponding Power Domain returns to the "ON" state.
In addition, the following SRAM within the ALWAYS_ON Power Domain can also be independently put
into SHUTDOWN by programming the x_MEM_PWRDN registers in the Control Module:
• Media Controller SRAM
• OCMC SRAM
7.2.4
SERDES_CLKP/N LDO
The SERDES_CLKP/N input buffers are powered by an internal LDO which is programmed through the
REFCLK_LJCBLDO_CTRL register in the Control Module.
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Dual Voltage I/Os
The device supports dual voltages on some of its I/Os. These I/Os are partitioned into the following
groups, and each group has its own dedicated supply pins: DVDD, DVDD_GPMC, DVDD_C, and
DVDD_SD. The supply voltage for each group can be independently powered with either 1.8 V or 3.3 V.
For the mapping between pins and power groups, see Section 3.3, Terminal Functions of the datasheet.
In addition, the I/O voltage on the DDR interface is independently selectable between 1.35 V, 1.5 V or
1.8 V to support various DDR device types.
7.2.6
I/O Power-Down Modes
On the device, there are power-down modes available for the following PHYs:
• Video DACs
• DDR
• USB
• HDMI
• CSI2
• PCIE
• SATA
When a PHY controller is in a power domain that is to be turned "OFF", software must configure the
corresponding PHY into power-down mode, prior to putting the power domain in the "OFF" state.
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7.2.7
SPRS872B – MAY 2013 – REVISED DECEMBER 2013
Standby and Deep Sleep Modes
The device supports Low-Power Standby and Deep-Sleep Modes as described below.
Standby Mode is defined as a state in which:
• All switchable power domains are in "OFF" state
• The ARM Cortex-A8 is executing an IDLE loop at its lowest frequency of operation
• All functional blocks not needed for a given application are clock gated
Deep Sleep Mode is defined to be the same as Standby Mode, with the addition of gating the crystal
oscillator to further eliminate all active power. The device core voltages can be reduced for optimal power
savings.
For detailed instructions on entering and exiting from Standby and Deep Sleep Modes, see the Power,
Reset, and Clock Management (PRCM) Module chapter in the device-specific Technical Reference
Manual.
7.2.8
Supply Sequencing
The device power supplies are organized into five Supply Sequencing Groups:
1. CVDD Core Logic supply (CVDD)
2. All CVDD_x supplies (CVDD_ARM and CVDD_HDVICP)
3. All 1.35-/1.5-/1.8-V DVDD_DDR[0] Supplies (1.35 V for DDR3L, 1.5 V for DDR3, 1.8 V for DDR2)
4. All 1.8-V Supplies (DVDD_x, VDDA_x_1P8, VDDA_1P8)
5. All 3.3-V Supplies (DVDD, DVDD_x, DVDD_C, VDDA_x_3P3)
To ensure proper device operation, a specific power-up and power-down sequence must be followed.
Some TI power-supply devices include features that facilitate these power sequencing requirements — for
example, TI’s TPS659113 integrated PMIC. For more information on TI power supplies and their features,
visit www.ti.com/processorpower.
7.2.8.1
Power-Up Sequence
For proper device operation, the following power-up sequence in Table 7-5 and Figure 7-1 must be
followed.
Table 7-5. Power-Up Sequence Ramping Values
NO.
1
(1)
(2)
DESCRIPTION
1.8 V supplies to 1.35-/1.5-/1.8-V DVDD_DDR[x] supplies
2
DVDD_DDR supplies stable to 3.3 V supplies ramp start
3
1.8 V supplies stable to CVDD, CVDD_x variable supplies
ramp start
4
All supplies valid to power-on-reset (POR high)
MIN
MAX
UNIT
0 (1)
ms
0
(2)
ms
0
(1)
ms
4 096
Master
Clocks
The 1.8 V supplies must be ≥ 1.35-/1.5-/1.8-V DVDD_DDR[x] and CVDD, CVDD_x variable supplies.
Both 1.8 V and DVDD_DDR[x] supplies must be powered up and stable prior to starting the ramp of the 3.3 V supplies.
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POR
1.8 V Supplies
(DVDD, DVDD_x, VDDA_x_1P8,
VDDA_1P8)
1.35 V/1.5 V/1.8 V DVDD_DDR[0]
3.3 V Supplies
(DVDD, DVDD_x, VDDA_x_3P3)
CVDD
CVDD_x
2
1
3
4
Both 1.8 V and DVDD_DDR[x] supplies must be powered up and stable prior to starting the ramp of the 3.3 V
supplies.
CVDD powered-up coincidently or prior to CVDD_ARM and CVDD_HDVICP supplies.
Figure 7-1. Power-Up Sequence
7.2.8.2
Power-Down Sequence
For proper device operation, the following power-down sequence in Table 7-6, Figure 7-2, Figure 7-3, and
Figure 7-4 must be followed.
Table 7-6. Power-Down Sequence Ramping Values
NO.
136
MIN
MAX
UNIT
5
CVDD, CVDD_x variable supplies to 1.8 V supplies
0
6
1.35-/1.5-/1.8-V DVDD_DDR[x] supplies to 1.8 V supplies
0
7
3.3 V supplies to 1.8 V supplies
(1)
(1)
ms
CVDD_x supplies to CVDD supply
(2)
(2)
ms
8
(1)
(2)
DESCRIPTION
ms
ms
The 3.3 V supplies must never be more than 2 V above the 1.8 V supplies (see Figure 7-3).
The CVDD supply must be powered down coincidentally or after CVDD_ARM and CVDD_HDVICP supplies (see Figure 7-4).
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1.8 V Supplies
(DVDD, DVDD_x, VDDA_x_1P8,
VDDA_1P8)
3.3 V Supplies
(DVDD, DVDD_x, DVDD_C, VDDA_x_3P3)
1.35 V/1.5 V/1.8 V DVDD_DDR[0]
CVDD, CVDD_x
7
6
5
Figure 7-2. Power-Down Sequence
3.3 V Supplies
V Delta
(A)
1.8 V Supplies
(Excluding DVDD_DDR[x])
A.
V Delta Max = 2 V.
Figure 7-3. 3.3 V Supplies Falling After 1.8 V Supplies Delta
CVDD_x
CVDD
8
Figure 7-4. CVDD and CVDD_x Power-Down Sequence
7.2.9
Power-Supply Decoupling
7.2.9.1
Analog and PLL
PLL and Analog supplies benefit from filters or ferrite beads to keep the noise from causing problems. The
minimum recommendation is a ferrite bead along with at least one capacitor on the device side of the
bead. An additional recommendation is to add one capacitor just before the bead to form a Pi filter. The
filter needs to be as close as possible to the device pin, with the device side capacitor being the most
important component to be close to the device pin. PLL pins close together can be combined on the same
supply, but analog pins should all have their own filters. PLL pins farther away from each other may need
their own filtered supply.
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Digital
Recommended capacitors for power supply decoupling are all 0.1uF in the smallest body size that can be
used. Capacitors are more effective in the smallest physical size to limit lead inductance. For example,
0201 sized capacitors are better than 0402 sized capacitors, and so on. TI recommends using capacitors
no larger than 0402. Place at least one capacitor for every two power pins. For those power pins that have
only one pin, a capacitor is still required. Place one bulk (10 uF or larger) capacitor for every 10 or so
power pins as closely as possible to the chip. These larger caps do not need to be under the chip
footprint.
Pay special attention not to put so much capacitance on the supply that it slows the start-up voltage ramp
enough to change the power sequencing order. Also be sure to verify that the main chip reset is low until
after all supplies are at their correct voltage and stable.
DDR peripheral related supply capacitor numbers are provided in Section 8.14, DDR2/DDR3/DDR3L
Memory Controller.
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7.3
SPRS872B – MAY 2013 – REVISED DECEMBER 2013
Reset
7.3.1
System-Level Reset Sources
The device has several types of system-level resets. Table 7-7 lists these reset types, along with the reset
initiator, and the effects of each reset on the device.
Table 7-7. System-Level Reset Types
TYPE
Power-on Reset (POR)
External Warm Reset
Emulation Warm Reset
INITIATOR
RESETS ALL
MODULES,
EXCLUDING EMAC
SWITCH,
EMULATION, PLL
AND CLOCK
CONFIG
RESETS EMAC
SWITCH
RESETS
EMULATION
PLL AND CLOCK
CONFIG
LATCHES
BOOT PINS
ASSERTS
RSTOUT_WD_OUT
PIN
POR pin
Yes
Yes
Yes
Yes
Yes
Optional (1) (2)
(3)
No
No
Yes
Optional (1) (2)
No
No
No
Optional (1)
RESET pin
Yes
Optional
On-Chip Emulation
Logic
Yes
Optional (3)
Watchdog Timer
Yes
Optional (3)
No
No
No
Yes
Software Global Cold Reset
Software
Yes
Optional (3)
Yes
Yes
No
Optional (1)
Software Global Warm Reset
Software
Yes
Optional (3)
No
No
No
Optional (1)
Test Reset
TRST pin
No
No
Yes
No
No
No
Watchdog Reset
(1)
(2)
(3)
RSTOUT_WD_OUT pin asserted only if BTMODE[11] was latched as "0" when coming out of reset.
While POR and/or RESET is asserted, the RSTOUT_WD_OUT pin is 3-stated and the internal pull resistor is disabled; therefore, an
external pullup/pulldown can be used to set the state of this pin (high/low) while POR and/or RESET is asserted. For more detailed
information on external PUs/PDs, see Section 4.5.1, Pullup/Pulldown Resistors.
EMAC Switch is NOT reset when the ISO_CONTROL bit in the RESET_ISO Control Module register is set to "1".
7.3.2
Power-on Reset (POR pin)
Power-on Reset (POR) is initiated by the POR pin and is used to reset the entire chip, including the Test
and Emulation logic, and the EMAC Switch. POR is also referred to as a cold reset since it is required to
be asserted when the device goes through a power-up cycle. However, a device power-up cycle is not
required to initiate a Power-on Reset.
The following sequence must be followed during a Power-on Reset:
1. Wait for the power supplies to reach normal operating conditions while keeping the POR pin asserted.
2. Wait for the input clock sources DEV_CLKIN, AUX_CLKIN, and SERDES_CLKN/P to be stable (if
used by the system) while keeping the POR pin asserted (low).
3. Once the power supplies and the input clock sources are stable, the POR pin must remain asserted
(low) [see Section 7.3.18, Reset Electrical Data/Timing]. Within the low period of the POR pin, the
following happens:
(a) All pins except Emulation pins enter a Hi-Z mode and the associated pulls, if applicable, will be
enabled.
(b) The PRCM asserts reset to all modules within the device.
(c) The PRCM begins propagating these clocks to the chip with the PLLs in BYPASS mode.
4. The POR pin may now be de-asserted (driven high). When the POR pin is de-asserted (high):
(a) The BTMODE[15:0] pins are latched.
(b) Reset to the ARM Cortex-A8 and Modules without a local processor is de-asserted.
(c) RSTOUT_WD_OUT is briefly asserted if BTMODE[11] was latched as "0".
(d) The clock, reset, and power-down state of each peripheral is determined by the default settings of
the PRCM.
(e) The ARM Cortex-A8 begins executing from the Boot ROM.
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7.3.3
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External Warm Reset (RESET pin)
An external warm reset is activated by driving the RESET pin active-low. This resets everything in the
device, except for the Test and Emulation logic, and the EMAC Switch (optional). An emulator session
stays alive during warm reset.
The following sequence must be followed during a warm reset:
1. Power supplies and input clock sources should already be stable.
2. The RESET pin must be asserted (low)[see Section 7.3.18, Reset Electrical Data/Timing]. Within the
low period of the RESET pin, the following happens:
(a) All pins, except Test and Emulation pins, enter a Hi-Z mode and the associated pulls, if applicable,
will be enabled.
(b) The PRCM asserts reset to all modules within the device, except for the Test and Emulation logic,
EMAC Switch (optional), PLL, and Clock configuration.
3. The RESET pin may now be de-asserted (driven high). When the RESET pin is de-asserted (high):
(a) The BTMODE[15:0] pins are latched.
(b) Reset to the ARM Cortex-A8 and modules without a local processor is de-asserted, with the
exception of Test and Emulation logic, EMAC Switch (optional), PLL, and Clock configuration.
(c) RSTOUT_WD_OUT is asserted [see Section 7.3.18, Reset Electrical Data/Timing], if BTMODE[11]
was latched as "0".
(d) The clock, reset, and power-down state of each peripheral is determined by the default settings of
the PRCM.
(e) The ARM Cortex-A8 begins executing from the Boot ROM.
7.3.4
Emulation Warm Reset
An Emulation Warm Reset is activated by the on-chip Emulation Module. It has the same effect and
requirements as an External Warm Reset (RESET), with the following exceptions:
• BTMODE[15:0] pins are not re-latched
• RSTOUT_WD_OUT is not 3-stated and is actively driven based on the value previously latched on the
BTMODE[11] pin.
The emulator initiates an Emulation Warm Reset via the ICEPICK module. To invoke the Emulation Warm
Reset via the ICEPICK module, the user can perform the following from the Code Composer Studio™ IDE
menu: Target -> Reset -> System Reset.
7.3.5
Watchdog Reset
A Watchdog Reset is initiated when the Watchdog Timer counter reaches zero. It has the same effect and
requirements as an External Warm Reset (RESET pin), with the following exceptions:
• BTMODE[15:0] pins are not re-latched
• RSTOUT_WD_OUT is not 3-stated and is actively driven based on the value previously latched on the
BTMODE[11] pin.
In addition, a Watchdog Reset always results in RSTOUT_WD_OUT being asserted, regardless of
whether the BTMODE[11] pin was latched as "0" or "1".
7.3.6
Software Global Cold Reset
A Software Global Cold Reset is initiated under software control. It has the same effect and requirements
as a POR Reset, with the following exceptions:
• BTMODE[15:0] pins are not re-latched and EMAC Switch (optional) is not reset
• RSTOUT_WD_OUT is not 3-stated and is actively driven based on the value previously latched on the
BTMODE[11] pin.
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Software initiates a Software Global Cold Reset by writing a "1" to the RST_GLOBAL_COLD_SW bit in
the PRM_RSTCTRL register in the PRCM.
For more detailed information on the PRM_RSTCTRL register, see the PRCM Registers section of the
Power, Reset, and Clock Management (PRCM) Module chapter in the device-specific Technical
Reference Manual.
7.3.7
Software Global Warm Reset
A Software Global Warm Reset is initiated under software control. It has the same effect and requirements
as a External Warm Reset (RESET pin), with the following exceptions:
• BTMODE[15:0] pins are not re-latched
• RSTOUT_WD_OUT is not 3-stated and is actively driven based on the value previously latched on the
BTMODE[11] pin.
Software initiates a Software Global Warm Reset by writing a "1" to the RST_GLOBAL_WARM_SW bit in
the PRM_RSTCTRL register in the PRCM.
For more detailed information on the PRM_RSTCTRL register, see the PRCM Registers section of the
Power, Reset, and Clock Management (PRCM) Module chapter in the device-specific Technical
Reference Manual.
7.3.8
Test Reset (TRST pin)
A Test Reset is activated by the emulator asserting the TRST pin. The only effect a Test Reset has is to
reset the Test and Emulation Logic.
7.3.9
Local Reset
The Local Reset for various Modules within the device is controlled by programming the PRCM and/or the
Peripheral Module’s internal registers. Only the associated Module is reset when a Local Reset is
asserted, leaving the rest of the device unaffected.
For more details on Peripheral Local Resets, see the Reset Management section of the Power, Reset,
and Clock Management (PRCM) Module chapter in the device-specific Technical Reference Manual.
7.3.10 Reset Priority
If any of the above reset sources occur simultaneously, the device only processes the highest-priority
reset request. The reset request priorities, from high-to-low, are as follows:
1. Power-on Reset (POR)
2. Test Reset (TRST)
3. External Warm Reset (RESET pin)
4. Emulation Warm Resets
5. Watchdog Reset
6. Software Global Cold/Warm Resets
7.3.11 Reset Status Register
The Reset Status Register (PRM_RSTST) contains information about the last reset that occurred in the
system. For more information on this register, see the Power, Reset, and Clock Management (PRCM)
Module chapter in the device-specific Technical Reference Manual.
7.3.12 PCIE Reset Isolation
The device supports reset isolation for the PCI Express (PCIE) module. This means that the PCI Express
Subsystem can be reset without resetting the rest of the device.
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When the device is a PCI Express Root Complex (RC), the PCIE Subsystem can be reset by software
through the PRCM. Software should ensure that there are no ongoing PCIE transactions before asserting
this reset by first taking the PCIE Subsystem into the IDLE state. After bringing the PCIE Subsystem out
of reset, bus enumeration should be performed again and should treat all Endpoints (EP) as if they had
just been connected.
When the device is a PCI Express Endpoint (EP), the PCIE Subsystem will generate an interrupt when an
in-band reset is received. Software should process this interrupt by putting the PCIE Subsystem in the
IDLE state and then asserting the PCIE local reset through the PRCM.
All device level resets mentioned in the previous sections, except Test Reset, will also reset the PCIE
Subsystem. Therefore, the PCIE peripheral should issue a Hot Reset to all downstream devices and reenumerate the bus upon coming out of reset.
For more detailed information on reset isolation procedures, see the PCIe Reset Isolation section of the
Power, Reset, and Clock Management (PRCM) Module chapter in the device-specific Technical
Reference Manual.
7.3.13 EMAC Switch Reset Isolation
The device supports reset isolation for the Ethernet Switch (EMAC Switch) only when clock sourced from
SATA0_SERDES. The other clocking source options do not provide RESET Isolation. This allows the
device to undergo all resets listed in Section 7.3.1, System-Level Reset Sources, with the exception of
POR Reset, without disrupting the Ethernet Switch or the traffic being routed through the switch during the
reset condition. The following reset types can optionally provide an EMAC Switch reset isolation by setting
the ISO_CONTROL bit in the RESET_ISO Control Module register to a "1":
• External Warm Reset
• Emulation Warm Reset
• Watchdog Reset
• Software Global Cold Reset
• Software Global Warm Reset
When one of above resets occurs and the Ethernet Switch (EMAC Switch) is programmed to be isolated:
• The switch function of the EMAC Switch and the PLL embedded in the SATA0_SERDES Module
(which provides the reference clocks to the EMAC Switch) will not be reset.
• Several Control Module registers are not reset. For more details, see the description of the
RESET_ISO register in the Control Module chapter of the device-specific Technical Reference Manual
.
• The pin multiplexing of some of the EMAC Switch pins is unaffected. For more details, see the
description of the RESET_ISO register in the Control Module chapter in the device-specific Technical
Reference Manual.
The EMAC Switch is always reset when:
• One of the above resets occurs and the Ethernet Switch is programmed to be “not isolated”
• A POR Reset occurs
7.3.14 RSTOUT_WD_OUT Pin
The RSTOUT_WD_OUT pin reflects device reset status and is de-asserted (high) when the device is out
reset. This output will always be asserted when a Watchdog Timer reset (Watchdog Reset) occurs. In
addition, this output is always 3-stated and the internal pull resistor is disabled on this pin while POR
and/or RESET is asserted; therefore, an external pullup/pulldown can be used to set the state of this pin
(high/low) while POR and/or RESET is asserted. For more detailed information on external PUs/PDs, see
Section 4.5.1, Pullup/Pulldown Resistors.
If the BTMODE[11] pin is latched as a "0" at the rising edge of POR or RESET, then RSTOUT_WD_OUT
is also asserted when any of the below resets occur:
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•
•
•
•
SPRS872B – MAY 2013 – REVISED DECEMBER 2013
Power-On Reset (asserted after the BTMODE[11] pin is latched)
External Warm Reset (asserted after the BTMODE[11] pin is latched)
Emulation Warm Reset
Software Global Cold/Warm Reset
The RSTOUT_WD_OUT pin remains asserted until the PRCM releases the host ARM Cortex-A8
processor for reset.
7.3.15 Effect of Reset on Emulation & Trace
The device Emulation & Trace Logic will only be reset by the following sources:
• Power-On Reset
• Software Global Cold Reset
• Test Reset
Other than these three reset types, none of the other resets will affect the Emulation and Trace Logic.
However, the multiplexing of the EMU[4:2] pins is reset by all system reset types except Test Reset.
7.3.16 Reset During Power Domain Switching
Each Power Domain has a dedicated Warm Reset and Cold Reset. Warm Reset for a Power Domain is
asserted under either of the following two conditions:
1. An External Warm Reset, Emulation Warm Reset, or Software Global Warm Reset occurs
2. When that Power Domain switches from the "ON" state to the "OFF" state
Cold Reset for a Power Domain is asserted under either of the following two conditions:
1. Power-On Reset or Software Global Cold Reset occurs
2. When that Power Domain switches from the "OFF" state to the "ON" state
7.3.17 Pin Behaviors at Reset
When any reset, other than Test Reset, (all described in Section 7.3.1, System-Level Reset Sources) is
asserted, all device I/O pins are reset into a Hi-Z state except for:
• Emulation Pins. These pins are only put into a Hi-Z state when Test Reset (TRST) is asserted.
• EMAC Switch Pins. These pins are always put into a Hi-Z state during Power-On Reset. However,
some EMAC Switch pins will not be put into a Hi-Z state during the other reset modes when the
ISO_CONTROL bit in the RESET_ISO register of the Control Module is programmed as a "1". For
more details, see the description of the RESET_ISO register in the Control Module chapter in the
device-specific Technical Reference Manual.
• RSTOUT_WD_OUT Pin during any reset types except for POR and RESET. For more detailed
information on RSTOUT_WD_OUT pin behavior, see Section 7.3.14, RSTOUT_WD_OUT Pin.
• DDR[0] Address/Control Pins (CLK, CLK, CKE, WE, CS[0], RAS, CAS, ODT[0], RST, BA[2:0], A[15:0]).
These pins are 3-stated during reset. However, these pins are then driven to the same value as their
internal pull resistor reset value when reset is released.
In addition, the PINCNTL registers, which control pin multiplexing, enabling the IPUs/IPDs, and enabling
the receiver, are reset to their default state. Again, enabling the EMAC Switch reset isolation prevents
some PINCNTL registers from being reset.
For details on EMAC Switch reset isolation, see the descriptions of the RESET_ISO register and the
PINCNTL registers in the Control Module chapter in the device-specific Technical Reference Manual.
Internal pull-up/down (IPU/IPD) resistors are enabled during and immediately after reset as described in
Section 3.3, Terminal Functions of this document.
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NOTE
The reset pin state is after all the power supplies are ramped up and stable. The state is not
not ensured during power-up sequencing.
Upon coming out of reset, the ARM Cortex-A8 starts executing code from the internal Boot
ROM. The Boot ROM code modifies the PINCNTLx registers to configure the associated
pins for the chosen primary and backup Bootmodes.
7.3.18 Reset Electrical Data/Timing
NOTE
For supported OPP frequencies, see Table 7-3, Device Operating Points (OPPs).
Table 7-8. Timing Requirements for Reset (see Figure 7-5 and Figure 7-6)
OPP100
NO.
1
tw(RESET)
2
3
(1)
(2)
MIN
MAX
UNIT
12P (1)
ns
POR
2P (2)
ns
RESET
2P (2)
ns
0
ns
Pulse duration, POR low or RESET low
tsu(BOOT)
Setup time, BTMODE[15:0] pins valid before POR high or
RESET high
th(BOOT)
Hold time, BTMODE[15:0] pins valid after POR high or RESET high
The device clock source must be stable and at a valid frequency prior to meeting the tw(RESET) requirement.
P = 1/(DEV Clock) frequency in ns.
Table 7-9. Switching Characteristics Over Recommended Operating Conditions During Reset
(see Figure 7-6)
NO.
4
OPP100
PARAMETER
td(RSTL-
MIN
MAX
UNIT
Delay time, RESET low or POR low to all I/Os entering their reset state
14
ns
Delay time, RESET high or POR high to all I/Os exiting their reset state
14
ns
IORST)
5
td(RSTHIOFUNC)
6
td(RSTH-
RESET assertion tw(RESET)
≥ 30P
0
2P
ns
RESET assertion tw(RESET)
< 30P
0
32P tw(RESET)
ns
Delay time, POR high to RSTOUT_WD_OUT high (1) (2)
0
12500P
ns
Delay time, RESET low to RSTOUT_WD_OUT Hi-Z (1) (2)
0
2P
ns
Delay time, POR high to RSTOUT_WD_OUT driven based on latched BTMODE[11]
value (1) (2)
0
2P
ns
Delay time, RESET high to RSTOUT_WD_OUT driven based on latched BTMODE[11]
value (1) (2)
0
2P
ns
Delay time, RESET high to RSTOUT_WD_OUT high
(1) (2)
RSTOUTH)
7
td(PORHRSTOUTH)
8
td(RSTLRSTOUTZ)
9
td(PORHRSTOUTL)
10
td(RSTHRSTOUTD)
(1)
(2)
144
For more detailed information on RSTOUT_WD_OUT pin behavior, see Section 7.3.14, RSTOUT_WD_OUT Pin.
P = 1/(DEV Clock) frequency in ns.
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Figure 7-5 shows the Power-Up Timing. Figure 7-6 shows the Warm Reset (RESET) Timing. Max Reset
Timing is identical to Warm Reset Timing, except the BTMODE[15:0] pins are not re-latched.
Power
Supplies
Ramping
Power Supplies Stable
Clock Source Stable
DEV_CLKIN/
(A)
AUX_CLKIN
1
POR
RESET
7
9
RSTOUT_WD_OUT
Hi-Z
BTMODE[11]
(B)
5
3
2
BTMODE[15:0]
Hi-Z
Config
5
(C)
Other I/O Pins
A.
B.
C.
RESET STATE
Power supplies and DEV_CLKIN/AUX_CLKIN must be stable before the start of tw(RESET).
RSTOUT_WD_OUT only asserted if BTMODE[11] was latched as a "0" when coming out of reset.
For more detailed information on the RESET STATE of each pin, see Section 7.3.17, Pin Behaviors at Reset. Also
see , Terminal Functions for the IPU/IPD settings during reset.
Figure 7-5. Power-Up Timing
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Power Supplies Stable
DEV_CLKIN/
AUX_CLKIN
POR
1
RESET
8
6
10
Hi-Z
RSTOUT_WD_OUT
BTMODE[11]
5
4
3
2
Hi-Z
BTMODE[15:0]
Config
5
4
(B)
Other I/O Pins
A.
B.
(A)
RESET STATE
RSTOUT_WD_OUT only asserted if BTMODE[11] was latched as a "0" when coming out of reset.
For more detailed information on the RESET STATE of each pin, see Section 7.3.17, Pin Behaviors at Reset. Also
see , Terminal Functions for the IPU/IPD settings during reset.
Figure 7-6. Warm Reset (RESET) Timing
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7.4
SPRS872B – MAY 2013 – REVISED DECEMBER 2013
Clocking
The device clocks are generated from several reference clocks that are fed to on-chip PLLs and dividers
(both inside and outside of the PRCM Module). Figure 7-7 shows a high-level overview of the device
system clocking structure (Note: to reduce complexity, not all clocking connections are shown). For
detailed information on the device clocks, see the Clock Generation and Management section of the
Power, Reset, and Clock Management (PRCM) Module chapter in the device-specific Technical
Reference Manual.
NOTE
For supported OPP frequencies, see Table 7-3, Device Operating Points (OPPs).
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PLL_HDVPSS
HDVPSS
PLL_MEDIACTL
ISS, Media Controller
SYSCLK4
L3 Fast/Medium, L4 Fast,
EDMA, OCMC
PRCM
PLL_L3L4
L3/L4 Slow, GPMC,
ELM, McASP,
Mailbox, Spinlock
SYSCLK6
USB0/1
CLKDCO
PLL_USB
DEVOSC/
DEV_CLKIN
AUXOSC/
AUX_CLKIN
SYSCLK10
M
U
X
CLKOUT
PRCM
SPI0/1/2/3, I2C0/1/2/3,
UART0/1/2, HDMI CEC
SYSCLK8
MMC0/1/2
(Note: Separate MUX
exists for each PLL)
PLL_DDR
DDR
/2
DMM
HDVPSS SD VENC
PLL_VIDEO0
HDMI
PLL_VIDEO2
HDMI PHY
HDVPSS VOUT1
M
U
X
M
U
X
M
U
X
PLL_VIDEO1
PLL_AUDIO
HDVPSS VOUT0
PRCM
From PLL_VIDEO0/1/2
PRCM
SYSCLK20
SYSCLK21
From AUX Clock, AUD_CLK0/1/2
PLL_ARM
(Embedded PLL)
M
U
X
MCASP0/1 AUX_CLK,
ATL
M
U
X
HDMI I2S
M
U
X
RTCDIVIDER
From CLKIN32 Pin
HDVPSS HD VENC
PRCM
SYSCLK18
From DEV/AUX Clock, AUD_CLK0/1/2, TCLKIN
Cortex-A8
RTC, GPIO, SyncTimer,
Cortex-A8 (Optional)
M
U
X
TIMER1/2/3/4/5/6/7/8
WDT0 (Optional)
DCAN0/1, SmartReflex
SERDES_CLK
From PLL_VIDEO0
M
U
X
SATA0 SERDES
(Embedded PLL)
M
U
X
EMAC Switch
PCIE SERDES
(Embedded PLL)
RCOSC32K
WDT0 (Optional)
Figure 7-7. System Clocking Overview
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7.4.1
SPRS872B – MAY 2013 – REVISED DECEMBER 2013
Device (DEV) and Auxiliary (AUX) Clock Inputs
The device provides two clock inputs, Device (DEVOSC_MXI/DEV_CLKIN) and Auxiliary
(AUXOSC_MXI/AUX_CLKIN). The Device (DEV) clock is used to generate the majority of the internal
reference clocks, while the Auxiliary (AUX) clock can optionally be used as a source for the Audio and/or
Video PLLs.
The DEV and AUX clocks can be sourced in two ways:
1. Using an external crystal in conjunction with the internal oscillator or
2. Using an external 1.8-V LVCMOS-compatible clock input
Note: The external crystals used with the internal oscillators must operate in fundamental parallel
resonant mode only. There is no overtone support.
The DEV Clock should in most cases be 20 MHz. However, it can optionally range anywhere from 20 - 30
MHz if the following are true:
• The DEV Clock is not used to source the SATA reference clock
• A precise 32768-Hz clock is not needed for Real-Time Clock functionality
• If the boot mode is FAST XIP
The AUX Clock is optional and can range from 20-30 MHz. It can be used to source the Audio and/or
Video PLLs when a very precise audio or video frequency is required.
7.4.1.1
Using the Internal Oscillators
When the internal oscillators are used to generate the DEV and AUX clocks, external crystals are required
to be connected across the DEVOSC or AUXOSC oscillator MXI and MXO pins, along with two load
capacitors (see Figure 7-8 and Figure 7-9). The external crystal load capacitors should also be connected
to the associated oscillator ground pin (VSSA_DEVOSC or VSSA_AUXOSC). The capacitors should not
be connected to board ground (VSS).
Figure 7-8. Device Oscillator
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AUXOSC_MXI/
AUX_CLKIN
AUXOSC_MXO
Rd
(Optional)
Crystal
C1
VSSA_AUXOSC
C2
Figure 7-9. Auxiliary Oscillator
The load capacitors, C1 and C2 in the above pictures, should be chosen such that the below equation is
satisfied. CL in the equation is the load specified by the crystal manufacturer. All discrete components
used to implement the oscillator circuit should be placed as close as possible to the associated oscillator
MXI, MXO, and VSS pins.
CL =
C1 C2
(C1 + C2 )
+ Cshunt
Table 7-10. Input Requirements for Crystal Circuit on the Device Oscillator (DEVOSC)
PARAMETER
MIN
TYP
MAX
4
ms
Crystal Oscillation frequency (1)
20
20
30
MHz
Parallel Load Capacitance (C1 and C2)
12
24
pF
Start-up time (from power up until oscillating at stable frequency)
Crystal ESR
50
Crystal Shunt Capacitance (Cshunt)
5
Crystal Oscillation Mode
Ω
pF
Fundamental Only
Crystal Frequency stability
(1)
UNIT
n/a
±50
ppm
20-MHz DEV clock is required for all bootmodes other than Fast XIP. For more detailed information on boot modes, see the ROM Code
Memory and Peripheral Booting chapter in the device-specific Technical Reference Manual.
Table 7-11. Input Requirements for Crystal Circuit on the Auxiliary Oscillator (AUXOSC)
PARAMETER
MIN
TYP
Start-up time (from power up until oscillating at stable frequency)
UNIT
4
ms
Crystal Oscillation frequency
20
30
MHz
Parallel Load Capacitance (C1 and C2)
12
24
pF
Crystal ESR
50
Crystal Shunt Capacitance (Cshunt)
5
Crystal Oscillation Mode
Ω
pF
Fundamental Only
Crystal Frequency stability (1)
(1)
MAX
n/a
±50
ppm
Applies only when sourcing the HDMI or HDVPSS DAC clocks from the AUXOSC
7.4.1.2
Using a 1.8V LVCMOS-Compatible Clock Input
A 1.8-V LVCMOS-Compatible Clock Input can be used instead of the internal oscillators as the DEV and
AUX clock inputs to the system. The external connections to support this are shown in Figure 7-10 and
Figure 7-11. The DEV_CLKIN and AUX_CLKIN pins are connected to the 1.8-V LVCMOS-Compatible
clock sources. The DEV_MXO and AUX_MXO pins are left unconnected. The VSSA_DEVOSC and
VSSA_AUXOSC pins are connected to board ground (VSS).
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DEVOSC_MXI/
DEV_CLKIN
DEVOSC_MXO
VSSA_DEVOSC
NC
Figure 7-10. 1.8-V LVCMOS-Compatible Clock Input (DEV_OSC)
AUXOSC_MXI/
AUX_CLKIN
AUXOSC_MXO
VSSA_AUXOSC
NC
Figure 7-11. 1.8-V LVCMOS-Compatible Clock Input (AUX_OSC)
The clock source must meet the DEVOSC_MXI/DEV_CLKIN timing requirements shown in Table 7-14,
Timing Requirements for DEVOSC_MXI/DEV_CLKIN.
The clock source must meet the AUXOSC_MXI/AUX_CLKIN timing requirements shown in Table 7-15,
Timing Requirements for AUXOSC_MXI/AUX_CLKIN.
7.4.2
SERDES_CLKN/P Input Clock
A high-quality, low-jitter differential clock source is required for the PCIE PHY and is an optional clock
source for the SATA PHY. The clock is required to be AC coupled to the device's SERDES_CLKP and
SERDES_CLKN pins according to the specifications in Table 7-12. Both the clock source and the coupling
capacitors should be placed physically as close to the processor as possible. In addition, make sure to
follow any PCB routing and termination recommendations that the clock source manufacturer
recommends.
Table 7-12. SERDES_CLKN/P AC Coupling Capacitors Recommendations
PARAMETER
SERDES_CLKN/P AC coupling capacitor value
SERDES_CLKN/P AC coupling capacitor package size (1) (2)
(1)
(2)
MIN
TYP
MAX
0.25
0.27
4.0
UNIT
nF
0402
0603
EIA
L x W, 10 Mil units, that is, a 0402 is a 40 x 20 Mil surface mount capacitor.
The physical size of the capacitor should be as small as practical. Use the same size on both lines in each pair placed side-by-side.
The value of this capacitor depends on several factors including differential input clock swing. For a
100MHz differential clock with an approximate 1V voltage swing, the recommended typical value for the
SerDes Clock AC Coupling Capacitors is 270pF.
Deviating from this recommendation can result in the reduction of clock signal amplitude or lowering the
noise rejection characteristics.
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The differential clock source is required to meet the REFCLK AC Specifications outlined in the PCI
EXPRESS CARD ELECTROMECHANICAL SPECIFICATION, REV. 2.0, at the input to the AC coupling
capacitors.
In addition, LVDS clock sources that are compliant to the above specification, but with the following
exceptions, are also acceptable:
Table 7-13. Acceptable Exceptions to the REFCLK AC Specifications for LVDS Clock Sources
PARAMETER
MIN
MAX
UNIT
VIH
Differential High-Level Input Voltage
125
1000
mV
VIL
Differential Low-Level Input Voltage
-1000
-125
mV
7.4.3
CLKIN32 Input Clock
An external 32768-Hz clock input can optionally be provided at the CLKIN32 pin to serve as a reference
clock in place of the RTCDIVIDER clock for the following Modules:
• RTC
• GPIO0/1/2/3
• TIMER1/2/3/4/5/6/7
• ARM Cortex-A8
• SYNCTIMER
The CLKIN32 source must meet the timing requirements shown in Table 7-16.
7.4.4
Output Clocks Select Logic
The device includes two selectable general-purpose clock outputs (CLKOUT0 and CLKOUT1). The source
for these output clocks is controlled by the CLKOUT_MUX register in the Control Module (see Figure 712).
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CLKOUT_MUX
RESERVED
RCOSC32K Output
PLL_AUDIO
ARM Cortex-A8 Functional Clock / 16
AUX Clock
DEV Clock
PLL_L3L4 Output
PLL_MEDIACTL Output / 2
PLL_HDVPSS Output / 2
PCIE SERDES Observation Clock
CLKIN32
PLL_VIDEO0
PLL_HDVICP
PLL_HDVPSS
SATA0 SERDES Observation Clock
11
10
01
00
PRCM SYSCLK Output
1011-1111
1010
1001
1000
0111
CLKOUT0
0110
CLKOUT1
0101
0100
0011
0010
0001
0000
Figure 7-12. CLKOUTx Source Selection Logic
For detailed information on the CLKOUTx switching characteristics, see Table 7-17.
7.4.5
Input/Output Clocks Electrical Data/Timing
Note: If an external clock oscillator is used, a single clean power supply should be used to power both the
device and the external clock oscillator circuit.
Table 7-14. Timing Requirements for DEVOSC_MXI/DEV_CLKIN (1)
(2) (3)
(see Figure 7-13)
OPP100
NO.
MIN
NOM
50
(2)
(3)
UNIT
1
tc(DMXI)
Cycle time, DEVOSC_MXI/DEV_CLKIN
33.33
50
ns
2
tw(DMXIH)
Pulse duration, DEVOSC_MXI/DEV_CLKIN high
0.45C
0.55C
ns
3
tw(DMXIL)
Pulse duration, DEVOSC_MXI/DEV_CLKIN low
0.45C
0.55C
ns
4
tt(DMXI)
Transition time, DEVOSC_MXI/DEV_CLKIN
7
ns
5
tJ(DMXI)
Period jitter, DEVOSC_MXI/DEV_CLKIN
0.02C
ns
Frequency Stability
(1)
MAX
±50
ppm
The DEVOSC_MXI/DEV_CLKIN frequency and PLL settings should be chosen such that the resulting SYSCLKs and Module Clocks are
within the specific ranges shown in the Section 7.4.7, SYSCLKs and Section 7.4.8, Module Clocks.
The reference points for the rise and fall transitions are measured at VIL MAX and VIH MIN.
C = DEV_CLKIN cycle time in ns. For example, when DEVOSC_MXI/DEV_CLKIN frequency is 20 MHz, use C = 50 ns.
5
1
1
4
2
DEVOSC_MXI/
DEV_CLKIN
3
4
Figure 7-13. DEV_MXI/DEV_CLKIN Timing
Power, Reset, Clocking, and Interrupts
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Table 7-15. Timing Requirements for AUX_MXI/AUX_CLKIN
(1) (2)
(see Figure 7-14)
OPP100
NO.
MIN
NOM
33.3
50
MAX
UNIT
1
tc(AMXI)
Cycle time, AUXOSC_MXI/AUX_CLKIN
50
ns
2
tw(AMXIH)
Pulse duration, AUXOSC_MXI/AUX_CLKIN high
0.45C
0.55C
ns
3
tw(AMXIL)
Pulse duration, AUXOSC_MXI/AUX_CLKIN low
0.45C
0.55C
ns
4
tt(AMXI)
Transition time, AUXOSC_MXI/AUX_CLKIN
7
ns
5
tJ(AMXI)
Period jitter, AUXOSC_MXI/AUX_CLKIN
0.02C
ns
6
Sf
Frequency stability, AUXOSC_MXI/AUX_CLKIN (3)
(1)
(2)
(3)
± 50 ppm
The reference points for the rise and fall transitions are measured at VIL MAX and VIH MIN.
C = AUX_CLKIN cycle time in ns. For example, when AUXOSC_MXI/AUX_CLKIN frequency is 20 MHz, use C = 50 ns.
Applies only when sourcing the HDMI or HDVPSS DAC clocks from the AUXOSC.
5
1
1
4
2
AUXOSC_MXI/
AUX_CLKIN
3
4
Figure 7-14. AUX_MXI/AUX_CLKIN Timing
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Table 7-16. Timing Requirements for CLKIN32
(1) (2)
(see Figure 7-15)
OPP100
NO.
MIN
NOM
MAX
1
tc(CLKIN32)
Cycle time, CLKIN32
2
tw(CLKIN32H)
Pulse duration, CLKIN32 high
0.45C
0.55C
ns
3
tw(CKIN32L)
Pulse duration, CLKIN32 low
0.45C
0.55C
ns
4
tt(CLKIN32)
Transition time, CLKIN32
7
ns
tJ(CLKIN32)
Period jitter, CLKIN32
0.02C
ns
5
(1)
(2)
1/32768
UNIT
s
The reference points for the rise and fall transitions are measured at VIL MAX and VIH MIN.
C = CLKIN32 cycle time in ns. For example, when CLKIN32 frequency is 32768 Hz, use C = 1/32768 s.
5
1
4
1
2
CLKIN32
3
4
Figure 7-15. CLKIN32 Timing
Table 7-17. Switching Characteristics Over Recommended Operating Conditions for CLKOUTx (CLKOUT0
and CLKOUT1) (1) (2)
(see Figure 7-16)
NO.
MIN
MAX
5
UNIT
1
tc(CLKOUTx)
Cycle time, CLKOUTx
2
tw(CLKOUTxH)
Pulse duration, CLKOUTx high
0.45P
0.55P
ns
3
tw(CLKOUTxL)
Pulse duration, CLKOUTx low
0.45P
0.55P
ns
tt(CLKOUTx)
Transition time, CLKOUTx
0.05P
ns
4
(1)
(2)
OPP100
PARAMETER
ns
The reference points for the rise and fall transitions are measured at VOL MAX and VOH MIN.
P = 1/CLKOUTx clock frequency in nanoseconds (ns). For example, when CLKOUTx frequency is 200 MHz, use P = 5 ns.
2
4
1
CLKOUTx
(Divide-by-1)
3
4
Figure 7-16. CLKOUTx Timing
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7.4.6
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PLLs
The device contains 10 top-level PLLs, and embedded PLLs (within the ARM Cortex-A8, PCIE, SATA,
and CSI) that provide clocks to different parts of the system. Figure 7-17 and Figure 7-18 show simplified
block diagrams of the Top-Level PLL and PLL_ARM. In addition, see the System Clocking Overview
(Figure 7-7) for a high-level view of the device clock architecture including the PLL reference clock
sources and connections.
DEV/AUX
Clock
1
(N + 1)
REFCLK
xM
Multiplier
CLKDCO
1
M2
CLKOUT
1
(N 2 + 1)
Figure 7-17. Top-Level PLL Simplified Block Diagram
DEV Clock
1
(N + 1)
REFCLK
x2M
Multiplier
DCOCLK
1
M2
1
2
CLKOUT
1
(N 2 + 1)
Figure 7-18. PLL_ARM Simplified Block Diagram
The reference clock for most of the PLLs comes from the DEV input clock, with select PLLs also having
the option to use the AUX input clock as a reference. Also, each PLL supports a Bypass mode in which
the reference clock can be directly passed to the PLL CLKOUT through a divider. All device PLL’s will
come-up in Bypass mode after reset.
For details on programming the device PLLs, see the Control Module chapter in the device-specific
Technical Reference Manual.
7.4.6.1
PLL Power Supply Filtering
The device PLLs are supplied externally via the VDDA_xPLL_1P8 power-supply pins (where "x"
represents ARM, VID0, VID1, AUDIO, DDR, and/or L3). External filtering must be added on the PLL
supply pins to ensure that the requirements in Table 7-18 are met.
Table 7-18. PLL Power Supply Requirements
PARAMETER
MIN
MAX
Dynamic noise at VDDA_xPLL_1P8 pins
7.4.6.2
50
UNIT
mV p-p
PLL Multipliers and Dividers
The Top-Level and PLL_ARM PLLs support the internal multiplier and divider values shown in Table 7-19,
Top-Level PLL Multiplier and Divider Limits and Table 7-20, PLL_ARM Multiplier and Divider Limits. The
PLLs must be programmed to conform to the various REFCLK, CLKDCO, DCOCLK, and CLKOUT limits
described in Section 7.4.6.3, PLL Frequency Limits.
Table 7-19. Top-Level PLL Multiplier and Divider Limits
PARAMETER
N Pre-Divider
156
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MIN
MAX
0
255
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Table 7-19. Top-Level PLL Multiplier and Divider Limits (continued)
PARAMETER
(1)
MIN
MAX
PLL Multiplier (M)
2
4095 (1)
M2 Post Divider
1
127
N2 Bypass Divider
0
15
MIN
MAX
The PLL Multiplier supports fractional values (up to 18-bits of fraction) except when the PLL Multiplier is > 4093.
Table 7-20. PLL_ARM Multiplier and Divider Limits
PARAMETER
(1)
(2)
N Pre-Divider
0
127
PLL Multiplier (M) (1)
2
2047 (2)
M2 Post Divider
1
31
N2 Bypass Divider
0
15
This parameter describes the limits on the programmable multiplier value M. The multiplication factor for the PLL_ARM is equal to 2 * M
(also see Figure 7-18).
The PLL Multiplier supports fractional values (up to 18-bits of fraction) except when the PLL Multiplier is < 20 OR > 2045.
7.4.6.3
PLL Frequency Limits
Each PLL supports a minimum and maximum operating frequency for its REFCLK, CKLDCO, and
CLKOUT values. The PLLs must be configured not to exceed any of the constraints placed on these
values shown in Table 7-21 through Table 7-23. Care must be taken to stay within these limits when
selecting external clock input frequencies, internal divider values, and PLL multiply ratios. In addition,
limits shown in these tables may be further restricted by the clock frequency limitations of the device
modules using these clocks. For more detailed information on the SYSCLK and Module Clock frequency
limits, see Section 7.4.7, SYSCLKs and Section 7.4.8, Module Clocks.
Table 7-21. Top-Level PLL Frequency Ranges (ALL OPPs)
CLOCK
(1)
(2)
MIN
MAX
UNIT
REFCLK
0.5
2.5
MHz
CLKDCO (HS1) (1)
1000
2000
MHz
CLKDCO (HS2) (2)
500
1000
MHz
CLKOUT
see Table 7-23
see Table 7-23
MHz
The PLL has two modes of operation: HS1 and HS2. The mode of operation should be set, according to the desired CLKDCO
frequency, by programming the SELFREQDCO field of the ADPLLLJx_CLKCTRL registers in the Control Module.
CLKDCO of the PLL_USB is used undivided by the USB modules; therefore, CLKDCO for the PLL_USB PLL must be programmed to
960 MHz for proper operation.
Table 7-22. ARM Cortex-A8 Embedded PLL (PLL_ARM) Frequency Ranges (ALL OPPs)
CLOCK
MIN
MAX
UNIT
REFCLK
0.032
52
MHz
DCOCLK
20
2000
MHz
CLKOUT
see Table 7-23
see Table 7-23
MHz
Table 7-23. PLL CLKOUT Frequency Ranges
PLL
OPP100
MIN
MAX
UNIT
PLL_ARM
10
600
MHz
PLL_HDVICP
10
266
MHz
PLL_L3L4
10
200
MHz
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Table 7-23. PLL CLKOUT Frequency Ranges (continued)
OPP100
PLL
(1)
7.4.6.4
MIN
MAX
UNIT
PLL_DDR
10
400
MHz
PLL_HDVPSS
10
200
MHz
PLL_AUDIO
10
200
MHz
PLL_MEDIACTL
10
400
MHz
PLL_USB
10 (1)
960
MHz
PLL_VIDEO0
10
200
MHz
PLL_VIDEO1
10
200
MHz
PLL_VIDEO2
10
200
MHz
When the USB is used, PLL_USB must be fixed at 960 MHz.
PLL Register Description(s)
The PLL Control Registers reside in the Control Module and are listed in Section 4.1, Control Module of
this datasheet.
7.4.7
SYSCLKs
In some cases, the system clock inputs and PLL outputs are sent to the PRCM Module for division and
multiplexing before being routed to the various device Modules. These clock outputs from the PRCM
Module are called SYSCLKs. Table Table 7-24 lists the device SYSCLKs along with their maximum
supported clock frequencies. In addition, limits shown in these tables may be further restricted by the clock
frequency limitations of the device modules using these clocks. For more details on Module Clock
frequency limits, see Section 7.4.8 Module Clocks.
NOTE
For supported OPP frequencies, see Table 7-3, Device Operating Points (OPPs).
Table 7-24. Maximum SYSCLK Clock Frequencies
158
SYSCLK
MAX CLOCK FREQUENCY
OPP100 (MHz)
SYSCLK1
RSV
SYSCLK2
RSV
SYSCLK3
266
SYSCLK4
220
SYSCLK5
RSV
SYSCLK6
110
SYSCLK7
RSV
SYSCLK8
192
SYSCLK9
RSV
SYSCLK10
48
SYSCLK11
RSV
SYSCLK12
RSV
SYSCLK13
RSV
SYSCLK14
27
SYSCLK15
RSV
SYSCLK16
27
SYSCLK17
RSV
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Table 7-24. Maximum SYSCLK Clock Frequencies (continued)
7.4.8
SYSCLK
MAX CLOCK FREQUENCY
OPP100 (MHz)
SYSCLK18
0.032768
SYSCLK19
192
SYSCLK20
192
SYSCLK21
192
SYSCLK22
RSV
SYSCLK23
RSV
Module Clocks
Device Modules either receive their clock directly from an external clock input, directly from a PLL, or from
a PRCM SYSCLK output. Table 7-25 lists the clock source options for each Module on this device, along
with the maximum frequency that Module can accept. To ensure proper Module functionality, the device
PLLs and dividers must be programmed not to exceed the maximum frequencies listed in this table.
Table 7-25. Maximum Module Clock Frequencies
MODULE
CLOCK SOURCE(S)
MAX FREQUENCY
OPP100 (MHz)
Cortex-A8
PLL_ARM
SYSCLK18
600
DCAN0/1
DEV Clock
30
DDR0
PLL_DDR
400
DMM
PLL_DDR/2
200
EDMA
SYSCLK4
220
EMAC Switch (GMII)
SATA0 SERDES
PLL_VIDEO0
Fixed 125
EMAC Switch (RGMII)
PLL_VIDEO0
SATA0 SERDES
Fixed 250
EMAC Switch (RMII and MII)
SATA0 SERDES
PLL_VIDEO0
EMAC_RMREFCLK Pin
Fixed 50
Face Detect
SYSCLK4
220
GPIO
SYSCLK6
110
GPIO Debounce
SYSCLK18
Fixed 0.032768
GPMC
SYSCLK6
110
HDMI
PLL_VIDEO2
186
HDMI CEC
SYSCLK10
Fixed 48
HDMI I2S
SYSCLK20
SYSCLK21
AUD_CLK0/1/2
AUX Clock
50
HDVICP2
SYSCLK3
266
HDVPSS
PLL_HDVPSS
200
HDVPSS VOUT1
PLL_VIDEO2
HDMI PHY
186
HDVPSS VOUT0
PLL_VIDEO1
PLL_VIDEO2
165
HDVPSS SD VENC
PLL_VIDEO0
Fixed 54
HDVPSS HD VENC
PLL_VIDEO0
PLL_VIDEO1
HDMI
Fixed 148.5
I2C0/1/2/3
SYSCLK10
48
ISS
PLL_ MEDIACTL
400
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Table 7-25. Maximum Module Clock Frequencies (continued)
160
MODULE
CLOCK SOURCE(S)
MAX FREQUENCY
OPP100 (MHz)
L3 Fast
SYSCLK4
220
L3 Medium
SYSCLK4
220
L3 Slow
SYSCLK6
110
L4 Fast
SYSCLK4
220
L4 Slow
SYSCLK6
110
Mailbox
SYSCLK6
110
McASP
SYSCLK6
110
McASP0/1 AUX_CLK
SYSCLK20
SYSCLK21
192
Media Controller
PLL_MEDIACTL
400
MMCSD0/1/2
SYSCLK8
192
OCMC RAM
SYSCLK4
220
PCIe SERDES
SERDES_CLKx Pins
100
SATA0 SERDES
DEV Clock
SERDES_CLKx Pins
20 or 100
SmartReflex
DEV Clock
30
SPI0/1/2/3
SYSCLK10
48
Spinlock
SYSCLK6
110
Sync Timer
SYSCLK18
Fixed 0.032768
TIMER1/2/3/4/5/6/7/8
SYSCLK18
DEV Clock
AUX Clock
AUD_CLK0/1/2
TCLKIN
30
UART0/1/2
SYSCLK10
48
USB
PLL_USB CLKDCO
Fixed 960
WDT0
RTCDIVIDER
RCOSC32K
Fixed 0.032768
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7.5
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Interrupts
The device has a large number of interrupts to service the needs of its many peripherals and subsystems.
The ARM Cortex-A8 and Media Controller are capable of servicing these interrupts. The following sections
list the device interrupt mapping and multiplexing schemes.
7.5.1
ARM Cortex-A8 Interrupts
The ARM Cortex-A8 Interrupt Controller (AINTC) is responsible for prioritizing all service requests from the
System peripherals and generating either IRQs or FIQs to the Cortex-A8. The AINTC has the capability to
handle up to 128 requests, and the priority of the interrupt inputs are programmable. Table 7-26 lists the
interrupt sources for the AINTC.
For more details on ARM Cortex-A8 interrupt control, see the Interrupt Controller section of the Chip Level
Resources chapter in the device-specific Technical Reference Manual.
Table 7-26. ARM Cortex-A8 Interrupt Controller (AINTC) Interrupt Sources
Cortex-A8
INTERRUPT NUMBER
ACRONYM
SOURCE
0
EMUINT
Cortex-A8 Emulation
1
COMMTX
Cortex-A8 Emulation
2
COMMRX
Cortex-A8 Emulation
3
BENCH
Cortex-A8 Emulation
4
ELM_IRQ
5
–
Reserved
6
–
Reserved
7
NMI
NMIn Pin
8
–
Reserved
ELM
9
L3DEBUG
L3 Interconnect
10
L3APPINT
L3 Interconnect
11
TINT8
12
EDMACOMPINT
13
EDMAMPERR
EDMA Memory Protection Error
14
EDMAERRINT
EDMA CC Error
TIMER8
EDMA CC Completion
15
WDTINT0
Watchdog Timer 0
16
SATAINT0
SATA0
17
USBSSINT
USB Subsystem
18
USBINT0
USB0
USB1
19
USBINT1
20-27
–
Reserved
28
SDINT1
MMC/SD1
29
SDINT2
MMC/SD2
30
I2CINT2
I2C2
31
I2CINT3
I2C3
32
GPIOINT2A
GPIO2 A
33
GPIOINT2B
GPIO2 B
34
USBWAKEUP
USB Subsystem Wakeup
35
PCIeWAKEUP
PCIe Wakeup
36
DSSINT
HDVPSS
37
–
Reserved
38
HDMIINT
39
ISS_IRQ_5
HDMI
ISS
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Table 7-26. ARM Cortex-A8 Interrupt Controller (AINTC) Interrupt Sources (continued)
162
Cortex-A8
INTERRUPT NUMBER
ACRONYM
40
3PGSWRXTHR0
EMAC Switch RX Threshold
41
3PGSWRXINT0
EMAC Switch Receive
42
3PGSWTXINT0
EMAC Switch Transmit
EMAC Switch Miscellaneous
SOURCE
43
3PGSWMISC0
44-47
–
48
PCIINT0
PCIe
49
PCIINT1
PCIe
50
PCIINT2
PCIe
51
PCIINT3
PCIe
52
DCAN0_INT0
DCAN0
53
DCAN0_INT1
DCAN0
54
DCAN0_PARITY
55
DCAN1_INT0
DCAN1
56
DCAN1_INT1
DCAN1
57
DCAN1_PARITY
58-61
–
62
GPIOINT3A
GPIO3
63
GPIOINT3B
GPIO3
64
SDINT0
MMC/SD0
65
SPIINT0
SPI0
Reserved
DCAN0 Parity
DCAN1 Parity
Reserved
66
-
67
TINT1
Reserved
TIMER1
68
TINT2
TIMER2
69
TINT3
TIMER3
70
I2CINT0
I2C0
71
I2CINT1
I2C1
72
UARTINT0
UART0
73
UARTINT1
UART1
74
UARTINT2
UART2
75
RTCINT
76
RTCALARMINT
77
MBINT
78
–
RTC
RTC Alarm
Mailbox
Reserved
79
PLLINT
80
MCATXINT0
PLL Recalculation Interrupt
McASP0 Transmit
81
MCARXINT0
McASP0 Receive
82
MCATXINT1
McASP1 Transmit
83
MCARXINT1
McASP1 Receive
84
–
Reserved
85
–
Reserved
86
–
Reserved
87
–
Reserved
88
–
Reserved
89
–
Reserved
90
SMRFLX_HDVICP
91
–
92
TINT4
SmartReflex HDVICP Domain
Reserved
TIMER4
Power, Reset, Clocking, and Interrupts
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Table 7-26. ARM Cortex-A8 Interrupt Controller (AINTC) Interrupt Sources (continued)
Cortex-A8
INTERRUPT NUMBER
ACRONYM
93
TINT5
TIMER5
94
TINT6
TIMER6
95
TINT7
TIMER7
96
GPIOINT0A
GPIO0
97
GPIOINT0B
GPIO0
98
GPIOINT1A
GPIO1
SOURCE
99
GPIOINT1B
GPIO1
100
GPMCINT
GPMC
101
DDRERR
DDR
102
–
Reserved
103
HDVICPCONT1SYNC
HDVICP2
104
HDVICPCONT2SYNC
HDVICP2
105
–
Reserved
106
–
Reserved
107
IVA0MBOXINT
108
–
Reserved
109
–
Reserved
110
–
Reserved
111
–
Reserved
112
TCERRINT0
EDMA TC 0 Error
113
TCERRINT1
EDMA TC 1 Error
114
TCERRINT2
EDMA TC 2 Error
115
TCERRINT3
EDMA TC 3 Error
116-119
–
120
SMRFLX_ARM
121
SMRFLX_CORE
HDVICP2 Mailbox
Reserved
SmartReflex ARM Domain
SmartReflex CORE Domain
122
–
123
MCMMUINT
Reserved
124
DMMINT
DMM
125
SPIINT1
SPI1
126
SPIINT2
SPI2
127
SPIINT3
SPI3
Media Controller
Power, Reset, Clocking, and Interrupts
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8 Peripheral Information and Timings
8.1
Parameter Information
Tester Pin Electronics
42 Ω
3.5 nH
Transmission Line
Z0 = 50 Ω
(see Note)
4.0 pF
1.85 pF
Data Sheet Timing Reference Point
Output
Under
Test
Device Pin
(see Note)
NOTE: The data sheet provides timing at the device pin. For output timing analysis, the tester pin electronics and its transmission line effects must be
taken into account. A transmission line with a delay of 2 ns can be used to produce the desired transmission line effect. The transmission line is
intended as a load only. It is not necessary to add or subtract the transmission line delay (2 ns) from the data sheet timings.
Input requirements in this data sheet are tested with an input slew rate of < 4 Volts per nanosecond (4 V/ns) at the device pin.
Figure 8-1. Test Load Circuit for AC Timing Measurements
The load capacitance value stated is only for characterization and measurement of AC timing signals. This
load capacitance value does not indicate the maximum load the device is capable of driving.
8.1.1
1.8-V and 3.3-V Signal Transition Levels
All input and output timing parameters are referenced to Vref for both "0" and "1" logic levels. For 3.3-V I/O,
Vref = 1.5 V. For 1.8-V I/O, Vref = 0.9 V.
Vref
Figure 8-2. Input and Output Voltage Reference Levels for AC Timing Measurements
All rise and fall transition timing parameters are referenced to VIL MAX and VIH MIN for input clocks, VOL
MAX and VOH MIN for output clocks.
Vref = VIH MIN (or VOH MIN)
Vref = VIL MAX (or VOL MAX)
Figure 8-3. Rise and Fall Transition Time Voltage Reference Levels
8.1.2
3.3-V Signal Transition Rates
All timings are tested with an input edge rate of 4 volts per nanosecond (4 V/ns).
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8.1.3
SPRS872B – MAY 2013 – REVISED DECEMBER 2013
Timing Parameters and Board Routing Analysis
The timing parameter values specified in this data manual do not include delays by board routings. As a
good board design practice, such delays must always be taken into account. Timing values may be
adjusted by increasing/decreasing such delays. TI recommends utilizing the available I/O buffer
information specification (IBIS) models to analyze the timing characteristics correctly. If needed, external
logic hardware such as buffers may be used to compensate any timing differences.
8.2
Recommended Clock and Control Signal Transition Behavior
All clocks and control signals must transition between VIH and VIL (or between VIL and VIH) in a monotonic
manner.
NOTE
For supported OPP frequencies, see Table 7-3, Device Operating Points (OPPs).
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8.3
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Audio Tracking Logic (ATL)
8.3.1
Overview
The device contains four ATL modules that can be used for asynchronous sample rate conversion of
audio. The ATL calculates the error between two time bases, such as audio syncs, and optionally
generates an averaged clock using cycle stealing via software.
For more detailed information on the ATL peripheral, see the Audio Tracking Logic (ATL) chapter of the
device-specific Technical Reference Manual.
8.3.2
ATL Peripheral Registers
This ATL peripheral registers are described in the device-specific Technical Reference Manual (TRM).
Each register is documented as an offset from a base address for the peripheral. The base addresses for
all of the peripherals are in the device memory map (see Section 2.10).
8.3.3
ATL Electrical Data/Timing
Table 8-1. Switching Characteristics Over Recommended Operating Conditions for ATL_CLKOUTx
NO.
OPP100/OPP120/
Turbo
PARAMETER
MIN
1
tc(ATLCLKOUT)
Cycle time, ATL_CLKOUTx
20
ns
(1)
ns
ns
2
tw(ATLCLKOUTL)
Pulse Duration, ATL_CLKOUTx low
0.45*P - M
3
tw(ATLCLKOUTH)
Pulse Duration, ATL_CLKOUTx high
0.45*P - M (1)
(1)
UNIT
MAX
P = ATL_CLKOUTx period.
M = internal ATL PCLK period.
1
2
ATL_CLKOUTx
3
Figure 8-4. ATL_CLKOUTx Timing
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8.4
SPRS872B – MAY 2013 – REVISED DECEMBER 2013
Controller Area Network Interface (DCAN)
The device provides two DCAN interfaces for supporting distributed realtime control with a high level of
security. The DCAN interfaces implement the following features:
• Supports CAN protocol version 2.0 part A, B
• Bit rates up to 1 MBit/s
• 64 message objects
• Individual identifier mask for each message object
• Programmable FIFO mode for message objects
• Programmable loop-back modes for self-test operation
• Suspend mode for debug support
• Software module reset
• Automatic bus on after Bus-Off state by a programmable 32-bit timer
• Message RAM parity check mechanism
• Direct access to Message RAM during test mode
• CAN Rx/Tx pins are configurable as general-purpose IO pins
• Two interrupt lines (plus additional parity-error interrupts line)
• RAM initialization
• DMA support
For more detailed information on the DCAN peripheral, see the DCAN Controller Area Network chapter in
the device-specific Technical Reference Manual.
8.4.1
DCAN Peripheral Register Descriptions
The DCAN peripheral registers are described in the device-specific Technical Reference Manual. Each
register is documented as an offset from a base address for the peripheral. The base addresses for all of
the peripherals are in the device memory map (see Section 2.10).
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DCAN Electrical Data/Timing
Table 8-2. Timing Requirements for DCANx Receive (1) (see Figure 8-5)
OPP100/OPP120/Turbo
NO.
1
(1)
MIN
f(baud)
Maximum programmable baud rate
tw(DCANRX)
Pulse duration, receive data bit (DCANx_RX)
NOM
UNIT
MAX
1
H-2
Mbps
H+2
ns
H = period of baud rate, 1/programmed baud rate.
Table 8-3. Switching Characteristics Over Recommended Operating Conditions for DCANx Transmit
(1)
(see Figure 8-5)
NO.
2
(1)
OPP100/OPP120/
Turbo
PARAMETER
f(baud)
Maximum programmable baud rate
tw(DCANTX)
Pulse duration, transmit data bit (DCANx_TX)
UNIT
MIN
MAX
H-2
H+2
1
Mbps
ns
H = period of baud rate, 1/programmed baud rate.
1
DCANx_RX
2
DCANx_TX
Figure 8-5. DCANx Timings
168
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8.5
SPRS872B – MAY 2013 – REVISED DECEMBER 2013
EDMA
The EDMA controller handles all data transfers between memories and the device slave peripherals on
the device. These data transfers include cache servicing, non-cacheable memory accesses, userprogrammed data transfers, and host accesses.
8.5.1
EDMA Channel Synchronization Events
The EDMA channel controller supports up to 64 channels which service peripherals and memory. Each
EDMA channel is mapped to a default EDMA synchronization event as shown in Table 8-4. In addition,
each EDMA channel can alternatively be mapped to one of the 31 multiplexed EDMA synchronization
events shown in Table 8-5. The EVT_MUX_x registers in the Control Module are used to select between
the default event and the multiplexed events for each channel.
For more detailed information on the EDMA module and how EDMA events are enabled, captured,
processed, linked, chained, cleared, and more, see the Enhanced Direct Memory Access Controller
chapter in the device-specific Technical Reference Manual.
Table 8-4. EDMA Default Synchronization Events
EVENT
NUMBER
DEFAULT
EVENT NAME
DEFAULT EVENT DESCRIPTION
0-1
–
2
SDTXEVT1
Reserved
SD1 Transmit
SD1 Receive
3
SDRXEVT1
4-7
–
8
AXEVT0
McASP0 Transmit
Reserved
9
AREVT0
McASP0 Receive
10
AXEVT1
McASP1 Transmit
11
AREVT1
McASP1 Receive
12
–
Reserved
13
–
Reserved
14
–
Reserved
15
–
Reserved
16
SPI0XEVT0
SPI0 Transmit 0
17
SPI0REVT0
SPI0 Receive 0
18
SPI0XEVT1
SPI0 Transmit 1
19
SPI0REVT1
SPI0 Receive 1
20
SPI0XEVT2
SPI0 Transmit 2
21
SPI0REVT2
SPI0 Receive 2
22
SPI0XEVT3
SPI0 Transmit 3
23
SPI0REVT3
SPI0 Receive 3
24
SDTXEVT0
SD0 Transmit
25
SDRXEVT0
SD0 Receive
26
UTXEVT0
UART0 Transmit
27
URXEVT0
UART0 Receive
28
UTXEVT1
UART1 Transmit
29
URXEVT1
UART1 Receive
30
UTXEVT2
UART2 Transmit
31
URXEVT2
UART2 Receive
42
SPI1XEVT0
SPI1 Transmit 0
43
SPI1REVT0
SPI1 Receive 0
44
SPI1XEVT1
SPI1 Transmit 1
45
SPI1REVT1
SPI1 Receive 1
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Table 8-4. EDMA Default Synchronization Events (continued)
EVENT
NUMBER
DEFAULT
EVENT NAME
DEFAULT EVENT DESCRIPTION
46
–
48
TINT4
Reserved
TIMER4
49
TINT5
TIMER5
50
TINT6
TIMER6
51
TINT7
TIMER7
52
GPMCEVT
GPMC
58
I2CTXEVT0
I2C0 Transmit
59
I2CRXEVT0
I2C0 Receive
60
I2CTXEVT1
I2C1 Transmit
61
I2CRXEVT1
I2C1 Receive
62
–
Reserved
63
–
Reserved
Table 8-5. EDMA Multiplexed Synchronization Events
170
EVT_MUX_x
VALUE
MULTIPLEXED
EVENT NAME
0
-
Default Event
1
SDTXEVT2
SD2 Transmit
2
SDRXEVT2
SD2 Receive
3
I2CTXEVT2
I2C2 Transmit
4
I2CRXEVT2
I2C2 Receive
5
I2CTXEVT3
I2C3 Transmit
6
I2CRXEVT3
I2C3 Receive
7
–
Reserved
8
–
Reserved
9
–
Reserved
10
–
Reserved
11
–
Reserved
12
–
Reserved
16
SPI2XEVT0
SPI2 Transmit 0
17
SPI2REVT0
SPI2 Receive 0
18
SPI2XEVT1
SPI2 Transmit 1
19
SPI2REVT1
SPI2 Receive 1
20
SPI3XEVT0
SPI3 Transmit 0
21
SPI3REVT0
SPI3 Receive 0
22
–
23
TINT1
TIMER1
24
TINT2
TIMER2
25
TINT3
TIMER3
26
–
Reserved
27
–
Reserved
28
EDMAEVT0
EDMA_EVT0 Pin
29
EDMAEVT1
EDMA_EVT1 Pin
30
EDMAEVT2
EDMA_EVT2 Pin
31
EDMAEVT3
EDMA_EVT3 Pin
MULTIPLEXED EVENT DESCRIPTION
Reserved
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8.5.2
SPRS872B – MAY 2013 – REVISED DECEMBER 2013
EDMA Peripheral Register Description
The EDMA peripheral registers are described in the device-specific Technical Reference Manual. Each
register is documented as an offset from a base address for the peripheral. The base addresses for all of
the peripherals are in the device memory map (see Section 2.10).
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8.6
8.6.1
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Emulation Features and Capability
Advanced Event Triggering (AET)
The device supports Advanced Event Triggering (AET). This capability can be used to debug complex
problems as well as understand performance characteristics of user applications. AET provides the
following capabilities:
• Hardware Program Breakpoints: specify addresses or address ranges that can generate events such
as halting the processor or triggering the trace capture.
• Data Watchpoints: specify data variable addresses, address ranges, or data values that can generate
events such as halting the processor or triggering the trace capture.
• Counters: count the occurrence of an event or cycles for performance monitoring.
• State Sequencing: allows combinations of hardware program breakpoints and data watchpoints to
precisely generate events for complex sequences.
For more information on AET, see the following documents:
• Using Advanced Event Triggering to Find and Fix Intermittent Real-Time Bugs application report
(Literature Number: SPRA753).
• Using Advanced Event Triggering to Debug Real-Time Problems in High Speed Embedded
Microprocessor Systems application report (Literature Number: SPRA387).
8.6.2
Trace
The device supports Trace at the Cortex™-A8 and System levels. Trace is a debug technology that
provides a detailed, historical account of application code execution, timing, and data accesses. Trace
collects, compresses, and exports debug information for analysis. The debug information can be exported
to the Embedded Trace Buffer (ETB), or to the 5-pin Trace Interface (system trace only). Trace works in
real-time and does not impact the execution of the system.
For more information on board design guidelines for Trace Advanced Emulation, see the Emulation and
Trace Headers Technical Reference Manual (Literature Number: SPRU655).
8.6.3
IEEE 1149.1 JTAG
The JTAG (IEEE Standard 1149.1-1990 Standard-Test-Access Port and Boundary Scan Architecture)
interface is used for BSDL testing and emulation of the device. The TRST pin only needs to be released
when it is necessary to use a JTAG controller to debug the device or exercise the device's boundary scan
functionality. For maximum reliability, the device includes an internal pulldown (IPD) on the TRST pin to
ensure that TRST is always asserted upon power up and the device's internal emulation logic is always
properly initialized. JTAG controllers from Texas Instruments actively drive TRST high. However, some
third-party JTAG controllers may not drive TRST high but expect the use of a pullup resistor on TRST.
When using this type of JTAG controller, assert TRST to initialize the device after powerup and externally
drive TRST high before attempting any emulation or boundary-scan operations.
The main JTAG features include:
• 32KB embedded trace buffer (ETB)
• 5-pin system trace interface for debug
• Supports Advanced Event Triggering (AET)
• All processors can be emulated via JTAG ports
• All functions on EMU pins of the device:
– EMU[1:0] - cross-triggering, boot mode (WIR), STM trace
– EMU[4:2] - STM trace only (single direction)
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8.6.3.1
SPRS872B – MAY 2013 – REVISED DECEMBER 2013
JTAG ID (JTAGID) Register Description
Table 8-6. JTAG ID Register (1)
(1)
(2)
HEX ADDRESS
ACRONYM
0x4814 0600
JTAGID
REGISTER NAME
JTAG Identification Register (2)
IEEE Standard 1149.1-1990 Standard-Test-Access Port and Boundary Scan Architecture.
Read-only. Provides the device 32-bit JTAG ID.
The JTAG ID register is a read-only register that identifies to the customer the JTAG/device ID. For this
device, the JTAG ID register resides at address location 0x4814 0600. For the actual register bit names
and their associated bit field descriptions, see Figure 8-6 and Table 8-7.
31
28 27
12 11
1
0
VARIANT (4bit)
PART NUMBER (16-bit)
MANUFACTURER (11-bit)
LSB
R-xxxx
R-1011 1001 0110 1011
R-0000 0010 111
R-1
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Figure 8-6. JTAG ID Register Description - Device Register Value: 0x0B8F 202F
Table 8-7. JTAG ID Register Selection Bit Descriptions
Bit
Field
Description
31:28
VARIANT
Variant (4-bit) value. Device value: xxxx. This value reflects the device silicon revision [For example, 0x0
(0000) for initial silicon (1.0)]. For more detailed information on the current device silicon revision, see the
device-specific Silicon Errata.
27:12
PART NUMBER
Part Number (16-bit) value. Device value: 0xB96B (1011 1001 0110 1011)
11:1
MANUFACTURER
Manufacturer (11-bit) value. Device value: 0x017 (0000 0010 111)
LSB
LSB. This bit is read as a ""1 for this device.
0
8.6.3.2
JTAG Electrical Data/Timing
Table 8-8. Timing Requirements for IEEE 1149.1 JTAG
(see Figure 8-7)
OPP100/OPP120/
Turbo
NO.
MIN
UNIT
MAX
1
tc(TCK)
Cycle time, TCK
59
ns
1a
tw(TCKH)
Pulse duration, TCK high (40% of tc)
23.6
ns
1b
tw(TCKL)
Pulse duration, TCK low (40% of tc)
23.6
ns
3
tsu(TDI-TCK)
Input setup time, TDI valid to TCK high (20% of (tc * 0.5))
5.9
ns
3
tsu(TMS-TCK)
Input setup time, TMS valid to TCK high (20% of (tc * 0.5))
5.9
ns
th(TCK-TDI)
Input hold time, TDI valid from TCK high
29.5
ns
th(TCK-TMS)
Input hold time, TMS valid from TCK high
29.5
ns
4
Table 8-9. Switching Characteristics Over Recommended Operating Conditions for IEEE 1149.1 JTAG
(see Figure 8-7)
NO.
2
(1)
PARAMETER
td(TCKL-TDOV)
Delay time, TCK low to TDO valid
OPP100/OPP120/
Turbo
MIN
MAX
0
23.575 (1)
UNIT
ns
(0.5 * tc) - 2
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1
1a
1b
TCK
2
TDO
3
4
TDI/TMS
Figure 8-7. JTAG Timing
Table 8-10. Timing Requirements for IEEE 1149.1 JTAG With RTCK
(see Figure 8-7)
OPP100/OPP120/
Turbo
NO.
MIN
UNIT
MAX
1
tc(TCK)
Cycle time, TCK
59
ns
1a
tw(TCKH)
Pulse duration, TCK high (40% of tc)
23.6
ns
1b
tw(TCKL)
Pulse duration, TCK low (40% of tc)
23.6
ns
3
tsu(TDI-TCK)
Input setup time, TDI valid to TCK high (20% of (tc * 0.5))
5.9
ns
3
tsu(TMS-TCK)
Input setup time, TMS valid to TCK high (20% of (tc * 0.5))
5.9
ns
th(TCK-TDI)
Input hold time, TDI valid from TCK high
29.5
ns
th(TCK-TMS)
Input hold time, TMS valid from TCK high
29.5
ns
4
Table 8-11. Switching Characteristics Over Recommended Operating Conditions for IEEE 1149.1 JTAG
With RTCK
(see Figure 8-8)
NO.
OPP100/OPP120/
Turbo
PARAMETER
UNIT
MIN
MAX
0
24
5
td(TCK-RTCK)
Delay time, TCK to RTCK with no selected subpaths (that is,
ICEPick is the only tap selected - when the ARM is in the scan
chain, the delay time is a function of the ARM functional clock.)
6
tc(RTCK)
Cycle time, RTCK
59
ns
7
tw(RTCKH)
Pulse duration, RTCK high (40% of tc)
23.6
ns
8
tw(RTCKL)
Pulse duration, RTCK low (40% of tc)
23.6
ns
ns
5
TCK
6
7
8
RTCK
Figure 8-8. JTAG With RTCK Timing
174
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Table 8-12. Switching Characteristics Over Recommended Operating Conditions for STM Trace
(see Figure 8-9)
NO.
OPP100/OPP120/
Turbo
PARAMETER
MIN
1
2
3
(1)
UNIT
MAX
tw(EMUH50)
Pulse duration, EMUx high detected at 50% VOH with 60/40 duty
cycle
4 (1)
ns
tw(EMUH90)
Pulse duration, EMUx high detected at 90% VOH
3.5
ns
tw(EMUL50)
Pulse duration, EMUx low detected at 50% VOH with 60/40 duty
cycle
4 (1)
ns
tw(EMUL10)
Pulse duration, EMUx low detected at 10% VOH
3.5
ns
tsko(EMU)
Output skew time, time delay difference between EMUx pins
configured as trace.
tskp(EMU)
Pulse skew, magnitude of difference between high-to-low (tPHL)
and low-to-high (tPLH) propagation delays
tsldp_o(EMU)
Output slew rate EMUx
-0.5
0.5
ns
0.6 (1)
ns
3.3
V/ns
This parameter applies to the maximum trace export frequency operating in a 40/60 duty cycle.
Buffer
Inputs
A
Buffers
EMUx Pins
B
tPLH
tPHL
1
2
B
A
3
C
C
Figure 8-9. STM Trace Timing
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Ethernet MAC Switch (EMAC SW)
The EMAC SW controls the flow of packet data between the device and two external Ethernet PHYs, with
hardware flow control and quality-of-service (QOS) support. The EMAC SW contains a 3-port gigabit
switch, where one port is internally connected and the other two ports are brought out externally. Each of
the external EMAC ports supports 10Base-T (10 Mbits/second [Mbps]), and 100BaseTX (100 Mbps), in
either half- or full-duplex mode, and 1000BaseT (1000 Mbps) in full-duplex mode.
The EMAC SW controls the flow of packet data from the device to the external PHYs. The EMAC0/1 ports
on the device support four interface modes: Media Independent Interface (MII), Gigabit Media
Independent Interface (GMII), Reduced Media Independent Interface (RMII) and Reduced Gigabit Media
Independent Interface (RGMII). In addition, a single MDIO interface is pinned out to control the PHY
configuration and status monitoring. Multiple external PHYs can be controlled by the MDIO interface.
The EMAC SW module conforms to the IEEE 802.3-2002 standard, describing the “Carrier Sense Multiple
Access with Collision Detection (CSMA/CD) Access Method and Physical Layer” specifications. The IEEE
802.3 standard has also been adopted by ISO/IEC and re-designated as ISO/IEC 8802-3:2000(E).
Deviating from this standard, the EMAC SW module does not use the Transmit Coding Error signal
MTXER. Instead of driving the error pin when an underflow condition occurs on a transmitted frame, the
EMAC SW will intentionally generate an incorrect checksum by inverting the frame CRC, so that the
transmitted frame will be detected as an error by the network. In addition, the EMAC SW I/Os operate at
3.3 V and are not compatible with 2.5-V I/O signaling. Therefore, only Ethernet PHYs with 3.3-V I/O
interface should be used.
In networking systems, packet transmission and reception are critical tasks. The communications port
programming interface (CPPI) protocol maximizes the efficiency of interaction between the host software
and communications modules. The CPPI block contains 2048 words of 32-bit buffer descriptor memory
that holds up to 512 buffer descriptors.
Ethernet port mirroring is not supported internally on this device. This function is supported by using an
external Ethernet repeater.
For more detailed information on the EMAC SW module, see the 3PSW Ethernet Subsystem chapter in
the device-specific Technical Reference Manual.
8.7.1
EMAC Peripheral Register Descriptions
The EMAC peripheral registers are described in the device-specific Technical Reference Manual. Each
register is documented as an offset from a base address for the peripheral. The base addresses for all of
the peripherals are in the device memory map (see Section 2.10).
176
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EMAC Electrical Data/Timing
8.7.2.1
EMAC MII and GMII Electrical Data/Timing
GMII mode is not supported for OPP50.
Table 8-13. Timing Requirements for EMAC[x]_MRCLK - [G]MII Operation
(see Figure 8-10)
OPP100/OPP120/Turbo
1000 Mbps (1 Gbps)
(GMII Only)
NO.
MIN
1
tc(MRCLK)
Cycle time, EMAC[x]_MRCLK
2
MAX
100 Mbps
MIN
10 Mbps
MAX
MIN
UNIT
MAX
8
40
400
ns
tw(MRCLKH)
Pulse duration,
EMAC[x]_MRCLK high
2.8
14
140
ns
3
tw(MRCLKL)
Pulse duration,
EMAC[x]_MRCLK low
2.8
14
140
ns
4
tt(MRCLK)
Transition time,
EMAC[x]_MRCLK
1
3
3
ns
4
1
3
2
EMAC[x]_MRCLK
4
Figure 8-10. EMAC[x]_MRCLK Timing (EMAC Receive) - [G]MII Operation
Table 8-14. Timing Requirements for EMAC[x]_MTCLK - [G]MII Operation
(see Figure 8-15)
OPP100/OPP120/Turbo
1000 Mbps (1 Gbps)
(GMII Only)
NO.
MIN
1
MAX
100 Mbps
MIN
10 Mbps
MAX
MIN
UNIT
MAX
tc(MTCLK)
Cycle time, EMAC[x]_MTCLK
8
40
400
ns
2
tw(MTCLKH)
Pulse duration,
EMAC[x]_MTCLK high
2.8
14
140
ns
3
tw(MTCLKL)
Pulse duration,
EMAC[x]_MTCLK low
2.8
14
140
ns
4
tt(MTCLK)
Transition time,
EMAC[x]_MTCLK
1
3
3
4
1
2
ns
3
EMAC[x]_MTCLK
4
Figure 8-11. EMAC[x]_MTCLK Timing (EMAC Transmit) - [G]MII Operation
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Table 8-15. Timing Requirements for EMAC [G]MII Receive 10/100/1000 Mbit/s
(see Figure 8-12)
OPP100/OPP120/Turbo
1000 Mbps (1
Gbps)
NO.
MIN
100/10 Mbps
MAX
MIN
UNIT
MAX
tsu(MRXD-MRCLK)
1
tsu(MRXDV-MRCLK)
Setup time, receive selected signals valid before
EMAC[1:0]_MRCLK
3.14
8
ns
Hold time, receive selected signals valid after
EMAC[1:0]_MRCLK
1.09
8
ns
tsu(MRXER-MRCLK)
th(MRCLK-MRXD)
2
th(MRCLK-MRXDV)
th(MRCLK-MRXER)
1
2
EMAC[x]_MRCLK (Input)
EMAC[x]_MRXD3−EMAC[x]_MRXD0,
EMAC[x]_MRXDV, EMAC[x]_MRXER (Inputs)
Figure 8-12. EMAC Receive Interface Timing [G]MII Operation
Table 8-16. Switching Characteristics Over Recommended Operating Conditions for EMAC [G]MII
Transmit 10/100 Mbits/s
(see Figure 8-13)
OPP100/OPP120/
Turbo
NO.
1
PARAMETER
td(MTXCLK-MTXD)
td(MTCLK-MTXEN)
UNIT
100/10 Mbps
MIN
MAX
0
25
Delay time, EMAC[x]_MTCLK to transmit selected signals valid
ns
Table 8-17. Switching Characteristics Over Recommended Operating Conditions for EMAC [G]MII
Transmit 1000 Mbits/s
(see Figure 8-13)
OPP100/OPP120/
Turbo
NO.
1
PARAMETER
td(GMTCLK-MTXD)
Delay time, EMAC[x]_GMTCLK to transmit selected signals valid
td(GMTCLK-MTXEN)
UNIT
1000 Mbps (1 Gbps)
MIN
MAX
0.5
5
ns
1
EMAC[x]_MTCLK (Input)
EMAC[x]_MTXD3−EMAC[x]_MTXD0,
EMAC[x]_MTXEN (Outputs)
Figure 8-13. EMAC Transmit Interface Timing [G]MII Operation
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8.7.2.2
SPRS872B – MAY 2013 – REVISED DECEMBER 2013
EMAC RMII Electrical Data/Timing
Table 8-18. Timing Requirements for EMAC[x]_RMREFCLK - RMII Operation
(see Figure 8-14)
OPP100/OPP120/Turbo
NO.
MIN
MAX
UNIT
1
tc(RMREFCLK)
Cycle time, EMAC[x]_RMREFCLK
19.999
20.001
ns
2
tw(RMREFCLKH)
Pulse duration, EMAC[x]_RMREFCLK high
7
13
ns
3
tw(RMREFCLKL)
Pulse duration, EMAC[x]_RMREFCLK low
7
13
ns
4
tt(RMREFCLK)
Transition time, EMAC[x]_RMREFCLK
3
ns
1
2
4
RMREFCLK
(Input)
3
4
Figure 8-14. RMREFCLK Timing RMII Operation
Table 8-19. Timing Requirements for EMAC RMII Receive
(see Figure 8-14)
OPP100/OPP120/
Turbo
NO.
MIN
UNIT
MAX
tsu(RMRXD-RMREFCLK)
1
tsu(RMCRSDV-RMREFCLK)
Setup time, receive selected signals valid before
EMAC[x]_RMREFCLK
4
ns
Hold time, receive selected signals valid after
EMAC[x]_RMREFCLK
2
ns
tsu(RMRXER-RMREFCLK)
th(RMREFCLK-RMRXD)
2
th(RMREFCLK-RMCRSDV)
th(RMREFCLK-RMRXER)
1
2
RMREFCLK
RMRXD1−RMRXD0,
RMCRSDV, RMRXER (inputs)
Figure 8-15. EMAC Receive Interface Timing RMII Operation
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Table 8-20. Switching Characteristics Over Recommended Operating Conditions for EMAC RMII Transmit
10/100 Mbits/s
(see Figure 8-16)
NO.
OPP100/OPP120/
Turbo
PARAMETER
UNIT
MIN
MAX
1
td(RMREFCLK-RMTXD)
Delay time, EMAC[x]_RMREFCLK high to EMAC[x]_RMTXD[x]
valid
2.4
13
2
tdd(RMREFCLK-RMTXEN)
Delay time, EMAC[x]_RMREFCLK high to EMAC[x]_RMTXEN
valid
2.4
13
ns
1
RMREFCLK
RMTXD1−RMTXD0,
RMTXEN (Outputs)
Figure 8-16. EMAC Transmit Interface Timing RMII Operation
8.7.2.3
EMAC RGMII Electrical Data/Timing
RGMII mode is not supported for OPP50.
Table 8-21. Timing Requirements for EMAC[x]_RGRXC - RGMII Operation
(see Figure 8-17)
OPP100/OPP120/Turbo
NO.
1
2
3
4
180
tc(RGRXC)
tw(RGRXCH)
tw(RGRXCL)
tt(RGRXC)
Cycle time, EMAC[x]_RGRXC
Pulse duration, EMAC[x]_RGRXC high
Pulse duration, EMAC[x]_RGRXC low
Transition time, EMAC[x]_RGRXC
MIN
MAX
10 Mbps
360
440
100 Mbps
36
44
1000 Mbps
7.2
8.8
10 Mbps
0.40*tc(RGRXC)
0.60*tc(RGRXC)
100 Mbps
0.40*tc(RGRXC)
0.60*tc(RGRXC)
1000 Mbps
0.45*tc(RGRXC)
0.55*tc(RGRXC)
10 Mbps
0.40*tc(RGRXC)
0.60*tc(RGRXC)
100 Mbps
0.40*tc(RGRXC)
0.60*tc(RGRXC)
1000 Mbps
0.45*tc(RGRXC)
0.55*tc(RGRXC)
10 Mbps
0.75
100 Mbps
0.75
1000 Mbps
0.75
Peripheral Information and Timings
UNIT
ns
ns
ns
ns
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Table 8-22. Timing Requirements for EMAC RGMII Input Receive for 10/100/1000 Mbps (1)
(see Figure 8-17)
OPP100/OPP120/
Turbo
NO.
MIN
tsu(RGRXD-
5
RGRXCH)
th(RGRXCH-
6
RGRXD)
(1)
UNIT
MAX
Setup time, receive selected signals valid before
EMAC[x]_RGRXC (at device) high/low
Internal delay
enabled
1.0
ns
Hold time, receive selected signals valid after
EMAC[x]_RGRXC (at device) high/low
Internal delay
enabled
1.0
ns
For RGMII, receive selected signals include: EMAC[x]_RGRXD[3:0] and EMAC[x]_RGRXCTL.
1
4
2
4
3
EMAC[x]_RGRXC
(A)
(at device)
5
1st Half-byte
6
2nd Half-byte
EMAC[x]_RGRXD[3:0]
EMAC[x]_RGRXCTL
A.
B.
(B)
(B)
RGRXD[3:0]
RGRXD[7:4]
RXDV
RXERR
EMAC[x]_RGRXC must be externally delayed relative to the data and control pins. The internal delay can be enabled
or disabled via the EMAC RGMIIn_ID_MODE register.
Data and control information is received using both edges of the clocks. EMAC[x]_RGRXD[3:0] carries data bits 3-0
on the rising edge of EMAC[x]_RGRXC and data bits 7-4 on the falling edge of EMAC[x]_RGRXC. Similarly,
EMAC[x]_RGRXCTL carries RXDV on rising edge of EMAC[x]_RGRXC and RXERR on falling edge of
EMAC[x]_RGRXC.
Figure 8-17. EMAC Receive Interface Timing [RGMII Operation]
Table 8-23. Switching Characteristics Over Recommended Operating Conditions for RGTXC - RGMII
Operation for 10/100/1000 Mbit/s
(see Figure 8-18)
OPP100/OPP120/
Turbo
NO.
MIN
10 Mbps
1
2
3
4
tc(RGTXC)
tw(RGTXCH)
tw(RGTXCL)
tt(RGTXC)
Cycle time, EMAC[x]_RGTXC
Pulse duration, EMAC[x]_RGTXC high
Pulse duration, EMAC[x]_RGTXC low
Transition time, EMAC[x]_RGTXC
UNIT
MAX
360
440
100 Mbps
36
44
1000 Mbps
7.2
8.8
10 Mbps
0.40*tc(RGTXC)
0.60*tc(RGTXC)
100 Mbps
0.40*tc(RGTXC)
0.60*tc(RGTXC)
1000 Mbps
0.45*tc(RGTXC)
0.55*tc(RGTXC)
10 Mbps
0.40*tc(RGTXC)
0.60*tc(RGTXC)
100 Mbps
0.40*tc(RGTXC)
0.60*tc(RGTXC)
1000 Mbps
0.45*tc(RGTXC)
0.55*tc(RGTXC)
10 Mbps
0.75
100 Mbps
0.75
1000 Mbps
0.75
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ns
ns
ns
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Table 8-24. Switching Characteristics Over Recommended Operating Conditions for EMAC RGMII
Transmit (1)
(see Figure 8-18)
NO.
OPP100/OPP120
/
Turbo
PARAMETER
MIN
tsu(RGTXD-
5
RGTXCH)
th(RGTXCH-
6
RGTXD)
(1)
UNIT
MAX
Setup time, transmit selected signals valid before
EMAC[x]_RGTXC (at device) high/low
Internal delay enabled
1.2
ns
Hold time, transmit selected signals valid after
EMAC[x]_RGTXC (at device) high/low
Internal delay enabled
1.2
ns
For RGMII, transmit selected signals include: EMAC[x]_RGTXD[3:0] and EMAC[x]_RGTXCTL.
RGTXC at device pins
1
2
EMQAC[x]_RGTXC
(A)
(at device)
Internal RGTXC
3
4
4
1
5
(B)
1st Half-byte
(B)
TXEN
EMAC[x]_RGTXD[3:0]
2nd Half-byte
6
2
EMAC[x]_RGTXCTL
A.
B.
TXERR
RGTXC is delayed internally before being driven to the EMAC[x]_RGTXC pin. The internal delay can be enabled or
disabled via the EMAC RGMIIn_ID_MODE register.
Data and control information is transmitted using both edges of the clocks. EMAC[x]_RGTXD[3:0] carries data bits 3-0
on the rising edge of EMAC[x]_RGTXC and data bits 7-4 on the falling edge of EMAC[x]_RGTXC. Similarly,
EMAC[x]_RGTXCTL carries TXEN on rising edge of EMAC[x]_RGTXC and TXERR of falling edge of
EMAC[x]_RGTXC.
Figure 8-18. EMAC Transmit Interface Timing [RGMII Operation]
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8.7.3
SPRS872B – MAY 2013 – REVISED DECEMBER 2013
Management Data Input/Output (MDIO)
The Management Data Input/Output (MDIO) module continuously polls all 32 MDIO addresses in order to
enumerate all PHY devices in the system.
The MDIO module implements the 802.3 serial management interface to interrogate and control Ethernet
PHYs using a shared two-wire bus. Host software uses the MDIO module to configure the autonegotiation parameters of each PHY attached to the EMAC SW, retrieve the negotiation results, and
configure required parameters in the EMAC SW module for correct operation. The module is designed to
allow almost transparent operation of the MDIO interface, with very little maintenance from the core
processor. A single MDIO interface is pinned out to control the PHY configuration and status monitoring.
Multiple external PHYs can be controlled by the MDIO interface.
For more detailed information on the MDIO peripheral, see the 3PSW Ethernet Subsystem chapter in the
device-specific Technical Reference Manual.
8.7.3.1
MDIO Peripheral Register Descriptions
The MDIO peripheral registers are described in the device-specific Technical Reference Manual. Each
register is documented as an offset from a base address for the peripheral. The base addresses for all of
the peripherals are in the device memory map (see Section 2.10).
8.7.3.2
MDIO Electrical Data/Timing
Table 8-25. Timing Requirements for MDIO Input
(see Figure 8-19)
OPP100/OPP120/
Turbo
NO.
MIN
1
UNIT
MAX
tc(MDCLK)
Cycle time, MDCLK
400
ns
tw(MDCLK)
Pulse duration, MDCLK high or low
180
ns
4
tsu(MDIO-MDCLKH)
Setup time, MDIO data input valid before MDCLK high
15
ns
5
th(MDCLKH-MDIO)
Hold time, MDIO data input valid after MDCLK high
10
ns
1
MDCLK
4
5
MDIO
(input)
Figure 8-19. MDIO Input Timing
Table 8-26. Switching Characteristics Over Recommended Operating Conditions for MDIO Output
(see Figure 8-20)
NO.
PARAMETER
OPP100/OPP120/
Turbo
MIN
7
td(MDCLKL-MDIO)
Delay time, MDCLK low to MDIO data output valid
UNIT
MAX
100
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1
MDCLK
7
MDIO
(output)
Figure 8-20. MDIO Output Timing
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8.8
SPRS872B – MAY 2013 – REVISED DECEMBER 2013
General-Purpose Input/Output (GPIO)
The GPIO peripheral provides general-purpose pins that can be configured as either inputs
When configured as an output, a write to an internal register controls the state driven on the
When configured as an input, the state of the input is detectable by reading the state of
register. In addition, the GPIO peripheral can produce CPU interrupts in different interrupt
modes. The GPIO peripheral provides generic connections to external devices.
or outputs.
output pin.
an internal
generation
The device contains four GPIO modules and each GPIO module consists of up to 32 identical channels.
The device GPIO peripheral supports the following:
• Up to 125 1.8-V/3.3-V GPIO pins, GP0[0:28], GP1[0:31], GP2[0:31], and GP3[0:31] (the exact number
available varies as a function of the device configuration). Each channel can be configured to be used
in the following applications:
– Data input/output
– Keyboard interface with a de-bouncing cell
– Synchronous interrupt generation (in active mode) upon the detection of external events (signal
transitions and/or signal levels).
• Synchronous interrupt requests from each channel are processed by four identical interrupt generation
sub-modules to be used independently by the ARM or Media Controller. Interrupts can be triggered by
rising and/or falling edge, specified for each interrupt-capable GPIO signal.
• Shared registers can be accessed through "Set & Clear" protocol. Software writes 1 to corresponding
bit positions to set or to clear GPIO signals. This allows multiple software processes to toggle GPIO
output signals without critical section protection (disable interrupts, program GPIO, re-enable interrupts,
to prevent context switching to another process during GPIO programming).
• Separate input/output registers.
• Output register in addition to set/clear so that, if preferred by software, some GPIO output signals can
be toggled by direct write to the output registers.
• Output register, when read, reflects output drive status. This, in addition to the input register reflecting
pin status and open-drain I/O cell, allows wired logic to be implemented.
For more detailed information on GPIOs, see the General-Purpose I/O (GPIO) Interface chapter in the
device-specific Technical Reference Manual.
8.8.1
GPIO Peripheral Register Descriptions
The GPIO peripheral registers are described in the device-specific Technical Reference Manual. Each
register is documented as an offset from a base address for the peripheral. The base addresses for all of
the peripherals are in the device memory map (see Section 2.10).
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GPIO Electrical Data/Timing
Table 8-27. Timing Requirements for GPIO Inputs
(see Figure 8-21)
OPP100/OPP120/
Turbo
NO.
MIN
1
tw(GPIH)
2
(1)
tw(GPIL)
Pulse duration, GPx[31:0] input high
Pulse duration, GPx[31:0] input low
UNIT
MAX
12P (1)
ns
(1)
ns
12P
P = Module clock.
Table 8-28. Switching Characteristics Over Recommended Operating Conditions for GPIO Outputs
(see Figure 8-21)
NO.
OPP100/OPP120/
Turbo
PARAMETER
MIN
UNIT
MAX
3
tw(GPOH)
Pulse duration, GPx[31:0] output high
36P-8 (1)
ns
4
tw(GPOL)
Pulse duration, GPx[31:0] output low
36P-8 (1)
ns
(1)
P = Module clock.
2
GPx[31:0]
input
1
4
GPx[31:0]
output
3
Figure 8-21. GPIO Port Timing
186
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8.9
SPRS872B – MAY 2013 – REVISED DECEMBER 2013
General-Purpose Memory Controller (GPMC) and Error Location Module (ELM)
The GPMC is a device memory controller used to provide a glueless interface to external memory devices
such as NOR Flash, NAND Flash (with BCH and Hamming Error Code Detection for 8-bit or 16-bit NAND
Flash), SRAM, and Pseudo-SRAM. It includes flexible asynchronous protocol control for interface to
SRAM-like memories and custom logic (FPGA, CPLD, ASICs, etc.).
Other supported features include:
• 8-/16-bit wide multiplexed address/data bus
• 512 MBytes maximum addressing capability divided among up to eight chip selects
• Non-multiplexed address/data mode
• Pre-fetch and write posting engine associated with system DMA to get full performance from NAND
device with minimum impact on NOR/SRAM concurrent access.
The device also contains an Error Locator Module (ELM) which is used to extract error addresses from
syndrome polynomials generated using a BCH algorithm. Each of these polynomials gives a status of the
read operations for a 512 bytes block from a NAND flash and its associated BCH parity bits, plus
optionally spare area information. The ELM has the following features:
• 4-bit, 8-bit and 16-bit per 512byte block error location based on BCH algorithms
• Eight simultaneous processing contexts
• Page-based and continuous modes
• Interrupt generation on error location process completion
– When the full page has been processed in page mode
– For each syndrome polynomial in continuous mode
8.9.1
GPMC and ELM Peripherals Register Descriptions
The GPMC and ELM peripheral registers are described in the device-specific Technical Reference
Manual. Each register is documented as an offset from a base address for the peripheral. The base
addresses for all of the peripherals are in the device memory map (see Section 2.10).
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GPMC Electrical Data/Timing
8.9.2.1
GPMC and NOR Flash Interface Synchronous Mode Timing (Non-Multiplexed and Multiplexed
Modes)
Table 8-29. Timing Requirements for GPMC and NOR Flash Interface - Synchronous Mode
(see Figure 8-22, Figure 8-23, Figure 8-24 for Non-Multiplexed Modes)
(see Figure 8-25, Figure 8-26, Figure 8-27 for Multiplexed Modes)
OPP100/OPP120/Turbo
NO.
MIN
MAX
UNIT
13
tsu(DV-CLKH)
Setup time, read GPMC_D[15:0] valid before GPMC_CLK high
3.2
ns
14
th(CLKH-DV)
Hold time, read GPMC_D[15:0] valid after GPMC_CLK high
2.5
ns
22
tsu(WAITV-CLKH)
Setup time, GPMC_WAIT[x] valid before GPMC_CLK high
3.2
ns
23
th(CLKH-WAITV)
Hold time, GPMC_WAIT[x] valid after GPMC_CLK high
2.5
ns
Table 8-30. Switching Characteristics Over Recommended Operating Conditions for GPMC and NOR
Flash Interface - Synchronous Mode
(see Figure 8-22, Figure 8-23, Figure 8-24 for Non-Multiplexed Modes)
(see Figure 8-25, Figure 8-26, Figure 8-27 for Multiplexed Modes)
NO.
OPP100/OPP120/Turb
o
PARAMETER
MIN
1
2
3
tc(CLK)
16 (1)
Cycle time, output clock GPMC_CLK period
UNIT
MAX
ns
(2)
tw(CLKH)
Pulse duration, output clock GPMC_CLK high
0.5P
tw(CLKL)
Pulse duration, output clock GPMC_CLK low
0.5P (2)
td(CLKH-nCSV)
Delay time, GPMC_CLK rising edge to GPMC_CS[x] transition
ns
F - 2.2 (3)
F + 4.5 (3)
ns
(4)
(4)
ns
B + 2.3 (5)
ns
4
td(CLKH-nCSIV)
Delay time, GPMC_CLK rising edge to GPMC_CS[x] invalid
E - 2.2
5
td(ADDV-CLK)
Delay time, GPMC_A[27:0] address bus valid to GPMC_CLK first edge
B - 4.5 (5)
6
td(CLKH-ADDIV)
Delay time, GPMC_CLK rising edge to GPMC_A[27:0] GPMC address bus
invalid
-2.3
7
td(nBEV-CLK)
Delay time, GPMC_BE0_CLE, GPMC_BE1 valid to GPMC_CLK first edge
B - 1.9 (5)
B + 2.3 (5)
ns
(6)
D + 1.9 (6)
ns
8
(1)
(2)
(3)
(4)
(5)
(6)
188
td(CLKH-nBEIV)
Delay time, GPMC_CLK rising edge to GPMC_BE0_CLE, GPMC_BE1 invalid
D - 2.3
E + 4.5
ns
Sync mode = 62.5 MHz; Async mode = 125 MHz.
P = GPMC_CLK period.
For nCS falling edge (CS activated):
• For GpmcFCLKDivider = 0:
F = 0.5 * CSExtraDelay * GPMC_FCLK
• For GpmcFCLKDivider = 1:
F = 0.5 * CSExtraDelay * GPMC_FCLK if (ClkActivationTime and CSOnTime are odd) or (ClkActivationTime and CSOnTime are
even)
F = (1 + 0.5 * CSExtraDelay) * GPMC_FCLK otherwise
• For GpmcFCLKDivider = 2:
F = 0.5 * CSExtraDelay * GPMC_FCLK if ((CSOnTime – ClkActivationTime) is a multiple of 3)
F = (1 + 0.5 * CSExtraDelay) * GPMC_FCLK if ((CSOnTime – ClkActivationTime – 1) is a multiple of 3)
F = (2 + 0.5 * CSExtraDelay) * GPMC_FCLK if ((CSOnTime – ClkActivationTime – 2) is a multiple of 3)
For single read: E = (CSRdOffTime – AccessTime) * (TimeParaGranularity + 1) * GPMC_FCLK
For burst read: E = (CSRdOffTime – AccessTime) * (TimeParaGranularity + 1) * GPMC_FCLK
For burst write: E = (CSWrOffTime – AccessTime) * (TimeParaGranularity + 1) * GPMC_FCLK
B = ClkActivationTime * GPMC_FCLK
For single read: D = (RdCycleTime – AccessTime) * (TimeParaGranularity + 1) * GPMC_FCLK
For burst read: D = (RdCycleTime – AccessTime) * (TimeParaGranularity + 1) * GPMC_FCLK
For burst write: D = (WrCycleTime – AccessTime) * (TimeParaGranularity + 1) * GPMC_FCLK
Peripheral Information and Timings
Copyright © 2013, Texas Instruments Incorporated
Submit Documentation Feedback
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DMVA3, DMVA4
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SPRS872B – MAY 2013 – REVISED DECEMBER 2013
Table 8-30. Switching Characteristics Over Recommended Operating Conditions for GPMC and NOR
Flash Interface - Synchronous Mode (continued)
(see Figure 8-22, Figure 8-23, Figure 8-24 for Non-Multiplexed Modes)
(see Figure 8-25, Figure 8-26, Figure 8-27 for Multiplexed Modes)
NO.
9
PARAMETER
td(CLKH-nADV)
Delay time, GPMC_CLK rising edge to GPMC_ADV_ALE transition
OPP100/OPP120/Turb
o
UNIT
MIN
MAX
G - 2.3 (7)
G + 4.5 (7)
ns
(6)
D + 4.5 (6)
ns
10
td(CLKH-nADVIV)
Delay time, GPMC_CLK rising edge to GPMC_ADV_ALE invalid
D - 2.3
11
td(CLKH-nOE)
Delay time, GPMC_CLK rising edge to GPMC_OE_RE transition
H - 2.3 (8)
H + 3.5 (8)
ns
(4)
(4)
ns
12
(7)
(8)
td(CLKH-nOEIV)
Delay time, GPMC_CLK rising edge to GPMC_OE_RE invalid
E - 2.3
E + 3.5
For ADV falling edge (ADV activated):
• Case GpmcFCLKDivider = 0:
G = 0.5 * ADVExtraDelay * GPMC_FCLK
• Case GpmcFCLKDivider = 1:
G = 0.5 * ADVExtraDelay * GPMC_FCLK if (ClkActivationTime and ADVOnTime are odd) or (ClkActivationTime and ADVOnTime are
even)
G = (1 + 0.5 * ADVExtraDelay) * GPMC_FCLK otherwise
• Case GpmcFCLKDivider = 2:
G = 0.5 * ADVExtraDelay * GPMC_FCLK if ((ADVOnTime – ClkActivationTime) is a multiple of 3)
G = (1 + 0.5 * ADVExtraDelay) * GPMC_FCLK if ((ADVOnTime – ClkActivationTime – 1) is a multiple of 3)
G = (2 + 0.5 * ADVExtraDelay) * GPMC_FCLK if ((ADVOnTime – ClkActivationTime – 2) is a multiple of 3)
For ADV rising edge (ADV deactivated) in Reading mode:
• Case GpmcFCLKDivider = 0:
G = 0.5 * ADVExtraDelay * GPMC_FCLK
• Case GpmcFCLKDivider = 1:
G = 0.5 * ADVExtraDelay * GPMC_FCLK if (ClkActivationTime and ADVRdOffTime are odd) or (ClkActivationTime and
ADVRdOffTime are even)
G = (1 + 0.5 * ADVExtraDelay) * GPMC_FCLK otherwise
• Case GpmcFCLKDivider = 2:
G = 0.5 * ADVExtraDelay * GPMC_FCLK if ((ADVRdOffTime – ClkActivationTime) is a multiple of 3)
G = (1 + 0.5 * ADVExtraDelay) * GPMC_FCLK if ((ADVRdOffTime – ClkActivationTime – 1) is a multiple of 3)
G = (2 + 0.5 * ADVExtraDelay) * GPMC_FCLK if ((ADVRdOffTime – ClkActivationTime – 2) is a multiple of 3)
For ADV rising edge (ADV deactivated) in Writing mode:
• Case GpmcFCLKDivider = 0:
G = 0.5 * ADVExtraDelay * GPMC_FCLK
• Case GpmcFCLKDivider = 1:
G = 0.5 * ADVExtraDelay * GPMC_FCLK if (ClkActivationTime and ADVWrOffTime are odd) or (ClkActivationTime and
ADVWrOffTime are even)
G = (1 + 0.5 * ADVExtraDelay) * GPMC_FCLK otherwise
• Case GpmcFCLKDivider = 2:
G = 0.5 * ADVExtraDelay * GPMC_FCLK if ((ADVWrOffTime – ClkActivationTime) is a multiple of 3)
G = (1 + 0.5 * ADVExtraDelay) * GPMC_FCLK if ((ADVWrOffTime – ClkActivationTime – 1) is a multiple of 3)
G = (2 + 0.5 * ADVExtraDelay) * GPMC_FCLK if ((ADVWrOffTime – ClkActivationTime – 2) is a multiple of 3)
For OE falling edge (OE activated) / IO DIR rising edge (IN direction) :
• Case GpmcFCLKDivider = 0:
H = 0.5 * OEExtraDelay * GPMC_FCLK
• Case GpmcFCLKDivider = 1:
H = 0.5 * OEExtraDelay * GPMC_FCLK if (ClkActivationTime and OEOnTime are odd) or (ClkActivationTime and OEOnTime are
even)
H = (1 + 0.5 * OEExtraDelay) * GPMC_FCLK otherwise
• Case GpmcFCLKDivider = 2:
H = 0.5 * OEExtraDelay * GPMC_FCLK if ((OEOnTime – ClkActivationTime) is a multiple of 3)
H = (1 + 0.5 * OEExtraDelay) * GPMC_FCLK if ((OEOnTime – ClkActivationTime – 1) is a multiple of 3)
H = (2 + 0.5 * OEExtraDelay) * GPMC_FCLK if ((OEOnTime – ClkActivationTime – 2) is a multiple of 3)
For OE rising edge (OE deactivated):
• Case GpmcFCLKDivider = 0:
H = 0.5 * OEExtraDelay * GPMC_FCLK
• Case GpmcFCLKDivider = 1:
H = 0.5 * OEExtraDelay * GPMC_FCLK if (ClkActivationTime and OEOffTime are odd) or (ClkActivationTime and OEOffTime are
even)
H = (1 + 0.5 * OEExtraDelay) * GPMC_FCLK otherwise
• Case GpmcFCLKDivider = 2:
H = 0.5 * OEExtraDelay * GPMC_FCLK if ((OEOffTime – ClkActivationTime) is a multiple of 3)
H = (1 + 0.5 * OEExtraDelay) * GPMC_FCLK if ((OEOffTime – ClkActivationTime – 1) is a multiple of 3)
H = (2 + 0.5 * OEExtraDelay) * GPMC_FCLK if ((OEOffTime – ClkActivationTime – 2) is a multiple of 3)
Peripheral Information and Timings
Copyright © 2013, Texas Instruments Incorporated
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SPRS872B – MAY 2013 – REVISED DECEMBER 2013
www.ti.com
Table 8-30. Switching Characteristics Over Recommended Operating Conditions for GPMC and NOR
Flash Interface - Synchronous Mode (continued)
(see Figure 8-22, Figure 8-23, Figure 8-24 for Non-Multiplexed Modes)
(see Figure 8-25, Figure 8-26, Figure 8-27 for Multiplexed Modes)
NO.
15
16
OPP100/OPP120/Turb
o
PARAMETER
td(CLKH-nWE)
Delay time, GPMC_CLK rising edge to GPMC_WE transition
UNIT
MIN
MAX
I - 2.3 (9)
I + 4.5 (9)
ns
(10)
J + 1.9 (10)
ns
J + 1.9 (10)
ns
td(CLKH-Data)
Delay time, GPMC_CLK rising edge to GPMC_D[15:0] data bus transition
J - 2.3
18
td(CLKH-nBE)
Delay time, GPMC_CLK rising edge to GPMC_BE0_CLE, GPMC_BE1
transition
J - 2.3 (10)
19
tw(nCSV)
Pulse duration, GPMC_CS[x] low
A (11)
ns
20
tw(nBEV)
Pulse duration, GPMC_BE0_CLE, GPMC_BE1 low
C (12)
ns
21
tw(nADVV)
Pulse duration, GPMC_ADV_ALE low
K (13)
ns
(9)
(10)
(11)
(12)
(13)
190
For WE falling edge (WE activated):
• Case GpmcFCLKDivider = 0:
I = 0.5 * WEExtraDelay * GPMC_FCLK
• Case GpmcFCLKDivider = 1:
I = 0.5 * WEExtraDelay * GPMC_FCLK if (ClkActivationTime and WEOnTime are odd) or (ClkActivationTime and WEOnTime are
even)
I = (1 + 0.5 * WEExtraDelay) * GPMC_FCLK otherwise
• Case GpmcFCLKDivider = 2:
I = 0.5 * WEExtraDelay * GPMC_FCLK if ((WEOnTime – ClkActivationTime) is a multiple of 3)
I = (1 + 0.5 * WEExtraDelay) * GPMC_FCLK if ((WEOnTime – ClkActivationTime – 1) is a multiple of 3)
I = (2 + 0.5 * WEExtraDelay) * GPMC_FCLK if ((WEOnTime – ClkActivationTime – 2) is a multiple of 3)
For WE rising edge (WE deactivated):
• Case GpmcFCLKDivider = 0:
I = 0.5 * WEExtraDelay * GPMC_FCLK
• Case GpmcFCLKDivider = 1:
I = 0.5 * WEExtraDelay * GPMC_FCLK if (ClkActivationTime and WEOffTime are odd) or (ClkActivationTime and WEOffTime are
even)
I = (1 + 0.5 * WEExtraDelay) * GPMC_FCLK otherwise
• Case GpmcFCLKDivider = 2:
I = 0.5 * WEExtraDelay * GPMC_FCLK if ((WEOffTime – ClkActivationTime) is a multiple of 3)
I = (1 + 0.5 * WEExtraDelay) * GPMC_FCLK if ((WEOffTime – ClkActivationTime – 1) is a multiple of 3)
I = (2 + 0.5 * WEExtraDelay) * GPMC_FCLK if ((WEOffTime – ClkActivationTime – 2) is a multiple of 3)
J = GPMC_FCLK period.
For single read: A = (CSRdOffTime - CSOnTime) * (TimeParaGranularity + 1) * GPMC_FCLK period
For burst read: A = (CSRdOffTime - CSOnTime + (n - 1) * PageBurstAccessTime) * (TimeParaGranularity + 1) * GPMC_FCLK period [n
= page burst access number]
For burst write: A = (CSWrOffTime - CSOnTime + (n - 1) * PageBurstAccessTime) * (TimeParaGranularity + 1) * GPMC_FCLK period [n
= page burst access number]
For single read: C = RdCycleTime * (TimeParaGranularity + 1) * GPMC_FCLK
For burst read: C = (RdCycleTime + (n – 1) * PageBurstAccessTime) * (TimeParaGranularity + 1) * GPMC_FCLK [n = page burst
access number]
For Burst write: C = (WrCycleTime + (n – 1) * PageBurstAccessTime) * (TimeParaGranularity + 1) * GPMC_FCLK [n = page burst
access number]
For read: K = (ADVRdOffTime - ADVOnTime) * (TimeParaGranularity + 1) * GPMC_FCLK
For write: K = (ADVWrOffTime - ADVOnTime) * (TimeParaGranularity + 1) * GPMC_FCLK
Peripheral Information and Timings
Copyright © 2013, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: DMVA3
DMVA3, DMVA4
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SPRS872B – MAY 2013 – REVISED DECEMBER 2013
2
1
2
GPMC_CLK
3
4
19
GPMC_CS[x]
5
GPMC_A[27:0]
Address
7
8
20
GPMC_BE1
7
8
20
GPMC_BE0_CLE
9
9
10
21
GPMC_ADV_ALE
11
12
GPMC_OE
14
13
GPMC_D[15:0]
D0
23
22
GPMC_WAIT[x]
Figure 8-22. GPMC Non-Multiplexed NOR Flash - Synchronous Single Read (GPMCFCLKDIVIDER = 0)
2
1
2
GPMC_CLK
3
4
19
GPMC_CS[x]
5
GPMC_A[27:0]
Address
8
7
20
Valid
GPMC_BE1
8
7
20
Valid
GPMC_BE0_CLE
9
9
10
21
GPMC_ADV_ALE
11
12
GPMC_OE
14
13
13
13
13
GPMC_D[15:0]
(Non-Multplexed Mode)
D0
23
D1
D2
D3
22
GPMC_WAIT[x]
Figure 8-23. GPMC Non-Multiplexed NOR Flash - 14x16-bit Synchronous Burst Read
(GPMCFCLKDIVIDER = 0)
Peripheral Information and Timings
Copyright © 2013, Texas Instruments Incorporated
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191
DMVA3, DMVA4
SPRS872B – MAY 2013 – REVISED DECEMBER 2013
www.ti.com
2
1
2
GPMC_CLK
3
4
19
GPMC_CS[x]
5
GPMC_A[27:0]
Address
7
18
18
18
GPMC_BE1
18
7
18
18
GPMC_BE0_CLE
9
9
10
21
GPMC_ADV_ALE
15
15
GPMC_WE
GPMC_D[15:0]
(Non-Multiplexed Mode)
16
16
16
D1
D0
23
16
D2
D3
22
GPMC_WAIT[x]
Figure 8-24. GPMC Non-Multiplexed NOR Flash - Synchronous Burst Write (GPMCFCLKDIVIDER = 0)
2
2
1
GPMC_CLK
3
4
19
GPMC_CS[x]
5
GPMC_A[27:16]
Address
7
8
20
GPMC_BE1
7
8
20
GPMC_BE0_CLE
9
9
10
21
GPMC_ADV_ALE
11
12
GPMC_OE
5
GPMC_D[15:0]
(Multiplexed Mode)
6
Address (LSB)
23
13
14
D0
22
GPMC_WAIT[x]
Figure 8-25. GPMC Multiplexed NOR Flash - Synchronous Single Read (GPMCFCLKDIVIDER = 0)
192
Peripheral Information and Timings
Copyright © 2013, Texas Instruments Incorporated
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Product Folder Links: DMVA3
DMVA3, DMVA4
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SPRS872B – MAY 2013 – REVISED DECEMBER 2013
2
1
2
GPMC_CLK
3
4
19
GPMC_CS[x]
5
GPMC_A[27:16]
Address (MSB)
8
7
20
Valid
GPMC_BE1
8
7
20
Valid
GPMC_BE0_CLE
9
9
10
21
GPMC_ADV_ALE
11
12
GPMC_OE
14
13
5
GPMC_D[15:0]
(Multplexed Mode)
13
13
13
6
Address (LSB)
D0
23
D1
D2
D3
22
GPMC_WAIT[x]
Figure 8-26. GPMC Multiplexed NOR Flash - 14x16-bit Synchronous Burst Read (GPMCFCLKDIVIDER = 0)
2
1
2
GPMC_CLK
3
4
19
GPMC_CS[x]
5
GPMC_A[27:16]
6
Address (MSB)
7
18
18
18
GPMC_BE1
18
7
18
18
GPMC_BE0_CLE
9
9
10
21
GPMC_ADV_ALE
15
15
GPMC_WE
GPMC_D[15:0]
(Multiplexed Mode)
16
6,16
5
Address (LSB)
16
D0
23
D1
16
D2
D3
22
GPMC_WAIT[x]
Figure 8-27. GPMC Non-Multiplexed NOR Flash - Synchronous Burst Write (GPMCFCLKDIVIDER = 0)
8.9.2.2
GPMC and NOR Flash Interface Asynchronous Mode Timing (Non-Multiplexed and Multiplexed
Modes)
Peripheral Information and Timings
Copyright © 2013, Texas Instruments Incorporated
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Product Folder Links: DMVA3
193
DMVA3, DMVA4
SPRS872B – MAY 2013 – REVISED DECEMBER 2013
www.ti.com
Table 8-31. Timing Requirements for GPMC and NOR Flash Interface - Asynchronous Mode
(see Figure 8-28, Figure 8-29 for Non-Multiplexed Mode )
(see Figure 8-30, Figure 8-32 for Multiplexed Mode)
OPP100/OPP120/Turbo
NO.
MIN
UNIT
MAX
6
tacc(DAT)
Data maximum access time (GPMC_FCLK cycles)
H (1)
cycles
21
tacc1-pgmode(DAT)
Page mode successive data maximum access time (GPMC_FCLK
cycles)
P (2)
cycles
Page mode first data maximum access time (GPMC_FCLK cycles)
(1)
cycles
22
(1)
(2)
tacc2-pgmode(DAT)
H
H = AccessTime * (TimeParaGranularity + 1)
P = PageBurstAccessTime * (TimeParaGranularity + 1).
Table 8-32. Switching Characteristics Over Recommended Operating Conditions for GPMC and NOR
Flash Interface - Asynchronous Mode
(see Figure 8-28, Figure 8-29, Figure 8-30, Figure 8-31 for Non-Multiplexed Modes)
(see Figure 8-32, Figure 8-33 for Multiplexed Modes)
NO
.
OPP100/OPP120/Turb
o
PARAMETER
MIN
UNIT
MAX
1
tw(nBEV)
Pulse duration, GPMC_BE0_CLE, GPMC_BE1 valid time
N (1)
ns
2
tw(nCSV)
Pulse duration, GPMC_CS[x] low
A (2)
ns
4
td(nCSV-nADVIV)
Delay time, GPMC_CS[x] valid to GPMC_NADV_ALE invalid
B - 0.2 (3)
B + 2.0 (3)
ns
(4)
(4)
ns
5
td(nCSV-nOEIV)
Delay time, GPMC_CS[x] valid to GPMC_OE_RE invalid (single read)
C - 0.2
10
td(AV-nCSV)
Delay time, GPMC_A[27:0] address bus valid to GPMC_CS[x] valid
J - 0.2 (5)
J + 2.0 (5)
ns
11
td(nBEV-nCSV)
Delay time, GPMC_BE0_CLE, GPMC_BE1 valid to GPMC_CS[x] valid
J - 0.2 (5)
J + 2.0 (5)
ns
13
td(nCSV-nADVV)
Delay time, GPMC_CS[x] valid to GPMC_ADV_ALE valid
K - 0.2 (6)
K + 2.0 (6)
ns
L - 0.2
(7)
(7)
ns
G
(8)
14
td(nCSV-nOEV)
Delay time, GPMC_CS[x] valid to GPMC_OE_RE valid
17
tw(AIV)
Pulse duration, GPMC_A[27:0] address bus invalid between 2 successive R/W
accesses
19
td(nCSV-nOEIV)
Delay time, GPMC_CS[x] valid to GPMC_OE_RE invalid (burst read)
21
tw(AV)
Pulse duration, GPMC_A[27:0] address bus valid: second, third and fourth
accesses
26
td(nCSV-nWEV)
Delay time, GPMC_CS[x] valid to GPMC_WE valid
I - 0.2 (9)
D
C + 2.0
L + 2.0
ns
I + 2.0 (9)
(10)
E - 0.2 (11)
ns
ns
E + 2.0 (11)
ns
(1)
For single read: N = RdCycleTime * (TimeParaGranularity + 1) * GPMC_FCLK
For single write: N = WrCycleTime * (TimeParaGranularity + 1) * GPMC_FCLK
For burst read: N = (RdCycleTime + (n - 1) * PageBurstAccessTime) * (TimeParaGranularity + 1) * GPMC_FCLK
For burst write: N = (WrCycleTime + (n - 1) * PageBurstAccessTime) * (TimeParaGranularity + 1) * GPMC_FCLK
(2) For single read: A = (CSRdOffTime - CSOnTime) * (TimeParaGranularity + 1) * GPMC_FCLK
For single write: A = (CSWrOffTime - CSOnTime) * (TimeParaGranularity + 1) * GPMC_FCLK
For burst read: A = (CSRdOffTime - CSOnTime + (n - 1) * PageBurstAccessTime) * (TimeParaGranularity + 1) * GPMC_FCLK
For burst write: A = (CSWrOffTime - CSOnTime + (n - 1) * PageBurstAccessTime) * (TimeParaGranularity + 1) * GPMC_FCLK
(3) = B - nCS Max Delay + nADV Min Delay
For reading: B = ((ADVRdOffTime - CSOnTime) * (TimeParaGranularity + 1) + 0.5 * (ADVExtraDelay - CSExtraDelay)) * GPMC_FCLK
For writing: B = ((ADVWrOffTime - CSOnTime) * (TimeParaGranularity + 1) + 0.5 * (ADVExtraDelay - CSExtraDelay)) * GPMC_FCLK
(4) = C - nCS Max Delay + nOE Min Delay
C = ((OEOffTime - CSOnTime) * (TimeParaGranularity + 1) + 0.5 * (OEExtraDelay - CSExtraDelay)) * GPMC_FCLK
(5) = J - Address Max Delay + nCS Min Delay
J = (CSOnTime * (TimeParaGranularity + 1) + 0.5 * CSExtraDelay) * GPMC_FCLK
(6) = K - nCS Max Delay + nADV Min Delay
K = ((ADVOnTime - CSOnTime) * (TimeParaGranularity + 1) + 0.5 * (ADVExtraDelay - CSExtraDelay)) * GPMC_FCLK
(7) = L - nCS Max Delay + nOE Min Delay
L = ((OEOnTime - CSOnTime) * (TimeParaGranularity + 1) + 0.5 * (OEExtraDelay - CSExtraDelay)) * GPMC_FCLK
(8) G = Cycle2CycleDelay * GPMC_FCLK
(9) = I - nCS Max Delay + nOE Min Delay
I = ((OEOffTime + (n - 1) * PageBurstAccessTime - CSOnTime) * (TimeParaGranularity + 1) + 0.5 * (OEExtraDelay - CSExtraDelay)) *
GPMC_FCLK
(10) D = PageBurstAccessTime * (TimeParaGranularity + 1) * GPMC_FCLK
(11) = E - nCS Max Delay + nWE Min Delay
E = ((WEOnTime - CSOnTime) * (TimeParaGranularity + 1) + 0.5 * (WEExtraDelay - CSExtraDelay)) * GPMC_FCLK
194
Peripheral Information and Timings
Copyright © 2013, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: DMVA3
DMVA3, DMVA4
www.ti.com
SPRS872B – MAY 2013 – REVISED DECEMBER 2013
Table 8-32. Switching Characteristics Over Recommended Operating Conditions for GPMC and NOR
Flash Interface - Asynchronous Mode (continued)
(see Figure 8-28, Figure 8-29, Figure 8-30, Figure 8-31 for Non-Multiplexed Modes)
(see Figure 8-32, Figure 8-33 for Multiplexed Modes)
NO
.
OPP100/OPP120/Turb
o
PARAMETER
UNIT
MIN
MAX
F - 0.2 (12)
F + 2.0 (12)
ns
2.0
ns
J + 2.0 (5)
ns
28
td(nCSV-nWEIV)
Delay time, GPMC_CS[x] valid to GPMC_WE invalid
29
td(nWEV-DV)
Delay time, GPMC_WE valid to GPMC_D[15:0] data bus valid
30
td(DV-nCSV)
Delay time, GPMC_D[15:0] data bus valid to GPMC_CS[x] valid
37
td(ADVV-AIV)
Delay time, GPMC_ADV_ALE valid to GPMC_D[15:0] address invalid
2.0
ns
38
td(nOEV-AIV)
Delay time, GPMC_OE_RE valid to GPMC_D[15:0] address/data busses phase
end
2.0
ns
39
td(AIV-ADVV)
Delay time, GPMC_D[15:0] address valid to GPMC_ADV_ALE invalid
2.0
ns
J - 0.2 (5)
(12) = F - nCS Max Delay + nWE Min Delay
F = ((WEOffTime - CSOnTime) * (TimeParaGranularity + 1) + 0.5 * (WEExtraDelay - CSExtraDelay)) * GPMC_FCLK
GPMC_FCLK
GPMC_CLK
6
2
GPMC_CS[x]
10
GPMC_A[10:1]
Valid Address
11
1
GPMC_BE1
11
1
GPMC_BE0_CLE
4
13
GPMC_ADV_ALE
5
14
GPMC_OE
GPMC_D[15:0]
Data In 0
Data In 0
GPMC_WAIT[x]
Figure 8-28. GPMC/Non-Multiplexed NOR Flash - Asynchronous Read - Single Word Timing
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GPMC_FCLK
GPMC_CLK
6
6
2
2
GPMC_CS[x]
17
10
10
GPMC_A[10:1]
Address 1
Address 2
11
11
1
1
GPMC_BE1
11
11
1
1
GPMC_BE0_CLE
4
4
13
13
GPMC_ADV_ALE
5
5
14
14
GPMC_OE
GPMC_D[15:0]
Data Upper
GPMC_WAIT[x]
Figure 8-29. GPMC/Non-Multiplexed NOR Flash - Asynchronous Read - 32-Bit Access Timing
GPMC_FCLK
GPMC_CLK
22
21
21
21
2
GPMC_CS[x]
10
GPMC_A[10:1]
Add0
Add1
Add2
Add3
D0
D1
D2
Add4
11
1
GPMC_BE1
11
1
GPMC_BE0_CLE
13
GPMC_ADV_ALE
19
14
GPMC_OE
GPMC_D[15:0]
D3
D3
GPMC_WAIT[x]
Figure 8-30. GPMC/Non-Multiplexed Only NOR Flash - Asynchronous Read - Page Mode 4x16-Bit Timing
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GPMC_FCLK
GPMC_CLK
2
GPMC_CS[x]
10
GPMC_A[10:1]
Valid Address
11
1
GPMC_BE1
11
1
GPMC_BE0_CLE
4
13
GPMC_ADV_ALE
28
26
GPMC_WE
30
GPMC_D[15:0]
Data OUT
GPMC_WAIT[x]
Figure 8-31. GPMC/Non-Multiplexed NOR Flash - Asynchronous Write - Single Word Timing
GPMC_FCLK
GPMC_CLK
2
6
GPMC_CS[x]
10
Address (MSB)
GPMC_A[26:17]
11
1
GPMC_BE1
11
1
GPMC_BE0_CLE
13
4
GPMC_ADV_ALE
5
14
GPMC_OE
GPMC_A[16:1]
GPMC_D[15:0]
38
30
Address (LSB)
Data IN
Data IN
GPMC_WAIT[x]
Figure 8-32. GPMC/Multiplexed NOR Flash - Asynchronous Read - Single Word Timing
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GPMC_FCLK
GPMC_CLK
2
GPMC_CS[x]
10
Address (MSB)
GPMC_A[26:17]
11
1
GPMC_BE1
11
1
GPMC_BE0_CLE
13
4
GPMC_ADV_ALE
28
26
GPMC_WE
30
GPMC_A[16:1]
GPMC_D[15:0]
29
Valid Address (LSB)
Data OUT
GPMC_WAIT[x]
Figure 8-33. GPMC/Multiplexed NOR Flash - Asynchronous Write - Single Word Timing
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GPMC/NAND Flash and ELM Interface Timing
Table 8-33. Timing Requirements for GPMC/NAND Flash Interface
(see Figure 8-36)
OPP100/OPP120/Turbo
NO.
13
(1)
MIN
tacc(DAT)
J (1)
Data maximum access time (GPMC_FCLK cycles)
UNIT
MAX
cycles
J = AccessTime * (TimeParaGranularity + 1)
Table 8-34. Switching Characteristics Over Recommended Operating Conditions for GPMC/NAND Flash
Interface
(see Figure 8-34, Figure 8-35, Figure 8-36, Figure 8-37)
NO.
1
PARAMETER
tw(nWEV)
OPP100/OPP120/Turbo
MIN
MAX
UNIT
A (1)
ns
(2)
B + 2.0 (2)
ns
Pulse duration, GPMC_WE valid time
2
td(nCSV-nWEV)
Delay time, GPMC_CS[X] valid to GPMC_WE valid
B - 0.2
3
td(CLEH-nWEV)
Delay time, GPMC_BE0_CLE high to GPMC_WE valid
C - 0.2 (3)
C + 2.0 (3)
ns
(4)
(4)
ns
4
td(nWEV-DV)
Delay time, GPMC_D[15:0] valid to GPMC_WE valid
D - 0.2
5
td(nWEIV-DIV)
Delay time, GPMC_WE invalid to GPMC_AD[15:0] invalid
E - 0.2 (5)
D + 2.0
E + 2.0 (5)
ns
6
td(nWEIV-CLEIV)
Delay time, GPMC_WE invalid to GPMC_BE0_CLE invalid
F - 0.2 (6)
F + 2.0 (6)
ns
(7)
(7)
ns
7
td(nWEIV-nCSIV)
Delay time, GPMC_WE invalid to GPMC_CS[X] invalid
G - 0.2
8
td(ALEH-nWEV)
Delay time, GPMC_ADV_ALE High to GPMC_WE valid
C - 0.2 (3)
C + 2.0 (3)
ns
9
td(nWEIV-ALEIV)
Delay time, GPMC_WE invalid to GPMC_ADV_ALE invalid
F - 0.2 (6)
F + 2.0 (6)
ns
10
tc(nWE)
Cycle time, write cycle time
H (8)
ns
(9)
ns
11
td(nCSV-nOEV)
Delay time, GPMC_CS[X] valid to GPMC_OE_RE valid
12
tw(nOEV)
Pulse duration, GPMC_OE_RE valid time
K (10)
ns
13
tc(nOE)
Cycle time, read cycle time
L (11)
ns
(12)
ns
14
td(nOEIV-nCSIV)
Delay time, GPMC_OE_RE invalid to GPMC_CS[X] invalid
I - 0.2
(9)
G + 2.0
M - 0.2
(12)
I + 2.0
M + 2.0
(1)
(2)
A = (WEOffTime - WEOnTime) * (TimeParaGranularity + 1) * GPMC_FCLK
= B + nWE Min Delay - nCS Max Delay
B = ((WEOnTime - CSOnTime) * (TimeParaGranularity + 1) + 0.5 * (WEExtraDelay - CSExtraDelay)) * GPMC_FCLK
(3) = C + nWE Min Delay - CLE Max Delay
C = ((WEOnTime - ADVOnTime) * (TimeParaGranularity + 1) + 0.5 * (WEExtraDelay - ADVExtraDelay)) * GPMC_FCLK
(4) = D + nWE Min Delay - Data Max Delay
D = (WEOnTime * (TimeParaGranularity + 1) + 0.5 * WEExtraDelay ) * GPMC_FCLK
(5) =E + Data Min Delay - nWE Max Delay
E = ((WrCycleTime - WEOffTime) * (TimeParaGranularity + 1) - 0.5 * WEExtraDelay ) * GPMC_FCLK
(6) = F + CLE Min Delay - nWE Max Delay
F = ((ADVWrOffTime - WEOffTime) * (TimeParaGranularity + 1) + 0.5 * (ADVExtraDelay - WEExtraDelay )) * GPMC_FCLK
(7) =G + nCS Min Delay - nWE Max Delay
G = ((CSWrOffTime - WEOffTime) * (TimeParaGranularity + 1) + 0.5 * (CSExtraDelay - WEExtraDelay )) * GPMC_FCLK
(8) H = WrCycleTime * (1 + TimeParaGranularity) * GPMC_FCLK
(9) = I + nOE Min Delay - nCS Max Delay
I = ((OEOnTime - CSOnTime) * (TimeParaGranularity + 1) + 0.5 * (OEExtraDelay - CSExtraDelay)) * GPMC_FCLK
(10) K = (OEOffTime - OEOnTime) * (1 + TimeParaGranularity) * GPMC_FCLK
(11) L = RdCycleTime * (1 + TimeParaGranularity) * GPMC_FCLK
(12) =M + nCS Min Delay - nOE Max Delay
M = ((CSRdOffTime - OEOffTime) * (TimeParaGranularity + 1) + 0.5 * (CSExtraDelay - OEExtraDelay ))* GPMC_FCLK
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GPMC_FCLK
2
7
GPMC_CS[x]
3
6
GPMC_BE0_CLE
GPMC_ADV_ALE
GPMC_OE
1
GPMC_WE
5
4
GPMC_A[16:1]
GPMC_D[15:0]
Command
Figure 8-34. GPMC/NAND Flash - Command Latch Cycle Timing
GPMC_FCLK
2
7
GPMC_CS[x]
GPMC_BE0_CLE
8
9
GPMC_ADV_ALE
GPMC_OE
10
1
GPMC_WE
5
4
GPMC_A[16:1]
GPMC_D[15:0]
Address
Figure 8-35. GPMC/NAND Flash - Address Latch Cycle Timing
200
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GPMC_FCLK
13
16
11
GPMC_CS[x]
GPMC_BE0_CLE
GPMC_ADV_ALE
15
14
GPMC_OE
GPMC_A[16:1]
GPMC_D[15:0]
Data
GPMC_WAIT[x]
Figure 8-36. GPMC/NAND Flash - Data Read Cycle Timing
GPMC_FCLK
2
7
GPMC_CS[x]
GPMC_BE0_CLE
GPMC_ADV_ALE
GPMC_OE
10
1
GPMC_WE
5
4
GPMC_A[16:1]
GPMC_D[15:0]
Data
Figure 8-37. GPMC/NAND Flash - Data Write Cycle Timing
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8.10 High-Definition Multimedia Interface (HDMI)
The device includes an HDMI 1.3a-compliant transmitter for digital video and audio data to display
devices. The HDMI interface consists of a digital HDMI transmitter core with TMDS encoder, a core
wrapper with interface logic and control registers, and a transmit PHY, with the following features:
• Hot-plug detection
• Consumer electronics control (CEC) messages
• DVI 1.0 compliant (only RGB pixel format)
• CEA 861-D and VESA DMT formats
• Supports up to 165-MHz pixel clock
– 1920 x 1080p @75 Hz with 8-bit/component color depth
– 1600 x 1200 @60 Hz with 8-bit/component color depth
• Support for deep-color mode:
– 10-bit/component color depth up to 1080p @60 Hz (Max pixel clock = 148.5 MHz)
– 12-bit/component color depth up to 720p/1080i @60 Hz (Max pixel clock = 123.75 MHz)
• TMDS clock to the HDMI-PHY is up to 185.625 MHz
• Maximum supported pixel clock:
– 165 MHz for 8-bit color depth
– 148.5 MHz for 10-bit color depth
– 123.75 MHz for 12-bit color depth
• Uncompressed multichannel (up to eight channels) audio (L-PCM) support
• Master I2C interface for display data channel (DDC) connection
• Options available to support HDCP encryption engine for transmitting protected audio and video (for
information, contact your local TI sales representative).
For more details on the HDMI, see the High-Definition Multimedia Interface (HDMI) chapter in the devicespecific Technical Reference Manual.
8.10.1 HDMI Design Guidelines
This section provides PCB design and layout guidelines for the HDMI interface. The design rules constrain
PCB trace length, PCB trace skew, signal integrity, cross-talk, and signal timing. Simulation and system
design work has been done to ensure the HDMI interface requirements are met.
8.10.1.1 HDMI Interface Schematic
The HDMI bus is separated into three main sections:
1. Transition Minimized Differential Signaling (TMDS) high-speed digital video interface
2. Display Data Channel (I2C bus for configuration and status exchange between two devices)
3. Consumer Electronics Control (optional) for remote control of connected devices.
The DDC and CEC are low-speed interfaces, so nothing special is required for PCB layout of these
signals. Their connection is shown in Figure 8-38, HDMI Interface High-Level Schematic.
The TMDS channels are high-speed differential pairs and, therefore, require the most care in layout.
Specifications for TMDS layout are below.
Figure 8-38 shows the HDMI interface schematic. The specific pin numbers can be obtained from , HDMI
Terminal Functions.
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DEVICE
HDMI CONNECTOR
HDMI_DP0
HDMI_DN0
TD0+
TD0-
HDMI_DP1
HDMI_DN1
TD1+
TD1-
HDMI_DP2
HDMI_DN2
TPD12S521
or other
ESD Protection
w/I2C-Level
Translation
HDMI_CLKP
HDMI_CLKN
TD0
Shld
TD1
Shld
TD2
Shld
TD2+
TD2TCLK
TCLK+
HDMI_CEC
TCLK
Shld
CEC
DDC
Gnd
3.3 V
Rpullup
HDMI_SDA
HDMI_SCL
(A)
SDA
SCL
HDMI_HPDET
A.
HPDET
5K-10K Ω pullup resistors are required if not integrated in the ESD protection chip.
Figure 8-38. HDMI Interface High-Level Schematic
8.10.1.2 TMDS Routing
The TMDS signals are high-speed differential pairs. Care must be taken in the PCB layout of these signals
to ensure good signal integrity.
The TMDS differential signal traces must be routed to achieve 100 Ω (±10%) differential impedance and
60 Ω (±10%) single-ended impedance. Single-ended impedance control is required because differential
signals are extremely difficult to closely couple on PCBs and, therefore, single-ended impedance becomes
important.
These impedances are impacted by trace width, trace spacing, distance to reference planes, and dielectric
material. Verify with a PCB design tool that the trace geometry for both data signal pairs results in as
close to 60 Ω impedance traces as possible. For best accuracy, work with your PCB fabricator to ensure
this impedance is met.
In general, closely coupled differential signal traces are not an advantage on PCBs. When differential
signals are closely coupled, tight spacing and width control is necessary. Very small width and spacing
variations affect impedance dramatically, so tight impedance control can be more problematic to maintain
in production.
Loosely coupled PCB differential signals make impedance control much easier. Wider traces and spacing
make obstacle avoidance easier, and trace width variations do not affect impedance as much; therefore, it
is easier to maintain an accurate impedance over the length of the signal. The wider traces also show
reduced skin effect and, therefore, often result in better signal integrity.
Table 8-35 shows the routing specifications for the TMDS signals.
Table 8-35. TMDS Routing Specifications
PARAMETER
MIN
TYP
Processor-to-HDMI header trace length
MAX
UNIT
7000
Number of stubs allowed on TMDS traces
0
Mils
Stubs
TX/RX pair differential impedance
90
100
110
Ω
TX/RX single ended impedance
54
60
66
Ω
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Table 8-35. TMDS Routing Specifications (continued)
PARAMETER
MIN
TYP
Number of vias on each TMDS trace
2
UNIT
Vias (1)
2*DS (2)
TMDS differential pair to any other trace spacing
(1)
(2)
MAX
Vias must be used in pairs with their distance minimized.
DS = differential spacing of the HDMI traces.
8.10.1.3 DDC Signals
As shown in Figure 8-38, HDMI Interface High-Level Schematic, the DDC connects just like a standard
I2C bus. As such, resistor pullups must be used to pull up the open drain buffer signals unless they are
integrated into the ESD protection chip used. If used, these pullup resistors should be connected to a 3.3V supply.
8.10.1.4 HDMI ESD Protection Device (Required)
Interfaces that connect to a cable such as HDMI generally require more ESD protection than can be built
into the processor's outputs. Therefore, this HDMI interface requires the use of an ESD protection chip to
provide adequate ESD protection and to translate I2C voltage levels from the 3.3 V supplied by the device
to the 5 volts required by the HDMI specification.
When selecting an ESD protection chip, choose the lowest capacitance ESD protection available to
minimize signal degradation. In no case should the ESD protection circuit capacitance be more than 5 pF.
TI manufactures devices that provide ESD protection for HDMI signals such as the TPD12S521. For more
information see the www.ti.com website.
8.10.1.5 PCB Stackup Specifications
Table 8-36 shows the stackup and feature sizes required for HDMI.
Table 8-36. HDMI PCB Stackup Specifications
MIN
TYP
MAX
PCB routing/plane layers
PARAMETER
4
6
-
Layers
Signal routing layers
2
3
-
Layers
Number of ground plane cuts allowed within HDMI routing region
-
-
0
Cuts
Number of layers between HDMI routing region and reference ground plane
-
-
0
Layers
PCB trace width
-
4
-
Mils
PCB BGA escape via pad size
-
20
-
Mils
PCB BGA escape via hole size
-
Processor device BGA pad size (1) (2)
(1)
(2)
UNIT
10
Mils
0.4
mm
Non-solder mask defined pad.
Per IPC-7351A BGA pad size guideline.
8.10.1.6 Grounding
Each TMDS channel has its own shield pin which should be grounded to provide a return current path for
the TMDS signal.
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8.11 High-Definition Video Processing Subsystem (HDVPSS)
The device High-Definition Video Processing Subsystem (HDVPSS) provides a video input interface for
external imaging peripherals (for example, image sensors, video decoders, and more) and a video output
interface for display devices, such as analog SDTV and HDTV displays, digital HDTV displays, digital LCD
panels, and more. It includes HD and SD video encoders and an HDMI transmitter interface.
The device HDVPSS features include:
• Two display processing pipelines with de-interlacing, scaling, alpha blending, chroma keying, color
space conversion, flicker filtering, and pixel format conversion.
• HD/SD compositor features for PIP support.
• Format conversions (up to 1080p 60 Hz) include scan format conversion, scan rate conversion, aspectratio conversion, and frame size conversion.
• Supports additional video processing capabilities by using the subsystem's memory-to-memory feature.
• Two parallel video processing pipelines support HD (up to 1080p60) and SD (NTSC/PAL)
simultaneous outputs.
– HD analog component output with OSD and embedded timing codes (BT.1120)
• 3-channel HD-DAC with 10-bit resolution.
• External HSYNC and VSYNC signals.
– SD analog output with OSD with embedded timing codes (BT.656)
• Composite output
• 1-channel SD-DAC with 10-bit resolution
• Options available to support MacroVision and CGMS-A (contact local TI Sales rep for
information).
– Digital HDMI 1.3a-compliant transmitter (for details, see Section 8.10, High-Definition Multimedia
Interface (HDMI)).
– One digital video output supporting up to 30-bits @ 165 MHz
– One digital video output supporting up to 24-bits @ 165 MHz
– Supports clock inversion for VOUT[0] and VOUT[1] clock signals.
• Two independently configurable external video input capture ports (up to 165 MHz).
– 16/24-bit HD digital video input or dual clock independent 8-bit SD inputs on each capture port.
– 8/16/24-bit digital video input
– 8-bit digital video input
– Embedded sync and external sync modes are supported for all input configurations (VIN1 Port B
supports embedded sync only).
– De-multiplexing of both pixel-to-pixel and line-to-line multiplexed streams, effectively supporting up
to 16 simultaneous SD inputs with a glueless interface to an external multiplexer such as the
TVP5158.
– Additional features include: programmable color space conversion, scaler and chroma
downsampler, ancillary VANC/VBI data capture (decoded by software).
• Graphics features:
– Three independently-generated graphics layers.
– Each supports full-screen resolution graphics in HD, SD or both.
– Up/down scaler optimized for graphics.
– Global and pixel-level alpha blending supported.
For more detailed information on specific features and registers, see the High Definition Video Processing
Subsystem chapter in the device-specific Technical Reference Manual.
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8.11.1 HDVPSS Electrical Data/Timing
Table 8-37. Timing Requirements for HDVPSS Input
(see Figure 8-39 and Figure 8-40)
OPP100/OPP120/
Turbo
NO.
MIN
UNIT
MAX
VIN[X]A_CLK
6.06 (1)
ns
Pulse duration, VIN[x]A_CLK high (45% of tc)
2.73
ns
tw(CLKH)
Pulse duration, VIN[x]A_CLK low (45% of tc)
2.73
ns
tt(CLK)
Transition time, VIN[x]A_CLK (10%-90%)
1
tc(CLK)
Cycle time, VIN[x]A_CLK
2
tw(CLKH)
3
7
2.64
ns
tsu(DE-CLK)
tsu(VSYNC-CLK)
4
tsu(FLD-CLK)
Input setup time, control valid to VIN[x]A_CLK high/low
3.11
Input setup time, data valid to VIN[x]A_CLK high/low
3.11
Input hold time, control valid from VIN[x]A_CLK high/low
-0.5
Input hold time, data valid from VIN[x]A_CLK high/low
-0.5
ns
tsu(HSYNC-CLK)
tsu(D-CLK)
th(CLK-DE)
th(CLK-VSYNC)
5
th(CLK-FLD)
ns
th(CLK-HSYNC)
th(CLK-D)
VIN[x]B_CLK
6.06 (1)
ns
Pulse duration, VIN[x]B_CLK high (45% of tc)
2.73
ns
Pulse duration, VIN[x]B_CLK low (45% of tc)
2.73
1
tc(CLK)
Cycle time, VIN[x]B_CLK
2
tw(CLKH)
3
tw(CLKH)
7
tt(CLK)
Transition time, VIN[x]B_CLK (10%-90%)
ns
2.64
ns
tsu(DE-CLK)
tsu(VSYNC-CLK)
4
tsu(FLD-CLK)
Input setup time, control valid to VIN[x]B_CLK high/low
3.11
Input setup time, data valid to VIN[x]B_CLK high/low
3.11
Input hold time, control valid from VIN[x]B_CLK high/low
-0.5
Input hold time, data valid from VIN[x]B_CLK high/low
-0.5
ns
tsu(HSYNC-CLK)
tsu(D-CLK)
th(CLK-DE)
th(CLK-VSYNC)
5
th(CLK-FLD)
ns
th(CLK-HSYNC)
th(CLK-D)
(1)
206
For maximum frequency of 165 MHz.
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Table 8-38. Switching Characteristics Over Recommended Operating Conditions for HDVPSS Output
(see Figure 8-39 and Figure 8-41)
NO.
OPP100/OPP120/Turbo
PARAMETER
MIN
MAX
UNIT
6.06 (1)
ns
Pulse duration, VOUT[x]_CLK high (45% of tc)
2.73
ns
tw(CLKL)
Pulse duration, VOUT[x]_CLK low (45% of tc)
2.73
tt(CLK)
Transition time, VOUT[x]_CLK (10%-90%)
1
tc(CLK)
Cycle time, VOUT[x]_CLK
2
tw(CLKH)
3
7
ns
2.64
ns
1.64
4.18
ns
1.64
4.18
ns
-1.64
4.18
ns
-1.64
4.18
ns
td(CLK-AVID)
td(CLK-FLD)
Delay time, VOUT[x]_CLK low (falling) to control valid, positive
clock edge
td(CLK-VSYNC)
td(CLK-HSYNC)
td(CLK-RCR)
Delay time, VOUT[0]_CLK low (falling) to data valid, positive clock
edge
td(CLK-GYYC)
td(CLK-BCBC)
td(CLK-YYC)
6
Delay time, VOUT[1]_CLK low (falling) to data valid, positive clock
edge
td(CLK-C)
td(CLK-AVID)
td(CLK-FLD)
Delay time, VOUT[x]_CLK low (falling) to control valid, negative
clock edge
td(CLK-VSYNC)
td(CLK-HSYNC)
td(CLK-RCR)
Delay time, VOUT[0]_CLK low (falling) to data valid, negative clock
edge
td(CLK-GYYC)
td(CLK-BCBC)
td(CLK-YYC)
Delay time, VOUT[1]_CLK low (falling) to data valid, negative clock
edge
td(CLK-C)
(1)
For maximum frequency of 165 MHz.
3
2
1
VIN[x]A_CLK/
VIN[x]B_CLK/
VOUT[x]_CLK
7
1
7
Figure 8-39. HDVPSS Clock Timing
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VIN[x]A_CLK/
VIN[x]B_CLK
(positive-edge clocking)
VIN[x]A_CLK/
VIN[x]B_CLK
(negative-edge clocking)
5
4
VIN[x]A/
VIN[x]B
Figure 8-40. HDVPSS Input Timing
VOUT[x]_CLK
6
VOUT[x]
Figure 8-41. HDVPSS Output Timing
208
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8.11.2 Video SD-DAC Guidelines and Electrical Data/Timing
The device's analog video SD-DAC output can be operated in one of two modes: Normal mode and
TVOUT Bypass mode. In Normal mode, the device’s internal video amplifier is used. In TVOUT Bypass
mode, the internal video amplifier is bypassed and an external amplifier is required.
Figure 8-42 shows a typical circuit that permits connecting the analog video output from the device to
standard 75-Ω impedance video systems in Normal mode. Figure 8-43 shows a typical circuit that permits
connecting the analog video output from the device to standard 75-Ω impedance video systems in TVOUT
Bypass mode.
Reconstruction
(A)
Filter
~9.5 MHz
TV_OUTx
CAC
(B)
ROUT
TV_VFBx
A.
B.
Reconstruction Filter (optional)
AC coupling capacitor (optional)
Figure 8-42. TV Output (Normal Mode)
Reconstruction
(A)
Filter
~9.5 MHz
TV_VFBx
Amplifier
3.7 V/V
75 Ω
CAC
(B)
RLOAD
A.
B.
Reconstruction Filter (optional). Note: An amplifier with an integrated reconstruction filter can alternatively be used
instead of a discrete reconstruction filter.
AC coupling capacitor (optional)
Figure 8-43. TV Output (TVOUT Bypass Mode)
During board design, the onboard traces and parasitics must be matched for the channel. The video SDDAC output pin (TV_OUT0/TV_VFB0) are very high-frequency analog signals and must be routed with
extreme care. As a result, the paths of these signals must be as short as possible, and as isolated as
possible from other interfering signals. In TVOUT Bypass mode, the load resistor and amplifier/buffer
should be placed as close as possible to the TV_VFB0 pin. Other layout guidelines include:
• Take special care to bypass the VDDA_VDAC_1P8 power supply pin with a capacitor. For more
information, see Section 7.2.9, Power-Supply Decoupling.
• In TVOUT Bypass mode, place the RLOAD resistor as close as possible to the Reconstruction Filter
and Amplifier. In addition, place the 75-Ω resistor as close as possible (< 0.5 ") to the Amplifier/buffer
output pin. To maintain a high-quality video signal, the onboard traces after the 75-Ω resistor should
have a characteristic impedance of 75 Ω (± 20%).
• In Normal mode, TV_VFB0 is the most sensitive pin in the TV out system. The ROUT resistor should
be placed as close as possible to the device pin. To maintain a high-quality video signal, the onboard
traces leading to the TV_OUT0 pin should have a characteristic impedance of 75 Ω (± 20%) starting
from the closest possible place to the device pin output.
• Minimize input trace lengths to the device to reduce parasitic capacitance.
• Include solid ground return paths.
For additional Video SD-DAC Design guidelines, see the High Definition Video Processing Subsystem
chapter in the device-specific Technical Reference Manual.
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Table 8-39. Static and Dynamic SD-DAC Specifications
VDAC STATIC SPECIFICATIONS
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Reference Current Setting Resistor
(RSET)
Normal Mode
4653
4700
4747
Ω
TVOUT Bypass Mode
9900
10000
10100
Ω
Output resistor between TV_OUT0
and TV_VFB0 pins (ROUT)
Normal Mode
2673
2700
2727
Ω
Load Resistor (RLOAD)
Normal Mode
TVOUT Bypass Mode
N/A
75-Ω Inside the Display
TVOUT Bypass Mode
1485
AC-Coupling Capacitor (Optional)
[CAC]
Normal Mode
220
Total Capacitance from TV_OUT0
to VSSA_VDAC_1P8
Normal Mode
TVOUT Bypass Mode
1500
1515
See External Amplifier Specification
TVOUT Bypass Mode
300
pF
4
LSB
N/A
Resolution
10
Integral Non-Linearity (INL), Best
Fit
Normal Mode
Differential Non-Linearity (DNL)
Normal Mode
-4
TVOUT Bypass Mode
TVOUT Bypass Mode
Full-Scale Output Voltage
Full-Scale Output Current
Ω
uF
Bits
-1
1
LSB
-2.5
2.5
LSB
-1
1
LSB
Normal Mode (RLOAD = 75 Ω)
1.3
V
TVOUT Bypass Mode (RLOAD =
1.5 kΩ)
0.7
V
470
uA
Normal Mode
N/A
TVOUT Bypass Mode
Gain Error
Normal Mode (Composite) and
TVOUT Bypass Mode
Output Impedance
Looking into TV_OUT0 nodes
-10
10
%FS
Ω
75
VDAC DYNAMIC SPECIFICATIONS
PARAMETER
TEST CONDITIONS
MIN
Output Update Rate (FCLK)
TYP
MAX
UNIT
54
60
MHz
Signal Bandwidth
3 dB
6
MHz
Spurious-Free Dynamic Range
(SFDR) within bandwidth
FCLK = 54 MHz, FOUT = 1 MHz
50
dBc
Signal-to-Noise Ration (SNR)
FCLK = 54 MHz, FOUT = 1 MHz
54
dB
Normal Mode, 100 mVpp @ 6
MHz on VDDA_VDAC_1P8
6
TVOUT Bypass Mode, 100
mVpp @ 6 MHz on
VDDA_VDAC_1P8
20
Power Supply Rejection (PSR)
210
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8.11.3 Video HD-DAC Guidelines and Electrical Data/Timing
The device's analog video HD-DAC outputs are designed to drive a 165-Ω load. An external video
buffer/amplifier is required to provide additional gain (4.5V/V) and to drive the actual video outputs. 75-Ω
back termination resistors should be connected in series with the video buffer output pins. For component
video applications, a reconstruction filter should precede the video buffer. One solution is to use a video
buffer/amplifier with integrated reconstruction filter, such as the Texas Instruments THS7360, which
provides a complete solution for the typical output circuit, shown in Figure 8-44.
Reconstruction
Filter
HDDAC_x
RLOAD
SD:
ED:
HD:
1080p:
Amplifier
75 W
4.5 V/V
9.5 MHz
18 MHz
36 MHz
72 MHz
Figure 8-44. Typical Output Circuits for Analog Video from DACs
During board design, the onboard traces and parasitics must be matched for the channel. The video HDDAC output pins (HDDAC_x) are very high-frequency analog signals and must be routed with extreme
care. As a result, the path of this signal must be as short as possible, and as isolated as possible from
other interfering signals. Other schematic and layout guidelines include:
• The correct external video gain (4.5V/V) must always be provided (even when not using the
recommended video buffer). The recommended video buffer is the THS7360.
• The load resistor (RLOAD) should be placed as close as possible (< 0.5 in.) to the THS7360 video
buffer input pins.
• The 75-Ω series resistors should be placed as close as possible (< 0.5 in.) to the THS7360 video
buffer output pins.
• The trace lengths within a video format group should match as close as possible (for example, for
component video outputs, the Y, Pb, and Pr trace lengths should match each other).
• The characteristic impedance of the HD-DAC output signal traces should match the HD-DAC load
value (165Ω) as close as possible (±10%). The minimum trace width may limit how closely these
impedances can be matched.
• The characteristic impedance of the video buffer output signal traces should match the back
termination value (75 Ω) as close as possible (±10%). The minimum trace width may limit how closely
these impedances can be matched.
• To provide adequate frequency response on the VGA/YPbPr output, recommend the following:
– The length of the signal traces from the HD-DAC output pins to the THS7360 video buffer input pins
should be minimized (< 1 in.) to reduce parasitic capacitance (~2 pF per inch).
– Ensure the THS7360 reconstruction filter is properly programmed for each output format.
– Enable 2x up-sampling for 720p/1080i component video outputs.
• To minimize noise on the VGA/YPbPr output, recommend the following:
– The HD-DAC power supply pins (VDDA_REF_1P8V, VDDA_HD_1P8V) should be connected to a
low-noise 1.8-V analog supply. Use a dedicated voltage regulator for best noise performance.
– The THS7360 power supply pin should be connected to a low-noise 3.3-V analog supply. Use a
dedicated voltage regulator for best noise performance.
– Special care should be taken to provide adequate power supply decoupling on all analog supply
pins (for example, ferrite bead and bypass capacitor).
– Provide a ground guard adjacent to analog video signal traces to minimize noise coupling.
– Provide a low impedance path to ground for the shield of the VGA/YPbPr output connector.
– Include solid ground return paths.
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•
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To
–
–
–
provide adequate ESD protection on the VGA/YPbPr output, recommend the following:
Provide ESD protection on all output signals (that is, Video, Syncs and DDC I/F).
Minimize the distance from the ESD protection device to the VGA/YPbPr output connector.
Mount all ESD protection devices on the PCB level next to the ground plane to provide the lowest
possible impedance path to ground.
– Provide a low impedance path to ground for the shield of the VGA/YPbPr output connector.
For VGA outputs, recommend the following:
– 3.3 V to 5 V level shifters should be used for the H/V Sync signals.
– 3.3 V to 5 V bi-directional level shifters should be used for the DDC signals. This is typically
implemented using two N-channel enhancement MOSFETs.
– Recommend using the TPD7S019 ESD protection device with integrated level shifters for the H/V
Sync and DDC signals.
– The source impedance of the H/V Sync outputs should be 50 Ω.
– The characteristic impedance of the H/V Sync output signal traces should be 50 Ω.
– The THS7360 reconstruction filter should be bypassed to provide maximum bandwidth.
– The 5-V supply output should be current limited (for example, using a series resistor or resettable
fuse).
For additional video HD-DAC design guidelines, see the High Definition Video Processing Subsystem
chapter in the device-specific Technical Reference Manual.
Table 8-40. HD-DAC Recommended Operating Conditions
MIN
NOM
MAX
Output Load Capacitance (CLOAD) (1)
UNIT
5
pF
Output Load Resistors (RLOAD)
–1%
165
+1%
Ω
Full-Scale Current Adjust Resistor (RHDDAC_IREF)
–1%
2.67
+1%
kΩ
Optional External Voltage Reference (HDDAC_VREF) (2)
–5%
467
+5%
mV
Required External Amplification (THS7360)
–3%
4.5
+3%
V/V
(1)
(2)
The output load capacitance includes the signal trace parasitic capacitance and the video buffer input capacitance.
An external voltage reference is not required since an internal bandgap reference is provided.
Table 8-41. HD-DAC Specifications
PARAMETER
CONDITIONS
MIN
Resolution
TYP
MAX
10
UNIT
Bits
DC Accuracy
Integral Non-Linearity (INL), best fit
2.5
LSB
Differential Non-Linearity (DNL)
1.0
LSB
Analog Output
Full-Scale Output Current (IFS)
DAC input = 1023
Full-Scale Output Voltage (VFS)
DAC input = 1023
3
–15%
Zero Scale Offset Error (ZSET)
494
mA
+15%
0.5
Channel matching
mV
LSB
2
%
Dynamic Specifications
Maximum Output Update Rate (FCLK)
Spurious - Free Dynamic Range (SFDR)
212
150
MHz
FCLK = 74.25 MHz,
30-MHz full-scale sine wave
70
dB
FCLK = 148.5 MHz,
30-MHz full-scale sine wave
60
dB
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8.12 Inter-Integrated Circuit (I2C)
The device includes four inter-integrated circuit (I2C) modules which provide an interface to other devices
compliant with Philips Semiconductors Inter-IC bus (I2C-bus™) specification version 2.1. External
components attached to this 2-wire serial bus can transmit/receive 8-bit data to/from the device through
the I2C module. The I2C port does not support CBUS compatible devices.
The I2C port supports the following features:
• Compatible with Philips I2C Specification Revision 2.1 (January 2000)
• Standard and fast modes from 10 - 400 Kbps (no fail-safe I/O buffers)
• Noise filter to remove noise 50 ns or less
• Seven- and ten-bit device addressing modes
• Multimaster transmitter/slave receiver mode
• Multimaster receiver/slave transmitter mode
• Combined master transmit/receive and receive/transmit modes
• Two DMA channels, one interrupt line
• Built-in FIFO (32 byte) for buffered read or write.
For more detailed information on the I2C peripheral, see the Inter-Integrated Circuit (I2C) Controller
Module chapter in the device-specific Technical Reference Manual.
8.12.1 I2C Peripheral Register Descriptions
The I2C peripheral registers are described in the device-specific Technical Reference Manual. Each
register is documented as an offset from a base address for the peripheral. The base addresses for all of
the peripherals are in the device memory map (see Section 2.10).
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8.12.2 I2C Electrical Data/Timing
Table 8-42. Timing Requirements for I2C Input Timings (1)
(see Figure 8-45)
OPP100/OPP120/Turbo
STANDARD
MODE
NO.
MIN
1
MAX
FAST MODE
MIN
UNIT
MAX
tc(SCL)
Cycle time, SCL
10
2.5
µs
2
tsu(SCLH-SDAL)
Setup time, SCL high before SDA low (for a repeated START
condition)
4.7
0.6
µs
3
th(SDAL-SCLL)
Hold time, SCL low after SDA low (for a START and a
repeated START condition)
4
0.6
µs
4
tw(SCLL)
Pulse duration, SCL low
4.7
1.3
µs
5
tw(SCLH)
Pulse duration, SCL high
4
0.6
µs
(2)
6
tsu(SDAV-SCLH)
Setup time, SDA valid before SCL high
250
7
th(SCLL-SDAV)
Hold time, SDA valid after SCL low
0 (3) 3.45 (4)
100
0 (3)
8
tw(SDAH)
Pulse duration, SDA high between STOP and START
conditions
4.7
1.3
9
tr(SDA)
Rise time, SDA
1000
20 + 0.1Cb
(5)
300
ns
10
tr(SCL)
Rise time, SCL
1000
20 + 0.1Cb
(5)
300
ns
300
ns
300
ns
11
tf(SDA)
Fall time, SDA
300
20 + 0.1Cb
(5)
12
tf(SCL)
Fall time, SCL
300
20 + 0.1Cb
(5)
13
tsu(SCLH-SDAH)
Setup time, SCL high before SDA high (for STOP condition)
14
tw(SP)
Pulse duration, spike (must be suppressed)
15
(5)
(1)
(2)
(3)
(4)
(5)
Cb
4
ns
0.9 (4)
µs
0.6
µs
0
Capacitive load for each bus line
400
µs
50
ns
400
pF
The I2C pins SDA and SCL do not feature fail-safe I/O buffers. These pins could potentially draw current when the device is powered
down.
A Fast-mode I2C-bus™ device can be used in a Standard-mode I2C-bus system, but the requirement tsu(SDA-SCLH)≥ 250 ns must then be
met. This will automatically be the case if the device does not stretch the LOW period of the SCL signal. If such a device does stretch
the LOW period of the SCL signal, it must output the next data bit to the SDA line tr max + tsu(SDA-SCLH)= 1000 + 250 = 1250 ns
(according to the Standard-mode I2C-Bus Specification) before the SCL line is released.
A device must internally provide a hold time of at least 300 ns for the SDA signal (referred to the VIHmin of the SCL signal) to bridge the
undefined region of the falling edge of SCL.
The maximum th(SDA-SCLL) has only to be met if the device does not stretch the low period [tw(SCLL)] of the SCL signal.
Cb = total capacitance of one bus line in pF. If mixed with HS-mode devices, faster fall-times are allowed.
9
11
I2C[x]_SDA
6
8
14
4
13
5
10
I2C[x]_SCL
1
12
3
7
2
3
Stop
Start
Repeated
Start
Stop
Figure 8-45. I2C Receive Timing
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Table 8-43. Switching Characteristics Over Recommended Operating Conditions for I2C Output Timings
(see Figure 8-46)
OPP100/OPP120/Turbo
NO.
STANDARD
MODE
PARAMETER
MIN
16
(1)
MAX
FAST MODE
MIN
UNIT
MAX
tc(SCL)
Cycle time, SCL
10
2.5
µs
17
tsu(SCLH-SDAL)
Setup time, SCL high before SDA low (for a repeated START
condition)
4.7
0.6
µs
18
th(SDAL-SCLL)
Hold time, SCL low after SDA low (for a START and a repeated
START condition)
4
0.6
µs
19
tw(SCLL)
Pulse duration, SCL low
4.7
1.3
µs
20
tw(SCLH)
Pulse duration, SCL high
4
0.6
µs
21
tsu(SDAV-SCLH)
Setup time, SDA valid before SCL high
250
100
22
th(SCLL-SDAV)
Hold time, SDA valid after SCL low (for I2C bus devices)
23
tw(SDAH)
Pulse duration, SDA high between STOP and START
conditions
24
tr(SDA)
Rise time, SDA
1000
20 + 0.1Cb
300
ns
25
tr(SCL)
Rise time, SCL
1000
20 + 0.1Cb
300
ns
26
tf(SDA)
Fall time, SDA
300
20 + 0.1Cb
300
ns
27
tf(SCL)
Fall time, SCL
300
20 + 0.1Cb
300
ns
28
tsu(SCLH-SDAH)
Setup time, SCL high before SDA high (for STOP condition)
29
Cp
Capacitance for each I2C pin
0
3.45
4.7
0
ns
0.9
µs
1.3
4
(1)
(1)
(1)
(1)
µs
0.6
10
µs
10
pF
Cb = total capacitance of one bus line in pF. If mixed with HS-mode devices, faster fall-times are allowed.
24
26
I2C[x]_SDA
21
23
19
28
20
25
I2C[x]_SCL
27
16
18
22
17
18
Stop
Start
Repeated
Start
Stop
Figure 8-46. I2C Transmit Timing
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8.13 Imaging Subsystem (ISS)
The device Imaging Subsystem captures and processes pixel data from external image and video inputs.
The inputs can be connected to the Image Processing block through the Parallel Camera Interface (CAM).
In addition, a Timing control module provides flash strobe and mechanical shutter interfaces. The features
of each component of the ISS are described below.
• Parallel Camera (CAM) interface features:
– Input format
• Bayer pattern Raw (up to 16bit) or YCbCr 422 (8-bit or 16-bit) data.
• ITU-R BT.656/1120 standard format
– Generates HD/VD timing signals and field ID to an external timing generator, or can synchronize to
the external timing generator.
– Support for progressive and interlaced sensors (hardware support for up to 2 fields and firmware
supports for higher number of fields, typically 3-, 4-, and 5-field sensors.
• CSI2 Serial Connection features:
– Supports up to 1Gb/s data-rate per lane for 1, 2, and 3 Data-lane configurations, and up to
824Mbps per lane for a 4 Data-lane configuration
– Supports sensor capture up to 4K x 2K 10-bit Bayer @ 30fps
– Supports up to four data configurable links in addition to the clock signaling
– Data merger for 2-, 3-, or 4-data lane configurations
– 1-D and 2-D addressing mode
– Supports all primary and secondary MIPI-defined formats (RGB, RAW, YUV, and more)
– DPCM decompression
– Image cropping and A-Law/DPCM compression
• Image Sensor Interface (ISIF) features:
– Support for up to 32K pixels (image size) in both the horizontal and vertical direction
– Color space conversion for non-Bayer pattern Raw data
– Digital black clamping with Horizontal/Vertical offset drift compensation
– Vertical Line defect correction based on a lookup table
– Color-dependent gain control and black level offset control
– Ability to control output to the DDR2/DDR3/DDR3L via an external write enable signal
– Down sampling via programmable culling patterns
– A-law/DPCM compression
– Generating 16-, 12- or 8-bit output to memory
• Two independent Resizers
– Providing two different sizes of outputs simultaneously on one input
– Maximum line width is 5376 and 2336, respectively
– YUV422 to YUV420 conversion
– Data output format: RGB565, ARGB888, YUV422 co sited and YUV4:2:0 planar
– Resizer Ratio: x1/4096 ~ x20
– Input from memory
• Timing control module features:
– STROBE signal for flash pre-strobe and flash strobe
– SHUTTER signal for mechanical shutter control
– Global reset control
For more detailed information on the ISS, see the ISS Overview section, the ISS Interfaces section, and
the ISS ISP section of the device-specific Technical Reference Manual.
216
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8.13.1 ISS Peripheral Register Description
The ISS peripheral registers are described in the device-specific Technical Reference Manual. Each
register is documented as an offset from a base address for the peripheral. The base addresses for all of
the peripherals are in the device memory map (see Section 2.10).
8.13.2 ISSCAM Electrical Data/Timing
Table 8-44. Timing Requirements for ISSCAM (1) (see Figure 8-47)
OPP100/OPP120/Turb
o
UNIT
MIN NOM
MAX
N
O.
1
tc(PCLK)
Cycle time, PCLK
6.17
ns
2
tw(PCLKH)
Pulse duration, PCLK high
2.78
ns
3
tw(PCLKL)
Pulse duration, PCLK low
2.78
4
tt(PCLK)
Transition time, PCLK
ns
2.64
tsu(DATA-
ns
3.11
ns
tsu(DE-PCLK)
3.11
ns
tsu(VS-PCLK) Input setup time, Data/Control valid before PCLK high/low
3.11
ns
tsu(HS-PCLK)
3.11
ns
tsu(FLD-
3.11
ns
-0.5
ns
0.0
ns
-0.5
ns
-0.5
ns
-0.5
ns
-0.5
ns
PCLK)
5
PCLK)
th(PCLK-
≤ 148.5 MHz clock rate
Input hold time, Data valid after PCLK high/low
DATA)
6
> 148.5 MHz and
≤ 162 MHz clock rate
th(PCLK-DE)
th(PCLK-VS)
th(PCLK-HS)
Input hold time, Control valid after PCLK high/low
th(PCLK-FLD)
(1)
H = period of baud rate, 1/programmed baud rate.
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Table 8-45. Switching Characteristics Over Recommended Operating Conditions for ISSCAM (see
Figure 8-47)
NO.
OPP100/OPP120/Turbo
PARAMETER
MIN
MAX
UNIT
15
td(PCLK-FLD)
Delay time, PCLK rising/falling clock edge to Control valid
1.64
14.68
ns
16
td(PCLK-VS)
Delay time, PCLK rising/falling clock edge to Control valid
1.64
14.68
ns
17
td(PCLK-HS)
Delay time, PCLK rising/falling clock edge to Control valid
1.64
14.68
ns
18
td(PCLK-STROBE)
Delay time, PCLK rising/falling clock edge to Control valid
1.64
14.68
ns
19
td(PCLK-SHUTTER)
Delay time, PCLK rising/falling clock edge to Control valid
1.64
14.68
ns
PCLK
(negative edge clocking)
4
1
3
PCLK
(positive edge clocking)
2
4
Data/Control input
5
6
Data/Control output
7
Figure 8-47. ISSCAM Timings
8.13.3 CSI2 PCB Layout Specifications
The following PCB guidelines for CSI2 working at 1 Gbps (up to 3 data lanes), 824 Mbps (up to 4 data
lanes), and 800 Mbps (up to 4 data lanes) are based on a three-step design and validation methodology.
For the design of the PCB differential lines, PCB designers need to keep in mind the requirements of Step
1 and Step 2: the characteristic impedance must be 50 Ω, the total length must be smaller than 100 mm,
and the length mismatch requirements must be satisfied.
After the PCB design is finished, the S-parameters of the PCB differential lines will be extracted with a 3D
Maxwell Equation Solver, such as High-Frequency Structure Simulator (HFSS) or equivalent, and
compared to the frequency-domain specification as outlined in Step 3 of the design methodology. If the
PCB lines satisfy the frequency-domain specification, the design is done. Otherwise, the design needs to
be improved.
8.13.3.1 Step 1: General Guidelines
The general guidelines for the PCB differential lines of CSI2 are given as:
• Single-ended Z0 = 50 Ω
• Total conductor length on the board < 100 mm
In this step, the general rule of thumb for the space S = 2 × W is not designated. Although the S = 2 × W
rule is a good rule of thumb, it is not always the best solution. The electrical performance will be checked
with the frequency-domain specification in Step 3. Even if the design does not follow the S = 2 × W rule,
the differential lines are okay if the lines satisfy the frequency-domain specification in Step 3.
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8.13.3.2 Step 2: Length Mismatch Guidelines
8.13.3.2.1 CSI2 at 1.0 Gbps
The guidelines of the length mismatch for CSI2 at 1.0 Gbps are presented in Table 8-46. The intralane
length mismatch must be less than 0.5 mm, and the interlane length mismatch must be less than 1.5 mm.
Table 8-46. Length Mismatch Guidelines for CSI2 at 1.0 Gbps
PARAMETER
TYPICAL VALUE
UNIT
Operating speed
1000
Mbps
UI (bit time)
1000
ps
Intralane skew (UI / 300)
Length between N and P traces
3
ps
0.5
mm
Interlane skew (UI / 100)
10
ps
Length between pairs
1.5
mm
8.13.3.2.2 CSI2 at 824 Mbps
The guidelines of the length mismatch for CSI2 at 824 Mbps are presented in Table 8-47. The intralane
length mismatch must be less than 0.6 mm, and the interlane length mismatch must be less than 1.8 mm.
Table 8-47. Length Mismatch Guidelines for CSI2 at 824 Mbps
PARAMETER
TYPICAL VALUE
UNIT
Operating speed
824
Mbps
UI (bit time)
1213
ps
Intralane skew (UI / 300)
4
ps
Length between N and P traces
0.6
mm
Interlane skew (UI / 100)
12
ps
Length between pairs
1.8
mm
8.13.3.2.3 CSI2 at 800 Mbps
The guidelines of the length mismatch for CSI2 at 800 Mbps are presented in Table 8-48. The intralane
length mismatch must be less than 0.6 mm, and the interlane length mismatch must be less than 1.8 mm.
Table 8-48. Length Mismatch Guidelines for CSI2 at 800 Mbps
PARAMETER
TYPICAL VALUE
UNIT
Operating speed
800
Mbps
UI (bit time)
1250
ps
4
ps
Length between N and P traces
0.6
mm
Interlane skew (UI / 100)
12
ps
Length between pairs
1.8
mm
Intralane skew (UI / 300)
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8.13.3.3 Step 3: Frequency-Domain Specification Guidelines
The PCB differential lines should be drawn in order to satisfy the Step 1 and Step 2 requirements.
However, although the PCB designer may draw the lines carefully, the lines can have poor electrical
performance due to many reasons.
Vertical connections such as vias and non-uniform line connections can degrade the electrical
performance of the differential lines. The ground design around the lines can also affect the electrical
performance. To ensure that the differential lines are well designed, the frequency-domain behavior must
be compared to the frequency-domain specification.
1. Intralane frequency-domain specification
– Differential-mode characteristics
– Sdd12, Sdd11/Sdd22
– Common-mode characteristics
– Scc11/Scc22
– Mode-conversion characteristics
– Scd11, Scd12, Scd21, Scd22, Sdc11, Sdc12, Sdc21, Sdc22
2. Interlane frequency-domain specification
– Differential-mode characteristics
– Sdd11/Sdd22
– Common-mode characteristics
– Scc11/Scc22
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8.14 DDR2/DDR3/DDR3L Memory Controller
The device has a dedicated interface to DDR3L, DDR3 and DDR2 SDRAM. It supports DDR2, DDR3 and
DDR3L SDRAM devices with the following features:
• 16-bit or 32-bit data path to external SDRAM memory
• Memory device capacity: 64Mb, 128Mb, 256Mb, 512Mb, 1Gb, 2Gb, and 4Gb devices
• One interface with associated DDR2/DDR3/DDR3L PHY
For details on the DDR2, DDR3 and DDR3L Memory Controller, see the DDR2/DDR3/DDR3L Memory
Controller chapter in the device-specific Technical Reference Manual.
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8.14.1 DDR2/3/3L Memory Controller Register Descriptions
The DDR2/3/3L peripheral registers are described in the device-specific Technical Reference Manual.
Each register is documented as an offset from a base address for the peripheral. The base addresses for
all of the peripherals are in the device memory map (see Section 2.10).
8.14.2 DDR2 Routing Specifications
8.14.2.1 Board Designs
TI only supports board designs that follow the guidelines outlined in this document. The switching
characteristics and the timing diagram for the DDR2 memory controller are shown in Table 8-49 and
Figure 8-48.
Table 8-49. Switching Characteristics Over Recommended Operating Conditions for DDR2 Memory
Controller
NO.
1
-1G
PARAMETER
tc(DDR_CLK)
Cycle time, DDR_CLK
MIN
MAX
2.5
8
UNIT
ns
1
DDR_CLK
Figure 8-48. DDR2 Memory Controller Clock Timing
8.14.2.2 DDR2 Interface
This section provides the timing specification for the DDR2 interface as a PCB design and manufacturing
specification. The design rules constrain PCB trace length, PCB trace skew, signal integrity, cross-talk,
and signal timing. These rules, when followed, result in a reliable DDR2 memory system without the need
for a complex timing closure process. For more information regarding the guidelines for using this DDR2
specification, see the Understanding TI’s PCB Routing Rule-Based DDR Timing Specification Application
Report (Literature Number: SPRAAV0).
8.14.2.2.1 DDR2 Interface Schematic
Figure 8-49 shows the DDR2 interface schematic for a x32 DDR2 memory system. In Figure 8-50 the x16
DDR2 system schematic is identical except that the high-word DDR2 device is deleted.
When not using a DDR2 interface, the proper method of handling the unused pins is to tie off the DQS
pins by pulling the non-inverted DQS pin to the DVDD_DDR[0] supply via a 1k-Ω resistor and pulling the
inverted DQS pin to ground via a 1k-Ω resistor. This needs to be done for each byte not used. Also,
include the 50-Ω pulldown for DDR[0]_VTP. The DVDD_DDR[0] and VREFSSTL_DDR[0] power supply
pins must be connected to their respective power supplies even if DDR[0] is not used. All other DDR
interface pins can be left unconnected. Note that the supported modes for use of the DDR EMIF are 32bits wide, 16-bits wide, or not used.
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DDR2
DDR[0]_D[0]
DQ0
DDR[0]_D[7]
DDR[0]_DQM[0]
DDR[0]_DQS[0]
DQ7
LDM
LDQS
DDR[0]_DQS[0]
DDR[0]_D[8]
LDQS
DQ8
DDR[0]_D[15]
DDR[0]_DQM[1]
DDR[0]_DQS[1]
DQ15
UDM
UDQS
DDR[0]_DQS[1]
DDR[0]_ODT[0]
UDQS
ODT
T0
DDR2
ODT
DDR[0]_D[16]
DQ0
DDR[0]_D[23]
DDR[0]_DQM[2]
DDR[0]_DQS[2]
DDR[0]_DQS[2]
DDR[0]_D[24]
DQ7
LDM
LDQS
LDQS
DQ8
DDR[0]_D[31]
DDR[0]_DQM[3]
DDR[0]_DQS[3]
DDR[0]_DQS[3]
DQ15
UDM
UDQS
UDQS
DDR[0]_BA[0]
T0
BA0
BA0
DDR[0]_BA[2]
DDR[0]_A[0]
T0
T0
BA2
A0
BA2
A0
DDR[0]_A[15]
DDR[0]_CS[0]
T0
T0
A15
CS
A15
CS
DDR[0]_CAS
DDR[0]_RAS
T0
T0
CAS
RAS
CAS
DDR[0]_WE
DDR[0]_CKE
DDR[0]_CLK
T0
T0
T0
T0
WE
CKE
CK
CK
VREF
WE
CKE
CK
CK
VREF
DDR[0]_CLK
VREFSSTL_DDR[0]
0.1 µF
DDR[0]_RST
(B)
(B)
0.1 µF
(A)
Vio 1.8
RAS
VREF
0.1 µF
0.1 µF
VREF
1 K Ω 1%
VREF
(B)
0.1 µF
1 K Ω 1%
NC
DDR[0]_VTP
50 Ω (±2%)
T0
A.
B.
Termination is required. See terminator comments.
Vio1.8 is the power supply for the DDR2 memories and the device DDR2 interface.
One of these capacitors can be eliminated if the divider and its capacitors are placed near a VREF pin.
Figure 8-49. 32-Bit DDR2 High-Level Schematic
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DDR2
DDR[0]_D[0]
DQ0
DDR[0]_D[7]
DDR[0]_DQM[0]
DDR[0]_DQS[0]
DQ7
LDM
LDQS
DDR[0]_DQS[0]
DDR[0]_D[8]
LDQS
DQ8
DDR[0]_D[15]
DDR[0]_DQM[1]
DDR[0]_DQS[1]
DDR[0]_DQS[1]
DQ15
UDM
UDQS
UDQS
DDR[0]_ODT[0]
T0
ODT
DDR[0]_D[16]
NC
DDR[0]_D[23]
DDR[0]_DQM[2]
NC
NC
1 KΩ
DDR[0]_D[24]
NC
1 KΩ
DDR[0]_D[31]
DDR[0]_DQM[3]
DDR[0]_DQS[3]
DDR[0]_DQS[3]
NC
NC
(A)
Vio 1.8
DDR[0]_DQS[2]
DDR[0]_DQS[2]
(A)
Vio 1.8
1 KΩ
1 KΩ
DDR[0]_BA[0]
T0
BA0
DDR[0]_BA[2]
DDR[0]_A[0]
T0
T0
BA2
A0
DDR[0]_A[15]
DDR[0]_CS[0]
T0
T0
A15
CS
DDR[0]_CAS
DDR[0]_RAS
DDR[0]_WE
DDR[0]_CKE
DDR[0]_CLK
T0
T0
T0
T0
T0
T0
CAS
DDR[0]_CLK
VREFSSTL_DDR[0]
VREF
(B)
0.1 µF
VREF
1 K Ω 1%
VREF
(B)
0.1 µF
DDR[0]_RST
(A)
Vio 1.8
RAS
WE
CKE
CK
CK
0.1 µF
0.1 µF
1 K Ω 1%
NC
DDR[0]_VTP
50 Ω (±2%)
T0
A.
B.
Termination is required. See terminator comments.
Vio1.8 is the power supply for the DDR2 memories and the device DDR2 interface.
One of these capacitors can be eliminated if the divider and its capacitors are placed near a VREF pin.
Figure 8-50. 16-Bit DDR2 High-Level Schematic
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8.14.2.2.2 Compatible DDR2 Devices
Table 8-50 shows the parameters of the DDR2 devices that are compatible with this interface. Generally,
the DDR2 interface is compatible with x16 DDR2-800 speed grade DDR2 devices.
Table 8-50. Compatible DDR2 Devices (Per Interface)
NO.
(1)
(2)
(3)
PARAMETER
MIN
MAX
UNIT
1
DDR2 device speed grade (1)
2
DDR2 device bit width
x16
x16
3
DDR2 device count (2)
1
2
Devices
4
DDR2 device ball count (3)
84
92
Balls
DDR2-800
Bits
Higher DDR2 speed grades are supported due to inherent DDR2 backwards compatibility.
One DDR2 device is used for a 16-bit DDR2 memory system. Two DDR2 devices are used for a 32-bit DDR2 memory system.
The 92-ball devices are retained for legacy support. New designs will migrate to 84-ball DDR2 devices. Electrically, the 92- and 84-ball
DDR2 devices are the same.
8.14.2.2.3 PCB Stackup
The minimum stackup required for routing the device is a six-layer stackup as shown in Table 8-51.
Additional layers may be added to the PCB stackup to accommodate other circuitry or to reduce the size
of the PCB footprint.
Table 8-51. Minimum PCB Stackup
LAYER
TYPE
DESCRIPTION
1
Signal
Top routing mostly horizontal
2
Plane
Ground
3
Plane
Power
4
Signal
Internal routing
5
Plane
Ground
6
Signal
Bottom routing mostly vertical
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Complete stackup specifications are provided in Table 8-52.
Table 8-52. PCB Stackup Specifications
NO.
PARAMETER
MIN
TYP
1
PCB routing/plane layers
6
2
Signal routing layers
3
3
Full ground layers under DDR2 routing region
2
4
Number of ground plane cuts allowed within DDR routing region
5
Number of ground reference planes required for each DDR2 routing layer
6
Number of layers between DDR2 routing layer and reference ground plane
7
PCB feature spacing
4
8
PCB trace width, w
4
9
PCB BGA escape via pad size (1)
10
PCB BGA escape via hole size
11
Processor BGA pad size
13
Single-ended impedance, Zo
14
Impedance control (2)
(1)
(2)
226
MAX
UNIT
0
1
0
18
(1)
Mils
Mils
20
10
Mils
0.4
50
Z-5
Z
Mils
mm
75
Ω
Z+5
Ω
A 20/10 via may be used if enough power routing resources are available. An 18/10 via allows for more flexible power routing to the
processor.
Z is the nominal singled-ended impedance selected for the PCB specified by item 13.
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8.14.2.2.4 Placement
Figure 8-51 shows the required placement for the processor as well as the DDR2 devices. The
dimensions for this figure are defined in Table 8-53. The placement does not restrict the side of the PCB
on which the devices are mounted. The ultimate purpose of the placement is to limit the maximum trace
lengths and allow for proper routing space. For a 16-bit DDR memory system, the high-word DDR2 device
is omitted from the placement.
Recommended DDR2 Device
Orientation
X
X1
A1
A1
X1
X1
OFFSET OFFSET
DDR2
Controller
Y
Figure 8-51. Device and DDR2 Device Placement
Table 8-53. Placement Specifications
NO.
(1)
(2)
(3)
(4)
(5)
PARAMETER
MIN
(1) (2)
1
X+Y
2
X' (1) (2)
3
X' Offset (1) (2)
4
DDR2 keepout region (4)
5
Clearance from non-DDR2 signal to DDR2 keepout region (5)
(3)
MAX
UNIT
1660
Mils
1280
Mils
650
Mils
4
w
For dimension definitions, see Figure 8-49.
Measurements from center of processor to center of DDR2 device.
For 16-bit memory systems, it is recommended that X' offset be as small as possible.
DDR2 keepout region to encompass entire DDR2 routing area.
Non-DDR2 signals allowed within DDR2 keepout region provided they are separated from DDR2 routing layers by a ground plane.
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8.14.2.2.5 DDR2 Keepout Region
The region of the PCB used for the DDR2 circuitry must be isolated from other signals. The DDR2
keepout region is defined for this purpose and is shown in Figure 8-52. The size of this region varies with
the placement and DDR routing. Additional clearances required for the keepout region are shown in
Table 8-53.
A1
DDR2 Device
A1
A1
DDR2 Controller
A1
Figure 8-52. DDR2 Keepout Region
NOTE
The region shown in should encompass all the DDR2 circuitry and varies depending on
placement. Non-DDR2 signals should not be routed on the DDR signal layers within the
DDR2 keepout region. Non-DDR2 signals may be routed in the region, provided they are
routed on layers separated from DDR2 signal layers by a ground layer. No breaks should be
allowed in the reference ground layers in this region. In addition, the 1.8-V power plane
should cover the entire keepout region. Routes for the DDR interface must be separated by
at least 4x; the more separation, the better.
8.14.2.2.6 Bulk Bypass Capacitors
Bulk bypass capacitors are required for moderate speed bypassing of the DDR2 and other circuitry.
Table 8-54 contains the minimum numbers and capacitance required for the bulk bypass capacitors. Note
that this table only covers the bypass needs of the DDR2 interfaces and DDR2 device. Additional bulk
bypass capacitance may be needed for other circuitry.
Table 8-54. Bulk Bypass Capacitors
No.
Parameter
Min
Max
Unit
1
DVDD18 bulk bypass capacitor count (1)
3
Devices
2
DVDD18 bulk bypass total capacitance
30
μF
1
Devices
10
μF
(1)
3
DDR bulk bypass capacitor count
4
DDR bulk bypass total capacitance (1)
(1)
These devices should be placed near the device they are bypassing, but preference should be given to the placement of the high-speed
(HS) bypass capacitors.
8.14.2.2.7 High-Speed Bypass Capacitors
High-speed (HS) bypass capacitors are critical for proper DDR2 interface operation. It is particularly
important to minimize the parasitic series inductance of the HS bypass capacitors, processor/DDR power,
and processor/DDR ground connections. Table 8-55 contains the specification for the HS bypass
capacitors as well as for the power connections on the PCB. Due to the number of required bypass
capacitors, it is recommended that the bypass capacitors are placed before routing the board.
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Table 8-55. High-Speed Bypass Capacitors
NO.
PARAMETER
MIN
1
HS bypass capacitor package size (1)
2
Distance from HS bypass capacitor to device being bypassed
3
Number of connection vias for each HS bypass capacitor (2)
2
4
Trace length from bypass capacitor contact to connection via
1
5
Number of connection vias for each processor power/ground ball
1
6
Trace length from processor power/ground ball to connection via
7
Number of connection vias for each DDR2 device power/ground ball
8
Trace length from DDR2 device power/ground ball to connection via
9
DVDD18 HS bypass capacitor count (3)
20
10
DVDD18 HS bypass capacitor total capacitance
1.2
11
DDR device HS bypass capacitor count (4) (5)
12
DDR device HS bypass capacitor total capacitance (5)
(1)
(2)
(3)
(4)
(5)
MAX
UNIT
0402
10 Mils
250
Mils
Vias
30
Mils
Vias
35
Mils
1
Vias
35
8
Mils
Devices
μF
Devices
0.4
μF
LxW, 10-mil units, that is, a 0402 is a 40x20-mil surface-mount capacitor.
An additional HS bypass capacitor can share the connection vias only if it is mounted on the opposite side of the board.
These devices should be placed as close as possible to the device being bypassed.
These devices should be placed as close as possible to the device being bypassed.
Per DDR device.
8.14.2.2.8 Net Classes
Table 8-56 lists the clock net classes for the DDR2 interface. Table 8-57 lists the signal net classes, and
associated clock net classes, for the signals in the DDR2 interface. These net classes are used for the
termination and routing rules that follow.
Table 8-56. Clock Net Class Definitions
CLOCK NET CLASS
PROCESSOR PIN NAMES
CK
DDR[0]_CLK/DDR[0]_CLK
(1)
DQS0
DDR[0]_DQS[0]/DDR[0]_DQS[0]
DQS1
DDR[0]_DQS[1]/DDR[0]_DQS[1]
DQS2 (1)
DDR[0]_DQS[2]/DDR[0]_DQS[2]
DQS3 (1)
DDR[0]_DQS[3]/DDR[0]_DQS[3]
Only used on 32-bit wide DDR2 memory systems.
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Table 8-57. Signal Net Class Definitions
CLOCK NET CLASS
ASSOCIATED CLOCK
NET CLASS
ADDR_CTRL
CK
DQ0
DQS0
DDR[0]_D[7:0], DDR[0]_DQM[0]
DQ1
DQS1
DDR[0]_D[15:8], DDR[0]_DQM[1]
DQ2 (1)
DQS2
DDR[0]_D[23:16], DDR[0]_DQM[2]
(1)
DQS3
DDR[0]_D[31:24], DDR[0]_DQM[3]
DQ3
(1)
PROCESSOR PIN NAMES
DDR[0]_BA[2:0], DDR[0]_A[15:0], DDR[0]_CS[x], DDR[0]_CAS,
DDR[0]_RAS, DDR[0]_WE, DDR[0]_CKE, DDR[0]_ODT[0]
Only used on 32-bit wide DDR2 memory systems.
8.14.2.2.9 DDR2 Signal Termination
Signal terminators are required in CK and ADDR_CTRL net classes. Serial terminators may be used on
data lines to reduce EMI risk; however, serial terminations are the only type permitted. ODT's are
integrated on the data byte net classes. They should be enabled to ensure signal integrity.Table 8-58
shows the specifications for the series terminators.
Table 8-58. DDR2 Signal Terminations
NO.
1
PARAMETER
TYP
0
(1) (2) (3) (4)
2
ADDR_CTRL net class
3
Data byte net classes (DQS0-DQS3, DQ0-DQ3) (5)
(1)
(2)
(3)
(4)
(5)
MIN
CK net class (1) (2)
0
0
22
MAX
UNIT
10
Ω
Zo
Ω
Zo
Ω
Only series termination is permitted, parallel or SST specifically disallowed on board.
Only required for EMI reduction.
Terminator values larger than typical only recommended to address EMI issues.
Termination value should be uniform across net class.
No external terminations allowed for data byte net classes. ODT is to be used.
8.14.2.2.10 VREFSSTL_DDR Routing
VREFSSTL_DDR is used as a reference by the input buffers of the DDR2 memories as well as the
processor. VREF is intended to be half the DDR2 power supply voltage and should be created using a
resistive divider as shown in Figure 8-50. Other methods of creating VREF are not recommended.
Figure 8-53 shows the layout guidelines for VREF.
VREF Nominal Max Trace
width is 20 mils
VREF Bypass Capacitor
A1
+
DDR2 Device
A1
+
DDR2 Controller
Neck down to minimum in BGA escape
regions is acceptable. Narrowing to
accomodate via congestion for short
distances is also acceptable. Best
performance is obtained if the width
of VREF is maximized.
Figure 8-53. VREF Routing and Topology
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8.14.2.3 DDR2 CK and ADDR_CTRL Routing
Figure 8-54 shows the topology of the routing for the CK and ADDR_CTRL net classes. The route is a
balanced T as it is intended that the length of segments B and C be equal. In addition, the length of A
(A'+A'') should be maximized.
A1
A1
C
B
T
A´
DDR2
Controller
A´´
A = A´ + A´´
Figure 8-54. CK and ADDR_CTRL Routing and Topology
Table 8-59. CK and ADDR_CTRL Routing Specification
NO.
PARAMETER
MIN
(1)
TYP
MAX
UNIT
1
Center-to-center CK-CK spacing
2w
2
CK/CK skew (1)
25
Mils
3
CK A-to-B/A-to-C skew length mismatch (2)
25
Mils
4
CK B-to-C skew length mismatch
25
Mils
5
Center-to-center CK to other DDR2 trace spacing (3)
6
CK/ADDR_CTRL nominal trace length (4)
CACLM+50
Mils
7
ADDR_CTRL-to-CK skew length mismatch
100
Mils
8
ADDR_CTRL-to-ADDR_CTRL skew length mismatch
100
Mils
9
Center-to-center ADDR_CTRL to other DDR2 trace spacing (3)
4w
10
Center-to-center ADDR_CTRL to other ADDR_CTRL trace spacing (3)
3w
11
ADDR_CTRL A-to-B/A-to-C skew length mismatch (2)
100
Mils
12
ADDR_CTRL B-to-C skew length mismatch
100
Mils
(1)
(2)
(3)
(4)
4w
CACLM-50
CACLM
The length of segment A = A' + A′′ as shown in Figure 8-54.
Series terminator, if used, should be located closest to the device.
Center-to-center spacing is allowed to fall to minimum (2w) for up to 500 mils of routed length to accommodate BGA escape and routing
congestion.
CACLM is the longest Manhattan distance of the CK and ADDR_CTRL net classes.
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Figure 8-55 shows the topology and routing for the DQS and DQ net classes; the routes are point to point.
Skew matching across bytes is not needed nor recommended.
A1
T
A1
T
E0
E2
T
T
E1
DDR2
Controller
E3
Figure 8-55. DQS and DQ Routing and Topology
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Table 8-60. DQS and DQ Routing Specification
NO.
PARAMETER
MIN
1
Center-to-center DQS-DQSn spacing in E0|E1|E2|E3
2
DQS-DQSn skew in E0|E1|E2|E3
3
Center-to-center DQS to other DDR2 trace spacing (1)
4
DQS/DQ nominal trace length
5
DQ-to-DQS skew length mismatch (2) (3) (4)
6
DQ-to-DQ skew length mismatch (2) (3) (4)
(2) (3) (4)
DQLM-50
DQLM
(2) (3) (4)
DQ-to-DQ/DQS via count mismatch
Center-to-center DQ to other DDR2 trace spacing (1) (5)
4w
9
Center-to-center DQ to other DQ trace spacing (1) (6) (7)
3w
DQ/DQS E skew length mismatch
UNIT
25
Mils
DQLM+50
Mils
100
Mils
100
Mils
1
Vias
100
Mils
4w
8
10
MAX
2w
7
(1)
TYP
(2) (3) (4)
Center-to-center spacing is allowed to fall to minimum (2w) for up to 500 mils of routed length to accommodate BGA escape and routing
congestion.
A 16-bit DDR memory system has two sets of data net classes; one for data byte 0, and one for data byte 1, each with an associated
DQS (2 DQSs) per DDR EMIF used.
A 32-bit DDR memory system has four sets of data net classes; one each for data bytes 0 through 3, and each associated with a DQS
(4 DQSs) per DDR EMIF used.
There is no need, and it is not recommended, to skew match across data bytes; that is, from DQS0 and data byte 0 to DQS1 and data
byte 1.
DQs from other DQS domains are considered other DDR2 trace.
DQs from other data bytes are considered other DDR2 trace.
DQLM is the longest Manhattan distance of each of the DQS and DQ net classes.
(2)
(3)
(4)
(5)
(6)
(7)
8.14.3 DDR3/DDR3L Routing Specifications
8.14.3.1 Board Designs
TI only supports board designs utilizing DDR3/DDR3L memory that follow the guidelines in this document.
The switching characteristics and timing diagram for the DDR3/DDR3L memory controller are shown in
Table 8-61 and Figure 8-56. For the remainder of this section, DDR3 refers to both DDR3 and DDR3L.
Table 8-61. Switching Characteristics Over Recommended Operating Conditions for DDR3 Memory
Controller
NO.
1
(1)
-1G
PARAMETER
tc(DDR_CLK)
Cycle time, DDR_CLK
MIN
MAX
1.876
3.3 (1)
UNIT
ns
This is the absolute maximum the clock period can be. Actual maximum clock period may be limited by DDR3 speed grade and
operating frequency (see the DDR2/3 Memory Controller chapter in the device-specific Technical Reference Manual).
1
DDR_CLK
Figure 8-56. DDR3 Memory Controller Clock Timing
8.14.3.1.1 DDR3 versus DDR2
This specification only covers device PCB designs that utilize DDR3 memory. Designs using DDR2
memory should use the PCB design specifications for DDR2 memory in Section 8.14.2. While similar, the
two memory systems have different requirements. It is currently not possible to design one PCB that
covers both DDR2 and DDR3.
8.14.3.2 DDR3 Device Combinations
Since there are several possible combinations of device counts and single- or dual-side mounting,
Table 8-62 summarizes the supported device configurations.
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Table 8-62. Supported DDR3 Device Combinations
NUMBER OF DDR3 DEVICES
DDR3 DEVICE WIDTH (BITS)
MIRRORED?
DDR3 EMIF WIDTH (BITS)
1
16
N
16
2
8
Y (1)
16
2
16
N
32
(1)
(2)
Y
(1)
2
16
4
8
N
32
32
4
8
Y (2)
32
Two DDR3 devices are mirrored when one device is placed on the top of the board and the second device is placed on the bottom of
the board.
This is two mirrored pairs of DDR3 devices.
8.14.3.3 DDR3 Interface Schematic
8.14.3.3.1 32-Bit DDR3 Interface
The DDR3 interface schematic varies, depending upon the width of the DDR3 devices used and the width
of the bus used (16 or 32 bits). General connectivity is straightforward and very similar. 16-bit DDR
devices look like two 8-bit devices. Figure 8-57 and Figure 8-58 show the schematic connections for 32-bit
interfaces using x16 devices.
8.14.3.3.2 16-Bit DDR3 Interface
Note that the 16-bit wide interface schematic is practically identical to the 32-bit interface (see Figure 8-57
and Figure 8-58); only the high-word DDR memories are removed and the unused DQS inputs are tied off.
The processor DDR[0]_DQS[2] and DDR[0]_DQS[3] pins should be pulled to the DDR supply via 1-kΩ
resistors. Similarly, the DDR[0]_DQS[2] and DDR[0]_DQS[3] pins should be pulled to ground via 1-kΩ
resistors.
When not using a DDR interface, the proper method of handling the unused pins is to tie off the
DDR[0]_DQS[n] pins to the corresponding DVDD_DDR[0] supply via a 1-kΩ resistor and pulling the
DDR[0]_DQS[n] pins to ground via a 1k-Ω resistor. This needs to be done for each byte not used.
Although these signals have internal pullups and pulldowns, external pullups and pulldowns provide
additional protection against external electrical noise causing activity on the signals.
Also, include the 50-Ω pulldown for DDR[0]_VTP. The DVDD_DDR[0] and VREFSSTL_DDR[0] power
supply pins must be connected to their respective power supplies even if DDR[0] is not used. All other
DDR interface pins can be left unconnected. Note that the supported modes for use of the DDR EMIF are
32 bits wide, 16 bits wide, or not used.
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32-bit DDR3 EMIF
16-Bit DDR3
Devices
DDR[0]_D[31]
DQ15
8
DDR[0]_D[24]
DQ8
DDR[0]_DQM[3]
DDR[0]_DQS[3]
DDR[0]_DQS[3]
UDM
UDQS
UDQS
DDR[0]_D[23]
DQ7
8
DDR[0]_D[16]
D08
DDR[0]_DQM[2]
DDR[0]_DQS[2]
DDR[0]_DQS[2]
LDM
LDQS
LDQS
DDR[0]_D[15]
DQ15
8
DDR[0]_D[8]
DQ8
DDR[0]_DQM[1]
DDR[0]_DQS[1]
DDR[0]_DQS[1]
UDM
UDQS
UDQS
DDR[0]_D[7]
DQ7
8
DDR[0]_D[0]
DQ0
DDR[0]_DQM[0]
DDR[0]_DQS[0]
DDR[0]_DQS[0]
LDM
LDQS
LDQS
DDR[0]_CLK
DDR[0]_CLK
DDR[0]_ODT[0]
DDR[0]_CS[0]
DDR[0]_BA[0]
DDR[0]_BA[1]
DDR[0]_BA[2]
DDR[0]_A[0]
Zo
CK
CK
CK
CK
ODT
CS
BA0
BA1
BA2
ODT
CS
BA0
BA1
BA2
A0
A0
Zo
A15
A15
Zo
CAS
RAS
WE
CKE
RST
ZQ
VREFDQ
VREFCA
CAS
RAS
WE
CKE
RST
0.1 µF
DVDD_DDR[0]
Zo
DDR_VTT
16
DDR[0]_A[15]
DDR[0]_CAS
DDR[0]_RAS
DDR[0]_WE
DDR[0]_CKE
DDR[0]_RST
ZQ
VREFSSTL_DDR[0]
0.1 µF
0.1 µF
DDR_VREF
ZQ
VREFDQ
VREFCA
ZQ
0.1 µF
DDR[0]_VTP
50 Ω (±2%)
Zo
ZQ
Termination is required. See terminator comments.
Value determined according to the DDR memory device data sheet.
Figure 8-57. 32-Bit, One-Bank DDR3 Interface Schematic Using Two 16-Bit DDR3 Devices
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8-Bit DDR3
Devices
8-Bit DDR3
Devices
DDR[0]_D[31]
DQ7
8
DDR[0]_D[24]
DQ0
DDR[0]_DQM[3]
NC
DDR[0]_DQS[3]
DDR[0]_DQS[3]
DDR[0]_D[23]
DM/TQS
TDQS
DQS
DQS
DQ7
8
DDR[0]_D[16]
DQ0
DDR[0]_DQM[2]
NC
DDR[0]_DQS[2]
DDR[0]_DQS[2]
DDR[0]_D[15]
DM/TQS
TDQS
DQS
DQS
DQ7
8
DDR[0]_D[8]
DQ0
DDR[0]_DQM[1]
NC
DDR[0]_DQS[1]
DDR[0]_DQS[1]
DDR[0]_D[7]
DM/TQS
TDQS
DQS
DQS
DQ7
8
DDR[0]_D[0]
DQ0
DDR[0]_DQM[0]
NC
DDR[0]_DQS[0]
DDR[0]_DQS[0]
DDR[0]_CLK
DDR[0]_CLK
DM/TQS
TDQS
DQS
DQS
Zo
CK
CK
DDR[0]_ODT[0]
DDR[0]_CS[0]
DDR[0]_BA[0]
DDR[0]_BA[1]
DDR[0]_BA[2]
DDR[0]_A[0]
CK
CK
CK
CK
0.1 µF
CK
CK
DVDD_DDR[0]
Zo
ODT
CS
BA0
BA1
BA2
ODT
CS
BA0
BA1
BA2
ODT
CS
BA0
BA1
BA2
ODT
CS
BA0
BA1
BA2
A0
A0
A0
A0
Zo
A15
A15
A15
A15
Zo
CAS
RAS
WE
CKE
RST
ZQ
VREFDQ
VREFCA
CAS
RAS
WE
CKE
RST
CAS
RAS
WE
CKE
RST
ZQ
VREFDQ
VREFCA
CAS
RAS
WE
CKE
RST
DDR_VTT
16
DDR[0]_A[15]
DDR[0]_CAS
DDR[0]_RAS
DDR[0]_WE
DDR[0]_CKE
DDR[0]_RST
ZQ
VREFSSTL_DDR[0]
0.1 µF
ZQ
VREFDQ
VREFCA
0.1 µF
0.1 µF
ZQ
ZQ
0.1 µF
ZQ
VREFDQ
VREFCA
DDR_VREF
ZQ
0.1 µF
DDR[0]_VTP
50 Ω (±2%)
Zo
ZQ
Termination is required. See terminator comments.
Value determined according to the DDR memory device data sheet.
Figure 8-58. 32-Bit, One-Bank DDR3 Interface Schematic Using Four 8-Bit DDR3 Devices
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8.14.3.4 Compatible DDR3 Devices
Table 8-63 shows the parameters of the DDR3 devices that are compatible with this interface. Generally,
the interface is compatible with DDR3 devices in the x8 or x16 widths.
Table 8-63. Compatible DDR3 Devices (Per Interface)
NO.
MIN
MAX
1
DDR3 device speed grade: ≤ 400 MHz clock rate (1)
DDR3-800
(2)
2
DDR3 device speed grade: > 400 MHz clock rate (1)
DDR3-1600
(2)
3
DDR3 device bit width
x8
x16
2
4
4
(1)
(2)
(3)
PARAMETER
DDR3 device count
(3)
UNIT
Bits
Devices
DDR3 speed grade depends on desired clock rate. Data rate is 2x the clock rate. For DDR3-800, the clock rate is 400 MHz.
DDR3 devices with higher speed grades are supported; however, max clock rate will still be limited to 533 MHz as stated in Table 8-61
Switching Characteristics Over Recommended Operating Conditions for DDR3 Memory Controller.
For valid DDR3 device configurations and device counts, see Section 8.14.3.3, Figure 8-57, and Figure 8-58.
8.14.3.5 PCB Stackup
The minimum stackup for routing the DDR3 interface is a four-layer stack up as shown in Table 8-64.
Additional layers may be added to the PCB stackup to accommodate other circuitry, enhance SI/EMI
performance, or to reduce the size of the PCB footprint. A six-layer stackup is shown in Table 8-65.
Complete stackup specifications are provided in Table 8-66.
Table 8-64. Minimum PCB Stackup
LAYER
TYPE
DESCRIPTION
1
Signal
Top routing mostly vertical
2
Plane
Split power plane
3
Plane
Full ground plane
4
Signal
Bottom routing mostly horizontal
Table 8-65. Six-Layer PCB Stackup Suggestion
LAYER
TYPE
DESCRIPTION
1
Signal
Top routing mostly vertical
2
Plane
Ground
3
Plane
Split power plane
4
Plane
Split power plane or Internal routing
5
Plane
Ground
6
Signal
Bottom routing mostly horizontal
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Table 8-66. PCB Stackup Specifications
NO.
MIN
TYP
1
PCB routing/plane layers
PARAMETER
4
6
2
Signal routing layers
2
3
Full ground reference layers under DDR3 routing region (1)
MAX
1
(1)
4
Full 1.35-V/1.5-V power reference layers under the DDR3 routing region
5
Number of reference plane cuts allowed within DDR routing region (2)
0
6
Number of layers between DDR3 routing layer and reference plane (3)
0
7
PCB feature spacing
4
8
PCB trace width, w
4
9
PCB BGA escape via pad size (4)
10
PCB BGA escape via hole size
10
11
Processor BGA pad size
0.4
13
Single-ended impedance, Zo
14
Impedance control (5)
(1)
(2)
(3)
(4)
(5)
UNIT
1
18
50
Z-5
Z
Mils
Mils
20
Mils
Mils
mm
75
Ω
Z+5
Ω
Ground reference layers are preferred over power reference layers. Be sure to include bypass caps to accommodate reference layer
return current as the trace routes switch routing layers.
No traces should cross reference plane cuts within the DDR routing region. High-speed signal traces crossing reference plane cuts
create large return current paths which can lead to excessive crosstalk and EMI radiation.
Reference planes are to be directly adjacent to the signal plane to minimize the size of the return current loop.
An 18-mil pad assumes Via Channel is the most economical BGA escape. A 20-mil pad may be used if additional layers are available
for power routing. An 18-mil pad is required for minimum layer count escape.
Z is the nominal singled-ended impedance selected for the PCB specified by item 13.
8.14.3.6 Placement
Figure 8-59 shows the required placement for the processor as well as the DDR3 devices. The
dimensions for this figure are defined in Table 8-67. The placement does not restrict the side of the PCB
on which the devices are mounted. The ultimate purpose of the placement is to limit the maximum trace
lengths and allow for proper routing space. For a 16-bit DDR memory system, the high-word DDR3
devices are omitted from the placement.
X1
X2
X2
X2
DDR3
Controller
Y
Figure 8-59. Placement Specifications
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Table 8-67. Placement Specifications
NO.
(1)
(2)
(3)
(4)
(5)
PARAMETER
MIN
1
X1 (1) (2) (3)
2
X2 (1) (2)
3
Y Offset (1) (2) (3)
4
DDR3 keepout region
5
Clearance from non-DDR3 signal to DDR3 keepout region (4) (5)
MAX
UNIT
1000
Mils
600
Mils
1500
Mils
4
w
For dimension definitions, see Figure 8-59.
Measurements from center of processor to center of DDR3 device.
Minimizing X1 and Y improves timing margins.
w is defined as the signal trace width.
Non-DDR3 signals allowed within DDR3 keepout region provided they are separated from DDR3 routing layers by a ground plane.
8.14.3.7 DDR3 Keepout Region
The region of the PCB used for DDR3 circuitry must be isolated from other signals. The DDR3 keepout
region is defined for this purpose and is shown in Figure 8-60. The size of this region varies with the
placement and DDR routing. Additional clearances required for the keepout region are shown in Table 867. Non-DDR3 signals should not be routed on the DDR signal layers within the DDR3 keepout region.
Non-DDR3 signals may be routed in the region, provided they are routed on layers separated from the
DDR signal layers by a ground layer. No breaks should be allowed in the reference ground layers in this
region. In addition, the 1.35-V/1.5-V DDR3L/DDR3 power plane should cover the entire keepout region.
Also note that the DDR3 controller's signals should be separated from each other by the specification in
item 5 (see Table 8-67 for item 5 specification).
DDR3 Controller
DDR[0] Keep Out Region
Encompasses Entire DDR[0] Routing Area
Figure 8-60. DDR3 Keepout Region
8.14.3.8 Bulk Bypass Capacitors
Bulk bypass capacitors are required for moderate speed bypassing of the DDR3 and other circuitry.
Table 8-68 contains the minimum numbers and capacitance required for the bulk bypass capacitors. Note
that this table only covers the bypass needs of the DDR3 controller and DDR3 devices. Additional bulk
bypass capacitance may be needed for other circuitry.
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Table 8-68. Bulk Bypass Capacitors
NO.
PARAMETER
MIN
1
DVDD_DDR[0] bulk bypass capacitor count (1)
6
2
DVDD_DDR[0] bulk bypass total capacitance
140
(1)
MAX
UNIT
Devices
μF
These devices should be placed near the devices they are bypassing, but preference should be given to the placement of the highspeed (HS) bypass capacitors and DDR3 signal routing.
8.14.3.9 High-Speed Bypass Capacitors
High-speed (HS) bypass capacitors are critical for proper DDR3 interface operation. It is particularly
important to minimize the parasitic series inductance of the HS bypass capacitors, processor/DDR power,
and processor/DDR ground connections. Table 8-69 contains the specification for the HS bypass
capacitors as well as for the power connections on the PCB. Generally speaking, it is good to:
1. Fit as many HS bypass capacitors as possible. Due to the number of required bypass capacitors, it is
recommended that the bypass capacitors are placed before routing the board.
2. Minimize the distance from the bypass cap to the pins/balls being bypassed.
3. Use the smallest physical sized capacitors possible with the highest capacitance readily available.
4. Connect the bypass capacitor pads to their vias using the widest traces possible and using the largest
hole size via possible.
5. Minimize via sharing. Note the limits on via sharing shown in Table 8-69.
Table 8-69. High-Speed Bypass Capacitors
NO.
PARAMETER
MIN
1
HS bypass capacitor package size (1)
2
Distance, HS bypass capacitor to processor being bypassed (2) (3) (4)
3
Processor DVDD_DDR[0] HS bypass capacitor count
35
4
Processor DVDD_DDR[0] HS bypass capacitor total capacitance
2.5
5
Number of connection vias for each device power/ground ball (5)
6
Trace length from device power/ground ball to connection via (2)
7
Distance, HS bypass capacitor to DDR device being bypassed (6)
8
DDR3 device HS bypass capacitor count (7)
9
DDR3 device HS bypass capacitor total capacitance (7)
TYP
MAX
UNIT
201
402
10 Mils
400
Mils
Devices
μF
Vias
35
70
150
12
(8) (9)
10
Number of connection vias for each HS capacitor
11
Trace length from bypass capacitor connect to connection via (2) (9)
12
Number of connection vias for each DDR3 device power/ground ball (10)
13
Trace length from DDR3 device power/ground ball to connection via (2) (8)
Mils
Mils
Devices
μF
0.85
2
Vias
35
100
1
Mils
Vias
35
60
Mils
(1)
(2)
(3)
(4)
LxW, 10-mil units, that is, a 0402 is a 40x20-mil surface-mount capacitor.
Closer/shorter is better.
Measured from the nearest processor power/ground ball to the center of the capacitor package.
Three of these capacitors should be located underneath the processor, between the cluster of DVDD_DDR[0] balls and ground balls,
between the DDR interfaces on the package.
(5) See the Via Channel™ escape for the processor package.
(6) Measured from the DDR3 device power/ground ball to the center of the capacitor package.
(7) Per DDR3 device.
(8) An additional HS bypass capacitor can share the connection vias only if it is mounted on the opposite side of the board. No sharing of
vias is permitted on the same side of the board.
(9) An HS bypass capacitor may share a via with a DDR device mounted on the same side of the PCB. A wide trace should be used for the
connection and the length from the capacitor pad to the DDR device pad should be less than 150 mils.
(10) Up to a total of two pairs of DDR power/ground balls may share a via.
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8.14.3.9.1 Return Current Bypass Capacitors
Use additional bypass capacitors if the return current reference plane changes due to DDR3 signals
hopping from one signal layer to another. The bypass capacitor here provides a path for the return current
to hop planes along with the signal. As many of these return current bypass capacitors should be used as
possible. Since these are returns for signal current, the signal via size may be used for these capacitors.
8.14.3.10 Net Classes
Table 8-70 lists the clock net classes for the DDR3 interface. Table 8-71 lists the signal net classes, and
associated clock net classes, for signals in the DDR3 interface. These net classes are used for the
termination and routing rules that follow.
Table 8-70. Clock Net Class Definitions
CLOCK NET CLASS
PROCESSOR PIN NAMES
CK
DDR[0]_CLK/DDR[0]_CLK
DQS0
DDR[0]_DQS[0]/DDR[0]_DQS[0]
DQS1
DDR[0]_DQS[1]/DDR[0]_DQS[1]
(1)
DDR[0]_DQS[2]/DDR[0]_DQS[2]
DQS3 (1)
DDR[0]_DQS[3]/DDR[0]_DQS[3]
DQS2
(1)
Only used on 32-bit wide DDR3 memory systems.
Table 8-71. Signal Net Class Definitions
CLOCK NET CLASS
ASSOCIATED CLOCK
NET CLASS
ADDR_CTRL
CK
DQ0
DQS0
DDR[0]_D[7:0], DDR[0]_DQM[0]
DQ1
DQS1
DDR[0]_D[15:8], DDR[0]_DQM[1]
DQ2 (1)
DQS2
DDR[0]_D[23:16], DDR[0]_DQM[2]
(1)
DQS3
DDR[0]_D[31:24], DDR[0]_DQM[3]
DQ3
(1)
PROCESSOR PIN NAMES
DDR[0]_BA[2:0], DDR[0]_A[15:0], DDR[0]_CS[x], DDR[0]_CAS,
DDR[0]_RAS, DDR[0]_WE, DDR[0]_CKE, DDR[0]_ODT[0]
Only used on 32-bit wide DDR3 memory systems.
8.14.3.11 DDR3 Signal Termination
Signal terminators are required for the CK and ADDR_CTRL net classes. The data lines are terminated by
ODT and, thus, the PCB traces should be unterminated. Detailed termination specifications are covered in
the routing rules in the following sections.
8.14.3.12 VREFSSTL_DDR Routing
VREFSSTL_DDR (VREF) is used as a reference by the input buffers of the DDR3 memories as well as
the processor. VREF is intended to be half the DDR3 power supply voltage and is typically generated with
the DDR3 1.35-V/1.5-V and VTT power supply. It should be routed as a nominal 20-mil wide trace with 0.1
µF bypass capacitors near each device connection. Narrowing of VREF is allowed to accommodate
routing congestion.
8.14.3.13 VTT
Like VREF, the nominal value of the VTT supply is half the DDR3 supply voltage. Unlike VREF, VTT is
expected to source and sink current, specifically the termination current for the ADDR_CTRL net class
Thevinen terminators. VTT is needed at the end of the address bus and it should be routed as a power
sub-plane. VTT should be bypassed near the terminator resistors.
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8.14.3.14 CK and ADDR_CTRL Topologies and Routing Definition
The CK and ADDR_CTRL net classes are routed similarly and are length matched to minimize skew
between them. CK is a bit more complicated because it runs at a higher transition rate and is differential.
The following subsections show the topology and routing for various DDR3 configurations for CK and
ADDR_CTRL. The figures in the following subsections define the terms for the routing specification
detailed in Table 8-72.
8.14.3.14.1 Four DDR3 Devices
Four DDR3 devices are supported on the DDR EMIF consisting of four x8 DDR3 devices arranged as one
bank (CS). These four devices may be mounted on a single side of the PCB, or may be mirrored in two
pairs to save board space at a cost of increased routing complexity and parts on the backside of the PCB.
8.14.3.14.1.1 CK and ADDR_CTRL Topologies, Four DDR3 Devices
Figure 8-61 shows the topology of the CK net classes and Figure 8-62 shows the topology for the
corresponding ADDR_CTRL net classes.
+ –
+ –
+ –
+ –
AS+
AS-
AS+
AS-
AS+
AS-
AS+
AS-
DDR Differential CK Input Buffers
Clock Parallel
Terminator
Rcp
A1
Processor
Differential Clock
Output Buffer
A2
A3
A3
A4
DVDD_DDR[0]
AT
Cac
+
–
Rcp
A1
A2
A3
A3
A4
0.1 µF
AT
Routed as Differential Pair
Figure 8-61. CK Topology for Four x8 DDR3 Devices
Processor
Address and Control
Output Buffer
A1
A2
A3
A4
AS
AS
AS
AS
DDR Address and Control Input Buffers
A3
Address and Control
Terminator
Rtt
Vtt
AT
Figure 8-62. ADDR_CTRL Topology for Four x8 DDR3 Devices
8.14.3.14.1.2 CK and ADDR_CTRL Routing, Four DDR3 Devices
Figure 8-63 shows the CK routing for four DDR3 devices placed on the same side of the PCB. Figure 8-64
shows the corresponding ADDR_CTRL routing.
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A1
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DVDD_DDR[0]
A3
A3
=
A3
A3
A4
A4
Rcp
Cac
Rcp
0.1 µF
AT
AT
AS+
AS-
A2
A2
A1
Figure 8-63. CK Routing for Four Single-Side DDR3 Devices
Rtt
A3
=
A4
A3
AT
Vtt
AS
A2
Figure 8-64. ADDR_CTRL Routing for Four Single-Side DDR3 Devices
To save PCB space, the four DDR3 memories may be mounted as two mirrored pairs at a cost of
increased routing and assembly complexity. Figure 8-65 and Figure 8-66 show the routing for CK and
ADDR_CTRL, respectively, for four DDR3 devices mirrored in a two-pair configuration.
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DVDD_DDR[0]
A3
A3
=
A3
A3
A4
A4
Rcp
Cac
Rcp
0.1 µF
AT
AT
AS+
AS-
A2
A2
A1
Figure 8-65. CK Routing for Four Mirrored DDR3 Devices
Rtt
=
A4
A3
AT
Vtt
AS
A3
A2
Figure 8-66. ADDR_CTRL Routing for Four Mirrored DDR3 Devices
8.14.3.14.2 Two DDR3 Devices
Two DDR3 devices are supported on the DDR EMIF consisting of two x8 DDR3 devices arranged as one
bank (CS), 16 bits wide, or two x16 DDR3 devices arranged as one bank (CS), 32 bits wide. These two
devices may be mounted on a single side of the PCB, or may be mirrored in a pair to save board space at
a cost of increased routing complexity and parts on the backside of the PCB.
8.14.3.14.2.1 CK and ADDR_CTRL Topologies, Two DDR3 Devices
Figure 8-67 shows the topology of the CK net classes and Figure 8-68 shows the topology for the
corresponding ADDR_CTRL net classes.
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+ –
+ –
AS+
AS-
AS+
AS-
DDR Differential CK Input Buffers
Clock Parallel
Terminator
Rcp
A1
Processor
Differential Clock
Output Buffer
A2
A3
DVDD_DDR[0]
AT
Cac
+
–
Rcp
A1
A2
A3
0.1 µF
AT
Routed as Differential Pair
Figure 8-67. CK Topology for Two DDR3 Devices
Processor
Address and Control
Output Buffer
A1
A2
AS
AS
DDR Address and Control Input Buffers
A3
Address and Control
Terminator
Rtt
Vtt
AT
Figure 8-68. ADDR_CTRL Topology for Two DDR3 Devices
8.14.3.14.2.2 CK and ADDR_CTRL Routing, Two DDR3 Devices
Figure 8-69 shows the CK routing for two DDR3 devices placed on the same side of the PCB. Figure 8-70
shows the corresponding ADDR_CTRL routing.
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DVDD_DDR[0]
A3
A3
=
Rcp
Cac
Rcp
0.1 µF
AT
AT
AS+
AS-
A2
A2
A1
Figure 8-69. CK Routing for Two Single-Side DDR3 Devices
Rtt
A3
=
AT
Vtt
AS
A2
Figure 8-70. ADDR_CTRL Routing for Two Single-Side DDR3 Devices
To save PCB space, the two DDR3 memories may be mounted as a mirrored pair at a cost of increased
routing and assembly complexity. Figure 8-71 and Figure 8-72 show the routing for CK and ADDR_CTRL,
respectively, for two DDR3 devices mirrored in a single-pair configuration.
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A1
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DVDD_DDR[0]
A3
A3
=
Rcp
Cac
Rcp
0.1 µF
AT
AT
AS+
AS-
A2
A2
A1
Figure 8-71. CK Routing for Two Mirrored DDR3 Devices
Rtt
=
AT
Vtt
AS
A3
A2
Figure 8-72. ADDR_CTRL Routing for Two Mirrored DDR3 Devices
8.14.3.14.3 One DDR3 Device
A single DDR3 device is supported on the DDR EMIF consisting of one x16 DDR3 device arranged as
one bank (CS), 16 bits wide.
8.14.3.14.3.1 CK and ADDR_CTRL Topologies, One DDR3 Device
Figure 8-73 shows the topology of the CK net classes and Figure 8-74 shows the topology for the
corresponding ADDR_CTRL net classes.
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DDR Differential CK Input Buffer
AS+
AS-
+ –
Clock Parallel
Terminator
DVDD_DDR[0]
Rcp
A1
Processor
Differential Clock
Output Buffer
AT
A2
Cac
+
–
Rcp
A1
0.1 µF
AT
A2
Routed as Differential Pair
Figure 8-73. CK Topology for One DDR3 Device
AS
DDR Address and Control Input Buffers
Processor
Address and Control
Output Buffer
A1
A2
Address and Control
Terminator
Rtt
AT
Vtt
Figure 8-74. ADDR_CTRL Topology for One DDR3 Device
8.14.3.14.3.2 CK and ADDR/CTRL Routing, One DDR3 Device
Figure 8-75 shows the CK routing for one DDR3 device placed on the same side of the PCB. Figure 8-76
shows the corresponding ADDR_CTRL routing.
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A1
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DVDD_DDR[0]
Rcp
Cac
Rcp
0.1 µF
AT
AT
=
AS+
AS-
A2
A2
A1
Figure 8-75. CK Routing for One DDR3 Device
Rtt
AT
=
Vtt
AS
A2
Figure 8-76. ADDR_CTRL Routing for One DDR3 Device
8.14.3.15 Data Topologies and Routing Definition
No matter the number of DDR3 devices used, the data line topology is always point to point, so its
definition is simple.
8.14.3.15.1 DQS and DQ/DM Topologies, Any Number of Allowed DDR3 Devices
DQS lines are point-to-point differential, and DQ/DM lines are point-to-point singled ended. Figure 8-77
and Figure 8-78 show these topologies.
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Processor
DQS
IO Buffer
DDR
DQS
IO Buffer
DQSn+
DQSnRouted Differentially
n = 0, 1, 2, 3
Figure 8-77. DQS Topology
Processor
DQ and DM
IO Buffer
DDR
DQ and DM
IO Buffer
Dn
n = 0, 1, 2, 3
Figure 8-78. DQ/DM Topology
8.14.3.15.2 DQS and DQ/DM Routing, Any Number of Allowed DDR3 Devices
Figure 8-79 and Figure 8-80 show the DQS and DQ/DM routing.
DQS
DQSn+
DQSn-
Routed Differentially
n = 0, 1, 2, 3
Figure 8-79. DQS Routing With Any Number of Allowed DDR3 Devices
Dn
DQ and DM
n = 0, 1, 2, 3
Figure 8-80. DQ/DM Routing With Any Number of Allowed DDR3 Devices
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8.14.3.16 Routing Specification
8.14.3.16.1 CK and ADDR_CTRL Routing Specification
Skew within the CK and ADDR_CTRL net classes directly reduces setup and hold margin and, thus, this
skew must be controlled. The only way to practically match lengths on a PCB is to lengthen the shorter
traces up to the length of the longest net in the net class and its associated clock. A metric to establish
this maximum length is Manhattan distance. The Manhattan distance between two points on a PCB is the
length between the points when connecting them only with horizontal or vertical segments. A reasonable
trace route length is to within a percentage of its Manhattan distance. CACLM is defined as Clock Address
Control Longest Manhattan distance.
Given the clock and address pin locations on the processor and the DDR3 memories, the maximum
possible Manhattan distance can be determined given the placement. Figure 8-81 and Figure 8-82 show
this distance for four loads and two loads, respectively. It is from this distance that the specifications on
the lengths of the transmission lines for the address bus are determined. CACLM is determined similarly
for other address bus configurations; that is, it is based on the longest net of the CK/ADDR_CTRL net
class. For CK and ADDR_CTRL routing, these specifications are contained in Table 8-72.
(A)
A1
A8
CACLMY
CACLMX
A8
(A)
A8
(A)
A8
(A)
A8
(A)
Rtt
A3
=
A.
A4
A3
AT
Vtt
AS
A2
It is very likely that the longest CK/ADDR_CTRL Manhattan distance will be for Address Input 8 (A8) on the DDR3
memories. CACLM is based on the longest Manhattan distance due to the device placement. Verify the net class that
satisfies this criteria and use as the baseline for CK/ADDR_CTRL skew matching and length control.
The length of shorter CK/ADDR_CTRL stubs as well as the length of the terminator stub are not included in this
length calculation. Non-included lengths are grayed out in the figure.
Assuming A8 is the longest, CALM = CACLMY + CACLMX + 300 mils.
The extra 300 mils allows for routing down lower than the DDR3 memories and returning up to reach A8.
Figure 8-81. CACLM for Four Address Loads on One Side of PCB
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(A)
A1
A8
CACLMY
CACLMX
A8
(A)
A8
(A)
Rtt
A3
=
A.
AT
Vtt
AS
A2
It is very likely that the longest CK/ADDR_CTRL Manhattan distance will be for Address Input 8 (A8) on the DDR3
memories. CACLM is based on the longest Manhattan distance due to the device placement. Verify the net class that
satisfies this criteria and use as the baseline for CK/ADDR_CTRL skew matching and length control.
The length of shorter CK/ADDR_CTRL stubs as well as the length of the terminator stub are not included in this
length calculation. Non-included lengths are grayed out in the figure.
Assuming A8 is the longest, CALM = CACLMY + CACLMX + 300 mils.
The extra 300 mils allows for routing down lower than the DDR3 memories and returning up to reach A8.
Figure 8-82. CACLM for Two Address Loads on One Side of PCB
Table 8-72. CK and ADDR_CTRL Routing Specification (1) (2)
NO.
PARAMETER
MIN
TYP
MAX
UNIT
2500
mils
25
mils
660
mils
1
A1+A2 length
2
A1+A2 skew
3
A3 length
4
A3 skew (3)
25
mils
5
A3 skew
(4)
125
mils
6
A4 length
660
mils
7
A4 skew
25
mils
8
AS length
100
mils
9
AS skew
100
mils
10
AS+/AS- length
70
mils
11
AS+/AS- skew
5
mils
(5)
12
AT length
13
AT skew (6)
14
AT skew (7)
15
(1)
(2)
(3)
(4)
(5)
(6)
(7)
(8)
252
CK/ADDR_CTRL nominal trace length
500
mils
100
(8)
CACLM-50
CACLM
mils
5
mils
CACLM+50
mils
The use of vias should be minimized.
Additional bypass capacitors are required when using the DVDD_DDR[0] plane as the reference plane to allow the return current to
jump between the DVDD_DDR[0] plane and the ground plane when the net class switches layers at a via.
Non-mirrored configuration (all DDR3 memories on same side of PCB).
Mirrored configuration (one DDR3 device on top of the board and one DDR3 device on the bottom).
While this length can be increased for convenience, its length should be minimized.
ADDR_CTRL net class only (not CK net class). Minimizing this skew is recommended, but not required.
CK net class only.
CACLM is the longest Manhattan distance of the CK and ADDR_CTRL net classes + 300 mils. For definition, see Section 8.14.3.16.1,
Figure 8-81, and Figure 8-82.
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Table 8-72. CK and ADDR_CTRL Routing Specification(1)(2) (continued)
NO.
PARAMETER
MIN
16
Center-to-center CK to other DDR3 trace spacing (9)
4w
17
Center-to-center ADDR_CTRL to other DDR3 trace spacing (9) (10)
4w
18
Center-to-center ADDR_CTRL to other ADDR_CTRL trace spacing (9)
3w
19
CK center-to-center spacing (11)
20
CK spacing to other net (9)
21
Rcp (12)
Zo-1
22
Rtt (12) (13)
Zo-5
(9)
(10)
(11)
(12)
(13)
TYP
MAX
UNIT
Zo
Zo+
Ω
Zo
Zo+5
Ω
4w
Center-to-center spacing is allowed to fall to minimum (2w) for up to 1250 mils of routed length.
The ADDR_CTRL net class of the other DDR EMIF is considered other DDR3 trace spacing.
CK spacing set to ensure proper differential impedance.
Source termination (series resistor at driver) is specifically not allowed.
Termination values should be uniform across the net class.
8.14.3.16.2 DQS and DQ Routing Specification
Skew within the DQS and DQ/DM net classes directly reduces setup and hold margin and thus this skew
must be controlled. The only way to practically match lengths on a PCB is to lengthen the shorter traces
up to the length of the longest net in the net class and its associated clock. As with CK and ADDR_CTRL,
a reasonable trace route length is to within a percentage of its Manhattan distance. DQLMn is defined as
DQ Longest Manhattan distance n, where n is the byte number. For a 32-bit interface, there are four
DQLMs, DQLM0-DQLM3. Likewise, for a 16-bit interface, there are two DQLMs, DQLM0-DQLM1.
NOTE
It is not required, nor is it recommended, to match the lengths across all bytes. Length
matching is only required within each byte.
Given the DQS and DQ/DM pin locations on the processor and the DDR3 memories, the maximum
possible Manhattan distance can be determined given the placement. Figure 8-83 shows this distance for
four loads. It is from this distance that the specifications on the lengths of the transmission lines for the
data bus are determined. For DQS and DQ/DM routing, these specifications are contained in Table 8-73.
DQLMX0
DB0
DB1
DQ[0:7]/DM0/DQS0
DQ[8:15]/DM1/DQS1
DQLMX1
DQ[16:23]/DM2/DQS2
DB2
DQLMY0
DQLMX2
DQLMY3
DQLMY2
DB3
DQLMY1
DQ[23:31]/DM3/DQS3
DQLMX3
3
2
1
0
DB0 - DB3 represent data bytes 0 - 3.
There are four DQLMs, one for each byte (32-bit interface). Each DQLM is the longest Manhattan distance of the
byte; therefore:
DQLM0 = DQLMX0 + DQLMY0
DQLM1 = DQLMX1 + DQLMY1
DQLM2 = DQLMX2 + DQLMY2
DQLM3 = DQLMX3 + DQLMY3
Figure 8-83. DQLM for Any Number of Allowed DDR3 Devices
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Table 8-73. Data Routing Specification (1)
NO.
MAX
UNIT
1
DB0 nominal length (2) (3)
PARAMETER
MIN
DQLM0
mils
2
DB1 nominal length (2) (4)
DQLM1
mils
3
DB2 nominal length (2) (5)
DQLM2
mils
4
DB3 nominal length
(2) (6)
DQLM3
mils
5
DBn skew (7)
25
mils
6
DQSn+ to DQSn- skew
5
mils
25
mils
(7) (8)
7
DQSn to DBn skew
8
Center-to-center DBn to other DDR3 trace spacing (9) (10)
4w
9
Center-to-center DBn to other DBn trace spacing (9) (11)
3w
(12)
10
DQSn center-to-center spacing
11
DQSn center-to-center spacing to other net(9)
(1)
(2)
(3)
(4)
(5)
(6)
(7)
(8)
(9)
(10)
(11)
(12)
254
TYP
4w
External termination disallowed. Data termination should use built-in ODT functionality.
DQLMn is the longest Manhattan distance of a byte. r definition, see Section 8.14.3.16.2 and Figure 8-83.
DQLM0 is the longest Manhattan length for the net classes of Byte 0.
DQLM1 is the longest Manhattan length for the net classes of Byte 1.
DQLM2 is the longest Manhattan length for the net classes of Byte 2.
DQLM3 is the longest Manhattan length for the net classes of Byte 3.
Length matching is only done within a byte. Length matching across bytes is neither required nor recommended.
Each DQS pair is length matched to its associated byte.
Center-to-center spacing is allowed to fall to minimum (2w) for up to 1250 mils of routed length.
Other DDR3 trace spacing means other DDR3 net classes not within the byte.
This applies to spacing within the net classes of a byte.
DQS pair spacing is set to ensure proper differential impedance.
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8.15 Multichannel Audio Serial Port (McASP)
The multichannel audio serial port (McASP) functions as a general-purpose audio serial port optimized for
the needs of multichannel audio applications. The McASP is useful for time-division multiplexed (TDM)
stream, Inter-Integrated Sound (I2S) protocols, and inter-component digital audio interface transmission
(DIT).
8.15.1 McASP Device-Specific Information
The device includes two multichannel audio serial port (McASP) interface peripherals (McASP0 and
McASP1). The McASP module consists of a transmit and receive section. These sections can operate
completely independently with different data formats, separate master clocks, bit clocks, and frame syncs
or, alternatively, the transmit and receive sections may be synchronized. The McASP module also
includes shift registers that may be configured to operate as either transmit data or receive data.
The transmit section of the McASP can transmit data in either a time-division-multiplexed (TDM)
synchronous serial format or in a digital audio interface (DIT) format where the bit stream is encoded for
S/PDIF, AES-3, IEC-60958, CP-430 transmission. The receive section of the McASP peripheral supports
the TDM synchronous serial format.
The McASP module can support one transmit data format (either a TDM format or DIT format) and one
receive format at a time. All transmit shift registers use the same format and all receive shift registers use
the same format; however, the transmit and receive formats need not be the same. Both the transmit and
receive sections of the McASP also support burst mode, which is useful for non-audio data (for example,
passing control information between two devices).
The McASP peripheral has additional capability for flexible clock generation and error detection/handling,
as well as error management.
The device McASP0 module has up to 6 serial data pins, while McASP1 has 2 serial data pins. The
McASP FIFO size is 256 bytes and two DMA and two interrupt requests are supported. Buffers are used
transparently to better manage DMA, which can be leveraged to manage data flow more efficiently.
For more detailed information on and the functionality of the McASP peripheral, see the Multichannel
Audio Serial Port (McASP) chapter in the device-specific Technical Reference Manual.
8.15.2 McASP0 and McASP1 Peripheral Registers Descriptions
The McASP0 and McASP1 peripheral registers are described in the device-specific Technical Reference
Manual. Each register is documented as an offset from a base address for the peripheral. The base
addresses for all of the peripherals are in the device memory map (see Section 2.10).
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8.15.3 McASP (McASP[1:0]) Electrical Data/Timing
Table 8-74. Timing Requirements for McASP (1)
(see Figure 8-84)
OPP100/OPP120/
Turbo
NO.
MIN
1
tc(AHCLKRX)
Cycle time, MCA[x]_AHCLKR/X
2
tw(AHCLKRX)
Pulse duration, MCA[x]_AHCLKR/X high or low
3
tc(ACLKRX)
Cycle time, MCA[x]_ACLKR/X
4
tw(ACLKRX)
Pulse duration, MCA[x]_ACLKR/X high or low
5
tsu(AFSRX-ACLKRX)
Setup time, MCA[x]_AFSR/X input valid before
MCA[X]_ACLKR/X
ACLKR/X int
ACLKR/X int
th(ACLKRX-AFSRX)
Hold time, MCA[x]_AFSR/X input valid after
MCA[X]_ACLKR/X
ACLKR/X ext in
ACLKR/X int
tsu(AXR-ACLKRX)
Setup time, MCA[x]_AXR input valid before
MCA[X]_ACLKR/X
ACLKR/X ext in
ACLKR/X int
(1)
(2)
(3)
256
th(ACLKRX-AXR)
Hold time, MCA[x]_AXR input valid after
MCA[X]_ACLKR/X
0.5P 2.5 (2)
ns
20
ns
0.5R 2.5 (3)
ns
4
ns
4
1
ns
1
10.5
ACLKR/X ext out
8
ns
-1
ACLKR/X ext out
7
20
10.5
ACLKR/X ext in
ACLKR/X ext out
6
UNIT
MAX
4
ns
4
-1
ACLKR/X ext in
1
ACLKR/X ext out
1
ns
ACLKR internal: ACLKRCTL.CLKRM=1, PDIR.ACLKR = 1
ACLKR external input: ACLKRCTL.CLKRM=0, PDIR.ACLKR=0
ACLKR external output: ACLKRCTL.CLKRM=0, PDIR.ACLKR=1
ACLKX internal: ACLKXCTL.CLKXM=1, PDIR.ACLKX = 1
ACLKX external input: ACLKXCTL.CLKXM=0, PDIR.ACLKX=0
ACLKX external output: ACLKXCTL.CLKXM=0, PDIR.ACLKX=1
P = MCA[x]_AHCLKR/X period in nano seconds (ns).
R = MCA[x]_ACLKR/X period in ns.
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2
1
2
MCA[x]_ACLKR/X (Falling Edge Polarity)
MCA[x]_AHCLKR/X (Rising Edge Polarity)
4
4
3
MCA[x]_ACLKR/X (CLKRP = CLKXP = 0)
MCA[x]_ACLKR/X (CLKRP = CLKXP = 1)
(A)
(B)
6
5
MCA[x]_AFSR/X (Bit Width, 0 Bit Delay)
MCA[x]_AFSR/X (Bit Width, 1 Bit Delay)
MCA[x]_AFSR/X (Bit Width, 2 Bit Delay)
MCA[x]_AFSR/X (Slot Width, 0 Bit Delay)
MCA[x]_AFSR/X (Slot Width, 1 Bit Delay)
MCA[x]_AFSR/X (Slot Width, 2 Bit Delay)
8
7
MCA[x]_AXR[x] (Data In/Receive)
A.
B.
For CLKRP = CLKXP =
receiver is configured for
For CLKRP = CLKXP =
receiver is configured for
A0 A1
A30 A31 B0 B1
B30 B31 C0 C1 C2 C3
0, the McASP transmitter is configured for rising edge (to shift data out) and the McASP
falling edge (to shift data in).
1, the McASP transmitter is configured for falling edge (to shift data out) and the McASP
rising edge (to shift data in).
C31
Figure 8-84. McASP Input Timing
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Table 8-75. Switching Characteristics Over Recommended Operating Conditions for McASP (1)
(see Figure 8-85)
NO.
OPP100/OPP120/
Turbo
PARAMETER
MIN
9
tc(AHCLKRX)
Cycle time, MCA[X]_AHCLKR/X
10
tw(AHCLKRX)
Pulse duration, MCA[X]_AHCLKR/X high or low
11
tc(ACLKRX)
Cycle time, MCA[X]_ACLKR/X
12
13
tw(ACLKRX)
td(ACLKRX-AFSRX)
Pulse duration, MCA[X]_ACLKR/X high or low
Delay time, MCA[X]_ACLKR/X transmit edge to
MCA[X]_AFSR/X output valid
Delay time, MCA[X]_ACLKR/X transmit edge to
MCA[X]_AFSR/X output valid with Pad Loopback
14
td(ACLKX-AXR)
Delay time, MCA[X]_ACLKX transmit edge to
MCA[X]_AXR output valid
Delay time, MCA[X]_ACLKX transmit edge to
MCA[X]_AXR output valid with Pad Loopback
Disable time, MCA[X]_ACLKX transmit edge to
MCA[X]_AXR output high impedance
15
(1)
(2)
(3)
258
tdis(ACLKX-AXR)
Disable time, MCA[X]_ACLKX transmit edge to
MCA[X]_AXR output high impedance with Pad
Loopback
ACLKR/X int
UNIT
MAX
20 (2)
ns
0.5P 2.5 (3)
ns
20
ns
0.5P 2.5 (3)
ns
-2
5
ACLKR/X ext in
1
11.5
ACLKR/X ext out
1
11.5
ACLKX int
-2
5
ACLKX ext in
1
11.5
ACLKX ext out
1
11.5
ACLKX int
ACLKX ext in
-2
5
1
11.5
ns
ns
ns
ACLKX ext out
1
11.5
ACLKR internal: ACLKRCTL.CLKRM=1, PDIR.ACLKR = 1
ACLKR external input: ACLKRCTL.CLKRM=0, PDIR.ACLKR=0
ACLKR external output: ACLKRCTL.CLKRM=0, PDIR.ACLKR=1
ACLKX internal: ACLKXCTL.CLKXM=1, PDIR.ACLKX = 1
ACLKX external input: ACLKXCTL.CLKXM=0, PDIR.ACLKX=0
ACLKX external output: ACLKXCTL.CLKXM=0, PDIR.ACLKX=1
50 MHz
P = AHCLKR/X period.
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10
10
9
MCA[x]_ACLKR/X (Falling Edge Polarity)
MCA[x]_AHCLKR/X (Rising Edge Polarity)
11
MCA[x]_ACLKR/X (CLKRP = CLKXP = 1)
MCA[x]_ACLKR/X (CLKRP = CLKXP = 0)
12
12
(A)
(B)
13
13
13
13
MCA[x]_AFSR/X (Bit Width, 0 Bit Delay)
MCA[x]_AFSR/X (Bit Width, 1 Bit Delay)
MCA[x]_AFSR/X (Bit Width, 2 Bit Delay)
MCA[x]_AFSR/X (Slot Width, 0 Bit Delay)
13
13
13
MCA[x]_AFSR/X (Slot Width, 1 Bit Delay)
MCA[x]_AFSR/X (Slot Width, 2 Bit Delay)
MCA[x]_AXR[x] (Data Out/Transmit)
14
15
A.
B.
For CLKRP = CLKXP =
receiver is configured for
For CLKRP = CLKXP =
receiver is configured for
A0 A1
A30 A31 B0 B1
B30 B31 C0 C1 C2 C3
C31
1, the McASP transmitter is configured for falling edge (to shift data out) and the McASP
rising edge (to shift data in).
0, the McASP transmitter is configured for rising edge (to shift data out) and the McASP
falling edge (to shift data in).
Figure 8-85. McASP Output Timing
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8.16 MultiMedia Card/Secure Digital/Secure Digital Input Output (MMC/SD/SDIO)
The device includes 3 MMC/SD/SDIO Controllers which are compliant with MMC V4.3, Secure Digital Part
1 Physical Layer Specification V2.00 and Secure Digital Input Output (SDIO) V2.00 specifications.
The device MMC/SD/SDIO Controller has the following features:
• MultiMedia card (MMC)
• Secure Digital (SD) memory card
• MMC/SD protocol support
• SDIO protocol support
• Programmable clock frequency
• 1024 byte read/write FIFO to lower system overhead
• Slave EDMA transfer capability
• SD High capacity support
• SDXC card support
– Supports only SDHC clock rates
– Booting from SDXC cards is not supported
8.16.1 MMC/SD/SDIO Peripheral Register Descriptions
The MMC/SD/SDIO peripheral registers are described in the device-specific Technical Reference Manual.
Each register is documented as an offset from a base address for the peripheral. The base addresses for
all of the peripherals are in the device memory map (see Section 2.10).
8.16.2 MMC/SD/SDIO Electrical Data/Timing
Table 8-76. Timing Requirements for MMC/SD/SDIO
(see Figure 8-87, Figure 8-89)
OPP100/OPP120/
Turbo
NO
.
UNIT
ALL MODES
MIN
MAX
1
tsu(CMDV-CLKH)
Setup time, SD_CMD valid before SD_CLK rising clock edge
4.1
ns
2
th(CLKH-CMDV)
Hold time, SD_CMD valid after SD_CLK rising clock edge
1.9
ns
3
tsu(DATV-CLKH)
Setup time, SD_DATx valid before SD_CLK rising clock edge
4.1
ns
4
th(CLKH-DATV)
Hold time, SD_DATx valid after SD_CLK rising clock edge
1.9
ns
Table 8-77. Switching Characteristics Over Recommended Operating Conditions for MMC/SD/SDIO
(see Figure 8-86 through Figure 8-89)
OPP100/OPP120/
Turbo
NO.
MODES
PARAMETER
3.3 V STD
1.8 V SDR12
MIN
7
8
9
10
(1)
260
fop(CLK)
Operating frequency, SD_CLK
tc(CLK)
Operating period: SD_CLK
fop(CLKID)
Identification mode frequency, SD_CLK
tc(CLKID)
Identification mode period: SD_CLK
tw(CLKL)
Pulse duration, SD_CLK low
tw(CLKH)
Pulse duration, SD_CLK high
UNIT
3.3 V HS
1.8 V SDR25
MAX
MIN
24
41.7
MAX
48
20.8
400
MHz
ns
400
kHz
2500.0
2500.0
ns
0.5*P (1)
0.5*P (1)
ns
(1)
(1)
ns
0.5*P
0.5*P
P = SD_CLK period.
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Table 8-77. Switching Characteristics Over Recommended Operating Conditions for
MMC/SD/SDIO (continued)
(see Figure 8-86 through Figure 8-89)
OPP100/OPP120/
Turbo
NO.
MODES
PARAMETER
3.3 V STD
1.8 V SDR12
MIN
UNIT
3.3 V HS
1.8 V SDR25
MAX
MIN
MAX
11
tr(CLK)
Rise time, All Signals (10% to 90%)
2.2
2.2
ns
12
tf(CLK)
Fall time, All Signals (10% to 90%)
2.2
2.2
ns
13
td(CLKL-CMD)
Delay time, SD_CLK rising clock edge to SD_CMD
transition
-4
4
2.3
14
ns
14
td(CLKL-DAT)
Delay time, SD_CLK rising clock edge to SD_DATx
transition
-4
4
2.3
14
ns
10
7
9
SDx_CLK
13
13
START
SDx_CMD
13
13
XMIT
Valid
Valid
Valid
END
Figure 8-86. MMC/SD/SDIO Host Command Timing
9
7
10
SDx_CLK
1
2
SDx_CMD
START
XMIT
Valid
Valid
Valid
END
Figure 8-87. MMC/SD/SDIO Card Response Timing
10
9
7
SDx_CLK
14
14
START
SDx_DAT[x]
14
14
D0
D1
Dx
END
Figure 8-88. MMC/SD/SDIO Host Write Timing
9
10
7
SDx_CLK
4
4
3
3
SDx_DAT[x]
Start
D0
D1
Dx
End
Figure 8-89. MMC/SD/SDIO Host Read and Card CRC Status Timing
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8.17 Peripheral Component Interconnect Express (PCIe)
The device supports connections to PCIe-compliant devices via the integrated PCIe master/slave bus
interface. The PCIe module is comprised of a dual-mode PCIe core and a SerDes PHY. The device
implements a single one-lane PCIe 2.0 (5.0 GT/s) Endpoint/Root Complex port.
The device PCIe supports the following features:
• Supports Gen1/Gen2 in x1 or x2 mode
• One port with one 5 GT/s lane
• Single virtual channel (VC), single traffic class (TC)
• Single function in end-point mode
• Automatic width and speed negotiation and lane reversal
• Max payload: 128 byte outbound, 256 byte inbound
• Automatic credit management
• ECRC generation and checking
• Configurable BAR filtering
• Supports PCIe messages
• Legacy interrupt reception (RC) and generation (EP)
• MSI generation and reception
• PCI device power management, except D3 cold with vaux
• Active state power management state L0 and L1.
For more detailed information on the PCIe port peripheral module, see the PCI Express (PCIe) Module
chapter in the device-specific Technical Reference Manual.
The PCIe peripheral on the device conforms to the PCI Express Base 2.0 Specification.
8.17.1 PCIe Peripheral Register Descriptions
The PCIe peripheral registers are described in the device-specific Technical Reference Manual. Each
register is documented as an offset from a base address for the peripheral. The base addresses for all of
the peripherals are in the device memory map (see Section 2.10).
8.17.2 PCIe Electrical Data/Timing
Texas Instruments (TI) has performed the simulation and system characterization to ensure that the PCIe
peripheral meets all AC timing specifications as required by the PCI Express Base 2.0 Specification.
Therefore, the AC timing specifications are not reproduced here. For more information on the AC timing
specifications, see Sections 4.3.3.5 and 4.3.4.4 of the PCI Express Base 2.0 Specification.
8.17.3 PCIe Design and Layout Guidelines
8.17.3.1 Clock Source
A standard 100-MHz PCIe differential clock source must be used for PCIe operation (for more details, see
Section 7.4.2, SERDES CLKN/P Input Clock).
8.17.3.2 PCIe Connections and Interface Compliance
The PCIe interface on the device is compliant with the PCI Express Base 2.0 Specification. Refer to the
PCIe specifications for all connections that are described in it. For coupling capacitor selection, see
Section 8.17.3.2.1, Coupling Capacitors.
The use of PCIe-compatible bridges and switches is allowed for interfacing with more than one other
processor or PCIe device.
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8.17.3.2.1 Coupling Capacitors
AC coupling capacitors are required on the transmit data pair. Table 8-78 shows the requirements for
these capacitors.
Table 8-78. AC Coupling Capacitors Requirements
PARAMETER
MIN
PCIe AC coupling capacitor value
PCIe AC coupling capacitor package size (1)
(1)
(2)
TYP
75
0402
MAX
UNIT
200
nF
0603
EIA (2)
The physical size of the capacitor should be as small as practical. Use the same size on both lines in each pair, placed side by side.
EIA LxW units; that is, a 0402 is a 40x20 mil (thousandths of an inch) surface-mount capacitor.
8.17.3.2.2 Polarity Inversion
The PCIe specification requires polarity inversion support. This means, for layout purposes, polarity is
unimportant since each signal can change its polarity on-die inside the chip. This means polarity within a
lane is unimportant for layout.
8.17.3.3 Non-Standard PCIe Connections
The following sections contain suggestions for any PCIe connection that is not described in the official
PCIe specification, such as an on-board device-to-device connection, or device-to-other PCIe-compliant
processor connection.
8.17.3.3.1 PCB Stackup Specifications
Table 8-79 shows the stackup and feature sizes required for these types of PCIe connections.
Table 8-79. PCIe PCB Stackup Specifications
MIN
TYP
MAX
PCB Routing/Plane Layers
PARAMETER
4
6
-
Layers
Signal Routing Layers
2
3
-
Layers
Number of ground plane cuts allowed within PCIe routing region
-
-
0
Cuts
Number of layers between PCIe routing area and reference plane (1)
-
-
0
Layers
PCB Routing clearance
-
4
-
Mils
PCB Trace width (2)
-
4
-
Mils
PCB BGA escape via pad size
-
20
-
Mils
PCB BGA escape via hole size
-
10
Mils
0.4
mm
Processor BGA pad size
(1)
(2)
(3)
(4)
(3) (4)
UNIT
A reference plane may be a ground plane or the power plane referencing the PCIe signals.
In breakout area.
Non-solder mask defined pad.
Per IPC-7351A BGA pad size guideline.
8.17.3.3.2 Routing Specifications
The PCIe data signal traces must be routed to achieve 100 Ω (±20%) differential impedance and 60 Ω
(±15%) single-ended impedance. The single-ended impedance is required because differential signals are
extremely difficult to closely couple on PCBs and, therefore, single-ended impedance becomes important.
These requirements are the same as those recommended in the PCIe Motherboard Checklist 1.0
document, available from PCI-SIG.
These impedances are impacted by trace width, trace spacing, distance between signals and referencing
planes, and dielectric material. Verify with a PCB design tool that the trace geometry for both data signal
pairs result in as close to 100 Ω differential impedance and 60 Ω single-ended impedance as possible. For
best accuracy, work with your PCB fabricator to ensure this impedance is met.
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In general, closely coupled differential signal traces are not an advantage on PCBs. When differential
signals are closely coupled, tight spacing and width control is necessary. Very small width and spacing
variations affect impedance dramatically, so tight impedance control can be more problematic to maintain
in production.
Loosely coupled PCB differential signals make impedance control much easier. Wider traces and spacing
make obstacle avoidance easier, and trace width variations do not affect impedance as much; therefore, it
is easier to maintain an accurate impedance over the length of the signal. The wider traces also show
reduced skin effect and, therefore, often result in better signal integrity.
Table 8-80 shows the routing specifications for the PCIe data signals.
Table 8-80. PCIe Routing Specifications
MAX
UNIT
PCIe signal trace length
PARAMETER
MIN
TYP
10 (1)
Inches
Differential pair trace matching
10 (2)
Number of stubs allowed on PCIe traces (3)
0
TX/RX pair differential impedance
80
100
120
TX/RX single ended impedance
51
60
69
Mils
Stubs
Ω
Ω
Pad size of vias on PCIe trace
25 (4)
Hole size of vias on PCIe trace
14
Mils
3
Vias (5)
Number of vias on each PCIe trace
2*DS (6)
PCIe differential pair to any other trace spacing
(1)
(2)
(3)
(4)
(5)
(6)
264
Mils
Beyond this, signal integrity may suffer.
For example, RXP0 within 10 Mils of RXN0.
In-line pads may be used for probing.
35-Mil antipad max recommended.
Vias must be used in pairs with their distance minimized.
DS = differential spacing of the PCIe traces.
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8.18 Serial ATA Controller (SATA)
The Serial ATA (SATA) peripheral provides a direct interface to one hard disk drive (SATA) or multiple
hard disk drives using a Port Multiplier and supports the following features:
• Serial ATA 1.5 Gbps and 3 Gbps speeds
• Integrated PHYs
• Integrated Rx and Tx data buffers
• Supports all SATA power management features
• Hardware-assisted native command queuing (NCQ) for up to 32 entries
• Supports port multiplier with command-based switching
• Activity LED support.
8.18.1 SATA Peripheral Register Descriptions
The SATA peripheral registers are described in the device-specific Technical Reference Manual. Each
register is documented as an offset from a base address for the peripheral. The base addresses for all of
the peripherals are in the device memory map (see Section 2.10).
8.18.2 SATA Interface Design Guidelines
This section provides PCB design and layout guidelines for the SATA interface. The design rules constrain
PCB trace length, PCB trace skew, signal integrity, cross-talk, and signal timing. Simulation and system
design work has been done to ensure the SATA interface requirements are met.
A standard 100-MHz differential clock source must be used for SATA operation (for details, see
Section 7.4.2, SERDES_CLKN/P Input Clock).
8.18.2.1 SATA Interface Schematic
Figure 8-90 shows the data portion of the SATA interface schematic.
The specific pin numbers can be obtained from Section 3.3.21, Serial ATA (SATA) Signals.
SATA Interface (Processor)
SATA Connector
10 nF
SATA_TXN0
SATA_TXP0
TXTX+
10 nF
10 nF
SATA_RXN0
SATA_RXP0
RXRX+
10 nF
Figure 8-90. SATA Interface High-Level Schematic
8.18.2.2 Compatible SATA Components and Modes
Table 8-81 shows the compatible SATA components and supported modes. Note that the only supported
configuration is an internal cable from the processor host to the SATA device.
Table 8-81. SATA Supported Modes
PARAMETER
MIN
MAX
UNIT
1.5
3.0
Gbps
xSATA
-
-
-
No
Backplane
-
-
-
No
Transfer Rates
SUPPORTED
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Table 8-81. SATA Supported Modes (continued)
PARAMETER
Internal Cable (iSATA)
MIN
MAX
-
-
UNIT
SUPPORTED
-
Yes
8.18.2.3 PCB Stackup Specifications
Table 8-82 shows the PCB stackup and feature sizes required for SATA.
Table 8-82. SATA PCB Stackup Specifications
PARAMETER
MIN
TYP
MAX
PCB routing/plane layers
4
6
-
Layers
Signal routing layers
2
3
-
Layers
Number of ground plane cuts allowed within SATA routing region
-
-
0
Cuts
Number of layers between SATA routing region and reference ground plane
-
-
0
Layers
PCB trace width, w
-
4
-
Mils
PCB BGA escape via pad size
-
20
-
Mils
PCB BGA escape via hole size
-
10
Mils
0.4
mm
Processor BGA pad size
(1)
(1)
UNIT
NSMD pad, per IPC-7351A BGA pad size guideline.
8.18.2.4 Routing Specifications
The SATA data signal traces must be routed to achieve 100 Ω (±20%) differential impedance and 60 Ω
(±15%) single-ended impedance. The single-ended impedance is required because differential signals are
extremely difficult to closely couple on PCBs and, therefore, single-ended impedance becomes important.
60 Ω is chosen for the single-ended impedance to minimize problems caused by too low an impedance.
These impedances are impacted by trace width, trace spacing, distance to reference planes, and dielectric
material. Verify with a PCB design tool that the trace geometry for both data signal pairs results in as
close to 100 Ω differential impedance and 60 Ω single-ended impedance traces as possible. For best
accuracy, work with your PCB fabricator to ensure this impedance is met.
When routing SATA on the top (or any single) layer, the pin assignment will not allow a straight routing for
the SATAx_RXP0 and SATAx_RXN0 signals. There are two ways to overcome this:
1. Swap the SATA pin assignment in the software registers to allow straight, single layer routing.
2. Use the method pictured below in Figure 8-91 and Figure 8-92 to route to the SATA connector. This
method results in lines that are still length matched, and still on just one single layer.
Figure 8-91. SATA Routing
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SATAx_RXP0
SATAx_RXN0
Figure 8-92. Close Up of SATA Routing
Table 8-83 shows the routing specifications for the SATA data signals.
Table 8-83. SATA Routing Specifications
PARAMETER
MIN
TYP
Processor-to-SATA header trace length
Number of stubs allowed on SATA traces (2)
MAX
UNIT
10 (1)
Inches
0
Stubs
Ω
TX/RX pair differential impedance
80
100
120
TX/RX single ended impedance
51
60
69
Ω
3
Vias (3)
Number of vias on each SATA trace
2*DS (4)
SATA differential pair to any other trace spacing
(1)
(2)
(3)
(4)
Beyond this, signal integrity may suffer.
In-line pads may be used for probing.
Vias must be used in pairs with their distance minimized.
DS = differential spacing of the SATA traces.
8.18.2.5 Coupling Capacitors
AC coupling capacitors are required on the receive data pair. Table 8-84 shows the requirements for these
capacitors.
Table 8-84. SATA AC Coupling Capacitors Requirements
PARAMETER
SATA AC coupling capacitor value
SATA AC coupling capacitor package size
(1)
(2)
(1)
MIN
TYP
MAX
1
10
12
0402
0603
UNIT
nF
EIA (2)
The physical size of the capacitor should be as small as practical. Use the same size on both lines in each pair, placed side by side.
EIA LxW units; that is, a 0402 is a 40 x 20 mil surface-mount capacitor.
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8.19 Serial Peripheral Interface (SPI)
The SPI is a high-speed synchronous serial input/output port that allows a serial bit stream of programmed
length (4 to 32 bits) to be shifted into and out of the device at a programmed bit-transfer rate. The SPI is
normally used for communication between the device and external peripherals. Typical applications
include an interface-to-external I/O or peripheral expansion via devices such as shift registers, display
drivers, SPI EEPROMs, and Analog-to-Digital Converters (ADCs).
The SPI supports the following features:
• Master/Slave operation
• Four chip selects for interfacing/control to up to four SPI Slave devices and connection to a single
external Master
• 32-bit shift register
• Buffered receive/transmit data register per channel (1 word deep), FIFO size is 64 bytes
• Programmable SPI configuration per channel (clock definition, enable polarity and word width)
• Supports one interrupt request and two DMA requests per channel.
For more detailed information on the SPI, see the Multichannel Serial Port Interface (McSPI) chapter in
the device-specific Technical Reference Manual.
8.19.1 SPI Peripheral Register Descriptions
The SPI peripheral registers are described in the device-specific Technical Reference Manual. Each
register is documented as an offset from a base address for the peripheral. The base addresses for all of
the peripherals are in the device memory map (see Section 2.10).
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8.19.2 SPI Electrical Data/Timing
Table 8-85. Timing Requirements for SPI - Master Mode
(see Figure 8-93 and Figure 8-94)
OPP100/OPP120/
Turbo
NO.
MIN
UNIT
MAX
MASTER: SPI0, SPI1, SPI2 (M0) and SPI3 (M0)1 LOAD AT A MAXIMUM OF 5 pF
1
tc(SPICLK)
Cycle time, SPI_CLK (1) (2)
(1)
2
tw(SPICLKL)
Pulse duration, SPI_CLK low
3
tw(SPICLKH)
Pulse duration, SPI_CLK high (1)
4
tsu(MISO-SPICLK)
Setup time, SPI_D[x] valid before SPI_CLK active
edge (1)
5
th(SPICLK-MISO)
Hold time, SPI_D[x] valid after SPI_CLK active edge (1)
4
2.67
ns
3.57
ns
Delay time, SPI_SCS[x] active edge to SPI_D[x] transition
td(SPICLK-SCS)
ns
3.57
Delay time, SPI_CLK active edge to SPI_D[x] transition
9
ns
(1)
td(SCS-MOSI)
Delay time, SPI_CLK last edge to SPI_SCS[x]
inactive (1)
ns
2.29
td(SPICLK-MOSI)
Delay time, SPI_SCS[x] active to SPI_CLK first
edge (1)
ns
0.5*P - 1 (4)
SPI2, SPI3
7
td(SCS-SPICLK)
ns
0.5*P - 1 (4)
SPI0, SPI1
6
8
20.8 (3)
MASTER_PH
A0 (5)
B-4.2
(6)
ns
MASTER_PH
A1 (5)
A-4.2 (7)
ns
MASTER_PH
A0 (5)
A-4.2 (7)
ns
MASTER_PH
A1 (5)
B-4.2 (6)
ns
MASTER: SPI0, SPI1, SPI2 (M0) and SPI3 (M0) LOAD AT MAX 25pF
MASTER: SPI2 (M1, M2, M3) and SPI3 (M1, M2, M3) 1 to 4 LOAD AT 5 to 25pF
1
2
3
(8)
Pulse duration, SPI_CLK low
(1)
(1)
Pulse duration, SPI_CLK high
4
tsu(MISO-SPICLK)
Setup time, SPI_D[x] valid before SPI_CLK active
edge (1)
5
th(SPICLK-MISO)
Hold time, SPI_D[x] valid after SPI_CLK active edge (1)
6
ns
3.8
(1)
Delay time, SPI_CLK active edge to SPI_D[x] transition
Delay time, SPI_SCS[x] active edge to SPI_D[x] transition
td(SPICLK-SCS)
ns
SPI2, SPI3
td(SCS-MOSI)
Delay time, SPI_CLK last edge to SPI_SCS[x]
inactive (1)
ns
(4)
4
td(SPICLK-MOSI)
Delay time, SPI_SCS[x] active to SPI_CLK first
edge (1)
ns
0.5*P - 2 (4)
0.5*P - 2
7
td(SCS-SPICLK)
41.7 (8)
SPI0, SPI1
6
9
(2)
(3)
(4)
(5)
(6)
(7)
tw(SPICLKL)
Cycle time, SPI_CLK (1) (2)
tw(SPICLKH)
8
(1)
tc(SPICLK)
-5.5
ns
5.5
ns
5.5
ns
MASTER_PH
A0 (5)
B-3.5 (6)
ns
MASTER_PH
A1 (5)
A-3.5 (7)
ns
MASTER_PH
A0 (5)
A-3.5 (7)
ns
MASTER_PH
A1 (5)
B-3.5 (6)
ns
This timing applies to all configurations regardless of SPI_CLK polarity and which clock edges are used to drive output data and capture
input data.
Related to the SPI_CLK maximum frequency.
Maximum frequency = 48 MHz
P = SPICLK period.
SPI_CLK phase is programmable with the PHA bit of the SPI_CH(i)CONF register.
B = (TCS + 0.5) * TSPICLKREF * Fratio, where TCS is a bit field of the SPI_CH(i)CONF register and Fratio = Even ≥2.
When P = 20.8 ns, A = (TCS + 1) * TSPICLKREF, where TCS is a bit field of the SPI_CH(i)CONF register. When P > 20.8 ns, A = (TCS
+ 0.5) * Fratio * TSPICLKREF, where TCS is a bit field of the SPI_CH(i)CONF register.
Maximum frequency = 24 MHz
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PHA=0
EPOL=1
SPI_SCS[x] (Out)
1
3
8
SPI_SCLK (Out)
9
2
POL=0
1
2
3
POL=1
SPI_SCLK (Out)
6
7
SPI_D[x] (Out)
Bit n-1
6
Bit n-3
Bit n-2
Bit 0
Bit n-4
PHA=1
EPOL=1
SPI_SCS[x] (Out)
1
3
8
SPI_SCLK (Out)
9
2
POL=0
1
2
3
POL=1
SPI_SCLK (Out)
6
SPI_D[x] (Out)
Bit n-1
6
Bit n-2
6
Bit n-3
6
Bit 1
Bit 0
Figure 8-93. SPI Master Mode Transmit Timing
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PHA=0
EPOL=1
SPI_SCS[x] (Out)
1
3
8
SPI_SCLK (Out)
9
2
POL=0
1
2
3
POL=1
SPI_SCLK (Out)
4
4
5
SPI_D[x] (In)
5
Bit n-1
Bit n-3
Bit n-2
Bit 0
Bit n-4
PHA=1
EPOL=1
SPI_SCS[x] (Out)
1
3
8
SPI_SCLK (Out)
9
2
POL=0
1
2
3
POL=1
SPI_SCLK (Out)
4
4
5
SPI_D[x] (In)
Bit n-1
5
Bit n-2
Bit n-3
Bit 0
Bit 1
Figure 8-94. SPI Master Mode Receive Timing
Table 8-86. Timing Requirements for SPI - Slave Mode
(see Figure 8-95 and Figure 8-96)
OPP100/OPP120/Turbo
NO.
1
(1)
(2)
(3)
(4)
(5)
MIN
tc(SPICLK)
Cycle time, SPI_CLK (1) (2)
(1)
2
tw(SPICLKL)
Pulse duration, SPI_CLK low
3
tw(SPICLKH)
Pulse duration, SPI_CLK high (1)
4
tsu(MOSI-SPICLK)
Setup time, SPI_D[x] valid before SPI_CLK active edge (1)
5
th(SPICLK-MOSI)
Hold time, SPI_D[x] valid after SPI_CLK active edge
6
td(SPICLK-MISO)
Delay time, SPI_CLK active edge to SPI_D[x] transition (1)
7
td(SCS-MISO)
Delay time, SPI_SCS[x] active edge to SPI_D[x]
transition (5)
8
tsu(SCS-SPICLK)
Setup time, SPI_SCS[x] valid before SPI_CLK first edge (1)
UNIT
62.5 (3)
ns
(4)
ns
0.5*P - 3 (4)
ns
12.92
ns
0.5*P - 3
(1)
MAX
12.92
-4.00
ns
17.1
ns
17.1
ns
12.92
ns
This timing applies to all configurations regardless of SPI_CLK polarity and which clock edges are used to drive output data and capture
input data.
Related to the input maximum frequency supported by the SPI module.
Maximum frequency = 16 MHz
P = SPICLK period.
PHA = 0; SPI_CLK phase is programmable with the PHA bit of the SPI_CH(i)CONF register.
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Table 8-86. Timing Requirements for SPI - Slave Mode (continued)
(see Figure 8-95 and Figure 8-96)
OPP100/OPP120/Turbo
NO.
9
MIN
Hold time, SPI_SCS[x] valid after SPI_CLK last edge (1)
th(SPICLK-SCS)
MAX
12.92
UNIT
ns
PHA=0
EPOL=1
SPI_SCS[x] (In)
1
3
8
SPI_SCLK (In)
2
9
POL=0
1
3
2
POL=1
SPI_SCLK (In)
SPI_D[x] (Out)
6
7
6
Bit n-1
Bit n-2
Bit n-3
Bit 0
Bit n-4
PHA=1
EPOL=1
SPI_SCS[x] (In)
1
3
8
SPI_SCLK (In)
9
2
POL=0
1
2
3
POL=1
SPI_SCLK (In)
6
SPI_D[x] (Out)
Bit n-1
6
6
Bit n-2
Bit n-3
6
Bit 1
Bit 0
Figure 8-95. SPI Slave Mode Transmit Timing
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PHA=0
EPOL=1
SPI_SCS[x] (In)
1
3
8
SPI_SCLK (In)
2
9
POL=0
1
3
2
POL=1
SPI_SCLK (In)
4
4
5
SPI_D[x] (In)
5
Bit n-1
Bit n-3
Bit n-2
Bit 0
Bit n-4
PHA=1
EPOL=1
SPI_SCS[x] (In)
1
3
8
SPI_SCLK (In)
9
2
POL=0
1
2
3
POL=1
SPI_SCLK (In)
4
5
SPI_D[x] (In)
Bit n-1
4
5
Bit n-2
Bit n-3
Bit 1
Bit 0
Figure 8-96. SPI Slave Mode Receive Timing
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8.20 Timers
The device has eight 32-bit general-purpose (GP) timers (TIMER8 - TIMER1) that have the following
features:
• TIMER8, TIMER1 are for software use and do not have an external connection
• Dedicated input trigger for capture mode and dedicated output trigger/pulse width modulation (PWM)
signal
• Interrupts generated on overflow, compare, and capture
• Free-running 32-bit upward counter
• Supported modes:
– Compare and capture modes
– Auto-reload mode
– Start-stop mode
• TIMER[8:1] functional clock is sourced from either the DEVOSC, AUXOSC, AUD_CLK2/1/0, TCLKIN,
or SYSCLK18 27 MHz as selected by the timer clock multiplexers.
• On-the-fly read/write register (while counting)
• Generates interrupts to the ARM and Media Controller.
The device has one system watchdog timer that have the following features:
• Free-running 32-bit upward counter
• On-the-fly read/write register (while counting)
• Reset upon occurrence of a timer overflow condition
• The system watchdog timer has two possible clock sources:
– RCOSC32K oscillator
– RTCDIVIDER
• The watchdog timer is used to provide a recovery mechanism for the device in the event of a fault
condition, such as a non-exiting code loop.
For more detailed information on the GP and Watchdog Timers, see the Timers and Watchdog Timer
chapters in the device-specific Technical Reference Manual.
8.20.1 Timer Peripheral Register Descriptions
The Timer peripheral registers are described in the device-specific Technical Reference Manual. Each
register is documented as an offset from a base address for the peripheral. The base addresses for all of
the peripherals are in the device memory map (see Section 2.10).
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8.20.2 Timer Electrical/Data Timing
Table 8-87. Timing Requirements for Timer
(see Figure 8-97)
OPP100/OPP120/
Turbo
NO.
MIN
1
tw(EVTIH)
2
(1)
tw(EVTIL)
Pulse duration, high
Pulse duration, low
UNIT
MAX
4P (1)
ns
(1)
ns
4P
P = module clock.
Table 8-88. Switching Characteristics Over Recommended Operating Conditions for Timer
(see Figure 8-97)
NO.
OPP100/OPP120/
Turbo
PARAMETER
MIN
(1)
UNIT
MAX
3
tw(EVTOH)
Pulse duration, high
4P-3 (1)
ns
4
tw(EVTOL)
Pulse duration, low
4P-3 (1)
ns
P = module clock.
1
2
TCLKIN
3
4
TIMx_IO
Figure 8-97. Timer Timing
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8.21 Universal Asynchronous Receiver/Transmitter (UART)
The UART performs serial-to-parallel conversions on data received from a peripheral device and parallelto-serial conversion on data received from the CPU. The device provides up to three UART peripheral
interfaces, depending on the selected pin multiplexing.
Each UART has the following features:
• Selectable UART/IrDA (SIR/MIR)/CIR modes
• Dual 64-entry FIFOs for received and transmitted data payload
• Programmable and selectable transmit and receive FIFO trigger levels for DMA and interrupt
generation
• Baud-rate generation based upon programmable divisors N (N=1…16384)
• Two DMA requests and one interrupt request to the system
• Can connect to any RS-232 compliant device.
UART functions include:
• Baud-rate up to 3.6 Mbit/s on UART0, UART1, and UART2
• Programmable serial interfaces characteristics
– 5, 6, 7, or 8-bit characters
– Even, odd, or no parity-bit generation and detection
– 1, 1.5, or 2 stop-bit generation
– Flow control: hardware (RTS/CTS) or software (XON/XOFF)
• Additional modem control functions (UART0_DTR, UART0_DSR, UART0_DCD, and UART0_RIN) for
UART0 only; UART1 and UART2 do not support full-flow control signaling.
IR-IrDA functions include:
• Support of IrDA 1.4 slow infrared (SIR, baud-rate up to 115.2 Kbits/s), medium infrared (MIR, baudrate up to 1.152 Mbits/s) and fast infrared (FIR baud-rate up to 4.0 Mbits/s) communications
• Supports framing error, cyclic redundancy check (CRC) error, illegal symbol (FIR), and abort pattern
(SIR, MIR) detection
• 8-entry status FIFO (with selectable trigger levels) available to monitor frame length and frame errors.
IR-CIR functions include:
• Consumer infrared (CIR) remote control mode with programmable data encoding
• Free data format (supports any remote control private standards)
• Selectable bit rate and configurable carrier frequency.
For more detailed information on the UART peripheral, see the UART/IrDA/CIR Module chapter in the
device-specific Technical Reference Manual.
8.21.1 UART Peripheral Register Descriptions
The UART peripheral registers are described in the device-specific Technical Reference Manual. Each
register is documented as an offset from a base address for the peripheral. The base addresses for all of
the peripherals are in the device memory map (see Section 2.10).
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8.21.2 UART Electrical/Data Timing
Table 8-89. Timing Requirements for UART
(see Figure 8-98)
OPP100/OPP120/
Turbo
NO.
4
(1)
(2)
MAX
Pulse width, receive data bit, 15/30/100pF high or low
0.96U (1)
1.05U (1)
ns
tw(CTS)
Pulse width, receive start bit, 15/30/100pF high or low
(1)
(1)
ns
td(RTS-TX)
Delay time, transmit start bit to transmit data
P (2)
ns
td(CTS-TX)
Delay time, receive start bit to transmit data
P (2)
ns
tw(RX)
5
UNIT
MIN
0.96U
1.05U
U = UART baud time = 1/programmed baud rate
P = Clock period of the reference clock (FCLK, usually 48 MHz).
Table 8-90. Switching Characteristics Over Recommended Operating Conditions for UART
(see Figure 8-98)
NO.
OPP100/OPP120/
Turbo
PARAMETER
MIN
f(baud)
2
3
(1)
tw(TX)
tw(RTS)
Maximum programmable baud rate
UNIT
MAX
15 pF
5
30 pF
0.23
100 pF
0.115
MHz
Pulse width, transmit data bit, 15/30/100 pF high or low
U - 2 (1)
U + 2 (1)
ns
Pulse width, transmit start bit, 15/30/100 pF high or low
(1)
(1)
ns
U-2
U+2
U = UART baud time = 1/programmed baud rate
3
2
UARTx_TXD
Start
Bit
Data Bits
5
4
UARTx_RXD
Start
Bit
Data Bits
Figure 8-98. UART Timing
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8.22 Universal Serial Bus (USB2.0)
The device includes two USB2.0 modules which support the Universal Serial Bus Specification Revision
2.0. The following are some of the major USB features that are supported:
• USB 2.0 peripheral at high speed (HS: 480 Mbps) and full speed (FS: 12 Mbps)
• USB 2.0 host at HS, FS, and low speed (LS: 1.5 Mbps)
• Each endpoint (other than endpoint 0, control only) can support all transfer modes (control, bulk,
interrupt, and isochronous)
• Supports high-bandwidth ISO mode
• Supports 15 Transmit (TX) and 15 Receive (RX) endpoints including endpoint 0
• FIFO RAM
– 32K endpoint
– Programmable size
• Includes two integrated PHYs
• RNDIS-like mode for terminating RNDIS-type protocols without using short-packet termination for
support of MSC applications.
• USB Dual Role Device: Host Negotiation Protocol (HNP)
The USB2.0 peripherals do not support the following features:
• On-chip charge pump (VBUS Power must be generated external to the device.)
• RNDIS mode acceleration for USB sizes that are not multiples of 64 bytes
• Endpoint max USB packet sizes that do not conform to the USB 2.0 spec (for FS/LS: 8, 16, 32, 64, –
and 1023 are defined; for HS: 64, 128, 512, and 1024 are defined
• USB OTG extension: Session Request Protocol (SRP)
For more detailed information on the USB2.0 peripheral, see the Universal Serial Bus (USB) chapter in the
device-specific Technical Reference Manual.
8.22.1 USB2.0 Peripheral Register Descriptions
The USB peripheral registers are described in the device-specific Technical Reference Manual. Each
register is documented as an offset from a base address for the peripheral. The base addresses for all of
the peripherals are in the device memory map (see Section 2.10).
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8.22.2 USB2.0 Electrical Data/Timing
Table 8-91. Switching Characteristics Over Recommended Operating Conditions for USB2.0
(see Figure 8-99)
OPP100/OPP120/
Turbo
NO.
PARAMETER
(1)
FULL SPEED
12 Mbps
HIGH SPEED
480 Mbps
MIN
MAX
MIN
MAX
MIN
1
tr(D)
Rise time, USBx_DP and USBx_DM signals
75
300
4
20
0.5
2
tf(D)
Fall time, USBx_DP and USBx_DM signals (1)
75
300
4
20
0.5
3
trfM
Rise/Fall time, matching (2)
80
125
90
111
–
1.3
2
1.3
2
–
(1)
4
VCRS
Output signal cross-over voltage
5
tjr(source)NT
Source (Host) Driver jitter, next transition
tjr(FUNC)NT
Function Driver jitter, next transition
tjr(source)PT
Source (Host) Driver jitter, paired transition (4)
6
tjr(FUNC)PT
Function Driver jitter, paired transition
7
tw(EOPT)
Pulse duration, EOP transmitter
1250
8
tw(EOPR)
Pulse duration, EOP receiver (5)
670
9
t(DRATE)
Data Rate
10
ZDRV
Driver Output Resistance
11
ZINP
Receiver Input Impedance
(1)
(2)
(3)
(4)
(5)
LOW SPEED
1.5 Mbps
ns
ns
–
%
–
V
2
(3)
ns
25
2
(3)
ns
1
1
(3)
ns
1
(3)
ns
–
ns
1500
160
175
82
–
–
–
1.5
300
MAX
2
10
–
UNIT
12
ns
480 Mb/s
28
49.5
40.5
49.5
Ω
300
–
–
–
kΩ
Low Speed: CL = 200 pF, Full Speed: CL = 50 pF, High Speed: CL = 50 pF
tRFM = (tr/tf) x 100. [Excluding the first transaction from the Idle state.]
For more detailed information, see the Universal Serial Bus Specification Revision 2.0, Chapter 7, Electrical.
tjr = tpx(1) - tpx(0)
Must accept as valid EOP.
USBx_DM
VCRS
USBx_DP
t per − t jr
90% VOH
10% VOL
tr
tf
Figure 8-99. USB2.0 Integrated Transceiver Interface Timing
For more detailed information on USB2.0 board design, routing, and layout guidelines, see the USB 2.0
Board Design and Layout Guidelines Application Report (Literature Number: SPRAAR7).
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9 Device and Documentation Support
9.1
9.1.1
Device Support
Development Support
TI offers an extensive line of development tools, including tools to evaluate the performance of the
processors, generate code, develop algorithm implementations, and fully integrate and debug software
and hardware modules. The tool's support documentation is electronically available within the Code
Composer Studio™ Integrated Development Environment (IDE).
The following products support development of DMVA3/4 processor applications:
Software Development Tools: Code Composer Studio™ Integrated Development Environment (IDE):
including Editor C/C++/Assembly Code Generation, and Debug plus additional development tools
Scalable, Real-Time Foundation Software ( Device/BIOS™), which provides the basic run-time target
software needed to support any DMVA3/4 processor application.
Hardware Development Tools: Extended Development System ( XDS™) Emulator
For a complete listing of development-support tools for the DMVA3/4 processor platform, visit the Texas
Instruments website at www.ti.com. For information on pricing and availability, contact the nearest TI field
sales office or authorized distributor.
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9.1.2
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Device and Development Support-Tool Nomenclature
To designate the stages in the product development cycle, TI assigns prefixes to the part numbers of all
MPUs and support tools. Each device has one of three prefixes: X, P, or null (no prefix). Texas
Instruments recommends two of three possible prefix designators for its support tools: TMDX and TMDS.
These prefixes represent evolutionary stages of product development from engineering prototypes
(TMDX) through fully qualified production devices/tools (TMDS).
Device development evolutionary flow:
X
Pre-production device that is not necessarily representative of the final device's electrical
specifications and may not use production assembly flow.
P
Prototype device that is not necessarily the final silicon die and may not necessarily meet
final electrical specifications.
null
Production version of the silicon die that is fully qualified.
Support tool development evolutionary flow:
TMDX
Development-support product that has not yet completed Texas Instruments internal
qualification testing.
TMDS
Fully-qualified development-support product.
X and P devices and TMDX development-support tools are shipped against the following disclaimer:
"Developmental product is intended for internal evaluation purposes."
Production devices and TMDS development-support tools have been characterized fully, and the quality
and reliability of the device have been demonstrated fully. TI's standard warranty applies.
Predictions show that prototype devices (X or P) have a greater failure rate than the standard production
devices. Texas Instruments recommends that these devices not be used in any production system
because their expected end-use failure rate still is undefined. Only qualified production devices are to be
used.
9.1.3
Device Nomenclature
TI device nomenclature also includes a suffix with the device family name. This suffix indicates the
package type (for example, AAR), the temperature range (for example, blank is the default commercial
temperature range). Figure 9-1 provides a legend for reading the complete device name for any DMVA3/4
device.
For device part numbers and further ordering information of DMVA3/4 devices in the AAR package type,
see the TI website (www.ti.com) or contact your TI sales representative.
( ) DMVA3/4 ( )
AAR
( )
PREFIX
Blank = Production Device (TMS)
X = Pre-production Device
P = Prototype Device
DEVICE
DMVA3/4 DaVinci™ Digital Media Processors
DMVA3 (720-MHZ ARM, 290-MHZ HDVICP2)
DMVA4 (970-MHZ ARM, 410-MHZ HDVICP2)
SILICON REVISION
A = Revision 1.1
TEMPERATURE RANGE
Blank = 0°C to 95°C, Commercial Temperature
D = -40°C to 95°C, Extended Temperature
(A)
PACKAGE TYPE
AAR = 609-Pin Plastic BGA, with Pb-Free Die Bump
and Solder Ball
Figure 9-1. Device Nomenclature
Device and Documentation Support
Copyright © 2013, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: DMVA3
281
DMVA3, DMVA4
SPRS872B – MAY 2013 – REVISED DECEMBER 2013
9.2
www.ti.com
Documentation Support
Contact your TI sales representative for support documents.
For additional peripheral information, see the latest version of the DM38x DaVinci™ Digital Media
Processor Technical Reference Manual (Literature Number: SPRUHG1).
9.3
Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the
respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views;
see TI's Terms of Use.
TI E2E Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and
help solve problems with fellow engineers.
TI Embedded Processors Wiki Texas Instruments Embedded Processors Wiki. Established to help
developers get started with Embedded Processors from Texas Instruments and to foster
innovation and growth of general knowledge about the hardware and software surrounding
these devices.
282
Device and Documentation Support
Copyright © 2013, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: DMVA3
DMVA3, DMVA4
www.ti.com
SPRS872B – MAY 2013 – REVISED DECEMBER 2013
10 Mechanical
Table 10-1 shows the thermal resistance characteristics for the PBGA–AAR mechanical package.
The device package has been specially engineered with a new technology called Via Channel™, allowing
0.8 mm PCB design rules to be employed. This allows larger than normal PCB via and trace sizes and
reduced PCB signal layers to be used in a PCB design with this 0.5 mm pitch package, and will
substantially reduce PCB costs. It also allows PCB routing in only two signal layers (four layers total
deleted) due to the increased layer efficiency of the Via Channel™ BGA technology.
10.1 Thermal Data for the AAR
Table 10-1. Thermal Resistance Characteristics (PBGA Package) [AAR]
ΘJA/JMA
Junction-to-air/ Junction-to-moving air
PsiJT
Junction-to-package top
PsiJB
Junction-to-board
Air Flow (m/s) (1)
ºC/W (2)
still air
17.79
1.0 m/s
13.36
2.0 m/s
12.54
3.0 m/s
12.04
still air
0.08
1.0 m/s
0.16
2.0 m/s
0.20
3.0 m/s
0.23
still air
4.90
1.0 m/s
4.81
2.0 m/s
4.78
3.0 m/s
4.76
ΘJB
Junction-to-board
4.86
ΘJC (1SOP board)
Junction-to-case
3.84
(1)
(2)
m/s = meters per second.
These measurements were conducted in a JEDEC defined 2S2P system (with the exception of the Theta JC [ΘJC] measurement, which
was conducted in a JEDEC defined 1S0P system) and will change based on environment as well as application. For more information,
see these EIA/JEDEC standards:
• JESD51-2, Integrated Circuits Thermal Test Method Environment Conditions - Natural Convection (Still Air).
• JESD51-3, Low Effective Thermal Conductivity Test Board for Leaded Surface Mount Packages.
• JESD51-7, High Effective Thermal Conductivity Test Board for Leaded Surface Mount Packages.
• JESD51-9, Test Boards for Area Array Surface Mount Packages.
10.2 Packaging Information
The following packaging information and addendum reflect the most current data available for the
designated device(s). This data is subject to change without notice and without revision of this document.
Mechanical
Copyright © 2013, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: DMVA3
283
PACKAGE OPTION ADDENDUM
www.ti.com
25-Sep-2019
PACKAGING INFORMATION
Orderable Device
Status
(1)
DMVA3AAAR
ACTIVE
Package Type Package Pins Package
Drawing
Qty
FCBGA
AAR
609
90
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Green (RoHS
& no Sb/Br)
SNAGCU
Level-3-260C-168 HR
Op Temp (°C)
Device Marking
(4/5)
0 to 0
DMVA3AAAR
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
Samples
PACKAGE OUTLINE
AAR0609A
FCBGA - 1.32 mm max height
SCALE 0.900
BALL GRID ARRAY
16.1
15.9
B
A
BALL A1 CORNER
16.1
15.9
1.32
1.10
C
SEATING PLANE
BALL TYP
0.28
TYP
0.18
0.1 C
15 TYP
0.5 TYP
PKG
(0.5) TYP
(0.5) TYP
0.5 TYP
AL
AK
PKG
15
TYP
AJ
AH
AG
AF
AE
AD
AC
AB
AA
Y
W
V
U
T
R
P
N
M
L
K
J
H
G
F
E
D
C
B
A
609X
1
2
3
4
5
6
7
8
9
0.35
0.25
0.15
0.08
C A B
C
11 13 15 17 19 21 23 25 27 29 31
10 12 14 16 18 20 22 24 26 28 30
4224431/A 10/2018
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. Pb-free solder ball design.
www.ti.com
EXAMPLE BOARD LAYOUT
AAR0609A
FCBGA - 1.32 mm max height
BALL GRID ARRAY
(0.5) TYP
609X ( 0.3)
1
2 3
4
5
6
7
8
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
A
B
C
(0.5) TYP
D
E
F
G
H
J
K
L
M
N
P
PKG
R
T
U
V
W
Y
AA
AB
AC
AD
AE
AF
AG
AH
AJ
AK
AL
PKG
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:6X
( 0.3)
METAL
0.05 MAX
METAL UNDER
SOLDER MASK
0.05 MIN
EXPOSED METAL
SOLDER MASK
OPENING
EXPOSED METAL
NON-SOLDER MASK
DEFINED
(PREFERRED)
( 0.3)
SOLDER MASK
OPENING
SOLDER MASK
DEFINED
SOLDER MASK DETAILS
NOT TO SCALE
4224431/A 10/2018
NOTES: (continued)
5. Final dimensions may vary due to manufacturing tolerance considerations and also routing constraints.
For more information, see Texas Instruments literature number SPRU811 (www.ti.com/lit/spru811).
www.ti.com
EXAMPLE STENCIL DESIGN
AAR0609A
FCBGA - 1.32 mm max height
BALL GRID ARRAY
(0.5) TYP
609X ( 0.3)
1
2 3
4
5
6
7
8
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
A
B
C
(0.5) TYP
D
E
F
G
H
K
L
M
N
P
PKG
R
T
U
V
W
Y
AA
AB
AC
AD
AE
AF
AG
AH
AJ
AK
AL
PKG
SOLDER PASTE EXAMPLE
BASED ON 0.1 mm THICK STENCIL
SCALE:6X
4224431/A 10/2018
NOTES: (continued)
6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release.
www.ti.com
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