Texas Instruments | Rad-Tolerant Class-V Floating-Point Digital Signal Processor (Rev. F) | Datasheet | Texas Instruments Rad-Tolerant Class-V Floating-Point Digital Signal Processor (Rev. F) Datasheet

Texas Instruments Rad-Tolerant Class-V Floating-Point Digital Signal Processor (Rev. F) Datasheet
SMJ320C6701-SP
www.ti.com
SGUS030F – APRIL 2000 – REVISED SEPTEMBER 2013
RAD-TOLERANT CLASS-V FLOATING-POINT DIGITAL SIGNAL PROCESSOR
Check for Samples: SMJ320C6701-SP
FEATURES
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23456
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Rad-Tolerant: 100-kRad (Si) TID
SEL Immune at 89MeV-cm2/mg LET Ions
QML-V Qualified, SMD 5962-98661
Highest-Performance Floating-Point Digital
Signal Processor (DSP) SMJ320C6701
– 7-ns Instruction Cycle Time
– 140-MHz Clock Rate
– Eight 32-Bit Instructions/Cycle
– Up to One GFLOPS Performance
– Pin Compatible With ’C6201 Fixed-Point
DSP
SMJ: QML Processing to MIL-PRF-38535
SM: Standard Processing
Operating Temperature Ranges
– –55°C to 115°C
– –55°C to 125°C
VelociTI™ Advanced Very Long Instruction
Word (VLIW) ’C67x CPU Core
– Eight Highly Independent Functional Units:
– Four ALUs (Floating and Fixed Point)
– Two ALUs (Fixed Point)
– Two Multipliers (Floating and Fixed
Point)
– Load-Store Architecture With 32
32-Bit General-Purpose Registers
– Instruction Packing Reduces Code Size
– All Instructions Conditional
Instruction Set Features
– Hardware Support for IEEE SinglePrecision Instructions
– Hardware Support for IEEE DoublePrecision Instructions
– Byte Addressable (8-/16-/32-Bit Data)
– 32-Bit Address Range
– 8-Bit Overflow Protection
– Saturation
– Bit-Field Extract, Set, Clear
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– Bit Counting
– Normalization
1M-Bit On-Chip SRAM
– 512K-Bit Internal Program/Cache (16K 32Bit Instructions)
– 512K-Bit Dual-Access Internal Data (64K
Bytes)
32-Bit External Memory Interface (EMIF)
– Glueless Interface to Synchronous
Memories: SDRAM and SBSRAM
– Glueless Interface to Asynchronous
Memories: SRAM and EPROM
Four-Channel Bootloading
Direct Memory Access (DMA) Controller With
Auxiliary Channel
16-Bit Host-Port Interface (HPI)
– Access to Entire Memory Map
Two Multichannel Buffered Serial Ports
(McBSPs)
– Direct Interface to T1/E1, MVIP, SCSA
Framers
– ST Bus Switching Compatible
– Up to 256 Channels Each
– AC97 Compatible
– Serial Peripheral Interface (SPI)
Compatible ( Motorola™)
Two 32-Bit General-Purpose Timers
Flexible Phase-Locked Loop (PLL) Clock
Generator
IEEE Std 1149.1 (JTAG (1) )
Boundary Scan Compatible
429-Pin Ceramic Ball Grid Array (CBGA/GLP)
and Ceramic Land Grid Array (CLGA/ZMB)
Package Types
0.18-μm/5-Level Metal Process
– CMOS Technology
3.3-V I/Os, 1.9 V Internal
IEEE Std 1149.1-1990 Test Access Port and Boundary Scan
Architecture
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
VelociTI, XDS, XDS510, XDS510WS are trademarks of Texas Instruments.
Windows, Win32, NT are trademarks of Microsoft Corporation.
Motorola is a trademark of Motorola, Inc.
SPARC is a trademark of SPARC International.
Solaris is a trademark of Sun Microsystems, Inc..
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
(1)
Copyright © 2000–2013, Texas Instruments Incorporated
SMJ320C6701-SP
SGUS030F – APRIL 2000 – REVISED SEPTEMBER 2013
•
(2)
www.ti.com
Engineering Evaluation (/EM) Samples are
Available (2)
These units are intended for engineering evaluation only.
They are processed to a non-compliant flow (e.g. No Burn-In,
etc.) and are tested to a temperature rating of 25°C only.
These units are not suitable for qualification, production,
radiation testing or flight use. Parts are not warranted for
performance over the full MIL specified temperature range of
-55°C to 125°C or operating life.
GLP AND ZMB PACKAGES
( BOTTOM VIEW )
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DESCRIPTION
The SMJ320C67x DSPs are the floating-point DSP family in the SMJ320C6000 platform. The SMJ320C6701
(’C6701) device is based on the high-performance, advanced VelociTI™ very-long-instruction-word (VLIW)
architecture developed by Texas Instruments (TI), making this DSP an excellent choice for multichannel and
multifunction applications. With performance of up to 1 giga floating-point operations per second (GFLOPS) at a
clock rate of 140 MHz, the ’C6701 offers cost-effective solutions to high-performance DSP programming
challenges. The ’C6701 DSP possesses the operational flexibility of high-speed controllers and the numerical
capability of array processors. This processor has 32 general-purpose registers of 32-bit word length and eight
highly independent functional units. The eight functional units provide four floating-/fixed-point ALUs, two fixedpoint ALUs, and two floating-/fixed-point multipliers. The ’C6701 can produce two multiply-accumulates (MACs)
per cycle for a total of 334 million MACs per second (MMACS). The ’C6701 DSP also has application-specific
hardware logic, on-chip memory, and additional on-chip peripherals.
The ’C6701 includes a large bank of on-chip memory and has a powerful and diverse set of peripherals. Program
memory consists of a 64K-byte block that is user-configurable as cache or memory-mapped program space.
Data memory consists of two 32K-byte blocks of RAM. The peripheral set includes two multichannel buffered
serial ports (McBSPs), two general-purpose timers, a host-port interface (HPI), and a glueless external memory
interface (EMIF) capable of interfacing to SDRAM or SBSRAM and asynchronous peripherals.
The ’C6701 has a complete set of development tools that includes a new C compiler, an assembly optimizer to
simplify programming and scheduling, and a Windows™ debugger interface for visibility into source code
execution.
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SGUS030F – APRIL 2000 – REVISED SEPTEMBER 2013
Device Characteristics
Table 1 provides an overview of the ’C6701 DSP. The table shows significant features of each device, including
the capacity of on-chip RAM, the peripherals, the execution time, and the package type with pin count.
Table 1. Characteristics of 'C6701 Processors
CHARACTERISTICS
DESCRIPTION
Device Number
SMJ320C6701
On–Chip Memory
512K-bit Program Memory
512K-bit Data Memory (organized as 2 blocks)
Peripherals
2 Mutichannel Buffered Serial Ports (McBSP)
2 General-Purpose Timers
Host-Port Interface (HPI)
External Memory Interface (EMIF)
Cycle Time
7 ns at 140 MHz
Package Type
27 mm × 27 mm, 429–Pin BGA (GLP) and 429-Pin LGA (ZMB)
Nominal Voltage
1.9 V Core
3.3 V I/O
Functional and CPU Block Diagram
’C6701 Digital Signal Processor
Program
Bus
SDRAM
SBSRAM
32
SRAM
External Memory
Interface (EMIF)
ROM/FLASH
Internal Program Memory
1 Block Program/Cache
(64K Bytes)
Program
Access/Cache
Controller
I/O Devices
’C67x CPU
(1)
Instruction Fetch
Timer 1
Instruction Dispatch
16
Host Port
Interface
(HPI)
Data Bus
DMA Buses
Multichannel
Buffered Serial
Port 1
Control
Registers
Control
Logic
Instruction Decode
Multichannel
Buffered Serial
Port 0
Framing Chips:
H.100, MVIP,
SCSA, T1, E1
AC97 Devices,
SPI Devices,
Codecs
HOST CONNECTION
MC68360 Glueless
MPC860 Glueless
PCI9050 Bridge + Inverter
MC68302 + PAL
MPC750 + PAL
MPC960 (Jx/Rx) + PAL
Timer 0
Data Path B
A Register File
B Register File
In-Circuit
Emulation
.D2 .M2(1) .S2(1) .L2(1)
Interrupt
Control
.L1(1) .S1(1) .M1(1) .D1
Direct Memory
Access Controller
(DMA)
(4 Channels)
PLL
(x1, x4)
Data Path A
PowerDown
Logic
Data
Access
Controller
Test
Internal Data
Memory
(64K Bytes)
2 Blocks of 8 Banks
Each
These functional units execute floating-point instructions.
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CPU Description
The CPU fetches VelociTI advanced very-long instruction words (VLIW) (256 bits wide) to supply up to eight 32bit instructions to the eight functional units during every clock cycle. The VelociTI VLIW architecture features
controls by which all eight units do not have to be supplied with instructions if they are not ready to execute. The
first bit of every 32-bit instruction determines if the next instruction belongs to the same execute packet as the
previous instruction, or whether it should be executed in the following clock as a part of the next execute packet.
Fetch packets are always 256 bits wide; however, the execute packets can vary in size. The variable-length
execute packets are a key memory-saving feature, distinguishing the ’C67x CPU from other VLIW architectures.
The CPU features two sets of functional units. Each set contains four units and a register file. One set contains
functional units .L1, .S1, .M1, and .D1; the other set contains units .D2, .M2, .S2, and .L2. The two register files
contain 16 32-bit registers each for the total of 32 general-purpose registers. The two sets of functional units,
along with two register files, compose sides A and B of the CPU (see the functional and CPU block diagram and
Figure 1). The four functional units on each side of the CPU can freely share the 16 registers belonging to that
side. Additionally, each side features a single data bus connected to all registers on the other side, by which the
two sets of functional units can access data from the register files on opposite sides. While register access by
functional units on the same side of the CPU as the register file can service all the units in a single clock cycle,
register access using the register file across the CPU supports one read and one write per cycle.
The ’C67x CPU executes all ’C62x instructions. In addition to ’C62x fixed-point instructions, the six out of eight
functional units (.L1, .M1, .D1, .D2, .M2, and .L2) also execute floating-point instructions. The remaining two
functional units (.S1 and .S2) also execute the new LDDW instruction which loads 64 bits per CPU side for a
total of 128 bits per cycle.
Another key feature of the ’C67x CPU is the load/store architecture, where all instructions operate on registers
(as opposed to data in memory). Two sets of data-addressing units (.D1 and .D2) are responsible for all data
transfers between the register files and the memory. The data address driven by the .D units allows data
addresses generated from one register file to be used to load or store data to or from the other register file. The
’C67x CPU supports a variety of indirect-addressing modes using either linear- or circular-addressing modes with
5- or 15-bit offsets. All instructions are conditional, and most can access any one of the 32 registers. Some
registers, however, are singled out to support specific addressing or to hold the condition for conditional
instructions (if the condition is not automatically "true"). The two .M functional units are dedicated for multiplies.
The two .S and .L functional units perform a general set of arithmetic, logical, and branch functions with results
available every clock cycle.
The processing flow begins when a 256-bit-wide instruction fetch packet is fetched from a program memory. The
32-bit instructions destined for the individual functional units are "linked" together by "1" bits in the least
significant bit (LSB) position of the instructions. The instructions that are "chained" together for simultaneous
execution (up to eight in total) compose an execute packet. A "0" in the LSB of an instruction breaks the chain,
effectively placing the instructions that follow it in the next execute packet. If an execute packet crosses the
fetch-packet boundary (256 bits wide), the assembler places it in the next fetch packet, while the remainder of
the current fetch packet is padded with NOP instructions. The number of execute packets within a fetch packet
can vary from one to eight. Execute packets are dispatched to their respective functional units at the rate of one
per clock cycle and the next 256-bit fetch packet is not fetched until all the execute packets from the current fetch
packet have been dispatched. After decoding, the instructions simultaneously drive all active functional units for a
maximum execution rate of eight instructions every clock cycle. While most results are stored in 32-bit registers,
they can be subsequently moved to memory as bytes or half-words as well. All load and store instructions are
byte, half-word, or word addressable.
4
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src1
.L1(1)
src2
dst
long dst
long src
LD1 32 MSB
ST1
8
long src
long dst
dst
(1)
.S1
src1
Data Path A
8
32
8
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LD1 32 LSB
DA1
DA2
LD2 32 LSB
dst
src1
src2
.D1
.D2
dst
src1
src2
1X
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src2
src1
dst
src1
dst
src2
Data Path B
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LD2 32 MSB
ST2
src1
.S2(1) dst
long dst
long src
long src
long dst
dst
.L2(1) src2
src1
(1)
Register
File A
(A0−A15)
2X
src2
.M2(1)
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src2
.M1(1)
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SGUS030F – APRIL 2000 – REVISED SEPTEMBER 2013
Register
File B
(B0−B15)
8
8
8
Á
Á
Á
Á
Á
Á
32
32
8
These functional units execute floating-point instructions.
Control
Register File
Figure 1. SMJ320C67x CPU Data Paths
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Signal Groups Description
CLKIN
CLKOUT2
CLKOUT1
CLKMODE1
CLKMODE0
Boot Mode
BOOTMODE4
BOOTMODE3
BOOTMODE2
BOOTMODE1
BOOTMODE0
Reset and
Interrupts
RESET
NMI
EXT_INT7
EXT_INT6
EXT_INT5
EXT_INT4
IACK
INUM3
INUM2
INUM1
INUM0
Little ENDIAN
Big ENDIAN
LENDIAN
CLOCK/PLL
PLLFREQ3
PLLFREQ2
PLLFREQ1
PLLV
PLLG
PLLF
TMS
TDO
TDI
TCK
TRST
EMU1
EMU0
IEEE Standard
1149.1
(JTAG)
Emulation
RSV9
RSV8
RSV7
RSV6
RSV5
RSV4
RSV3
RSV2
RSV1
RSV0
DMA Status
DMAC3
DMAC2
DMAC1
DMAC0
Power-Down
Status
PD
Reserved
Control/Status
HD[15:0]
16
HCNTL0
HCNTL1
Data
HPI
(Host-Port Interface)
HAS
HR/W
HCS
HDS1
HDS2
HRDY
HINT
Register Select
Control
HHWIL
HBE1
HBE0
Half-Word/Byte
Select
Figure 2. CPU and Peripheral Signals
6
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32
ED[31:0]
Data
CE3
CE2
CE1
CE0
EA[21:2]
Asynchronous
Memory
Control
ARE
AOE
AWE
ARDY
Memory Map
Space Select
20
Word Address
BE3
BE2
BE1
BE0
HOLD
HOLDA
SBSRAM
Control
SSADS
SSOE
SSWE
SSCLK
SDRAM
Control
SDA10
SDRAS
SDCAS
SDWE
SDCLK
Byte Enables
HOLD/
HOLDA
EMIF
(External Memory Interface)
TOUT1
Timer 1
Timer 0
TINP1
TOUT0
TINP0
Timers
McBSP1
McBSP0
CLKX1
FSX1
DX1
Receive
Receive
CLKX0
FSX0
DX0
CLKR1
FSR1
DR1
Transmit
Transmit
CLKR0
FSR0
DR0
CLKS1
Clock
Clock
CLKS0
McBSPs
(Multichannel Buffered Serial Ports)
Figure 3. Peripheral Signals
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Signal Descriptions
SIGNAL
TYPE (1)
DESCRIPTION
NAME
NO.
CLKIN
A14
I
Clock Input
CLKOUT1
Y6
O
Clock output at full device speed
CLKOUT2
V9
O
Clock output at half of device speed
CLKMODE1
B17
CLKMODE0
C17
CLOCK/PLL
Clock mode select
I
•
Selects whether the output clock frequency = input clock freq ×4
or ×1
PLLFREQ3
C13
PLLFREQ2
G11
PLLFREQ1
F11
PLLV (2)
D12
A (3)
PLL analog VCC connection for the low-pass filter
G10
A
(3)
PLL analog GND connection for the low-pass filter
C12
A (3)
PLLG
(2)
PLLF
PLL frequency range (3, 2, and 1)
I
•
The target range for CLKOUT1 frequency is determined by the
3–bit value of the PLLFREQ pins.
PLL low-pass filter connection to external components and a bypass capacitor
JTAG EMULATION
TMS
K19
I
TDO
R12
O/Z
JTAG test port mode select (features an internal pull-up)
TDI
R13
I
JTAG test port data in (features an internal pull-up)
TCK
M20
I
JTAG test port clock
TRST
N18
I
JTAG test port reset (features an internal pull-down)
EMU1
R20
I/O/Z
Emulation pin 1, pullup with a dedicated 20-kΩ resistor (4)
EMU0
T18
I/O/Z
Emulation pin 0, pullup with a dedicated 20-kΩ resistor (4)
RESET
J20
I
NMI
K21
I
EXT_INT7
R16
EXT_INT6
P20
EXT_INT5
R15
EXT_INT4
R18
IACK
R11
INUM3
T19
INUM2
T20
INUM1
T14
INUM0
T16
JTAG test port data out
RESET AND INTERRUPTS
I
O
Device reset
Nonmaskable interrupt
•
Edge driven (rising edge)
External interrupts
•
Edge driven (rising edge)
Interrupt acknowledge for all active interrupts serviced by the CPU
Active interrupt identification number
O
•
•
Valid during IACK for all active interrupts (not just external)
Encoding order follows the interrupt service fetch packet
ordering.
LITTLE ENDIAN/BIG ENDIAN
LENDIAN
G20
I
If high, selects little-endian byte/half-word addressing order within a word.
If low, selects big-endian addressing.
PD
D19
O
Power-down mode 2 or 3 (active if high)
POWER-DOWN STATUS
(1)
(2)
(3)
(4)
8
I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground
PLLV and PLLG signals are not part of external voltage supply or ground. See the CLOCK/PLL documentation for information on how to
connect those pins.
A = Analog signal (PLL filter)
For emulation and normal operation, pull up EMU1 and EMU0 with a dedicated 20-kΩ resistor. For boundary scan, pull down EMU1 and
EMU0 with a dedicated 20-kΩ resistor.
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Signal Descriptions (continued)
SIGNAL
TYPE (1)
DESCRIPTION
NAME
NO.
HINT
H2
O/Z
HCNTL1
J6
I
Host control – selects between control, address or data registers
HCNTL0
H6
I
Host control – selects between control, address or data registers
HHWIL
E4
I
Host halfword select – first or second halfword (not necessarily high or low order)
HBE1
G6
I
Host byte select within word or half-word
HBE0
F6
I
Host byte select within word or half-word
HR/W
D4
I
Host read or write select
HD15
D11
HD14
B11
HD13
A11
HOST-PORT INTERFACE (HPI)
HD12
G9
HD11
D10
HD10
A10
HD9
C10
HD8
B9
HD7
F9
HD6
C9
HD5
A9
HD4
B8
HD3
D9
HD2
D8
HD1
B7
HD0
C7
I/O/Z
Host interrupt (from DSP to host)
Host-port data (used for transfer of data, address and control)
HAS
L6
I
Host address strobe
HCS
C5
I
Host chip select
HDS1
C4
I
Host data strobe 1
HDS2
K6
I
Host data strobe 2
HRDY
H3
O
Host ready (from DSP to host)
BOOT MODE
BOOTMODE4
B16
BOOTMODE3
G14
BOOTMODE2
F15
BOOTMODE1
C18
BOOTMODE0
D17
I
Boot mode
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Signal Descriptions (continued)
SIGNAL
TYPE (1)
DESCRIPTION
NAME
NO.
CE3
Y5
O/Z
CE2
V3
O/Z
CE1
T6
O/Z
CE0
U2
O/Z
BE3
R8
O/Z
Byte enable control
BE2
T3
O/Z
BE1
T2
O/Z
BE0
R2
O/Z
•
•
•
EMIF - CONTROL SIGNALS COMMON TO ALL TYPES OF MEMORY
Memory space enables
•
•
Enabled by bits 24 and 25 of the word address
Only one asserted during any external data access
Decoded from the two lowest bits of the internal address
Byte write enables for most types of memory
Can be directly connected to SDRAM read and write mask signal
(SDQM)
EMIF - ADDRESS
EA21
L4
EA20
L3
EA19
J2
EA18
J1
EA17
K1
EA16
K2
EA15
L2
EA14
L1
EA13
M1
EA12
M2
EA11
M6
EA10
N4
EA9
N1
EA8
N2
EA7
N6
EA6
P4
EA5
P3
EA4
P2
EA3
P1
EA2
P6
10
O/Z
External address (word address)
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Signal Descriptions (continued)
SIGNAL
NAME
NO.
ED31
U18
ED30
U20
TYPE (1)
DESCRIPTION
EMIF - DATA
ED29
T15
ED28
V18
ED27
V17
ED26
V16
ED25
T12
ED24
W17
ED23
T13
ED22
Y17
ED21
T11
ED20
Y16
ED19
W15
ED18
V14
ED17
Y15
ED16
R9
ED15
Y14
ED14
V13
ED13
AA13
ED12
T10
ED11
Y13
ED10
W12
ED9
Y12
ED8
Y11
ED7
V10
ED6
AA10
ED5
Y10
ED4
W10
ED3
Y9
ED2
AA9
I/O/Z
External data
ED1
Y8
ED0
W9
ARE
R7
O/Z
Asynchronous memory read enable
AOE
T7
O/Z
Asynchronous memory output enable
AWE
V5
O/Z
Asynchronous memory write enable
ARDY
R4
I
Asynchronous memory ready input
EMIF - ASYNCHRONOUS MEMORY CONTROL
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Signal Descriptions (continued)
SIGNAL
TYPE (1)
DESCRIPTION
NAME
NO.
SSADS
V8
O/Z
SBSRAM address strobe
SSOE
W7
O/Z
SBSRAM output enable
SSWE
Y7
O/Z
SBSRAM write enable
SSCLK
AA8
O/Z
EMIF - SYNCHRONOUS BURST SRAM CONTROL
SBSRAM clock
EMIF - SYNCHRONOUS DRAM CONTROL
SDA10
V7
SDRAS
V6
O/Z
O/Z
SDRAM address 10 (separate for deactivate command)
SDRAM row address strobe
SDCAS
W5
O/Z
SDRAM column address strobe
SDWE
T8
O/Z
SDRAM write enable
SDCLK
T9
O/Z
SDRAM clock
HOLD
R6
I
Hold request from the host
HOLDA
B15
O
Hold request acknowledge to the host
TOUT1
G2
O/Z
EMIF - BUS ARBITRATION
TIMERS
TINP1
K3
I
TOUT0
M18
O/Z
TINP0
J18
I
Timer 1 or general-purpose output
Timer 1 or general-purpose input
Timer 0 or general-purpose output
Timer 0 or general-purpose input
DMA ACTION COMPLETE
DMAC3
E18
DMAC2
F19
DMAC1
E20
DMAC0
G16
CLKS1
F4
I
CLKR1
H4
I/O/Z
Receive clock
CLKX1
J4
I/O/Z
Transmit clock
DR1
E2
I
Receive data
DX1
G4
O/Z
Transmit data
FSR1
F3
I/O/Z
Receive frame sync
FSX1
F2
I/O/Z
Transmit frame sync
O
DMA action complete
MULTICHANNEL BUFFERED SERIAL PORT 1 (McBSP1)
12
External clock source (as opposed to internal)
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Signal Descriptions (continued)
SIGNAL
TYPE (1)
DESCRIPTION
NAME
NO.
CLKS0
K18
I
CLKR0
L21
I/O/Z
Receive clock
CLKX0
K20
I/O/Z
Transmit clock
DR0
J21
I
Receive data
DX0
M21
O/Z
Transmit data
FSR0
P16
I/O/Z
Receive frame sync
FSX0
N16
I/O/Z
Transmit frame sync
RSV0
N21
I
Reserved for testing, pullup with a dedicated 20-kΩ resistor
RSV1
K16
I
Reserved for testing, pullup with a dedicated 20-kΩ resistor
RSV2
B13
I
Reserved for testing, pullup with a dedicated 20-kΩ resistor
RSV3
B14
I
Reserved for testing, pullup with a dedicated 20-kΩ resistor
MULTICHANNEL BUFFERED SERIAL PORT 0 (McBSP0)
Extended clock source (as opposed to internal)
RESERVED FOR TEST
RSV4
F13
I
Reserved for testing, pulldown with a dedicated 20-kΩ resistor
RSV5
C15
O
Reserved (leave unconnected, do not connect to power or ground)
RSV6
F7
I
Reserved for testing, pullup with a dedicated 20-kΩ resistor
RSV7
D7
I
Reserved for testing, pullup with a dedicated 20-kΩ resistor
RSV8
B5
I
Reserved for testing, pullup with a dedicated 20-kΩ resistor
RSV9
F16
O
Reserved (leave unconnected, do not connect to power or ground)
S
3.3-V supply voltage
C14
C8
E19
E3
H11
H13
H9
J10
J12
J14
DVDD
J19
J3
J8
K11
K13
K15
K7
K9
L10
L12
L14
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Signal Descriptions (continued)
SIGNAL
NAME
NO.
TYPE (1)
DESCRIPTION
SUPPLY VOLTAGE PINS (CONTINUED)
L8
M11
M13
M15
M7
M9
N10
N12
N14
DVDD
N19
S
3.3-V supply voltage
S
1.9-V supply voltage
N3
N8
P11
P13
P9
U19
U3
W14
W8
A12
A13
B10
B12
B6
D15
D16
F10
F14
CVDD
F8
G13
G7
G8
K4
M3
M4
A3
A5
A7
A16
14
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Signal Descriptions (continued)
SIGNAL
NAME
NO.
TYPE (1)
DESCRIPTION
SUPPLY VOLTAGE PINS (CONTINUED)
A18
AA4
AA6
AA15
AA17
AA19
B2
B4
B19
C1
C3
C20
D2
D21
E1
E6
CVDD
E8
E10
S
1.9-V supply voltage
E12
E14
E16
F5
F17
F21
G1
H5
H17
K5
K17
M5
M17
P5
P17
R21
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Signal Descriptions (continued)
SIGNAL
NAME
NO.
TYPE (1)
DESCRIPTION
SUPPLY VOLTAGE PINS (CONTINUED)
T1
T5
T17
U6
U8
U10
U12
U14
U16
U21
V1
V20
W2
W19
W21
Y3
Y18
Y20
CVDD
AA11
S
1.9-V supply voltage
AA12
F20
G18
H16
H18
L18
L19
L20
N20
P18
P19
R10
R14
U4
V11
V12
V15
W13
16
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Signal Descriptions (continued)
SIGNAL
NAME
NO.
TYPE (1)
DESCRIPTION
GROUND PINS
C11
C16
C6
D5
G3
H10
H12
H14
H7
H8
J11
J13
J7
J9
K8
L7
L9
M8
N7
VSS
R3
GND
Ground
A4
A6
A8
A15
A17
A19
AA3
AA5
AA7
AA14
AA16
AA18
B3
B18
B20
C2
C19
C21
D1
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Signal Descriptions (continued)
SIGNAL
NAME
NO.
TYPE (1)
DESCRIPTION
GROUND PINS (CONTINUED)
D20
E5
E7
E9
E11
E13
E15
E17
E21
F1
G5
G17
G21
H1
J5
J17
L5
VSS
L17
GND
Ground pins
N5
N17
P21
R1
R5
R17
T21
U1
U5
U7
U9
U11
U13
U15
U17
V2
V21
18
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Signal Descriptions (continued)
SIGNAL
NAME
NO.
TYPE (1)
DESCRIPTION
GROUND PINS (CONTINUED)
W1
W3
W20
Y2
Y4
Y19
F18
G19
H15
J15
J16
K10
K12
K14
L11
L13
L15
VSS
M10
GND
Ground pins
M12
M14
N11
N13
N15
N9
P10
P12
P14
P15
P7
P8
R19
T4
W11
W16
W6
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Signal Descriptions (continued)
SIGNAL
NAME
NO.
TYPE (1)
DESCRIPTION
REMAINING UNCONNECTED PINS
D13
D14
D18
D3
D6
F12
G12
G15
NC
H19
H20
Unconnected pins
H21
L16
M16
M19
V19
V4
W18
W4
20
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Development Support
Texas Instruments (TI) offers an extensive line of development tools for the ’C6x generation of DSPs, including
tools to evaluate the performance of the processors, generate code, develop algorithm implementations, and fully
integrate and debug software and hardware modules.
The following products support development of ’C6x-based applications:
• Software-development tools
– Assembly optimizer
– Assembler/Linker
– Simulator
– Optimizing ANSI C compiler
– Application algorithms
– C/Assembly debugger and code profiler
• Hardware-development tools
– Extended development system ( XDS™) emulator (supports ’C6x multiprocessor system debug)
– EVM (Evaluation Module)
The TMS320 DSP Development Support Reference Guide (SPRU011) contains information about developmentsupport products for all TMS320 family member devices, including documentation. See this document for further
information on TMS320 documentation or any TMS320 support products from Texas Instruments. An additional
document, the TMS320 Third-Party Support Reference Guide (SPRU052), contains information about TMS320related products from other companies in the industry. To receive TMS320 literature, contact the Literature
Response Center at 800/477-8924.
See Table 2 for a complete listing of development-support tools for the ’C6x. For information on pricing and
availability, contact the nearest TI field sales office or authorized distributor.
Table 2. SMJ320C6x Development-Support Tools
DEVELOPMENT TOOL
PLATFORM
PART NUMBER
Software
Sun Solaris 2.3™ (2)
AD0345AS8500RF – Single user
AD0345BS8500RF – Multi user
C Compiler/Assembler/Linker/Assembly
Optimizer
Win32™
TMDX3246855-07
C Compiler/Assembler/Linker/Assembly
Optimizer
SPARC™ Solaris™
TMDX3246555-07
Win32
TMDS3246851-07
Ada 95 Compiler (1)
Simulator
Simulator
XDS510™ Debugger/Emulation Software
SPARC Solaris
TMDS3246551-07
Win32, Windows NT™
TMDX324016X-07
Hardware
XDS510 Emulator
(3)
XDS510WS™ Emulator (4)
PC
TMDS00510
SCSI
TMDS00510WS
Software/Hardware
EVM Evaluation Kit
PC/Win95/Windows NT
TMDX3260A6201
EVM Evaluation Kit (including TMDX324685507)
PC/Win95/Windows NT
TMDX326006201
(1)
(2)
(3)
(4)
Contact IRVINE Compiler Corporation (949) 250-1366 to order
NT support estimated availability 1Q00
Includes XDS510 board and JTAG emulation cable. TMDX324016X-07 C-source Debugger/Emulation software is not included.
Includes XDS510WS box, SCSI cable, power supply, and JTAG emulation cable.
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Device and Development-Support Tool Nomenclature
To designate the stages in the product-development cycle, TI assigns prefixes to the part numbers of all SMJ320
devices and support tools. Each SMJ320 member has one of three prefixes: SMX, SM, or SMJ. Texas
Instruments recommends two of three possible prefix designators for support tools: TMDX and TMDS. These
prefixes represent evolutionary stages of product development from engineering prototypes (SMX/TMDX)
through fully qualified production devices/tools (SMJ/TMDS).
Device development evolutionary flow:
SMX
Experimental device that is not necessarily representative of the final device’s electrical
specifications
SM
Final silicon die that conforms to the device’s electrical specifications but has not completed
quality and reliability verification
SMJ
Fully qualified production device processed to MIL-PRF-38535
Support tool development evolutionary flow:
TMDX
Development-support product that has not yet completed Texas Instruments internal
qualification testing.
TMDS
Fully qualified development-support product
SMX devices and TMDX development-support tools are shipped against the following disclaimer:
"Developmental product is intended for internal evaluation purposes."
SMJ devices and TMDS development-support tools have been characterized fully, and the quality and reliability
of the device have been demonstrated fully. TI’s standard warranty applies.
Predictions show that prototype devices (SMX or SM) have a greater failure rate than the standard production
devices. Texas Instruments recommends that these devices not be used in any production system because their
expected end-use failure rate still is undefined. Only qualified production devices are to be used.
TI device nomenclature also includes a suffix with the device family name. This suffix indicates the package type
(for example, GLP), the temperature range, and the device speed range in megahertz (for example, 14 is 140
MHz). Figure 4 provides a legend for reading the complete device name for any SMJ320 family member.
22
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SMJ 320
C 6701
GLP
W
14
PREFIX
SMX= Experimental device
SMJ = MIL-PRF-38535, QML
SM = Commercial
processing
DEVICE FAMILY
320 = SMJ320 family
TECHNOLOGY
C = CMOS
-SP
RAD-TOLERANT CLASS V
DEVICE SPEED RANGE
14 = 140 MHz
TEMPERATURE RANGE (DEFAULT: 0°C TO 90°C)
W = -55 °C to 115°C, extended temperature
PACKAGE TYPE (1)
GLP = 429-pin ceramic BGA
ZMB = 429-pin ceramic LGA
DEVICE
’6x DSP:
6201B
6203
6701
(1)
BGA = Ball grid array
Figure 4. SMJ320 Device Nomenclature (Including SMJ320C6701-SP)
Documentation Support
Extensive documentation supports all SMJ320 family generations of devices from product announcement through
applications development. The types of documentation available include: data sheets, such as this document,
with design specifications; complete user’s reference guides for all devices; technical briefs; development-support
tools; and hardware and software applications. The following is a brief, descriptive list of support documentation
specific to the ’C6x devices:
The TMS320C6000 CPU and Instruction Set Reference Guide (literature number SPRU189) describes the
’C6000 CPU architecture, instruction set, pipeline, and associated interrupts.
The TMS320C6000 Peripherals Reference Guide (literature number SPRU190) describes the functionality of the
peripherals available on ’C6x devices, such as the external memory interface (EMIF), host-port interface (HPI),
multichannel buffered serial ports (McBSPs), direct-memory-access (DMA), enhanced direct-memory-access
(EDMA) controller, expansion bus (XB), clocking and phase-locked loop (PLL); and power-down modes. This
guide also includes information on internal data and program memories.
The TMS320C6000 Programmer’s Guide (literature number SPRU198) describes ways to optimize C and
assembly code for ’C6x devices and includes application program examples.
The TMS320C6x C Source Debugger User’s Guide (literature number SPRU188) describes how to invoke the
’C6x simulator and emulator versions of the C source debugger interface and discusses various aspects of the
debugger, including: command entry, code execution, data management, breakpoints, profiling, and analysis.
The TMS320C6x Peripheral Support Library Programmer’s Reference (literature number SPRU273) describes
the contents of the ’C6x peripheral support library of functions and macros. It lists functions and macros both by
header file and alphabetically, provides a complete description of each, and gives code examples to show how
they are used.
TMS320C6000 Assembly Language Tools User’s Guide (literature number SPRU186) describes the assembly
language tools (assembler, linker, and other tools used to develop assembly language code), assembler
directives, macros, common object file format, and symbolic debugging directives for the ’C6000 generation of
devices.
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The TMS320C6x Evaluation Module Reference Guide (literature number SPRU269) provides instructions for
installing and operating the ’C6x evaluation module. It also includes support software documentation, application
programming interfaces, and technical reference material.
TMS320C6000 DSP/BIOS User’s Guide (literature number SPRU303) describes how to use DSP/BIOS tools and
APIs to analyze embedded real-time DSP applications.
Code Composer User’s Guide (literature number SPRU296) explains how to use the Code Composer
development environment to build and debug embedded real-time DSP applications.
Code Composer Studio Tutorial (literature number SPRU301) introduces the Code Composer Studio integrated
development environment and software tools.
The TMS320C6000 Technical Brief (literature number SPRU197) gives an introduction to the ’C62x/C67x
devices, associated development tools, and third-party support.
A series of DSP textbooks is published by Prentice-Hall and John Wiley & Sons to support DSP research and
education. The TMS320 newsletter, Details on Signal Processing, is published quarterly and distributed to update
SMJ320 customers on product information. The TMS320 DSP bulletin board service (BBS) provides access to
information pertaining to the SMJ320 family, including documentation, source code, and object code for many
DSP algorithms and utilities. The BBS can be reached at 281/274-2323.
Information regarding TI DSP products is also available on the Worldwide Web at http://www.ti.com uniform
resource locator (URL).
Clock PLL
All of the internal ’C67x clocks are generated from a single source through the CLKIN pin. This source clock
either drives the PLL, which multiplies the source clock in frequency to generate the internal CPU clock, or
bypasses the PLL to become the internal CPU clock.
To use the PLL to generate the CPU clock, the external PLL filter circuit must be properly designed. Table 3,
Table 4, and Figure 5 show the external PLL circuitry for either x1 (PLL bypass) or x4 PLL multiply modes.
Table 3 and Figure 6 show the external PLL circuitry for a system with ONLY x1 (PLL bypass) mode.
To minimize the clock jitter, a single clean power supply should power both the ’C67x device and the external
clock oscillator circuit. Noise coupling into PLLF will directly impact PLL clock jitter. The minimum CLKIN rise and
fall times should also be observed. For the input clock timing requirements, see the input and output clocks
electricals section. Guidelines for EMI filter selection are as follows: maximum attenuation frequency = 20–30
MHz, maximum dB attenuation = 45–50 dB, and minimum dB attenuation above 30 MHz = 20 dB.
Table 3. CLKOUT1 Frequency Ranges (1)
(1)
PLLFREQ3
(C13)
PLLFREQ2
(G11)
PLLFREQ1
(F11)
CLKOUT1 FREQUENCY RANGE
(MHz)
0
0
0
50-140
Due to overlap of frequency ranges when choosing the PLLFREQ, more than one frequency range can contain the CLKOUT1
frequency. Choose the lowest frequency range that includes the desired frequency. For example, for CLKOUT1 = 133 MHz, choose
PLLFREQ value of 000b. PLLFREQ values other than 000b, 001b, and 010b are reserved.
Table 4. 'C6701 PLL Component Selection Table
(1)
CLKMODE
CLKIN
RANGE
(MHz)
CPU CLOCK
FREQUENCY
(CLKOUT1)
RANGE (MHz)
CLKOUT2 RANGE
(MHz)
R1
(W)
C1
(nF)
C2
(pF)
TYPICAL
LOCK TIME
(μs) (1)
x4
12.5 – 41.7
50-140
25 – 83.5
60.4
27
560
75
Under some operating conditions, the maximum PLL lock time may vary as much as 150% from the specified typical value. For
example, if the typical lock time is specified as 100 μs, the maximum value may be as long as 250 μs.
AVAILABLE MULTIPLY FACTORS
24
CLKMODE1
CLKMODE0
PLL MULTIPLY FACTORS
CPU CLOCK FREQUENCY
F(CPUCLOCK)
0
0
x1(BYPASS)
1 x f(CLKIN)
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AVAILABLE MULTIPLY FACTORS
CLKMODE1
CLKMODE0
PLL MULTIPLY FACTORS
CPU CLOCK FREQUENCY
F(CPUCLOCK)
0
1
Reserved
Reserved
1
0
Reserved
Reserved
1
1
x4
4 x f(CLKIN)
PLLFREQ3
PLLFREQ2
PLLFREQ1
3.3V
See Table 3
EMI Filter
PLLV
C3
10 mF
C4
Internal to ’C6701
PLL
CLKMODE0
CLKMODE1
PLLMULT
PLLCLK
0.1 mF
CLKIN
CLKIN
1
LOOP FILTER
C2
C1
CPU
CLOCK
PLLG
PLLF
0
R1
(1)
Keep the lead length and the number of vias between the PLLF pin, the PLLG pin, and R1, C1, and C2 to a minimum.
In addition, place all PLL external components (R1, C1, C2, C3, C4, and the EMI filter) as close to the ’C6000 device
as possible. For the best performance, TI recommends that all the PLL external components be on a single side of
the board without jumpers, switches, or components other than the ones shown.
(2)
For reduced PLL jitter, maximize the spacing between switching signals and the PLL external components (R1, C1,
C2, C3, C4, and the EMI filter).
(3)
The 3.3-V supply for the EMI filter must be from the same 3.3-V power plane supplying the I/O voltage, DVDD.
Figure 5. External PLL Circuitry for Either PLL ×4 Mode or ×1 (Bypass) Mode
PLLFREQ3
PLLFREQ2
PLLFREQ1
3.3V
See Table 3
PLLV
CLKMODE0
CLKMODE1
Internal to ’C6701
PLLMULT
PLL
PLLCLK
CLKIN
CLKIN
LOOP FILTER
1
CPU
CLOCK
PLLG
PLLF
0
(1)
For a system with ONLY PLL x1 (bypass) mode, short the PLLF terminal to the PLLG terminal.
(2)
The 3.3-V supply for the EMI filter must be from the same 3.3-V power plane supplying the I/O voltage, DVDD.
Figure 6. External PLL Circuitry for ×1 (Bypass) Mode Only
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Power-Supply Sequencing
TI DSPs do not require specific power sequencing between the core supply and the I/O supply. However,
systems should be designed to ensure that neither supply is powered up for extended periods of time if the other
supply is below the proper operating voltage.
System-Level Design Considerations
System-level design considerations, such as bus contention, may require supply sequencing to be implemented.
In this case, the core supply should be powered up at the same time as, or prior to (and powered down after),
the I/O buffers. This is to ensure that the I/O buffers receive valid inputs from the core before the output buffers
are powered up, thus, preventing bus contention with other chips on the board.
Power-Supply Design Considerations
For systems using the C6000™ DSP platform of devices, the core supply may be required to provide in excess
of 2 A per DSP until the I/O supply is powered up. This extra current condition is a result of uninitialized logic
within the DSP(s) and is corrected once the CPU sees an internal clock pulse. With the PLL enabled, as the I/O
supply is powered on, a clock pulse is produced stopping the extra current draw from the supply. With the PLL
disabled, an external clock pulse may be required to stop this extra current draw. A normal current state returns
once the I/O power supply is turned on and the CPU sees a clock pulse. Decreasing the amount of time between
the core supply power up and the I/O supply power up can minimize the effects of this current draw.
A dual-power supply with simultaneous sequencing, such as available with TPS563xx controllers or PT69xx plugin power modules, can be used to eliminate the delay between core and I/O power up [see the Using the
TPS56300 to Power DSPs application report (literature number SLVA088)]. A Schottky diode can also be used to
tie the core rail to the I/O rail, effectively pulling up the I/O power supply to a level that can help initialize the logic
within the DSP.
Core and I/O supply voltage regulators should be located close to the DSP (or DSP array) to minimize
inductance and resistance in the power delivery path. Additionally, when designing for high-performance
applications utilizing the C6000™ platform of DSPs, the PC board should include separate power planes for
core, I/O, and ground, all bypassed with high-quality low-ESL/ESR capacitors.
26
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Absolute Maximum Ratings (1)
over operating free-air temperature range (unless otherwise noted)
MIN
MAX
CVDD
Supply voltage range
(2)
–0.3
2.3
V
DVDD
Supply voltage range (2)
–0.3
4
V
Input voltage range
–0.3
4
V
Output voltage range
–0.3
4
V
TC
Operating case temperature range
Tstg
Storage temperature range
(1)
(2)
S-suffix device
–40
90
W-suffix device
–55
115
–55
150
UNIT
°C
°C
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating
conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
All voltage values are with respect to VSS.
Recommended Operating Conditions
MIN
NOM
MAX
UNIT
CVDD
Supply voltage
1.81
1.9
1.99
V
DVDD
Supply voltage
3.14
3.3
3.46
V
VSS
Supply ground
0
0
0
V
VIH
High-level input voltage
2
VIL
Low-level input voltage
0.8
V
IOH
High-level output current
–12
mA
IOL
Low-level output current
12
mA
TC
Case temperature
V
S-suffix device
–40
90
W-suffix device
–55
115
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Electrical Characteristics
over recommended ranges of supply voltage and operating case temperature (unless otherwise noted) (unchanged after 100
kRad)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
High-level output voltage
DVDD = MIN, IOH = MAX
VOL
Low-level output voltage
DVDD = MIN, IOL = MAX
0.6
V
II
Input current (1)
VI = VSS to DVDD
±10
μA
IOZ
Off-state output current
VO = DVDD or 0 V
±10
μA
IDD2V
Supply current, CPU + CPU memory
access (2)
IDD2V
Supply current, peripherals
IDD3V
Supply current, I/O pins (4)
(3)
2.4
UNIT
VOH
V
CVDD = NOM, CPU clock = 150 MHz
470
mA
CVDD = NOM, CPU clock = 150 MHz
250
mA
DVDD = NOM, CPU clock = 150 MHz
85
mA
(5)
pF
pF
Ci
Input capacitance
15
Co
Output capacitance
15 (5)
(1)
(2)
(3)
(4)
(5)
28
TMS and TDI are not included due to internal pullups.
TRST is not included due to internal pulldown.
Measured with average CPU activity:
50% of time: 8 instructions per cycle, 32-bit DMEM access per cycle
50% of time: 2 instructions per cycle, 16-bit DMEM access per cycle
Measured with average peripheral activity:
50% of time: Timers at max rate, McBSPs at E1 rate, and DMA burst transfer between DMEM and SDRAM
50% of time: Timers at max rate, McBSPs at E1 rate, and DMA servicing McBSPs
Measured with average I/O activity (30-pF load, SDCLK on):
25% of time: Reads from external SDRAM
25% of time: Writes to external SDRAM
50% of time: No activity
This parameter is not tested.
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PARAMETER MEASUREMENT INFORMATION
IOL
Tester Pin
Electronics
50 Ω
Vref
Output
Under
Test
CT = 30 pF(1)
IOH
(1)
Typical distributed load circuit capacitance.
Signal-Transition Levels
All input and output timing parameters are referenced to 1.5 V for both “0” and “1” logic levels.
Vref = 1.5 V
Figure 7. Input and Output Voltage Reference Levels for AC Timing Measurements
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INPUT AND OUTPUT CLOCKS
Timing Requirements for CLKIN (1)
(see Figure 8)
CLKMODE = x4
NO.
1
tc(CLKIN)
Cycle time, CLKIN
2
tw(CLKINH)
Pulse duration,
CLKIN high
0.4C
3
tw(CLKINL)
Pulse duration,
CLKIN low
0.4C (2)
4
(1)
(2)
(3)
MIN
tt(CLKIN)
CLKMODE = x1
MAX
MIN
MAX
UNIT
28.4
7.1
ns
(2) (3)
(2) (3)
ns
0.45C
(3)
0.45C (2)
Transition time, CLKIN
5
(3)
(2)
ns
0.6
(2)
ns
The reference points for the rise and fall transitions ar measured at 20% and 80%, respectively, of VIH.
This parameter is not tested.
C = CLKIN cycle time in ns. For example, when CLKIN frequency is 10 MHz, use C = 100 ns.
1
4
2
CLKIN
3
4
Figure 8. CLKIN Timing
Switching Characteristics for CLKOUT1 (1)
(2)
(see Figure 9)
NO.
1
tc(CKO1)
Cycle time, CLKOUT1
UNIT
MAX
MIN
MAX
P – 0.7 (3)
P + 0.7 (3)
P – 0.7 (3)
P + 0.7 (3)
ns
(3)
(3)
(3)
PH + 0.5 (3)
ns
PL – 0.5 (3)
PL + 0.5 (3)
ns
(3)
ns
tw(CKO1H)
Pulse duration, CLKOUT1 high
(P/2) – 0.5
3
tw(CKO1L)
Pulse duration, CLKOUT1 low
(P/2) – 0.5 (3)
tt(CKO1)
CLKMODE = x1
MIN
2
4
(1)
(2)
(3)
CLKMODE = x4
PARAMETER
(P/2) + 0.5
(P/2) + 0.5 (3)
Transition time, CLKOUT1
0.6
PH – 0.5
(3)
0.6
P = 1/CPU clock frequency in nanoseconds (ns).
PH is the high period of CLKIN in ns and PL is the low period of CLKIN in ns.
This parameter is not tested.
1
4
2
CLKOUT1
3
4
Figure 9. CLKOUT1 Timing
30
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Switching Characteristics for CLKOUT2 (1)
(see Figure 10)
NO.
(1)
(2)
PARAMETER
MIN
MAX
2P – 0.7
(2)
UNIT
2P + 0.7
(2)
ns
1
tc(CKO2)
Cycle time, CLKOUT2
2
tw(CKO2H)
Pulse duration, CLKOUT2 high
P – 0.7 (2)
P + 0.7 (2)
ns
3
tw(CKO2L)
Pulse duration, CLKOUT2 low
P – 0.7 (2)
P + 0.7 (2)
ns
4
tt(CKO2)
Transition time, CLKOUT2
0.6 (2)
ns
P = 1/CPU clock frequency in ns.
This parameter is not tested.
1
4
2
CLKOUT2
3
4
Figure 10. CLKOUT2 Timing
SDCLK, SSCLK Timing Parameter
SDCLK timing parameters are the same as CLKOUT2 parameters.
SSCLK timing parameters are the same as CLKOUT1 or CLKOUT2 parameters, depending on SSCLK
configuration.
Switching Characteristics for the Relation of SSCLK, SDCLK, and CLKOUT2 to CLKOUT1
(see Figure 11)
NO.
PARAMETER
MIN
1
td(CKO1–SSCLK)
Delay time, CLKOUT1 edge to SSCLK edge
2
td(CKO1–SSCLK1/2)
Delay time, CLKOUT1 edge to SSCLK edge (1/2 clock rate)
3
td(CKO1–CKO2)
4
td(CKO1–SDCLK)
MAX
UNIT
–0.8
3.4
ns
–1
3
ns
Delay time, CLKOUT1 edge to CLKOUT2 edge
–1.5
2.5
ns
Delay time, CLKOUT1 edge to SDCLK edge
–1.5
1.9
ns
CLKOUT1
1
SSCLK
2
SSCLK (1/2rate)
3
CLKOUT2
4
SDCLK
Figure 11. Relation of CLKOUT2, SDCLK, and SSCLK to CLKOUT1
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ASYNCHRONOUS MEMORY TIMING
Timing Requirements for Asynchronous Memory Cycles (1)
(see Figure 12 and Figure 13)
NO.
(1)
MIN
MAX
UNIT
6
tsu(EDV–CKO1H)
Setup time, read EDx valid before CLKOUT1 high
4.8
ns
7
th(CKO1H–EDV)
Hold time, read EDx valid after CLKOUT1 high
1.5
ns
10
tsu(ARDY–CKO1H)
Setup time, ARDY valid before CLKOUT1 high
3.5
ns
11
th(CKO1H–ARDY)
Hold time, ARDY valid after CLKOUT1 high
1.5
ns
To ensure data setup time, simply program the strobe width wide enough. ARDY is internally synchronized. If ARDY does meet setup or
hold time, it may be recognized in the current cycle or the next cycle. Thus, ARDY can be an asynchronous input.
Switching Characteristics for Asynchronous Memory Cycles (1)
(see Figure 12 and Figure 13)
NO.
(1)
PARAMETER
MIN
MAX
–1
UNIT
1
td(CKO1H–CEV)
Delay time, CLKOUT1 high to CEx valid
2
td(CKO1H–BEV)
Delay time, CLKOUT1 high to BEx valid
4.5
ns
4.5
3
td(CKO1H–BEIV)
Delay time, CLKOUT1 high to BEx invalid
ns
4
td(CKO1H–EAV)
Delay time, CLKOUT1 high to EAx valid
5
td(CKO1H–EAIV)
Delay time, CLKOUT1 high to EAx invalid
–1
8
td(CKO1H–AOEV)
Delay time, CLKOUT1 high to AOE valid
–1
4.5
ns
9
td(CKO1H–AREV)
Delay time, CLKOUT1 high to ARE valid
–1
4.5
ns
12
td(CKO1H–EDV)
Delay time, CLKOUT1 high to EDx valid
4.5
ns
13
td(CKO1H–EDIV)
Delay time, CLKOUT1 high to EDx invalid
–1
14
td(CKO1H–AWEV)
Delay time, CLKOUT1 high to AWE valid
–1
–1
ns
4.5
ns
ns
ns
4.5
ns
The minimum delay is also the minimum output hold after CLKOUT1 high.
Setup = 2
Not ready = 2
Strobe = 5
HOLD = 1
CLKOUT1
1
1
2
3
4
5
CEx
BE[3:0]
EA[21:2]
7
6
ED[31:0]
8
8
AOE
9
9
ARE
AWE
11
10
11
10
ARDY
Figure 12. Asynchronous Memory Read Timing
32
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Setup = 2
Not ready = 2
Strobe = 5
HOLD = 1
CLKOUT1
1
1
2
3
4
5
CEx
BE[3:0]
EA[21:2]
12
13
ED[31:0]
AOE
ARE
14
14
AWE
11
10
11
10
ARDY
Figure 13. Aysnchronous Memory Write Timing
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SYNCHRONOUS-BURST MEMORY TIMING
Timing Requirements for Synchronous-Burst SRAM Cycles (Full-Rate SSCLK)
(see Figure 14)
NO.
MIN
MAX
UNIT
7
tsu(EDV–SSCLKH)
Setup time, read EDx valid before SSCLK high
2.6
ns
8
th(SSCLKH–EDV)
Hold time, read EDx valid after SSCLK high
1.5
ns
Switching Characteristics for Synchronous-burst SRAM Cycles (1) (Full-Rate SSCLK)
(see Figure 14 and Figure 15)
NO.
(1)
PARAMETER
MIN
MAX
UNIT
1
tosu(CEV–SSCLKH)
Output setup time, CEx valid before SSCLK high
0.5P – 1.5
ns
2
toh(SSCLKH–CEV)
Output hold time, CEx valid after SSCLK high
0.5P – 2.5
ns
3
tosu(BEV–SSCLKH)
Output setup time, BEx valid before SSCLK high
0.5P – 1.6
ns
4
toh(SSCLKH–BEIV)
Output hold time, BEx invalid after SSCLK high
0.5P – 2.5
ns
5
tosu(EAV–SSCLKH)
Output setup time, EAx valid before SSCLK high
0.5P – 1.7
ns
6
toh(SSCLKH–EAIV)
Output hold time, EAx invalid after SSCLK high
0.5P – 2.5
ns
9
tosu(ADSV–SSCLKH)
Output setup time, SSADS valid before SSCLK high
0.5P – 1.5
ns
10
toh(SSCLKH–ADSV)
Output hold time, SSADS valid after SSCLK high
0.5P – 2.5
ns
11
tosu(OEV–SSCLKH)
Output setup time, SSOE valid before SSCLK high
0.5P – 1.5
ns
12
toh(SSCLKH–OEV)
Output hold time, SSOE valid after SSCLK high
0.5P – 2.5
ns
13
tosu(EDV–SSCLKH)
Output setup time, EDx valid before SSCLK high
0.5P – 1.5
ns
14
toh(SSCLKH–EDIV)
Output hold time, EDx invalid after SSCLK high
0.5P – 2.5
ns
15
tosu(WEV–SSCLKH)
Output setup time, SSWE valid before SSCLK high
0.5P – 1.5
ns
16
toh(SSCLKH–WEV)
Output hold time, SSWE valid after SSCLK high
0.5P – 2.5
ns
The effects of internal clock jitter are included at test. There is no need to adjust timing numbers for internal clock jitter. When the PLL is
used (CLKMODE x4), P = 1/CPU clock frequency in ns. For example, when running parts at 140 MHz, use P = 7 ns. For CLKMODE x1,
0.5P is defined as PH (pulse duration of CLKIN high) for all output setup times; 0.5P is defined as PL (pulse duration of CLKIN low) for
all output hold times.
SSCLK
1
2
CEx
3
BE[3:0]
BE1
BE2
BE3
4
BE4
A1
A2
A3
6
A4
5
EA[21:2]
8
7
Q1
ED[31:0]
9
Q2
Q3
Q4
10
SSADS
11
12
SSOE
SSWE
Figure 14. SBSRAM Read Timing (Full-Rate SSCLK)
34
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SSCLK
1
2
CEx
3
BE[3:0]
BE1
BE2
BE3
4
BE4
A1
A2
A3
6
A4
D3
14
D4
5
EA[21:2]
13
ED[31:0]
D1
D2
9
10
15
16
SSADS
SSOE
SSWE
Figure 15. SBSRAM Write Timing (Full-Rate SSCLK)
Timing Requirements for Synchronous-Burst SRAM Cycles (Half-Rate SSCLK)
(seeFigure 16)
NO.
MIN
MAX
UNIT
7
tsu(EDV–SSCLKH)
Setup time, read EDx valid before SSCLK high
3.8
ns
8
th(SSCLKH–EDV)
Hold time, read EDx valid after SSCLK high
1.5
ns
Switching Characteristics for Synchronous-Burst SRAM Cycles (1) (Half-Rate SSCLK)
(see Figure 16 and Figure 17)
NO.
(1)
PARAMETER
MIN
MAX
UNIT
1
tosu(CEV–SSCLKH)
Output setup time, CEx valid before SSCLK high
1.5P – 5.5
ns
2
toh(SSCLKH–CEV)
Output hold time, CEx valid after SSCLK high
0.5P – 2.3
ns
3
tosu(BEV–SSCLKH)
Output setup time, BEx valid before SSCLK high
1.5P – 5.5
ns
4
toh(SSCLKH–BEIV)
Output hold time, BEx invalid after SSCLK high
0.5P – 2.3
ns
5
tosu(EAV–SSCLKH)
Output setup time, EAx valid before SSCLK high
1.5P – 5.5
ns
6
toh(SSCLKH–EAIV)
Output hold time, EAx invalid after SSCLK high
0.5P – 2.3
ns
9
tosu(ADSV–SSCLKH)
Output setup time, SSADS valid before SSCLK high
1.5P – 5.5
ns
10
toh(SSCLKH–ADSV)
Output hold time, SSADS valid after SSCLK high
0.5P – 2.3
ns
11
tosu(OEV–SSCLKH)
Output setup time, SSOE valid before SSCLK high
1.5P – 5.5
ns
12
toh(SSCLKH–OEV)
Output hold time, SSOE valid after SSCLK high
0.5P – 2.3
ns
13
tosu(EDV–SSCLKH)
Output setup time, EDx valid before SSCLK high
1.5P – 5.5
ns
14
toh(SSCLKH–EDIV)
Output hold time, EDx invalid after SSCLK high
0.5P – 2.3
ns
15
tosu(WEV–SSCLKH)
Output setup time, SSWE valid before SSCLK high
1.5P – 5.5
ns
16
toh(SSCLKH–WEV)
Output hold time, SSWE valid after SSCLK high
0.5P – 2.3
ns
The effects of internal clock jitter are included at test. There is no need to adjust timing numbers for internal clock jitter. When the PLL is
used (CLKMODE x4), P = 1/CPU clock frequency in ns. For example, when running parts at 140 MHz, use P = 7 ns.
For CLKMODE x1:
1.5P = P + PH, where P = 1/CPU clock frequency, and PH = pulse duration of CLKIN high.
0.5P = PL, where PL = pulse duration of CLKIN low.
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SSCLK
1
2
CEx
BE[3:0]
3
BE1
BE2
BE3
BE4
4
EA[21:2]
5
A1
A2
A3
A4
6
7
Q1
ED[31:0]
8
Q2
9
Q3
Q4
10
SSADS
11
12
SSOE
SDWE
Figure 16. SBSRAM Read Timing (Half-Rate SSCLK)
SSCLK
1
2
CEx
BE[3:0]
3
BE1
BE2
BE3
BE4
4
EA[21:2]
5
A1
A2
A3
A4
ED[31:0]
Q1
Q2
Q3
Q4
6
13
14
9
10
15
16
SSADS
SSOE
SSWE
Figure 17. SBSRAM Write Timing (Half-Rate SSCLK)
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SYNCHRONOUS DRAM TIMING
Timing Requirements for Synchronous DRAM Cycles
(see Figure 18)
NO.
MIN
MAX
UNIT
7
tsu(EDV–SDCLKH)
Setup time, read EDx valid before SDCLK high
2
ns
8
th(SDCLKH–EDV)
Hold time, read EDx valid after SDCLK high
3
ns
Switching Characteristics for Synchronous DRAM Cycles (1)
(see Figure 18 – Figure 23)
NO.
(1)
PARAMETER
1
tosu(CEV–SDCLKH)
Output setup time, CEx valid before SDCLK high
2
toh(SDCLKH–CEV)
Output hold time, CEx valid after SDCLK high
3
tosu(BEV–SDCLKH)
Output setup time, BEx valid before SDCLK high
4
toh(SDCLKH–BEIV)
Output hold time, BEx invalid after SDCLK high
5
tosu(EAV–SDCLKH)
Output setup time, EAx valid before SDCLK high
6
toh(SDCLKH–EAIV)
Output hold time, EAx invalid after SDCLK high
9
tosu(SDCAS–SDCLKH)
Output setup time, SDCAS valid before SDCLK high
10
toh(SDCLKH–SDCAS)
11
tosu(EDV–SDCLKH)
12
toh(SDCLKH–EDIV)
Output hold time, EDx invalid after SDCLK high
13
tosu(SDWE–SDCLKH)
Output setup time, SDWE valid before SDCLK high
14
toh(SDCLKH–SDWE)
Output hold time, SDWE valid after SDCLK high
15
tosu(SDA10V–SDCLKH)
Output setup time, SDA10 valid before SDCLK high
16
toh(SDCLKH–SDA10IV)
Output hold time, SDA10 invalid after SDCLK high
17
tosu(SDRAS–SDCLKH)
Output setup time, SDRAS valid before SDCLK high
18
toh(SDCLKH–SDRAS)
Output hold time, SDRAS valid after SDCLK high
MIN
MAX
UNIT
1.5P – 5
ns
0.5P – 1.9
ns
1.5P – 5
ns
0.5P – 1.9
ns
1.5P – 5
ns
0.5P – 1.9
ns
1.5P – 5
ns
Output hold time, SDCAS valid after SDCLK high
0.5P – 1.9
ns
Output setup time, EDx valid before SDCLK high
1.5P – 5
ns
0.5P – 1.9
ns
1.5P – 5
ns
0.5P – 1.9
ns
1.5P – 5
ns
0.5P – 1.9
ns
1.5P – 5
ns
0.5P – 1.9
ns
The effects of internal clock jitter are included at test. There is no need to adjust timing numbers for internal clock jitter. When the PLL is
used (CLKMODE x4), P = 1/CPU clock frequency in ns. For example, when running parts at 140 MHz, use P = 7 ns.
For CLKMODE x1:
1.5P = P + PH, where P = 1/CPU clock frequency, and PH = pulse duration of CLKIN high.
0.5P = PL, where PL = pulse duration of CLKIN low.
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READ
READ
READ
SDCLK
1
2
CEx
3
BE[3:0]
5
EA[15:2]
4
BE1
BE2
CA2
CA3
BE3
6
CA1
7
8
D1
ED[31:0]
15
16
9
10
D2
D3
SDA10
SDRAS
SDCAS
SDWE
Figure 18. Three SDRAM Read Commands
WRITE
WRITE
WRITE
SDCLK
1
2
CEx
3
4
BE1
BE[3:0]
5
EA[15:2]
BE3
CA2
CA3
D2
D3
6
CA1
11
D1
ED[31:0]
BE2
12
15
16
9
10
13
14
SDA10
SDRAS
SDCAS
SDWE
Figure 19. Three SDRAM Write Commands
38
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ACTV
SDCLK
1
2
CEx
BE[3:0]
5
Bank Activate/Row Address
EA[15:2]
ED[31:0]
15
Row Address
SDA10
17
18
SDRAS
SDCAS
SDWE
Figure 20. SDRAM ACTV Command
DCAB
SDCLK
1
2
15
16
17
18
CEx
BE[3:0]
EA[15:2]
ED[31:0]
SDA10
SDRAS
SDCAS
13
14
SDWE
Figure 21. SDRAM DCAB Command
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REFR
SDCLK
1
2
CEx
BE[3:0]
EA[15:2]
ED[31:0]
SDA10
17
18
SDRAS
9
10
SDCAS
SDWE
Figure 22. SDRAM REFR Command
MRS
SDCLK
1
2
5
6
CEx
BE[3:0]
EA[15:2]
MRS Value
ED[31:0]
SDA10
17
18
9
10
13
14
SDRAS
SDCAS
SDWE
Figure 23. SDRAM MRS Command
40
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SGUS030F – APRIL 2000 – REVISED SEPTEMBER 2013
HOLD/HOLDA TIMING
Timing Requirements for the Hold/Hold Acknowledge Cycles (1)
(see Figure 24)
NO.
(1)
MIN
MAX
UNIT
1
tsu(HOLDH–CKO1H)
Setup time, HOLD high before CLKOUT1 high
5
ns
2
th(CKO1H–HOLDL)
Hold time, HOLD low after CLKOUT1 high
2
ns
HOLD is synchronized internally. Therefore, if setup and hold times are not met, it will either be recognized in the current cycle or in the
next cycle. Thus, HOLD can be an asynchronous input.
Switching Characteristics for the Hold/Hold Acknowledge Cycles (1)
(seeFigure 24)
NO.
PARAMETER
tR(HOLDL–EMHZ)
Response time, HOLD low to EMIF high impedance
4
tR(EMHZ–HOLDAL)
Response time, EMIF high impedance to HOLDA low
5
tR(HOLDH–HOLDAH)
Response time, HOLD high to HOLDA high
6
td(CKO1H–HOLDAL)
Delay time, CLKOUT1 high to HOLDA valid
7
td(CKO1H–BHZ)
8
9
(1)
(2)
(3)
(4)
MIN
3
MAX
UNIT
(2)
4P
ns
2P
ns
4P
7P
ns
1
8
ns
Delay time, CLKOUT1 high to EMIF Bus high impedance (3)
1 (4)
8 (4)
ns
td(CKO1H–BLZ)
Delay time, CLKOUT1 high to EMIF Bus low impedance (3)
1 (4)
12 (4)
ns
tR(HOLDH–BLZ)
(3)
3P
6P
ns
Response time, HOLD high to EMIF Bus low impedance
P = 1/CPU clock frequency in ns. For example, when running parts at 140 MHz, use P = 7 ns.
All pending EMIF transactions are allowed to complete before HOLDA is asserted. The worst cases for this is an asynchronous read or
write with external ARDY used or a minimum of eight consecutive SDRAM reads or writes when RBTR8 = 1. If no bus transactions are
occurring, then the minimum delay time can be achieved. Also, bus hold can be indefinitely delayed by setting the NOHOLD = 1.
EMIF Bus consists of CE[3:0], BE[3:0], ED[31:0], EA[21:2], ARE, AOE, AWE, SSADS, SSOE, SSWE, SDA10, SDRAS, SDCAS, and
SDWE.
This parameter is not tested.
DSP Owns Bus
External Requester
DSP Owns Bus
5
4
9
3
CLKOUT1
2
2
1
1
HOLD
6
6
HOLDA
7
8
EMIF Bus(1)
(1)
’C6701
Ext Req
’C6701
EMIF bus consists of CE[3:0], BE[3:0], ED[31:0], EA[21:2], ARE, AOE, AWE, SSADS, SSOE, SSWE, SDA10,
SDRAS, SDCAS, and SDWE.
Figure 24. HOLD/HOLDA Timing
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RESET TIMING
Timing Requirements for Reset
(see Figure 25)
NO.
1
MIN
tw(RESET)
(1)
(2)
(3)
UNIT
10 (2)
CLKOUT
1
cycles
250 (2)
μs
Width of the RESET pulse (PLL stable) (1)
Width of the RESET pulse (PLL needs to sync up) (3)
MAX
This parameter applies to CLKMODE x1 when CLKIN is stable and applies to CLKMODE x4 when CLKIN and PLL are stable.
This parameter is not tested.
This parameter only applies to CLKMODE x4. The RESET signal is not connected internally to the clock PLL circuit. The PLL, however,
may need up to 250 μs to stabilize following device powerup or after PLL configuration has been changed. During that time, RESET
must be asserted to ensure proper device operation. See the clock PLL section for PLL lock times.
Switching Characteristics During Reset (1)
(see Figure 25)
NO.
(1)
(2)
42
PARAMETER
2
tR(RESET)
Response time to change of value in RESET signal
3
td(CKO1H–CKO2IV)
Delay time, CLKOUT1 high to CLKOUT2 invalid
4
td(CKO1H–CKO2V)
Delay time, CLKOUT1 high to CLKOUT2 valid
5
td(CKO1H–SDCLKIV)
Delay time, CLKOUT1 high to SDCLK invalid
6
td(CKO1H–SDCLKV)
Delay time, CLKOUT1 high to SDCLK valid
7
td(CKO1H–SSCKIV)
Delay time, CLKOUT1 high to SSCLK invalid
8
td(CKO1H–SSCKV)
Delay time, CLKOUT1 high to SSCLK valid
9
td(CKO1H–LOWIV)
Delay time, CLKOUT1 high to low group invalid
10
td(CKO1H–LOWV)
Delay time, CLKOUT1 high to low group valid
11
td(CKO1H–HIGHIV)
Delay time, CLKOUT1 high to high group invalid
12
td(CKO1H–HIGHV)
Delay time, CLKOUT1 high to high group valid
MIN
MAX
UNIT
CLKOUT1
cycles
1 (2)
–1 (2)
ns
10 (2)
–1 (2)
ns
10
(2)
–1 (2)
(2)
–1 (2)
td(CKO1H–ZHZ)
Delay time, CLKOUT1 high to Z group high impedance
td(CKO1H–ZV)
Delay time, CLKOUT1 high to Z group valid
–1
ns
ns
10 (2)
14
ns
ns
10 (2)
13
ns
ns
10 (2)
–1
ns
(2)
ns
ns
10 (2)
ns
Low group consists of: IACK, INUM[3:0], DMAC[3:0], PD, TOUT0, and TOUT1.
High group consists of: HRDY and HINT.
Z group consists of: EA[21:2], ED[31:0], CE[3:0], BE[3:0], ARE, AWE, AOE, SSADS, SSOE, SSWE, SDA10, SDRAS, SDCAS, SDWE,
HD[15:0], CLKX0, CLKX1, FSX0, FSX1, DX0, DX1, CLKR0, CLKR1, FSR0, and FSR1.
This parameter is not tested
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CLKOUT1
1
2
2
RESET
3
4
5
6
7
8
9
10
11
12
13
14
CLKOUT2
SDCLK
SSCLK
LOW GROUP(1)
HIGH GROUP(1)
Z GROUP(1)
(1)
Low
group
consists
of
IACK,
INUM[3:0],
DMAC[3:0],
PD,
TOUT0,
and
TOUT1.
High
group
consists
of
HRDY
and
HINT.
Z group consists of EA[21:2], ED[31:0], CE[3:0], BE[3:0], ARE, AWE, AOE, SSADS, SSOE, SSWE, SDA10, SDRAS,
SDCAS, SDWE, HD[15:0], CLKX0, CLKX1, FSX0, FSX1, DX0, DX1, CLKR0, CLKR1, FSR0, and FSR1.
Figure 25. Reset Timing
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EXTERNAL INTERRUPT/RESET TIMING
Timing Requirements for Interrupt Response Cycles (1)
(2)
(see Figure 26)
NO.
2
3
(1)
(2)
(3)
MIN
tw(ILOW)
Width of the interrupt pulse low
tw(IHIGH)
Width of the interrupt pulse high
MAX
UNIT
2P (3)
ns
(3)
ns
2P
Interrupt signals are synchronized internally and are potentially recognized one cycle later if setup and hold times are violated. Thus,
they can be connected to asynchronous inputs.
P = 1/CPU clock frequency in ns. For example, when running parts at 140 MHz, use P = 7 ns.
This parameter is not tested.
Switching Characteristics During Interrupt Response Cycles (1)
(see Figure 26)
NO.
(1)
PARAMETER
1
tR(EINTH–IACKH)
Response time, EXT_INTx high to IACK high
4
td(CKO2L–IACKV)
Delay time, CLKOUT2 low to IACK valid
5
td(CKO2L–INUMV)
Delay time, CLKOUT2 low to INUMx valid
6
td(CKO2L–INUMIV)
Delay time, CLKOUT2 low to INUMx invalid
MIN
MAX
UNIT
9P
–0.5P
ns
13 – 0.5P
ns
10 – 0.5P
ns
–0.5P
ns
P = 1/CPU clock frequency in ns. For example, when running parts at 140 MHz, use P = 7 ns.
When the PLL is used (CLKMODE x4), 0.5P = 1/(2 x CPU clock frequency).
For CLKMODE x1: 0.5P = PH, where PH is the high period of CLKIN.
1
CLKOUT2
2
3
EXT_INTx, NMI
Intr Flag
4
4
IACK
6
5
INUMx
Interrupt Number
Figure 26. Interrupt Timing
44
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SGUS030F – APRIL 2000 – REVISED SEPTEMBER 2013
HOST-PORT INTERFACE TIMING
Timing Requirements for Host-Port Interface Cycles (1)
(2)
(see Figure 27, Figure 28, Figure 29, and Figure 30)
NO.
1
(3)
(4)
Setup time, select signals (3) valid before HSTROBE low
(3)
UNIT
ns
th(HSTBL–SEL)
Hold time, select signals
2
ns
3
tw(HSTBL)
Pulse duration, HSTROBE low
2P (4)
ns
4
tw(HSTBH)
Pulse duration, HSTROBE high between consecutive accesses
2P (4)
ns
10
tsu(SEL–HASL)
Setup time, select signals (3) valid before HAS low
4
ns
(3)
valid after HSTROBE low
MAX
4
2
11
th(HASL–SEL)
Hold time, select signals
2
ns
12
tsu(HDV–HSTBH)
Setup time, host data valid before HSTROBE high
3
ns
13
th(HSTBH–HDV)
Hold time, host data valid after HSTROBE high
2
ns
14
th(HRDYL–HSTBL)
Hold time, HSTROBE low after HRDY low. HSTROBE should
not be inactivated until HRDY is active (low); otherwise, HPI
writes will not complete properly.
1 (4)
ns
18
tsu(HASL–HSTBL)
Setup time, HAS low before HSTROBE low
2 (4)
ns
(4)
ns
19
(1)
(2)
MIN
tsu(SEL–HSTBL)
th(HSTBL–HASL)
valid after HAS low
Hold time, HAS low after HSTROBE low
2
HSTROBE refers to the following logical operation on HCS, HDS1, and HDS2: [NOT(HDS1 XOR HDS2)] OR HCS.
The effects of internal clock jitter are included at test. There is no need to adjust timing numbers for internal clock jitter. P = 1/CPU clock
frequency in ns. For example, when running parts at 140 MHz, use P = 7 ns.
Select signals include: HCNTRL[1:0], HR/W, and HHWIL.
This parameter is not tested.
Switching Characteristics During Host-Port Interface Cycles (1)
(2)
(see Figure 27, Figure 28, Figure 29, and Figure 30)
NO.
(1)
(2)
(3)
(4)
(5)
(6)
PARAMETER
MIN
(3)
5
td(HCS–HRDY)
Delay time, HCS to HRDY
6
td(HSTBL–HRDYH)
Delay time, HSTROBE low to HRDY high (4)
7
toh(HSTBL–HDLZ)
Output hold time, HD low impedance after HSTROBE low for an
HPI read
8
td(HDV–HRDYL)
Delay time, HD valid to HRDY low
9
toh(HSTBH–HDV)
Output hold time, HD valid after HSTROBE high
MAX
UNIT
1
12
ns
1
12
ns
4 (5)
P–3
3
(5)
ns
(5)
ns
3
12
ns
(5)
(5)
ns
P+3
15
td(HSTBH–HDHZ)
Delay time, HSTROBE high to HD high impedance
16
td(HSTBL–HDV)
Delay time, HSTROBE low to HD valid
3
12
12
ns
17
td(HSTBH–HRDYH)
Delay time, HSTROBE high to HRDY high (6)
1
12
ns
HSTROBE refers to the following logical operation on HCS, HDS1, and HDS2: [NOT(HDS1 XOR HDS2)] OR HCS.
The effects of internal clock jitter are included at test. There is no need to adjust timing numbers for internal clock jitter. P = 1/CPU clock
frequency in ns. For example, when running parts at 140 MHz, use P = 7 ns.
HCS enables HRDY, and HRDY is always low when HCS is high. The case where HRDY goes high when HCS falls indicates that HPI
is busy completing a previous HPID write or READ with autoincrement.
This parameter is used during an HPID read. At the beginning of the first half–word transfer on the falling edge of HSTROBE, the HPI
sends the request to the DMA auxiliary channel, and HRDY remains high until the DMA auxiliary channel loads the requested data into
HPID.
This parameter is not tested.
This parameter is used after the second half-word of an HPID write or autoincrement read. HRDY remains low if the access is not an
HPID write or autoincrement read. Reading or writing to HPIC or HPIA does not affect the HRDY signal.
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HAS
1
1
2
2
HCNTL[1:0]
1
1
2
2
HR/W
1
1
2
2
HHWIL
4
3
HSTROBE(1)
HCS
15
9
7
15
9
16
HD[15:0] (output)
1st half-word
5
2nd half-word
8
17
5
HRDY (case 1)
6
8
17
5
HRDY (case 2)
(1)
HSTROBE refers to the following logical operation on HCS, HDS1, and HDS2: [NOT(HDS1 XOR HDS2)] OR HCS.
Figure 27. HPI Read Timing (HAS Not Used, Tied High)
HAS
19
11
19
10
11
10
HCNTL[1:0]
11
11
10
10
HR/W
11
11
10
10
HHWIL
4
3
HSTROBE(1)
18
18
HCS
15
7
9
15
16
9
HD[15:0] (output)
1st half-word
5
8
2nd half-word
17
5
17
5
HRDY (case 1)
6
8
HRDY (case 2)
(1)
HSTROBE refers to the following logical operation on HCS, HDS1, and HDS2: [NOT(HDS1 XOR HDS2)] OR HCS.
Figure 28. HPI Read Timing (HAS Used)
46
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HAS
1
1
2
2
HCNTL[1:0]
12
12
13
13
HBE[1:0]
1
1
2
2
HR/W
1
1
2
2
HHWIL
3
4
14
HSTROBE(1)
HCS
12
12
13
13
HD[15:0] (input)
1st half-word
5
17
2nd half-word
5
HRDY
(1)
HSTROBE refers to the following logical operation on HCS, HDS1, and HDS2: [NOT(HDS1 XOR HDS2)] OR HCS.
Figure 29. HPI Write Timing (HAS Not Used, Tied High)
HAS
12
19
13
12
19
13
HBE[1:0]
11
11
10
10
HCNTL[1:0]
11
11
10
10
HR/W
11
11
10
10
HHWIL
3
14
HSTROBE(1)
4
18
18
HCS
12
12
13
13
HD[15:0] (input)
1st half-word
5
2nd half-word
17
5
HRDY
(1)
HSTROBE refers to the following logical operation on HCS, HDS1, and HDS2: [NOT(HDS1 XOR HDS2)] OR HCS.
Figure 30. HPI Write Timing (HAS Used)
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MULTICHANNEL BUFFERED SERIAL PORT TIMING
Timing Requirements for McBSP (1)
(2)
(see Figure 31)
NO.
2
3
(1)
(2)
(3)
48
MIN
tc(CKRX)
tw(CKRX)
Cycle time, CLKR/X
Pulse duration, CLKR/X high or CLKR/X low
5
tsu(FRH–CKRL)
Setup time, external FSR high before CLKR low
6
th(CKRL–FRH)
Hold time, external FSR high after CLKR low
7
tsu(DRV–CKRL)
Setup time, DR valid before CLKR low
8
th(CKRL–DRV)
Hold time, DR valid after CLKR low
10
tsu(FXH–CKXL)
Setup time, external FSX high before CLKX low
11
th(CKXL–FXH)
Hold time, external FSX high after CLKX low
MAX
UNIT
CLKR/X ext
2P (3)
ns
CLKR/X ext
(3)
ns
P–1
CLKR int
13 (3)
CLKR ext
4
CLKR int
7 (3)
CLKR ext
4
CLKR int
10
CLKR ext
1
CLKR int
4
CLKR ext
4
CLKX int
13 (3)
CLKX ext
4
CLKX int
7 (3)
CLKX ext
3
ns
ns
ns
ns
ns
ns
P = 1/CPU clock frequency in ns. For example, when running parts at 140 MHz, use P = 7 ns.
CLKRP = CLKXP = FSRP = FSXP = 0 in the pin control register (PCR). If polarity of any of the signals is inverted, then the timing
references of that signal are also inverted.
This parameter is not tested.
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Switching Characteristics for McBSP (1)
(2) (3)
(see Figure 31)
NO.
(2)
(3)
(4)
(5)
MIN
MAX
UNIT
1
td(CKSH–CKRXH)
Delay time, CLKS high to CLKR/X high for internal
CLKR/X generated from CLKS input
2
tc(CKRX)
Cycle time, CLKR/X
CLKR/X
int
2P
3
tw(CKRX)
Pulse duration, CLKR/X high or CLKR/X low
CLKR/X
int
C – 1 (4)
C + 1 (4)
ns
4
td(CKRH–FRV)
Delay time, CLKR high to internal FSR valid
CLKR int
–4
4
ns
CLKX int
–4
5
CLKX ext
3 (5)
16 (5)
CLKX int
–3 (5)
2 (5)
CLKX ext
2 (5)
9 (5)
CLKX int
–2
4
CLKX ext
3
16
FSX int
–2 (5)
4 (5)
FSX ext
2 (5)
10 (5)
9
td(CKXH–FXV)
Delay time, CLKX high to internal FSX valid
12
tdis(CKXH–DXHZ)
Disable time, DX high impedance following last data bit
from CLKX high
13
td(CKXH–DXV)
Delay time, CLKX high to DX valid.
td(FXH–DXV)
Delay time, FSX high to DX valid.
ONLY applies when in data delay 0 (XDATDLY = 00b)
mode.
14
(1)
PARAMETER
3
15
ns
ns
ns
ns
ns
ns
CLKRP = CLKXP = FSRP = FSXP = 0 in the pin control register (PCR). If polarity of any of the signals is inverted, then the timing
references of that signal are also inverted.
Minimum delay times also represent minimum output hold times.
P = 1/CPU clock frequency in ns. For example, when running parts at 140 MHz, use P = 7 ns.
C = H or L
S = sample rate generator input clock = P if CLKSM = 1 (P = 1/CPU clock frequency)
= sample rate generator input clock = P_clks if CLKSM = 0 (P_clks = CLKS period)
H = CLKX high pulse width = (CLKGDV/2 + 1) * S if CLKGDV is even
= (CLKGDV + 1)/2 * S if CLKGDV is odd or zero
L = CLKX low pulse width = (CLKGDV/2) * S if CLKGDV is even
= (CLKGDV + 1)/2 * S if CLKGDV is odd or zero
This parameter is not tested.
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CLKS
1
2
3
3
CLKR
4
4
FSR (int)
5
6
FSR (ext)
7
DR
8
Bit(n-1)
(n-2)
(n-3)
2
3
3
CLKX
9
FSX (int)
11
10
FSX (ext)
FSX (XDATDLY=00b)
Bit 0
DX
13
14
13
Bit(n-1)
12
(n-2)
(n-3)
Figure 31. McBSP Timing
Timing Requirements for FSR When GSYNC = 1
(see Figure 32)
NO.
(1)
MIN
MAX
UNIT
1
tsu(FRH–CKSH)
Setup time, FSR high before CLKS high
4 (1)
ns
2
th(CKSH–FRH)
Hold time, FSR high after CLKS high
4 (1)
ns
This parameter is not tested.
CLKS
1
2
FSR external
CLKR/X (no need to resync)
CLKR/X(needs resync)
Figure 32. FSR Timing When GSYNC = 1
50
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Timing Requirements for McBSP as SPI Master or Slave: CLKSTP = 10b, CLKXP = 0 (1)
(2)
(seeFigure 33)
MASTER
NO.
(1)
(2)
MIN
4
tsu(DRV–CKXL)
Setup time, DR valid before CLKX low
5
th(CKXL–DRV)
Hold time, DR valid after CLKX low
SLAVE
MAX
MIN
UNIT
MAX
12
2 – 3P
ns
4
5 + 6P
ns
The effects of internal clock jitter are included at test. There is no need to adjust timing numbers for internal clock jitter. P = 1/CPU clock
frequency in ns. For example, when running parts at 140 MHz, use P = 7 ns.
For all SPI slave modes, CLKG is programmed as 1/2 of the CPU clock by setting CLKSM = CLKGDV = 1.
Switching Characteristics for McBSP as SPI Master or Slave: CLKSTP = 10b, CLKXP=0 (1)
(2)
(see Figure 33)
NO.
(1)
(2)
(3)
(4)
(5)
(6)
MASTER (3)
PARAMETER
SLAVE
MIN
MAX
MIN
MAX
UNIT
1
th(CKXL–FXL)
Hold time, FSX low after CLKX low (4)
T–4
T+4
ns
2
td(FXL–CKXH)
Delay time, FSX low to CLKX high (5)
L–4
L+4
ns
3
td(CKXH–DXV)
Delay time, CLKX high to DX valid
–4
4
6
tdis(CKXL–DXHZ)
Disable time, DX high impedance following last
data�bit from CLKX low
(6)
(6)
7
tdis(FXH–DXHZ)
Disable time, DX high impedance following last
data�bit from FSX high
8
td(FXL–DXV)
Delay time, FSX low to DX valid
L–2
L+3
3P + 1
5P + 17
ns
ns
P + 4 (6)
3P + 17 (6)
ns
2P + 1
4P + 13
ns
The effects of internal clock jitter are included at test. There is no need to adjust timing numbers for internal clock jitter. P = 1/CPU clock
frequency in ns. For example, when running parts at 140 MHz, use P = 7 ns.
For all SPI slave modes, CLKG is programmed as 1/2 of the CPU clock by setting CLKSM = CLKGDV = 1.
S = sample rate generator input clock = P if CLKSM = 1 (P = 1/CPU clock frequency)
= sample rate generator input clock = P_clks if CLKSM = 0 (P_clks = CLKS period)
T = CLKX period = (1 + CLKGDV) * S
H = CLKX high pulse width = (CLKGDV/2 + 1) * S if CLKGDV is even
= (CLKGDV + 1)/2 * S if CLKGDV is odd or zero
L = CLKX low pulse width = (CLKGDV/2) * S if CLKGDV is even
= (CLKGDV + 1)/2 * S if CLKGDV is odd or zero
FSRP = FSXP = 1. As a SPI master, FSX is inverted to provide active-low slave-enable output. As a slave, the active-low signal input on
FSX and FSR is inverted before being used internally.
CLKXM = FSXM = 1, CLKRM = FSRM = 0 for master McBSP
CLKXM = CLKRM = FSXM = FSRM = 0 for slave McBSP
FSX should be low before the rising edge of clock to enable slave devices and then begin a SPI transfer at the rising edge of the master
clock (CLKX).
This parameter is not tested.
CLKX
1
2
FSX
7
6
DX
8
3
Bit 0
Bit(n-1)
4
DR
Bit 0
(n-2)
(n-3)
(n-4)
5
Bit(n-1)
(n-2)
(n-3)
(n-4)
Figure 33. McBSP Timing as SPI Master or Slave: CLKSTP = 10b, CLKXP = 0
Timing Requirements SPI Master or Slave: CLKSTP = 11b, CLKXP = 0 (1)
(1)
(see Figure 34)
(1)
The effects of internal clock jitter are included at test. There is no need to adjust timing numbers for internal clock jitter. P = 1/CPU clock
frequency in ns. For example, when running parts at 140 MHz, use P = 7 ns.
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Timing Requirements SPI Master or Slave: CLKSTP = 11b, CLKXP = 0(1) (1) (continued)
(see Figure 34)
MASTER
NO.
MIN
4
tsu(DRV–CKXH)
Setup time, DR valid before CLKX high
5
th(CKXH–DRV)
Hold time, DR valid after CLKX high
SLAVE
MAX
MIN
MAX
UNIT
12
2 – 3P
ns
4
5 + 6P
ns
Switching Characteristics for McBSP as SPI Master or Slave: CLKSTP = 11b, CLKXP = 0 (1)
(2)
(see Figure 34)
NO.
1
(1)
(2)
(3)
(4)
(5)
(6)
MASTER (3)
PARAMETER
Hold time, FSX low after CLKX low (4)
th(CKXL–FXL)
(5)
2
td(FXL–CKXH)
Delay time, FSX low to CLKX high
3
td(CKXL–DXV)
Delay time, CLKX low to DX valid
6
tdis(CKXL–DXHZ)
Disable time, DX high impedance following last
data bit from CLKX low
7
td(FXL–DXV)
Delay time, FSX low to DX valid
SLAVE
MIN
MAX
L–4
L+4
T–4
T+4
–4
4
–2 (6)
H – 2 (6)
MIN
MAX
UNIT
ns
ns
3P + 1
5P + 17
ns
4 (6) 3P + 4 (6)
5P + 17 (6)
ns
4P + 13
ns
H + 3 (6)
2P + 1
The effects of internal clock jitter are included at test. There is no need to adjust timing numbers for internal clock jitter. P = 1/CPU clock
frequency in ns. For example, when running parts at 140 MHz, use P = 7 ns.
For all SPI slave modes, CLKG is programmed as 1/2 of the CPU clock by setting CLKSM = CLKGDV = 1.
S = sample rate generator input clock = P if CLKSM = 1 (P = 1/CPU clock frequency)
= sample rate generator input clock = P_clks if CLKSM = 0 (P_clks = CLKS period)
T = CLKX period = (1 + CLKGDV) * S
H = CLKX high pulse width = (CLKGDV/2 + 1) * S if CLKGDV is even
= (CLKGDV + 1)/2 * S if CLKGDV is odd or zero
L = CLKX low pulse width = (CLKGDV/2) * S if CLKGDV is even
= (CLKGDV + 1)/2 * S if CLKGDV is odd or zero
FSRP = FSXP = 1. As a SPI master, FSX is inverted to provide active-low slave-enable output. As a slave, the active-low signal input on
FSX and FSR is inverted before being used internally.
CLKXM = FSXM = 1, CLKRM = FSRM = 0 for master McBSP
CLKXM = CLKRM = FSXM = FSRM = 0 for slave McBSP
FSX should be low before the rising edge of clock to enable slave devices and then begin a SPI transfer at the rising edge of the master
clock (CLKX).
This parameter is not tested.
CLKX
1
2
6
Bit 0
7
FSX
DX
3
Bit(n-1)
4
DR
Bit 0
(n-2)
(n-3)
(n-4)
5
Bit(n-1)
(n-2)
(n-3)
(n-4)
Figure 34. McBSP Timing as SPI Master or Slave: CLKSTP = 11b, CLKXP = 0
52
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Timing Requirements for MCBSP as SPI Master or Slave: CLKSTOP = 10b, CLKXP = 1 (1)
(2)
(see Figure 35)
MASTER
NO.
(1)
(2)
MIN
4
tsu(DRV–CKXH)
Setup time, DR valid before CLKX high
5
th(CKXH–DRV)
Hold time, DR valid after CLKX high
SLAVE
MAX
MIN
MAX
UNIT
12
2 – 3P
ns
4
5 + 6P
ns
The effects of internal clock jitter are included at test. There is no need to adjust timing numbers for internal clock jitter. P = 1/CPU clock
frequency in ns. For example, when running parts at 140 MHz, use P = 7 ns.
For all SPI slave modes, CLKG is programmed as 1/2 of the CPU clock by setting CLKSM = CLKGDV = 1.
Switching Characteristics for McBSP as SPI Master or Slave: CLKSTP = 10b, CLKXP = 1 (1)
(2)
(see Figure 35)
NO.
(1)
(2)
(3)
(4)
(5)
(6)
MASTER (3)
PARAMETER
MIN
SLAVE
MAX
MIN
MAX
UNIT
1
th(CKXH–FXL)
Hold time, FSX low after CLKX high (4)
T–4
T+4
ns
2
td(FXL–CKXL)
Delay time, FSX low to CLKX low (5)
H–4
H+4
ns
3
td(CKXL–DXV)
Delay time, CLKX low to DX valid
–4
4
6
tdis(CKXH–DXHZ)
Disable time, DX high impedance following last
data bit from CLKX high
(6)
(6)
7
tdis(FXH–DXHZ)
Disable time, DX high impedance following last
data bit from FSX high
8
td(FXL–DXV)
Delay time, FSX low to DX valid
H–2
H+3
3P + 1
5P + 17
ns
ns
P + 4 (6)
3P + 17 (6)
ns
2P + 1
4P + 13
ns
The effects of internal clock jitter are included at test. There is no need to adjust timing numbers for internal clock jitter. P = 1/CPU clock
frequency in ns. For example, when running parts at 140 MHz, use P = 7 ns.
For all SPI slave modes, CLKG is programmed as 1/2 of the CPU clock by setting CLKSM = CLKGDV = 1.
S = sample rate generator input clock = P if CLKSM = 1 (P = 1/CPU clock frequency)
= sample rate generator input clock = P_clks if CLKSM = 0 (P_clks = CLKS period)
T = CLKX period = (1 + CLKGDV) * S
H = CLKX high pulse width = (CLKGDV/2 + 1) * S if CLKGDV is even
= (CLKGDV + 1)/2 * S if CLKGDV is odd or zero
L = CLKX low pulse width = (CLKGDV/2) * S if CLKGDV is even
= (CLKGDV + 1)/2 * S if CLKGDV is odd or zero
FSRP = FSXP = 1. As a SPI master, FSX is inverted to provide active-low slave-enable output. As a slave, the active-low signal input on
FSX and FSR is inverted before being used internally.
CLKXM = FSXM = 1, CLKRM = FSRM = 0 for master McBSP
CLKXM = CLKRM = FSXM = FSRM = 0 for slave McBSP
FSX should be low before the rising edge of clock to enable slave devices and then begin a SPI transfer at the rising edge of the master
clock (CLKX).
This parameter is not tested.
CLKX
1
2
FSX
7
6
DX
8
3
Bit 0
Bit(n-1)
4
DR
Bit 0
(n-2)
(n-3)
(n-4)
5
Bit(n-1)
(n-2)
(n-3)
(n-4)
Figure 35. McBSP Timing as SPI Master or Slave: CLKSTP = 10b, CLKXP = 1
Timing Requirements for McBSP as SPI Master or Slave: CLKSTOP = 11b, CLKXP = 1 (1)
(2)
(see Figure 36)
(1)
(2)
The effects of internal clock jitter are included at test. There is no need to adjust timing numbers for internal clock jitter. P = 1/CPU clock
frequency in ns. For example, when running parts at 140 MHz, use P = 7 ns.
For all SPI slave modes, CLKG is programmed as 1/2 of the CPU clock by setting CLKSM = CLKGDV = 1.
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Timing Requirements for McBSP as SPI Master or Slave: CLKSTOP = 11b, CLKXP = 1(1) (2)
(continued)
(see Figure 36)
MASTER
NO.
MIN
4
tsu(DRV–CKXL)
Setup time, DR valid before CLKX low
5
th(CKXL–DRV)
Hold time, DR valid after CLKX low
SLAVE
MAX
MIN
MAX
UNIT
12
2 - 3P
ns
4
5 + 6P
ns
Switching Characteristics for McBSP as SPI Master or Slave: CLKSTP = 11b, CLKXP = 1 (1)
(2)
(see Figure 36)
NO.
(1)
(2)
(3)
(4)
(5)
(6)
MASTER (3)
PARAMETER
SLAVE
MIN
MAX
MIN
MAX
UNIT
1
th(CKXH–FXL)
Hold time, FSX low after CLKX high (4)
H–4
H+4
ns
2
td(FXL–CKXL)
Delay time, FSX low to CLKX low (5)
T–4
T+4
ns
3
td(CKXH–DXV)
Delay time, CLKX high to DX valid
–4
4
3P + 1
6
tdis(CKXH–DXHZ)
Disable time, DX high impedance following last
data bit from CLKX high
(6)
(6)
(6)
5P + 17 (6)
ns
7
td(FXL–DXV)
Delay time, FSX low to DX valid
2P + 1
4P + 13
ns
–2
L – 2 (6)
4
3P + 4
L + 3 (6)
5P + 17 ns
The effects of internal clock jitter are included at test. There is no need to adjust timing numbers for internal clock jitter. P = 1/CPU clock
frequency in ns. For example, when running parts at 140 MHz, use P = 7 ns.
For all SPI slave modes, CLKG is programmed as 1/2 of the CPU clock by setting CLKSM = CLKGDV = 1.
S = sample rate generator input clock = P if CLKSM = 1 (P = 1/CPU clock frequency)
= sample rate generator input clock = P_clks if CLKSM = 0 (P_clks = CLKS period)
T = CLKX period = (1 + CLKGDV) * S
H = CLKX high pulse width = (CLKGDV/2 + 1) * S if CLKGDV is even
= (CLKGDV + 1)/2 * S if CLKGDV is odd or zero
L = CLKX low pulse width = (CLKGDV/2) * S if CLKGDV is even
= (CLKGDV + 1)/2 * S if CLKGDV is odd or zero
FSRP = FSXP = 1. As a SPI master, FSX is inverted to provide active-low slave-enable output. As a slave, the active-low signal input on
FSX and FSR is inverted before being used internally.
CLKXM = FSXM = 1, CLKRM = FSRM = 0 for master McBSP
CLKXM = CLKRM = FSXM = FSRM = 0 for slave McBSP
FSX should be low before the rising edge of clock to enable slave devices and then begin a SPI transfer at the rising edge of the master
clock (CLKX).
This parameter is not tested.
CLKX
1
2
FSX
6
DX
7
3
Bit 0
Bit(n-1)
4
DR
Bit 0
(n-2)
(n-3)
(n-4)
5
Bit(n-1)
(n-2)
(n-3)
(n-4)
Figure 36. McBSP Timing as SPI Master or Slave: CLKSTP = 11b, CLKXP = 1
54
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DMAC, TIMER, POWER-DOWN TIMING
Switching Characteristics for DMAC Outputs
(see Figure 37)
NO.
1
PARAMETER
td(CKO1H–DMACV)
MIN
Delay time, CLKOUT1 high to DMAC valid
MAX
2
UNIT
11
ns
CLKOUT1
1
1
DMAC[0:3]
Figure 37. DMAC Timing
Timing Requirements for Timer Inputs (1)
(see Figure 38)
NO.
1
(1)
MIN
tw(TINPH)
Pulse duration, TINP high
MAX
UNIT
2P
ns
P = 1/CPU clock frequency in ns. For example, when running parts at 140 MHz, use P = 7 ns.
Switching Characteristics for Timer Outputs
(see Figure 38)
NO.
2
PARAMETER
td(CKO1H–TOUTV)
MIN
Delay time, CLKOUT1 high to TOUT valid
MAX
1
UNIT
10
ns
CLKOUT1
1
TINP
2
2
TOUT
Figure 38. Timer Timing
Switching Characteristics for Power-Down Outputs
(seeFigure 39)
NO.
1
PARAMETER
td(CKO1H–PDV)
MIN
Delay time, CLKOUT1 high to PD valid
MAX
1
UNIT
9
ns
CLKOUT1
1
1
PD
Figure 39. Power-Down Timing
JTAG TEST-PORT TIMING
Timing Requirements for JTAG Test Port
(see Figure 40)
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Timing Requirements for JTAG Test Port (continued)
(see Figure 40)
NO.
MIN
MAX
UNIT
1
tc(TCK)
Cycle time, TCK
35
ns
3
tsu(TDIV–TCKH)
Setup time, TDI/TMS/TRST valid before TCK high
10
ns
4
th(TCKH–TDIV)
Hold time, TDI/TMS/TRST valid after TCK high
9
ns
Switching Characteristics for JTAG Test Port
(see Figure 40)
NO.
2
(1)
PARAMETER
td(TCKL–TDOV)
MIN
–3 (1)
Delay time, TCK low to TDO valid
MAX
15 (1)
UNIT
ns
This parameter is not tested.
1
TCK
2
2
TDO
4
3
TDI/TMS/TRST
Figure 40. JTAG Test-Port Timing
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PACKAGE OPTION ADDENDUM
www.ti.com
2-Oct-2019
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (°C)
Device Marking
(4/5)
5962-9866101VXA
ACTIVE
CFCBGA
GLP
429
1
TBD
SNPB
N / A for Pkg Type
-55 to 115
5962-9866101VX
A
SMV320C6701GLP
W14
5962-9866102VXA
ACTIVE
CFCBGA
GLP
429
1
TBD
SNPB
N / A for Pkg Type
-55 to 125
5962-9866102VX
A
SMV320C6701GLP
M14
5962-9866102VYC
ACTIVE
FCLGA
ZMB
429
1
TBD
Call TI
N / A for Pkg Type
-55 to 125
5962-9866102VY
C
SMV320C6701ZMB
M14
SMV320C6701GLP/EM
ACTIVE
CFCBGA
GLP
429
1
TBD
SNPB
N / A for Pkg Type
0 to 0
SMV320C6701GLP/EM
EVAL ONLY
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
2-Oct-2019
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
OTHER QUALIFIED VERSIONS OF SMJ320C6701-SP :
• Catalog: SMJ320C6701
NOTE: Qualified Version Definitions:
• Catalog - TI's standard catalog product
Addendum-Page 2
MECHANICAL DATA
MCBG004A – SEPTEMBER 1998 – REVISED JANUARY 2002
GLP (S-CBGA-N429)
CERAMIC BALL GRID ARRAY
27,20
SQ
26,80
25,40 TYP
1,27
1
A1 Corner
1,22
1,00
1,27
AA
Y
W
V
U
T
R
P
N
M
L
K
J
H
G
F
E
D
C
B
A
3
2
5
4
9
7
6
8
11 13 15 17 19 21
10 12 14 16 18 20
Bottom View
3,30 MAX
Seating Plane
0,90
0,60
NOTES: A.
B.
C.
D.
∅ 0,10 M
0,70
0,50
0,15
4164732/B 11/01
All linear dimensions are in millimeters.
This drawing is subject to change without notice.
Falls within JEDEC MO-156
Flip chip application only
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
1
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IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD
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