Texas Instruments | TMS320C6205 Fixed-Point Digital Signal Processor (Rev. G) | Datasheet | Texas Instruments TMS320C6205 Fixed-Point Digital Signal Processor (Rev. G) Datasheet

Texas Instruments TMS320C6205 Fixed-Point Digital Signal Processor (Rev. G) Datasheet
SPRS106G − OCTOBER 1999 − REVISED JULY 2006
High-Performance Fixed-Point Digital
Signal Processor (DSP) − TMS320C6205
− 5-ns Instruction Cycle Time
− 200-MHz Clock Rate
− Eight 32-Bit Instructions/Cycle
− 1600 MIPS
VelociTI Advanced-Very-Long-InstructionWord (VLIW) TMS320C62x DSP Core
− Eight Highly Independent Functional
Units:
− Six ALUs (32-/40-Bit)
− Two 16-Bit Multipliers (32-Bit Result)
− Load-Store Architecture With 32 32-Bit
General-Purpose Registers
− Instruction Packing Reduces Code Size
− All Instructions Conditional
Instruction Set Features
− Byte-Addressable (8-, 16-, 32-Bit Data)
− 8-Bit Overflow Protection
− Saturation
− Bit-Field Extract, Set, Clear
− Bit-Counting
− Normalization
1M-Bit On-Chip SRAM
− 512K-Bit Internal Program/Cache
(16K 32-Bit Instructions)
− 512K-Bit Dual-Access Internal Data
(64K Bytes)
− Organized as Two 32K-Byte Blocks for
Improved Concurrency
32-Bit External Memory Interface (EMIF)
− Glueless Interface to Synchronous
Memories: SDRAM or SBSRAM
− Glueless Interface to Asynchronous
Memories: SRAM and EPROM
− 52M-Byte Addressable External Memory
Space
Four-Channel Bootloading
Direct-Memory-Access (DMA) Controller
With an Auxiliary Channel
Flexible Phase-Locked-Loop (PLL) Clock
Generator
32-Bit/33-MHz
Peripheral
Component
Interconnect (PCI) Master/Slave Interface
Conforms to:
PCI Specification 2.2
Power Management Interface 1.1
Meets Requirements of PC99
− PCI Access to All On-Chip RAM,
Peripherals, and External Memory
(via EMIF)
− Four 8-Deep x 32-Wide FIFOs for
Efficient PCI Bus Data Transfer
− 3.3/5-V PCI Operation
− Three PCI Bus Address Registers:
Prefetchable Memory
Non-Prefetchable Memory I/O
− Supports 4-Wire Serial EEPROM
Interface
− PCI Interrupt Request Under DSP
Program Control
− DSP Interrupt Via PCI I/O Cycle
Two Multichannel Buffered Serial Ports
(McBSPs)
− Direct Interface to T1/E1, MVIP, SCSA
Framers
− ST-Bus-Switching Compatible
− Up to 256 Channels Each
− AC97-Compatible
− Serial-Peripheral-Interface (SPI)
Compatible (Motorola)
Two 32-Bit General-Purpose Timers
IEEE-1149.1 (JTAG†)
Boundary-Scan-Compatible
288-Pin MicroStar BGA Package
(GHK and ZHK Suffixes)
0.15-µm/5-Level Metal Process
− CMOS Technology
3.3-V I/Os, 1.5-V Internal, 5-V Voltage
Tolerance for PCI I/O Pins
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
VelociTI, TMS320C62x, and MicroStar BGA are trademarks of Texas Instruments.
Motorola is a trademark of Motorola, Inc.
† IEEE Standard 1149.1-1990 Standard-Test-Access Port and Boundary Scan Architecture.
Copyright  2006, Texas Instruments Incorporated
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1
SPRS106G − OCTOBER 1999 − REVISED JULY 2006
Table of Contents
2
revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
GHK and ZHK BGA packages (bottom view) . . . . . . . . . . 4
description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
device characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
functional and CPU (DSP core) block diagram . . . . . . . . . 7
CPU (DSP core) description . . . . . . . . . . . . . . . . . . . . . . . . 8
memory map summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
signal groups description . . . . . . . . . . . . . . . . . . . . . . . . . . 11
electrical characteristics over recommended ranges
of supply voltage and operating case
temperature (PCI only) . . . . . . . . . . . . . . . . . . . . . . 34
signal descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
development support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
documentation support . . . . . . . . . . . . . . . . . . . . . . . . . . . .
clock PLL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
power-down mode logic . . . . . . . . . . . . . . . . . . . . . . . . . . .
power-supply sequencing . . . . . . . . . . . . . . . . . . . . . . . . . .
absolute maximum ratings over operating case
temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . .
recommended operating conditions . . . . . . . . . . . . . . . . .
recommended operating conditions (PCI only) . . . . . . . .
electrical characteristics over recommended
rangesof supply voltage and operating
case temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . .
HOLD/HOLDA timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
14
23
26
27
29
32
parameter measurement information . . . . . . . . . . . . . . . 35
input and output clocks . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
asynchronous memory timing . . . . . . . . . . . . . . . . . . . . . 38
synchronous-burst memory timing . . . . . . . . . . . . . . . . . 41
synchronous DRAM timing . . . . . . . . . . . . . . . . . . . . . . . . 43
reset timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
external interrupt timing . . . . . . . . . . . . . . . . . . . . . . . . . . 50
PCI I/O timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
PCI reset timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
PCI serial EEPROM interface timing . . . . . . . . . . . . . . . 53
33
33
33
multichannel buffered serial port timing . . . . . . . . . . . . . 54
DMAC, timer, power-down timing . . . . . . . . . . . . . . . . . . 64
JTAG test-port timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
34
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mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
• HOUSTON, TEXAS 77251−1443
SPRS106G − OCTOBER 1999 − REVISED JULY 2006
REVISION HISTORY
This data sheet revision history highlights the technical changes made to the SPR106E device-specific data
sheet to make it an SPRS106F revision. It also highlights technical changes made to SPRS219F to generate
SPRS219G . These changes are marked by [Revision G] in the Revision History below.
Scope: Applicable updates to the C62x device family, specifically relating to the C6205 device, have been incorporated.
PAGE(S)
NO.
ADDITIONS/CHANGES/DELETIONS
Added information for the ZHK Mechanical Package [Revision G]
Moved Revision History to front of document [Revision G]
6
Device Characteristics, Characteristics of the C6205 Processor table:
Hardware Features, Peripherals:
Updated description for PCI
24
device and development-support tool nomenclature section:
Updated paragraphs and Figure [Revision G]
28
Table 4, C6205 PLL Component Selection Table, Typical Lock Time (µs) section:
Changed “75 MS” to “75 µs” [Revision G]
67−68
Added “Mechanical Data” title and paragraph
Added Package Information section [Revision G]
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3
SPRS106G − OCTOBER 1999 − REVISED JULY 2006
GHK and ZHK BGA packages (bottom view)
GHK and ZHK 288-PIN BALL GRID ARRAY (BGA) PACKAGES
( BOTTOM VIEW )
W
V
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L
K
J
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G
F
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D
C
B
A
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SPRS106G − OCTOBER 1999 − REVISED JULY 2006
description
The TMS320C62x DSPs (including the TMS320C6205 device) compose the fixed-point DSP generation in
the TMS320C6000 DSP platform. The TMS320C6205 (C6205) device is based on the high-performance,
advanced VelociTI very-long-instruction-word (VLIW) architecture developed by Texas Instruments (TI),
making the C6205 an excellent choice for multichannel and multifunction applications.
With performance of up to 1600 million instructions per second (MIPS) at a clock rate of 200 MHz, the C6205
offers cost-effective solutions to high-performance DSP-programming challenges. The C6205 DSP possesses
the operational flexibility of high-speed controllers and the numerical capability of array processors. This
processor has 32 general-purpose registers of 32-bit word length and eight highly independent functional units.
The eight functional units provide six arithmetic logic units (ALUs) for a high degree of parallelism and two 16-bit
multipliers for a 32-bit result. The C6205 can produce two multiply-accumulates (MACs) per cycle for a total of
400 million MACs per second (MMACS). The C6205 DSP also has application-specific hardware logic, on-chip
memory, and additional on-chip peripherals.
The C6205 includes a large bank of on-chip memory and has a powerful and diverse set of peripherals. Program
memory consists of a 64K-byte block that is user-configurable as cache or memory-mapped program space.
Data memory consists of two 32K-byte blocks of RAM. The peripheral set includes two multichannel buffered
serial ports (McBSPs), two general-purpose timers, a peripheral component interconnect (PCI) module that
supports 33-MHz master/slave interface and 4-wire serial EEPROM interface, and a glueless external memory
interface (EMIF) capable of interfacing to SDRAM or SBSRAM and asynchronous peripherals.
The C6205 has a complete set of development tools which includes: a new C compiler, an assembly optimizer
to simplify programming and scheduling, and a Windows debugger interface for visibility into source code
execution.
TMS320C6000 is a trademark of Texas Instruments.
Windows is a registered trademark of Microsoft Corporation.
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5
SPRS106G − OCTOBER 1999 − REVISED JULY 2006
device characteristics
Table 1 provides an overview of the C6205 DSP. The table shows significant features of each device, including
the capacity of on-chip RAM, the peripherals, the execution time, and the package type with pin count, etc.
Table 1. Characteristics of the C6205 Processor
HARDWARE FEATURES
Peripherals
Internal Program Memory
Internal Data Memory
C6205
EMIF
1
DMA
4-Channel With Throughput Enhancements
PCI (Device ID, bits 15:0, A106h [default value])
1
McBSPs
2
32-Bit Timers
2
Size (Bytes)
64K
Organization
1 Block: 64K Bytes Cache/Mapped Program
Size (Bytes)
64K
Organization
2 Blocks: Four 16-Bit Banks per Block, 50/50
Split
CPU ID+Rev ID
Control Status Register (CSR.[31:16])
Frequency
MHz
Cycle Time
ns
Voltage
200
5 ns (C6205-200)
Core (V)
1.5
I/O (V)
3.3
Voltage Tolerance for PCI I/O Pins (V)
PLL Options
CLKIN frequency multiplier
BGA Package
16 x 16 mm
Process Technology
µm
Product Status
Product Preview (PP)
Advance Information (AI)
Production Data (PD)
Device Part Numbers
(For more details on the C6000 DSP part
numbering, see Figure 4)
5.0
Bypass (x1), x4, x6, x7, x8, x9, x10, and x11
288-Pin MicroStar BGA (GHK/ZHK)
0.15 µm
PD
C6000 is a trademark of Texas Instruments.
6
0x0003
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TMX320C6205GHK
TMX320C6205ZHK
SPRS106G − OCTOBER 1999 − REVISED JULY 2006
functional and CPU (DSP core) block diagram
C6205 Digital Signal Processor
SDRAM or
SBSRAM
External Memory
Interface (EMIF)
ROM/FLASH
Internal Program Memory
1 Block Program/Cache
(64K Bytes)
Program
Access/Cache
Controller
32
SRAM
I/O Devices
C62x DSP Core
Timer 0
Instruction Fetch
Timer 1
Instruction Dispatch
Control
Logic
Instruction Decode
Multichannel
Buffered Serial
Port 0
Framing Chips:
H.100, MVIP,
SCSA, T1, E1
AC97 Devices,
SPI Devices,
Codecs
Control
Registers
Multichannel
Buffered Serial
Port 1
Data Path A
Data Path B
A Register File
B Register File
.L1
.S1 .M1 .D1
.D2 .M2
.S2
Test
In-Circuit
Emulation
.L2
DMA Bus
Interrupt
Selector
EEPROM
32
Master/Slave
PCI Interface
Peripheral Control Bus
Direct Memory
Access Controller
(DMA)
(4 Channels)
PLL
(x1, x4, x6, x7, x8,
x9, x10, x11)
POST OFFICE BOX 1443
Interrupt
Control
Internal Data
Memory
(64K Bytes)
2 Blocks of 4 Banks
Each
Data
Access
Controller
PowerDown
Logic
Boot Configuration
• HOUSTON, TEXAS 77251−1443
7
SPRS106G − OCTOBER 1999 − REVISED JULY 2006
CPU (DSP core) description
The CPU fetches VelociTI advanced very-long instruction words (VLIW) (256 bits wide) to supply up to eight
32-bit instructions to the eight functional units during every clock cycle. The VelociTI VLIW architecture
features controls by which all eight units do not have to be supplied with instructions if they are not ready to
execute. The first bit of every 32-bit instruction determines if the next instruction belongs to the same execute
packet as the previous instruction, or whether it should be executed in the following clock as a part of the next
execute packet. Fetch packets are always 256 bits wide; however, the execute packets can vary in size. The
variable-length execute packets are a key memory-saving feature, distinguishing the C62x CPU from other
VLIW architectures.
The CPU features two sets of functional units. Each set contains four units and a register file. One set contains
functional units .L1, .S1, .M1, and .D1; the other set contains units .D2, .M2, .S2, and .L2. The two register files
each contain 16 32-bit registers for a total of 32 general-purpose registers. The two sets of functional units, along
with two register files, compose sides A and B of the CPU [see the Functional and CPU (DSP Core) Block
Diagram and Figure 1]. The four functional units on each side of the CPU can freely share the 16 registers
belonging to that side. Additionally, each side features a single data bus connected to all the registers on the
other side, by which the two sets of functional units can access data from the register files on the opposite side.
While register access by functional units on the same side of the CPU as the register file can service all the units
in a single clock cycle, register access using the register file across the CPU supports one read and one write
per cycle.
Another key feature of the C62x CPU is the load/store architecture, where all instructions operate on registers
(as opposed to data in memory). Two sets of data-addressing units (.D1 and .D2) are responsible for all data
transfers between the register files and the memory. The data address driven by the .D units allows data
addresses generated from one register file to be used to load or store data to or from the other register file. The
C62x CPU supports a variety of indirect addressing modes using either linear- or circular-addressing modes
with 5- or 15-bit offsets. All instructions are conditional, and most can access any one of the 32 registers. Some
registers, however, are singled out to support specific addressing or to hold the condition for conditional
instructions (if the condition is not automatically “true”). The two .M functional units are dedicated for multiplies.
The two .S and .L functional units perform a general set of arithmetic, logical, and branch functions with results
available every clock cycle.
The processing flow begins when a 256-bit-wide instruction fetch packet is fetched from a program memory.
The 32-bit instructions destined for the individual functional units are “linked” together by “1” bits in the least
significant bit (LSB) position of the instructions. The instructions that are “chained” together for simultaneous
execution (up to eight in total) compose an execute packet. A “0” in the LSB of an instruction breaks the chain,
effectively placing the instructions that follow it in the next execute packet. If an execute packet crosses the
256-bit wide fetch-packet boundary, the assembler places it in the next fetch packet, while the remainder of the
current fetch packet is padded with NOP instructions. The number of execute packets within a fetch packet can
vary from one to eight. Execute packets are dispatched to their respective functional units at the rate of one per
clock cycle and the next 256-bit fetch packet is not fetched until all the execute packets from the current fetch
packet have been dispatched. After decoding, the instructions simultaneously drive all active functional units
for a maximum execution rate of eight instructions every clock cycle. While most results are stored in 32-bit
registers, they can be subsequently moved to memory as bytes or half-words as well. All load and store
instructions are byte-, half-word, or word-addressable.
8
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CPU (DSP core) description (continued)
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src1
src2
.L1
dst
long dst
long src
ST1
Data Path A
long src
long dst
dst
.S1
src1
32
8
dst
src1
LD1
DA1
DA2
.D2
dst
src1
src2
2X
1X
src2
src1
dst
Á
Á
Á
Á
LD2
src2
.M2
src1
dst
src2
Data Path B
src1
.S2
dst
long dst
long src
ST2
long src
long dst
dst
.L2
src2
src1
Register
File A
(A0−A15)
Á
Á
Á
Á
src2
.D1
8
8
src2
.M1
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ÁÁ
Register
File B
(B0−B15)
8
32
8
Á
Á
Á
Á
8
Control
Register
File
Figure 1. TMS320C62x CPU (DSP Core) Data Paths
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SPRS106G − OCTOBER 1999 − REVISED JULY 2006
memory map summary
Table 2 shows the memory map address ranges of the C6205 device. The C6205 device has the capability of
a MAP 0 or MAP 1 memory block configuration. The maps differ in that MAP 0 has external memory mapped
at address 0x0000 0000 and MAP 1 has internal memory mapped at address 0x0000 0000. These memory
block configurations are set up at reset by the boot configuration pins (generically called BOOTMODE[4:0]). For
the C6205 device, the BOOTMODE configuration is handled, at reset, by the expansion bus module (specifically
XD[4:0] pins). For more detailed information on the C6205 device settings, which include the device boot mode
configuration at reset and other device-specific configurations, see TMS320C620x/C670x DSP Boot Modes
and Configuration (literature number SPRU642).
Table 2. TMS320C6205 Memory Map Summary
MEMORY BLOCK DESCRIPTION
BLOCK SIZE
(BYTES)
HEX ADDRESS RANGE
MAP 0
MAP 1
External Memory Interface (EMIF) CE0
Internal Program RAM
64K
0000 0000 – 0000 FFFF
EMIF CE0
Reserved
4M – 64K
0001 0000 – 003F FFFF
EMIF CE0
EMIF CE0
12M
0040 0000 – 00FF FFFF
EMIF CE1
EMIF CE0
4M
0100 0000 – 013F FFFF
Internal Program RAM
EMIF CE1
64K
0140 0000 – 0140 FFFF
EMIF CE1
Reserved
10
4M – 64K
0141 0000 – 017F FFFF
EMIF Registers
256K
0180 0000 – 0183 FFFF
DMA Controller Registers
256K
0184 0000 – 0187 FFFF
Reserved
256K
0188 0000 – 018B FFFF
McBSP 0 Registers
256K
018C 0000 – 018F FFFF
McBSP 1 Registers
256K
0190 0000 – 0193 FFFF
Timer 0 Registers
256K
0194 0000 – 0197 FFFF
Timer 1 Registers
256K
0198 0000 – 019B FFFF
Interrupt Selector Registers
256K
019C 0000 – 019F FFFF
Reserved
256K
01A0 0000 – 01A3 FFFF
PCI Registers
320K
01A4 0000 – 01A8 FFFF
Reserved
6M – 576K
01A9 0000 – 01FF FFFF
EMIF CE2
16M
0200 0000 – 02FF FFFF
EMIF CE3
16M
0300 0000 – 03FF FFFF
Reserved
2G – 64M
0400 0000 – 7FFF FFFF
Internal Data RAM
64K
8000 0000 – 8000 FFFF
Reserved
2G – 64K
8001 0000 – FFFF FFFF
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signal groups description
CLKIN
CLKOUT2
CLKMODE0
PLLV
PLLG
PLLF
TMS
TDO
TDI
TCK
TRST
EMU1
EMU0
Clock/PLL
Reset and
Interrupts
IEEE Standard
1149.1
(JTAG)
Emulation
RESET
NMI
EXT_INT7
EXT_INT6
EXT_INT5
EXT_INT4
IACK
INUM3
INUM2
INUM1
INUM0
DMA Status
DMAC3
DMAC2
DMAC1
DMAC0
Power-Down
Status
PD
RSV11
RSV10
RSV9
RSV8
RSV7
RSV6
RSV5
RSV4
RSV3
RSV2
RSV1
RSV0
Reserved
Control/Status
Figure 2. CPU (DSP Core) Signals
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SPRS106G − OCTOBER 1999 − REVISED JULY 2006
signal groups description (continued)
Asynchronous
Memory
Control
32
ED[31:0]
Data
CE3
CE2
CE1
CE0
EA[21:2]
BE3
BE2
BE1
BE0
TOUT1
TINP1
Memory Map
Space Select
20
Synchronous
Memory
Control
Word Address
HOLD/
HOLDA
Byte Enables
ARE
AOE
AWE
ARDY
SDA10
SDRAS/SSOE
SDCAS/SSADS
SDWE/SSWE
HOLD
HOLDA
EMIF
(External Memory Interface)
Timer 1
Timer 0
TOUT0
TINP0
Timers
McBSP1
McBSP0
CLKX1
FSX1
DX1
Transmit
Transmit
CLKX0
FSX0
DX0
CLKR1
FSR1
DR1
Receive
Receive
CLKR0
FSR0
DR0
CLKS1
Clock
Clock
CLKS0
McBSPs
(Multichannel Buffered Serial Ports)
Figure 3. Peripheral Signals
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signal groups description (continued)
32
AD[31:0]
PCBE3
PCBE2
PCBE1
PCBE0
Data/Address
Command
Byte Enable
Clock
Control
PCLK
PIDSEL
PDEVSEL
PFRAME
PINTA
PPAR
PRST
PIRDY
PSTOP
PTRDY
PGNT
PREQ
PME
3.3VauxDET
PWR_WKP
3.3Vaux
Arbitration
Error
Power
Management
Serial
EEPROM
Control
PSERR
PPERR
XSP_DO
XSP_CS
XSP_CLK
XSP_DI
PCI Interface
Figure 3. Peripheral Signals (Continued)
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Signal Descriptions
SIGNAL
NAME
NO.
TYPE†
DESCRIPTION
CLOCK/PLL
CLKIN
CLKOUT2
J3
I
T19
O
Clock Input
Clock output at half of device speed
Used for synchronous memory interface
Clock mode select 0
Selects whether the on-chip PLL is used or bypassed. For more details, see the Clock PLL section.
CLKMODE0
L3
I
PLLV‡
PLLG‡
K5
PLL analog VCC connection for the low-pass filter
L2
A§
A§
PLLF‡
L1
A§
PLL low-pass filter connection to external components and a bypass capacitor
The PLL Multiply Factor is selected at boot configuration. For more details, see the EMIF − Data
pin descriptions and the clock PLL section.
PLL analog GND connection for the low-pass filter
JTAG EMULATION
TMS
E17
I
TDO
D19
O/Z
JTAG test-port mode select (features an internal pullup)
TDI
D18
I
JTAG test-port data in (features an internal pullup)
TCK
D17
I
JTAG test-port clock
TRST
C19
I
JTAG test-port reset (features an internal pulldown)
EMU1
E18
I/O/Z
EMU0
F15
I/O/Z
RESET
C3
I
NMI
A8
I
EXT_INT7
B15
EXT_INT6
C15
JTAG test-port data out
Emulation pin 1, pullup with a dedicated 20-kΩ resistor¶
Emulation pin 0, pullup with a dedicated 20-kΩ resistor¶
RESET AND INTERRUPTS
EXT_INT5
A16
EXT_INT4
B16
IACK
A15
INUM3
F12
INUM2
A14
INUM1
B14
INUM0
C14
Device reset
Nonmaskable interrupt
Edge-driven (rising edge)
External interrupts
I
O
Edge-driven
Polarity independently selected via the External Interrupt Polarity Register bits (EXTPOL.[3:0])
Interrupt acknowledge for all active interrupts serviced by the CPU
Active interrupt identification number
O
Valid during IACK for all active interrupts (not just external)
Encoding order follows the interrupt-service fetch-packet ordering
POWER-DOWN STATUS
PD
B18
O
Power-down modes 2 or 3 (active if high)
† I = Input, O = Output, Z = High Impedance, S = Supply Voltage, GND = Ground
‡ PLLV, PLLG, and PLLF are not part of external voltage supply or ground. See the clock PLL section for information on how to connect these pins.
§ A = Analog Signal (PLL Filter)
¶ For emulation and normal operation, pull up EMU1 and EMU0 with a dedicated 20-kΩ resistor. For boundary scan, pull down EMU1 and EMU0
with a dedicated 20-kΩ resistor.
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Signal Descriptions (Continued)
SIGNAL
NAME
NO.
TYPE†
DESCRIPTION
PCI INTERFACE
PCLK
W5
AD31
D2
AD30
E3
AD29
E2
AD28
E1
AD27
F3
AD26
F5
AD25
F1
AD24
G3
AD23
H3
AD22
H2
AD21
J1
AD20
H1
AD19
M2
AD18
M1
AD17
N2
AD16
N1
AD15
T1
AD14
V2
AD13
U2
AD12
U1
AD11
W3
AD10
W2
AD9
V1
AD8
U4
AD7
W4
AD6
U5
AD5
V5
AD4
U6
AD3
V6
AD2
V3
AD1
W6
AD0
U7
PCBE3
G2
PCBE2
M3
PCBE1
T2
I
PCI input clock
I/O/Z
PCI Data-Address bus
I/O/Z
PCI command/byte enable signals
PCBE0
V4
† I = Input, O = Output, Z = High Impedance, S = Supply Voltage, GND = Ground
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Signal Descriptions (Continued)
SIGNAL
NAME
NO.
TYPE†
DESCRIPTION
PCI INTERFACE (CONTINUED)
PINTA
C1
O/Z
PCI interrupt A
PREQ
F2
O/Z
PCI bus request (bus arbitration)
PSERR
P5
O/Z
PCI system error
PPERR
P2
I/O/Z
PCI parity error
PRST
C2
I
PDEVSEL
R2
I/O/Z
PGNT
D1
I
PFRAME
N5
I/O/Z
PCI frame
PIRDY
P1
I/O/Z
PCI initiator ready
PPAR
T3
I/O/Z
PCI parity
PIDSEL
H5
I
PSTOP
R1
I/O/Z
PCI stop
PTRDY
N3
I/O/Z
PCI target ready
XSP_CLK
C17
O
Serial EEPROM clock
XSP_DI
C18
I
Serial EEPROM data in, pulldown with a dedicated 20-kΩ resistor
XSP_DO
B19
O
Serial EEPROM data out
XSP_CS
C11
O
Serial EEPROM chip select
3.3VauxDET
B1
I
PCI reset
PCI device select
PCI bus grant (bus arbitration)
PCI initialization device select
3.3-V auxiliary power supply detect.
Used to indicate the presence of 3.3Vaux. A weak pulldown must be implemented to this pin.
3.3Vaux
B2
S
3.3-V auxiliary power supply voltage
PME
D3
O
Power management event
PWR_WKP
A2
I
Power wakeup signal
CE3
V18
CE2
U17
EMIF − CONTROL SIGNALS COMMON TO ALL TYPES OF MEMORY
CE1
W18
CE0
V17
BE3
U16
BE2
W17
BE1
V16
BE0
W16
EA21
V7
EA20
W7
EA19
U8
EA18
V8
Memory space enables
O/Z
Enabled by bits 24 and 25 of the word address
Only one asserted during any external data access
Byte-enable control
O/Z
Decoded from the two lowest bits of the internal address
Byte-write enables for most types of memory
Can be directly connected to SDRAM read and write mask signal (SDQM)
EMIF − ADDRESS
O/Z
External address (word address)
EA17
W8
† I = Input, O = Output, Z = High Impedance, S = Supply Voltage, GND = Ground
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Signal Descriptions (Continued)
SIGNAL
NAME
NO.
TYPE†
DESCRIPTION
EMIF − ADDRESS (CONTINUED)
EA16
W9
EA15
V9
EA14
U9
EA13
W10
EA12
V10
EA11
U10
EA10
W11
EA9
V11
EA8
U11
EA7
R11
EA6
W12
EA5
U12
EA4
R12
EA3
W13
EA2
V13
ED31
F14
ED30
E19
O/Z
External address (word address)
EMIF − DATA
ED29
F17
ED28
G15
ED27
F18
ED26
F19
ED25
G17
ED24
G18
ED23
G19
ED22
H17
ED21
H18
ED20
H19
ED19
J18
ED18
J19
ED17
K15
ED16
K17
ED15
K18
ED14
K19
ED13
L17
ED12
L18
ED11
L19
ED10
M19
External data
I/O/Z
Used for transfer of EMIF data
Also controls initialization of DSP modes at reset via pullup/pulldown resistors
ED31 - PLL_Conf2
ED27 - PLL_Conf1
ED23 - PLL_Conf0
ED15 - EEPROM autoinitialization
ED8
- Endianness
ED[7:5] - EEPROM size
ED[4:0] - Bootmode
ED9
M18
† I = Input, O = Output, Z = High Impedance, S = Supply Voltage, GND = Ground
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Signal Descriptions (Continued)
SIGNAL
NAME
NO.
TYPE†
DESCRIPTION
EMIF − DATA (CONTINUED)
ED8
M17
ED7
N19
ED6
P19
ED5
N15
ED4
P18
ED3
P17
ED2
R19
ED1
R18
ED0
R17
ARE
I/O/Z
External data
U14
O/Z
Asynchronous memory read-enable
AOE
W14
O/Z
Asynchronous memory output-enable
AWE
V14
O/Z
Asynchronous memory write-enable
ARDY
W15
I
Asynchronous memory ready input
EMIF − ASYNCHRONOUS MEMORY CONTROL
EMIF − SYNCHRONOUS DRAM (SDRAM)/SYNCHRONOUS BURST SRAM (SBSRAM) CONTROL
SDA10
U19
O/Z
SDRAM address 10 (separate for deactivate command)
SDCAS/SSADS
V19
O/Z
SDRAM column-address strobe/SBSRAM address strobe
SDRAS/SSOE
U18
O/Z
SDRAM row-address strobe/SBSRAM output-enable
SDWE/SSWE
T17
O/Z
SDRAM write-enable/SBSRAM write-enable
HOLD
P14
I
Hold request from the host
HOLDA
V15
O
Hold-request-acknowledge to the host
TOUT0
E5
O
Timer 0 or general-purpose output
TINP0
C5
I
Timer 0 or general-purpose input
TOUT1
A5
O
Timer 1 or general-purpose output
TINP1
B5
I
Timer 1 or general-purpose input
EMIF − BUS ARBITRATION
TIMER 0
Timer 1
DMA ACTION COMPLETE STATUS
DMAC3
A17
DMAC2
B17
DMAC1
C16
DMAC0
A18
CLKS0
A12
I
CLKR0
B9
I/O/Z
Receive clock
CLKX0
C9
I/O/Z
Transmit clock
DR0
A10
I
Receive data
DX0
B10
O/Z
Transmit data
FSR0
E10
I/O/Z
Receive frame sync
O
DMA action complete
MULTICHANNEL BUFFERED SERIAL PORT 0 (McBSP0)
External clock source (as opposed to internal)
FSX0
A9
I/O/Z
Transmit frame sync
† I = Input, O = Output, Z = High Impedance, S = Supply Voltage, GND = Ground
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Signal Descriptions (Continued)
SIGNAL
NAME
NO.
TYPE†
DESCRIPTION
MULTICHANNEL BUFFERED SERIAL PORT 1 (McBSP1)
CLKS1
C6
I
CLKR1
B6
I/O/Z
External clock source (as opposed to internal)
Receive clock
CLKX1
E6
I/O/Z
Transmit clock
DR1
A7
I
Receive data
DX1
B7
O/Z
Transmit data
FSR1
C7
I/O/Z
Receive frame sync
FSX1
A6
I/O/Z
Transmit frame sync
RESERVED FOR TEST
RSV0
C8
I
Reserved for testing, pullup with a dedicated 20-kΩ resistor
RSV1
A4
I
Reserved for testing, pullup with a dedicated 20-kΩ resistor
RSV2
K3
I
Reserved for testing, pullup with a dedicated 20-kΩ resistor
RSV3
L5
O
Reserved (leave unconnected, do not connect to power or ground)
RSV4
T18
O
Reserved (leave unconnected, do not connect to power or ground)
RSV5
A3
O
Reserved (leave unconnected, do not connect to power or ground)
RSV6
B3
O
Reserved (leave unconnected, do not connect to power or ground)
RSV7
B4
O
Reserved (leave unconnected, do not connect to power or ground)
RSV8
C4
O
Reserved (leave unconnected, do not connect to power or ground)
RSV9
K2
O
Reserved (leave unconnected, do not connect to power or ground)
RSV10
J17
O
Reserved (leave unconnected, do not connect to power or ground)
RSV11
N18
O
Reserved (leave unconnected, do not connect to power or ground)
SUPPLY VOLTAGE PINS
B8
E7
E8
E9
E11
E13
H14
K14
DVDD
L15
S
3.3-V I/O supply voltage
M14
P15
R8
R9
R10
R13
R14
U15
† I = Input, O = Output, Z = High Impedance, S = Supply Voltage, GND = Ground
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Signal Descriptions (Continued)
SIGNAL
NAME
NO.
TYPE†
DESCRIPTION
SUPPLY VOLTAGE PINS (CONTINUED)
B12
E14
F9
F10
G5
H15
J2
J5
CVDD
J15
S
1.5-V core supply voltage
M5
M15
N17
P6
P9
P12
U13
PCI SUPPLY VOLTAGE PINS
G1
VIOP
P3
S
3.3/5-V PCI clamp pins
S
3.3-V PCI power supply pins
U3
F6
J6
L6
VDDP
R3
R6
R7
GROUND PINS
A11
A13
B11
B13
C10
C12
VSS
C13
GND
Ground pins
E12
G7
G8
G9
G10
† I = Input, O = Output, Z = High Impedance, S = Supply Voltage, GND = Ground
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Signal Descriptions (Continued)
SIGNAL
NAME
NO.
TYPE†
DESCRIPTION
GROUND PINS (CONTINUED)
G11
G12
G13
H7
H8
H9
H10
H11
H12
H13
J7
J8
J9
J10
J11
J12
J13
K1
K7
VSS
K8
GND
Ground pins
K9
K10
K11
K12
K13
L7
L8
L9
L10
L11
L12
L13
M7
M8
M9
M10
M11
M12
M13
† I = Input, O = Output, Z = High Impedance, S = Supply Voltage, GND = Ground
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Signal Descriptions (Continued)
SIGNAL
NAME
NO.
TYPE†
DESCRIPTION
GROUND PINS (CONTINUED)
N7
N8
N9
N10
VSS
N11
GND
Ground pins
N12
N13
V12
† I = Input, O = Output, Z = High Impedance, S = Supply Voltage, GND = Ground
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development support
TI offers an extensive line of development tools for the TMS320C6000 DSP platform, including tools to
evaluate the performance of the processors, generate code, develop algorithm implementations, and fully
integrate and debug software and hardware modules.
The following products support development of C6000 DSP-based applications:
Software Development Tools:
Code Composer Studio Integrated Development Environment (IDE) including Editor
C/C++/Assembly Code Generation, and Debug plus additional development tools
Scalable, Real-Time Foundation Software (DSP BIOS), which provides the basic run-time target software
needed to support any DSP application.
Hardware Development Tools:
Extended Development System (XDS) Emulator (supports C6000 DSP multiprocessor system debug)
EVM (Evaluation Module)
The TMS320 DSP Development Support Reference Guide (SPRU011) contains information about
development-support products for all TMS320 DSP family member devices, including documentation. See
this document for further information on TMS320 DSP documentation or any TMS320 DSP support products
from Texas Instruments. An additional document, the TMS320 Third-Party Support Reference Guide
(SPRU052), contains information about TMS320 DSP-related products from other companies in the industry.
To receive TMS320 DSP literature, contact the Literature Response Center at 800/477-8924.
For a complete listing of development-support tools for the TMS320C6000 DSP platform, visit the Texas
Instruments web site on the Worldwide Web at http://www.ti.com uniform resource locator (URL) and select
“Find Development Tools”. For device-specific tools, under “Semiconductor Products” select “Digital Signal
Processors”, choose a product family, and select the particular DSP device. For information on pricing and
availability, contact the nearest TI field sales office or authorized distributor.
Code Composer Studio, XDS, and TMS320 are trademarks of Texas Instruments.
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device and development-support tool nomenclature
To designate the stages in the product development cycle, TI assigns prefixes to the part numbers of all DSP
devices and support tools. Each DSP commercial family member has one of three prefixes: TMX, TMP, or TMS
(i.e., TMS320C6205GHK200). Texas Instruments recommends two of three possible prefix designators for
support tools: TMDX and TMDS. These prefixes represent evolutionary stages of product development from
engineering prototypes (TMX / TMDX) through fully qualified production devices/tools (TMS / TMDS).
Device development evolutionary flow:
TMX
Experimental device that is not necessarily representative of the final device’s electrical
specifications
TMP
Final silicon die that conforms to the device’s electrical specifications but has not completed
quality and reliability verification
TMS
Fully qualified production device
Support tool development evolutionary flow:
TMDX
Development-support product that has not yet completed Texas Instruments internal qualification
testing.
TMDS
Fully qualified development-support product
TMX and TMP devices and TMDX development-support tools are shipped against the following disclaimer:
“Developmental product is intended for internal evaluation purposes.”
TMS devices and TMDS development-support tools have been characterized fully, and the quality and reliability
of the device have been demonstrated fully. TI’s standard warranty applies.
Predictions show that prototype devices (TMX or TMP) have a greater failure rate than the standard production
devices. Texas Instruments recommends that these devices not be used in any production system because their
expected end-use failure rate still is undefined. Only qualified production devices are to be used.
TI device nomenclature also includes a suffix with the device family name. This suffix indicates the package type
(for example, GHK), the temperature range (for example, blank is the default commercial temperature range),
and the device speed range in megahertz (for example, -200 is 200 MHz).
The ZHK package, like the GHK package, is a 288-ball plastic BGA only with Pb-free balls.For device part
numbers and further ordering information for TMS320C6205 in the GHK and ZHK package types, see the TI
website (http://www.ti.com) or contact your TI sales representative.
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device and development-support tool nomenclature (continued)
‡
TMS 320
C 6205
PREFIX
TMX = Experimental device
TMP = Prototype device
TMS = Qualified device
SMJ = MIL-PRF-38535, QML
SM = High Rel (non-38535)
GHK
( )
200
DEVICE SPEED RANGE
200 MHz
DEVICE FAMILY
320 = TMS320 DSP family
TEMPERATURE RANGE (DEFAULT: 0°C TO 90°C)
Blank = 0°C to 90°C, commercial temperature
A
= −40°C to 105°C, extended temperature
PACKAGE TYPE†‡§
GHK = 288-pin plastic MicroStar BGA
ZHK = 288-pin plastic MicroStar BGA with Pb-free
. . . . . . . soldered balls
TECHNOLOGY
C = CMOS
DEVICE
C6000 DSP:
6205
† BGA = Ball Grid Array
‡ For actual device part numbers (P/Ns) and ordering information, see the Mechanical Data section of this
document or the TI website (www.ti.com).
§ The ZHK mechanical package designator represents the version of the GHK with Pb−Free soldered balls.
Figure 4. TMS320C6000 DSP Platform Device Nomenclature (Including the TMS320C6205 Device)
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documentation support
Extensive documentation supports all TMS320 DSP family devices from product announcement through
applications development. The types of documentation available include: data sheets, such as this document,
with design specifications; complete user’s reference guides for all devices and tools; technical briefs;
development-support tools; on-line help; and hardware and software applications. The following is a brief,
descriptive list of support documentation specific to the C6000 DSP devices:
The TMS320C6000 CPU and Instruction Set Reference Guide (literature number SPRU189) describes the
C6000 DSP core (CPU) architecture, instruction set, pipeline, and associated interrupts.
The TMS320C6000 DSP Peripherals Overview Reference Guide (literature number SPRU190) briefly
describes the functionality of the peripherals available on the C6000 DSP platform of devices, such as the
64-/32-/16-bit external memory interfaces (EMIFs), 32-/16-bit host-port interfaces (HPIs), multichannel buffered
serial ports (McBSPs), direct memory access (DMA), enhanced direct-memory-access (EDMA) controller,
expansion bus (XB), peripheral component interconnect (PCI), clocking and phase-locked loop (PLL); and
power-down modes.
The TMS320C6000 Technical Brief (literature number SPRU197) gives an introduction to the C62x/C67x
devices, associated development tools, and third-party support.
The tools support documentation is electronically available within the Code Composer Studio Integrated
Development Environment (IDE). For a complete listing of the latest C6000 DSP documentation, visit the
Texas Instruments web site on the Worldwide Web at http://www.ti.com uniform resource locator (URL).
See the Worldwide Web URL for the new How to Begin Development with the TMS320C6205 DSP application
report (literature number SPRA596) which describes the functionalities unique to the C6205 device, especially
the peripheral component interconnect (PCI) module interface.
C62x and C67x are trademarks of Texas Instruments.
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clock PLL
Most of the internal C6205 clocks are generated from a single source through the CLKIN pin. This source clock
either drives the PLL, which multiplies the source clock in frequency to generate the internal CPU clock, or
bypasses the PLL to become the internal CPU clock.
To use the PLL to generate the CPU clock, the external PLL filter circuit must be properly designed. Figure 5,
Table 3, and Table 4 show the external PLL circuitry for either x1 (PLL bypass) or x4 PLL multiply modes.
Figure 6 shows the external PLL circuitry for a system with ONLY x1 (PLL bypass) mode.
To minimize the clock jitter, a single clean power supply should power both the C6205 device and the external
clock oscillator circuit. Noise coupling into PLLF directly impacts PLL clock jitter. The minimum CLKIN rise and
fall times should also be observed. For the input clock timing requirements, see the input and output clocks
electricals section.
3.3V
PLLV
EMI Filter
Internal to C6205
ED[31,27,23]
(see Table 3)
C3
10 mF
C4
0.1 mF
PLL
CLKMODE0
(see Table 3)
PLLMULT
PLLCLK
CLKIN
CLKIN
1
LOOP FILTER
C2
C1
CPU
CLOCK
PLLG
PLLF
0
R1
NOTES: A. Keep the lead length and the number of vias between pin PLLF, pin PLLG, R1, C1, and C2 to a minimum. In addition, place all PLL
components (R1, C1, C2, C3, C4, and EMI Filter) as close to the C6000 DSP device as possible. Best performance is achieved
with the PLL components on a single side of the board without jumpers, switches, or components other than the ones shown.
B. For reduced PLL jitter, maximize the spacing between switching signals and the PLL external components (R1, C1, C2, C3, C4,
and the EMI Filter).
C. The 3.3-V supply for the EMI filter must be from the same 3.3-V power plane supplying the I/O voltage, DVDD.
D. EMI filter manufacturer: TDK part number ACF451832-333, 223, 153, 103. Panasonic part number EXCCET103U.
E. At power up, the PLL requires a falling edge of RESET to initialize the PLL engine. It may be necessary to toggle reset in order to
establish proper PLL operation.
Figure 5. External PLL Circuitry for Either PLL Multiply Modes or x1 (Bypass) Mode
3.3V
PLLV
CLKMODE0
PLL
Internal to C6205
PLLMULT
PLLCLK
CLKIN
CLKIN
LOOP FILTER
1
CPU
CLOCK
PLLG
PLLF
0
NOTES: A. For a system with ONLY PLL x1 (bypass) mode, short the PLLF to PLLG.
B. The 3.3-V supply for PLLV must be from the same 3.3-V power plane supplying the I/O voltage, DVDD.
Figure 6. External PLL Circuitry for x1 (Bypass) PLL Mode Only
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clock PLL (continued)
Table 3. C6205 PLL Multiply Modes and x1 (Bypass) Options
CLKMODE0†
ED[31]‡
ED[27]‡
ED[23]‡
PLL MULTIPLY
FACTORS
CPU CLOCK FREQ
f(CPU clock)
0
X
X
X
x1 (Bypass)
1 × f(CLKIN)
1
0
0
0
x1 (Bypass)
1 × f(CLKIN)
1
0
0
1
x4
4 × f(CLKIN)
1
0
1
0
x8
8 × f(CLKIN)
1
0
1
1
x10
10 × f(CLKIN)
1
1
0
0
x6
6 × f(CLKIN)
1
1
0
1
x9
9 × f(CLKIN)
1
1
1
0
x7
1
1
1
1
x11
7 × f(CLKIN)
11 × f(CLKIN)
† CLKMODE0 equal to 0 denotes on-chip PLL bypassed
CLKMODE0 equal to 1 denotes on-chip PLL used, except when configuration bits (ED[31], ED[27], and
ED[23]) are 0 at device reset.
‡ ED[31], ED[27], and ED[23] are the on-chip PLL configuration bits that are latched during device reset,
along with the other boot configuration bits ED[31:0].
Table 4. C6205 PLL Component Selection Table§
CLKMODE
CLKIN
RANGE
(MHz)
x4
32.5−50
x6
21.7−33.3
x7
18.6−28.6
x8
16.3−25
x9
14.4−22.2
x10
13−20
x11
11.8−18.2
CPU CLOCK
FREQUENCY
(CLKOUT1)
RANGE (MHz)
CLKOUT2
RANGE
(MHz)
R1 [+1%]
(W)
C1 [+10%]
(nF)
C2 [+10%]
(pF)
TYPICAL
LOCK TIME
(µs)
130−200
65−100
60.4
27
560
75
§ Under some operating conditions, the maximum PLL lock time may vary as much as 150% from the specified typical value. For example, if the
typical lock time is specified as 100 µs, the maximum value may be as long as 250 µs.
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power-down mode logic
Figure 7 shows the power-down mode logic on the C6205.
CLKOUT1
TMS320C6205
Internal Clock Tree
PD1
PD2
PD
PowerDown
Logic
Clock
PLL
(pin)
IFR
IER
PWRD
Internal
Peripheral
Internal
Peripheral
CSR
CPU
PD3
CLKIN
RESET
Figure 7. Power-Down Mode Logic†
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29
SPRS106G − OCTOBER 1999 − REVISED JULY 2006
triggering, wake-up, and effects
The power-down modes and their wake-up methods are programmed by setting the PWRD field (bits 15−10)
of the control status register (CSR). The PWRD field of the CSR is shown in Figure 8 and described in Table 5.
When writing to the CSR, all bits of the PWRD field should be set at the same time. Logic 0 should be used when
“writing” to the reserved bit (bit 15) of the PWRD field. The CSR is discussed in detail in the TMS320C6000 CPU
and Instruction Set Reference Guide (literature number SPRU189).
31
16
15
14
13
12
11
10
Reserved
Enable or
Non-Enabled
Interrupt Wake
Enabled
Interrupt Wake
PD3
PD2
PD1
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
7
9
8
0
Legend: R/W−x = Read/write reset value
NOTE: The shadowed bits are not part of the power-down logic discussion and therefore are not covered here. For information on these other
bit fields in the CSR register, see the TMS320C6000 CPU and Instruction Set Reference Guide (literature number SPRU189).
Figure 8. PWRD Field of the CSR Register
Power-down mode PD1 takes effect eight to nine clock cycles after the instruction that sets the PWRD bits in the
CSR.
If PD1 mode is terminated by a non-enabled interrupt, the program execution returns to the instruction where PD1
took effect. If PD1 mode is terminated by an enabled interrupt, the interrupt service routine will be executed first,
then the program execution returns to the instruction where PD1 took effect. The GIE bit in CSR and the NMIE
bit in the interrupt enable register (IER) must also be set in order for the interrupt service routine to execute;
otherwise, execution returns to the instruction where PD1 took effect upon PD1 mode termination by an enabled
interrupt.
PD2 and PD3 modes can only be aborted by device reset. Table 5 summarizes all the power-down modes.
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Table 5. Characteristics of the Power-Down Modes
PRWD FIELD
(BITS 15−10)
POWER-DOWN
MODE
WAKE-UP METHOD
000000
No power-down
—
—
001001
PD1
Wake by an enabled interrupt
010001
PD1
Wake by an enabled or
non-enabled interrupt
011010
011100
PD2†
PD3†
EFFECT ON CHIP’S OPERATION
CPU halted (except for the interrupt logic)
Power-down mode blocks the internal clock inputs at the
boundary of the CPU, preventing most of the CPU’s logic from
switching. During PD1, DMA transactions can proceed between
peripherals and internal memory.
Wake by a device reset
Output clock from PLL is halted, stopping the internal clock
structure from switching and resulting in the entire chip being
halted. All register and internal RAM contents are preserved. All
functional I/O “freeze” in the last state when the PLL clock is
turned off.
Wake by a device reset
Input clock to the PLL stops generating clocks. All register and
internal RAM contents are preserved. All functional I/O “freeze” in
the last state when the PLL clock is turned off. Following reset, the
PLL needs time to re-lock, just as it does following power-up.
Wake-up from PD3 takes longer than wake-up from PD2 because
the PLL needs to be re-locked.
All others
Reserved
—
—
† When entering PD2 and PD3, all functional I/O remains in the previous state. However, for peripherals which are asynchronous in nature or
peripherals with an external clock source, output signals may transition in response to stimulus on the inputs. Under these conditions,
peripherals will not operate according to specifications.
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power-supply sequencing
TI DSPs do not require specific power sequencing between the core supply and the I/O supply. However,
systems should be designed to ensure that neither supply is powered up for extended periods of time if the other
supply is below the proper operating voltage.
system-level design considerations
System-level design considerations, such as bus contention, may require supply sequencing to be
implemented. In this case, the core supply should be powered up at the same time as, or prior to (and powered
down after), the I/O buffers. This is to ensure that the I/O buffers receive valid inputs from the core before the
output buffers are powered up, thus, preventing bus contention with other chips on the board.
power-supply design considerations
For systems using the C6000 DSP platform of devices, the core supply may be required to provide in excess
of 2 A per DSP until the I/O supply is powered up. This extra current condition is a result of uninitialized logic
within the DSP(s) and is corrected once the CPU sees an internal clock pulse. With the PLL enabled, as the
I/O supply is powered on, a clock pulse is produced stopping the extra current draw from the supply. With the
PLL disabled, as many as five external clock cycle pulses may be required to stop this extra current draw. A
normal current state returns once the I/O power supply is turned on and the CPU sees a clock pulse. Decreasing
the amount of time between the core supply power up and the I/O supply power up can minimize the effects
of this current draw.
A dual-power supply with simultaneous sequencing, such as that available with TPS563xx controllers or
PT69xx plug-in power modules, can be used to eliminate the delay between core and I/O power up [see the
Using the TPS56300 to Power DSPs application report (literature number SLVA088)]. A Schottky diode can also
be used to tie the core rail to the I/O rail, effectively pulling up the I/O power supply to a level that can help initialize
the logic within the DSP.
Core and I/O supply voltage regulators should be located close to the DSP (or DSP array) to minimize
inductance and resistance in the power delivery path. Additionally, when designing for high-performance
applications utilizing the C6000 platform of DSPs, the PC board should include separate power planes for
core, I/O, and ground, all bypassed with high-quality low-ESL/ESR capacitors.
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absolute maximum ratings over operating case temperature range (unless otherwise noted)†
Supply voltage ranges: CVDD (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . − 0.3 V to 2.3 V
DVDD (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.3 V to 4 V
(PCI), VIOP (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 5.5 V
(PCI), VDDP (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.3 V to 4 V
Input voltage ranges: (except PCI), VI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.3 V to 4 V
(PCI), VIP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to VIOP + 0.5 V
Output voltage ranges: (except PCI), VO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.3 V to 4 V
(PCI), VOP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to VIOP + 0.5 V
Operating case temperature range, TC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0C to 90C
Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65C to 150C
† Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTE 1: All voltage values are with respect to VSS.
recommended operating conditions
MIN
NOM
MAX
UNIT
CVDD
Supply voltage, Core
1.43
1.5
1.57
V
DVDD
Supply voltage, I/O
3.14
3.3
3.46
V
VSS
VIH
Supply ground
0
0
0
V
High-level input voltage
2
VIL
IOH
Low-level input voltage
0.8
V
High-level output current
−8
mA
IOL
TC
Low-level output current
8
mA
90
C
Operating case temperature
V
0
recommended operating conditions (PCI only)
VDDP
3.3-V PCI power supply voltage‡
VIOP
3.3/5-V PCI Clamp voltage (PCI)
VIP
Input voltage (PCI)
VIHP
High-level input voltage (PCI)
CMOS-compatible
VILP
Low-level input voltage (PCI)
CMOS-compatible
OPERATION
MIN
3.3 V
3
NOM
3.3
MAX
UNIT
3.6
V
3.3 V
3
5V
4.75
3.3
3.6
V
5
5.25
3.3 V
−0.5
V
−0.5
VIOP + 0.5
VIOP + 0.5
5V
V
3.3 V
5V
0.5VIOP
2
VIOP + 0.5
VIOP + 0.5
V
3.3 V
−0.5
5V
−0.5
0.3VIOP
0.8
V
‡ The 3.3-V PCI power supply voltage should follow similar sequencing as the I/O buffers supply voltage, see the power-supply sequencing section
of this data sheet.
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electrical characteristics over recommended ranges of supply voltage and operating case
temperature (unless otherwise noted)
PARAMETER
VOH
VOL
II
IOZ
TEST CONDITIONS
High-level output voltage (except PCI)
DVDD = MIN,
Low-level output voltage (except PCI)
Input current†
DVDD = MIN,
MIN
IOH = MAX
IOL = MAX
TYP
MAX
2.4
UNIT
V
0.6
V
±10
µA
±10
µA
Off-state output current
VI = VSS to DVDD
VO = DVDD or 0 V
IDD2V
Supply current, CPU + CPU memory
access‡
CVDD = NOM,
CPU clock = 200 MHz
290
mA
IDD2V
IDD3V
Supply current, peripherals‡
Supply current, I/O pins‡
CVDD = NOM,
CPU clock = 200 MHz
240
mA
DVDD = NOM,
CPU clock = 200 MHz
100
mA
Ci
Input capacitance
10
pF
Co
Output capacitance
10
pF
† TMS and TDI are not included due to internal pullups. TRST is not included due to internal pulldown.
‡ Measured with average activity (50% high/50% low power). For more details on CPU, peripheral, and I/O activity, see the TMS320C6000 Power
Consumption Summary application report (literature number SPRA486).
electrical characteristics over recommended ranges of supply voltage and operating case
temperature (unless otherwise noted) (PCI only)
PARAMETER
PCI SIDE
VOHP
High-level output voltage (PCI)
All PCI pins
VOLP
Low-level output voltage (PCI)
IILP
Low-level input leakage current (PCI)
All PCI pins
All PCI pins§
TEST CONDITIONS AND
OPERATION
POST OFFICE BOX 1443
MAX
IOHP = −0.5 mA
IOHP = −2 mA
3.3 V
0.9VIOP§
5V
2.4
IOLP = 1.5 mA
IOLP = 6 mA
3.3 V
0.1VIOP§
5V
0 < VIP < VIOP
3.3 V
0.55
±10
5V
−70
VIP = 0.5 V
VIP = 2.7 V
IIHP
High-level input leakage current (PCI)
All PCI pins§
5V
§ Input leakage currents include Hi-Z output leakage for all bidirectional buffers with 3-state outputs.
34
MIN
• HOUSTON, TEXAS 77251−1443
UNIT
V
70
V
µA
A
µA
SPRS106G − OCTOBER 1999 − REVISED JULY 2006
PARAMETER MEASUREMENT INFORMATION
IOL
Tester Pin
Electronics
50 Ω
Vcomm
Output
Under
Test
CT
IOH
Where:
IOL
IOH
Vcomm
CT
=
=
=
=
2 mA
2 mA
0.8 V
15−30-pF typical load-circuit capacitance
Figure 9. Test Load Circuit for AC Timing Measurements
signal transition levels
All input and output timing parameters are referenced to 1.5 V for both “0” and “1” logic levels.
Vref = 1.5 V
Figure 10. Input and Output Voltage Reference Levels for ac Timing Measurements
All rise and fall transition timing parameters are referenced to VIL MAX and VIH MIN for input clocks, VOL MAX
and VOH MIN for output clocks, VILP MAX and VIHP MIN for PCI input clocks, and VOLP MAX and VOHP MIN for
PCI output clocks.
Vref = VIH MIN (or VOH MIN or
VIHP MIN or VOHP MIN)
Vref = VIL MAX (or VOL MAX or
VILP MAX or VOLP MAX)
Figure 11. Rise and Fall Transition Time Voltage Reference Levels
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INPUT AND OUTPUT CLOCKS
timing requirements for CLKIN†‡§ (see Figure 12)
−200
PLL mode x4,
x6, x7, x8, x9,
x10, x11
NO.
MIN
1
2
3
MAX
PLL mode
x1
MIN
UNIT
MAX
tc(CLKIN)
tw(CLKINH)
Cycle time, CLKIN
5*M
5
ns
Pulse duration, CLKIN high
0.4C
0.45C
ns
tw(CLKINL)
tt(CLKIN)
Pulse duration, CLKIN low
0.4C
0.45C
ns
4
Transition time, CLKIN
5
† The reference points for the rise and fall transitions are measured at VIL MAX and VIH MIN.
‡ M = the PLL multiplier factor (x4, x6, x7, x8, x9, x10, or x11). For more details, see the clock PLL section of this data sheet.
§ C = CLKIN cycle time in ns. For example, when CLKIN frequency is 50 MHz, use C = 20 ns.
1
0.6
ns
4
2
CLKIN
3
4
Figure 12. CLKIN Timings
timing requirements for PCLKIN¶ (see Figure 13)
−200
NO.
1
2
3
4
MIN
MAX
UNIT
tc(PCLK)
tw(PCLKH)
Cycle time, PCLK
30
ns
Pulse duration, PCLK high
11
ns
tw(PCLKL)
tsr(PCLK)
Pulse duration, PCLK low
11
∆v/∆t slew rate, PCLK
1
ns
4
V/ns
¶ When the 5-V PCI clamp is used, the reference points for the rise and fall transitions are measured VILP MAX and VIHP MIN for 5 V operation.
When the 3.3-V PCI clamp is used, the reference points for the rise and fall transitions are measured at VILP MAX and VIHP MIN for 3.3 V
operation.
2 V MIN
Peak to Peak for
5V signaling
1
or
0.4 VIOP MIN
Peak to Peak for
3V signaling
4
2
PCLK
3
4
Figure 13. PCLK Timings
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SPRS106G − OCTOBER 1999 − REVISED JULY 2006
INPUT AND OUTPUT CLOCKS (CONTINUED)
switching characteristics over recommended operating conditions for CLKOUT2†‡ (see Figure 14)
−200
NO.
2
3
PARAMETER
tw(CKO2H)
tw(CKO2L)
UNIT
MIN
MAX
Pulse duration, CLKOUT2 high
P − 0.7
P + 0.7
ns
Pulse duration, CLKOUT2 low
P − 0.7
P + 0.7
ns
0.6
ns
4
tt(CKO2)
Transition time, CLKOUT2
† The reference points for the rise and fall transitions are measured at VOL MAX and VOH MIN.
‡ P = 1/CPU clock frequency in nanoseconds (ns).
1
4
2
CLKOUT2
3
4
Figure 14. CLKOUT2 Timings
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SPRS106G − OCTOBER 1999 − REVISED JULY 2006
ASYNCHRONOUS MEMORY TIMING
timing requirements for asynchronous memory cycles†‡§¶ (see Figure 15 − Figure 18)
−200
NO.
3
MIN
tsu(EDV-AREH)
th(AREH-EDV)
Setup time, EDx valid before ARE high
tsu(ARDYH-AREL)
th(AREL-ARDYH)
Setup time, ARDY high before ARE low
tsu(ARDYL-AREL)
th(AREL-ARDYL)
Setup time, ARDY low before ARE low
10
11
tw(ARDYH)
Pulse width, ARDY high
15
tsu(ARDYH-AWEL)
th(AWEL-ARDYH)
Setup time, ARDY high before AWE low
tsu(ARDYL-AWEL)
th(AWEL-ARDYL)
Setup time, ARDY low before AWE low
4
6
7
9
16
18
19
Hold time, EDx valid after ARE high
Hold time, ARDY high after ARE low
Hold time, ARDY low after ARE low
Hold time, ARDY high after AWE low
Hold time, ARDY low after AWE low
MAX
UNIT
1.5
ns
3.5
ns
−[(RST − 3) * P − 6]
ns
(RST − 3) * P + 3
ns
−[(RST − 3) * P − 6]
ns
(RST − 3) * P + 3
ns
2P
ns
−[(WST − 3) * P − 6]
ns
(WST − 3) * P + 3
ns
−[(WST − 3) * P − 6]
ns
(WST − 3) * P + 3
ns
† To ensure data setup time, simply program the strobe width wide enough. ARDY is internally synchronized. If ARDY does meet setup or hold
time, it may be recognized in the current cycle or the next cycle. Thus, ARDY can be an asynchronous input.
‡ RS = Read Setup, RST = Read Strobe, RH = Read Hold, WS = Write Setup, WST = Write Strobe, WH = Write Hold. These parameters are
programmed via the EMIF CE space control registers.
§ P = 1/CPU clock frequency in ns. For example, when running parts at 200 MHz, use P = 5 ns.
¶ The sum of RS and RST (or WS and WST) must be a minimum of 4 in order to use ARDY input to extend strobe width.
switching characteristics over recommended operating conditions for asynchronous memory
cycles‡§¶# (see Figure 15 − Figure 18)
−200
NO.
1
PARAMETER
MIN
TYP
MAX
UNIT
tosu(SELV-AREL)
toh(AREH-SELIV)
Output setup time, select signals valid to ARE low
RS * P − 2
ns
2
Output hold time, ARE high to select signals invalid
RH * P − 2
ns
5
tw(AREL)
Pulse width, ARE low
8
td(ARDYH-AREH)
tosu(SELV-AWEL)
Delay time, ARDY high to ARE high
Output setup time, select signals valid to AWE low
WS * P − 2
ns
toh(AWEH-SELIV)
tw(AWEL)
Output hold time, AWE high to select signals invalid
WH * P − 2
ns
12
13
14
RST * P
Pulse width, AWE low
3P
WST * P
17
ns
4P + 5
ns
ns
td(ARDYH-AWEH) Delay time, ARDY high to AWE high
3P
4P + 5
ns
‡ RS = Read Setup, RST = Read Strobe, RH = Read Hold, WS = Write Setup, WST = Write Strobe, WH = Write Hold. These parameters are
programmed via the EMIF CE space control registers.
§ P = 1/CPU clock frequency in ns. For example, when running parts at 200 MHz, use P = 5 ns.
¶ The sum of RS and RST (or WS and WST) must be a minimum of 4 in order to use ARDY input to extend strobe width.
# Select signals include: CEx, BE[3:0], EA[21:2], AOE; and for writes, include ED[31:0], with the exception that CEx can stay active for an additional
7P ns following the end of the cycle.
38
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ASYNCHRONOUS MEMORY TIMING (CONTINUED)
Setup = 2 Strobe = 3
Hold = 2
CPU Clock†
1
2
1
2
1
2
CEx
BE[3:0]
EA[21:2]
3
4
ED[31:0]
1
2
AOE
5
6
7
ARE
AWE
ARDY
† CPU clock is an internal signal.
Figure 15. Asynchronous Memory Read Timing (ARDY Not Used)
Setup = 2
Strobe = 3
Not Ready
Hold = 2
CPU Clock†
1
2
1
2
1
2
CEx
BE[3:0]
EA[21:2]
3
4
ED[31:0]
1
2
AOE
8
10
9
ARE
AWE
11
ARDY
† CPU clock is an internal signal.
Figure 16. Asynchronous Memory Read Timing (ARDY Used)
POST OFFICE BOX 1443
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SPRS106G − OCTOBER 1999 − REVISED JULY 2006
ASYNCHRONOUS MEMORY TIMING (CONTINUED)
Setup = 2 Strobe = 3
Hold = 2
CPU Clock†
12
13
12
13
12
13
12
13
CEx
BE[3:0]
EA[21:2]
ED[31:0]
AOE
15
ARE
16
14
AWE
ARDY
† CPU clock is an internal signal.
Figure 17. Asynchronous Memory Write Timing (ARDY Not Used)
Setup = 2 Strobe = 3
Not Ready
Hold = 2
CPU Clock†
12
13
12
13
12
13
12
13
CEx
BE[3:0]
EA[21:2]
ED[31:0]
AOE
ARE
17
18
19
AWE
11
ARDY
† CPU clock is an internal signal.
Figure 18. Asynchronous Memory Write Timing (ARDY Used)
40
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SYNCHRONOUS-BURST MEMORY TIMING
timing requirements for synchronous-burst SRAM cycles (see Figure 19)
−200
NO.
7
8
MIN
tsu(EDV-CKO2H)
th(CKO2H-EDV)
MAX
UNIT
Setup time, read EDx valid before CLKOUT2 high
2.5
ns
Hold time, read EDx valid after CLKOUT2 high
1.5
ns
switching characteristics over recommended operating conditions for synchronous-burst SRAM
cycles†‡ (see Figure 19 and Figure 20)
−200
NO.
1
2
3
4
5
6
9
10
11
12
13
PARAMETER
MIN
tosu(CEV-CKO2H)
toh(CKO2H-CEV)
Output setup time, CEx valid before CLKOUT2 high
tosu(BEV-CKO2H)
toh(CKO2H-BEIV)
Output setup time, BEx valid before CLKOUT2 high
tosu(EAV-CKO2H)
toh(CKO2H-EAIV)
Output setup time, EAx valid before CLKOUT2 high
tosu(ADSV-CKO2H)
toh(CKO2H-ADSV)
Output setup time, SDCAS/SSADS valid before CLKOUT2 high
tosu(OEV-CKO2H)
toh(CKO2H-OEV)
Output setup time, SDRAS/SSOE valid before CLKOUT2 high
14
tosu(EDV-CKO2H)
toh(CKO2H-EDIV)
15
tosu(WEV-CKO2H)
Output hold time, CEx valid after CLKOUT2 high
Output hold time, BEx invalid after CLKOUT2 high
Output hold time, EAx invalid after CLKOUT2 high
Output hold time, SDCAS/SSADS valid after CLKOUT2 high
MAX
UNIT
P − 0.8
ns
P−4
ns
P − 0.8
ns
P−4
ns
P − 0.8
ns
P−4
ns
P − 0.8
ns
P−4
ns
P − 0.8
ns
Output hold time, SDRAS/SSOE valid after CLKOUT2 high
Output setup time, EDx valid before CLKOUT2 high§
P−4
ns
P−1
ns
Output hold time, EDx invalid after CLKOUT2 high
P−4
ns
P − 0.8
ns
Output setup time, SDWE/SSWE valid before CLKOUT2 high
16
toh(CKO2H-WEV)
Output hold time, SDWE/SSWE valid after CLKOUT2 high
P−4
ns
† P = 1/CPU clock frequency in ns. For example, when running parts at 200 MHz, use P = 5 ns.
‡ SDCAS/SSADS, SDRAS/SSOE, and SDWE/SSWE operate as SSADS, SSOE, and SSWE, respectively, during SBSRAM accesses.
§ For the first write in a series of one or more consecutive adjacent writes, the write data is generated one CLKOUT2 cycle early to accommodate
the ED enable time.
POST OFFICE BOX 1443
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41
SPRS106G − OCTOBER 1999 − REVISED JULY 2006
SYNCHRONOUS-BURST MEMORY TIMING (CONTINUED)
CLKOUT2
1
2
CEx
BE[3:0]
3
BE1
BE2
BE3
BE4
4
EA[21:2]
5
A1
A2
A3
A4
6
7
Q1
ED[31:0]
8
Q2
Q3
9
Q4
10
SDCAS/SSADS†
11
12
SDRAS/SSOE†
SDWE/SSWE†
† SDCAS/SSADS, SDRAS/SSOE, and SDWE/SSWE operate as SSADS, SSOE, and SSWE, respectively, during SBSRAM accesses.
Figure 19. SBSRAM Read Timing
CLKOUT2
1
2
CEx
BE[3:0]
3
BE1
BE2
BE3
BE4
4
EA[21:2]
5
A1
A2
A3
A4
Q1
Q2
Q3
Q4
6
13
14
ED[31:0]
9
10
15
16
SDCAS/SSADS†
SDRAS/SSOE†
SDWE/SSWE†
† SDCAS/SSADS, SDRAS/SSOE, and SDWE/SSWE operate as SSADS, SSOE, and SSWE, respectively, during SBSRAM accesses.
Figure 20. SBSRAM Write Timing
42
POST OFFICE BOX 1443
• HOUSTON, TEXAS 77251−1443
SPRS106G − OCTOBER 1999 − REVISED JULY 2006
SYNCHRONOUS DRAM TIMING
timing requirements for synchronous DRAM cycles (see Figure 21)
−200
NO.
7
8
MIN
tsu(EDV-CKO2H)
th(CKO2H-EDV)
Setup time, read EDx valid before CLKOUT2 high
MAX
UNIT
1.25
ns
3
ns
Hold time, read EDx valid after CLKOUT2 high
switching characteristics over recommended operating conditions for synchronous DRAM
cycles†‡ (see Figure 21−Figure 26)
−200
NO.
1
2
3
4
5
6
9
10
11
12
13
14
15
16
17
18
PARAMETER
MIN
tosu(CEV-CKO2H)
toh(CKO2H-CEV)
Output setup time, CEx valid before CLKOUT2 high
tosu(BEV-CKO2H)
toh(CKO2H-BEIV)
Output setup time, BEx valid before CLKOUT2 high
tosu(EAV-CKO2H)
toh(CKO2H-EAIV)
Output setup time, EAx valid before CLKOUT2 high
tosu(CASV-CKO2H)
toh(CKO2H-CASV)
Output setup time, SDCAS/SSADS valid before CLKOUT2 high
tosu(EDV-CKO2H)
toh(CKO2H-EDIV)
MAX
UNIT
P−1
ns
P − 3.5
ns
P−1
ns
P − 3.5
ns
P−1
ns
P − 3.5
ns
P−1
ns
Output hold time, SDCAS/SSADS valid after CLKOUT2 high
Output setup time, EDx valid before CLKOUT2 high§
P − 3.5
ns
P−3
ns
Output hold time, EDx invalid after CLKOUT2 high
P − 3.5
ns
Output hold time, CEx valid after CLKOUT2 high
Output hold time, BEx invalid after CLKOUT2 high
Output hold time, EAx invalid after CLKOUT2 high
tosu(WEV-CKO2H)
toh(CKO2H-WEV)
Output setup time, SDWE/SSWE valid before CLKOUT2 high
tosu(SDA10V-CKO2H)
toh(CKO2H-SDA10IV)
Output setup time, SDA10 valid before CLKOUT2 high
tosu(RASV-CKO2H)
toh(CKO2H-RASV)
Output setup time, SDRAS/SSOE valid before CLKOUT2 high
Output hold time, SDWE/SSWE valid after CLKOUT2 high
Output hold time, SDA10 invalid after CLKOUT2 high
Output hold time, SDRAS/SSOE valid after CLKOUT2 high
P−1
ns
P − 3.5
ns
P−1
ns
P − 3.5
ns
P−1
ns
ns
† P = 1/CPU clock frequency in ns. For example, when running parts at 200 MHz, use P = 5 ns.
‡ SDCAS/SSADS, SDRAS/SSOE, and SDWE/SSWE operate as SDCAS, SDRAS, and SDWE, respectively, during SDRAM accesses.
§ For the first write in a series of one or more consecutive adjacent writes, the write data is generated one CLKOUT2 cycle early to accommodate
the ED enable time.
POST OFFICE BOX 1443
• HOUSTON, TEXAS 77251−1443
P − 3.5
43
SPRS106G − OCTOBER 1999 − REVISED JULY 2006
SYNCHRONOUS DRAM TIMING (CONTINUED)
READ
READ
READ
CLKOUT2
1
2
CEx
3
BE[3:0]
5
EA[15:2]
4
BE1
BE2
CA2
CA3
BE3
6
CA1
7
8
D1
ED[31:0]
15
16
9
10
D2
D3
SDA10
SDRAS/SSOE†
SDCAS/SSADS†
SDWE/SSWE†
† SDCAS/SSADS, SDRAS/SSOE, and SDWE/SSWE operate as SDCAS, SDRAS, and SDWE, respectively, during SDRAM accesses.
Figure 21. Three SDRAM READ Commands
WRITE
WRITE
WRITE
CLKOUT2
1
2
CEx
3
BE[3:0]
4
BE1
5
EA[15:2]
BE3
CA2
CA3
D2
D3
6
CA1
11
D1
ED[31:0]
BE2
12
15
16
9
10
13
14
SDA10
SDRAS/SSOE†
SDCAS/SSADS†
SDWE/SSWE†
† SDCAS/SSADS, SDRAS/SSOE, and SDWE/SSWE operate as SDCAS, SDRAS, and SDWE, respectively, during SDRAM accesses.
Figure 22. Three SDRAM WRT Commands
44
POST OFFICE BOX 1443
• HOUSTON, TEXAS 77251−1443
SPRS106G − OCTOBER 1999 − REVISED JULY 2006
SYNCHRONOUS DRAM TIMING (CONTINUED)
ACTV
CLKOUT2
1
2
CEx
BE[3:0]
5
Bank Activate/Row Address
EA[15:2]
ED[31:0]
15
Row Address
SDA10
17
18
SDRAS/SSOE†
SDCAS/SSADS†
SDWE/SSWE†
† SDCAS/SSADS, SDRAS/SSOE, and SDWE/SSWE operate as SDCAS, SDRAS, and SDWE, respectively, during SDRAM accesses.
Figure 23. SDRAM ACTV Command
DCAB
CLKOUT2
1
2
15
16
17
18
CEx
BE[3:0]
EA[15:2]
ED[31:0]
SDA10
SDRAS/SSOE†
SDCAS/SSADS†
13
14
SDWE/SSWE†
† SDCAS/SSADS, SDRAS/SSOE, and SDWE/SSWE operate as SDCAS, SDRAS, and SDWE, respectively, during SDRAM accesses.
Figure 24. SDRAM DCAB Command
POST OFFICE BOX 1443
• HOUSTON, TEXAS 77251−1443
45
SPRS106G − OCTOBER 1999 − REVISED JULY 2006
SYNCHRONOUS DRAM TIMING (CONTINUED)
REFR
CLKOUT2
1
2
CEx
BE[3:0]
EA[15:2]
ED[31:0]
SDA10
17
18
SDRAS/SSOE†
9
10
SDCAS/SSADS†
SDWE/SSWE†
† SDCAS/SSADS, SDRAS/SSOE, and SDWE/SSWE operate as SDCAS, SDRAS, and SDWE, respectively, during SDRAM accesses.
Figure 25. SDRAM REFR Command
MRS
CLKOUT2
1
2
5
6
CEx
BE[3:0]
EA[15:2]
MRS Value
ED[31:0]
SDA10
17
18
9
10
13
14
SDRAS/SSOE†
SDCAS/SSADS†
SDWE/SSWE†
† SDCAS/SSADS, SDRAS/SSOE, and SDWE/SSWE operate as SDCAS, SDRAS, and SDWE, respectively, during SDRAM accesses.
Figure 26. SDRAM MRS Command
46
POST OFFICE BOX 1443
• HOUSTON, TEXAS 77251−1443
SPRS106G − OCTOBER 1999 − REVISED JULY 2006
HOLD/HOLDA TIMING
timing requirements for the HOLD/HOLDA cycles† (see Figure 27)
−200
NO.
MIN
3
toh(HOLDAL-HOLDL) Output hold time, HOLD low after HOLDA low
† P = 1/CPU clock frequency in ns. For example, when running parts at 200 MHz, use P = 5 ns.
MAX
P
UNIT
ns
switching characteristics over recommended operating conditions for the HOLD/HOLDA cycles†‡
(see Figure 27)
−200
NO.
1
2
4
5
PARAMETER
MIN
td(HOLDL-EMHZ)
td(EMHZ-HOLDAL)
Delay time, HOLD low to EMIF Bus high impedance
td(HOLDH-EMLZ)
td(EMLZ-HOLDAH)
Delay time, HOLD high to EMIF Bus low impedance
Delay time, EMIF Bus high impedance to HOLDA low
Delay time, EMIF Bus low impedance to HOLDA high
4P
MAX
§
UNIT
ns
0
2P
ns
3P
7P
ns
0
2P
ns
† P = 1/CPU clock frequency in ns. For example, when running parts at 200 MHz, use P = 5 ns.
‡ EMIF Bus consists of CE[3:0], BE[3:0], ED[31:0], EA[21:2], ARE, AOE, AWE, SDCAS/SSADS, SDRAS/SSOE, SDWE/SSWE, and SDA10.
§ All pending EMIF transactions are allowed to complete before HOLDA is asserted. The worst case for this is an asynchronous read or write with
external ARDY used or a minimum of eight consecutive SDRAM reads or writes when RBTR8 = 1. If no bus transactions are occurring, then the
minimum delay time can be achieved. Also, bus hold can be indefinitely delayed by setting NOHOLD = 1.
External Requestor
Owns Bus
DSP Owns Bus
DSP Owns Bus
3
HOLD
2
5
HOLDA
EMIF Bus†
1
4
C6205
C6205
† EMIF Bus consists of CE[3:0], BE[3:0], ED[31:0], EA[21:2], ARE, AOE, AWE, SDCAS/SSADS, SDRAS/SSOE, SDWE/SSWE, and SDA10.
Figure 27. HOLD/HOLDA Timing
POST OFFICE BOX 1443
• HOUSTON, TEXAS 77251−1443
47
SPRS106G − OCTOBER 1999 − REVISED JULY 2006
RESET TIMING
timing requirements for reset (see Figure 28)
−200
NO.
Width of the RESET pulse (PLL stable)†
1
tw(RST)
Width of the RESET pulse (PLL needs to sync up)§
10
tsu(ED)
th(ED)
Setup time, ED boot configuration bits valid before RESET high¶
Hold time, ED boot configuration bits valid after RESET high¶
11
MIN
10P‡
MAX
UNIT
ns
µs
250
5P‡#
ns
5P‡
ns
† This parameter applies to CLKMODE x1 when CLKIN is stable, and applies to CLKMODE x4, x6, x7, x8, x9, x10, and x11 when CLKIN and PLL
are stable.
‡ P = 1/CPU clock frequency in ns. For example, when running parts at 200 MHz, use P = 5 ns.
§ This parameter applies to CLKMODE x4, x6, x7, x8, x9, x10, and x11 only. The RESET signal is not connected internally to the Clock PLL circuit.
The PLL requires a minimum of 250 µs to stabilize following device power up or after PLL configuration has been changed. During that time,
RESET must be asserted to ensure proper device operation. See the clock PLL section for power up (specifically Figure 5, Note E) and for PLL
lock times (Table 4).
¶ ED[31:0] are the boot configuration pins during device reset.
# A 250 µs setup time before the rising edge of RESET is required when using CLKMODE x4, x6, x7, x8, x9, x10, or x11.
switching characteristics over recommended operating conditions during reset‡|| (see Figure 28)
−200
NO.
2
3
4
5
6
7
8
9
PARAMETER
td(RSTL-CKO2IV)
td(RSTH-CKO2V)
Delay time, RESET low to CLKOUT2 invalid
td(RSTL-HIGHIV)
td(RSTH-HIGHV)
Delay time, RESET low to high group invalid
td(RSTL-LOWIV)
td(RSTH-LOWV)
Delay time, RESET low to low group invalid
td(RSTL-ZHZ)
td(RSTH-ZV)
Delay time, RESET low to Z group high impedance
MIN
P
Delay time, RESET high to CLKOUT2 valid
P
ns
ns
4P
P
Delay time, RESET high to low group valid
UNIT
ns
4P
Delay time, RESET high to high group valid
Delay time, RESET high to Z group valid
MAX
ns
ns
4P
P
ns
ns
4P
ns
‡ P = 1/CPU clock frequency in ns. For example, when running parts at 200 MHz, use P = 5 ns.
|| High group consists of:
HOLDA
Low group consists of:
IACK, INUM[3:0], DMAC[3:0], PD, TOUT0, and TOUT1, XSP_CLK, XSP_DO, and XSP_CS
Z group consists of:
EA[21:2], ED[31:0], CE[3:0], BE[3:0], ARE, AWE, AOE, SDCAS/SSADS, SDRAS/SSOE, SDWE/SSWE,
SDA10, CLKX0, CLKX1, FSX0, FSX1, DX0, DX1, CLKR0, CLKR1, FSR0, FSR1, AD[31:0],
PCBE[3:0], PINTA, PREQ, PSERR, PPERR, PDEVSEL, PFRAME, PIRDY, PPAR, PSTOP, PTRDY, and PME
48
POST OFFICE BOX 1443
• HOUSTON, TEXAS 77251−1443
SPRS106G − OCTOBER 1999 − REVISED JULY 2006
RESET TIMING (CONTINUED)
1
10
11
RESET
2
3
4
5
6
7
8
9
CLKOUT2
HIGH GROUP†
LOW GROUP†
Z GROUP†
Boot Configuration
ED[31:0]‡
† High group consists of:
Low group consists of:
Z group consists of:
HOLDA
IACK, INUM[3:0], DMAC[3:0], PD, TOUT0, and TOUT1, XSP_CLK, XSP_DO, and XSP_CS
EA[21:2], ED[31:0], CE[3:0], BE[3:0], ARE, AWE, AOE, SDCAS/SSADS, SDRAS/SSOE, SDWE/SSWE,
SDA10, CLKX0, CLKX1, FSX0, FSX1, DX0, DX1, CLKR0, CLKR1, FSR0, FSR1, AD[31:0],
PCBE[3:0], PINTA, PREQ, PSERR, PPERR, PDEVSEL, PFRAME, PIRDY, PPAR, PSTOP, PTRDY, and PME
‡ ED[31:0] are the boot configuration pins during device reset.
Figure 28. Reset Timing
POST OFFICE BOX 1443
• HOUSTON, TEXAS 77251−1443
49
SPRS106G − OCTOBER 1999 − REVISED JULY 2006
EXTERNAL INTERRUPT TIMING
timing requirements for interrupt response cycles† (see Figure 29)
−200
NO.
2
MIN
tw(ILOW)
tw(IHIGH)
MAX
UNIT
Width of the interrupt pulse low
2P
ns
3
Width of the interrupt pulse high
† P = 1/CPU clock frequency in ns. For example, when running parts at 200 MHz, use P = 5 ns.
2P
ns
switching characteristics over recommended operating conditions during interrupt response
cycles† (see Figure 29)
−200
NO.
1
4
5
PARAMETER
MIN
MAX
9P
tR(EINTH − IACKH)
td(CKO2L-IACKV)
Response time, EXT_INTx high to IACK high
Delay time, CLKOUT2 low to IACK valid
0
10
ns
td(CKO2L-INUMV)
td(CKO2L-INUMIV)
Delay time, CLKOUT2 low to INUMx valid
0
10
ns
0
10
ns
6
Delay time, CLKOUT2 low to INUMx invalid
† P = 1/CPU clock frequency in ns. For example, when running parts at 200 MHz, use P = 5 ns.
ns
1
CLKOUT2
2
3
EXT_INTx, NMI
Intr Flag
4
4
IACK
6
5
Interrupt Number
INUMx
Figure 29. Interrupt Timing
50
UNIT
POST OFFICE BOX 1443
• HOUSTON, TEXAS 77251−1443
SPRS106G − OCTOBER 1999 − REVISED JULY 2006
PCI I/O TIMINGS
timing requirements for PCI inputs (see Figure 30)
−200
NO.
5
6
MIN
tsu(IV-PCLKH)
th(IV-PCLKH)
MAX
UNIT
Setup time, input valid before PCLK high
7
ns
Hold time, input valid after PCLK high
0
ns
switching characteristics over recommended operating conditions for PCI outputs (see Figure 30)
−200
NO.
1
2
3
4
PARAMETER
MIN
MAX
11
UNIT
td(PCLKH-OV)
td(PCLKH-OIV)
Delay time, PCLK high to output valid
Delay time, PCLK high to output invalid
2
ns
td(PCLKH-OLZ)
td(PCLKH-OHZ)
Delay time, PCLK high to output low impedance
2
ns
Delay time, PCLK high to output high impedance
28
ns
ns
PCLK
1
2
Valid
PCI Output
3
4
Valid
PCI Input
5
6
Figure 30. PCI Intput/Output Timings
POST OFFICE BOX 1443
• HOUSTON, TEXAS 77251−1443
51
SPRS106G − OCTOBER 1999 − REVISED JULY 2006
PCI RESET TIMING
timing requirements for PCI reset (see Figure 31)
−200
NO.
1
2
MIN
tw(PRST)
tsu(PCLKA-PRSTH)
Pulse duration, PRST
Setup time, PCLK active before PRST high
PCLK
1
PRST
2
Figure 31. PCI Reset (PRST) Timings
52
POST OFFICE BOX 1443
• HOUSTON, TEXAS 77251−1443
MAX
UNIT
1
ms
100
µs
SPRS106G − OCTOBER 1999 − REVISED JULY 2006
PCI SERIAL EEPROM INTERFACE TIMING
timing requirements for serial EEPROM interface (see Figure 32)
−200
NO.
8
MIN
tsu(DIV-CLKH)
th(CLKH-DIV)
9
Setup time, XSP_DI valid before XSP_CLK high
MAX
UNIT
50
ns
0
ns
Hold time, XSP_DI valid after XSP_CLK high
switching characteristics over recommended operating conditions for serial EEPROM interface†
(see Figure 32)
−200
NO.
1
2
3
4
5
6
PARAMETER
MIN
NOM
MAX
UNIT
tw(CSL)
td(CLKL-CSL)
Pulse duration, XSP_CS low
td(CSH-CLKH)
tw(CLKH)
Delay time, XSP_CS high to XSP_CLK high
Pulse duration, XSP_CLK high
1023P
ns
tw(CLKL)
tosu(DOV-CLKH)
Pulse duration, XSP_CLK low
1023P
ns
Output setup time, XSP_DO valid after XSP_CLK high
1023P
ns
1023P
ns
Delay time, XSP_CLK low to XSP_CS low
7
toh(CLKH-DOV)
Output hold time, XSP_DO valid after XSP_CLK high
† P = 1/CPU clock frequency in ns. For example, when running parts at 200 MHz, use P = 5 ns.
2046P
ns
0
ns
1023P
ns
2
1
XSP_CS
3
4
5
XSP_CLK
6
7
XSP_DO
8
9
XSP_DI
Figure 32. PCI Serial EEPROM Interface Timing
POST OFFICE BOX 1443
• HOUSTON, TEXAS 77251−1443
53
SPRS106G − OCTOBER 1999 − REVISED JULY 2006
MULTICHANNEL BUFFERED SERIAL PORT TIMING
timing requirements for McBSP†‡ (see Figure 33)
−200
NO.
2
3
tc(CKRX)
tw(CKRX)
Cycle time, CLKR/X
CLKR/X ext
MIN
2P§
Pulse duration, CLKR/X high or CLKR/X low
CLKR/X ext
P −1¶
5
tsu(FRH-CKRL)
Setup time, external FSR high before CLKR low
6
th(CKRL-FRH)
Hold time, external FSR high after CLKR low
7
tsu(DRV-CKRL)
Setup time, DR valid before CLKR low
8
th(CKRL-DRV)
Hold time, DR valid after CLKR low
10
tsu(FXH-CKXL)
Setup time, external FSX high before CLKX low
11
th(CKXL-FXH)
Hold time, external FSX high after CLKX low
CLKR int
9
CLKR ext
2
CLKR int
6
CLKR ext
3
CLKR int
8
CLKR ext
0.5
CLKR int
4
CLKR ext
3
CLKX int
9
CLKX ext
2
CLKX int
6
CLKX ext
3
MAX
UNIT
ns
ns
ns
ns
ns
ns
ns
ns
† CLKRP = CLKXP = FSRP = FSXP = 0. If the polarity of any of the signals is inverted, then the timing references of that signal are also inverted.
‡ P = 1/CPU clock frequency in ns. For example, when running parts at 200 MHz, use P = 5 ns.
§ The maximum bit rate for the C6205 devices is 100 Mbps or CPU/2 (the slower of the two). Care must be taken to ensure that the AC timings
specified in this data sheet are met. The maximum bit rate for McBSP-to-McBSP communications is 100 MHz; therefore, the minimum CLKR/X
clock cycle is either twice the CPU cycle time (2P), or 10 ns (100 MHz), whichever value is larger. For example, when running parts at 200 MHz
(P = 5 ns), use 10 ns as the minimum CLKR/X clock cycle (by setting the appropriate CLKGDV ratio or external clock source). When running
parts at 100 MHz (P = 10 ns), use 2P = 20 ns (50 MHz) as the minimum CLKR/X clock cycle. The maximum bit rate for McBSP-to-McBSP
communications applies when the serial port is a master of the clock and frame syncs (with CLKR connected to CLKX, FSR connected to FSX,
CLKXM = FSXM = 1, and CLKRM = FSRM = 0) in data delay 1 or 2 mode (R/XDATDLY = 01b or 10b) and the other device the McBSP
communicates to is a slave.
¶ The minimum CLKR/X pulse duration is either (P −1) or 4 ns, whichever is larger. For example, when running parts at 200 MHz (P = 5 ns), use
4 ns as the minimum CLKR/X pulse duration. When running parts at 100 MHz (P = 10 ns), use (P −1) = 9 ns as the minimum CLKR/X pulse
duration.
54
POST OFFICE BOX 1443
• HOUSTON, TEXAS 77251−1443
SPRS106G − OCTOBER 1999 − REVISED JULY 2006
MULTICHANNEL BUFFERED SERIAL PORT TIMING (CONTINUED)
switching characteristics over recommended operating conditions for McBSP†‡ (see Figure 33)
−200
NO.
PARAMETER
Delay time, CLKS high to CLKR/X high for internal
CLKR/X generated from CLKS input
MAX
3
12
2P−2§¶
C − 2#
C + 2#
ns
ns
1
td(CKSH-CKRXH)
2
Cycle time, CLKR/X
3
tc(CKRX)
tw(CKRX)
Pulse duration, CLKR/X high or CLKR/X low
CLKR/X int
4
td(CKRH-FRV)
Delay time, CLKR high to internal FSR valid
CLKR int
−3
3
CLKX int
−3
3
CLKX ext
3
9
CLKX int
−1
4
CLKX ext
3
9
CLKX int
−1
4
CLKX ext
2
12
FSX int
−1
5
FSX ext
2
12
CLKR/X int
9
td(CKXH-FXV)
Delay time, CLKX high to internal FSX valid
12
tdis(CKXH-DXHZ)
Disable time, DX high impedance following last data bit from
CLKX high
13
td(CKXH-DXV)
Delay time, CLKX high to DX valid
14
td(FXH-DXV)
Delay time, FSX high to DX valid
ONLY applies when in data delay 0 (XDATDLY = 00b) mode.
UNIT
MIN
ns
ns
ns
ns
ns
ns
† CLKRP = CLKXP = FSRP = FSXP = 0. If the polarity of any of the signals is inverted, then the timing references of that signal are also inverted.
‡ Minimum delay times also represent minimum output hold times.
§ P = 1/CPU clock frequency in ns. For example, when running parts at 200 MHz, use P = 5 ns.
¶ The maximum bit rate for the C6205 devices is 100 Mbps or CPU/2 (the slower of the two). Care must be taken to ensure that the AC timings
specified in this data sheet are met. The maximum bit rate for McBSP-to-McBSP communications is 100 MHz; therefore, the minimum CLKR/X
clock cycle is either twice the CPU cycle time (2P), or 10 ns (100 MHz), whichever value is larger. For example, when running parts at 200 MHz
(P = 5 ns), use 10 ns as the minimum CLKR/X clock cycle (by setting the appropriate CLKGDV ratio or external clock source). When running
parts at 100 MHz (P = 10 ns), use 2P = 20 ns (50 MHz) as the minimum CLKR/X clock cycle. The maximum bit rate for McBSP-to-McBSP
communications applies when the serial port is a master of the clock and frame syncs (with CLKR connected to CLKX, FSR connected to FSX,
CLKXM = FSXM = 1, and CLKRM = FSRM = 0) in data delay 1 or 2 mode (R/XDATDLY = 01b or 10b) and the other device the McBSP
communicates to is a slave.
# C = H or L
S = sample rate generator input clock = P if CLKSM = 1 (P = 1/CPU clock frequency)
= sample rate generator input clock = P_clks if CLKSM = 0 (P_clks = CLKS period)
H = CLKX high pulse width = (CLKGDV/2 + 1) * S if CLKGDV is even
= (CLKGDV + 1)/2 * S if CLKGDV is odd or zero
L = CLKX low pulse width = (CLKGDV/2) * S if CLKGDV is even
= (CLKGDV + 1)/2 * S if CLKGDV is odd or zero
CLKGDV should be set appropriately to ensure the McBSP bit rate does not exceed the 100-MHz limit.
POST OFFICE BOX 1443
• HOUSTON, TEXAS 77251−1443
55
SPRS106G − OCTOBER 1999 − REVISED JULY 2006
MULTICHANNEL BUFFERED SERIAL PORT TIMING (CONTINUED)
CLKS
1
2
3
3
CLKR
4
4
FSR (int)
5
6
FSR (ext)
7
DR
8
Bit(n-1)
(n-2)
(n-3)
2
3
3
CLKX
9
FSX (int)
11
10
FSX (ext)
FSX (XDATDLY=00b)
12
DX
Bit 0
14
13
Bit(n-1)
13
(n-2)
Figure 33. McBSP Timings
56
POST OFFICE BOX 1443
• HOUSTON, TEXAS 77251−1443
(n-3)
SPRS106G − OCTOBER 1999 − REVISED JULY 2006
MULTICHANNEL BUFFERED SERIAL PORT TIMING (CONTINUED)
timing requirements for FSR when GSYNC = 1 (see Figure 34)
−200
NO.
1
2
MIN
tsu(FRH-CKSH)
th(CKSH-FRH)
MAX
UNIT
Setup time, FSR high before CLKS high
4
ns
Hold time, FSR high after CLKS high
4
ns
CLKS
1
2
FSR external
CLKR/X (no need to resync)
CLKR/X (needs resync)
Figure 34. FSR Timing When GSYNC = 1
POST OFFICE BOX 1443
• HOUSTON, TEXAS 77251−1443
57
SPRS106G − OCTOBER 1999 − REVISED JULY 2006
MULTICHANNEL BUFFERED SERIAL PORT TIMING (CONTINUED)
timing requirements for McBSP as SPI master or slave: CLKSTP = 10b, CLKXP = 0†‡ (see Figure 35)
−200
MASTER
NO.
MIN
4
5
tsu(DRV-CKXL)
th(CKXL-DRV)
Setup time, DR valid before CLKX low
Hold time, DR valid after CLKX low
SLAVE
MAX
MIN
UNIT
MAX
12
2 − 3P
ns
4
6 + 6P
ns
† P = 1/CPU clock frequency in ns. For example, when running parts at 200 MHz, use P = 5 ns.
‡ For all SPI slave modes, CLKG is programmed as 1/2 of the CPU clock by setting CLKSM = CLKGDV = 1.
switching characteristics over recommended operating conditions for McBSP as SPI master or
slave: CLKSTP = 10b, CLKXP = 0†‡ (see Figure 35)
−200
NO.
MASTER§
PARAMETER
2
th(CKXL-FXL)
td(FXL-CKXH)
Hold time, FSX low after CLKX low¶
Delay time, FSX low to CLKX high#
3
td(CKXH-DXV)
Delay time, CLKX high to DX valid
6
tdis(CKXL-DXHZ)
Disable time, DX high impedance following last data bit from
CLKX low
7
tdis(FXH-DXHZ)
Disable time, DX high impedance following last data bit from
FSX high
1
SLAVE
MIN
UNIT
MIN
MAX
T−3
T+5
ns
L−4
L+5
ns
−4
5
L−2
L+3
3P + 3
MAX
5P + 17
ns
ns
P+3
3P + 17
ns
8
td(FXL-DXV)
Delay time, FSX low to DX valid
2P + 2 4P + 17
ns
† P = 1/CPU clock frequency in ns. For example, when running parts at 200 MHz, use P = 5 ns.
‡ For all SPI slave modes, CLKG is programmed as 1/2 of the CPU clock by setting CLKSM = CLKGDV = 1.
§ S = sample rate generator input clock = P if CLKSM = 1 (P = 1/CPU clock frequency)
= sample rate generator input clock = P_clks if CLKSM = 0 (P_clks = CLKS period)
T = CLKX period = (1 + CLKGDV) * S
H = CLKX high pulse width = (CLKGDV/2 + 1) * S if CLKGDV is even
= (CLKGDV + 1)/2 * S if CLKGDV is odd or zero
L = CLKX low pulse width = (CLKGDV/2) * S if CLKGDV is even
= (CLKGDV + 1)/2 * S if CLKGDV is odd or zero
¶ FSRP = FSXP = 1. As a SPI master, FSX is inverted to provide active-low slave-enable output. As a slave, the active-low signal input on FSX
and FSR is inverted before being used internally.
CLKXM = FSXM = 1, CLKRM = FSRM = 0 for master McBSP
CLKXM = CLKRM = FSXM = FSRM = 0 for slave McBSP
# FSX should be low before the rising edge of clock to enable slave devices and then begin a SPI transfer at the rising edge of the master clock
(CLKX).
58
POST OFFICE BOX 1443
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SPRS106G − OCTOBER 1999 − REVISED JULY 2006
MULTICHANNEL BUFFERED SERIAL PORT TIMING (CONTINUED)
CLKX
1
2
FSX
7
6
DX
8
3
Bit 0
Bit(n-1)
4
DR
Bit 0
(n-2)
(n-3)
(n-4)
5
Bit(n-1)
(n-2)
(n-3)
(n-4)
Figure 35. McBSP Timing as SPI Master or Slave: CLKSTP = 10b, CLKXP = 0
POST OFFICE BOX 1443
• HOUSTON, TEXAS 77251−1443
59
SPRS106G − OCTOBER 1999 − REVISED JULY 2006
MULTICHANNEL BUFFERED SERIAL PORT TIMING (CONTINUED)
timing requirements for McBSP as SPI master or slave: CLKSTP = 11b, CLKXP = 0†‡ (see Figure 36)
−200
MASTER
NO.
MIN
4
5
tsu(DRV-CKXH)
th(CKXH-DRV)
Setup time, DR valid before CLKX high
SLAVE
MAX
MIN
UNIT
MAX
12
2 − 3P
ns
4
5 + 6P
ns
Hold time, DR valid after CLKX high
† P = 1/CPU clock frequency in ns. For example, when running parts at 200 MHz, use P = 5 ns.
‡ For all SPI slave modes, CLKG is programmed as 1/2 of the CPU clock by setting CLKSM = CLKGDV = 1.
switching characteristics over recommended operating conditions for McBSP as SPI master or
slave: CLKSTP = 11b, CLKXP = 0†‡ (see Figure 36)
−200
NO.
MASTER§
PARAMETER
MIN
2
th(CKXL-FXL)
td(FXL-CKXH)
Hold time, FSX low after CLKX low¶
Delay time, FSX low to CLKX high#
3
td(CKXL-DXV)
tdis(CKXL-DXHZ)
1
6
MAX
SLAVE
MIN
UNIT
MAX
L−2
L+3
ns
T−2
T+3
ns
Delay time, CLKX low to DX valid
−2
4
3P + 4
5P + 17
ns
Disable time, DX high impedance following last data bit from
CLKX low
−2
4
3P + 3
5P + 17
ns
7
td(FXL-DXV)
Delay time, FSX low to DX valid
H − 2 H + 4 2P + 2 4P + 17
ns
† P = 1/CPU clock frequency in ns. For example, when running parts at 200 MHz, use P = 5 ns.
‡ For all SPI slave modes, CLKG is programmed as 1/2 of the CPU clock by setting CLKSM = CLKGDV = 1.
§ S = sample rate generator input clock = P if CLKSM = 1 (P = 1/CPU clock frequency)
= sample rate generator input clock = P_clks if CLKSM = 0 (P_clks = CLKS period)
T = CLKX period = (1 + CLKGDV) * S
H = CLKX high pulse width = (CLKGDV/2 + 1) * S if CLKGDV is even
= (CLKGDV + 1)/2 * S if CLKGDV is odd or zero
L = CLKX low pulse width = (CLKGDV/2) * S if CLKGDV is even
= (CLKGDV + 1)/2 * S if CLKGDV is odd or zero
¶ FSRP = FSXP = 1. As a SPI master, FSX is inverted to provide active-low slave-enable output. As a slave, the active-low signal input on FSX
and FSR is inverted before being used internally.
CLKXM = FSXM = 1, CLKRM = FSRM = 0 for master McBSP
CLKXM = CLKRM = FSXM = FSRM = 0 for slave McBSP
# FSX should be low before the rising edge of clock to enable slave devices and then begin a SPI transfer at the rising edge of the master clock
(CLKX).
CLKX
1
2
6
Bit 0
7
FSX
DX
3
Bit(n-1)
4
DR
Bit 0
(n-2)
(n-3)
(n-4)
5
Bit(n-1)
(n-2)
(n-3)
(n-4)
Figure 36. McBSP Timing as SPI Master or Slave: CLKSTP = 11b, CLKXP = 0
60
POST OFFICE BOX 1443
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SPRS106G − OCTOBER 1999 − REVISED JULY 2006
MULTICHANNEL BUFFERED SERIAL PORT TIMING (CONTINUED)
timing requirements for McBSP as SPI master or slave: CLKSTP = 10b, CLKXP = 1†‡ (see Figure 37)
−200
MASTER
NO.
MIN
4
5
tsu(DRV-CKXH)
th(CKXH-DRV)
Setup time, DR valid before CLKX high
SLAVE
MAX
MIN
UNIT
MAX
12
2 − 3P
ns
4
5 + 6P
ns
Hold time, DR valid after CLKX high
† P = 1/CPU clock frequency in ns. For example, when running parts at 200 MHz, use P = 5 ns.
‡ For all SPI slave modes, CLKG is programmed as 1/2 of the CPU clock by setting CLKSM = CLKGDV = 1.
switching characteristics over recommended operating conditions for McBSP as SPI master or
slave: CLKSTP = 10b, CLKXP = 1†‡ (see Figure 37)
−200
NO.
MASTER§
PARAMETER
MIN
2
th(CKXH-FXL)
td(FXL-CKXL)
Hold time, FSX low after CLKX high¶
Delay time, FSX low to CLKX low#
3
td(CKXL-DXV)
Delay time, CLKX low to DX valid
6
tdis(CKXH-DXHZ)
Disable time, DX high impedance following last data bit from
CLKX high
7
tdis(FXH-DXHZ)
Disable time, DX high impedance following last data bit from
FSX high
1
MAX
SLAVE
MIN
UNIT
MAX
T−2
T+3
ns
H−2
H+3
ns
−2
4
H−2
H+3
3P + 4
5P + 17
ns
ns
P+3
3P + 17
ns
8
td(FXL-DXV)
Delay time, FSX low to DX valid
2P + 2 4P + 17
ns
† P = 1/CPU clock frequency in ns. For example, when running parts at 200 MHz, use P = 5 ns.
‡ For all SPI slave modes, CLKG is programmed as 1/2 of the CPU clock by setting CLKSM = CLKGDV = 1.
§ S = sample rate generator input clock = P if CLKSM = 1 (P = 1/CPU clock frequency)
= sample rate generator input clock = P_clks if CLKSM = 0 (P_clks = CLKS period)
T = CLKX period = (1 + CLKGDV) * S
H = CLKX high pulse width = (CLKGDV/2 + 1) * S if CLKGDV is even
= (CLKGDV + 1)/2 * S if CLKGDV is odd or zero
L = CLKX low pulse width = (CLKGDV/2) * S if CLKGDV is even
= (CLKGDV + 1)/2 * S if CLKGDV is odd or zero
¶ FSRP = FSXP = 1. As a SPI master, FSX is inverted to provide active-low slave-enable output. As a slave, the active-low signal input on FSX
and FSR is inverted before being used internally.
CLKXM = FSXM = 1, CLKRM = FSRM = 0 for master McBSP
CLKXM = CLKRM = FSXM = FSRM = 0 for slave McBSP
# FSX should be low before the rising edge of clock to enable slave devices and then begin a SPI transfer at the rising edge of the master clock
(CLKX).
POST OFFICE BOX 1443
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61
SPRS106G − OCTOBER 1999 − REVISED JULY 2006
MULTICHANNEL BUFFERED SERIAL PORT TIMING (CONTINUED)
CLKX
1
2
FSX
7
6
DX
8
3
Bit 0
Bit(n-1)
4
DR
Bit 0
(n-2)
(n-3)
(n-4)
5
Bit(n-1)
(n-2)
(n-3)
(n-4)
Figure 37. McBSP Timing as SPI Master or Slave: CLKSTP = 10b, CLKXP = 1
62
POST OFFICE BOX 1443
• HOUSTON, TEXAS 77251−1443
SPRS106G − OCTOBER 1999 − REVISED JULY 2006
MULTICHANNEL BUFFERED SERIAL PORT TIMING (CONTINUED)
timing requirements for McBSP as SPI master or slave: CLKSTP = 11b, CLKXP = 1†‡ (see Figure 38)
−200
MASTER
NO.
MIN
4
5
tsu(DRV-CKXL)
th(CKXL-DRV)
Setup time, DR valid before CLKX low
SLAVE
MAX
MIN
UNIT
MAX
12
2 − 3P
ns
4
5 + 6P
ns
Hold time, DR valid after CLKX low
† P = 1/CPU clock frequency in ns. For example, when running parts at 200 MHz, use P = 5 ns.
‡ For all SPI slave modes, CLKG is programmed as 1/2 of the CPU clock by setting CLKSM = CLKGDV = 1.
switching characteristics over recommended operating conditions for McBSP as SPI master or
slave: CLKSTP = 11b, CLKXP = 1†‡ (see Figure 38)
−200
NO.
MASTER§
PARAMETER
SLAVE
MIN
UNIT
MIN
MAX
MAX
H−2
H+3
ns
T−2
T+1
ns
2
th(CKXH-FXL)
td(FXL-CKXL)
Hold time, FSX low after CLKX high¶
Delay time, FSX low to CLKX low#
3
td(CKXH-DXV)
Delay time, CLKX high to DX valid
−2
4
3P + 4
5P + 17
ns
tdis(CKXH-DXHZ)
Disable time, DX high impedance following last data bit from
CLKX high
−2
4
3P + 3
5P + 17
ns
1
6
7
td(FXL-DXV)
Delay time, FSX low to DX valid
L−2
L+4
2P + 2 4P + 17
ns
† P = 1/CPU clock frequency in ns. For example, when running parts at 200 MHz, use P = 5 ns.
‡ For all SPI slave modes, CLKG is programmed as 1/2 of the CPU clock by setting CLKSM = CLKGDV = 1.
§ S = sample rate generator input clock = P if CLKSM = 1 (P = 1/CPU clock frequency)
= sample rate generator input clock = P_clks if CLKSM = 0 (P_clks = CLKS period)
T = CLKX period = (1 + CLKGDV) * S
H = CLKX high pulse width = (CLKGDV/2 + 1) * S if CLKGDV is even
= (CLKGDV + 1)/2 * S if CLKGDV is odd or zero
L = CLKX low pulse width = (CLKGDV/2) * S if CLKGDV is even
= (CLKGDV + 1)/2 * S if CLKGDV is odd or zero
¶ FSRP = FSXP = 1. As a SPI master, FSX is inverted to provide active-low slave-enable output. As a slave, the active-low signal input on FSX
and FSR is inverted before being used internally.
CLKXM = FSXM = 1, CLKRM = FSRM = 0 for master McBSP
CLKXM = CLKRM = FSXM = FSRM = 0 for slave McBSP
# FSX should be low before the rising edge of clock to enable slave devices and then begin a SPI transfer at the rising edge of the master clock
(CLKX).
CLKX
1
2
FSX
7
6
DX
3
Bit 0
Bit(n-1)
4
DR
Bit 0
(n-2)
(n-3)
(n-4)
5
Bit(n-1)
(n-2)
(n-3)
(n-4)
Figure 38. McBSP Timing as SPI Master or Slave: CLKSTP = 11b, CLKXP = 1
POST OFFICE BOX 1443
• HOUSTON, TEXAS 77251−1443
63
SPRS106G − OCTOBER 1999 − REVISED JULY 2006
DMAC, TIMER, POWER-DOWN TIMING
switching characteristics over recommended operating conditions for DMAC outputs†
(see Figure 39)
−200
NO.
PARAMETER
MIN
1
tw(DMACH) Pulse duration, DMAC high
† P = 1/CPU clock frequency in ns. For example, when running parts at 200 MHz, use P = 5 ns.
MAX
2P −3
UNIT
ns
1
DMAC[3:0]
Figure 39. DMAC Timing
timing requirements for timer inputs† (see Figure 40)
−200
NO.
1
2
MIN
tw(TINPH)
tw(TINPL)
MAX
UNIT
Pulse duration, TINP high
2P
ns
Pulse duration, TINP low
2P
ns
† P = 1/CPU clock frequency in ns. For example, when running parts at 200 MHz, use P = 5 ns.
switching characteristics over recommended operating conditions for timer outputs†
(see Figure 40)
−200
NO.
3
PARAMETER
tw(TOUTH)
tw(TOUTL)
MIN
Pulse duration, TOUT high
4
Pulse duration, TOUT low
† P = 1/CPU clock frequency in ns. For example, when running parts at 200 MHz, use P = 5 ns.
2
1
TINPx
4
3
TOUTx
Figure 40. Timer Timing
64
POST OFFICE BOX 1443
• HOUSTON, TEXAS 77251−1443
MAX
UNIT
2P −3
ns
2P −3
ns
SPRS106G − OCTOBER 1999 − REVISED JULY 2006
DMAC, TIMER, POWER-DOWN TIMING (CONTINUED)
switching characteristics over recommended operating conditions for power-down outputs†
(see Figure 41)
−200
NO.
PARAMETER
MIN
1
tw(PDH)
Pulse duration, PD high
† P = 1/CPU clock frequency in ns. For example, when running parts at 200 MHz, use P = 5 ns.
2P
MAX
UNIT
ns
1
PD
Figure 41. Power-Down Timing
POST OFFICE BOX 1443
• HOUSTON, TEXAS 77251−1443
65
SPRS106G − OCTOBER 1999 − REVISED JULY 2006
JTAG TEST-PORT TIMING
timing requirements for JTAG test port (see Figure 42)
−200
NO.
1
MIN
MAX
UNIT
Cycle time, TCK
35
ns
3
tc(TCK)
tsu(TDIV-TCKH)
Setup time, TDI/TMS/TRST valid before TCK high
11
ns
4
th(TCKH-TDIV)
Hold time, TDI/TMS/TRST valid after TCK high
9
ns
switching characteristics over recommended operating conditions for JTAG test port
(see Figure 42)
−200
NO.
2
PARAMETER
td(TCKL-TDOV)
Delay time, TCK low to TDO valid
MIN
MAX
−4.5
12
1
TCK
2
2
TDO
4
3
TDI/TMS/TRST
Figure 42. JTAG Test-Port Timing
66
POST OFFICE BOX 1443
• HOUSTON, TEXAS 77251−1443
UNIT
ns
SPRS106G − OCTOBER 1999 − REVISED JULY 2006
MECHANICAL DATA FOR TMS320C6205
The following table(s) show the thermal resistance characteristics for the S−PBGA mechanical package.
thermal resistance characteristics (S-PBGA package) (GHK)
NO
1
°C/W
Air Flow (m/s†)
RΘJC
RΘJA
Junction-to-case
9.5
N/A
Junction-to-free air
26.5
0.00
RΘJA
RΘJA
Junction-to-free air
23.9
0.50
Junction-to-free air
22.6
1.00
5
RΘJA
Junction-to-free air
† m/s = meters per second
21.3
2.00
°C/W
Air Flow (m/s†)
2
3
4
thermal resistance characteristics (S-PBGA package) (ZHK)
NO
1
RΘJC
RΘJA
Junction-to-case
9.5
N/A
Junction-to-free air
26.5
0.00
RΘJA
RΘJA
Junction-to-free air
23.9
0.50
Junction-to-free air
22.6
1.00
RΘJA
Junction-to-free air
† m/s = meters per second
21.3
2.00
2
3
4
5
POST OFFICE BOX 1443
• HOUSTON, TEXAS 77251−1443
67
SPRS106G − OCTOBER 1999 − REVISED JULY 2006
packaging information
The following packaging information and addendum reflect the most current released data available for the
designated device(s). This data is subject to change without notice and without revision of this document.
68
POST OFFICE BOX 1443
• HOUSTON, TEXAS 77251−1443
PACKAGE OPTION ADDENDUM
www.ti.com
17-Apr-2019
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (°C)
Device Marking
(4/5)
TMS320C6205DGHK200
NRND
BGA
MICROSTAR
GHK
288
90
TBD
SNPB
Level-3-220C-168 HR
0 to 90
320C6205DGHK
200
TMS
TMS320C6205DZHK200
NRND
BGA
MICROSTAR
ZHK
288
90
Green (RoHS
& no Sb/Br)
SNAGCU
Level-3-260C-168 HR
0 to 90
320C6205DZHK
200
TMS
TMS320C6205GHK200
NRND
BGA
MICROSTAR
GHK
288
90
TBD
SNPB
Level-3-220C-168 HR
0 to 90
320C6205GHK
200
TMS
TMS320C6205GHKA200
NRND
BGA
MICROSTAR
GHK
288
90
TBD
SNPB
Level-3-220C-168 HR
-40 to 105
C6205GHK200
A
TMS320
TMS320C6205ZHK200
NRND
BGA
MICROSTAR
ZHK
288
90
Green (RoHS
& no Sb/Br)
SNAGCU
Level-3-260C-168 HR
0 to 90
320C6205ZHK
200
TMS
TMS32C6205DGHKA200
NRND
BGA
MICROSTAR
GHK
288
90
TBD
SNPB
Level-3-220C-168 HR
-40 to 105
C6205DGHK200
A
TMS320
TMS32C6205DZHKA200
NRND
BGA
MICROSTAR
ZHK
288
90
Green (RoHS
& no Sb/Br)
SNAGCU
Level-3-260C-168 HR
-40 to 105
C6205DZHK200
A
TMS320
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
(4)
17-Apr-2019
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
IMPORTANT NOTICE AND DISCLAIMER
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