Texas Instruments | SM320VC5510A-EP Fixed-Point Digital Signal Processor (Rev. A) | Datasheet | Texas Instruments SM320VC5510A-EP Fixed-Point Digital Signal Processor (Rev. A) Datasheet

Texas Instruments SM320VC5510A-EP Fixed-Point Digital Signal Processor (Rev. A) Datasheet
SM320VC5510A-EP Fixed-Point
Digital Signal Processor
Data Manual
Literature Number: SGUS045A
August 2003 − Revised November 2003
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Contents
Contents
Section
1
2
3
4
5
Page
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
2.1
Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
2.2
Pin Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
2.3
Signal Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Functional Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
3.1
Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
3.1.1
On-Chip Dual-Access RAM (DARAM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
3.1.2
On-Chip Single-Access RAM (SARAM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
3.1.3
On-Chip ROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
3.1.4
Instruction Cache . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
3.1.5
Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
3.1.6
Bootloader . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
3.2
Peripherals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
3.2.1
System Register (SYSR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
3.2.2
Direct Memory Access (DMA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
3.2.3
Enhanced Host Port Interface (EHPI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
3.2.4
General-Purpose Input/Output Port (GPIO) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
3.3
CPU Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
3.4
Peripheral Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
3.5
Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
3.5.1
IFR and IER Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
3.5.2
Interrupt Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
3.6
Notices Concerning CLKOUT Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
3.6.1
CLKOUT Voltage Level . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
3.6.2
CLKOUT Value During Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Documentation Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
4.1
Device and Development-Support Tool Nomenclature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
4.2
320VC5510 Device Nomenclature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
5.1
Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
5.2
Recommended Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
5.3
Electrical Characteristics Over Recommended Operating Case Temperature
Range (Unless Otherwise Noted) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
5.4
Package Thermal Resistance Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
5.5
Timing Parameter Symbology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
5.6
Clock Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
5.6.1
Clock Generation in Bypass Mode (DPLL Disabled) . . . . . . . . . . . . . . . . . . . . . . . . 42
5.6.2
Clock Generation in Lock Mode (DPLL Synthesis Enabled) . . . . . . . . . . . . . . . . . 43
5.7
Memory Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
5.7.1
Asynchronous Memory Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
5.7.2
Synchronous-Burst SRAM (SBSRAM) Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
5.7.3
Synchronous DRAM (SDRAM) Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
5.8
HOLD and HOLDA Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
5.9
Reset Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
5.10
External Interrupt Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
August 2003 − Revised November 2003
SGUS045A
iii
Contents
5.11
5.12
5.13
5.14
6
iv
XF Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
General-Purpose Input/Output (IOx) Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
TIN/TOUT Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Multichannel Buffered Serial Port (McBSP) Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.14.1
McBSP Transmit and Receive Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.14.2
McBSP General-Purpose I/O Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.14.3
McBSP as SPI Master or Slave Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.15
Enhanced Host-Port Interface (EHPI) Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Mechanical Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.1
Ball Grid Array (GGW) Package Mechanical Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
SGUS045A
55
56
57
58
58
61
62
66
72
72
August 2003 − Revised November 2003
Figures
List of Figures
Figure
Page
2−1. 320VC5510 GGW MicroStar BGAE Package (Bottom View) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3−1. 320VC5510 Functional Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3−2. 320VC5510 Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3−3. System Register (SYSR) Bit Layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3−4. EHPI Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3−5. I/O Direction Register (IODIR) Bit Layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3−6. I/O Data Register (IODATA) Bit Layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3−7. IFR0, IER0, DBIFR0, and DBIER0 Bit Locations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3−8. IFR1, IER1, DBIFR1, and DBIER1 Bit Locations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4−1. Device Nomenclature for the 320VC5510 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5−1. 3.3-V Test Load Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5−2. Bypass Mode Clock Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5−3. External Multiply-by-N Clock Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5−4. Asynchronous Memory Read Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5−5. Asynchronous Memory Write Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5−6. SBSRAM Read Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5−7. SBSRAM Write Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5−8. Two SDRAM Read Commands (Active Row) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5−9. Two SDRAM WRT Commands (Active Row) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5−10. SDRAM ACTV Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5−11. SDRAM DCAB Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5−12. SDRAM REFR Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5−13. SDRAM MRS Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5−14. HOLD/HOLDA Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5−15. Reset Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5−16. External Interrupt Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5−17. XF Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5−18. General-Purpose Input/Output (IOx) Signal Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5−19. TIN/TOUT Timing When Configured as Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5−20. TIN/TOUT Timing When Configured as Outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5−21. McBSP Receive Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5−22. McBSP Transmit Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5−23. McBSP General-Purpose I/O Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5−24. McBSP Timing as SPI Master or Slave: CLKSTP = 10b, CLKXP = 0 . . . . . . . . . . . . . . . . . . . . . . . . .
5−25. McBSP Timing as SPI Master or Slave: CLKSTP = 11b, CLKXP = 0 . . . . . . . . . . . . . . . . . . . . . . . . .
5−26. McBSP Timing as SPI Master or Slave: CLKSTP = 10b, CLKXP = 1 . . . . . . . . . . . . . . . . . . . . . . . . .
5−27. McBSP Timing as SPI Master or Slave: CLKSTP = 11b, CLKXP = 1 . . . . . . . . . . . . . . . . . . . . . . . . .
5−28. EHPI Nonmultiplexed Read/Write Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5−29. EHPI Multiplexed Memory (HPID) Access Read/Write Timings Without Autoincrement . . . . . . . . . .
5−30. EHPI Multiplexed Memory (HPID) Access Read Timings With Autoincrement . . . . . . . . . . . . . . . . . .
August 2003 − Revised November 2003
3
12
15
17
19
20
20
34
34
37
40
42
43
45
46
48
48
50
50
51
51
52
52
53
54
55
55
56
57
57
60
60
61
62
63
64
65
67
68
69
SGUS045A
v
Figures
5−31. EHPI Multiplexed Memory (HPID) Access Write Timings With Autoincrement . . . . . . . . . . . . . . . . . . 70
5−32. EHPI Multiplexed Register Access Read/Write Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
6−1. 320VC5510 240-Ball MicroStar BGAE Plastic Ball Grid Array Package . . . . . . . . . . . . . . . . . . . . . . . . 72
vi
SGUS045A
August 2003 − Revised November 2003
Tables
List of Tables
Table
Page
2−1. Pin Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2−2. Signal Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3−1. DARAM Blocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3−2. SARAM Blocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3−3. Standard On-Chip ROM Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3−4. 320VC5510 Boot Configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3−5. System Register (SYSR) Bit Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3−6. DMA Sync Events . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3−7. I/O Direction Register (IODIR) Bit Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3−8. I/O Data Register (IODATA) Bit Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3−9. CPU Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3−10. Peripheral Bus Controller Configuration Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3−11. Instruction Cache Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3−12. External Memory Interface Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3−13. DMA Configuration Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3−14. Clock Generator Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3−15. Timer Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3−16. Multichannel Serial Port #0 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3−17. Multichannel Serial Port #1 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3−18. Multichannel Serial Port #2 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3−19. GPIO Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3−20. Device Revision ID Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3−21. Interrupt Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5−1. Thermal Resistance Characteristics (Ambient) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5−2. Thermal Resistance Characteristics (Case) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5−3. CLKIN in Bypass Mode Timing Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5−4. CLKOUT in Bypass Mode Switching Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5−5. CLKIN in Lock Mode Timing Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5−6. CLKOUT in Lock Mode Switching Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5−7. Asynchronous Memory Cycles Timing Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5−8. Asynchronous Memory Cycles Switching Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5−9. Synchronous-Burst SRAM Cycle Timing Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5−10. Synchronous-Burst SRAM Cycle Switching Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5−11. Synchronous DRAM Cycle Timing Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5−12. Synchronous DRAM Cycle Switching Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5−13. HOLD and HOLDA Timing Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5−14. HOLD and HOLDA Switching Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5−15. Reset Timing Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5−16. Reset Switching Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5−17. External Interrupt Timing Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5−18. XF Switching Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5−19. General-Purpose Input/Output (GPIO) Pins Configured as Inputs Timing Requirements . . . . . . . . .
5−20. General-Purpose Input/Output (GPIO) Pins Configured as Inputs Switching Characteristics . . . . .
5−21. TIN/TOUT Pins Configured as Inputs Timing Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5−22. TIN/TOUT Pins Configured as Outputs Switching Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5−23. McBSP Timing Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
August 2003 − Revised November 2003
4
6
13
13
14
16
17
18
20
20
21
23
23
24
25
28
28
29
30
31
32
32
33
40
40
42
42
43
43
44
44
47
47
49
49
53
53
54
54
55
55
56
56
57
57
58
SGUS045A
vii
Tables
5−24.
5−25.
5−26.
5−27.
5−28.
5−29.
5−30.
5−31.
5−32.
5−33.
5−34.
5−35.
5−36.
viii
McBSP Switching Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
McBSP General-Purpose I/O Timing Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
McBSP General-Purpose I/O Switching Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
McBSP as SPI Master or Slave Timing Requirements (CLKSTP = 10b, CLKXP = 0) . . . . . . . . . . . .
McBSP as SPI Master or Slave Switching Characteristics (CLKSTP = 10b, CLKXP = 0) . . . . . . . .
McBSP as SPI Master or Slave Timing Requirements (CLKSTP = 11b, CLKXP = 0) . . . . . . . . . . . .
McBSP as SPI Master or Slave Switching Characteristics (CLKSTP = 11b, CLKXP = 0) . . . . . . . .
McBSP as SPI Master or Slave Timing Requirements (CLKSTP = 10b, CLKXP = 1) . . . . . . . . . . . .
McBSP as SPI Master or Slave Switching Characteristics (CLKSTP = 10b, CLKXP = 1) . . . . . . . .
McBSP as SPI Master or Slave Timing Requirements (CLKSTP = 11b, CLKXP = 1) . . . . . . . . . . . .
McBSP as SPI Master or Slave Switching Characteristics (CLKSTP = 11b, CLKXP = 1) . . . . . . . .
EHPI Timing Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
EHPI Switching Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
SGUS045A
59
61
61
62
62
63
63
64
64
65
65
66
66
August 2003 − Revised November 2003
Features
1
Features
D Controlled Baseline
D
D
D
D
D
D
D
D
− One Assembly/Test Site, One Fabrication
Site
Extended Temperature Performance of
−40°C to 85°C
Enhanced Diminishing Manufacturing
Sources (DMS) Support
Enhanced Product-Change Notification
Qualification Pedigree†
High-Performance, Low-Power,
Fixed-Point 320C55x
Digital Signal Processor (DSP)
− 5-ns Instruction Cycle Time
− 200-MHz Clock Rate
− One/Two Instructions Executed per Cycle
− Dual Multipliers (Up to 400 Million
Multiply-Accumulates Per Second
(MMACS))
− Two Arithmetic/Logic Units
− One Internal Program Bus
− Three Internal Data/Operand Read Buses
− Two Internal Data/Operand Write Buses
Instruction Cache (24K Bytes)
160K x 16-Bit On-Chip RAM Composed of:
− Eight Blocks of 4K × 16-Bit
Dual-Access RAM (DARAM) (64K Bytes)
− 32 Blocks of 4K × 16-Bit
Single-Access RAM (SARAM)
(256K Bytes)
16K × 16-Bit On-Chip ROM (32K Bytes)
D 8M × 16-Bit Maximum Addressable
External Memory Space
D 32-Bit External Memory Interface (EMIF)
D
D
D
D
D
D
D
With Glueless Interface to:
− Asynchronous Static RAM (SRAM)
− Asynchronous EPROM
− Synchronous DRAM (SDRAM)
− Synchronous Burst SRAM (SBSRAM)
Programmable Low-Power Control of Six
Device Functional Domains
On-Chip Peripherals
− Two 20-Bit Timers
− Six-Channel Direct Memory Access
(DMA) Controller
− Three Multichannel Buffered Serial Ports
(McBSPs)
− 16-Bit Parallel Enhanced Host-Port
Interface (EHPI)
− Programmable Digital Phase-Locked
Loop (DPLL) Clock Generator
− Eight General-Purpose I/O (GPIO) Pins
and Dedicated General-Purpose
Output (XF)
On-Chip Scan-Based Emulation Logic
IEEE Std 1149.1‡ (JTAG) Boundary Scan
Logic
240-Terminal MicroStar BGA
(Ball Grid Array) (GGW Suffix)
3.3-V I/O Supply Voltage
1.6-V Core Supply Voltage§
TMS320C55x and MicroStar BGA are trademarks of Texas Instruments.
Other trademarks are the property of their respective owners.
† Component qualification in accordance with JEDEC and industry standards to ensure reliable operation over an extended temperature range.
This includes, but is not limited to, Highly Accelerated Stress Test (HAST) or biased 85/85, temperature cycle, autoclave or unbiased HAST,
electromigration, bond intermetallic life, and mold compound life. Such qualification testing should not be viewed as justifying use of this
component beyond specified performance and environmental limits.
‡ IEEE Standard 1149.1-1990 Standard-Test-Access Port and Boundary Scan Architecture.
§ Some TMX320VC5510 prototype devices may require core supply voltage other than 1.6 V. See the Electrical Specification section of this data
manual for more information. See the TMS320VC5510 Digital Signal Processor Silicon Errata (literature number SPRZ008) for further
clarification and distinguishing markings.
August 2003 − Revised November 2003
SGUS045A
1
Introduction
2
Introduction
This section describes the main features of the 320VC5510 digital signal processor (DSP), lists the pin
assignments, and describes the function of each pin. This data manual also provides a detailed description
section, electrical specifications, parameter measurement information, and mechanical data about the
available packaging.
NOTE: This data manual is designed to be used in conjunction with the TMS320C55x DSP
Functional Overview (literature number SPRU312).
2.1
Description
The 320VC5510 (5510) fixed-point digital signal processor (DSP) is based on the TMS320C55x DSP
generation CPU processor core. The C55x DSP architecture achieves high performance and low power
through increased parallelism and total focus on reduction in power dissipation. The CPU supports an internal
bus structure composed of one program bus, three data-read buses, two-data write buses, and additional
buses dedicated to peripheral and DMA activity. These buses provide the ability to perform up to three data
reads and two data writes in a single cycle. In parallel, the DMA controller can perform up to two data transfers
per cycle independent of the CPU activity.
The C55x CPU provides two multiply-accumulate (MAC) units, each capable of 17-bit x 17-bit multiplication
in a single cycle. A central 40-bit arithmetic/logic unit (ALU) is supported by an additional 16-bit ALU. Use
of the ALUs is under instruction set control, providing the ability to optimize parallel activity and power
consumption. These resources are managed in the address unit (AU) and data unit (DU) of the C55x CPU.
The C55x DSP generation supports a variable byte width instruction set for improved code density. The
instruction unit (IU) performs 32-bit program fetches from internal or external memory and queues instructions
for the program unit (PU). The program unit decodes the instructions, directs tasks to AU and DU resources,
and manages the fully protected pipeline. Predictive branching capability avoids pipeline flushes on execution
of conditional instructions. The 5510 also includes a 24K-byte instruction cache to minimize external memory
accesses, improving data throughput and conserving system power.
The 5510 peripheral set includes an external memory interface (EMIF) that provides glueless access to
asynchronous memories like EPROM and SRAM, as well as to high-speed, high-density memories such as
synchronous DRAM and synchronous burst SRAM. Three full-duplex multichannel buffered serial ports
(McBSPs) provide glueless interface to a variety of industry-standard serial devices, and multichannel
communication with up to 128 separately enabled channels. The enhanced host-port interface (EHPI) is a
16-bit parallel interface used to provide host processor access to internal memory on the 5510. The EHPI can
be configured in either multiplexed or non-multiplexed mode to provide glueless interface to a wider variety
of host processors. The DMA controller provides data movement for six independent channel contexts without
CPU intervention, providing DMA throughput of up to two 16-bit words per cycle. Two general-purpose timers,
eight general-purpose I/O (GPIO) pins, and digital phase-locked loop (DPLL) clock generation are also
included.
The 5510 is supported by the industry’s leading eXpressDSP software environment including the Code
Composer Studio integrated development environment, DSP/BIOS software kernel foundation, the
TMS320 DSP Algorithm Standard, and the industry’s largest third-party network. Code Composer Studio
features code generation tools including a C-Compiler, Visual Linker, simulator, Real-Time Data Exchange
(RTDX), XDS510 emulation device drivers, and Chip Support Libraries (CSL). DSP/BIOS is a scalable
real-time software foundation available for no cost to users of Texas Instruments’ DSP products providing a
preemptive task scheduler and real-time analysis capabilities with very low memory and megahertz overhead.
The TMS320 DSP Algorithm Standard is a specification of coding conventions allowing fast integration of
algorithms from different teams, sites, or third parties into the application framework. Texas Instruments’
extensive DSP third-party network of over 400 providers brings focused competencies and complete solutions
to customers.
C55x, eXpressDSP, Code Composer Studio, DSP/BIOS, TMS320, RTDX, and XDS510 are trademarks of Texas Instruments.
2
SGUS045A
August 2003 − Revised November 2003
Introduction
Texas Instruments (TI) has also developed foundation software available for the 5510. The C55x DSP Library
(DSPLIB) features over 50 C-callable software kernels (FIR/IIR filters, Fast Fourier Transforms (FFTs), and
various computational functions). The DSP Image/Video Processing Library (IMGLIB) contains over
20 software kernels highly optimized for C55x DSPs and is compiled with the latest revision of the C55x DSP
code generation tools. These imaging functions support a wide range of applications that include
compression, video processing, machine vision, and medical imaging.
The TMS320C55x DSP core was created with an open architecture that allows the addition of
application-specific hardware to boost performance on specific algorithms. The hardware extensions on the
5510 strike the perfect balance of fixed function performance with programmable flexibility, while achieving
low-power consumption, and cost that traditionally has been difficult to find in the video-processor market. The
extensions allow the 5510 to deliver exceptional video codec performance with more than half its bandwidth
available for performing additional functions such as color space conversion, user-interface operations,
security, TCP/IP, voice recognition, and text-to-speech conversion. As a result, a single 5510 DSP can power
most portable digital video applications with processing headroom to spare. For more information, see the
TMS320C55x Hardware Extensions for Image/Video Applications Programmer’s Reference (literature
number SPRU098). For more information on using the the DSP Image Processing Library, see the
TMS320C55x Image/Video Processing Library Programmer’s Reference (literature number SPRU037).
2.2
Pin Assignments
Figure 2−1 illustrates the ball locations for the 240-pin ball grid array (BGA) package and is used in conjunction
with Table 2−1 to locate signal names and ball grid numbers.
U
T
R
P
N
M
L
K
J
H
G
F
E
D
C
B
A
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15 16 17
Figure 2−1. 320VC5510 GGW MicroStar BGA Package (Bottom View)
August 2003 − Revised November 2003
SGUS045A
3
Introduction
Table 2−1. Pin Assignments
BGA BALL #
SIGNAL
BGA BALL #
SIGNAL
BGA BALL #
SIGNAL
BGA BALL #
A1
A2
A9
A3
DVDD
A4
A8
A6
A4
A7
DVDD
A8
D2
A9
VSS
CVDD
VSS
A10
SDRAS
A12
DVDD
SDCAS
A14
A15
HD10
A16
A17
B1
B2
XF
B3
VSS
D9
B4
VSS
D7
VSS
CVDD
VSS
A11
A13
B5
D5
B6
D3
B7
A2
B8
A0
B9
CLKMEM
B10
SDA10
B11
HD2
B12
SDWE
B13
HD1
B14
HRDY
B15
HD3
B16
HD0
B17
HDS1
C1
A10
C2
D13
C3
D10
C4
A6
C5
A7
C6
A5
HD5
A5
4
SIGNAL
C7
A3
C8
D0
C9
HD4
C10
C11
HD6
C12
HD7
C13
HD8
C14
HD9
C15
HR/W
C16
HCS
C17
TRST
D1
DVDD
D2
D14
D3
D11
D4
D8
D5
D6
D6
D4
D7
D1
D8
A1
D9
HD15
D10
HD14
D11
HD13
D12
HD12
D13
HD11
D14
HDS2
D15
HA11
D16
HA0
D17
DVDD
E1
A11
E2
D15
E3
D12
E4
CE3
E5
BOOTM3
E6
CVDD
E7
CVDD
E8
NC
E9
NC
E10
CVDD
E11
NC
E12
NC
E13
RSVD9
E14
HA12
E15
HA10
E16
HA1/HCNTL1
E17
RST_MODE
F1
DVDD
F2
A13
F3
A12
F4
A16
F5
CVDD
F13
RSVD8
F14
HA9
F15
HA2/HAS
F16
CLKIN
F17
CVDD
G1
CE2
G2
A17
G3
A15
G4
A14
G5
NC
G13
RSVD7
G14
HA8
G15
HA3
G16
RESET
G17
HA13
H1
H2
CE1
H3
A19
H4
A18
H5
VSS
NC
H13
RSVD6
H14
HA4
H15
CLKOUT
H16
HA14
H17
J1
J2
CE0
J3
A21
J4
VSS
A20
J5
VSS
NC
J13
RSVD5
J14
HA5
J15
HA15
J16
HA7
J17
K1
IO7
K2
BE0
K3
BE1
K4
VSS
IO0
K5
CVDD
K13
RSVD4
K14
TMS
K15
HBE0
K16
HA16
K17
HA6
L1
CVDD
L2
IO6
L3
BE2
L4
BE3
L5
NC
L13
RSVD3
L14
EMU1/OFF
L15
TDO
L16
TDI
L17
TCK
M1
IO5
M2
SSWE
M3
SSOE
M4
IO1/BOOTM0
M5
NC
M13
RSVD2
M14
HA18
M15
HA17
M16
HBE1
M17
DVDD
N1
DVDD
N2
IO4
N3
D16
N4
SSADS
N5
NC
N6
CVDD
N7
NC
N8
NC
N9
NC
N10
CVDD
N11
NC
N12
NC
N13
RSVD1
N14
HINT
N15
HCNTL0
N16
HMODE
N17
HA19
P1
IO3/BOOTM2
P2
CLKS1
P3
DR1
P4
D19
CLKS2
P5
D22
P6
D23
P7
D24
P8
P9
FSX0
P10
D31
P11
D28
P12
INT4
P13
ARDY
P14
HOLDA
P15
TIN/TOUT0
P16
CLKMD
SGUS045A
August 2003 − Revised November 2003
Introduction
Table 2−1. Pin Assignments (Continued)
BGA BALL #
SIGNAL
BGA BALL #
SIGNAL
BGA BALL #
SIGNAL
BGA BALL #
SIGNAL
P17
R1
CVDD
R2
FSR1
R3
D18
R4
CVDD
D20
R5
CLKR2
R6
FSR2
R7
DR2
R8
D26
R9
FSX2
R10
DX0
R11
INT5
R12
INT0
R13
INT2
R14
ARE
R15
CLKX1
R16
EMU0
R17
TIN/TOUT1
T1
D17
T2
IO2/BOOTM1
T3
CLKR1
T4
D21
T5
FSR0
T6
DR0
T7
D25
T8
D27
T9
D29
T10
D30
T11
NC
T12
NMI
T13
AWE
T14
INT3
T15
FSX1
T16
DX1
T17
VSS
DVDD
U3
CLKR0
U4
VSS
CLKS0
U7
CLKX0
U8
VSS
CVDD
CLKX2
U1
U2
VSS
DVDD
U11
DX2
U12
CVDD
U13
VSS
INT1
U15
AOE
U16
HOLD
U17
VSS
U6
U10
U14
August 2003 − Revised November 2003
U5
U9
SGUS045A
5
Introduction
2.3
Signal Descriptions
Table 2−2 lists each signal, function, and operating mode(s) grouped by function. See Section 2.2 for exact
pin locations based on package type.
Table 2−2. Signal Descriptions
SIGNAL
NAME
TYPE†
OTHER‡
DESCRIPTION
EMIF - ADDRESS BUS
A[21:0]
O/Z
E,F
External memory address bus (byte address). Address all external memory (program and
data). Since A[23:22] are redundant to the CE[3:0] memory space selects in terms of memory
addressing capability, A[23:22] are not externally provided.
EMIF - CONTROL SIGNALS COMMON TO ALL MEMORY TYPES
CE0
CE1
CE2
CE3
O/Z
E,F
External memory space enables. Select one of four external memory ranges based on the
address.
BE0
BE1
BE2
BE3
O/Z
E,F
Byte-enable control. Can be used as chip selects for external memory. These signals respond
according to the data width of the memory access. 8-bit accesses cause a single byte enable to
respond. 16-bit accesses cause two byte enables to respond. 32-bit accesses cause all four byte
enables to respond.
CLKMEM
O/Z
E,F
Memory interface clock (for SDRAM / SBSRAM). Clock for synchronizing the external
synchronous memories to the C55x external memory interface.
EMIF - DATA BUS
D[31:0]
I/O/Z
D,E,F
External data bus. Provides data exchange between external memories and the C55x external
memory interface.
The bus holders on D[31:0] are controlled by the BH bit in the system register (SYSR).
EMIF - BUS ARBITRATION
HOLD
I
−
Hold request. HOLD is asserted by an external host to request control of the address, data and
control signals.
HOLDA
O/Z
F
Hold acknowledge. HOLDA is asserted by the DSP to indicate that the DSP is in the HOLD state
and that the EMIF address, data and control signals are in a high-impedance state, allowing the
external memory interface to be accessed by other devices.
EMIF - ASYNCHRONOUS MEMORY CONTROL SIGNALS
Asynchronous memory read enable. ARE acts as a strobe during asynchronous memory reads
only.
ARE
AOE
O/Z
Asynchronous memory output enable. AOE indicates whether a memory access is a read
(low) or a write (high).
Asynchronous memory write enable. AWE acts as a strobe during asynchronous memory
writes only.
AWE
ARDY
E,F
I
Asynchronous memory ready input. ARDY indicates that an external device is ready for a bus
transaction to be completed. If the device is not ready (ARDY is low), the processor extends the
memory access by one cycle and checks ARDY again. The ARDY signal is sampled at the end
of the STROBE period in the memory access.
† I = Input, O = Output, S = Supply, Z = High impedance
‡ Other Pin Characteristics:
A − Internal pullup (always enabled)
E − Pin is high impedance in HOLD mode (due to HOLD pin).
B − Internal pulldown (always enabled)
F − Pin is high impedance in OFF mode (due to EMU1/OFF pin).
C − Hysteresis input
G − Pin can be configured as a general-purpose input.
D − Pin has bus holder
H − PIn can be configured as a general-purpose output.
J − Internal pullup enabled by the HPE bit in the system register (SYSR)
K − Internal pulldown enabled by the HPE bit in the system register (SYSR)
6
SGUS045A
August 2003 − Revised November 2003
Introduction
Table 2−2. Signal Descriptions (Continued)
SIGNAL
NAME
TYPE†
OTHER‡
DESCRIPTION
EMIF - SYNCHRONOUS BURST SRAM CONTROL SIGNALS
SBSRAM address strobe. SSADS is active (low) during the period of the SBSRAM access when
the address is made available to the external memory by the DSP.
SSADS
SSOE
O/Z
E,F
SSWE
SBSRAM output enable. SSOE is active (low) during read accesses to SBSRAM.
SBSRAM write enable. SSWE is active (low) during write accesses to SBSRAM.
EMIF - SYNCHRONOUS DRAM CONTROL SIGNALS
SDRAM row address strobe. SDRAS is active (low) during the ACTV, DCAB, REFR, and MRS
commands.
SDRAS
SDCAS
O/Z
E,F
SDRAM address column strobe. SDCAS is active (low) during reads, writes, and the REFR and
MRS commands.
SDWE
SDRAM write enable. SDWE is active (low) during writes, and the DCAB and MRS commands.
SDA10
SDRAM A10 address (address/autoprecharge disable). SDA10 is used during reads, writes,
and all commands.
MULTICHANNEL BUFFERED SERIAL PORT SIGNALS
CLKR0
CLKR1
CLKR2
I/O/Z
C,F,G,H
DR0
DR1
DR2
I
G
FSR0
FSR1
FSR2
I/O/Z
F,G,H
Frame synchronization signal for the receiver
CLKX0
CLKX1
CLKX2
I/O/Z
C,F,G,H
Serial shift clock reference for the transmitter
DX0
DX1
DX2
O/Z
F,H
FSX0
FSX1
FSX2
I/O/Z
F,G,H
CLKS0
CLKS1
CLKS2
I
G
Serial shift clock reference for the receiver
Serial receive data input
Serial transmit data output
Frame synchronization signal for the transmitter
External clock source to the sample rate generator
† I = Input, O = Output, S = Supply, Z = High impedance
‡ Other Pin Characteristics:
A − Internal pullup (always enabled)
E − Pin is high impedance in HOLD mode (due to HOLD pin).
B − Internal pulldown (always enabled)
F − Pin is high impedance in OFF mode (due to EMU1/OFF pin).
C − Hysteresis input
G − Pin can be configured as a general-purpose input.
D − Pin has bus holder
H − PIn can be configured as a general-purpose output.
J − Internal pullup enabled by the HPE bit in the system register (SYSR)
K − Internal pulldown enabled by the HPE bit in the system register (SYSR)
August 2003 − Revised November 2003
SGUS045A
7
Introduction
Table 2−2. Signal Descriptions (Continued)
SIGNAL
NAME
TYPE†
OTHER‡
DESCRIPTION
ENHANCED HOST-PORT INTERFACE (EHPI)
Host address bus:
In non-multiplexed mode (HMODE pin high):
HA[19:0] functions as the host address bus only
HA[19:3]
HA2/HAS
HA1/HCNTL1
HA0
I
HD[15:0]
I/O/Z
D,F
HCS
I
J
Host chip select. HCS is the select input for the EHPI and must be driven low during accesses.
If the EHPI is not used, HCS must be driven high.
HA2/HAS
I
J
Host address strobe. Operates as HAS when HMODE is low (multiplexed mode). Hosts with
multiplexed address and data pins may require HAS to latch the address in the HPIA register.
HR/W
I
ËËËËË
ËËËËË
ËËËËË
ËËËËË
J
Host read or write select. Controls the direction of the EHPI transfer.
I
J
Host data strobes. HDS1 and HDS2 are driven by the host read and write strobes to control data
transfers.
O/Z
F,J
Host ready (from DSP to host). HRDY informs the host when the EHPI is ready for the next
transfer.
J
HDS1
HDS2
HRDY
K
I
J
Host multiplexed/non-multiplexed mode select. When HMODE is high, the EHPI operates in
nonmultiplexed mode. When HMODE is low, the EHPI operates in multiplexed mode.
I
J
Host control selects. HCNTL0 and HCNTL1 select host accesses to EHPI address, data or
control registers. HA1/HCNTL operates as HCNTL when HMODE is low (multiplexed mode).
O/Z
F
Host interrupt (from DSP to host). This output is used to interrupt the host. HINT is high
following reset.
HCNTL0
HINT
The bus holders on HD[15:0] are controlled by the HBH bit in the system register (SYSR).
I
HBE1
HA1/HCNTL1
Host data bus. Provides data exchange between the host and C55x EHPI.
EHPI byte enables. HBE0 and HBE1 are driven low selectively by the host to indicate whether
the transaction involves the lower byte only, the upper byte only, or both.
HBE0
HMODE
In multiplexed mode (HMODE pin low):
HA[19:3] are disabled
HA2/HAS functions as HAS (Host Address Strobe). Hosts with multiplexed address and data pins
may require HAS to latch the address in the HPIA register.
HA1/HCNTL1 functions as HCNTL1 (Host Control Input) and with HCNTL0 determines the type
of transaction being performed.
As of revision 2.1, the byte-enable function on the EHPI will no longer be supported. These pins
must be driven low by an external device, by external pulldown resistors or by the internal
pulldown circuit controlled by the HPE bit in the SYSR register.
† I = Input, O = Output, S = Supply, Z = High impedance
‡ Other Pin Characteristics:
A − Internal pullup (always enabled)
E − Pin is high impedance in HOLD mode (due to HOLD pin).
B − Internal pulldown (always enabled)
F − Pin is high impedance in OFF mode (due to EMU1/OFF pin).
C − Hysteresis input
G − Pin can be configured as a general-purpose input.
D − Pin has bus holder
H − PIn can be configured as a general-purpose output.
J − Internal pullup enabled by the HPE bit in the system register (SYSR)
K − Internal pulldown enabled by the HPE bit in the system register (SYSR)
8
SGUS045A
August 2003 − Revised November 2003
Introduction
Table 2−2. Signal Descriptions (Continued)
SIGNAL
NAME
TYPE†
OTHER‡
DESCRIPTION
INTERRUPT AND RESET SIGNALS
RESET
I
C
Device reset. RESET causes the DSP to terminate execution and causes reinitialization of the
CPU and peripherals. The response of the DSP after reset is determined by the RST_MODE pin.
Device reset mode control. RST_MODE controls how a device reset is handled.
RST_MODE
As of revision 2.1, the RST_MODE function will no longer be supported. RST_MODE will be
driven low internally. After reset, the CPU will branch to the reset vector and begin execution.
I
The external state of the RST_MODE pin will have no effect on device operation.
INT0
INT1
INT2
INT3
INT4
INT5
I
C
Maskable external interrupts. INT0−INT5 are prioritized and are maskable via the interrupt
enable registers (IER0 and IER1) and the Interrupt Mode bit (INTM in ST1_55). INT0−INT5 can
be polled and reset via the Interrupt Flag Registers (IFR0 and IFR1).
NMI
I
C
Nonmaskable external interrupt. NMI is an external interrupt that cannot be masked by the
interrupt enable registers (IER0 and IER1). When NMI is activated, the interrupt is always
performed.
JTAG EMULATION
TCK
I
A,C
IEEE Standard 1149.1 test clock. TCK is normally a free-running clock signal with a 50% duty
cycle. The changes on the test access port (TAP) of input signals TDI and TMS are clocked into
the TAP controller, instruction register, or selected test data register on the rising edge of TCK.
Changes at the TAP output signal TDO occur on the falling edge of TCK.
TDI
I
A
IEEE Standard 1149.1 test data input. TDI is clocked into the selected register (instruction or
data) on the rising edge of TCK.
TDO
O
−
IEEE Standard 1149.1 test data output. The contents of the selected register (instruction or
data) are shifted out of TDO on the falling edge of TCK. TDO is in the high-impedance state except
when the scanning of data is in progress.
TMS
I
A
IEEE Standard 1149.1 test mode select. This serial control input is clocked into the TAP
controller on the rising edge of TCK.
TRST
I
B
IEEE Standard 1149.1 test reset. TRST, when high, gives the IEEE standard 1149.1 scan system
control of the operations of the device. If TRST is not connected, or driven low, the device operates
in its functional mode, and the IEEE standard 1149.1 signals are ignored.
This pin has an on-chip pulldown circuit to provide control of the pin when it is not externally
connected. An external pullup resistor should not be connected to this pin.
† I = Input, O = Output, S = Supply, Z = High impedance
‡ Other Pin Characteristics:
A − Internal pullup (always enabled)
E − Pin is high impedance in HOLD mode (due to HOLD pin).
B − Internal pulldown (always enabled)
F − Pin is high impedance in OFF mode (due to EMU1/OFF pin).
C − Hysteresis input
G − Pin can be configured as a general-purpose input.
D − Pin has bus holder
H − PIn can be configured as a general-purpose output.
J − Internal pullup enabled by the HPE bit in the system register (SYSR)
K − Internal pulldown enabled by the HPE bit in the system register (SYSR)
August 2003 − Revised November 2003
SGUS045A
9
Introduction
Table 2−2. Signal Descriptions (Continued)
SIGNAL
NAME
TYPE†
OTHER‡
DESCRIPTION
JTAG EMULATION (CONTINUED)
EMU0
EMU1/OFF
I/O/Z
I/O/Z
A
A
Emulation pin 0. When TRST is driven low, EMU0 must be high for activation of the OFF
condition. When TRST is driven high, EMU0 is used as an interrupt to or from the emulator system
and is defined as input/output by way of the IEEE standard 1449.1 scan system.
Emulation pin 1 / disable all outputs. When TRST is driven high, EMU1/OFF is used as an
interrupt to or from the emulator system and is defined as input/output by way of the IEEE standard
1149.1 scan system. When TRST is driven low, EMU1/OFF is configured as OFF. The EMU1/OFF
signal, when active low, puts all output drivers into the high-impedance state. Note that OFF is
used exclusively for testing and emulation purposes (not for multiprocessing applications).
Therefore, for the OFF feature, the following apply:
TRST = low
EMU0 = high
EMU1/OFF = low
RSVD[1:9]
I/O
Reserved. Reserved for future emulation purposes. These pins should be left unconnected.
CLOCK SIGNALS
CLKIN
I
C
Clock input
CLKOUT
O/Z
F
Clock output. CLKOUT can represent the internal CPU clock or can be divided down to generate
a slower clock by programming the CLKDIV field in the system register (SYSR).
CLKMD
I
C
Clock mode select. CLKMD selects the mode of the clock generator after reset. When CLKMD
is low after reset, the clock generator will run at the same frequency as CLKIN. If CLKMD is high
after reset, the clock generator will run at one-half of the frequency of CLKIN. The clock generator
can later be reprogrammed in software.
TIMERS
TIN/TOUT0
F,H
Timer 0 input/output. When configured as an output, TIN/TOUT0 generates a pulse or toggles
when on-chip Timer 0 counts down to zero. When configured as an input, TIN/TOUT0 is used
as a clock reference for Timer 0. The operation of this pin is configured in the timer control register
(TCR0).
F,H
Timer 1 input/output. When configured as an output, TIN/TOUT1 generates a pulse or toggles
when on-chip Timer 1 counts down to zero. When configured as an input, TIN/TOUT1 is used
as a clock reference for Timer 1. The operation of this pin is configured in the timer control register
(TCR1).
I/O/Z
TIN/TOUT1
GENERAL-PURPOSE I/O SIGNALS
IO7
IO6
IO5
IO4
IO3/BOOTM2
IO2/BOOTM1
IO1/BOOTM0
IO0
I/O/Z
BOOTM3
I
F,G,H
General-purpose configurable inputs/outputs. IO[7:0] can be individually configured as inputs
or outputs via the GPIO direction register (IODIR). Data can be read from inputs or data written
to outputs via the GPIO Data Register (IODATA). In addition, the bootloader uses IO4 as an output
during the boot process. For detailed information on the operation of the bootloader, see the Using
the TMS320VC5510 Bootloader application report (literature number SPRA763).
Boot Mode Selection signals. BOOTM[2:0] are sampled following reset to configure the boot
mode for the DSP. These signals are shared with IO[3:1]. After boot is complete, these signals
can be used as general-purpose inputs/outputs.
A
Boot Mode Selection signal. BOOTM3 is sampled during the operation of the on-chip
bootloader in conjunction with BOOTM[2:0] to configure the boot mode. BOOTM3 is not present
on TMX320VC5510 revision 1.x.
XF
O/Z
F,H
External flag output
† I = Input, O = Output, S = Supply, Z = High impedance
‡ Other Pin Characteristics:
A − Internal pullup (always enabled)
E − Pin is high impedance in HOLD mode (due to HOLD pin).
B − Internal pulldown (always enabled)
F − Pin is high impedance in OFF mode (due to EMU1/OFF pin).
C − Hysteresis input
G − Pin can be configured as a general-purpose input.
D − Pin has bus holder
H − PIn can be configured as a general-purpose output.
J − Internal pullup enabled by the HPE bit in the system register (SYSR)
K − Internal pulldown enabled by the HPE bit in the system register (SYSR)
10
SGUS045A
August 2003 − Revised November 2003
Introduction
Table 2−2. Signal Descriptions (Continued)
SIGNAL
NAME
TYPE†
OTHER‡
DESCRIPTION
SUPPLY VOLTAGE PINS
CVDD
S
Dedicated power supply for the internal logic (CPU and peripherals)
DVDD
S
Dedicated power supply for the I/O pins
VSS
S
Ground
MISCELLANEOUS PINS
NC
No connection − do not connect
† I = Input, O = Output, S = Supply, Z = High impedance
‡ Other Pin Characteristics:
A − Internal pullup (always enabled)
E − Pin is high impedance in HOLD mode (due to HOLD pin).
B − Internal pulldown (always enabled)
F − Pin is high impedance in OFF mode (due to EMU1/OFF pin).
C − Hysteresis input
G − Pin can be configured as a general-purpose input.
D − Pin has bus holder
H − PIn can be configured as a general-purpose output.
J − Internal pullup enabled by the HPE bit in the system register (SYSR)
K − Internal pulldown enabled by the HPE bit in the system register (SYSR)
August 2003 − Revised November 2003
SGUS045A
11
Functional Overview
3
Functional Overview
The following functional overview is based on the block diagram in Figure 3−1.
A[21:0]
D[31:0]
CE[3:0]
BE[3:0]
HOLD
HOLDA
ARE
AOE
AWE
ARDY
EMIF
SSADS
SSOE
SSWE
CLKMEM
SDRAS
SDCAS
SDWE
SDA10
HBE[1:0]
HDS[2:1]
HCS
HR/W
HAS
HINT
TRST
EMU1/OFF
RESET
NMI
INT[5:0]
Figure 3−1. 320VC5510 Functional Block Diagram
12
SGUS045A
August 2003 − Revised November 2003
Functional Overview
3.1
Memory
The 5510 supports a unified memory map (program and data accesses are made to the same physical space).
The total on-chip memory is 352K bytes (176K 16-bit words).
3.1.1 On-Chip Dual-Access RAM (DARAM)
The DARAM is located in the byte address range 000000h−00FFFFh and is composed of eight blocks of
8K-bytes each (see Table 3−1). Each DARAM block can perform two accesses per cycle (two reads, two
writes, or a read and a write). DARAM can be accessed by the internal program, data, or DMA buses.
Table 3−1. DARAM Blocks
BYTE ADDRESS RANGE
MEMORY BLOCK
000000h − 001FFFh
DARAM 0
002000h − 003FFFh
DARAM 1
004000h − 005FFFh
DARAM 2
006000h − 007FFFh
DARAM 3
008000h − 009FFFh
DARAM 4
00A000h − 00BFFFh
DARAM 5
00C000h − 00DFFFh
DARAM 6
00E000h − 00FFFFh
DARAM 7
3.1.2 On-Chip Single-Access RAM (SARAM)
The SARAM is located at the byte address range 010000h−04FFFFh and is composed of 32 blocks of
8K-bytes each (see Table 3−2). Each SARAM block can perform one access per cycle (one read or one write).
SARAM can be accessed by the internal program, data, or DMA buses.
Table 3−2. SARAM Blocks
BYTE ADDRESS RANGE
MEMORY BLOCK
BYTE ADDRESS RANGE
MEMORY BLOCK
010000h − 011FFFh
SARAM 0
030000h − 031FFFh
SARAM 16
012000h − 013FFFh
SARAM 1
032000h − 033FFFh
SARAM 17
014000h − 015FFFh
SARAM 2
034000h − 035FFFh
SARAM 18
016000h − 017FFFh
SARAM 3
036000h − 037FFFh
SARAM 19
018000h − 019FFFh
SARAM 4
038000h − 039FFFh
SARAM 20
01A000h − 01BFFFh
SARAM 5
03A000h − 03BFFFh
SARAM 21
01C000h − 01DFFFh
SARAM 6
03C000h − 03DFFFh
SARAM 22
01E000h − 01FFFFh
SARAM 7
03E000h − 03FFFFh
SARAM 23
020000h − 021FFFh
SARAM 8
040000h − 041FFFh
SARAM 24
022000h − 023FFFh
SARAM 9
042000h − 043FFFh
SARAM 25
024000h − 025FFFh
SARAM 10
044000h − 045FFFh
SARAM 26
026000h − 027FFFh
SARAM 11
046000h − 047FFFh
SARAM 27
028000h − 029FFFh
SARAM 12
048000h − 049FFFh
SARAM 28
02A000h − 02BFFFh
SARAM 13
04A000h − 04BFFFh
SARAM 29
02C000h − 02DFFFh
SARAM 14
04C000h − 04DFFFh
SARAM 30
02E000h − 02FFFFh
SARAM 15
04E000h − 04FFFFh
SARAM 31
August 2003 − Revised November 2003
SGUS045A
13
Functional Overview
3.1.3 On-Chip ROM
The ROM is located at the byte address range FF8000h−FFFFFFh when MP/MC = 0 at reset. The ROM is
composed of a single block of 32K bytes. When MP/MC = 1 at reset, the on-chip ROM is disabled and not
present in the memory map, and byte address range FF8000h−FFFFFFh is directed to external memory
space. MP/MC is a bit located in the ST3 status register, and its status is determined by the logic level on the
BOOTM[2:0] pins when sampled at reset. If BOOTM[2:0] are all logic 0 at reset, the MP/MC bit is set to 1 and
the on-chip ROM is disabled; otherwise, the MP/MC bit is cleared to 0 and the on-chip ROM is enabled. These
pins are not sampled again until the next hardware reset. The software reset instruction does not affect the
MP/MC bit. Software can also be used to set or clear the MP/MC bit. ROM can be accessed by the program,
data, or DMA buses. The first 16-bit word access to ROM requires three cycles. Subsequent accesses require
two cycles per 16-bit word.
The standard on-chip ROM contains a bootloader which provides a variety of methods to load application code
automatically after power up or a hardware reset. For more information, see Section 3.1.5 of this document.
The vector table associated with the bootloader is also contained in the ROM.
A sine look-up table is provided containing 256 values (crossing 360 degrees) expressed in Q15 format.
The remaining components are used during factory testing purposes.
Table 3−3. Standard On-Chip ROM Contents
BYTE ADDRESS RANGE
DESCRIPTION
FF8000h − FF8FFFh
Bootloader
FF9000h − FFF9FFh
Reserved
FFFA00h − FFFBFFh
Sine look-up table
FFFC00h − FFFEFFh
Factory Test Code
FFFF00h − FFFFFBh
Vector Table
FFFFFCh − FFFFFFh
ID Code
3.1.4 Instruction Cache
The 24K-byte instruction cache provides three configurations:
•
•
•
One 2-way cache block only
One 2-way cache block plus one RAMSET block
One 2-way cache block plus two RAMSET blocks
The 2-way cache uses 2-way set associative mapping and holds up to 16K bytes. It is organized as 512 sets
of two cache lines per set. Each cache line contains 16 bytes. Each tag has two corresponding cache lines,
providing two opportunities for a hit on a given tag. The 2-way cache is updated based on a least-recently-used
algorithm.
Each RAMSET block provides a 4K-byte bank of memory to hold a continuous image of code. Each RAMSET
is composed of 256 lines with 16 bytes per line. Each RAMSET uses a single tag to define a continuous
memory image in the RAMSET. The tag defines the start address of the RAMSET. Once the TAG is loaded,
the RAMSET is filled. The RAMSET contents remain constant until the tag is changed. The RAMSETs provide
an efficient method to cache frequently used functions.
Control bits in CPU status register ST3_55 provide the ability to enable, freeze, and flush the cache.
For more information on the instruction cache, see the TMS320C5510 DSP Instruction Cache Reference
Guide (literature number SPRU576).
14
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Functional Overview
3.1.5 Memory Map
Byte Address† (Hex)
000000
010000
Memory Blocks
Block Length
DARAM‡
(8 blocks)
65,536 bytes
SARAM§
(32 blocks)
262,144 bytes
050000
External¶ − CE0
3,866,624 bytes
External¶ − CE1
4,194,304 bytes
External¶ − CE2
4,194,304 bytes
External¶ − CE3
4,161,536 bytes
400000
800000
C00000
FF8000
FFFFFF
ROM#
if MP/MC=0
(1 block)
External¶ − CE3 32,768 bytes
if MP/MC=1
† Address shown represents the first byte address in each block.
‡ Dual-access RAM (DARAM): two accesses per cycle per block, 8 blocks of 8K bytes.
§ Single-access RAM (SARAM): one access per cycle per block, 32 blocks of 8K bytes.
¶ External memory spaces are selected by the chip-enable signal shown (CE[0:3]).
Supported memory types include: asynchronous, synchronous DRAM (SDRAM), and
synchronous burst SRAM (SBSRAM).
# Read-only memory (ROM): one access every two cycles, one block of 32K bytes.
Figure 3−2. 320VC5510 Memory Map
3.1.6 Bootloader
The on-chip bootloader provides a method to transfer application code and tables from an external source to
the on-chip RAM at power up. The 5510 provides several options to download the code to accommodate
varying system requirements. These options include:
•
•
•
•
Enhanced Host-Port Interface (EHPI) boot
External memory boot from 8-/16-/32-bit-wide asynchronous memory
Serial slave boot from McBSP0 with 8- or 16-bit element length
Serial EEPROM boot from McBSP0 in 8-bit SPI format
External pins BOOTM3, BOOTM2, BOOTM1, and BOOTM0 select the boot configuration. The values of
BOOTM[2:0] are latched with the rising edge of the RESET input. BOOTM[0] is shared with general-purpose
IO1. BOOTM[1] is shared with general-purpose IO2. BOOTM[2] is shared with general-purpose IO3.
The boot configurations available are summarized in Table 3−4. For detailed information on the bootloader
functions, refer to the Using the TMS320VC5510 Bootloader Application Report (literature number
SPRA763).
August 2003 − Revised November 2003
SGUS045A
15
Functional Overview
Table 3−4. 320VC5510 Boot Configurations
BOOTM[3:0]
BOOT PROCESS
EXECUTION START BYTE ADDRESS
AFTER BOOT IS COMPLETE
0000
No boot
FFFF00h (reset vector)
0001
Serial SPI EEPROM boot from McBSP0 supporting 24-bit address
Destination specified in the boot table
0010
Reserved
−
0011
Reserved
−
0100
Reserved
−
0101
Reserved
−
0110
Reserved
−
0111
Reserved
−
1000
No boot
FFFF00h (reset vector)
1001
Serial SPI EEPROM boot from McBSP0 supporting 16-bit address
Destination specified in the boot table
1010
Parallel EMIF boot from 8-bit asynchronous memory
Destination specified in the boot table
1011
Parallel EMIF boot from 16-bit asynchronous memory
Destination specified in the boot table
1100
Parallel EMIF boot from 32-bit asynchronous memory
Destination specified in the boot table
1101
EHPI boot
010000h (on-chip SARAM)
1110
Standard serial boot from McBSP0, 16-bit element length
Destination specified in the boot table
1111
Standard serial boot from McBSP0, 8-bit element length
Destination specified in the boot table
3.2
Peripherals
The 5510 supports the following peripherals:
•
•
•
•
•
•
•
An external memory interface (EMIF)
A six-channel direct memory access (DMA) controller
16-bit parallel Enhanced Host-Port Interface (EHPI)
A digital phase-locked loop (DPLL) clock generator
Two timers
Three multichannel buffered serial ports (McBSPs)
Eight configurable general-purpose I/O pins
Peripheral information specific to the 5510 peripherals is included in the following sections. For detailed
information on the C55x DSP peripherals, see the following documents:
•
•
16
TMS320C55x DSP Functional Overview (literature number SPRU312)
TMS320C55x DSP Peripherals Reference Guide (literature number SPRU317)
SGUS045A
August 2003 − Revised November 2003
Functional Overview
3.2.1 System Register (SYSR)
The 5510 system register (SYSR) provides control over certain device-specific functions. SYSR is located at
port address 07FDh.
15
10
9
8
7
6
5
4
3
2
0
Reserved
HPE
BH
HBH
BOOTM3
Reserved
Reserved
Reserved
CLKDIV
R−000000
R/W−1
R/W−0
R/W−0
R−0
R−0
R/W−0
R/W−0
R/W−000
LEGEND: R = Read, W = Write, n = value after reset
Figure 3−3. System Register (SYSR) Bit Layout
Table 3−5. System Register (SYSR) Bit Functions
BIT
NO.
BIT
NAME
RESET
VALUE
15−10
Reserved
000000
FUNCTION
These bits are reserved and are unaffected by writes.
9
HPE
1
EHPI pullup/pulldown enable. Enables the internal pullups on the EHPI control pins HCS, HAS, HR/W,
HMODE, HCNTL0, and HA1/HCNTL1. Enables the internal pulldowns on EHPI control pins HBE0 and
HBE1.
HPE = 0
Pullups and pulldowns disabled
HPE = 1
Pullups and pulldowns enabled.
8
BH
0
EMIF data bus holder enable. Enables internal bus holders on D[31:0].
BH = 0
EMIF data bus holders disabled.
BH = 1
EMIF data bus holders enabled.
7
HBH
0
EHPI data bus holder enable. Enables internal bus holders on HD[15:0].
HBH = 0
EHPI data bus holders disabled.
HBH = 1
EHPI data bus holders enabled.
6
BOOTM3
0
BOOTM3 status. This read-only bit represents the state of the BOOTM3 pin.
5
Reserved
0
This bit is reserved and is unaffected by writes.
4
Reserved
0
This bit is reserved and must be written as 0.
3
Reserved
0
This bit is reserved and is unaffected by writes.
2−0
CLKDIV
000
CLKOUT divide factor. Allows the clock present on the CLKOUT pin to be a divided-down version of the
internal CPU clock. This field does not affect the programming of the PLL
CLKDIV = 000 CLKOUT represents the CPU clock divided by 1
CLKDIV = 001 CLKOUT represents the CPU clock divided by 2
CLKDIV = 010 CLKOUT represents the CPU clock divided by 4
CLKDIV = 011 CLKOUT represents the CPU clock divided by 6
CLKDIV = 100 CLKOUT represents the CPU clock divided by 8
CLKDIV = 101 CLKOUT represents the CPU clock divided by 10
CLKDIV = 110 CLKOUT represents the CPU clock divided by 12
CLKDIV = 111 CLKOUT represents the CPU clock divided by 14
August 2003 − Revised November 2003
SGUS045A
17
Functional Overview
3.2.2 Direct Memory Access (DMA)
The 5510 DMA provides the following features:
•
Four standard ports, one for each of the following data resources: DARAM, SARAM, Peripherals, and
External Memory
•
Six channels, which allow the DMA controller to track the context of six independent DMA channels
•
Programmable low/high priority for each DMA channel
•
One interrupt for each DMA channel
•
Event synchronization. DMA transfers in each channel can be dependent on the occurrence of selected
events.
•
Programmable address modification for source and destination addresses
•
Dedicated Idle Domain allows the DMA controller to be placed in a low-power (idle) state under software
control.
•
DMA controller supports EHPI accesses to internal/external memory
The 5510 DMA controller allows transfers to be synchronized to selected events. The 5510 supports
14 separate sync events and each channel can be tied to separate sync events independent of the other
channels. Sync events are selected by programming the SYNC field in the channel-specific DMA Channel
Control Register (DMA_CCR). The sync events available on the 5510 are shown in Table 3−6.
Table 3−6. DMA Sync Events
SYNC FIELD IN DMA_CCR
No sync event
00001b
McBSP0 receive event (REVT0)
00010b
McBSP0 transmit event (XEVT0)
00101b
McBSP1 receive event (REVT1)
00110b
McBSP1 transmit event (XEVT1)
01001b
McBSP2 receive event (REVT2)
01010b
McBSP2 transmit event (XEVT2)
01101b
Timer 0 event
01110b
Timer 1 event
01111b
External Interrupt 0
10000b
External Interrupt 1
10001b
External Interrupt 2
10010b
External Interrupt 3
10011b
External Interrupt 4
10100b
External Interrupt 5
Other values
18
SGUS045A
SYNC EVENT
00000b
Reserved (do not use these values)
August 2003 − Revised November 2003
Functional Overview
3.2.3 Enhanced Host Port Interface (EHPI)
The 5510 EHPI provides a 16-bit parallel interface to a host with the following features:
•
•
•
•
•
•
•
20-bit host address bus
16-bit host data bus
Multiplexed and non-multiplexed bus modes
Host access to on-chip SARAM, on-chip DARAM, and external memory
20-bit address register (in multiplexed mode) with autoincrement capability for faster transfers
Multiple address/data strobes provide a glueless interface to a variety of hosts
HRDY signal for handshaking with host
The 5510 EHPI can access internal DARAM, internal SARAM and a portion of the external memory space.
The EHPI cannot directly access the on-chip peripherals and cannot access the memory-mapped registers
below word address 000060h in DARAM. Note that all memory accesses made though the EHPI are
word-addressed. A map of the memory space accessible by the EHPI is shown in Figure 3−4. The EHPI can
access from word address 000060h to 0FFFFFh. The shaded areas of the memory map are not accessible
by the EHPI.
Word Address
000000h
Memory Blocks
Memory Mapped
Registers (DARAM)
000060h
DARAM
008000h
SARAM
Memory Accessible
Through the EHPI
028000h
External − CE0
100000h
External − CE0
200000h
External − CE1
400000h
External − CE2
600000h
External − CE3
NOTE A: The shaded areas of the memory map are not accessible by the EHPI.
Figure 3−4. EHPI Memory Map
When the EHPI inputs are uncontrolled, noise on the inputs can cause spurious accesses that may corrupt
internal memory. If the EHPI is not driven by a host, the HCS pin should be driven high by one of the following
methods:
•
•
•
An external device
External pullup resistor, or
The on-chip pullup circuit controlled by the HPE bit in the System Register (SYSR). See Section 3.2.1
for more information on how to configure this control.
As of revision 2.1, the byte-enable function of the EHPI is no longer supported. Pins HBE0 and HBE1 must
be driven low at all times.
August 2003 − Revised November 2003
SGUS045A
19
Functional Overview
3.2.4 General-Purpose Input/Output Port (GPIO)
The 5510 provides eight dedicated general-purpose input/output pins, IO0−IO7. Each pin can be
independently configured as an input or an output using the I/O Direction Register (IODIR). The I/O Data
Register (IODATA) is used to monitor the logic state of pins configured as inputs and control the logic state
of pins configured as outputs. IODIR and IODATA are accessible to the CPU and to the DMA controller at
addresses in I/O space. See Table 3−19 for address information. The description of the IODIR is shown in
Figure 3−5 and Table 3−7. The description of IODATA is shown in Figure 3−6 and Table 3−8.
To configure a GPIO pin as an input, clear the direction bit that corresponds to the pin in IODIR to 0. To read
the logic state of the input pin, read the corresponding bit in IODATA.
To configure a GPIO pin as an output, set the direction bit that corresponds to the pin in IODIR to 1. To control
the logic state of the output pin, write to the corresponding bit in IODATA.
15
8
7
6
5
4
3
2
1
0
Reserved
IO7DIR
IO6DIR
IO5DIR
IO4DIR
IO3DIR
IO2DIR
IO1DIR
IO0DIR
R−00000000
R/W−0
R/W−0
R/W−0
R/W−0
R/W−0
R/W−0
R/W−0
R/W−0
LEGEND: R = Read, W = Write, n = value after reset
Figure 3−5. I/O Direction Register (IODIR) Bit Layout
Table 3−7. I/O Direction Register (IODIR) Bit Functions
BIT
NO.
BIT
NAME
RESET
VALUE
15−8
Reserved
0
These bits are reserved and are unaffected by writes.
7−0
IOxDIR
0
IOx Direction Control Bit. Controls whether IOx operates as an input or an output.
IOxDIR = 0
IOx is configured as an input.
IOxDIR = 1
IOx is configured as an output.
15
8
FUNCTION
7
6
5
4
3
2
1
0
Reserved
IO7D
IO6D
IO5D
IO4D
IO3D
IO2D
IO1D
IO0D
R−00000000
R/W−pin
R/W−pin
R/W−pin
R/W−pin
R/W−pin
R/W−pin
R/W−pin
R/W−pin
LEGEND: R = Read, W = Write, pin = value present on the pin (IO7−IO0 default to inputs after reset)
Figure 3−6. I/O Data Register (IODATA) Bit Layout
Table 3−8. I/O Data Register (IODATA) Bit Functions
BIT
NO.
BIT
NAME
RESET
VALUE
15−8
Reserved
0
7−0
IOxD
pin†
FUNCTION
These bits are reserved and are unaffected by writes.
IOx Data Bit.
If IOx is configured as an input (IOxDIR = 0 in IODIR):
IOxD = 0
The signal on the IOx pin is low.
IOxD = 1
The signal on the IOx pin is high.
If IOx is configured as an output (IOxDIR = 1 in IODIR):
IOxD = 0
Drive the signal on the IOx pin low.
IOxD = 1
Drive the signal on the IOx pin high.
† pin = value present on the pin (IO7−IO0 default to inputs after reset)
20
SGUS045A
August 2003 − Revised November 2003
Functional Overview
3.3
CPU Register Description
The 5510 CPU registers are shown in Table 3−9. For code compatibility, many TMS320C55x (C55x) CPU
registers map to comparable TMS320C54x (C54x) CPU register addresses. The corresponding
TMS320C54x (C54x) CPU registers are indicated in these instances.
Table 3−9. CPU Registers
C54X
REGISTER
VC5510
REGISTER
WORD ADDRESS
(HEX)
IMR
IER0
00
Interrupt Mask Register 0
IFR
IFR0
01
Interrupt Flag Register 0
−
ST0_55
02
Status Register 0 for C55x
−
ST1_55
03
Status Register 1 for C55x
−
ST3_55
04
Status Register 3 for C55x
−
−
05
Reserved
ST0
ST0
06
Status Register ST0 (for 54x compatibility)
ST1
ST1
07
Status Register ST1 (for 54x compatibility)
AL
AC0L
08
AH
AC0H
09
AG
AC0G
0A
BL
AC1L
0B
DESCRIPTION
Accumulator 0 (equivalent to Accumulator A on C54x)
BH
AC1H
0C
BG
AC1G
0D
TREG
T3
0E
Temporary Register
TRN
TRN0
0F
Transition Register
AR0
AR0
10
Auxiliary Register 0
AR1
AR1
11
Auxiliary Register 1
AR2
AR2
12
Auxiliary Register 2
AR3
AR3
13
Auxiliary Register 3
AR4
AR4
14
Auxiliary Register 4
AR5
AR5
15
Auxiliary Register 5
AR6
AR6
16
Auxiliary Register 6
AR7
AR7
17
Auxiliary Register 7
SP
SP
18
Stack Pointer Register
BK
BK03
19
Circular Buffer Size Register
BRC
BRC0
1A
Block Repeat Counter
RSA
RSA0L
1B
Block Repeat Start Address
REA
REA0L
1C
Block Repeat End Address
PMST
PMST
1D
Processor Mode Status Register
XPC
XPC
1E
Program Counter Extension Register
−
−
1F
Reserved
−
T0
20
Temporary Data Register 0
−
T1
21
Temporary Data Register 1
−
T2
22
Temporary Data Register 2
−
T3
23
Temporary Data Register 3
Accumulator 1 (equivalent to Accumulator A on C54x)
TMS320C54x and C54x are trademarks of Texas Instruments.
August 2003 − Revised November 2003
SGUS045A
21
Functional Overview
Table 3−9. CPU Registers (Continued)
VC5510
REGISTER
WORD ADDRESS
(HEX)
−
AC2L
24
−
AC2H
25
−
AC2G
26
−
CDP
27
−
AC3L
28
C54X
REGISTER
22
−
AC3H
29
−
AC3G
2A
DESCRIPTION
Accumulator 2
Coefficient Data Pointer
Accumulator 3
−
DPH
2B
Extended Data Page Pointer
−
MDP05
2C
Reserved
−
MDP67
2D
Reserved
−
DP
2E
Memory Data Page Start Address
−
PDP
2F
Peripheral Data Page Start Address
−
BK47
30
Circular Buffer Size Register for AR[4−7]
−
BKC
31
Circular Buffer Size Register for CDP
−
BSA01
32
Circular Buffer Start Address Register for AR[0−1]
−
BSA23
33
Circular Buffer Start Address Register for AR[2−3]
−
BSA45
34
Circular Buffer Start Address Register for AR[4−5]
−
BSA67
35
Circular Buffer Start Address Register for AR[6−7]
−
BSAC
36
Circular Buffer Coefficient Start Address Register
−
BIOS
37
Data Page Pointer Storage Location for 128-word Data Table
−
TRN1
38
Transition Register 1
−
BRC1
39
Block Repeat Counter 1
−
BRS1
3A
Block Repeat Save 1
−
CSR
3B
Computed Single Repeat
−
RSA0H
3C
−
RSA0L
3D
−
REA0H
3E
−
REA0L
3F
−
RSA1H
40
−
RSA1L
41
−
REA1H
42
−
REA1L
43
−
RPTC
44
Repeat Counter
−
IER1
45
Interrupt Mask Register 1
−
IFR1
46
Interrupt Flag Register 1
−
DBIER0
47
Debug IER0
−
DBIER1
48
Debug IER1
−
IVPD
49
Interrupt Vector Pointer DSP
−
IVPH
4A
Interrupt Vector Pointer HOST
−
ST2_55
4B
Status Register 2 for C55x
−
SSP
4C
System Stack Pointer
−
SP
4D
User Stack Pointer
−
SPH
4E
Extended Data Page Pointer for the SP and the SSP
−
CDPH
4F
Main Data Page Pointer for the CDP
SGUS045A
Repeat Start Address 0
Repeat End Address 0
Repeat Start Address 1
Repeat End Address 1
August 2003 − Revised November 2003
Functional Overview
3.4
Peripheral Register Description
Peripheral registers on the 5510 are accessed using the port qualifier. For more information on the use of the
port qualifier, see the TMS320C55x Assembly Language Tools User’s Guide (literature number SPRU280).
For detailed information on the operation of the peripherals and the functions of each of the peripheral
registers, refer to the TMS320C55x DSP Peripherals Reference Guide (literature number SPRU317).
Table 3−10. Peripheral Bus Controller Configuration Registers
PORT ADDRESS
REGISTER NAME
DESCRIPTION
0x0001
ICR
Idle Control Register
0x0002
ISTR
Idle Status Register
0x000F
BOOT_MOD
Boot Mode Register (read only)
Table 3−11. Instruction Cache Registers
PORT ADDRESS
REGISTER NAME
DESCRIPTION
0x1400
ICGC
I-Cache Global Control Register
0x1401
ICFL0
I-Cache Flush Line Address Register 0
0x1402
ICFL1
I-Cache Flush Line Address Register 1
0x1403
ICWC
I-Cache N-Way Control Register
0x1404
ICSTAT
I-Cache Status Register
0x1405
ICRC1
I-Cache Ramset 1 Control Register
0x1406
ICRTAG1
I-Cache Ramset 1 Tag Register
0x1407
ICRC2
I-Cache Ramset 2 Control Register
0x1408
ICRTAG2
I-Cache Ramset 2 Tag Register
August 2003 − Revised November 2003
SGUS045A
23
Functional Overview
Table 3−12. External Memory Interface Registers
PORT ADDRESS
REGISTER NAME
DESCRIPTION
0x0800
EGCR
EMIF Global Control Register
0x0801
EMI_RST
EMIF Global Reset Register
0x0802
EMI_BE
EMIF Bus Error Status Register
0x0803
CE0_1
EMIF CE0 Space Control Register 1
0x0804
CE0_2
EMIF CE0 Space Control Register 2
0x0805
CE0_3
EMIF CE0 Space Control Register 3
0x0806
CE1_1
EMIF CE1 Space Control Register 1
0x0807
CE1_2
EMIF CE1 Space Control Register 2
0x0808
CE1_3
EMIF CE1 Space Control Register 3
0x0809
CE2_1
EMIF CE2 Space Control Register 1
0x080A
CE2_2
EMIF CE2 Space Control Register 2
0x080B
CE2_3
EMIF CE2 Space Control Register 3
0x080C
CE3_1
EMIF CE3 Space Control Register 1
0x080D
CE3_2
EMIF CE3 Space Control Register 2
0x080E
CE3_3
EMIF CE3 Space Control Register 3
0x080F
SDC1
EMIF SDRAM Control Register 1
0x0810
SDPER
EMIF SDRAM Period Register
0x0811
SDCNT
EMIF SDRAM Counter Register
0x0812
INIT
EMIF SDRAM Init Register
0x0813
SDC2
EMIF SDRAM Control Register 2
24
SGUS045A
August 2003 − Revised November 2003
Functional Overview
Table 3−13. DMA Configuration Registers
PORT ADDRESS
REGISTER NAME
DESCRIPTION
GLOBAL REGISTER
0x0E00
DMA_GCR
DMA Global Control Register
0x0E02
DMA_GSCR
DMA Software Compatibility Register
0x0E03
DMA_GTCR
DMA Timeout Control Register
CHANNEL #0 REGISTERS
0x0C00
DMA_CSDP0
DMA Channel 0 Source / Destination Parameters Register
0x0C01
DMA_CCR0
DMA Channel 0 Control Register
0x0C02
DMA_CICR0
DMA Channel 0 Interrupt Control Register
0x0C03
DMA_CSR0
DMA Channel 0 Status Register
0x0C04
DMA_CSSA_L0
DMA Channel 0 Source Start Address Register (lower bits)
0x0C05
DMA_CSSA_U0
DMA Channel 0 Source Start Address Register (upper bits)
0x0C06
DMA_CDSA_L0
DMA Channel 0 Source Destination Address Register (lower bits)
0x0C07
DMA_CDSA_U0
DMA Channel 0 Source Destination Address Register (upper bits)
0x0C08
DMA_CEN0
DMA Channel 0 Element Number Register
0x0C09
DMA_CFN0
DMA Channel 0 Frame Number Register
0x0C0A
DMA_CFI0/
DMA_CSFI0†
DMA Channel 0 Frame Index Register/
DMA Channel 0 Source Frame Index Register†
0x0C0B
DMA_CEI0/
DMA_CSEI0‡
DMA Channel 0 Element Index Register/
DMA Channel 0 Source Element Index Register‡
0x0C0C
DMA_CSAC0
DMA Channel 0 Source Address Counter
0x0C0D
DMA_CDAC0
DMA Channel 0 Destination Address Counter
0x0C0E
DMA_CDEI0
DMA Channel 0 Destination Element Index Register
0x0C0F
DMA_CDFI0
DMA Channel 0 Destination Frame Index Register
CHANNEL #1 REGISTERS
0x0C20
DMA_CSDP1
DMA Channel 1 Source / Destination Parameters Register
0x0C21
DMA_CCR1
DMA Channel 1 Control Register
0x0C22
DMA_CICR1
DMA Channel 1 Interrupt Control Register
0x0C23
DMA_CSR1
DMA Channel 1 Status Register
0x0C24
DMA_CSSA_L1
DMA Channel 1 Source Start Address Register (lower bits)
0x0C25
DMA_CSSA_U1
DMA Channel 1 Source Start Address Register (upper bits)
0x0C26
DMA_CDSA_L1
DMA Channel 1 Source Destination Address Register (lower bits)
0x0C27
DMA_CDSA_U1
DMA Channel 1 Source Destination Address Register (upper bits)
0x0C28
DMA_CEN1
DMA Channel 1 Element Number Register
0x0C29
DMA_CFN1
DMA Channel 1 Frame Number Register
0x0C2A
DMA_CFI1/
DMA_CSFI1†
DMA Channel 1 Frame Index Register/
DMA Channel 1 Source Frame Index Register†
0x0C2B
DMA_CEI1/
DMA_CSEI1‡
DMA Channel 1 Element Index Register/
DMA Channel 1 Source Element Index Register‡
0x0C2C
DMA_CSAC1
DMA Channel 1 Source Address Counter
0x0C2D
DMA_CDAC1
DMA Channel 1 Destination Address Counter
0x0C2E
DMA_CDEI1
DMA Channel 1 Destination Element Index Register
0x0C2F
DMA_CDFI1
DMA Channel 1 Destination Frame Index Register
† On revision 1.x, the channel frame index applies to both source and destination and this register behaves as DMA_CFIn. On revision 2.0 and
later, DMA_CSFIn and DMA_CDFIn provide separate source and destination frame indexing. Revisions 2.0 and later can be programmed
for software compatibility with revisions 1.x through the Software Compatibility Register (DMA_GSCR).
‡ On revision 1.x, the channel element index applies to both source and destination and this register behaves as DMA_CEIn. On revision 2.0
and later, DMA_CSEIn and DMA_CDEIn provide separate source and destination frame indexing. Revisions 2.0 and later can be programmed
for software compatibility with revisions 1.x through the Software Compatibility Register (DMA_GSCR).
August 2003 − Revised November 2003
SGUS045A
25
Functional Overview
Table 3−13. DMA Configuration Registers (Continued)
PORT ADDRESS
REGISTER NAME
DESCRIPTION
CHANNEL #2 REGISTERS
0x0C40
DMA_CSDP2
DMA Channel 2 Source / Destination Parameters Register
0x0C41
DMA_CCR2
DMA Channel 2 Control Register
0x0C42
DMA_CICR2
DMA Channel 2 Interrupt Control Register
0x0C43
DMA_CSR2
DMA Channel 2 Status Register
0x0C44
DMA_CSSA_L2
DMA Channel 2 Source Start Address Register (lower bits)
0x0C45
DMA_CSSA_U2
DMA Channel 2 Source Start Address Register (upper bits)
0x0C46
DMA_CDSA_L2
DMA Channel 2 Source Destination Address Register (lower bits)
0x0C47
DMA_CDSA_U2
DMA Channel 2 Source Destination Address Register (upper bits)
0x0C48
DMA_CEN2
DMA Channel 2 Element Number Register
0x0C49
DMA_CFN2
DMA Channel 2 Frame Number Register
0x0C4A
DMA_CFI2/
DMA_CSFI2†
DMA Channel 2 Frame Index Register/
DMA Channel 2 Source Frame Index Register†
0x0C4B
DMA_CEI2/
DMA_CSEI2‡
DMA Channel 2 Element Index Register/
DMA Channel 2 Source Element Index Register‡
0x0C4C
DMA_CSAC2
DMA Channel 2 Source Address Counter
0x0C4D
DMA_CDAC2
DMA Channel 2 Destination Address Counter
0x0C4E
DMA_CDEI2
DMA Channel 2 Destination Element Index Register
0x0C4F
DMA_CDFI2
DMA Channel 2 Destination Frame Index Register
CHANNEL #3 REGISTERS
0x0C60
DMA_CSDP3
DMA Channel 3 Source / Destination Parameters Register
0x0C61
DMA_CCR3
DMA Channel 3 Control Register
0x0C62
DMA_CICR3
DMA Channel 3 Interrupt Control Register
0x0C63
DMA_CSR3
DMA Channel 3 Status Register
0x0C64
DMA_CSSA_L3
DMA Channel 3 Source Start Address Register (lower bits)
0x0C65
DMA_CSSA_U3
DMA Channel 3 Source Start Address Register (upper bits)
0x0C66
DMA_CDSA_L3
DMA Channel 3 Source Destination Address Register (lower bits)
0x0C67
DMA_CDSA_U3
DMA Channel 3 Source Destination Address Register (upper bits)
0x0C68
DMA_CEN3
DMA Channel 3 Element Number Register
0x0C69
DMA_CFN3
DMA Channel 3 Frame Number Register
0x0C6A
DMA_CFI3/
DMA_CSFI3†
DMA Channel 3 Frame Index Register/
DMA Channel 3 Source Frame Index Register†
0x0C6B
DMA_CEI3/
DMA_CSEI3‡
DMA Channel 3 Element Index Register/
DMA Channel 3 Source Element Index Register‡
0x0C6C
DMA_CSAC3
DMA Channel 3 Source Address Counter
0x0C6D
DMA_CDAC3
DMA Channel 3 Destination Address Counter
0x0C6E
DMA_CDEI3
DMA Channel 3 Destination Element Index Register
0x0C6F
DMA_CDFI3
DMA Channel 3 Destination Frame Index Register
† On revision 1.x, the channel frame index applies to both source and destination and this register behaves as DMA_CFIn. On revision 2.0 and
later, DMA_CSFIn and DMA_CDFIn provide separate source and destination frame indexing. Revisions 2.0 and later can be programmed
for software compatibility with revisions 1.x through the Software Compatibility Register (DMA_GSCR).
‡ On revision 1.x, the channel element index applies to both source and destination and this register behaves as DMA_CEIn. On revision 2.0
and later, DMA_CSEIn and DMA_CDEIn provide separate source and destination frame indexing. Revisions 2.0 and later can be programmed
for software compatibility with revisions 1.x through the Software Compatibility Register (DMA_GSCR).
26
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Functional Overview
Table 3−13. DMA Configuration Registers (Continued)
PORT ADDRESS
REGISTER NAME
DESCRIPTION
CHANNEL #4 REGISTERS
0x0C80
DMA_CSDP4
DMA Channel 4 Source / Destination Parameters Register
0x0C81
DMA_CCR4
DMA Channel 4 Control Register
0x0C82
DMA_CICR4
DMA Channel 4 Interrupt Control Register
0x0C83
DMA_CSR4
DMA Channel 4 Status Register
0x0C84
DMA_CSSA_L4
DMA Channel 4 Source Start Address Register (lower bits)
0x0C85
DMA_CSSA_U4
DMA Channel 4 Source Start Address Register (upper bits)
0x0C86
DMA_CDSA_L4
DMA Channel 4 Source Destination Address Register (lower bits)
0x0C87
DMA_CDSA_U4
DMA Channel 4 Source Destination Address Register (upper bits)
0x0C88
DMA_CEN4
DMA Channel 4 Element Number Register
0x0C89
DMA_CFN4
DMA Channel 4 Frame Number Register
0x0C8A
DMA_CFI4/
DMA_CSFI4†
DMA Channel 4 Frame Index Register/
DMA Channel 4 Source Frame Index Register†
0x0C8B
DMA_CEI4/
DMA_CSEI4‡
DMA Channel 4 Element Index Register/
DMA Channel 4 Source Element Index Register‡
0x0C8C
DMA_CSAC4
DMA Channel 4 Source Address Counter
0x0C8D
DMA_CDAC4
DMA Channel 4 Destination Address Counter
0x0C8E
DMA_CDEI4
DMA Channel 4 Destination Element Index Register
0x0C8F
DMA_CDFI4
DMA Channel 4 Destination Frame Index Register
CHANNEL #5 REGISTERS
0x0CA0
DMA_CSDP5
DMA Channel 5 Source / Destination Parameters Register
0x0CA1
DMA_CCR5
DMA Channel 5 Control Register
0x0CA2
DMA_CICR5
DMA Channel 5 Interrupt Control Register
0x0CA3
DMA_CSR5
DMA Channel 5 Status Register
0x0CA4
DMA_CSSA_L5
DMA Channel 5 Source Start Address Register (lower bits)
0x0CA5
DMA_CSSA_U5
DMA Channel 5 Source Start Address Register (upper bits)
0x0CA6
DMA_CDSA_L5
DMA Channel 5 Source Destination Address Register (lower bits)
0x0CA7
DMA_CDSA_U5
DMA Channel 5 Source Destination Address Register (upper bits)
0x0CA8
DMA_CEN5
DMA Channel 5 Element Number Register
0x0CA9
DMA_CFN5
DMA Channel 5 Frame Number Register
0x0CAA
DMA_CFI5/
DMA_CSFI5†
DMA Channel 5 Frame Index Register/
DMA Channel 5 Source Frame Index Register†
0x0CAB
DMA_CEI5/
DMA_CSEI5‡
DMA Channel 5 Element Index Register/
DMA Channel 5 Source Element Index Register‡
0x0CAC
DMA_CSAC5
DMA Channel 5 Source Address Counter
0x0CAD
DMA_CDAC5
DMA Channel 5 Destination Address Counter
0x0CAE
DMA_CDEI5
DMA Channel 5 Destination Element Index Register
0x0CAF
DMA_CDFI5
DMA Channel 5 Destination Frame Index Register
† On revision 1.x, the channel frame index applies to both source and destination and this register behaves as DMA_CFIn. On revision 2.0 and
later, DMA_CSFIn and DMA_CDFIn provide separate source and destination frame indexing. Revisions 2.0 and later can be programmed
for software compatibility with revisions 1.x through the Software Compatibility Register (DMA_GSCR).
‡ On revision 1.x, the channel element index applies to both source and destination and this register behaves as DMA_CEIn. On revision 2.0
and later, DMA_CSEIn and DMA_CDEIn provide separate source and destination frame indexing. Revisions 2.0 and later can be programmed
for software compatibility with revisions 1.x through the Software Compatibility Register (DMA_GSCR).
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27
Functional Overview
Table 3−14. Clock Generator Registers
PORT ADDRESS
0x1C00
REGISTER NAME
CLKMD
DESCRIPTION
Clock Mode Register
Table 3−15. Timer Registers
PORT ADDRESS
REGISTER NAME
DESCRIPTION
0x1000
TIM0
Timer 0 Count Register
0x1001
PRD0
Timer 0 Period Register
0x1002
TCR0
Timer 0 Timer Control Register
0x1003
PRSC0
Timer 0 Timer Prescaler Register
0x2400
TIM1
Timer 1 Timer Count Register
0x2401
PRD1
Timer 1 Period Register
0x2402
TCR1
Timer 1 Timer Control Register
0x2403
PRSC1
Timer 1 Timer Prescaler Register
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Functional Overview
Table 3−16. Multichannel Serial Port #0 Registers
PORT ADDRESS
REGISTER NAME
DESCRIPTION
0x2800
DRR2_0
McBSP 0 Data Receive Register 2
0x2801
DRR1_0
McBSP 0 Data Receive Register 1
0x2802
DXR2_0
McBSP 0 Data Transmit Register 2
0x2803
DXR1_0
McBSP 0 Data Transmit Register 1
0x2804
SPCR2_0
McBSP 0 Serial Port Control Register 2
0x2805
SPCR1_0
McBSP 0 Serial Port Control Register 1
0x2806
RCR2_0
McBSP 0 Receive Control Register 2
0x2807
RCR1_0
McBSP 0 Receive Control Register 1
0x2808
XCR2_0
McBSP 0 Transmit Control Register 2
0x2809
XCR1_0
McBSP 0 Transmit Control Register 1
0x280A
SRGR2_0
McBSP 0 Sample Rate Generator Register 2
0x280B
SRGR1_0
McBSP 0 Sample Rate Generator Register 1
0x280C
MCR2_0
McBSP 0 Multichannel Register 2
0x280D
MCR1_0
McBSP 0 Multichannel Register 1
0x280E
RCERA_0
McBSP 0 Receive Channel Enable Register Partition A
0x280F
RCERB_0
McBSP 0 Receive Channel Enable Register Partition B
0x2810
XCERA_0
McBSP 0 Transmit Channel Enable Register Partition A
0x2811
XCERB_0
McBSP 0 Transmit Channel Enable Register Partition B
0x2812
PCR0
McBSP 0 Pin Control Register
0x2813
RCERC_0
McBSP 0 Receive Channel Enable Register Partition C
0x2814
RCERD_0
McBSP 0 Receive Channel Enable Register Partition D
0x2815
XCERC_0
McBSP 0 Transmit Channel Enable Register Partition C
0x2816
XCERD_0
McBSP 0 Transmit Channel Enable Register Partition D
0x2817
RCERE_0
McBSP 0 Receive Channel Enable Register Partition E
0x2818
RCERF_0
McBSP 0 Receive Channel Enable Register Partition F
0x2819
XCERE_0
McBSP 0 Transmit Channel Enable Register Partition E
0x281A
XCERF_0
McBSP 0 Transmit Channel Enable Register Partition F
0x281B
RCERG_0
McBSP 0 Receive Channel Enable Register Partition G
0x281C
RCERH_0
McBSP 0 Receive Channel Enable Register Partition H
0x281D
XCERG_0
McBSP 0 Transmit Channel Enable Register Partition G
0x281E
XCERH_0
McBSP 0 Transmit Channel Enable Register Partition H
August 2003 − Revised November 2003
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Functional Overview
Table 3−17. Multichannel Serial Port #1 Registers
PORT ADDRESS
REGISTER NAME
DESCRIPTION
0x2C00
DRR2_1
McBSP 1 Data Receive Register 2
0x2C01
DRR1_1
McBSP 1 Data Receive Register 1
0x2C02
DXR2_1
McBSP 1 Data Transmit Register 2
0x2C03
DXR1_1
McBSP 1 Data Transmit Register 1
0x2C04
SPCR2_1
McBSP 1 Serial Port Control Register 2
0x2C05
SPCR1_1
McBSP 1 Serial Port Control Register 1
0x2C06
RCR2_1
McBSP 1 Receive Control Register 2
0x2C07
RCR1_1
McBSP 1 Receive Control Register 1
0x2C08
XCR2_1
McBSP 1 Transmit Control Register 2
0x2C09
XCR1_1
McBSP 1 Transmit Control Register 1
0x2C0A
SRGR2_1
McBSP 1 Sample Rate Generator Register 2
0x2C0B
SRGR1_1
McBSP 1 Sample Rate Generator Register 1
0x2C0C
MCR2_1
McBSP 1 Multichannel Register 2
0x2C0D
MCR1_1
McBSP 1 Multichannel Register 1
0x2C0E
RCERA_1
McBSP 1 Receive Channel Enable Register Partition A
0x2C0F
RCERB_1
McBSP 1 Receive Channel Enable Register Partition B
0x2C10
XCERA_1
McBSP 1 Transmit Channel Enable Register Partition A
0x2C11
XCERB_1
McBSP 1 Transmit Channel Enable Register Partition B
0x2C12
PCR1
McBSP 1 Pin Control Register
0x2C13
RCERC_1
McBSP 1 Receive Channel Enable Register Partition C
0x2C14
RCERD_1
McBSP 1 Receive Channel Enable Register Partition D
0x2C15
XCERC_1
McBSP 1 Transmit Channel Enable Register Partition C
0x2C16
XCERD_1
McBSP 1 Transmit Channel Enable Register Partition D
0x2C17
RCERE_1
McBSP 1 Receive Channel Enable Register Partition E
0x2C18
RCERF_1
McBSP 1 Receive Channel Enable Register Partition F
0x2C19
XCERE_1
McBSP 1 Transmit Channel Enable Register Partition E
0x2C1A
XCERF_1
McBSP 1 Transmit Channel Enable Register Partition F
0x2C1B
RCERG_1
McBSP 1 Receive Channel Enable Register Partition G
0x2C1C
RCERH_1
McBSP 1 Receive Channel Enable Register Partition H
0x2C1D
XCERG_1
McBSP 1 Transmit Channel Enable Register Partition G
0x2C1E
XCERH_1
McBSP 1 Transmit Channel Enable Register Partition H
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Functional Overview
Table 3−18. Multichannel Serial Port #2 Registers
PORT ADDRESS
REGISTER NAME
DESCRIPTION
0x3000
DRR2_2
McBSP 2 Data Receive Register 2
0x3001
DRR1_2
McBSP 2 Data Receive Register 1
0x3002
DXR2_2
McBSP 2 Data Transmit Register 2
0x3003
DXR1_2
McBSP 2 Data Transmit Register 1
0x3004
SPCR2_2
McBSP 2 Serial Port Control Register 2
0x3005
SPCR1_2
McBSP 2 Serial Port Control Register 1
0x3006
RCR2_2
McBSP 2 Receive Control Register 2
0x3007
RCR1_2
McBSP 2 Receive Control Register 1
0x3008
XCR2_2
McBSP 2 Transmit Control Register 2
0x3009
XCR1_2
McBSP 2 Transmit Control Register 1
0x300A
SRGR2_2
McBSP 2 Sample Rate Generator Register 2
0x300B
SRGR1_2
McBSP 2 Sample Rate Generator Register 1
0x300C
MCR2_2
McBSP 2 Multichannel Register 2
0x300D
MCR1_2
McBSP 2 Multichannel Register 1
0x300E
RCERA_2
McBSP 2 Receive Channel Enable Register Partition A
0x300F
RCERB_2
McBSP 2 Receive Channel Enable Register Partition B
0x3010
XCERA_2
McBSP 2 Transmit Channel Enable Register Partition A
0x3011
XCERB_2
McBSP 2 Transmit Channel Enable Register Partition B
0x3012
PCR2
McBSP 2 Pin Control Register
0x3013
RCERC_2
McBSP 2 Receive Channel Enable Register Partition C
0x3014
RCERD_2
McBSP 2 Receive Channel Enable Register Partition D
0x3015
XCERC_2
McBSP 2 Transmit Channel Enable Register Partition C
0x3016
XCERD_2
McBSP 2 Transmit Channel Enable Register Partition D
0x3017
RCERE_2
McBSP 2 Receive Channel Enable Register Partition E
0x3018
RCERF_2
McBSP 2 Receive Channel Enable Register Partition F
0x3019
XCERE_2
McBSP 2 Transmit Channel Enable Register Partition E
0x301A
XCERF_2
McBSP 2 Transmit Channel Enable Register Partition F
0x301B
RCERG_2
McBSP 2 Receive Channel Enable Register Partition G
0x301C
RCERH_2
McBSP 2 Receive Channel Enable Register Partition H
0x301D
XCERG_2
McBSP 2 Transmit Channel Enable Register Partition G
0x301E
XCERH_2
McBSP 2 Transmit Channel Enable Register Partition H
August 2003 − Revised November 2003
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Functional Overview
Table 3−19. GPIO Registers
WORD ADDRESS
REGISTER NAME
DESCRIPTION
0x3400
IODIR
General-purpose I/O Direction Register
0x3401
IODATA
General-purpose I/O Data Register
Table 3−20. Device Revision ID Registers
PORT ADDRESS
0x3800 − 0x3803
0x3804
REGISTER NAME
Die_ID[63:0]
Rev_ID[15:0]
DESCRIPTION
†
Factory Die Identification
Identifies silicon revision
Revision 1.x: 0x8050
Revision 2.0: 0x6510
Revision 2.1: 0x6511
Revision 2.2: 0x6512
† The Die_ID register contains factory identification information and does not require any intervention from the user.
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Functional Overview
3.5
Interrupts
Vector-relative locations and priorities for all internal and external interrupts are shown in Table 3−21. The
locations of the interrupt vectors are defined as an offset from the location defined in the interrupt vector
pointers (IVPD and IVPH). For more detailed information about the interrupt vector pointers and interrupts,
see the TMS320C55x DSP CPU Reference Guide (literature number SPRU371).
Table 3−21. Interrupt Table
NAME
SOFTWARE
(TRAP)
EQUIVALENT
OFFSET LOCATION
(HEX BYTES)
PRIORITY
FUNCTION
RESET
SINT0
0
0
Reset (hardware and software)
NMI
SINT1
8
1
Nonmaskable interrupt
INT0
SINT2
10
3
External interrupt #0
INT2
SINT3
18
5
External interrupt #2
TINT0
SINT4
20
6
Timer #0 interrupt
RINT0
SINT5
28
7
McBSP #0 receive interrupt
RINT1
SINT6
30
9
McBSP #1 receive interrupt
XINT1
SINT7
38
10
McBSP #1 transmit interrupt
−
SINT8
40
11
Software interrupt #8
DMAC1
SINT9
48
13
DMA Channel #1 interrupt
DSPINT
SINT10
50
14
Interrupt from host (EHPI)
INT3
SINT11
58
15
External interrupt #3
RINT2
SINT12
60
17
McBSP #2 receive interrupt
XINT2
SINT13
68
18
McBSP #2 transmit interrupt
DMAC4
SINT14
70
21
DMA Channel #4 interrupt
DMAC5
SINT15
78
22
DMA Channel #5 interrupt
INT1
SINT16
80
4
External interrupt #1
XINT0
SINT17
88
8
McBSP #0 transmit interrupt
DMAC0
SINT18
90
12
DMA Channel #0 interrupt
INT4
SINT19
98
16
External interrupt #4
DMAC2
SINT20
A0
19
DMA Channel #2 interrupt
DMAC3
SINT21
A8
20
DMA Channel #3 interrupt
TINT1
SINT22
B0
23
Timer #1 interrupt
INT5
SINT23
B8
24
External interrupt #5
BERR
SINT24
C0
2
Bus Error interrupt
DLOG
SINT25
C8
25
Data Log interrupt
RTOS
SINT26
D0
26
Real-time Operating System interrupt
−
SINT27
D8
27
Software interrupt #27
−
SINT28
E0
28
Software interrupt #28
−
SINT29
E8
29
Software interrupt #29
−
SINT30
F0
30
Software interrupt #30
SINT31
F8
31
Software interrupt #31
August 2003 − Revised November 2003
SGUS045A
33
Functional Overview
3.5.1 IFR and IER Registers
The Interrupt Enable Registers (IER0 and IER1) control which interrupts will be masked or enabled during
normal operation. The Interrupt Flag Registers (IFR0 and IFR1) contain flags that indicate interrupts that are
currently pending.
The Debug Interrupt Enable Registers (DBIER0 and DBIER1) are used only when the CPU is halted in the
real-time emulation mode. If the CPU is running in real-time mode, the standard interrupt processing (IER0/1)
is used and DBIER0/1 are ignored.
A maskable interrupt enabled in a DBIER0/1 is defined as a time-critical interrupt. When the CPU is halted
in the real-time mode, the only interrupts that are serviced are time-critical interrupts that are also enabled in
an interrupt enable register (IER0 or IER1)
Write the DBIER0/1 to enable or disable time-critical interrupts. To enable an interrupt, set its corresponding
bit. To disable an interrupt, clear its corresponding bit. Note that DBIER0/1 are not affected by a software reset
instruction or by a DSP hardware reset. Initialize these registers before using the real-time emulation mode.
The bit layouts of these registers for each interrupt are shown in Figure 3−7.
15
14
13
12
11
10
9
8
DMAC5
DMAC4
XINT2
RINT2
INT3
DSPINT
DMAC1
Reserved
7
6
5
4
3
2
XINT1
RINT1
RINT0
TINT0
INT2
INT0
1
0
Reserved
Figure 3−7. IFR0, IER0, DBIFR0, and DBIER0 Bit Locations
The IFR1 (Interrupt Flag Register 1) and IER1 (Interrupt Enable Register 1) bit layouts are shown in
Figure 3−8.
15
11
Reserved
10
9
8
RTOS
DLOG
BERR
7
6
5
4
3
2
1
0
INT5
TINT1
DMAC3
DMAC2
INT4
DMAC0
XINT0
INT1
Figure 3−8. IFR1, IER1, DBIFR1, and DBIER1 Bit Locations
3.5.2 Interrupt Timing
The external interrupts (NMI and INTx) are automatically synchronized to the CPU. The interrupt inputs are
sampled on the falling edges of the CPU clock. A sequence on the interrupt pin of 1-0-0-0 on consecutive
cycles is required for an interrupt to be detected. Therefore, the minimum low pulse duration on the external
interrupts on the 5510 is three CPU clock periods.
34
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Functional Overview
3.6
Notices Concerning CLKOUT Operation
3.6.1 CLKOUT Voltage Level
On the 320VC5510, CLKOUT is driven at CVDD supply voltage. This voltage level may be too low to interface
to some devices. In that event, buffers may need to be employed to support interfacing CLKOUT.
3.6.2 CLKOUT Value During Reset
During reset, the CLKOUT pin is driven to a logic 1 instead of logic 0 as indicated in the TMS320C55x DSP
CPU Reference Guide (literature number SPRU371).
August 2003 − Revised November 2003
SGUS045A
35
Documentation Support
4
Documentation Support
Extensive documentation supports all TMS320 DSP family of devices from product announcement through
applications development. The following types of documentation are available to support the design and use
of the TMS320C5000 platform of DSPs:
•
•
•
•
•
•
•
TMS320C55x DSP Functional Overview (literature number SPRU312)
TMS320C55x DSP Peripherals Reference Guide (literature number SPRU317)
TMS320C55x DSP CPU Reference Guide (literature number SPRU371)
Device-specific data sheets
Complete user’s guides
Development support tools
Hardware and software application reports
The reference set describes in detail the TMS320C55x DSP products currently available and the hardware
and software applications, including algorithms, for fixed-point TMS320 DSP family of devices.
A series of DSP textbooks is published by Prentice-Hall and John Wiley & Sons to support digital signal
processing research and education. The TMS320 DSP newsletter, Details on Signal Processing, is published
quarterly and distributed to update TMS320 DSP customers on product information.
Information regarding Texas Instruments (TI) DSP products is also available on the Worldwide Web at
http://www.ti.com uniform resource locator (URL).
4.1
Device and Development-Support Tool Nomenclature
To designate the stages in the product development cycle, TI assigns prefixes to the part numbers of all 320
DSP devices and support tools. Each 320 DSP commercial family member has one of three prefixes: SMX,
TMP, or SM/SMJ. Texas Instruments recommends two of three possible prefix designators for support tools:
TMDX and TMDS. These prefixes represent evolutionary stages of product development from engineering
prototypes (SMX / TMDX) through fully qualified production devices/tools (SM/SMJ / TMDS).
Device development evolutionary flow:
SMX
Experimental device that is not necessarily representative of the final device’s electrical
specifications
TMP
Final silicon die that conforms to the device’s electrical specifications but has not completed quality
and reliability verification
SM/SMJ Fully qualified production device
Support tool development evolutionary flow:
TMDX
Development-support product that has not yet completed Texas Instruments internal qualification
testing.
TMDS
Fully qualified development-support product
SMX and TMP devices and TMDX development-support tools are shipped with appropriate disclaimers
describing their limitations and intended uses. Experimental devices (SMX) may not be representative of a
final product and Texas Instruments reserves the right to change or discontinue these products without notice.
SM/SMJ devices and TMDS development-support tools have been characterized fully, and the quality and
reliability of the device have been demonstrated fully. TI’s standard warranty applies.
Predictions show that prototype devices (SMX or TMP) have a greater failure rate than the standard
production devices. Texas Instruments recommends that these devices not be used in any production system
because their expected end-use failure rate still is undefined. Only qualified production devices are to be used.
TMS320C5000 is a trademark of Texas Instruments.
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Documentation Support
4.2
320VC5510 Device Nomenclature
SM
PREFIX
SMX =
TMP =
TMS =
SMJ =
SM =
320 VC 5510 (A)
GGW
(A)
2
EP
Experimental device
Prototype device
Qualified device
MIL-STD-883C
Commercial processing
ENHANCED PLASTIC DESIGNATOR
DEVICE SPEED RANGE
1 = 160 MHz
2 = 200 MHz
DEVICE FAMILY
320 or
32 = TMS320 family
DEVICE TEMP. RANGE
(no suffix) = 0° to 85°C
A = −40° to 85°C
TECHNOLOGY
VC = Dual-Supply CMOS
PACKAGE TYPE†
GGW = 240-pin plastic BGA
DEVICE REVISION
(no suffix) = Revision 2.1
A = Revision 2.2
DEVICE
55x DSP:
5510
† BGA =
Ball Grid Array
Figure 4−1. Device Nomenclature for the 320VC5510
August 2003 − Revised November 2003
SGUS045A
37
Electrical Specifications
5
Electrical Specifications
This section provides the absolute maximum ratings and the recommended operating conditions for the
SM320VC5510A-EP DSP.
All electrical and switching characteristics in this data manual are valid over the recommended operating
conditions unless otherwise specified.
See Figure 5−1 for the test load circuit values on a 3.3-V device. Measured timing information contained in
this data manual is based on the test load setup and conditions shown in Figure 5−1.
5.1
Absolute Maximum Ratings†
Supply voltage I/O range, DVDD‡ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . − 0.3 V to 4.0 V
Supply voltage core range, CVDD‡ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . − 0.3 V to 2.0 V
Input voltage range, VI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . − 0.3 V to 4.5 V
Output voltage range, VO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . − 0.3 V to 4.5 V
Operating case temperature range, TC: (Extended)§ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . − 40_C to 85°C
Storage temperature range Tstg§ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . − 55_C to 150_C
† Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
‡ All voltage values are with respect to VSS
.
§ Long term high-temperature storage and/or extended use at maximum recommended operating conditions may result in a reduction of overall
device life. See www.ti.com/ep_quality for additional information on enhanced plastic packaging.
5.2
DVDD
Recommended Operating Conditions
Device supply voltage, I/O
CVDD
Device supply voltage, core
VSS
Supply voltage, GND
Prototype revisions 2.1 and 2.2 and
production silicon†
High-level input voltage, I/O
DVDD = 3.3 ± 0.3 V
All other inputs
Hysteresis inputs
VIL
Low-level input voltage, I/O
DVDD = 3.3 ± 0.3 V
All other inputs
IOH
IOL
NOM
MAX
3.0
3.3
3.6
V
1.55
1.6
1.65
V
0
Hysteresis inputs
VIH
MIN
UNIT
V
2.4
DVDD + 0.3
2.0
DVDD + 0.3
−0.3
0.8
−0.3
0.8
V
V
High-level output current
All outputs
−8
mA
Low-level output current
All outputs
8
mA
TC
Operating case temperature
Extended Temperature Range
−40
85
°C
† See the TMS320VC5510 Digital Signal Processor Silicon Errata (literature number SPRZ008) for further clarification and distinguishing markings.
38
SGUS045A
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Electrical Specifications
5.3
Electrical Characteristics Over Recommended Operating Case Temperature
Range (Unless Otherwise Noted)
PARAMETER
VOH
VOL
IIZ
High-level output
voltage
2.4
CLKOUT
CVDD = 1.6 ± 0.05 V,
IOH = MAX
1.24
Output-only or input/output pins with
bus holders
All other output-only or input/output
pins
Input pins with internal pulldown
II
Input current
Input pins with internal pullup
All other input-only pins or input-only
pins with pullup/pulldown disabled
IDDC
CVDD supply current, CPU + internal memory access †
IDDP
DVDD supply current, pins active ‡
IDDC
CVDD supply current, standby
Only CLKGEN domain enabled, PLL enabled.
IDDC
CVDD supply current, standby
All domains idled.
IOL = MAX
Bus holders enabled
CVDD = MAX,
VO = VSS to VDD
Bus holders disabled
CVDD = MAX,
VO = VSS to VDD
CVDD = MAX,
VI = VSS to VDD
Pullup enabled
CVDD = MAX,
VI = VSS to VDD
CVDD = MAX,
VI = VSS to VDD
CVDD = 1.6 V,
CPU clock = 200 MHz
TC = 25°C
DVDD = 3.3 V
CPU clock = 100 MHz
TC = 25°C
CVDD = 1.6 V
10-MHz clock input,
DPLL mode = x 20
TC = 25°C
CVDD = 1.6 V
input clock stopped,
TC = 25°C
CVDD = 1.6 V
input clock stopped,
TC = 55°C
CVDD = 1.6 V
input clock stopped,
TC = 85°C
DVDD = 3.3 V
no pin activity,
TC = 25°C
IDDP
MIN
All output except CLKOUT
Low-level output voltage
Input current for outputs
in high impedance
TEST CONDITIONS
DVDD = 3.3 ± 0.3 V,
IOH = MAX
DVDD supply current, standby
All domains idled.
DVDD = 3.3 V
no pin activity,
TC = 55°C
DVDD = 3.3 V
no pin activity,
TC = 85°C
TYP
MAX
UNIT
V
0.4
− 275
V
275
µA
A
−5
5
−5
300
− 300
5
−5
5
µA
112
mA
8
mA
32
mA
69
µA
374
µA
976
µA
10
µA
10
µA
10
µA
Ci
Input capacitance
3
pF
Co
Output capacitance
3
pF
† Test Condition: CPU executing 75% Dual-MAC / 25% ADD with moderate data bus activity (table of sine values). CPU and CLKGEN domains
are active. All other domains are idled. The DPLL is enabled.
‡ Test Condition: One word of a table of 16-bit sine values is written to the EMIF each microsecond (16 Mbps). Each EMIF output pin is connected
to a 10-pF load capacitance.
August 2003 − Revised November 2003
SGUS045A
39
Electrical Specifications
IOL-test
50 Ω
Tester Pin
Electronics
Output
Under
Test
VLoad
CT
IOH-test
Where:
IOL-test
IOH-test
VLoad
CT
=
=
=
=
+2 mA (all outputs)
−2 mA (all outputs)
50% of DVdd
15 pF typical load circuit capacitance.
Figure 5−1. 3.3-V Test Load Circuit
5.4
Package Thermal Resistance Characteristics
Table 5−1 provides the thermal resistance characteristics for the recommended package types used on the
320VC5510 DSP.
Table 5−1. Thermal Resistance Characteristics (Ambient)
RΘJA (°C / W)
BOARD TYPE†
AIRFLOW (LFM)
26
High-K
0
22
High-K
150
20
High-K
250
50
Low-K
0
35
Low-K
150
29
Low-K
250
† Board types are as defined by JEDEC. Reference JEDEC Standard JESD51-9, Test Boards for Area Array Surface Mount Package Thermal
Measurements.
Table 5−2. Thermal Resistance Characteristics (Case)
RΘJC (°C / W)
BOARD TYPE†
6
2s JEDEC Test Card
† Board types are as defined by JEDEC. Reference JEDEC Standard JESD51-9, Test Boards for Area Array Surface Mount Package Thermal
Measurements.
40
SGUS045A
August 2003 − Revised November 2003
Electrical Specifications
5.5
Timing Parameter Symbology
Timing parameter symbols used in the timing requirements and switching characteristics tables are created
in accordance with JEDEC Standard 100. To shorten the symbols, some of the pin names and other related
terminology have been abbreviated as follows:
Lowercase subscripts and their meanings:
Letters and symbols and their meanings:
a
access time
H
High
c
cycle time (period)
L
Low
d
delay time
V
Valid
dis
disable time
Z
High impedance
en
enable time
f
fall time
h
hold time
r
rise time
su
setup time
t
transition time
v
valid time
w
pulse duration (width)
X
Unknown, changing, or don’t care level
August 2003 − Revised November 2003
SGUS045A
41
Electrical Specifications
5.6
Clock Options
This section provides the timing requirements and switching characteristics for the various clock options
available on the 5510.
5.6.1 Clock Generation in Bypass Mode (DPLL Disabled)
The frequency of the reference clock provided at the CLKIN pin can be divided by a factor of one, two, or four
to generate the internal CPU clock cycle. The divide factor (D) is set in the BYPASS_DIV field of the clock mode
register. The contents of this field only affect clock generation while the device is in bypass mode. In this mode,
the digital phase-locked loop (DPLL) clock synthesis is disabled.
Table 5−3 and Table 5−4 assume testing over recommended operating conditions and H = 0.5tc(CO) (see
Figure 5−2).
Table 5−3. CLKIN in Bypass Mode Timing Requirements
VC5510-200
NO.
C7
MIN
MAX
20
UNIT
tc(CI)
tf(CI)
Cycle time, CLKIN
†
ns
C8
Fall time, CLKIN
6
ns
C9
tr(CI)
Rise time, CLKIN
6
ns
C10
tw(CIL)
Pulse duration, CLKIN low
4
ns
C11
tw(CIH)
Pulse duration, CLKIN high
4
ns
† This device utilizes a fully static design and therefore can operate with tc(CI) approaching ∞. The device is characterized at frequencies
approaching 0 Hz.
Table 5−4. CLKOUT in Bypass Mode Switching Characteristics
VC5510-200
NO.
C1
C2
C3
C4
C5
C6
PARAMETER
MIN
MAX
20
TYP
tc(CI)/N‡
1
7
14
UNIT
tc(CO)
td(CI-CO)
Cycle time, CLKOUT
tf(CO)
tr(CO)
Fall time, CLKOUT
tw(COL)
tw(COH)
Pulse duration, CLKOUT low
H−1
H+1
ns
Pulse duration, CLKOUT high
H−1
H+1
ns
Delay time, CLKIN high/low to CLKOUT high/low
ns
1
Rise time, CLKOUT
ns
ns
1
ns
‡ N = Clock frequency synthesis factor
C11
C9
C8
C10
C7
CLKIN
C1
C2
C6
C3
C4
C5
CLKOUT
NOTE A: The relationship of CLKIN to CLKOUT depends on the divide factor chosen. The waveform relationship shown in Figure 5−2 is intended
to illustrate the timing parameters only and may differ based on configuration.
Figure 5−2. Bypass Mode Clock Timing
42
SGUS045A
August 2003 − Revised November 2003
Electrical Specifications
5.6.2 Clock Generation in Lock Mode (DPLL Synthesis Enabled)
The frequency of the reference clock provided at the CLKIN pin can be multiplied by a synthesis factor of N
to generate the internal CPU clock cycle. The synthesis factor is determined by:
N+ M
DL
where: M = the multiply factor set in the PLL_MULT field of the clock mode register,
DL = the divide factor set in the PLL_DIV field of the clock mode register
Valid values for M are (multiply by) 2 to 31. Valid values for DL are (divide by) 1, 2, 3, and 4.
For detailed information on clock generation configuration, see the TMS320C55x DSP Peripherals Reference
Guide (literature number SPRU317).
Table 5−5 and Table 5−6 assume testing over recommended operating conditions and H = 0.5tc(CO) (see
Figure 5−3).
Table 5−5. CLKIN in Lock Mode Timing Requirements
VC5510-200
NO.
C7
Cycle time, CLKIN
C8
tc(CI)
tf(CI)
C9
tr(CI)
C10
tw(CIL)
Pulse duration, CLKIN low
MIN
20†
DPLL synthesis enabled
MAX
UNIT
400
ns
Fall time, CLKIN
6
ns
Rise time, CLKIN
6
ns
4
ns
C11 tw(CIH) Pulse duration, CLKIN high
4
ns
† The clock frequency synthesis factor and minimum CLKIN cycle time should be chosen such that the resulting CLKOUT cycle time is within the
specified range (tc(CO)).
Table 5−6. CLKOUT in Lock Mode Switching Characteristics
VC5510-200
NO.
C1
C2
C3
C4
C5
C6
PARAMETER
MIN
MAX
14
UNIT
tc(CO)
td(CI-CO)
Cycle time, CLKOUT
5
TYP
tc(CI)/N‡
Delay time, CLKIN high/low to CLKOUT high/low
1
7
tf(CO)
tr(CO)
Fall time, CLKOUT
1
ns
Rise time, CLKOUT
1
ns
tw(COL)
tw(COH)
Pulse duration, CLKOUT low
H−1
H+1
ns
Pulse duration, CLKOUT high
H−1
H+1
ns
ns
ns
‡ N = Clock frequency synthesis factor
C8
C10
C9
C11
C7
CLKIN
C2
C1
CLKOUT
C5
C3
C6
C4
Bypass Mode
NOTE A: The waveform relationship of CLKIN to CLKOUT depends on the multiply and divide factors chosen. The waveform relationship shown
in Figure 5−3 is intended to illustrate the timing parameters only and may differ based on configuration.
Figure 5−3. External Multiply-by-N Clock Timing
August 2003 − Revised November 2003
SGUS045A
43
Electrical Specifications
5.7
Memory Timing
5.7.1 Asynchronous Memory Timing
Table 5−7 and Table 5−8 assume testing over recommended operating conditions (see Figure 5−4 and
Figure 5−5). Note that the asynchronous memory interface is read-only when configured as 8-bit mode.
Asynchronous writes in 8-bit mode are not supported.
Table 5−7. Asynchronous Memory Cycles Timing Requirements
VC5510-200
NO.
A6
A7
A10
MIN
MAX
UNIT
tsu(DV-COH)
th(COH-DV)
Setup time, read data valid before CLKOUT high†
6
ns
Hold time, read data valid after CLKOUT high
0
ns
tsu(ARDY-COH)
th(COH-ARDY)
Setup time, ARDY valid before CLKOUT high
7
ns
A11
Hold time, ARDY valid after CLKOUT high
0
ns
† To ensure data setup time, simply program the strobe width wide enough. ARDY is internally synchronized. If ARDY does meet setup or hold
time, it may be recognized in the current cycle or the next cycle. Thus, ARDY can be an asynchronous input.
Table 5−8. Asynchronous Memory Cycles Switching Characteristics‡§
VC5510-200
NO.
A1
A2
A3
A4
A5
A8
A9
A12
A13
A14
PARAMETER
UNIT
MIN
MAX
−2
4
ns
4
ns
td(COH-CEV)
td(COH-BEV)
Delay time, CLKOUT high to CEx transition
td(COH-BEIV)
td(COH-AV)
Delay time, CLKOUT high to BEx invalid
td(COH-AIV)
td(COH-AOEV)
Delay time, CLKOUT high to address invalid
−2
Delay time, CLKOUT high to AOE valid
−2
4
ns
td(COH-AREV)
td(COH-DV)
Delay time, CLKOUT high to ARE valid
−2
4
ns
4
ns
td(COH-DIV)
td(COH-AWEV)
Delay time, CLKOUT high to data invalid (write)
−2
Delay time, CLKOUT high to AWE valid
−2
Delay time, CLKOUT high to BEx valid
−2
Delay time, CLKOUT high to address valid
ns
4
Delay time, CLKOUT high to data valid (write)
ns
ns
ns
4
ns
‡ The minimum delay is also the minimum output hold after CLKOUT high.
§ All timings referenced to CLKOUT assume CLKOUT represents the internal CPU clock (divide-by-1 mode).
44
SGUS045A
August 2003 − Revised November 2003
Electrical Specifications
Setup = 1†
Strobe = 5†
Not ready = 2 Hold = 1†
Extended
Hold = 2†‡
CLKOUT§
A1
A1
A2
A3
A4
A5
CEx¶
BE[3:0]
A[21:0]
A6
A7
D[31:0]
A8
A8
AOE
A9
A9
ARE
AWE
A11
A10
A11
A10
ARDY#
† Setup, Strobe, Hold, and Extended Hold are programmable in the EMIF. The programmable Hold period is not associated with the activity of
the HOLD and HOLDA signals.
‡ The extended hold time is programmable in the EMIF and is only present when consecutive memory accesses are made to different CEx spaces,
or are of different types (read/write).
§ All timings referenced to CLKOUT assume CLKOUT is the same frequency as the internal CPU clock (divide-by-1 mode).
¶ The chip enable that becomes active depends on the address.
# ARDY is synchronized internally. If the setup time shown is not met, ARDY will be recognized on the next clock cycle.
Figure 5−4. Asynchronous Memory Read Timing
August 2003 − Revised November 2003
SGUS045A
45
Electrical Specifications
Setup = 1†
Strobe = 5†
Not ready = 2 Hold = 1†
Extended
Hold = 2†‡
CLKOUT§
A1
A1
A2
A3
A4
A5
CEx¶
BE[3:0]
A[21:0]
A12
A13
D[31:0]
AOE
ARE
300
A14
A14
AWE
A11
A10
A11
A10
ARDY#
† Setup, Strobe, Hold, and Extended Hold are programmable in the EMIF. The programmable Hold period is not associated with the activity of
the HOLD and HOLDA signals.
‡ The extended hold time is programmable in the EMIF and is only present when consecutive memory accesses are made to different CEx spaces,
or are of different types (read/write).
§ All timings referenced to CLKOUT assume CLKOUT is the same frequency as the internal CPU clock (divide-by-1 mode).
¶ The chip enable that becomes active depends on the address.
# ARDY is synchronized internally. If the setup time shown is not met, ARDY will be recognized on the next clock cycle.
Figure 5−5. Asynchronous Memory Write Timing
46
SGUS045A
August 2003 − Revised November 2003
Electrical Specifications
5.7.2 Synchronous-Burst SRAM (SBSRAM) Timing
Table 5−9 and Table 5−10 assume testing over recommended operating conditions (see Figure 5−6 and
Figure 5−7).
Table 5−9. Synchronous-Burst SRAM Cycle Timing Requirements
VC5510-200
NO.
SB7
SB8
MIN
tsu(DV-CLKMEMH)
th(CLKMEMH-DV)
MAX
UNIT
Setup time, read data valid before CLKMEM high
5
ns
Hold time, read data valid after CLKMEM high
2
ns
Table 5−10. Synchronous-Burst SRAM Cycle Switching Characteristics
VC5510-200
NO.
SB1
PARAMETER
MIN
MAX
UNIT
td(CLKMEMH-CEL)
td(CLKMEMH-CEH)
Delay time, CLKMEM high to CEx low
3
6
ns
Delay time, CLKMEM high to CEx high
3
6
ns
td(CLKMEMH-BEV)
td(CLKMEMH-BEIV)
Delay time, CLKMEM high to BEx valid
3
6
ns
Delay time, CLKMEM high to BEx invalid
3
6
ns
td(CLKMEMH-AV)
td(CLKMEMH-AIV)
Delay time, CLKMEM high to address valid
3
6
ns
Delay time, CLKMEM high to address invalid
3
6
ns
td(CLKMEMH-ADSL)
td(CLKMEMH-ADSH)
Delay time, CLKMEM high to SSADS low
3
6
ns
Delay time, CLKMEM high to SSADS high
3
6
ns
td(CLKMEMH-OEL)
td(CLKMEMH-OEH)
Delay time, CLKMEM high to SSOE low
3
6
ns
Delay time, CLKMEM high to SSOE high
3
6
ns
Delay time, CLKMEM high to data valid
3
6
ns
SB14
td(CLKMEMH-DV)
td(CLKMEMH-DIV)
Delay time, CLKMEM high to data invalid
3
6
ns
SB15
td(CLKMEMH-WEL)
Delay time, CLKMEM high to SSWE low
3
6
ns
SB16
td(CLKMEMH-WEH)
Delay time, CLKMEM high to SSWE high
3
6
ns
SB2
SB3
SB4
SB5
SB6
SB9
SB10
SB11
SB12
SB13
August 2003 − Revised November 2003
SGUS045A
47
Electrical Specifications
CLKMEM
SB1
SB2
CEx†
SB3
BE[3:0]
BE1
SB4
BE2
BE3
BE4
A3
A4
SB6
SB5
A[21:0]
A1
A2
SB7
SB8
Q2
Q2
Q1
D[31:0]
Q3
Q3
Q4
Q4
SB9
SB10
SSADS
SB11
SB12
SSOE
SSWE
† The chip enable that becomes active depends on the address.
Figure 5−6. SBSRAM Read Timing
CLKMEM
SB1
SB2
SB3
SB4
CEx†
BE[3:0]
BE1
BE2
BE3
BE4
SB5
A[21:0]
A1
SB6
A2
A3
A4
D2
D3
D4
SB13
D[31:0]
D1
SB14
SB9
SB10
SB15
SB16
SSADS
SSOE
SSWE
† The chip enable that becomes active depends on the address.
Figure 5−7. SBSRAM Write Timing
48
SGUS045A
August 2003 − Revised November 2003
Electrical Specifications
5.7.3 Synchronous DRAM (SDRAM) Timing
Table 5−11 and Table 5−12 assume testing over recommended operating conditions (see Figure 5−8 through
Figure 5−13).
Table 5−11. Synchronous DRAM Cycle Timing Requirements
VC5510-200
NO.
SD7
SD8
MIN
tsu(DV-CLKMEMH)
th(CLKMEMH-DV)
UNIT
MAX
Setup time, read data valid before CLKMEM high
5
ns
Hold time, read data valid after CLKMEM high
2
ns
Table 5−12. Synchronous DRAM Cycle Switching Characteristics
VC5510-200
NO.
SD1
SD2
SD3
SD4
SD5
SD6
SD9
SD10
SD11
SD12
SD13
SD14
SD15
SD16
SD17
SD18
PARAMETER
MIN
MAX
UNIT
td(CLKMEMH-CEL)
td(CLKMEMH-CEH)
Delay time, CLKMEM high to CEx low
3
6
ns
Delay time, CLKMEM high to CEx high
3
6
ns
td(CLKMEMH-BEV)
td(CLKMEMH-BEIV)
Delay time, CLKMEM high to BEx valid
3
6
ns
Delay time, CLKMEM high to BEx invalid
3
6
ns
td(CLKMEMH-AV)
td(CLKMEMH-AIV)
Delay time, CLKMEM high to address valid
3
6
ns
Delay time, CLKMEM high to address invalid
3
6
ns
td(CLKMEMH-SDCASL)
td(CLKMEMH-SDCASH)
Delay time, CLKMEM high to SDCAS low
3
5
ns
Delay time, CLKMEM high to SDCAS high
3
5
ns
td(CLKMEMH-DV)
td(CLKMEMH-DIV)
Delay time, CLKMEM high to data valid
3
5
ns
Delay time, CLKMEM high to data invalid
3
5
ns
td(CLKMEMH-SDWEL)
td(CLKMEMH-SDWEH)
Delay time, CLKMEM high to SDWE low
3
5
ns
Delay time, CLKMEM high to SDWE high
3
5
ns
td(CLKMEMH-SDA10V)
td(CLKMEMH-SDA10IV)
Delay time, CLKMEM high to SDA10 valid
3
5
ns
Delay time, CLKMEM high to SDA10 invalid
3
5
ns
td(CLKMEMH-SDRASL)
td(CLKMEMH-SDRASH)
Delay time, CLKMEM high to SDRAS low
3
5
ns
Delay time, CLKMEM high to SDRAS high
3
5
ns
August 2003 − Revised November 2003
SGUS045A
49
Electrical Specifications
READ
READ
CLKMEM
SD1
SD2
CEx†
SD3
BE[3:0]‡
SD5
A[15:2]§
CA1
SD6
CA2
SD7
SD8
D2
D1
D[31:0]
SD15
SD16
SDA10
SDRAS
SD9
SD10
SDCAS
SDWE
† The chip enable that becomes active depends on the address.
‡ All BE[3:0] signals are driven low (active) during reads. Byte manipulation of the read data is performed inside the EMIF. These signals remain
active until the next access that is not an SDRAM read occurs.
§ The number of address signals used depends on the SDRAM size and width.
Figure 5−8. Two SDRAM Read Commands (Active Row)
WRITE
WRITE
CLKMEM
SD1
SD2
CEx†
SD3
BE[3:0]
BE1
SD5
A[15:2]‡
CA1
SD11
D1
D[31:0]
SD4
BE2
SD6
CA2
SD12
D2
SD15
SD16
SD9
SD10
SD13
SD14
SDA10
SDRAS
SDCAS
SDWE
† The chip enable that becomes active depends on the address.
‡ The number of address signals used depends on the SDRAM size and width.
Figure 5−9. Two SDRAM WRT Commands (Active Row)
50
SGUS045A
August 2003 − Revised November 2003
Electrical Specifications
ACTV
CLKMEM
SD2
SD1
CEx†
BE[3:0]
SD5
A[15:2]‡
Bank Activate/Row Address
D[31:0]
SD15
Row Address
SDA10
SD18
SD17
SDRAS
SDCAS
SDWE
† The chip enable that becomes active depends on the address.
‡ The number of address signals used depends on the SDRAM size and width.
Figure 5−10. SDRAM ACTV Command
DCAB
CLKMEM
SD1
SD2
SD15
SD16
SD17
SD18
SD13
SD14
CEx†
BE[3:0]
A[15:2]‡
D[31:0]
SDA10
SDRAS
SDCAS
SDWE
† The chip enable that becomes active depends on the address.
‡ The number of address signals used depends on the SDRAM size and width.
Figure 5−11. SDRAM DCAB Command
August 2003 − Revised November 2003
SGUS045A
51
Electrical Specifications
REFR
CLKMEM
SD1
SD2
SD15
SD16
SD17
SD18
SD9
SD10
CEx†
BE[3:0]
A[15:2]‡
D[31:0]
SDA10
SDRAS
SDCAS
SDWE
† The chip enable that becomes active depends on the address.
‡ The number of address signals used depends on the SDRAM size and width.
Figure 5−12. SDRAM REFR Command
MRS
CLKMEM
SD1
SD2
SD5
SD6
CEx†
BE[3:0]
A[15:2]‡
MRS Value 0x30
D[31:0]
SD15
SD16
SD17
SD18
SD9
SD10
SD13
SD14
SDA10
SDRAS
SDCAS
SDWE
† The chip enable that becomes active depends on the address.
‡ The number of address signals used depends on the SDRAM size and width.
Figure 5−13. SDRAM MRS Command
52
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August 2003 − Revised November 2003
Electrical Specifications
5.8
HOLD and HOLDA Timings
Table 5−13 and Table 5−14 assume testing over recommended operating conditions (see Figure 5−14).
Table 5−13. HOLD and HOLDA Timing Requirements
VC5510-200
NO.
MIN
H1
tsu(HOLDH-COH)
Setup time, HOLD high before CLKOUT high†
† HOLD is synchronized internally. If the setup time shown is not met, HOLD will be recognized on the next clock cycle.
MAX
7
UNIT
ns
Table 5−14. HOLD and HOLDA Switching Characteristics‡
VC5510-200
NO.
H2
H3
H4
H5
PARAMETER
MIN
tR(COH-BHZ)
Response time, CLKOUT high to EMIF Bus high impedance (HZ)¶
tR(COH-HOLDAL) Response time, CLKOUT high to HOLDA low
4P
MAX
§
5P−1
tR(COH-HOLDAH) Response time, CLKOUT high to HOLDA high
tR(COH-BLZ)
Response time, CLKOUT high to EMIF Bus low impedance (LZ) (active)¶
UNIT
ns
ns
4P−1
4P+5
ns
4P−1
4P+5
ns
‡ P = 1/CPU clock frequency in ns. For example, when running parts at 200 MHz, use P = 5 ns.
§ All pending EMIF transactions are allowed to complete before HOLDA is asserted. If no bus transactions are occurring, then the minimum delay
time can be achieved. Also, bus hold can be indefinitely delayed by setting NOHOLD = 1.
¶ EMIF Bus consists of CE[3:0], BE[3:0], D[31:0], A[21:0], ARE, AOE, AWE, SSADS, SSOE, SSWE, CLKMEM, SDA10, SDRAS, SDCAS, and
SDWE.
CLKOUT
H1
H1
HOLD
H3
H4
HOLDA
H2
H5
EMIF BUS†
† EMIF Bus consists of CE[3:0], BE[3:0], D[31:0], A[21:0], ARE, AOE, AWE, SSADS, SSOE, SSWE, SDA10, SDRAS, SDCAS, SDWE, and
CLKMEM.
Figure 5−14. HOLD/HOLDA Timing
August 2003 − Revised November 2003
SGUS045A
53
Electrical Specifications
5.9
Reset Timings
Table 5−15 and Table 5−16 assume testing over recommended operating conditions (see Figure 5−15).
Table 5−15. Reset Timing Requirements†
VC5510-200
NO.
R1
MIN
tw(RSL)
Pulse width, reset low
MAX
2P + 5
UNIT
ns
† P = 1/CPU clock frequency in ns. For example, when running parts at 200 MHz, use P = 5 ns.
Table 5−16. Reset Switching Characteristics†
VC5510-200
NO.
R3
R4
R5
R6
R7
R8
R9
R10
PARAMETER
MIN
td(RSL-EMIFHZ)
td(RSL-EMIFV)
Delay time, reset low to EMIF group high impedance‡
Delay time, reset low to EMIF group valid‡
td(RSL-LOWIV)
td(RSL-LOWV)
Delay time, reset low to low group invalid§
Delay time, reset low to low group valid§
td(RSL-HIGHIV)
td(RSL-HIGHV)
Delay time, reset low to high group invalid§
Delay time, reset low to high group valid§
td(RSL-ZHZ)
td(RSL-ZV)
Delay time, reset low to Z group high impedance¶
Delay time, reset low to Z group valid¶
MAX
UNIT
19
ns
38P + 19
ns
17
ns
38P + 17
ns
9
ns
38P + 9
ns
18
ns
39P + 18
ns
† P = 1/CPU clock frequency in ns. For example, when running parts at 200 MHz, use P = 5 ns.
‡ EMIF group: CE[0:3], BE[0:3], CLKMEM, ARE, AOE, AWE, SSADS, SSOE, SSWE, SDRAS, SDCAS, SDWE, and SDA10
§ High group: HINT
Low group: HOLDA
¶ Z group: A[21:0], D[31:0], CLKR[2:0], CLKX[2:0], FSR[2:0], FSX[2:0], DX[2:0], IO[7:0], XF, and TIN/TOUT[1:0]
R1
RESET
R3
R4
EMIF Group†
R5
R6
R7
R8
R9
R10
Low Group‡
High Group‡
Z Group§
† EMIF group: CE[0:3], BE[0:3], CLKMEM, ARE, AOE, AWE, SSADS, SSOE, SSWE, SDRAS, SDCAS, SDWE, and SDA10
‡ High group: HINT
Low group: HOLDA
§ Z group: A[21:0], D[31:0], CLKR[2:0], CLKX[2:0], FSR[2:0], FSX[2:0], DX[2:0], IO[7:0], XF, and TIN/TOUT[1:0]
Figure 5−15. Reset Timing
54
SGUS045A
August 2003 − Revised November 2003
Electrical Specifications
5.10 External Interrupt Timings
Table 5−17 assumes testing over recommended operating conditions (see Figure 5−16).
Table 5−17. External Interrupt Timing Requirements†
VC5510-200
NO.
I1
MIN
tw(INTL)A
Pulse width, interrupt low, CPU active
I2
tw(INTH)A
Pulse width, interrupt high, CPU active
† P = 1/CPU clock frequency in ns. For example, when running parts at 200 MHz, use P = 5 ns.
MAX
UNIT
3P
ns
2P
ns
I1
INTn, NMI
I2
Figure 5−16. External Interrupt Timing
5.11 XF Timings
Table 5−18 assumes testing over recommended operating conditions (see Figure 5−17).
Table 5−18. XF Switching Characteristics
VC5510-200
NO.
X1
PARAMETER
td(XF)
MIN
MAX
Delay time, CLKOUT high to XF high
0
4
Delay time, CLKOUT high to XF low
0
4
UNIT
ns
CLKOUT
X1
XF
Figure 5−17. XF Timing
August 2003 − Revised November 2003
SGUS045A
55
Electrical Specifications
5.12 General-Purpose Input/Output (IOx) Timings
Table 5−19 and Table 5−20 assume testing over recommended operating conditions (see Figure 5−18).
Table 5−19. General-Purpose Input/Output (GPIO) Pins Configured as Inputs Timing Requirements
VC5510-200
NO.
G2
G3
MIN
tsu(GPIO-COH)
th(COH-GPIO)
MAX
UNIT
Setup time, IOx input valid before CLKOUT high
8
ns
Hold time, IOx input valid after CLKOUT high
0
ns
Table 5−20. General-Purpose Input/Output (GPIO) Pins Configured as Inputs Switching Characteristics
VC5510-200
NO.
G1
PARAMETER
td(COH-GPIO)
Delay time, CLKOUT high to IOx output change
MIN
MAX
0
6
UNIT
ns
CLKOUT
G2
G3
IOx Input Mode
G1
IOx Output Mode
Figure 5−18. General-Purpose Input/Output (IOx) Signal Timings
56
SGUS045A
August 2003 − Revised November 2003
Electrical Specifications
5.13 TIN/TOUT Timings
Table 5−21 and Table 5−22 assumes testing over recommended operating conditions (see Figure 5−19 and
Figure 5−20).
Table 5−21. TIN/TOUT Pins Configured as Inputs Timing Requirements†
VC5510-200
NO.
T4
T5
MIN
tw(TIN/TOUTL)
tw(TIN/TOUTH)
MAX
UNIT
Pulse width, TIN/TOUT low
2P + 1
ns
Pulse width, TIN/TOUT high
2P + 1
ns
† P = 1/CPU clock frequency in ns. For example, when running parts at 200 MHz, use P = 5 ns.
Table 5−22. TIN/TOUT Pins Configured as Outputs Switching Characteristics†‡
VC5510-200
NO.
T1
T2
PARAMETER
td(COH-TIN/TOUTH)
td(COH-TIN/TOUTL)
UNIT
MIN
MAX
Delay time, CLKOUT high to TIN/TOUT high
0
2
ns
Delay time, CLKOUT high to TIN/TOUT low
0
2
ns
T3
tw(TIN/TOUT)
Pulse duration, TIN/TOUT (output)
P
† P = 1/CPU clock frequency in ns. For example, when running parts at 200 MHz, use P = 5 ns.
‡ For proper operation of the TIN/TOUT pin configured as an output, the timer period must be configured for at least 4 cycles.
T5
ns
T4
TIN/TOUT
as Input
Figure 5−19. TIN/TOUT Timing When Configured as Inputs
CLKOUT
T1
T2
T3
TIN/TOUT
as Output
Figure 5−20. TIN/TOUT Timing When Configured as Outputs
August 2003 − Revised November 2003
SGUS045A
57
Electrical Specifications
5.14 Multichannel Buffered Serial Port (McBSP) Timings
5.14.1
McBSP Transmit and Receive Timings
Table 5−23 and Table 5−24 assume testing over recommended operating conditions (see Figure 5−21 and
Figure 5−22).
Table 5−23. McBSP Timing Requirements†‡
VC5510-200
NO.
M11
M12
M13
M14
MIN
tc(CKRX)
tw(CKRX)
Cycle time, CLKR/X
CLKR/X ext
2P
Pulse duration, CLKR/X high or CLKR/X low
CLKR/X ext
P−1
tr(CKRX)
tf(CKRX)
Rise time, CLKR/X
CLKR/X ext
Fall time, CLKR/X
CLKR/X ext
M15
tsu(FRH-CKRL)
Setup time, external FSR high before CLKR low
M16
th(CKRL-FRH)
Hold time, external FSR high after CLKR low
M17
tsu(DRV-CKRL)
Setup time, DR valid before CLKR low
M18
th(CKRL-DRV)
Hold time, DR valid after CLKR low
M19
tsu(FXH-CKXL)
Setup time, external FSX high before CLKX low
M20
th(CKXL-FXH)
Hold time, external FSX high after CLKX low
CLKR int
5
CLKR ext
1
CLKR int
0
CLKR ext
2
CLKR int
4
CLKR ext
1
CLKR int
0
CLKR ext
2
CLKX int
5
CLKX ext
1
CLKX int
0
CLKX ext
2
MAX
UNIT
ns
ns
5
ns
5
ns
ns
ns
ns
ns
ns
ns
† Polarity bits CLKRP = CLKXP = FSRP = FSXP = 0. If the polarity of any of the signals is inverted, then the timing references of that signal are
also inverted.
‡ P = 1/CPU clock frequency in ns. For example, when running parts at 200 MHz, use P = 5 ns.
58
SGUS045A
August 2003 − Revised November 2003
Electrical Specifications
Table 5−24. McBSP Switching Characteristics†‡
VC5510-200
NO.
M1
PARAMETER
MIN
Cycle time, CLKR/X
M2
tc(CKRX)
tw(CKRXH)
CLKR/X int
Pulse duration, CLKR/X high
CLKR/X int
2P
D−1§
M3
tw(CKRXL)
Pulse duration, CLKR/X low
CLKR/X int
CLKR int
M4
td(CKRH-FRV)
Delay time, CLKR high to internal FSR valid
MAX
ns
ns
C−1§
D+1§
C+1§
−2
2
ns
ns
CLKR ext
3
7
CLKX int
−2
2
CLKX ext
3
7
M5
td(CKXH-FXV)
Delay time, CLKX high to internal FSX valid
0
2
tdis(CKXH-DXHZ)
Disable time, CLKX high to DX high impedance
following last data bit
CLKX int
M6
CLKX ext
1
11
Delay time, CLKX high to DX valid.
This applies to all bits except the first bit transmitted.
CLKX int
6
CLKX ext
9
CLKX int
6
CLKX ext
9
CLKX int
2P+6
CLKX ext
2P+9
M7
td(CKXH-DXV)
Delay time, CLKX high to DX valid¶
DXENA = 0
Only applies to first bit transmitted when in Data DXENA = 1
Delay 1 or 2 (XDATDLY=01b or 10b) modes
CLKX int
Enable time, CLKX high to DX driven¶
M8
DXENA = 0
ten(CKXH-DX)
Only applies to first bit transmitted when in Data DXENA = 1
Delay 1 or 2 (XDATDLY=01b or 10b) modes
Delay time, FSX high to DX valid¶
M9
DXENA = 0
td(FXH-DXV)
Only applies to first bit transmitted when in Data DXENA = 1
Delay 0 (XDATDLY=00b) mode.
Enable time, FSX high to DX driven¶
M10
DXENA = 0
UNIT
ns
ns
ns
ns
0
CLKX ext
6
CLKX int
P
CLKX ext
P+6
ns
FSX int
5
FSX ext
9
FSX int
2P+5
FSX ext
2P+9
FSX int
0
FSX ext
6
ns
ten(FXH-DX)
ns
FSX int
P
Only applies to first bit transmitted when in Data DXENA = 1
FSX ext
P+6
Delay 0 (XDATDLY=00b) mode
† Polarity bits CLKRP = CLKXP = FSRP = FSXP = 0. If the polarity of any of the signals is inverted, then the timing references of that signal are
also inverted.
‡ P = 1/CPU clock frequency in ns. For example, when running parts at 200 MHz, use P = 5 ns.
§ T=CLKRX period = (1 + CLKGDV) * P
C=CLKRX low pulse width = T/2 when CLKGDV is odd or zero and = (CLKGDV/2) * P when CLKGDV is even
D=CLKRX high pulse width = T/2 when CLKGDV is odd or zero and = (CLKGDV/2 + 1) * P when CLKGDV is even
¶ See the TMS320C55x DSP Peripherals Reference Guide (literature number SPRU317) for a description of the DX enable (DXENA) and data
delay features of the McBSP.
August 2003 − Revised November 2003
SGUS045A
59
Electrical Specifications
M1, M11
M2, M12
M13
M3, M12
CLKR
M4
M4
M14
FSR (int)
M15
M16
FSR (ext)
M18
M17
DR
(RDATDLY=00b)
Bit (n−1)
(n−2)
(n−3)
M17
(n−4)
M18
DR
(RDATDLY=01b)
Bit (n−1)
(n−2)
M17
(n−3)
M18
DR
(RDATDLY=10b)
Bit (n−1)
(n−2)
Figure 5−21. McBSP Receive Timings
M1, M11
M2, M12
M13
M3, M12
M14
CLKX
M5
M5
FSX (int)
M19
M20
FSX (ext)
M9
M7
M10
DX
(XDATDLY=00b)
Bit 0
Bit (n−1)
(n−2)
(n−3)
(n−4)
(n−2)
(n−3)
M7
M8
DX
(XDATDLY=01b)
Bit 0
Bit (n−1)
M7
M6
DX
(XDATDLY=10b)
M8
Bit 0
Bit (n−1)
(n−2)
Figure 5−22. McBSP Transmit Timings
60
SGUS045A
August 2003 − Revised November 2003
Electrical Specifications
5.14.2
McBSP General-Purpose I/O Timing
Table 5−25 and Table 5−26 assume testing over recommended operating conditions (see Figure 5−23).
Table 5−25. McBSP General-Purpose I/O Timing Requirements
VC5510-200
NO.
M22
M23
MIN
tsu(MGPIO-COH)
th(COH-MGPIO)
Setup time, MGPIOx input mode before CLKOUT high†
Hold time, MGPIOx input mode after CLKOUT high†
MAX
UNIT
7
ns
0
ns
† MGPIOx refers to CLKRx, FSRx, DRx, CLKXx, or FSXx when configured as a general-purpose input.
Table 5−26. McBSP General-Purpose I/O Switching Characteristics
VC5510-200
NO.
PARAMETER
M21 td(COH-MGPIO)
Delay time, CLKOUT high to MGPIOx output mode‡
‡ MGPIOx refers to CLKRx, FSRx, CLKXx, FSXx, or DXx when configured as a general-purpose output.
M22
MIN
MAX
0
3
UNIT
ns
M21
CLKOUT
M23
MGPIOx Input
Mode†
MGPIOx Output
Mode‡
† MGPIOx refers to CLKRx, FSRx, DRx, CLKXx, or FSXx when configured as a general-purpose input.
‡ MGPIOx refers to CLKRx, FSRx, CLKXx, FSXx, or DXx when configured as a general-purpose output.
Figure 5−23. McBSP General-Purpose I/O Timings
August 2003 − Revised November 2003
SGUS045A
61
Electrical Specifications
5.14.3
McBSP as SPI Master or Slave Timing
Table 5−27 to Table 5−34 assume testing over recommended operating conditions (see Figure 5−24 through
Figure 5−27).
Table 5−27. McBSP as SPI Master or Slave Timing Requirements (CLKSTP = 10b, CLKXP = 0)†‡
VC5510-200
MASTER
NO.
MIN
M30
SLAVE
MAX
UNIT
MIN
MAX
Setup time, DR valid before CLKX low
4
3 − 6P
ns
M31
tsu(DRV-CKXL)
th(CKXL-DRV)
Hold time, DR valid after CLKX low
1
1 + 6P
ns
M32
tsu(BFXL-CKXH)
Setup time, FSX low before CLKX high
10
ns
16P
ns
M33 tc(CKX)
Cycle time, CLKX
2P
† For all SPI slave modes, CLKG is programmed as 1/2 of the CPU clock by setting CLKSM = CLKGDV = 1.
‡ P = 1/CPU clock frequency in ns. For example, when running parts at 200 MHz, use P = 5 ns.
Table 5−28. McBSP as SPI Master or Slave Switching Characteristics (CLKSTP = 10b, CLKXP = 0)†‡
VC5510-200
NO.
MASTER§
PARAMETER
M25
td(CKXL-FXL)
td(FXL-CKXH)
Delay time, FSX low to CLKX low¶
Delay time, FSX low to CLKX high#
M26
td(CKXH-DXV)
Delay time, CLKX high to DX valid
M27
tdis(CKXL-DXHZ)
Disable time, DX high impedance following
last data bit from CLKX low
M28
tdis(FXH-DXHZ)
Disable time, DX high impedance following
last data bit from FSX high
M24
SLAVE
UNIT
MIN
MAX
T−1
T+3
MIN
MAX
ns
C−2
C+2
ns
−2
4
C−2
C
3P + 2
5P+ 8
ns
ns
3P + 8
3P + 20
ns
M29 td(FXL-DXV)
Delay time, FSX low to DX valid
3P − 3
3P + 20
ns
† For all SPI slave modes, CLKG is programmed as 1/2 of the CPU clock by setting CLKSM = CLKGDV = 1.
‡ P = 1/CPU clock frequency in ns. For example, when running parts at 200 MHz, use P = 5 ns.
§ T = CLKX period = (1 + CLKGDV) * P
C = CLKX low pulse width = T/2 when CLKGDV is odd or zero and = (CLKGDV/2) * P when CLKGDV is even
¶ FSRP = FSXP = 1. As a SPI master, FSX is inverted to provide active-low slave-enable output. As a slave, the active-low signal input on FSX
and FSR is inverted before being used internally.
CLKXM = FSXM = 1, CLKRM = FSRM = 0 for master McBSP
CLKXM = CLKRM = FSXM = FSRM = 0 for slave McBSP
# FSX should be low before the rising edge of clock to enable slave devices and then begin a SPI transfer at the rising edge of the master clock
(CLKX).
LSB
M33
MSB
M32
CLKX
M24
M25
FSX
M28
M29
M26
M27
DX
Bit 0
Bit(n-1)
M30
DR
Bit 0
(n-2)
(n-3)
(n-4)
M31
Bit(n-1)
(n-2)
(n-3)
(n-4)
Figure 5−24. McBSP Timing as SPI Master or Slave: CLKSTP = 10b, CLKXP = 0
62
SGUS045A
August 2003 − Revised November 2003
Electrical Specifications
Table 5−29. McBSP as SPI Master or Slave Timing Requirements (CLKSTP = 11b, CLKXP = 0)†‡
VC5510-200
MASTER
NO.
MIN
M39
SLAVE
MAX
UNIT
MIN
MAX
Setup time, DR valid before CLKX high
4
3 − 6P
ns
M40
tsu(DRV-CKXH)
th(CKXH-DRV)
Hold time, DR valid after CLKX high
1
1 +6P
ns
M41
tsu(FXL-CKXH)
Setup time, FSX low before CLKX high
10
ns
16P
ns
M42 tc(CKX)
Cycle time, CLKX
2P
† For all SPI slave modes, CLKG is programmed as 1/2 of the CPU clock by setting CLKSM = CLKGDV = 1.
‡ P = 1/CPU clock frequency in ns. For example, when running parts at 200 MHz, use P = 5 ns.
Table 5−30. McBSP as SPI Master or Slave Switching Characteristics (CLKSTP = 11b, CLKXP = 0)†‡
VC5510-200
NO.
MASTER§
PARAMETER
M35
td(CKXL-FXL)
td(FXL-CKXH)
Delay time, FSX low to CLKX low¶
Delay time, FSX low to CLKX high#
M36
td(CKXL-DXV)
Delay time, CLKX low to DX valid
tdis(CKXL-DXHZ)
Disable time, DX high impedance following last data bit from
CLKX low
M34
M37
SLAVE
MIN
UNIT
MIN
MAX
C−1
C+3
MAX
T−2
T+2
−2
4
3P + 2
5P + 8
ns
−2
0
3P + 8
3P + 21
ns
ns
ns
M38 td(FXL-DXV)
Delay time, FSX low to DX valid
D − 2 D +10
3P − 3
3P + 21
ns
† For all SPI slave modes, CLKG is programmed as 1/2 of the CPU clock by setting CLKSM = CLKGDV = 1.
‡ P = 1/CPU clock frequency in ns. For example, when running parts at 200 MHz, use P = 5 ns.
§ T = CLKX period = (1 + CLKGDV) * P
C = CLKX low pulse width = T/2 when CLKGDV is odd or zero and = (CLKGDV/2) * P when CLKGDV is even
D = CLKX high pulse width = T/2 when CLKGDV is odd or zero and = (CLKGDV/2 + 1) * P when CLKGDV is even
¶ FSRP = FSXP = 1. As a SPI master, FSX is inverted to provide active-low slave-enable output. As a slave, the active-low signal input on FSX
and FSR is inverted before being used internally.
CLKXM = FSXM = 1, CLKRM = FSRM = 0 for master McBSP
CLKXM = CLKRM = FSXM = FSRM = 0 for slave McBSP
# FSX should be low before the rising edge of clock to enable slave devices and then begin a SPI transfer at the rising edge of the master clock
(CLKX).
LSB
M42
MSB
M41
CLKX
M34
M35
FSX
M37
DX
M36
M38
Bit 0
Bit(n-1)
M39
DR
Bit 0
(n-2)
(n-3)
(n-4)
M40
Bit(n-1)
(n-2)
(n-3)
(n-4)
Figure 5−25. McBSP Timing as SPI Master or Slave: CLKSTP = 11b, CLKXP = 0
August 2003 − Revised November 2003
SGUS045A
63
Electrical Specifications
Table 5−31. McBSP as SPI Master or Slave Timing Requirements (CLKSTP = 10b, CLKXP = 1)†‡
VC5510-200
MASTER
NO.
MIN
M49
SLAVE
MAX
MIN
UNIT
MAX
Setup time, DR valid before CLKX high
4
3 − 6P
ns
M50
tsu(DRV-CKXH)
th(CKXH-DRV)
Hold time, DR valid after CLKX high
1
1 + 6P
ns
M51
tsu(FXL-CKXL)
Setup time, FSX low before CLKX low
10
ns
16P
ns
M52 tc(CKX)
Cycle time, CLKX
2P
† For all SPI slave modes, CLKG is programmed as 1/2 of the CPU clock by setting CLKSM = CLKGDV = 1.
‡ P = 1/CPU clock frequency in ns. For example, when running parts at 200 MHz, use P = 5 ns.
Table 5−32. McBSP as SPI Master or Slave Switching Characteristics (CLKSTP = 10b, CLKXP = 1)†‡
VC5510-200
NO.
MASTER§
PARAMETER
M44
td(CKXH-FXL)
td(FXL-CKXL)
Delay time, FSX low to CLKX high¶
Delay time, FSX low to CLKX low#
M45
td(CKXL-DXV)
Delay time, CLKX low to DX valid
M46
tdis(CKXH-DXHZ)
Disable time, DX high impedance following last data bit from
CLKX high
M47
tdis(FXH-DXHZ)
Disable time, DX high impedance following last data bit from
FSX high
M43
SLAVE
MIN
MAX
T−1
T+3
D−2
D+2
−2
4
D−2
D
MIN
UNIT
MAX
ns
ns
3P + 2
5P + 8
ns
ns
3P + 8
3P + 20
ns
M48 td(FXL-DXV)
Delay time, FSX low to DX valid
3P − 3
3P + 20
ns
† For all SPI slave modes, CLKG is programmed as 1/2 of the CPU clock by setting CLKSM = CLKGDV = 1.
‡ P = 1/CPU clock frequency in ns. For example, when running parts at 200 MHz, use P = 5 ns.
§ T = CLKX period = (1 + CLKGDV) * P
D = CLKX high pulse width = T/2 when CLKGDV is odd or zero and = (CLKGDV/2 + 1) * P when CLKGDV is even
¶ FSRP = FSXP = 1. As a SPI master, FSX is inverted to provide active-low slave-enable output. As a slave, the active-low signal input on FSX
and FSR is inverted before being used internally.
CLKXM = FSXM = 1, CLKRM = FSRM = 0 for master McBSP
CLKXM = CLKRM = FSXM = FSRM = 0 for slave McBSP
# FSX should be low before the rising edge of clock to enable slave devices and then begin a SPI transfer at the rising edge of the master clock
(CLKX).
M52
MSB
M51
LSB
CLKX
M43
M44
FSX
M47
M48
M45
M46
DX
Bit 0
Bit(n-1)
M49
DR
Bit 0
(n-2)
(n-3)
(n-4)
M50
Bit(n-1)
(n-2)
(n-3)
(n-4)
Figure 5−26. McBSP Timing as SPI Master or Slave: CLKSTP = 10b, CLKXP = 1
64
SGUS045A
August 2003 − Revised November 2003
Electrical Specifications
Table 5−33. McBSP as SPI Master or Slave Timing Requirements (CLKSTP = 11b, CLKXP = 1)†‡
VC5510-200
MASTER
NO.
MIN
M58
SLAVE
MAX
MIN
UNIT
MAX
Setup time, DR valid before CLKX low
4
3 − 6P
ns
M59
tsu(DRV-CKXL)
th(CKXL-DRV)
Hold time, DR valid after CLKX low
1
1 + 6P
ns
M60
tsu(FXL-CKXL)
Setup time, FSX low before CLKX low
10
ns
16P
ns
M61 tc(CKX)
Cycle time, CLKX
2P
† For all SPI slave modes, CLKG is programmed as 1/2 of the CPU clock by setting CLKSM = CLKGDV = 1.
‡ P = 1/CPU clock frequency in ns. For example, when running parts at 200 MHz, use P = 5 ns.
Table 5−34. McBSP as SPI Master or Slave Switching Characteristics (CLKSTP = 11b, CLKXP = 1)†‡
VC5510-200
NO.
MASTER§
PARAMETER
M54
td(CKXH-FXL)
td(FXL-CKXL)
Delay time, FSX low to CLKX high¶
Delay time, FSX low to CLKX low#
M55
td(CKXH-DXV)
Delay time, CLKX high to DX valid
tdis(CKXH-DXHZ)
Disable time, DX high impedance following last data bit from
CLKX high
M53
M56
SLAVE
MIN
UNIT
MIN
MAX
D−1
D+3
MAX
T−2
T+2
−2
4
3P + 2
5P + 8
ns
−2
0
3P + 8
3P + 21
ns
ns
ns
M57 td(FXL-DXV)
Delay time, FSX low to DX valid
C − 2 C +10
3P − 3
3P + 21
ns
† For all SPI slave modes, CLKG is programmed as 1/2 of the CPU clock by setting CLKSM = CLKGDV = 1.
‡ P = 1/CPU clock frequency in ns. For example, when running parts at 200 MHz, use P = 5 ns.
§ T = CLKX period = (1 + CLKGDV) * P
C = CLKX low pulse width = T/2 when CLKGDV is odd or zero and = (CLKGDV/2) * P when CLKGDV is even
D = CLKX high pulse width = T/2 when CLKGDV is odd or zero and = (CLKGDV/2 + 1) * P when CLKGDV is even
¶ FSRP = FSXP = 1. As a SPI master, FSX is inverted to provide active-low slave-enable output. As a slave, the active-low signal input on FSX
and FSR is inverted before being used internally.
CLKXM = FSXM = 1, CLKRM = FSRM = 0 for master McBSP
CLKXM = CLKRM = FSXM = FSRM = 0 for slave McBSP
# FSX should be low before the rising edge of clock to enable slave devices and then begin a SPI transfer at the rising edge of the master clock
(CLKX).
M60
LSB
M61
MSB
CLKX
M53
M54
FSX
M56
DX
M55
M57
Bit 0
Bit(n-1)
M58
DR
Bit 0
(n-2)
(n-3)
(n-4)
M59
Bit(n-1)
(n-2)
(n-3)
(n-4)
Figure 5−27. McBSP Timing as SPI Master or Slave: CLKSTP = 11b, CLKXP = 1
August 2003 − Revised November 2003
SGUS045A
65
Electrical Specifications
5.15 Enhanced Host-Port Interface (EHPI) Timing
Table 5−35 and Table 5−36 assume testing over recommended operating conditions (see Figure 5−28
through Figure 5−32).
Table 5−35. EHPI Timing Requirements
VC5510-200
NO.
E11
MIN
E12
tsu(HASL-HDSL)
th(HDSL-HASL)
E13
MAX
UNIT
Setup time, HAS low before HDS low
4
ns
Hold time, HAS low after HDS low
3
ns
tsu(HCNTLV-HDSL)
Setup time, (HR/W, HA[19:0],
HCNTL[1:0]) valid before HDS low
4
ns
E14
th(HDSL-HCNTLIV)
Hold time, (HR/W, HA[19:0], HCNTL[1:0]) invalid after HDS low
E15
tw(HDSL)
tw(HDSH)
Pulse duration, HDS low
tsu(HDV-HDSH)
th(HDSH-HDIV)
tsu(HCNTLV-HASL)
th(HASL-HCNTLIV)
E16
E17
E18
E19
E20
4
ns
4P†
4P†
ns
Setup time, HD bus write data valid before HDS high
5
ns
Hold time, HD bus write data invalid after HDS high
3
ns
Setup time, (HR/W, HCNTL[1:0]) valid before HAS low
5
ns
Hold time, (HR/W, HCNTL[1:0]) valid after HAS low
3
ns
Pulse duration, HDS high
ns
† P = 1/CPU clock frequency in ns. For example, when running parts at 200 MHz, use P = 5 ns.
Table 5−36. EHPI Switching Characteristics
VC5510-200
NO.
PARAMETER
E1
td(HDSL-HDD)M
Delay time, HDS low to HD bus read data driven
(memory access)
E2
td(HDSL-HDV1)M
Delay time, HDS low to HD bus read data valid
(memory access)
E4
td(HDSL-HDD)R
Delay time, HDS low to HD bus read data driven
(register access)
E5
td(HDSL-HDV)R
Delay time, HDS low to HD bus read data valid
(register access)
E6
tdis(HDSH-HDIV)
td(HDSL-HRDYL)
Disable time, HDS high to HD bus read data invalid
td(HDV-HRDYH)
td(HDSH-HRDYL)
Delay time, HD bus valid to HRDY high (during reads)
E7
E8
E9
MIN
MAX
6
16
14P+10†‡
6
6
Delay time, HDS low to HRDY low (during reads)
ns
ns
16
ns
16
ns
16
P+10†
ns
2
Delay time, HDS high to HRDY low (during writes)
UNIT
ns
ns
16
ns
14P+10†
E10 td(HDSH-HRDYH)
Delay time, HDS high to HRDY high (during writes)
ns
† P = 1/CPU clock frequency in ns. For example, when running parts at 200 MHz, use P = 5 ns.
‡ EHPI latency is dependent on the number of DMA channels active, their priorities and their source/destination ports. The latency shown assumes
no competing CPU or DMA activity to the memory resource being accessed by the EHPI.
66
SGUS045A
August 2003 − Revised November 2003
Electrical Specifications
Read
Write
HCS
E16
E15
E15
HDS
E14
E13
E14
E13
HR/W
HCNTL[1:0]
Valid
Valid
HA[19:0]
Valid
Valid
E2
E1
E6
HD[15:0]
(read)
Read Data
E17
HD[15:0]
(write)
E18
Write Data
E10
E7
E8
E9
HRDY
NOTES: A. As of revision 2.1, the byte-enable function on the EHPI (as controlled by pins HBE0 and HBE1) is no longer supported. These pins
must always be driven low either by an external device, by external pulldown resistors or by using the on-chip pulldown circuitry
controlled by the HPE bit in the System Register (SYSR).
B. The falling edge of HCS must occur concurrent with or before the falling edge of HDS. The rising edge of HCS must occur concurrent
with or after the rising edge of HDS. If HDS1 and/or HDS2 are tied low and HCS is used as a strobe, the timing requirements shown
for HDS apply to HCS . Operation with HCS as a strobe is not recommended because HCS gates output of HRDY (when HCS is
high HRDY is not driven).
Figure 5−28. EHPI Nonmultiplexed Read/Write Timings
August 2003 − Revised November 2003
SGUS045A
67
Electrical Specifications
Read
Write
HCS
E11
E12
E12
E11
HAS
E15
E16
E15
HDS
E20
E19
E20
E19
E13
E13
E14
E14
HR/W
HCNTL[1:0]
Valid (11)
Valid (11)
E5
E6
E4
HD[15:0]
(read)
Read Data
E17
HD[15:0]
(write)
E18
Write Data
E10
E7
E8
E9
HRDY
NOTES: A. As of revision 2.1, the byte-enable function on the EHPI (as controlled by pins HBE0 and HBE1) is no longer supported. These pins
must always be driven low either by an external device, by external pulldown resistors or by using the on-chip pulldown circuitry
controlled by the HPE bit in the System Register (SYSR).
B. The falling edge of HCS must occur concurrent with or before the falling edge of HDS. The rising edge of HCS must occur concurrent
with or after the rising edge of HDS. If HDS1 and/or HDS2 are tied low and HCS is used as a strobe, the timing requirements shown
for HDS apply to HCS . Operation with HCS as a strobe is not recommended because HCS gates output of HRDY (when HCS is
high HRDY is not driven).
Figure 5−29. EHPI Multiplexed Memory (HPID) Access Read/Write Timings Without Autoincrement
68
SGUS045A
August 2003 − Revised November 2003
Electrical Specifications
HCS
E11
E12
HAS
E15
E16
HDS
E20
E19
E13
E14
HR/W
HCNTL[1:0]
Valid (01)
Valid (01)
E2
E2
E6
E1
HD[15:0]
(read)
E6
E1
Read Data
Read Data
E7
E7
E8
E8
HRDY
HPIA contents
n
n+1
n+2
NOTES: A. As of revision 2.1, the byte-enable function on the EHPI (as controlled by pins HBE0 and HBE1) is no longer supported. These pins
must always be driven low either by an external device, by external pulldown resistors or by using the on-chip pulldown circuitry
controlled by the HPE bit in the System Register (SYSR).
B. During autoincrement mode, although the EHPI internally increments the memory address, reads of the HPIA register by the host
will always indicate the base address.
C. The falling edge of HCS must occur concurrent with or before the falling edge of HDS. The rising edge of HCS must occur concurrent
with or after the rising edge of HDS. If HDS1 and/or HDS2 are tied low and HCS is used as a strobe, the timing requirements shown
for HDS apply to HCS . Operation with HCS as a strobe is not recommended because HCS gates output of HRDY (when HCS is
high HRDY is not driven).
Figure 5−30. EHPI Multiplexed Memory (HPID) Access Read Timings With Autoincrement
August 2003 − Revised November 2003
SGUS045A
69
Electrical Specifications
HCS
E12
E11
HAS
E15
E16
HDS
E20
E19
E13
E14
HR/W
HCNTL[1:0]
Valid (01)
Valid (01)
E17
HD[15:0]
(write)
E18
Write Data
Write Data
E10
E10
E9
E9
HRDY
HPIA contents
n
n+1
NOTES: A. As of revision 2.1, the byte-enable function on the EHPI (as controlled by pins HBE0 and HBE1) is no longer supported. These pins
must always be driven low either by an external device, by external pulldown resistors or by using the on-chip pulldown circuitry
controlled by the HPE bit in the System Register (SYSR).
B. During autoincrement mode, although the EHPI internally increments the memory address, reads of the HPIA register by the host
will always indicate the base address.
C. The falling edge of HCS must occur concurrent with or before the falling edge of HDS. The rising edge of HCS must occur concurrent
with or after the rising edge of HDS. If HDS1 and/or HDS2 are tied low and HCS is used as a strobe, the timing requirements shown
for HDS apply to HCS . Operation with HCS as a strobe is not recommended because HCS gates output of HRDY (when HCS is
high HRDY is not driven).
Figure 5−31. EHPI Multiplexed Memory (HPID) Access Write Timings With Autoincrement
70
SGUS045A
August 2003 − Revised November 2003
Electrical Specifications
Read
Write
HCS
E11
E12
E11
E12
HAS
E15
E16
E15
HDS
E20
E19
E19
E13
E20
E13
E14
E14
HR/W
HCNTL[1:0]
Valid (10 or 00)
Valid (10 or 00)
E5
E6
E4
HD[15:0]
(read)
Read Data
E17
HD[15:0]
(write)
E18
Write Data
HRDY
NOTES: A. As of revision 2.1, the byte-enable function on the EHPI (as controlled by pins HBE0 and HBE1) is no longer supported. These pins
must always be driven low either by an external device, by external pulldown resistors or by using the on-chip pulldown circuitry
controlled by the HPE bit in the System Register (SYSR).
B. During auto-increment mode, although the EHPI internally increments the memory address, reads of the HPIA register by the host
will always indicate the base address.
C. The falling edge of HCS must occur concurrent with or before the falling edge of HDS. The rising edge of HCS must occur concurrent
with or after the rising edge of HDS. If HDS1 and/or HDS2 are tied low and HCS is used as a strobe, the timing requirements shown
for HDS apply to HCS . Operation with HCS as a strobe is not recommended because HCS gates output of HRDY (when HCS is
high HRDY is not driven).
Figure 5−32. EHPI Multiplexed Register Access Read/Write Timings
August 2003 − Revised November 2003
SGUS045A
71
Mechanical Data
6
Mechanical Data
6.1
Ball Grid Array (GGW) Package Mechanical Data
GGW (S-PBGA-N240)
PLASTIC BALL GRID ARRAY
15,10
SQ
14,90
12,80 TYP
0,80
U
T
R
P
N
M
L
K
J
H
G
F
E
D
C
B
A
0,80
1
A1 Corner
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
Bottom View
0,95
0,85
1,40 MAX
Seating Plane
0,55
0,45
0,08
0,45
0,35
0,12
4145255−4/D 08/02
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice
C. MicroStar BGAt configuration.
Figure 6−1. 320VC5510 240-Ball MicroStar BGA Plastic Ball Grid Array Package
MicroStar BGA is a trademark of Texas Instruments.
72
SGUS045A
August 2003 − Revised November 2003
PACKAGE OPTION ADDENDUM
www.ti.com
24-Sep-2007
PACKAGING INFORMATION
Orderable Device
Status (1)
SM32VC5510AGGWA2EP
ACTIVE
BGA MI
CROSTA
R
GGW
240
126
TBD
SNPB
Level-3-220C-168 HR
V62/04605-01XA
ACTIVE
BGA MI
CROSTA
R
GGW
240
126
TBD
SNPB
Level-3-220C-168 HR
Package
Type
Package
Drawing
Pins Package Eco Plan (2)
Qty
Lead/Ball Finish
MSL Peak Temp (3)
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
Addendum-Page 1
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