Texas Instruments | SM320LC31-EP Digital Signal Processor | Datasheet | Texas Instruments SM320LC31-EP Digital Signal Processor Datasheet

Texas Instruments SM320LC31-EP Digital Signal Processor Datasheet
SGUS039 − AUGUST 2002
D Controlled Baseline
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D On-Chip Memory-Mapped Peripherals:
− One Assembly/Test Site, One Fabrication
Site
Enhanced Diminishing Manufacturing
Sources (DMS) Support
Enhanced Product Change Notification
Qualification Pedigree†
Operating Temperature Ranges:
− Military (M) −55°C to 125°C
High-Performance Floating-Point Digital
Signal Processor (DSP):
− SM320LC31-40EP (3.3 V)
50-ns Instruction Cycle Time
220 MOPS, 40 MFLOPS, 20 MIPS
32-Bit High-Performance CPU
16- / 32-Bit Integer and 32- / 40-Bit
Floating-Point Operations
32-Bit Instruction and Data Words, 24-Bit
Addresses
Two 1K Word × 32-Bit Single-Cycle
Dual-Access On-Chip RAM Blocks
Boot-Program Loader
64-Word × 32-Bit Instruction Cache
Eight Extended-Precision Registers
Two Address Generators With Eight
Auxiliary Registers and Two Auxiliary
Register Arithmetic Units (ARAUs)
Two Low-Power Modes
D
D
D
D
D
D
D
D
D
D
D
D
D
D
− One Serial Port Supporting
8- / 16- / 24- / 32-Bit Transfers
− Two 32-Bit Timers
− One-Channel Direct Memory Access
(DMA) Coprocessor for Concurrent I/O
and CPU Operation
Fabricated Using Enhanced Performance
Implanted CMOS (EPIC) Technology by
Texas Instruments (TI )
Two- and Three-Operand Instructions
40 / 32-Bit Floating-Point / Integer Multiplier
and Arithmetic Logic Unit (ALU)
Parallel ALU and Multiplier Execution in a
Single Cycle
Block-Repeat Capability
Zero-Overhead Loops With Single-Cycle
Branches
Conditional Calls and Returns
Interlocked Instructions for
Multiprocessing Support
Bus-Control Registers Configure
Strobe-Control Wait-State Generation
Validated Ada Compiler
Integer, Floating-Point, and Logical
Operations
32-Bit Barrel Shifter
One 32-Bit Data Bus (24-Bit Address)
Packaging
− 132-Lead Plastic Quad Flatpack
(PQ Suffix)
description
The SM320LC31-EP digital signal processor (DSP) is a 32-bit, floating-point processor manufactured in 0.6-µm
triple-level-metal CMOS technology. The device is part of the SMJ320C3x generation of DSPs from Texas
Instruments.
The SM320LC31-EP internal busing and special digital-signal-processing instruction set have the speed and
flexibility to execute up to 60 MFLOPS. The SM320LC31-EP optimizes speed by implementing functions in
hardware that other processors implement through software or microcode. This hardware-intensive approach
provides performance previously unavailable on a single chip.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
† Component qualification in accordance with JEDEC and industry standards to ensure reliable operation over an extended temperature range.
This includes, but is not limited to, Highly Accelerated Stress Test (HAST) or biased 85/85, temperature cycle, autoclave or unbiased HAST,
electromigration, bond intermetallic life, and mold compound life. Such qualification testing should not be viewed as justifying use of this
component beyond specified performance and environmental limits.
EPIC is a trademark of Texas Instruments Incorporated.
All trademarks are the property of their respective owners.
Copyright  2002, Texas Instruments Incorporated
! "#$ %!&
% "! "! '! ! !( !
%% )*& % "!+ %! !!$* $%!
!+ $$ "!!&
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description (continued)
The SM320LC31-EP can perform parallel multiply and ALU operations on integer or floating-point data in a
single cycle. Each processor also possesses a general-purpose register file, a program cache, dedicated
ARAUs, internal dual-access memories, one DMA channel supporting concurrent I/O, and a short
machine-cycle time. High performance and ease of use are results of these features.
General-purpose applications are greatly enhanced by the large address space, multiprocessor interface,
internally and externally generated wait states, one external interface port, two timers, one serial port, and
multiple-interrupt structure. The SM320LC31-EP supports a wide variety of system applications from host
processor to dedicated coprocessor.
High-level-language support is easily implemented through a register-based architecture, large address space,
powerful addressing modes, flexible instruction set, and well-supported floating-point arithmetic.
For additional information when designing for cold temperature operation, please see Texas Instruments
application report 320C3x, 320C4x and 320MCM42x Power-up Sensitivity at Cold Temperature, literature
number SGUA001.
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SM320LC31-EP pinout (top view)
The SM320LC31-EP device is packaged in a132-pin plastic quad flatpack (PQ Suffix). The full part number is
SM320LC31PQM40EP.
SHZ
VSS
TCLK0
VSS
MCBL/MP
EMU2
EMU1
EMU0
EMU3
TCLK1
VDD
A22
A23
VSS
A20
A21
VDD
VDD
A19
VSS
VSS
A11
A12
A13
A14
A15
A16
A17
A18
VDD
VSS
A10
VDD
PQ PACKAGE
(TOP VIEW)
A9
VSS
A8
A7
A6
A5
VDD
A4
A3
A2
A1
A0
VSS
D31
VDD
VDD
D30
VSS
VSS
VSS
D29
D28
VDD
D27
VSS
D26
D25
D24
D23
D22
D21
VDD
D20
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V DD
D5
D4
D3
D2
D1
D0
H1
H3
V DD
D7
D6
D9
D8
VSS
VSS
VSS
D12
D11
D10
V DD
V DD
D14
V DD
D13
V SS
D19
D18
D17
D16
D15
V SS
V SS
DX0
VDD
FSX0
VSS
CLKX0
CLKR0
FSR0
VSS
DR0
INT3
INT2
VDD
VDD
INT1
VSS
VSS
INT0
IACK
XF1
VDD
XF0
RESET
R/W
STRB
RDY
VDD
HOLD
HOLDA
X1
X2/CLKIN
VSS
VSS
VSS
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Terminal Assignments (PQ Package)
PIN
PIN
PIN
PIN
NUMBER
NAME
NUMBER
NAME
NUMBER
NAME
NUMBER
29
A0
64
D10
103
INT1
30
28
A1
63
D11
106
INT2
35
27
A2
62
D12
107
INT3
36
26
A3
60
D13
127
MCBL/MP
37
25
A4
58
D14
92
R/W
42
23
A5
56
D15
95
RDY
51
22
A6
55
D16
94
RESET
57
21
A7
54
D17
118
SHZ
61
20
A8
53
D18
93
STRB
69
18
A9
52
D19
120
TCLK0
70
16
A10
50
D20
14
A11
48
D21
13
A12
47
D22
6
12
A13
46
D23
15
11
A14
45
D24
24
10
A15
44
D25
32
9
A16
43
D26
33
8
A17
41
D27
40
7
A18
39
D28
49
5
A19
38
D29
59
2
A20
34
D30
65
1
A21
31
D31
66
130
A22
108
DR0
74
71
84
85
VDDL
VDDL
DVDD‡
101
DVDD‡
DVDD‡
113
VDDL
VDDL
DVDD‡
119
129
A23
116
DX0
83
DVDD‡
CVDD‡
111
CLKR0
124
EMU0
91
CVDD‡
112
CLKX0
125
EMU1
97
80
D0
126
EMU2
104
79
D1
123
EMU3
105
VDDL
VDDL
PVDD‡
78
D2
110
FSR0
115
77
D3
114
FSX0
121
76
D4
81
HOLD
131
75
D5
82
HOLDA
132
73
D6
90
H1
3
72
D7
89
H3
4
68
D8
99
IACK
17
67
D9
100
INT0
19
† CVSS, VSSL, and IVSS are on the same plane.
‡ AVDD, DVDD, CVDD, and PVDD are on the same plane.
§ VSUBS connects to die metallization. Tie this pin to clean ground.
4
AVDD‡
AVDD‡
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PVDD‡
VDDL
VDDL
VSSL†
DVSS
CVSS†
DVSS
CVSS†
86
102
109
117
NAME
VSSL†
VSSL†
DVSS
IVSS†
DVSS
CVSS†
IVSS†
DVSS
VSSL†
VSSL†
DVSS
CVSS†
IVSS†
DVSS
VSSL†
CVSS†
IVSS†
VSUBS§
DVSS
CVSS†
128
X1
88
X2/CLKIN
87
XF0
96
XF1
98
No Connect
SGUS039 − AUGUST 2002
Terminal Functions
TERMINAL
NAME
TYPE†
DESCRIPTION
QTY
CONDITIONS
WHEN
SIGNAL IS Z TYPE‡
PRIMARY-BUS INTERFACE
D31 −D0
32
I/O/Z
32-bit data port
S
H
R
A23 −A0
24
O/Z
24-bit address port
S
H
R
R/W
1
O/Z
Read / write. R/ W is high when a read is performed and low when a write is performed
over the parallel interface.
S
H
R
STRB
1
O/Z
External-access strobe
S
H
RDY
HOLD
HOLDA
1
1
1
I
Ready. RDY indicates that the external device is prepared for a transaction
completion.
I
Hold. When HOLD is a logic low, any ongoing transaction is completed. A23 −A0,
D31 −D0, STRB, and R / W are placed in the high-impedance state and all transactions over the primary-bus interface are held until HOLD becomes a logic high or until
the NOHOLD bit of the primary-bus-control register is set.
O/Z
Hold acknowledge. HOLDA is generated in response to a logic low on HOLD. HOLDA
indicates that A23 −A0, D31 −D0, STRB, and R / W are in the high-impedance state
and that all transactions over the bus are held. HOLDA is high in response to a logic
high of HOLD or the NOHOLD bit of the primary-bus-control register is set.
S
CONTROL SIGNALS
RESET
1
I
Reset. When RESET is a logic low, the device is in the reset condition. When RESET
becomes a logic high, execution begins from the location specified by the reset vector.
INT3 −INT0
4
I
External interrupts
IACK
1
O/Z
MCBL / MP
1
I
Microcomputer boot-loader / microprocessor mode-select
Interrupt acknowledge. IACK is generated by the IACK instruction. IACK can be used
to indicate the beginning or the end of an interrupt-service routine.
SHZ
1
I
Shutdown high impedance. When active, SHZ shuts down the device and places all
pins in the high-impedance state. SHZ is used for board-level testing to ensure that
no dual-drive conditions occur. CAUTION: A low on SHZ corrupts the device memory
and register contents. Reset the device with SHZ high to restore it to a known
operating condition.
XF1, XF0
2
I/O/Z
External flags. XF1 and XF0 are used as general-purpose I / Os or to support
interlocked processor instruction.
S
S
R
SERIAL PORT 0 SIGNALS
CLKR0
1
I/O/Z
Serial port 0 receive clock. CLKR0 is the serial shift clock for the serial port 0 receiver.
S
R
S
R
CLKX0
1
I/O/Z
Serial port 0 transmit clock. CLKX0 is the serial shift clock for the serial port 0
transmitter.
DR0
1
I/O/Z
Data-receive. Serial port 0 receives serial data on DR0.
S
R
DX0
1
I/O/Z
Data-transmit output. Serial port 0 transmits serial data on DX0.
S
R
S
R
S
R
FSR0
1
I/O/Z
Frame-synchronization pulse for receive. The FSR0 pulse initiates the data-receive
process using DR0.
FSX0
1
I/O/Z
Frame-synchronization pulse for transmit. The FSX0 pulse initiates the data-transmit
process using DX0.
S
S
TIMER SIGNALS
TCLK0
1
I/O/Z
Timer clock 0. As an input, TCLK0 is used by timer 0 to count external pulses. As an
output, TCLK0 outputs pulses generated by timer 0.
TCLK1
1
I/O/Z
Timer clock 1. As an input, TCLK0 is used by timer 1 to count external pulses. As an
output, TCLK1 outputs pulses generated by timer 1.
† I = input, O = output, Z = high-impedance state
‡ S = SHZ active, H = HOLD active, R = RESET active
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Terminal Functions (Continued)
TERMINAL
NAME
TYPE†
DESCRIPTION
QTY
CONDITIONS
WHEN
SIGNAL IS Z TYPE‡
SUPPLY AND OSCILLATOR SIGNALS
H1
1
O/Z
External H1 clock. H1 has a period equal to twice CLKIN.
S
H3
1
O/Z
External H3 clock. H3 has a period equal to twice CLKIN.
S
VDD
20
I
5-V supply for C31 devices and 3.3-V supply for LC31 devices. All must be
connected to a common supply plane.§
VSS
25
I
Ground. All grounds must be connected to a common ground plane.
X1
1
O
Output from the internal-crystal oscillator. If a crystal is not used, X1 should be left
unconnected.
X2 / CLKIN
1
I
Internal-oscillator input from a crystal or a clock
RESERVED¶
EMU2 −EMU0
3
I
Reserved for emulation. Use pullup resistors to VDD
EMU3
1
O/Z
Reserved for emulation
S
† I = input, O = output, Z = high-impedance state
‡ S = SHZ active, H = HOLD active, R = RESET active
§ Recommended decoupling capacitor value is 0.1 µF.
¶ Follow the connections specified for the reserved pins. Use 18 -kΩ −22-kΩ pullup resistors for best results. All VDD supply pins must be connected
to a common supply plane, and all ground pins must be connected to a common ground plane.
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SGUS039 − AUGUST 2002
functional block diagram
RAM
Block 0
(1K × 32)
Cache
(64 × 32)
32
24
RAM
Block 1
(1K × 32)
32
24
24
32
ÉÉÉÉÉ
ÉÉÉÉÉ
ÉÉÉ
ÉÉÉÉÉ
ÉÉÉ
ÉÉÉÉÉ
Boot
Loader
24
32
PDATA Bus
PADDR Bus
MUX
DDATA Bus
MUX
RDY
HOLD
HOLDA
STRB
R/W
D31− D0
A23 − A0
DADDR1 Bus
DADDR2 Bus
DMADATA Bus
DMAADDR Bus
32
24
24
32
32
24
24
DMA Controller
Serial Port 0
Serial-Port-Control
Register
Global-Control
Register
MUX
X1
X2 / CLKIN
H1
H3
EMU(3 − 0)
DestinationAddress
Register
REG1
TransferCounter
Register
REG2
REG1
CPU1
REG2
32
32
40
40
32-Bit
Barrel
Shifter
Multiplier
40
40
32
Data-Transmit
Register
Data-Receive
Register
Timer 0
Global-Control
Register
ALU
40
Peripheral Address Bus
CPU1
CPU2
Controller
RESET
INT(3 − 0)
IACK
MCBL / MP
XF(1,0)
VDD(19 − 0)
VSS(24 − 0)
Receive/Transmit
(R / X) Timer Register
Source-Address
Register
Peripheral Data Bus
IR
PC
FSX0
DX0
CLKX0
FSR0
DR0
CLKR0
40
ExtendedPrecision
Registers
(R7−R0)
40
40
Timer-Period
Register
TCLK0
Timer-Counter
Register
Timer 1
DISP0, IR0, IR1
Global-Control
Register
ARAU0
BK
ARAU1
Timer-Period
Register
24
24
24
32
32
Auxiliary
Registers
(AR0 − AR7)
TCLK1
Timer-Counter
Register
24
Port Control
32
STRB-Control
Register
32
32
Other
Registers
(12)
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SGUS039 − AUGUST 2002
memory map†
0h
Reset, Interrupt, Trap Vector, and
Reserved Locations (64)
(External STRB Active)
0h
03Fh
040h
Reserved for Boot-Loader
Operations
FFFh
1000h
External
STRB Active
(8M Words − 64 Words)
400000h
Boot 1
Boot 2
7FFFFFh
800000h
7FFFFFh
800000h
Reserved
(32K Words)
Reserved
(32K Words)
807FFFh
808000h
External
STRB
Active
(8M Words −
4K Words)
Peripheral Bus
Memory-Mapped Registers
(6K Words Internal)
807FFFh
808000h
Peripheral Bus
Memory-Mapped Registers
(6K Words Internal)
8097FFh
809800h
8097FFh
809800h
RAM Block 0
(1K Words Internal)
RAM Block 0
(1K Words Internal)
809BFFh
809C00h
809BFFh
809C00h
RAM Block 1
(1K Words − 63 Words Internal)
RAM Block 1
(1K Words Internal)
809FFFh
80A000h
External
STRB Active
(8M Words − 40K Words)
FFFFFFh
809FC0h
809FC1h
User-Program Interrupt
and Trap Branches
(63 Words Internal)
809FFFh
80A000h
FFF000h
Boot 3
FFFFFFh
(a) Microprocessor Mode
External
STRB Active
(8M Words −
40K Words)
(b) Microcomputer/Boot-Loader Mode
† Figure 1 depicts the memory map for the SMJ320C31. See the TMS320C3x Users Guide (literature number SPRU031) for a detailed description
of this memory mapping.
Figure 1. SM320C31-EP Memory Map
8
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SGUS039 − AUGUST 2002
memory map (continued)
00h
Reset
809FC1h
INT0
01h
INT0
809FC2h
INT1
02h
INT1
809FC3h
INT2
03h
INT2
809FC4h
INT3
04h
INT3
809FC5h
05h
XINT0
XINT0
06h
RINT0
809FC6h
RINT0
07h
08h
809FC7h
Reserved
Reserved
809FC8h
09h
TINT0
809FC9h
TINT0
0Ah
TINT1
809FCAh
TINT1
0Bh
DINT
809FCBh
DINT
0Ch
1Fh
Reserved
809FCCh
809FDFh
Reserved
20h
TRAP 0
809FE0h
TRAP 0
3Bh
TRAP 27
809FFBh
TRAP 27
3Ch
3Fh
Reserved
809FFCh
Reserved
809FFFh
(a) Microprocessor Mode
(b) Microcomputer / Boot-Loader Mode
Figure 2. Reset, Interrupt, and Trap Vector/Branches Memory-Map Locations
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memory map (continued)
808000h
DMA Global Control
808004h
DMA Source Address
808006h
DMA Destination Address
808008h
DMA Transfer Counter
808020h
Timer 0 Global Control
808024h
Timer 0 Counter
808028h
Timer 0 Period Register
808030h
Timer 1 Global Control
808034h
Timer 1 Counter
808038h
Timer 1 Period Register
808040h
Serial Global Control
808042h
FSX/DX/CLKX Serial Port Control
808043h
FSR/DR/CLKR Serial Port Control
808044h
Serial R/X Timer Control
808045h
Serial R/X Timer Counter
808046h
Serial R/X Timer Period Register
808048h
Data-Transmit
80804Ch
Data-Receive
808064h
Primary-Bus Control
†Shading denotes reserved address locations
Figure 3. Peripheral Bus Memory-Mapped Registers†
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absolute maximum ratings over specified temperature range (unless otherwise noted)†
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.3 V to 5 V
Supply voltage, VDD (see Note 1)
Input voltage, VI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.3 V to 5 V
Output voltage, VO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.3 V to 5 V
Continuous power dissipation (worst case) (see Note 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 850 mW
Operating case temperature, TC
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −55°C to 125°C
Storage temperature, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 150°C
† Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. All voltage values are with respect to VSS.
2. Actual operating power is less. This value was obtained under specially produced worst-case test conditions for the TMS320C31-33
and the TMS320LC31-40, which are not sustained during normal device operation. These conditions consist of continuous parallel
writes of a checkerboard pattern to both primary and extension buses at the maximum rate possible. See normal (ICC) current
specification in the electrical characteristics table and also read Calculation of TMS320C30 Power Dissipation Application Report
(literature number SPRA020).
recommended operating conditions (see Note 3)
VDD
VSS
VIH
Supply voltage (DVDD, etc.)
MIN
NOM
3.13
3.3
Supply voltage (CVSS, etc.)
MAX
3.47
0
High-level input voltage (except RESET)
1.8
High-level input voltage (RESET)
2.2
− 0.3*
UNIT
V
V
VDD + 0.3*
VDD + 0.3*
V
V
VIL
IOH
Low-level input voltage
0.6
V
High-level output current
− 300
µA
IOL
TC
Low-level output current
2
mA
125
°C
Operating case temperature
−55
VTH
High-level input voltage for CLKIN
2.5
VDD + 0.3*
V
* This parameter is not production tested.
NOTE 3: All voltage values are with respect to VSS. All input and output voltage levels are TTL-compatible. CLKIN can be driven by a CMOS
clock.
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electrical characteristics over recommended ranges of supply voltage (unless otherwise noted)
(see Note 3)†
PARAMETER
TEST CONDITIONS
VOH
VOL
High-level output voltage
IZ
II
High-impedance current
IIP
Input current (with internal pullup)
MIN
VDD = MIN, IOH = MAX
VDD = MIN, IOH = MAX
VDD = MAX
Low-level output voltage
Input current
ICC
Supply current¶#
IDD
Supply current
Standby,
Ci
Input capacitance
UNIT
V
0.4
V
− 20
+ 20
µA
− 10
+ 10
µA
− 600
10
µA
300
mA
fx = 40 MHz
IDLE2,
MAX
2
VI = VSS to VDD
Inputs with internal pullups§
TA = 25°C,
VDD = MAX
TYP‡
150
Clocks shut off
µA
20
All inputs except CLKIN
15*
CLKIN
25
pF
Co
Output capacitance
20*
pF
† All input and output voltage levels are TTL compatible.
‡ For LC31, all typical values are at VDD = 3.3 V, TA = 25°C.
§ Pins with internal pullup devices: INT3 −INT0, MCBL / MP.
¶ Actual operating current is less than this maximum value. This value was obtained under specially produced worst-case test conditions, which
are not sustained during normal device operation. These conditions consist of continuous parallel writes of a checkerboard pattern to both primary
and expansion buses at the maximum rate possible. See Calculation of TMS320C30 Power Dissipation Application Report (literature number
SPRA020).
# fx is the input clock frequency.
* This parameter is not production tested.
NOTE 3: All voltage values are with respect to VSS. All input and output voltage levels are TTL-compatible. CLKIN can be driven by a CMOS
clock.
PARAMETER MEASUREMENT INFORMATION
IOL
Tester Pin
Electronics
VLoad
CT
IOH
Where:
IOL
IOH
VLOAD
CT
=
=
=
=
2 mA (all outputs)
300 µA (all outputs)
2.15 V
80-pF typical load-circuit capacitance
Figure 4. SM320LC31-EP Test Load Circuit
12
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Output
Under
Test
SGUS039 − AUGUST 2002
PARAMETER MEASUREMENT INFORMATION
signal transition levels for LC31 (see Figure 5 and Figure 6)
Outputs are driven to a minimum logic-high level of 2 V and to a maximum logic-low level of 0.4 V. Output
transition times are specified as follows:
D For a high-to-low transition on an output signal, the level at which the output is said to be no longer high
is 2 V and the level at which the output is said to be low is 1 V.
D For a low-to-high transition, the level at which the output is said to be no longer low is 1 V and the level at
which the output is said to be high is 2 V.
2V
1.8 V
0.6 V
0.4 V
Figure 5. LC31 Output Levels
Transition times for inputs are specified as follows:
D For a high-to-low transition on an input signal, the level at which the input is said to be no longer high is
1.8 V and the level at which the input is said to be low is 0.6 V.
D For a low-to-high transition on an input signal, the level at which the input is said to be no longer low is
0.6 V and the level at which the input is said to be high is 1.8 V.
1.8 V
0.6 V
Figure 6. LC31 Input Levels
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PARAMETER MEASUREMENT INFORMATION
timing parameter symbology
Timing parameter symbols used herein were created in accordance with JEDEC Standard 100-A. In order to
shorten the symbols, some of the pin names and other related terminology have been abbreviated as follows,
unless otherwise noted:
14
A
A23 −A0
H
ASYNCH
Asynchronous reset signals
HOLD
HOLD
C
CLKX0
HOLDA
HOLDA
CI
CLKIN
IACK
IACK
CLKR
CLKR0
INT
INT3 −INT0
CONTROL
Control signals
RDY
RDY
D
D31 −D0
RW
R/W
DR
DR
RESET
RESET
DX
DX
S
STRB
FS
FSX/R
SCK
CLKX/R
FSX
FSX0
SHZ
SHZ
FSR
FSR0
TCLK
TCLK0, TCLK1, or TCLKx
GPI
General-purpose input
XF
XF0, XF1, or XFx
GPIO
General-purpose input/output; peripheral pin
XFIO
XFx switching from input to output
GPO
General-purpose output
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H1 and H3
SGUS039 − AUGUST 2002
timing
Timing specifications apply to the SM320LC31-EP.
X2/CLKIN, H1, and H3 timing
The following table defines the timing parameters for the X2/CLKIN, H1, and H3 interface signals.
timing parameters for X2/CLKIN, H1, H3 (see Figure 7, Figure 8, and Figure 9)
NO.
1
2
3
4
5
6
7
8
9
10
MIN
tf(CI)
tw(CIL)
Fall time, CLKIN
Pulse duration, CLKIN low tc(CI) = min
9
tw(CIH)
tr(CI)
Pulse duration, CLKIN high tc(CI) = min
9
tc(CI)
tf(H)
Cycle time, CLKIN
tw(HL)
tw(HH)
Pulse duration, H1 and H3 low
tr(H)
td(HL-HH)
Rise time, H1 and H3
MAX
5*
Rise time, CLKIN
25
Fall time, H1 and H3
Delay time. from H1 low to H3 high or from H3 low to H1 high
11
tc(H)
Cycle time, H1 and H3
† P = tc(CI)
* This parameter is not production tested.
ns
ns
ns
5*
ns
303
ns
3
ns
P−5†
P−6†
Pulse duration, H1 and H3 high
UNIT
ns
ns
3
ns
0
4
ns
50
606
ns
5
4
1
X2/CLKIN
3
2
Figure 7. Timing for X2/CLKIN
11
9
6
H1
8
7
10
10
H3
9
7
6
8
11
Figure 8. Timing for H1 and H3
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SGUS039 − AUGUST 2002
X2/CLKIN, H1, and H3 timing (continued)
12
12
10
CLKIN to H1/H3 - ns
10
8
8
6
6
4
4
3.8 V Band
2
2
0
−60
2.5 V Band
0
−40
−20
0
20
40
60
80
100
Temperature
Figure 9. SM320LC31-EP CLKIN to H1 / H3 as a Function of Temperature
(Typical)
16
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120
140
SGUS039 − AUGUST 2002
memory read/write timing
The following table defines memory read/write timing parameters for STRB.
timing parameters for memory (STRB = 0) read/write (see Figure 10 and Figure 11)†
NO.
12
13
14
15
16
17
18
19
20
21
22
23
MIN
MAX
td(H1L-SL)
td(H1L-SH)
Delay time, H1 low to STRB low
0*
6
ns
Delay time, H1 low to STRB high
0*
6
ns
td(H1H-RWL)R
td(H1L-A)
Delay time, H1 high to R/W low (read)
0*
9
ns
Delay time, H1 low to A valid
0*
10
ns
tsu(D-H1L)R
th(H1L-D)R
Setup time, D before H1 low (read)
14
ns
Hold time, D after H1 low (read)
0
ns
tsu(RDY-H1H)
th(H1H-RDY)
Setup time, RDY before H1 high
8
ns
Hold time, RDY after H1 high
0
td(H1H-RWH)W
tv(H1L-D)W
Delay time, H1 high to R/W high (write)
th(H1H-D)W
td(H1H-A)W
Hold time, D after H1 high (write)
Valid time, D after H1 low (write)
ns
9
ns
17
ns
0
Delay time, H1 high to A valid on back-to-back write cycles (write)
UNIT
ns
15
ns
24
td(A-RDY)
Delay time, RDY from A valid
7*
† See Figure 12 for address bus timing variation with load capacitance greater than typical load-circuit capacitance (CT = 80 pF).
* This parameter is not production tested.
ns
H3
H1
12
13
STRB
R/W
15
14
A
16
17
24
D
18
19
RDY
NOTE A: STRB remains low during back-to-back read operations.
Figure 10. Timing for Memory (STRB = 0) Read
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SGUS039 − AUGUST 2002
memory read / write timing (continued)
H3
H1
13
12
STRB
20
14
R/W
15
23
A
21
22
D
19
18
RDY
Figure 11. Timing for Memory (STRB = 0) Write
Change in Address-Bus Timing, ns
Address-Bus Timing Variation Load Capacitance
4.00
3.50
3.00
2.50
2.00
1.50
1.00
0.50
10
15
20
25
30
35
40
45
50
55
60
65
70
75
80
85
90
95
100
Change in Load Capacitance, pF
NOTE A: 30 pF/ns slope
Figure 12. Address-Bus Timing Variation With Load Capacitance (see Note A)
18
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XF0 and XF1 timing when executing LDFI or LDII
The following table defines the timing parameters for XF0 and XF1 during execution of LDFI or LDII.
timing for XF0 and XF1 when executing LDFI or LDII (see Figure 13)
NO.
25
MIN
Delay time, H3 high to XF0 low
26
td(H3H-XF0L)
tsu(XF1-H1L)
27
th(H1L-XF1)
Hold time, XF1 after H1 low
13
Setup time, XF1 before H1 low
Fetch
LDFI or LDII
MAX
Decode
Read
UNIT
ns
10
ns
0
ns
Execute
H3
H1
STRB
R/W
A
D
RDY
25
XF0 Pin
26
27
XF1 Pin
Figure 13. Timing for XF0 and XF1 When Executing LDFI or LDII
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SGUS039 − AUGUST 2002
XF0 timing when executing STFI and STII†
The following table defines the timing parameters for the XF0 pin during execution of STFI or STII.
timing for XF0 when executing STFI or STII (see Figure 14)
NO.
MIN
28
MAX
UNIT
td(H3H-XF0H) Delay time, H3 high to XF0 high
13
ns
† XF0 is always set high at the beginning of the execute phase of the interlock-store instruction. When no pipeline conflicts occur, the address of
the store is also driven at the beginning of the execute phase of the interlock-store instruction. However, if a pipeline conflict prevents the store
from executing, the address of the store will not be driven until the store can execute.
Fetch
STFI or STII
Decode
Read
Execute
H3
H1
STRB
R/W
A
D
28
RDY
XF0 Pin
Figure 14. Timing for XF0 When Executing an STFI or STII
20
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XF0 and XF1 timing when executing SIGI
The following table defines the timing parameters for the XF0 and XF1 pins during execution of SIGI.
timing for XF0 and XF1 when executing SIGI (see Figure 15)
NO.
29
30
31
32
MIN
MAX
UNIT
td(H3H-XF0L)
td(H3H-XF0H)
Delay time, H3 high to XF0 low
13
ns
Delay time, H3 high to XF0 high
13
ns
tsu(XF1-H1L)
th(H1L-XF1)
Setup time, XF1 before H1 low
Hold time, XF1 after H1 low
Fetch
SIGI
Decode
Read
10
ns
0
ns
Execute
H3
H1
29
31
30
XF0
32
XF1
Figure 15. Timing for XF0 and XF1 When Executing SIGI
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loading when XF is configured as an output
The following table defines the timing parameter for loading the XF register when the XFx pin is configured as
an output.
timing for loading the XF register when configured as an output pin (see Figure 16)
NO.
33
MIN
tv(H3H-XF)
Valid time, H3 high to XFx
Fetch Load
Instruction
13
Decode
Read
Execute
H3
H1
OUTXFx Bit
(see Note A)
1 or 0
33
XFx Pin
NOTE A: OUTXFx represents either bit 2 or 6 of the IOF register.
Figure 16. Timing for Loading XF Register When Configured as an Output Pin
22
MAX
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UNIT
ns
SGUS039 − AUGUST 2002
changing XFx from an output to an input
The following table defines the timing parameters for changing the XFx pin from an output pin to an input pin.
timing of XFx changing from output to input mode (see Figure 17)
NO.
34
35
MIN
th(H3H-XF)
tsu(XF-H1L)
Hold time, XFx after H3 high
13*
Setup time, XFx before H1 low
36
th(H1L-XF)
Hold time, XFx after H1 low
* This parameter is not production tested.
Execute
Load of IOF
MAX
Buffers Go
From Output
to Output
UNIT
ns
10
ns
0
ns
Synchronizer Value on Pin
Seen in IOF
Delay
H3
H1
35
I / OxFx Bit
(see Note A)
36
34
XFx Pin
INXFx Bit
(see Note A)
Output
Data
Sampled
Data
Seen
NOTE A: I / OxFx represents either bit 1 or bit 5 of the IOF register, and INXFx represents either bit 3 or bit 7 of the IOF register.
Figure 17. Timing for Change of XFx From Output to Input Mode
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changing XFx from an input to an output
The following table defines the timing parameter for changing the XFx pin from an input pin to an output pin.
timing for XFx changing from input to output mode (see Figure 18)
NO.
37
MIN
td(H3H-XFIO)
Delay time, H3 high to XFx switching from input to output
MAX
17
UNIT
ns
Execution of
Load of IOF
H3
H1
I / OxFx
Bit
(see Note A)
37
XFx Pin
NOTE A: I / OxFx represents either bit 1 or bit 5 of the IOF register.
Figure 18. Timing for Change of XFx From Input to Output Mode
reset timing
RESET is an asynchronous input that can be asserted at any time during a clock cycle. If the specified timings
are met, the exact sequence shown in Figure 19 occurs; otherwise, an additional delay of one clock cycle is
possible.
The asynchronous reset signals include XF0/1, CLKX0, DX0, FSX0, CLKR0, DR0, FSR0, and TCLK0/1.
Resetting the device initializes the primary- and expansion-bus control registers to seven software wait states
and therefore results in slow external accesses until these registers are initialized.
HOLD is an asynchronous input and can be asserted during reset.
24
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RESET timing (see Figure 19)
NO.
tsu(RESET-CIL)
td(CLKINH-H1H)
Setup time, RESET before CLKIN low
10
MAX
P†*
Delay time, CLKIN high to H1 high (see Note 4)
2
14
ns
td(CLKINH-H1L)
tsu(RESETH-H1L)
Delay time, CLKIN high to H1 low (see Note 4)
2
14
ns
Setup time, RESET high before H1 low and after ten H1 clock cycles
9
td(CLKINH-H3L)
td(CLKINH-H3H)
Delay time, CLKIN high to H3 low (see Note 4)
2
Delay time, CLKIN high to H3 high (see Note 4)
2
tdis(H1H-DZ)
tdis(H3H-AZ)
Disable time, H1 high to D (high impedance)
Disable time, H3 high to A (high impedance)
9*
ns
td(H3H-CONTROLH)
td(H1H-RWH)
Delay time, H3 high to control signals high
9*
ns
47
Delay time, H1 high to R/W high
9*
ns
48
td(H1H-IACKH)
Delay time, H1 high to IACK high
9*
ns
49
tdis(RESETL-ASYNCH)
Disable time, RESET low to asynchronous reset signals disabled (high
impedance)
21*
ns
38
39
40
41
42
43
44
45
46
MIN
UNIT
ns
ns
14
ns
14
ns
13*
ns
† P = tc(CI)
* This parameter is not production tested.
NOTE 4: See Figure 9 for typical temperature dependence.
CLKIN
38
RESET
(see Notes A and B)
39
40
41
H1
42
H3
Ten H1 Clock Cycles
44
D
(see Note C)
43
A
(see Note C)
45
46
Control Signals
(see Note D)
47
SMJ320C31 R/W
(see Note E)
48
IACK
Asynchronous
Reset Signals
(see Note A)
49
NOTES: A. Asynchronous reset signals include XF0 / 1, CLKX0, DX0, FSX0, CLKR0, DR0, FSR0, and TCLK0/1.
B. RESET is an asynchronous input and can be asserted at any point during a clock cycle. If the specified timings are met, the exact
sequence shown occurs; otherwise, an additional delay of one clock cycle is possible.
C. In microprocessor mode, the reset vector is fetched twice, with seven software wait states each time. In microcomputer mode, the
reset vector is fetched twice, with no software wait states.
D. Control signals include STRB.
E. The R/W outputs are placed in a high-impedance state during reset and can be provided with a resistive pullup, nominally
18−22 kΩ, if undesirable spurious writes are caused when these outputs go low.
Figure 19. Timing for RESET
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interrupt response timing
The following table defines the timing parameters for the INT signals.
timing for INT3−INT0 response (see Figure 20)
NO.
50
51
MIN
tsu(INT-H1L)
tw(INT)
Setup time, INT3−INT0 before H1 low
MAX
15
Pulse duration, interrupt to ensure only one interrupt
P
UNIT
ns
2P†*
ns
† P = tc(H)
* This parameter is not production tested.
The interrupt (INT) pins are asynchronous inputs that can be asserted at any time during a clock cycle. The
SM320LC31-EP interrupts are level-sensitive, not edge-sensitive. Interrupts are detected on the falling edge
of H1. Therefore, interrupts must be set up and held to the falling edge of H1 for proper detection. The CPU and
DMA respond to detected interrupts on instruction-fetch boundaries only.
For the processor to recognize only one interrupt on a given input, an interrupt pulse must be set up and held
to:
D A minimum of one H1 falling edge
D No more than two H1 falling edges
The SM320LC31-EP can accept an interrupt from the same source every two H1 clock cycles.
If the specified timings are met, the exact sequence shown in Figure 20 occurs; otherwise, an additional delay
of one clock cycle is possible.
Reset or
Interrupt
Vector Read
Fetch First
Instruction of
Service
Routine
H3
H1
50
INT3 −INT0
Pin
51
INT3 −INT0
Flag
ADDR
Vector Address
First Instruction Address
Data
Figure 20. Timing for INT3−INT0 Response
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interrupt-acknowledge timing
The IACK output goes active on the first half-cycle (HI rising) of the decode phase of the IACK instruction and
goes inactive at the first half-cycle (HI rising) of the read phase of the IACK instruction.
timing for IACK (see Note 5 and Figure 21)
NO.
52
53
MIN
td(H1H-IACKL)
td(H1H-IACKH)
MAX
UNIT
Delay time, H1 high to IACK low
9
ns
Delay time, H1 high to IACK high
9
ns
NOTE 5: IACK goes active on the first half-cycle (H1 rising) of the decode phase of the IACK instruction and goes inactive at the first half-cycle
(H1 rising) of the read phase of the IACK instruction. Because of pipeline conflicts, IACK remains low for one cycle even if the decode
phase of the IACK instruction is extended.
Fetch IACK
Instruction
Decode IACK
Instruction
IACK Data
Read
H3
H1
52
53
IACK
ADDR
Data
Figure 21. Timing for IACK
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27
SGUS039 − AUGUST 2002
serial-port timing (see Figure 22 and Figure 23)
NO.
54
MIN
td(H1H-SCK)
Delay time, H1 high to internal CLKX/R
13
CLKX/R ext
55
tc(SCK)
Cycle time, CLKX/R
56
tw(SCK)
Pulse duration, CLKX/R high/low
57
tr(SCK)
tf(SCK)
Rise time, CLKX/R
CLKX/R int
CLKX/R ext
58
CLKX/R int
tc(H)x2.6
tc(H)x2
tc(H)+10
[tc(SCK)/2]−5
Fall time, CLKX/R
tc(H)x232
[tc(SCK)/2]+5
7
7
CLKX ext
30
CLKX int
17
UNIT
ns
ns
ns
ns
ns
59
td(C-DX)
Delay time, CLKX to DX valid
60
tsu(DR-CLKRL)
Setup time, DR before CLKR low
61
th(CLKRL-DR)
Hold time, DR from CLKR low
62
td(C-FSX)
Delay time, CLKX to internal FSX high/low
63
tsu(FSR-CLKRL)
Setup time, FSR before CLKR low
64
th(SCKL-FS)
Hold time, FSX/R input from CLKX/R low
65
tsu(FSX-C)
Setup time, external FSX before CLKX
66
td(CH-DX)V
Delay time, CLKX to first DX bit, FSX
precedes CLKX high
67
td(FSX-DX)V
Delay time, FSX to first DX bit, CLKX precedes FSX
30*
ns
td(CH-DXZ)
Delay time, CLKX high to DX high impedance following last data
bit
17*
ns
CLKR ext
9
CLKR int
21
CLKR ext
9
CLKR int
0
68
CLKX int
15
CLKR ext
9
9
CLKX/R ext
9
CLKX/R int
0
CLKX int
−[tc(H)−8]*
[tc(H)−21]*
ns
[tc(SCK)/2]−10*
tc(SCK)/2*
30*
CLKX int
18*
• HOUSTON, TEXAS 77251−1443
ns
ns
CLKX ext
* This parameter is not production tested.
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ns
27
CLKR int
ns
ns
CLKX ext
CLKX ext
28
MAX
ns
ns
SGUS039 − AUGUST 2002
data-rate timing modes
Unless otherwise indicated, the data-rate timings shown in Figure 22 and Figure 23 are valid for all serial-port
modes, including handshake. For a functional description of serial-port operation, see the TMS320C3x User’s
Guide (literature number SPRU031).
55
54
H1
54
56
56
CLKX/R
58
57
66
61
Bit n-1
DX
68
59
Bit n-2
Bit 0
60
DR
Bit n-1
Bit n-2
FSR
63
62
62
FSX(INT)
64
FSX(EXT)
64
65
NOTES: A. Timing diagrams show operations with CLKXP = CLKRP = FSXP = FSRP = 0.
B. Timing diagrams depend on the length of the serial-port word, where n = 8, 16, 24, or 32 bits, respectively.
Figure 22. Timing for Fixed Data-Rate Mode
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SGUS039 − AUGUST 2002
data-rate timing modes (continued)
CLKX/R
62
FSX(INT)
67
65
FSX(EXT)
59
68
66
Bit n-1
64
DX
Bit n-2
Bit n-3
Bit 0
FSR
63
Bit n-1
DR
Bit n-2
Bit n-3
60
61
NOTES: A. Timing diagrams show operation with CLKXP = CLKRP = FSXP = FSRP = 0.
B. Timing diagrams depend on the length of the serial-port word, where n = 8, 16, 24, or 32 bits, respectively.
C. The timings that are not specified expressly for the variable data-rate mode are the same as those that are specified for the fixed
data-rate mode.
Figure 23. Timing for Variable Data-Rate Mode
30
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HOLD timing
HOLD is an asynchronous input that can be asserted at any time during a clock cycle. If the specified timings
are met, the exact sequence shown in Figure 27 occurs; otherwise, an additional delay of one clock cycle is
possible.
The NOHOLD bit of the primary-bus control register overrides the HOLD signal. When this bit is set, the device
comes out of hold and prevents future hold cycles.
Asserting HOLD prevents the processor from accessing the primary bus. Program execution continues until a
read from or a write to the primary bus is requested. In certain circumstances, the first write is pending, thus
allowing the processor to continue until a second write is encountered.
timing for HOLD/HOLDA (see Figure 24)
NO.
69
70
71
72
73
74
75
76
77
78
79
MIN
tsu(HOLD-H1L)
tv(H1L-HOLDA)
tw(HOLD)†
Setup time, HOLD before H1 low
13
Valid time, HOLDA after H1 low
0*
tw(HOLDA)
td(H1L-SH)H
Pulse duration, HOLDA low
tdis(H1L-S)
ten(H1L-S)
Pulse duration, HOLD low
MAX
UNIT
ns
9
ns
2tc(H)
tcH−5*
0*
9
ns
Disable time, H1 low to STRB to the high-impedance state
0*
9*
ns
Enable time, H1 low to STRB enabled (active)
0*
9
ns
tdis(H1L-RW)
ten(H1L-RW)
Disable time, H1 low to R/W to the high-impedance state
0*
9*
ns
Enable time, H1 low to R/W enabled (active)
0*
9
ns
tdis(H1L-A)
ten(H1L-A)
Disable time, H1 low to address to the high-impedance state
0*
10*
ns
Enable time, H1 low to address enabled (valid)
0*
13
ns
Delay time, H1 low to STRB high for a HOLD
ns
ns
80
tdis(H1H-D)
Disable time, H1 high to data to the high-impedance state
0*
9*
ns
† HOLD is an asynchronous input and can be asserted at any point during a clock cycle. If the specified timings are met, the exact sequence shown
in Figure 24 occurs; otherwise, an additional delay of one clock cycle is possible.
* This parameter is not production tested.
H3
H1
69
69
71
HOLD
70
70
72
HOLDA
73
74
75
STRB
76
77
R/W
78
79
A
80
D
Write Data
NOTE A: HOLDA goes low in response to HOLD going low and continues to remain low until one H1 cycle
after HOLD goes back high.
Figure 24. Timing for HOLD/HOLDA
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general-purpose I/O timing
Peripheral pins include CLKX0, CLKR0, DX0, DR0, FSX0, FSR0, and TCLK0 / 1. The contents of the internal
control registers associated with each peripheral define the modes for these pins.
peripheral pin I/O timing
The table, timing parameters for peripheral pin general-purpose I/O, defines peripheral pin general-purpose I/O
timing parameters.
timing requirements for peripheral pin general-purpose I/O (see Note 6 and Figure 25)
NO.
81
82
MIN
tsu(GPIO-H1L)
th(H1L-GPIO)
Setup time, general-purpose input before H1 low
Hold time, general-purpose input after H1 low
83
MAX
UNIT
10
ns
0
ns
td(H1H-GPIO)
Delay time, general-purpose output after H1 high
13
ns
NOTE 6: Peripheral pins include CLKX0, CLKR0, DX0, DR0, FSX0, FSR0, and TCLK0 / 1. The modes of these pins are defined by the contents
of internal-control registers associated with each peripheral.
H3
H1
82
81
83
83
Peripheral
Pin
(see Note A)
NOTE A: Peripheral pins include CLKX0, CLKR0, DX0, DR0, FSX0, FSR0, and TCLK0/1.
Figure 25. Timing for Peripheral Pin General-Purpose I/O
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changing the peripheral pin I/O modes
The following tables show the timing parameters for changing the peripheral pin from a general-purpose output
pin to a general-purpose input pin and vice versa.
timing requirements for peripheral pin changing from general-purpose output to input mode
(see Note 6 and Figure 26)
NO.
84
85
MIN
th(H1H)
tsu(GPIO-H1L)
Hold time, peripheral pin after H1 high
MAX
13
Setup time, peripheral pin before H1 low
9
UNIT
ns
ns
86
th(H1L-GPIO)
Hold time, peripheral pin after H1 low
0
ns
NOTE 6: Peripheral pins include CLKX0, CLKR0, DX0, DR0, FSX0, FSR0, and TCLK0 / 1. The modes of these pins are defined by the contents
of internal-control registers associated with each peripheral.
Execution
of Store of
PeripheralControl
Register
Buffers Go
From
Output to
Input
Synchronizer Delay
Value on Pin
Seen in
PeripheralControl
Register
H3
H1
85
I/O
Control Bit
86
84
Peripheral
Pin
(see Note A)
Data Bit
Output
Data
Sampled
Data
Seen
NOTE A: Peripheral pins include CLKX0, CLKR0, DX0, DR0, FSX0, FSR0, and TCLK0/1.
Figure 26. Timing for Change of Peripheral Pin From General-Purpose Output to Input Mode
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timing for peripheral pin changing from general-purpose input to output mode (see Note 6 and
Figure 27)
NO.
MIN
MAX
87
UNIT
td(H1H-GPIO) Delay time, H1 high to peripheral pin switching from input to output
13
ns
NOTE 6: Peripheral pins include CLKX0, CLKR0, DX0, DR0, FSX0, FSR0, and TCLK0 / 1. The modes of these pins are defined by the contents
of internal-control registers associated with each peripheral.
Execution of Store
of PeripheralControl Register
H3
H1
I/O
Control
Bit
87
Peripheral
Pin
(see Note A)
NOTE A: Peripheral pins include CLKX0, CLKR0, DX0, DR0, FSX0, FSR0, and TCLK0/1.
Figure 27. Timing for Change of Peripheral Pin From General-Purpose Input to Output Mode
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timer pin timing
Valid logic-level periods and polarity are specified by the contents of the internal control registers.
The following tables define the timing requirements for the timer pin.
timing for timer pin (see Note 7 and Figure 28)
NO.
88
MIN
Setup time, TCLK external before H1 low
89
tsu(TCLK-H1L)
th(H1L-TCLK)
90
td(H1H-TCLK)
Delay time, H1 high to TCLK internal valid
10
Hold time, TCLK external after H1 low
tc(TCLK)
Cycle time, TCLK
92
tw(TCLK)
Pulse duration, TCLK high/low
TCLK int
TCLK ext
TCLK int
UNIT
ns
0
TCLK ext
91
MAX
ns
9
ns
tc(H)×2.6
tc(H)×2
tc(H)×232*
ns
tc(H)+10
[tc(TCLK)/2]−5
[tc(TCLK)/2]+5
ns
* This parameter is not production tested.
NOTE 7: Numbers 88 and 89 are applicable for a synchronous input clock. Timing parameters 91 and 92 are applicable for an asynchronous
input clock.
H3
H1
89
90
88
Peripheral
Pin
(see Note A)
90
92
91
NOTE A: HOLDA goes low in response to HOLD going low and continues to remain low until one H1 cycle
after HOLD goes back high.
Figure 28. Timing for Timer Pin
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SHZ pin timing
The following table defines the timing parameter for the SHZ pin.
timing parameters for SHZ (see Figure 29)
NO.
93
MIN
tdis(SHZ)
Disable time, SHZ low to all O, I/O pins disabled (high impedance)
† P = tc(CI)
* This parameter is not production tested.
H3
H1
SHZ
93
All I/O Pins
NOTE A: Enabling SHZ destroys SM320LC31-EP register and memory contents. Assert SHZ = 1
and reset the SM320LC31-EP to restore it to a known condition.
Figure 29. Timing for SHZ
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0*
MAX
2P†*
UNIT
ns
SGUS039 − AUGUST 2002
part order information
DEVICE
TECHNOLOGY
POWER
SUPPLY
OPERATING
FREQUENCY
SM320LC31PQM40EP
0.72-µm CMOS
3.3 V ± 5%
40 MHz
SM
320
(L)
C
31
PACKAGE TYPE
PROCESSING
LEVEL
Plastic 132-lead good flatpack
PQ
M
40
EP
EP
ENHANCED PLASTIC
PREFIX
SMJ =
SM =
SMQ =
MIL-PRF-38535 (QML)
Standard Processing
Plastic (QML)
SPEED RANGE
40 = 40 MHz
50 = 50 MHz
60 = 60 MHz
DEVICE FAMILY
320 = SMJ320 Family
TEMPERATURE RANGE
M = − 55°C to 125°C
S = − 55°C to 105°C
L =
0°C to 70°C
TECHNOLOGY
L = Low Voltage
(3.3−V option)
PACKAGE TYPE
GFA = 141-Pin Ceramic Staggered Pin Grid
Array Ceramic Package
HFG = 132-Pin Ceramic Quad Flatpack with a
nonconductive tie bar
PQ
= 132-lead Plastic Quad Flatpack
TA
= 132-lead TAB frame with
polyimide encapsulant
TB
= 132-lead TAB frame, bare-die
option
KGD = Known Good Die
TECHNOLOGY
C = CMOS
DEVICE
31 = 320C31 or 320LC31
Note: Not all speed, package, process, or temperature combinations are available.
Figure 30. Device Nomenclature
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SGUS039 − AUGUST 2002
MECHANICAL DATA
PQ (S-PQFP-G***)
PLASTIC QUAD FLATPACK
100 LEAD SHOWN
13
1 100
89
14
88
0.012 (0,30)
0.008 (0,20)
0.006 (0,15) M
”D3” SQ
0.025 (0,635)
0.006 (0,16) NOM
64
38
0.150 (3,81)
0.130 (3,30)
39
63
Gage Plane
”D1” SQ
”D” SQ
0.010 (0,25)
0.020 (0,51) MIN
”D2” SQ
0°−ā 8°
0.046 (1,17)
0.036 (0,91)
Seating Plane
0.004 (0,10)
0.180 (4,57) MAX
LEADS ***
100
132
MAX
0.890 (22,61)
1.090 (27,69)
MIN
0.870 (22,10)
1.070 (27,18)
MAX
0.766 (19,46)
0.966 (24,54)
MIN
0.734 (18,64)
0.934 (23,72)
MAX
0.912 (23,16)
1.112 (28,25)
MIN
0.888 (22,56)
1.088 (27,64)
NOM
0.600 (15,24)
0.800 (20,32)
DIM
”D”
”D1”
”D2”
”D3”
4040045 / C 11/95
NOTES: A. All linear dimensions are in inches (millimeters).
B. This drawing is subject to change without notice.
C. Falls within JEDEC MO-069
38
POST OFFICE BOX 1443
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