Texas Instruments | SMJ320C50/SMQ320C50 Digital Signal Processors (Rev. B) | Datasheet | Texas Instruments SMJ320C50/SMQ320C50 Digital Signal Processors (Rev. B) Datasheet

Texas Instruments SMJ320C50/SMQ320C50 Digital Signal Processors (Rev. B) Datasheet
SMJ320C50/SMQ320C50
DIGITAL SIGNAL PROCESSOR
SGUS020B -- JUNE 1996 -- REVISED SEPTEMBER 2001
D Military Operating Temperature Range:
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
100
132
1
33
66
D
34
D
D
-- 55°C to 125°C
Processed to MIL-PRF-38535
Fast Instruction Cycle Time (30 ns and
40 ns)
Source-Code Compatible With All C1x
and C2x Devices
RAM-Based Operation
-- 9K × 16-Bit Single-Cycle On-Chip
Program/Data RAM
-- 1056 × 16-Bit Dual-Access On-Chip
Data RAM
2K × 16-Bit On-Chip Boot ROM
224K × 16-Bit Maximum Addressable
External Memory Space (64K Program,
64K Data, 64K I/O, and 32K Global)
32-Bit Arithmetic Logic Unit (ALU)
-- 32-bit Accumulator (ACC)
-- 32-Bit Accumulator Buffer (ACCB)
16-Bit Parallel Logic Unit (PLU)
16 × 16-Bit Multiplier, 32-Bit Product
11 Context-Switch Registers
Two Buffers for Circular Addressing
Full-Duplex Synchronous Serial Port
Time-Division Multiplexed Serial Port (TDM)
Timer With Control and Counter Registers
16 Software Programmable Wait-State
Generators
Divide-by-One Clock Option
IEEE 1149.1† Boundary Scan Logic
Operations Are Fully Static
Enhanced Performance Implanted CMOS
(EPIC™) Technology Fabricated by Texas
Instruments
Packaging
-- 141-Pin Ceramic Grid Array (GFA Suffix)
-- 132-Lead Ceramic Quad Flat Package
(HFG Suffix)
-- 132-Lead Plastic Quad Flat Package
(PQ Suffix)
HFG PACKAGE
(TOP VIEW)
99
67
GFA PACKAGE
(TOP VIEW)
A
C
E
G
J
L
N
R
U
W
B
D
F
H
K
M
P
T
V
1
2
3
4
5
6 8 10 12 14 16 18
7 9 11 13 15 17 19
PQ PACKAGE
(TOP VIEW)
17
1 132
117
18
116
50
84
51
83
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
† IEEE Standard 1149.1-1990 Standard-Test-Access Port and Boundary Scan Architecture
EPIC is a trademark of Texas Instruments Incorporated.
Copyright © 1998, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
POST OFFICE BOX 1443
On products compliant to MIL-STD-883, Class B, all parameters are
tested unless otherwise noted. On all other products, production
processing does not necessarily include testing of all parameters.
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1
SMJ320C50/SMQ320C50
DIGITAL SIGNAL PROCESSOR
SGUS020B -- JUNE 1996 -- REVISED SEPTEMBER 2001
description
The SMJ320C50 digital signal processor (DSP) is a high-performance, 16-bit, fixed-point processor
manufactured in 0.72-μm double-level metal CMOS technology. The SMJ320C50 is the first DSP from TI
designed as a fully static device. Full-static CMOS design contributes to low power consumption while
maintaining high performance, making it ideal for applications such as battery-operated communications
systems, satellite systems, and advanced control algorithms.
A number of enhancements to the basic SMJ320C2x architecture give the C50 a minimum 2× performance over
the previous generation. A four-deep instruction pipeline, that incorporates delayed branching, delayed call to
subroutine, and delayed return from subroutine, allows the C50 to perform instructions in fewer cycles. The
addition of a parallel logic unit (PLU) gives the C50 a method for manipulating bits in data memory without using
the accumulator and ALU. The C50 has additional shifting and scaling capability for proper alignment of
multiplicands or storage of values to data memory.
The C50 achieves its low-power consumption through the IDLE2 instruction. IDLE2 removes the functional
clock from the internal hardware of the C50, which puts it into a total-sleep mode that uses only 7 μA. A low-logic
level on an external interrupt with a duration of at least five clock cycles ends the IDLE2 mode.
The C50 is available with two clock speeds. The clock frequencies are 50 MHz, providing a 40-ns cycle time,
and 66 MHz, providing a 30-ns cycle time. The available options are listed in Table 1.
Table 1. Available Options
†
2
PART NUMBER
SPEED
SUPPLY
VOLTAGE
TOLERANCE
PACKAGE
SMJ320C50GFAM66
30-ns cycle time
±5%
Pin grid array
SMJ320C50HFGM66
30-ns cycle time
±5%
Quad flat package
SMJ320C50GFAM50
40 ns cycle time
±5%
Pin grid array
SMJ320C50HFGM50
40 ns cycle time
±5%
Quad flat package
SMQ320C50PQM66†
30 ns cycle time
±5%
Plastic Quad flat package
When ordering, use DESC P/N 5962-9455804NZD
POST OFFICE BOX 1443
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SMJ320C50/SMQ320C50
DIGITAL SIGNAL PROCESSOR
SGUS020B -- JUNE 1996 -- REVISED SEPTEMBER 2001
functional block diagram
Program Bus (Address)
Program Bus (Data)
IPTR
INT#
INTM
IMR
IFR
BMAR
MUX
PASR
PC(16)
BRAF
MP/MC
Compare
Stack
(8 × 16)
PAER
CNF
RAM
Program Memory
BRCR
Data Bus (Data)
TRM
TREG2
TREG1
MUX
TREG0
Multiplier
MUX
MUX
PREG(32)
COUNT
PM
Prescaler
P-Scaler
MUX
OVM
SXM
ALU(32)
ACCB(32)
ACC(32)
Post-Scaler
OV
TC
C
DBMR
MUX
BIM
PLU(16)
Data Bus (Data)
MUX
CBER
INDX
ARP
ARCR
NDX
CBSR
AUXREGS
(8 × 16)
MUX
CBCR
ARB
DP(9)
dma(7)
MUX
MUX
XF
ARAU(16)
Data Bus (Address)
Data Memory
CNF
OVLY
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GREG
BR
• HOUSTON, TEXAS 77251--1443
3
SMJ320C50/SMQ320C50
DIGITAL SIGNAL PROCESSOR
SGUS020B -- JUNE 1996 -- REVISED SEPTEMBER 2001
terminal assignments
NAME
PQ PKG
HFG PKG
NAME
PQ PKG
HFG PKG
GFA PKG
NC†
18
1
GFA PKG
A2
57
40
W3
NC†
19
2
A3
58
41
U7
VSS3
20
3
D8
A4
59
42
V6
VSS4
21
4
D10
A5
60
43
W5
NC†
22
5
A6
61
44
U9
D7
23
6
E3
A7
62
45
V8
D6
24
7
D2
A8
63
46
W7
D5
25
8
C1
A9
64
47
W9
D4
26
9
G3
VDD7
65
48
E9
D3
27
10
F2
VDD8
66
49
E11
D2
28
11
E1
TDI
67
50
V10
D1
29
12
J3
VSS9
68
51
K4
D0(LSB)
30
13
H2
VSS10
69
52
M4
TMS
31
14
G1
NC†
70
53
VDD3
32
15
C3
CLKMD1
71
54
W11
VDD4
33
16
D4
A10
72
55
W13
TCK
34
17
J1
A11
73
56
V12
VSS5
35
18
D12
A12
74
57
U11
VSS6
36
19
F4
A13
75
58
W15
NC†
37
20
A14
76
59
V14
INT1
38
21
L1
A15(MSB)
77
60
U13
INT2
39
22
N1
NC†
78
61
INT3
40
23
M2
NC†
79
62
INT4
41
24
L3
VDD9
80
63
E13
NMI
42
25
R1
VDD10
81
64
G5
DR
43
26
P2
RD
82
65
V16
TDR
44
27
N3
WE
83
66
U15
FSR
45
28
T2
NC†
84
67
CLKR
46
29
R3
NC†
85
68
VDD5
47
30
E5
VSS11
86
69
P4
VDD6
48
31
E7
VSS12
87
70
T4
NC†
49
32
NC†
88
71
NC†
50
33
DS
89
72
NC†
51
34
IS
90
73
T18
NC†
52
35
PS
91
74
U19
VSS7
53
36
H4
R/W
92
75
N17
VSS8
54
37
K2
STRB
93
76
P18
A0
55
38
U5
BR
94
77
R19
A1
56
39
V4
CLKIN2
95
78
L17
†
NC = No internal connection
GFA Package additional connections:
VDD: R11, E15, G15, J15, L15, N15, R13, R15, T16, U17, V18, W17, W19
VSS: T14, U1, U3, V2, W1, C17, C19, D14, D16, D18, F16, H16, K16, M16, P16
4
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R17
SMJ320C50/SMQ320C50
DIGITAL SIGNAL PROCESSOR
SGUS020B -- JUNE 1996 -- REVISED SEPTEMBER 2001
terminal assignments (continued)
NAME
PQ PKG
HFG PKG
GFA PKG
NAME
PQ PKG
HFG PKG
GFA PKG
X2/CLKIN
96
79
M18
TCLKX
123
106
B16
X1
97
80
N19
CLKX
124
107
A17
VDD11
98
81
J5
TFSR/TADD
125
108
C13
VDD12
99
82
L5
TCLKR
126
109
B14
A15
TDO
100
83
L19
RS
127
110
VSS13
101
84
T6
READY
128
111
C11
VSS14
102
85
T8
HOLD
129
112
B12
CLKMD2
103
86
K18
BIO
130
113
A13
FSX
104
87
J19
VDD15
131
114
R7
TFSX/TFRM
105
88
G19
VDD16
132
115
R9
DX
106
89
H18
IAQ
1
116
A11
TDX
107
90
J17
TRST
2
117
A9
HOLDA
108
91
E19
VSS1
3
118
B10
XF
109
92
F18
VSS2
4
119
D6
CLKOUT1
110
93
G17
MP/MC
5
120
A7
NC†
111
94
D15(MSB)
6
121
B8
IACK
112
95
E17
D14
7
122
C9
VDD13
113
96
N5
D13
8
123
A5
VDD14
114
97
R5
D12
9
124
B6
NC†
115
98
D11
10
125
C7
NC†
116
99
D10
11
126
A3
NC†
117
100
D9
12
127
B4
EMU0
118
101
B18
D8
13
128
C5
EMU1/OFF
119
102
A19
VDD1
14
129
A1
VSS15
120
103
T10
VDD2
15
130
B2
16
131
17
132
VSS16
121
104
T12
NC†
TOUT
122
105
C15
NC†
†
NC = No internal connection
GFA Package additional connections:
VDD: R11, E15, G15, J15, L15, N15, R13, R15, T16, U17, V18, W17, W19
VSS: T14, U1, U3, V2, W1, C17, C19, D14, D16, D18, F16, H16, K16, M16, P16
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• HOUSTON, TEXAS 77251--1443
5
SMJ320C50/SMQ320C50
DIGITAL SIGNAL PROCESSOR
SGUS020B -- JUNE 1996 -- REVISED SEPTEMBER 2001
Terminal Functions
TERMINAL
NAME
DESCRIPTION
TYPE†
ADDRESS AND DATA BUSES
A15 (MSB)
A14
A13
A12
A11
A10
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0 (LSB)
I/O/Z
Parallel address bus. Multiplexed to address external data, program memory, or I/O. A0--A15 are in the
high-impedance state in hold mode and when OFF is active (low). These signals are used as inputs for external DMA
access of the on-chip single-access RAM. They become inputs while HOLDA is active (low) if BR is driven low
externally.
D15 (MSB)
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0 (LSB)
I/O/Z
Parallel data bus. Multiplexed to transfer data between the core CPU and external data, program memory, or I/O
devices. D0--D15 are in the high-impedance state when not outputting data, when RS or HOLD is asserted, or when
OFF is active (low). These signals also are used in external DMA access of the on-chip single-access RAM.
MEMORY CONTROL SIGNALS
DS
PS
IS
O/Z
Data, program, and I/O space select signals. Always high unless asserted for communicating to a particular external
space. DS, PS, and IS are in the high-impedance state in hold mode or when OFF is active (low).
I
Data ready input. Indicates that an external device is prepared for the bus transaction to be completed. If the device
is not ready (READY is low), the processor waits one cycle and checks READY again. READY also indicates a bus
grant to an external device after a BR (bus request) signal.
R/W
I/O/Z
Read/write. R/W indicates transfer direction during communication to an external device and is normally in read
mode (high) unless asserted for performing a write operation. R/W is in the high-impedance state in hold mode or
when OFF is active (low). Used in external DMA access of the 9K RAM cell, this signal indicates the direction of the
data bus for DMA reads (high) and writes (low) when HOLDA and IAQ are active (low).
STRB
I/O/Z
Strobe. Always high unless asserted to indicate an external bus cycle, STRB is in the high-impedance state in the
hold mode or when OFF is active (low). Used in external DMA access of the on-chip single-access RAM and while
HOLDA and IAQ are active (low), STRB is used to select the memory access.
RD
O/Z
Read select. RD indicates an active external read cycle and can connect directly to the output enable (OE) of external
devices. This signal is active on all external program, data, and I/O reads. RD is in the high-impedance state in hold
mode or when OFF is active (low).
READY
†
I = Input, O = Output, Z = High-Impedance
NOTE: All input pins that are unused should be connected to VDD or an external pullup resistor. The BR pin has an internal pullup for performing
DMA to the on-chip RAM. For emulation, TRST has an internal pulldown, and TMS, TCK, and TDI have internal pullups. EMU0 and EMU1
require external pullups to support emulation.
6
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SMJ320C50/SMQ320C50
DIGITAL SIGNAL PROCESSOR
SGUS020B -- JUNE 1996 -- REVISED SEPTEMBER 2001
Terminal Functions (Continued)
TERMINAL
NAME
DESCRIPTION
TYPE†
MEMORY CONTROL SIGNALS (CONTINUED)
WE
O/Z
Write enable. The falling edge indicates that the device is driving the external data bus (D15--D0). Data can be
latched by an external device on the rising edge of WE. This signal is active on all external program, data, and I/O
writes. WE is in the high-impedance state in hold mode or when OFF is active (low).
MULTIPROCESSING SIGNALS
I
Hold. HOLD is asserted to request control of the address, data, and control lines. When acknowledged by the C50,
these lines go to the high-impedance state.
O/Z
Hold acknowledge. HOLDA indicates to the external circuitry that the processor is in a hold state and that the
address, data, and memory control lines are in the high-impedance state so that they are available to the external
circuitry for access to local memory. This signal also goes to the high-impedance state when OFF is active (low).
I/O/Z
Bus request. BR is asserted during access of external global data memory space. READY is asserted when the
global data memory is available for the bus transaction. BR can be used to extend the data memory address space
by up to 32K words. BR goes to the high-impedance state when OFF is active low. BR is used in external DMA access
of the on-chip single-access RAM. While HOLDA is active (low), BR is externally driven (low) to request access to
the on-chip single-access RAM.
IAQ
O/Z
Instruction acquisition. Asserted (active) when there is an instruction address on the address bus; goes into the
high-impedance state when OFF is active (low). IAQ is also used in external DMA access of the on-chip
single-access RAM. While HOLDA is active (low), IAQ acknowledges the BR request for access of the on-chip
single-access RAM and stops indicating instruction acquisition.
BIO
I
Branch control. BIO samples as the BIO condition and, if it is low, causes the device to execute the conditional
instruction. BIO must be active during the fetch of the conditional instruction.
XF
O/Z
External flag (latched software-programmable signal). Set high or low by a specific instruction or by loading status
register 1 (ST1). Used for signaling other processors in multiprocessor configurations or as a general-purpose
output. XF goes to the high-impedance state when OFF is active (low) and is set high at reset.
IACK
O/Z
Interrupt acknowledge. Indicates receipt of an interrupt and that the program counter is fetching the interrupt vector
location designated by A15--A0. IACK goes to the high-impedance state when OFF is active (low).
HOLD
HOLDA
BR
INITIALIZATION, INTERRUPT, AND RESET OPERATIONS
INT4
INT3
INT2
INT1
I
External interrupts. INT1--INT4 are prioritized and maskable by the interrupt mask register (IMR) and interrupt mode
bit (INTM, bit 9 of status register 0). These signals can be polled and reset by using the interrupt flag register.
NMI
I
Nonmaskable interrupt. NMI is the external interrupt that cannot be masked via INTM or IMR. When NMI is activated,
the processor traps to the appropriate vector location.
RS
I
Reset. RS causes the device to terminate execution and forces the program counter to zero. When RS is brought
to a high level, execution begins at location zero of program memory.
I
Microprocessor/microcomputer select. If active (low) at reset (microcomputer mode), the signal causes the internal
program ROM to be mapped into program memory space. In the microprocessor mode, all program memory is
mapped externally. This signal is sampled only during reset, and the mode that is set at reset can be overridden via
the software control bit MP/MC in the PMST register.
O/Z
Master clock (or CLKIN2 frequency). CLKOUT1 cycles at the machine-cycle rate of the CPU. The internal machine
cycle is bounded by the rising edges of this signal. This signal goes to the high-impedance state when OFF is active
(low).
MP/MC
OSCILLATOR/TIMER SIGNALS
CLKOUT1
†
I = Input, O = Output, Z = High-Impedance
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7
SMJ320C50/SMQ320C50
DIGITAL SIGNAL PROCESSOR
SGUS020B -- JUNE 1996 -- REVISED SEPTEMBER 2001
Terminal Functions (Continued)
TERMINAL
NAME
DESCRIPTION
TYPE†
OSCILLATOR/TIMER SIGNALS (CONTINUED)
CLKMD1
CLKMD2
I
CLKMD1
0
CLKMD2
0
0
1
1
0
1
1
Clock mode
External clock with divide-by-two option. Input clock is provided to X2/CLKIN1. Internal
oscillator and PLL are disabled.
Reserved for test purposes
External divide-by-one option. Input clock is provided to CLKIN2. Internal oscillator is
disabled and internal PLL is enabled.
Internal or external divide-by-two option. Input clock is provided to X2/CLKIN1. Internal
oscillator is enabled and internal PLL is disabled.
X2/CLKIN
I
Input to the internal oscillator from the crystal. If the internal oscillator is not being used, a clock can be input to the
device on X2/CLKIN. The internal machine cycle is half this clock rate.
X1
O
Output from the internal oscillator for the crystal. If the internal oscillator is not used, X1 must be left unconnected.
This signal does not go to the high-impedance state when OFF is active (low).
CLKIN2
I
Divide-by-one input clock for driving the internal machine rate.
TOUT
O
Timer output. TOUT signals a pulse when the on-chip timer counts down past zero. The pulse is a CLKOUT1 cycle
wide.
SUPPLY PINS
VDD1
VDD2
VDD3
VDD4
I
Power supply for data bus
VDD5
VDD6
I
Power supply for address bus
VDD7
VDD8
I
Power supply for inputs and internal logic
VDD9
VDD10
I
Power supply for address bus
VDD11
VDD12
I
Power supply for memory control signals
VDD13
VDD14
I
Power supply for inputs and internal logic
VDD15
VDD16
I
Power supply for memory control signals
VSS1
VSS2
I
Ground for memory control signals
VSS3
VSS4
VSS5
VSS6
I
Ground for data bus
VSS7
VSS8
VSS9
VSS10
I
Ground for address bus
VSS11
VSS12
I
Ground for memory control signals
VSS13
VSS14
VSS15
VSS16
I
Ground for inputs and internal logic
†
8
I = Input, O = Output, Z = High-Impedance
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SMJ320C50/SMQ320C50
DIGITAL SIGNAL PROCESSOR
SGUS020B -- JUNE 1996 -- REVISED SEPTEMBER 2001
Terminal Functions (Continued)
TERMINAL
NAME
DESCRIPTION
TYPE†
SERIAL PORT SIGNALS
CLKR
TCLKR
CLKX
TCLKX
I
Receive clock. External clock signal for clocking data from DR (data receive) or TDR (TDM data receive) into the
RSR (serial port receive shift register). Must be present during serial port transfers. If the serial port is not being used,
these signals can be sampled as an input via the IN0 bit of the serial port control (SPC) or TDR serial port control
(TSPC) registers.
I/O/Z
Transmit clock. Clock signal for clocking data from the DR or TDR to the DX (data transmit) or TDX (TDM data
transmit pins). CLKX can be an input if the MCM bit in the serial port control register is set to 0. It can also be driven
by the device at 1/4 the CLKOUT1 frequency when the MCM bit is set to 1. If the serial port is not being used, this
pin can be sampled as an input via the IN1 bit of the SPC or TSPC register. This signal goes into the high-impedance
state when OFF is active (low).
DR
TDR
I
DX
TDX
O/Z
Serial port transmit. Serial data transmitted from XSR (serial port transmit shift register) via DX or TDX. This signal
is in the high-impedance state when not transmitting and when OFF is active (low).
FSR
TFSR/TADD
I
I/O/Z
Frame synchronization pulse for receive. The falling edge of FSR or TFSR initiates the data receive process, which
begins the clocking of the RSR. TFSR becomes an input/output (TADD) pin when the serial port is operating in the
TDM mode (TDM bit = 1). In TDM mode, this pin is used to input/output the address of the port. This signal goes
into the high-impedance state when OFF is active (low).
I/O/Z
Frame synchronization pulse for transmit. The falling edge of FSX/TFSX initiates the data transmit process, which
begins the clocking of the XSR. Following reset, the default operating condition of FSX/TFSX is an input. This pin
may be selected by software to be an output when the TXM bit in the serial control register is set to 1. This signal
goes to the high-impedance state when OFF is active (low). When operating in TDM mode (TDM bit = 1), TFSX
becomes TFRM, the TDM frame-synchronization pulse.
FSX
TFSX/TFRM
Serial data receive. Serial data is received in the RSR (serial port receive shift register) via DR or TDR.
TEST SIGNALS
TCK
I
Boundary scan test clock. This is normally a free-running clock with a 50% duty cycle. The changes of TAP (test
access port) input signals (TMS and TDI) are clocked into the TAP controller, instruction register, or selected test
data register on the rising edge of TCK. Changes at the TAP output signal (TDO) occur on the falling edge of TCK.
TDI
I
Boundary scan test data input. TDI is clocked into the selected register (instruction or data) on a rising edge of TCK.
TDO
O/Z
Boundary scan test data output. The contents of the selected register (instruction or data) is shifted out of TDO on
the falling edge of TCK. TDO is in the high-impedance state except when scanning of data is in progress. This signal
also goes to the high-impedance state when OFF is active (low).
TMS
I
Boundary scan test mode select. This serial control input is clocked into the test access port (TAP) controller on the
rising edge of TCK.
TRST
I
Boundary scan test reset. Asserting this signal gives the JTAG scan system control of the operations of the device.
If this signal is not connected or is driven low, the device operates in its functional mode and the boundary scan
signals are ignored.
EMU0
I/O/Z
Emulator 0. When TRST is driven low, EMU0 must be high for activation of the OFF condition (see EMU1/OFF).
When TRST is driven high, EMU0 is used as an interrupt to or from the emulator system and is defined as input/output
put via boundary scan.
EMU1/OFF
I/O/Z
Emulator 1/OFF. When TRST is driven high, EMU1/OFF is used as an interrupt to or from the emulator system and
is defined as input/output via boundary scan. When TRST is driven low, EMU1/OFF is configured as OFF. When
the OFF signal is active (low), all output drivers are in the high-impedance state. OFF is used exclusively for testing
and emulation purposes (not for multiprocessing applications). For the OFF condition, the following conditions apply:
•
•
•
RESERVED‡
N/C
TRST = Low
EMU0 = High
EMU1/OFF = Low
Reserved. This pin must be left unconnected.
†
I = Input, O = Output, Z = High-Impedance
‡ Quad flat pack only
POST OFFICE BOX 1443
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9
SMJ320C50/SMQ320C50
DIGITAL SIGNAL PROCESSOR
SGUS020B -- JUNE 1996 -- REVISED SEPTEMBER 2001
absolute maximum ratings over operating case temperature range (unless otherwise noted)†
Supply voltage range, VDD (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input voltage range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output voltage range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Operating case temperature range, TC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . --
-- 0.3 V to 7 V
-- 0.3 V to 7 V
-- 0.3 V to 7 V
55°C to 125°C
65°C to 150°C
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTE 1: All voltage values are with respect to VSS.
recommended operating conditions
VDD
Supply voltage
VSS
Supply voltage
VIH
VIL
MIN
NOM
MAX
UNIT
4.75
5
5.25
V
0
High-level
High
level input voltage
3.0
VDD + 0.3
V
CLKX, CLKR, TCLKX, TCLKR
2.5
VDD + 0.3
V
All others
2.2
VDD + 0.3
V
-- 0.3
0.6
V
Low-level input voltage
IOH
High-level output current
IOL
Low-level output current
TC
Operating case temperature (see Note 2)
V
CLKIN, CLKIN2
--- 55
300‡
μA
2
mA
125
°C
‡
This IOH can be exceeded when using a 1-KΩ pulldown resistor on the TDM serial port TADD output; however, this output still meets VOH
specifications under these conditions.
NOTE 2: TC MAX at maximum rated operating conditions at any point on case. TC MIN at initial (time zero) power up.
electrical characteristics over recommended ranges of supply voltage and operating case
temperature (unless otherwise noted)
TEST CONDITIONS§
PARAMETER
VOH
High-level output voltage#
IOH = MAX
VOL
voltage¶
IOL = MAX
IOZ
II
Low-level output
High impedance output
High-impedance
current (VDD = MAX)
Input current
(VI = VSS to VDD)
MIN
TYP¶
2.4
3
MAX
UNIT
V
0.3
0.6
-- 500
||
30
All others
-- 30
||
30
TRST (with internal pulldown)
-- 30
||
800
-- 500
||
30
X2/CLKIN
-- 50
||
50
All other inputs
-- 30
||
30
μA
60
225
mA
40
225
mA
30
mA
7
μA
BR (with internal pullup)
TMS, TCK, TDI (with internal pullups)
IDDC
Supply current, core CPU
Operating,
TA = 25°C,
IDDP
Supply current, pins
Operating,
TA = 25°C,
VDD = 5.25 V, fx = 50 MHz
VDD = 5.25 V, fx = 50 MHz
IDLE instruction,
TC = 125°C,
VDD = 5.25 V, fx = 50 MHz
V
μA
A
μA
IDD
Supply current,
current standby
Ci
Input capacitance
15
40
pF
Co
Output capacitance
15
40
pF
IDLE2 instruction, Clocks shut off, TC =125°C,
VDD =5.25 V
§
For conditions shown as MIN/MAX, use the appropriate value specified under recommended operating conditions.
All typical or nominal values are at VDD = 5 V, TA (ambient air temperature)= 25°C.
# All input and output voltage levels are TTL-compatible. Figure 1 shows the test load circuit; Figure 2 and Figure 3 show the voltage reference
levels.
|| These values are not specified pending detailed characterization.
¶
10
POST OFFICE BOX 1443
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SMJ320C50/SMQ320C50
DIGITAL SIGNAL PROCESSOR
SGUS020B -- JUNE 1996 -- REVISED SEPTEMBER 2001
PARAMETER MEASUREMENT INFORMATION
IOL
Tester Pin
Electronics
50 Ω
VLOAD
Output
Under
Test
CT
IOH
Where:
IOL
IOH
VLOAD
CT
=
=
=
=
2.0 mA (all outputs)
300 μA (all outputs)
1.5 V
80 pF typical load circuit capacitance
Figure 1. Test Load Circuit
signal transition levels
Transistor-to-transistor logic (TTL) output levels are driven to a minimum logic-high level of 2.4 V and to a
maximum logic-low level of 0.6 V. Figure 2 shows the TTL-level outputs.
2.4 V
2V
1V
0.6 V
Figure 2. TTL-Level Outputs
TTL-output transition times are specified as follows:
D For a high-to-low transition, the level at which the output is said to be no longer high is 2 V, and the level
D
at which the output is said to be low is 1 V.
For a low-to-high transition, the level at which the output is said to be no longer low is 1 V, and the level
at which the output is said to be high is 2 V.
Figure 3 shows the TTL-level inputs.
2.2 V
0.6 V
Figure 3. TTL-Level Inputs
TTL-compatible input transition times are specified as follows:
D For a high-to-low transition on an input signal, the level at which the input is said to be no longer high
is 2 V, and the level at which the input is said to be low is 0.8 V.
D For a low to high transisiton on an input signal, the level at which the input is said to be no longer low
is 0.8 V, and the level at which the input is said to be high is 2 V.
POST OFFICE BOX 1443
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11
SMJ320C50/SMQ320C50
DIGITAL SIGNAL PROCESSOR
SGUS020B -- JUNE 1996 -- REVISED SEPTEMBER 2001
CLOCK CHARACTERISTICS AND TIMING
The C50 can use either its internal oscillator or an external frequency source for a clock. The clock mode is
determined by the CLKMD1 and CLKMD2 pins. Table 2 outlines the selection of the clock mode by these pins.
Table 2. Clock Mode Selection
CLKMD1
CLKMD2
1
0
External divide-by-one clock option
CLOCK SOURCE
0
1
Reserved for test purposes
1
1
External divide-by-two option or internal divide-by-two clock option
with an external crystal
0
0
External divide-by-two option with the internal oscillator disabled
internal divide-by-two clock option with external crystal
The internal oscillator is enabled by connecting a crystal across X1 and X2/CLKIN. The frequency of CLKOUT1
is one-half the crystal’s oscillating frequency. The crystal should be in either fundamental or overtone operation
and parallel resonant, with an effective series resistance of 30 Ω and a power dissipation of 1 mW; it should be
specified at a load capacitance of 20 pF. Overtone crystals require an additional tuned LC circuit. Figure 4 shows
an external crystal (fundamental frequency) connected to the on-chip oscillator.
recommended operating conditions for internal divide-by-two clock option
’320C50-50
MIN
†
fx
Input clock frequency
C1, C2
Load capacitance
NOM
0†
10
’320C50-66
MAX
MIN
50
0†
NOM
MAX
66
10
UNIT
MHz
pF
This device uses a fully static design and, therefore, can operate with tc(CI) approaching ∞. The device is characterized at frequencies
approaching 0 Hz but is tested at a minimum of 3.3 MHz to meet device test time requirements.
X1
X2/CLKIN
Crystal
C1
C2
Figure 4. Internal Clock Option
12
POST OFFICE BOX 1443
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SMJ320C50/SMQ320C50
DIGITAL SIGNAL PROCESSOR
SGUS020B -- JUNE 1996 -- REVISED SEPTEMBER 2001
external divide-by-two clock option
An external frequency source can be used by injecting the frequency directly into X2/CLKIN with X1 left
unconnected, CLKMD1 set high, and CLKMD2 set high. The external frequency is divided by two to generate
the internal machine cycle. The external frequency injected must conform to specifications listed in the timing
requirements table.
switching characteristics over recommended operating conditions [H = 0.5 tc(CO)]
’320C50-50
PARAMETER
†
’320C50-66
UNIT
MIN
TYP
MAX
MIN
TYP
MAX
40
2tc(CI)
†
30
2tc(CI)
†
ns
3
11
20
3
11
20
ns
tc(CO)
Cycle time, CLKOUT1
td(CIH-COH/L)
Delay time, X2/CLKIN high to CLKOUT1 high/low
tf(CO)
Fall time, CLKOUT1
5
5
ns
tr(CO)
Rise time, CLKOUT1
5
5
ns
tw(COL)
Pulse duration, CLKOUT1 low
H -- 3
H
H+2
H -- 3
H
H+2
ns
tw(COH)
Pulse duration, CLKOUT1 high
H -- 3
H
H+2
H -- 3
H
H+2
ns
This device uses a fully static design and, therefore, can operate with tc(CI) approaching ∞. The device is characterized at frequencies
approaching 0 Hz, but is tested at a minimum of 6.7 MHz to meet device test time requirements.
timing requirements
’320C50-50
’320C50-66
MIN
MAX
MIN
MAX
20
†
15
†
ns
5*
ns
UNIT
tc(CI)
Cycle time, X2/CLKIN
tf(CI)
Fall time, X2/CLKIN
tr(CI)
Rise time, X2/CLKIN
5*
ns
tw(CIL)
Pulse duration, X2/CLKIN low
8
†
7
†
ns
tw(CIH)
Pulse duration, X2/CLKIN high
8
†
7
†
ns
5*
5*
†
This device uses a fully static design and, therefore, can operate with tc(CI) approaching ∞. The device is characterized at frequencies
approaching 0 Hz, but is tested at a minimum of 6.7 MHz to meet device test time requirements.
* This parameter is not production tested.
tr(CI)
tw(CIH)
tc(CI)
tw(CIL)
tf(CI)
CLKIN
tf(CO)
tc(CO)
td(CIH-COH/L)
tw(COH)
tr(CO)
tw(COL)
CLKOUT1
Figure 5. External Divide-by-Two Clock Timing
POST OFFICE BOX 1443
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13
SMJ320C50/SMQ320C50
DIGITAL SIGNAL PROCESSOR
SGUS020B -- JUNE 1996 -- REVISED SEPTEMBER 2001
external divide-by-one clock option
An external frequency source can be used by injecting the frequency directly into CLKIN2 with X1 left
unconnected and X2 connected to VDD. This external frequency is divided by one to generate the internal
machine cycle. The divide-by-one option is used when CLKMD1 is strapped high and CLKMD2 is strapped low.
The external frequency injected must conform to specifications listed in the timing requirements table (see
Figure 6 for more details).
switching characteristics over recommended operating conditions [H = 0.5 tc(CO)]
’320C50-50
PARAMETER
’320C50-66
UNIT
MIN
TYP
MAX
MIN
TYP
MAX
40
tc(CI)
75*
30
tc(CI)
75*
ns
2
9
16
2
9
16
ns
tc(CO)
Cycle time, CLKOUT1
td(C2H-COH)
Delay time, CLKIN2 high to CLKOUT1 high
tf(CO)
Fall time, CLKOUT1
5
5
ns
tr(CO)
Rise time, CLKOUT1
5
5
ns
tw(COL)
Pulse duration, CLKOUT1 low
H -- 3*
H
H + 2*
H -- 3*
H
H + 2*
ns
tw(COH)
Pulse duration, CLKOUT1 high
H -- 3*
H
H + 2*
H -- 3*
H
H + 2*
ns
td(TP)
Delay time, transitory phase--PLL
synchronized after CLKIN2 supplied
*
1000tc(C2)*
1000tc(C2)*
ns
This parameter is not production tested.
timing requirements over recommended ranges of supply voltage and operating case temperature
’320C50-50
’320C50-66
UNIT
MIN
MAX
MIN
MAX
40
75†
30
75†
UNIT
ns
tc(C2)
Cycle time, CLKIN2
tf(C2)
Fall time, CLKIN2
5*
5*
ns
tr(C2)
Rise time, CLKIN2
5*
5*
ns
tw(C2L)
Pulse duration, CLKIN2 low
11
tc(C2)--11
9
tc(C2)--9
ns
tw(C2H)
Pulse duration, CLKIN2 high
11
tc(C2)--11
9
tc(C2)--9
ns
*
This parameter is not production tested.
† Clocks can be stopped only while the device executes IDLE2 when using the external divide-by-one clock option. Note that tp (the transitory
phase) occurs when restarting clock from IDLE2 in this mode.
tw(C2H)
tc(C2)
tw(C2L)
tf(C2)
tr(C2)
CLKIN2
td(C2H-COH)
tw(COH)
tc(CO)
tw(COL)
td(TP)
CLKOUT1
Unstable
Figure 6. External Divide-by-One Clock Timing
14
POST OFFICE BOX 1443
tf(CO)
• HOUSTON, TEXAS 77251--1443
tr(CO)
SMJ320C50/SMQ320C50
DIGITAL SIGNAL PROCESSOR
SGUS020B -- JUNE 1996 -- REVISED SEPTEMBER 2001
MEMORY AND PARALLEL I/O INTERFACE READ
Memory and parallel I/O interface read timings are illustrated in Figure 7.
switching characteristics over recommended operating conditions [H = 0.5tc(CO)]
PARAMETER
tsu(AV-RDL)
MIN
Setup time, address valid before RD low
MAX
UNIT
H--10†‡
ns
0†‡
ns
th(RDH-AV)
Hold time, address valid after RD high
tw(RDL)
Pulse duration, RD low
H--2§*
ns
tw(RDH)
Pulse duration, RD high
H--2§*
ns
td(RDH-WEL)
Delay time, RD high to WE low
2H--5
ns
†
A15--A0, PS, DS, IS, R/W, and BR timings are all included in timings referenced as address.
‡ See Figure 8 for address-bus timing variation with load capacitance.
§ STRB and RD timing is -- 3/+5 ns from CLKOUT1 timing on read cycles, following the first cycle after reset, which is always a seven wait-state cycle.
* This parameter is not production tested.
timing requirements
MIN
‡
ta(RDAV)
Access time, read data valid from address valid
ta(RDL-RD)
Access time, read data valid after RD low
tsu(RD-RDH)
Setup time, read data valid before RD high
th(RDH-RD)
Hold time, read data valid after RD high
MAX
UNIT
2H--15‡
ns
H--10
ns
10
ns
0
ns
See Figure 8 for address-bus timing variation with load capacitance.
POST OFFICE BOX 1443
• HOUSTON, TEXAS 77251--1443
15
SMJ320C50/SMQ320C50
DIGITAL SIGNAL PROCESSOR
SGUS020B -- JUNE 1996 -- REVISED SEPTEMBER 2001
MEMORY AND PARALLEL I/O INTERFACE WRITE
Memory and parallel I/O interface read timings are illustrated in Figure 7.
switching characteristics over recommended operating conditions [H = 0.5tc(CO)]
PARAMETER
tsu(AV-WEL)
MIN
Hold time, address valid after WE high
H --
tw(WEL)
Pulse duration, WE low
2H -- 4§*
tw(WEH)
Pulse duration, WE high
2H -- 2§
td(WEH-RDL)
Delay time, WE high to RD low
tsu(WDV-WEH)
Setup time, write data valid before WE high
Hold time, write data valid after WE high
ten(WE-BUd)
Enable time, WE to data bus driven
UNIT
ns
10†‡
th(WEH-AV)
th(WEH-WDV)
MAX
H -- 5†‡
Setup time, address valid before WE low
ns
2H + 2§*
ns
ns
3H -- 10
ns
2H -- 20§*
2H§¶*
ns
5§*
H+10§*
ns
H --
--5*
ns
†
A15--A0,PS, DS, IS, R/W, and BR timings are all included in timings referenced as address.
‡ See Figure 8 for address bus timing variation with load capacitance.
§ STRB and WE edges are 0--4 ns from CLKOUT1 edges on writes. Rising and falling edges of these signals track each other; tolerance of resulting
pulse durations is ± 2 ns, not ± 4 ns.
¶ This value holds true for zero or one wait state only.
* This parameter is not production tested.
ADDRESS
th(WEH-AV)
tsu(AV-WEL)
R/W
ta(RDAV)
ta(RDL-RD)
th(RDH-RD)
ten(WE-BUd)
tsu(RD-RDH)
th(WEH-WDV)
DATA
tsu(AV-RDL)
th(RDH-AV)
RD
td(RDH-WEL)
tw(RDH)
tsu(WDV-WEH)
td(WEH-RDL)
tw(WEL)
tw(RDL)
WE
tw(WEH)
STRB
NOTE A: All timings are for 0 wait states. However, external writes always require two cycles to prevent external bus conflicts. The above diagram
illustrates a one-cycle read and a two-cycle write and is not drawn to scale. All external writes immediately preceded by an external
read or immediately followed by an external read require three machine cycles.
Figure 7. Memory and Parallel I/O Interface Read and Write Timing
16
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• HOUSTON, TEXAS 77251--1443
SMJ320C50/SMQ320C50
DIGITAL SIGNAL PROCESSOR
SGUS020B -- JUNE 1996 -- REVISED SEPTEMBER 2001
Change in Address Bus Timing -- ns
MEMORY AND PARALLEL I/O INTERFACE WRITE (CONTINUED)
2
1.75
1.50
1.25
1
0.75
0.50
0.25
10
15
20
25
30
35
40
45
50
55
60
65
70
75
80
85
90
95
Change in Load Capacitance -- pF
Figure 8. Address Bus Timing Variation With Load Capacitance
POST OFFICE BOX 1443
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17
SMJ320C50/SMQ320C50
DIGITAL SIGNAL PROCESSOR
SGUS020B -- JUNE 1996 -- REVISED SEPTEMBER 2001
READY TIMING FOR EXTERNALLY GENERATED WAIT STATES
timing requirements
MIN
tsu(RY-COH)
Setup time, READY before CLKOUT1 rises
th(CO-RYH)
Hold time, READY after CLKOUT1 rises
tsu(RY-RDL)
Setup time, READY before RD falls
th(RDL-RY)
Hold time, READY after RD falls
tv(WEL-RY)
th(WEL-RY)
MAX
UNIT
10
ns
0
ns
10
ns
0
ns
Valid time, READY after WE falls
H -- 15
ns
Hold time, READY after WE falls
H+5
ns
CLKOUT1
tsu(RY-COH)
ADDRESS
th(CO-RYH)
READY
tsu(RY-RDL)
RD
th(RDL-RY)
Wait State
Generated
Internally
Wait State
Generated
by READY
Figure 9. Ready Timing for Externally Generated Wait States During an External Read Cycle
CLKOUT1
th(CO-RYH)
ADDRESS
tsu(RY-COH)
READY
tv(WEL-RY)
th(WEL-RY)
WE
Wait State Generated by READY
Figure 10. Ready Timing for Externally Generated Wait States During an External Write Cycle
POST OFFICE BOX 1443
• HOUSTON, TEXAS 77251--1443
19
SMJ320C50/SMQ320C50
DIGITAL SIGNAL PROCESSOR
SGUS020B -- JUNE 1996 -- REVISED SEPTEMBER 2001
RESET, INTERRUPT, AND BIO
timing requirements
MIN
†
MAX
UNIT
tsu(IN-COL)
Setup time, INT1--INT4, NMI, before CLKOUT1 low
15
ns
th(COL-IN)
Hold time, INT1--INT4, NMI, after CLKOUT1 low †
0
ns
tw(INL)SYN
Pulse duration, INT1--INT4, NMI low, synchronous
4H+15‡
ns
tw(INH)SYN
Pulse duration, INT1--INT4, NMI high, synchronous
2H+15‡*
ns
tw(INL)ASY
Pulse duration, INT1--INT4, NMI low, asynchronous
6H+15‡*
ns
tw(INH)ASY
Pulse duration, INT1--INT4, NMI high, asynchronous
4H+15‡*
ns
tsu(RS-X2L)
Setup time, RS before X2/CLKIN low
10
ns
tw(RSL)
Pulse duration, RS low
12H
ns
td(RSH)
Delay time, RS high to reset vector fetch
34H
ns
tw(BIL)SYN
Pulse duration, BIO low, synchronous
15
ns
tw(BIL)ASY
Pulse duration, BIO low, asynchronous
H+15*
ns
tsu(BI-COL)
Setup time, BIO before CLKOUT1 low
15
ns
th(COL-BI)
Hold time, BIO after CLKOUT1 low
0
ns
†
These parameters must be met to use the synchronous timings. Both reset and the interrupts can operate asynchronously. The pulse durations
require an extra half-cycle to assure internal synchronization.
‡ If in IDLE2, add 4H to these timings.
*This parameter is not production tested.
X2/CLKIN
RS
CLKOUT1
td(RSH)
tsu(RS-X2L)
tw(RSL)
tsu(BI-COL)
tsu(IN-COL)
tw(BIL)SYN
th(COL-BI)
BIO
A15--A0
INT4-INT1
tsu(IN-COL)
tw(INH)SYN
Figure 11. Reset, Interrupt, and BIO Timings
20
POST OFFICE BOX 1443
th(COL-IN)
tsu(IN-COL)
• HOUSTON, TEXAS 77251--1443
tw(INL)SYN
SMJ320C50/SMQ320C50
DIGITAL SIGNAL PROCESSOR
SGUS020B -- JUNE 1996 -- REVISED SEPTEMBER 2001
INSTRUCTION ACQUISITION (IAQ), INTERRUPT ACKNOWLEDGE (IACK),
EXTERNAL FLAG (XF), AND TOUT
switching characteristics over recommended operating conditions [H = 0.5tc(CO)]
PARAMETER
MIN
low†
MAX
UNIT
H--12‡
ns
tsu(AV-IQL)
Setup time, address valid before IAQ
th(IQL-AV)
Hold time, address valid after IAQ low
H--10‡
ns
tw(IQL)
Pulse duration, IAQ low
H--10‡
ns
td(CO-TU)
Delay time, CLKOUT1 falling to TOUT
tsu(AV-IKL)
Setup time, address valid before IACK low§
H--12‡
ns
th(IKH-AV)
Hold time, address valid after IACK high §
H--10‡
ns
tw(IKL)
Pulse duration, IACK low
H--10‡
ns
tw(TUH)
Pulse duration, TOUT high
2H--12
ns
td(CO-XFV)
Delay time, XF valid after CLKOUT1
--6
0
6
12
ns
ns
†
IAQ goes low during an instruction acquisition. It goes low only on the first cycle of the read when wait states are used. The falling edge should
be used to latch the valid address. The AVIS bit in the PMST register must be set to zero for the address to be valid when the instruction being
addressed resides in on-chip memory.
‡ Valid only if the external address reflects the current instruction activity (that is, code is executing on chip with no external bus cycles and AVIS
is on, or code is executing off-chip)
§ IACK goes low during the fetch of the first word of the interrupt vector. It goes low only on the first cycle of the read when wait states are used.
Address pins A1 -- A4 can be decoded at the falling edge to identify the interrupt being acknowledged. The AVIS bit in the PMST register must
be set to zero for the address to be valid when the vectors reside in on-chip memory.
th(IQL-AV)
ADDRESS
tsu(AV-IQL)
tw(IQL)
IAQ
tsu(AV-IKL)
th(IKH-AV)
IACK
tw(IKL)
STRB
CLKOUT1
td(CO-TU)
td(CO-TU)
td(CO-XFV)
XF
TOUT
tw(TUH)
NOTE: IAQ and IACK are not affected by wait states.
Figure 12. IAQ, IACK, and XF Timings Example With Two External Wait States
POST OFFICE BOX 1443
• HOUSTON, TEXAS 77251--1443
21
SMJ320C50/SMQ320C50
DIGITAL SIGNAL PROCESSOR
SGUS020B -- JUNE 1996 -- REVISED SEPTEMBER 2001
EXTERNAL DMA TIMING
switching characteristics over recommended operating conditions [H = 0.5tc(CO)] (see Note 3)
PARAMETER
MIN
MAX
†
UNIT
td(HOL-HAL)
Delay time, HOLD low to HOLDA low
4H
td(HOH-HAH)
Delay time, HOLD high before HOLDA high
2H
ns
ns
H--15‡*
ns
tdis(AZ-HAL)
Disable time, address in the high-impedance state before HOLDA low
ten(HAH-Ad)
Enable time, HOLDA high to address driven
td(XBL-IQL)
Delay time, XBR low to IAQ low
4H*
6H*
ns
td(XBH-IQH)
Delay time, XBR high to IAQ high
2H*
4H*
ns
td(XSL-RDV)
Delay time, read data valid after XSTRB low
40
ns
th(XSH-RD)
Hold time, read data after XSTRB high
H--5*
ns
0
ten(IQL-RDd)
Enable time, IAQ low to read data driven
tdis(W)
Disable time, XR/W low to data in the high-impedance state
ns
0*§
2H*
ns
0*
15*
ns
ns
ns
tdis(I-D)
Disable time, IAQ high to data in the high-impedance state
H*
ten(D-XRH)
Enable time, data from XR/W going high
4*
†
HOLD is not acknowledged until current external access request is complete.
‡ This parameter includes all memory control lines.
§ This parameter refers to the delay between the time the condition (IAQ = 0 and XR/W = 1) is satisfied and the time that the SMJ320C50x data
lines become valid.
* This parameter is not production tested.
NOTE 3: X preceding a name refers to the external drive of the signal.
timing requirements
MIN
MAX
UNIT
Delay time, HOLDA low to XBR low
0¶
ns
td(IQL-XSL)
Delay time, IAQ low to XSTRB low
0¶
ns
tsu(AV-XSL)
Setup time, Xaddress valid before XSTRB low
15
ns
tsu(DV-XSL)
Setup time, Xdata valid before XSTRB low
15
ns
th(XSL-D)
Hold time, Xdata hold after XSTRB low
15
ns
th(XSL-WA)
Hold time, write Xaddress hold after XSTRB low
15
ns
tw(XSL)
Pulse duration, XSTRB low
45
ns
tw(XSH)
Pulse duration, XSTRB high
45
ns
tsu(RW-XSL)
Setup time, R/W valid before XSTRB low
20
ns
th(XSH-RA)
Hold time, read Xaddress after XSTRB high
0
ns
td(HAL-XBL)
¶
XBR, XR/W, and XSTRB lines should be pulled up with a 10-kΩ resistor to assure that they are in an inactive (high) state during the transition
period between the SMJ320C50x driving them and the external circuit driving them.
NOTE 3. X preceding a name refers to the external drive of the signal.
22
POST OFFICE BOX 1443
• HOUSTON, TEXAS 77251--1443
SMJ320C50/SMQ320C50
DIGITAL SIGNAL PROCESSOR
SGUS020B -- JUNE 1996 -- REVISED SEPTEMBER 2001
EXTERNAL DMA TIMING (CONTINUED)
HOLD
td(HOH-HAH)
td(HOL-HAL)
HOLDA
Address
Bus/
Control
Signals† t
d(HAL-XBL)
ten(HAH-Ad)
tdis(AZ-HAL)
ten(I-B)
XBR
td(XBL-IQL)
td(XBH-IQH)
IAQ
td(IQL-XSL)
XSTRB
tsu(RW-XSL)
tw(XSH)
tw(XSL)
XR/W
tdis(W)
tsu(AV-XSL)
th(XSH-RD)
th(XSH-RA)
ten(IQL-RDd)
XADDRESS
td(XSL-RDV)
tsu(AV-XSL)
th(XSL-WA)
tdis(I-D)
DATA(RD)
ten(IQL-RDd)
th(XSL-D)
ten(D-XRH)
tsu(DV-XSL)
XDATA(WR)
†
A15--A0, PS, DS, IS, R/W, and BR timings are all included in timings referenced as address bus/control signals.
Figure 13. External DMA Timing
POST OFFICE BOX 1443
• HOUSTON, TEXAS 77251--1443
23
SMJ320C50/SMQ320C50
DIGITAL SIGNAL PROCESSOR
SGUS020B -- JUNE 1996 -- REVISED SEPTEMBER 2001
SERIAL-PORT RECEIVE
timing requirements
tc(SCK)
Cycle time, serial-port clock
tf(SCK)
Fall time, serial-port clock
tr(SCK)
Rise time, serial-port clock
tw(SCK)
Pulse duration, serial-port clock low/high
tsu(FS-CK)
MIN
MAX
5.2H
†
UNIT
ns
8*
ns
8*
ns
2.1H
ns
Setup time, FSR before CLKR falling edge
10
ns
th(CK-FS)
Hold time, FSR after CLKR falling edge
10
ns
tsu(DR-CK)
Setup time, DR before CLKR falling edge
10
ns
th(CK-DR)
Hold time, DR after CLKR falling edge
10
ns
†
The serial-port design is fully static and, therefore, can operate with tc(SCK) approaching ∞. It is characterized approaching an input frequency
of 0 Hz but tested at a much higher frequency to minimize test time.
* This parameter is not production tested.
tc(SCK)
tf(SCK)
tw(SCK)
CLKR
th(CK-FS)
tw(SCK)
tsu(FS-CK)
tr(SCK)
tsu(DR-CK)
FSR
th(CK-DR)
DR
Bit
1
2
NOTE A: Depending on whether information is sent in an 8-bit or 16-bit packet.
Figure 14. Serial-Port Receive Timing
24
POST OFFICE BOX 1443
• HOUSTON, TEXAS 77251--1443
7 or 15
(see Note A)
8 or 16
(see Note A)
SMJ320C50/SMQ320C50
DIGITAL SIGNAL PROCESSOR
SGUS020B -- JUNE 1996 -- REVISED SEPTEMBER 2001
SERIAL-PORT TRANSMIT, EXTERNAL CLOCKS AND EXTERNAL FRAMES
switching characteristics over recommended operating conditions (see Note 4)
PARAMETER
td(CXH-DXV)
Delay time, DX valid after CLKX high
tdis(CXH-DX)
Disable time, DX valid after CLKX high
th(CXH-DXV)
Hold time, DX valid after CLKX high
MIN
MAX
UNIT
25
ns
40*
ns
--5
ns
* This parameter is not production tested.
timing requirements
MIN
MAX
5.2H
†
UNIT
ns
tc(SCK)
Cycle time, serial-port clock
tf(SCK)
Fall time, serial-port clock
8*
ns
tr(SCK)
Rise time, serial-port clock
8*
ns
tw(SCK)
Pulse duration, serial-port clock low/high
td(CXH-FXH)
Delay time, FSX after CLKX high edge
th(CXL-FXL)
Hold time, FSX after CLKX falling edge
th(CXH-FXL)
2.1H
ns
2H--8
10
ns
2H--8‡*
Hold time, FSX after CLKX high edge
ns
ns
†
The serial-port design is fully static and therefore can operate with tc(SCK) approaching ∞. It is characterized approaching an input frequency of
0 Hz but tested at a much higher frequency to minimize test time.
‡ If the FSX pulse does not meet this specification, the first bit of serial data is driven on the DX pin until the falling edge of FSX. After the falling
edge of FSX, data is shifted out on the DX pin. The transmit-buffer-empty interrupt is generated when the th(FS) and th(FS)H specification is met.
NOTE 4: Internal clock with external FSX and vice versa are also allowable. However, FSX timings to CLKX are always defined depending on
the source of FSX, and CLKX timings are always dependent upon the source of CLKX. Specifically, the relationship of FSX to CLKX
is independent of the source of CLKX.
* This parameter is not production tested.
tc(SCK)
tf(SCK)
tw(SCK)
CLKX
td(CXH-FXH))
th(CXL-FXL)
tr(SCK)
th(CXH-FXL)
tw(SCK)
FSX
td(CXH-DXV)
tdis(CXH-DX)
th(CXH-DXV)
DX Bit
1
2
7 or 15
(see Note A)
8 or 16
(see Note A)
NOTE A: Depending on whether information is sent in an 8-bit or 16-bit packet
Figure 15. Serial-Port Transmit Timing of External Clocks and External Frames
POST OFFICE BOX 1443
• HOUSTON, TEXAS 77251--1443
25
SMJ320C50/SMQ320C50
DIGITAL SIGNAL PROCESSOR
SGUS020B -- JUNE 1996 -- REVISED SEPTEMBER 2001
SERIAL-PORT TRANSMIT, INTERNAL CLOCKS AND INTERNAL FRAMES
switching characteristics over recommended operating conditions [H = 0.5tc(CO)] (see Note 4)
PARAMETER
MIN
TYP
MAX
UNIT
td(CX-FX)
Delay time, CLKX rising to FSX
25
ns
td(CX-DX)
Delay time, CLKX rising to DX
25
ns
40*
ns
tdis(CX-DX)
Disable time, CLKX rising to DX
tc(SCK)
Cycle time, serial-port clock
tf(SCK)
Fall time, serial-port clock
tr(SCK)
Rise time, serial-port clock
tw(SCK)
Pulse duration, serial-port clock low/high
th(CXH-DXV)
Hold time, DX valid after CLKX high
8H
ns
5
ns
5
ns
4H -- 20
ns
-- 6
ns
* This parameter is not production tested.
NOTE 4: Internal clock with external FSX and vice versa are also allowable. However, FSX timings to CLKX are always defined depending on
the source of FSX, and CLKX timings are always dependent upon the source of CLKX. Specifically, the relationship of FSX to CLKX
is independent of the source of CLKX.
tc(SCK)
tf(SCK)
tw(SCK)
CLKX
td(CX-FX)
tw(SCK)
tr(SCK)
td(CX-FX)
td(CX-DX)
FSX
tdis(CX-DX)
th(CXH-DXV)
DX
Bit
1
2
7 or 15
(see Note A)
8 or 16
(see Note A)
NOTE A: Depending on whether information is sent in an 8-bit or 16-bit packet
Figure 16. Serial-Port Transmit Timing of Internal Clocks and Internal Frames
26
POST OFFICE BOX 1443
• HOUSTON, TEXAS 77251--1443
SMJ320C50/SMQ320C50
DIGITAL SIGNAL PROCESSOR
SGUS020B -- JUNE 1996 -- REVISED SEPTEMBER 2001
SERIAL-PORT RECEIVE TIMING IN TDM MODE
timing requirements
MIN
MAX
5.2H
†
UNIT
ns
tc(SCK)
Cycle time, serial-port clock
tf(SCK)
Fall time, serial-port clock
8*
ns
tr(SCK)
Rise time, serial-port clock
8*
ns
tw(SCK)
Pulse duration, serial-port clock low/high
tsu(TD-TCH)
Setup time, TDAT/TADD before TCLK rising
th(TCH-TD)
tsu(TA-TCH)
th(TCH-TA)
2.1H
ns
30
ns
Hold time, TDAT/TADD after TCLK rising
--3
ns
Setup time, TDAT/TADD before TCLK rising‡
20
ns
Hold time, TDAT/TADD after TCLK rising‡
-- 3
ns
10
ns
10
ns
edge§
tsu(TF-TCH)
Setup time, TRFM before TCLK rising
th(TCH-TF)
Hold time, TRFM after TCLK rising edge§
†
The serial-port design is fully static and therefore can operate with tc(SCK) approaching ∞. It is characterized approaching an input frequency of
0 Hz but tested at a much higher frequency to minimize test time.
‡ These parameters apply only to the first bits in the serial bit string.
§ TFRM timing and waveforms shown in Figure 17 are for external TFRM. TFRM also can be configured as internal. The TFRM internal case is
illustrated in the transmit timing diagram in Figure 18.
* This parameter is not production tested.
tf(SCK)
tw(SCK)
tr(SCK)
tw(SCK)
TCLK
tsu(TD-TCH)
tc(SCK)
th(TCH-TD)
B15
TDAT
B0
B14
B12
B8
B7
B2
B1
B0
th(TCH-TA)
th(TCH-TA)
tsu(TF-TCH)
TADD
B13
tsu(TA-TCH)
A0
A1
A2
A3
A7
th(TCH-TF)
TFRM
Figure 17. Serial-Port Receive Timing in TDM Mode
POST OFFICE BOX 1443
• HOUSTON, TEXAS 77251--1443
27
SMJ320C50/SMQ320C50
DIGITAL SIGNAL PROCESSOR
SGUS020B -- JUNE 1996 -- REVISED SEPTEMBER 2001
SERIAL-PORT TRANSMIT TIMING IN TDM MODE
switching characteristics over recommended operating conditions [H = 0.5tc(CO)]
PARAMETER
†
MIN
th(TCH-TDV)
Hold time, TDAT/TADD valid after TCLK rising
0
td(TCH-TFV)
Delay time, TFRM valid after TCLK rising†
H
td(TC-TDV)
Delay time, TCLK to valid TDAT/TADD
MAX
UNIT
ns
3H+10
ns
20
ns
TFRM timing and waveforms shown in Figure 18 are for internal TFRM. TFRM can also be configured as external, and the TFRM external case
is illustrated in the receive timing diagram in Figure 17.
timing requirements
MIN
TYP
MAX
5.2H
8H‡
§
ns
Fall time, serial-port clock
8*
ns
tr(SCK)
Rise time, serial-port clock
8*
ns
tw(SCK)
Pulse duration, serial-port clock low/high
tc(SCK)
Cycle time, serial-port clock
tf(SCK)
2.1H
UNIT
ns
‡
When SCK is generated internally.
The serial-port design is fully static and therefore can operate with tc(SCK) approaching ∞. It is characterized approaching an input frequency of
0 Hz but tested at a much higher frequency to minimize test time.
* This parameter is not production tested.
§
tf(SCK)
tw(SCK)
tw(SCK)
tr(SCK)
TCLK
tc(SCK)
B15
TDAT
B0
td(TCV-TDV)
B14
B13
B12
A2
A3
B8 B7
th(TCH-TDV)
td(TC-TDV)
th(TCH-TDV)
TADD
A1
td(TCH-TFV)
td(TCH-TFV)
A7
A0
TFRM
Figure 18. Serial-Port Transmit Timing in TDM Mode
28
POST OFFICE BOX 1443
• HOUSTON, TEXAS 77251--1443
B2
B1
B0
SMJ320C50/SMQ320C50
DIGITAL SIGNAL PROCESSOR
SGUS020B -- JUNE 1996 -- REVISED SEPTEMBER 2001
MECHANICAL DATA
HFG (S-CQFP-F132)
CERAMIC QUAD FLATPACK WITH TIE-BAR
0.960 (24,38)
TYP SQ
0.945 (24,00)
0.800 (20,32) TYP SQ
”A”
33
0.225 (5,72)
Tie Bar Width
0.175 (4,45)
1
34
132
1.210 (30,73)
TYP
2.015 (51,18)
1.990 (50,55)
100
2.025 (51,44) MAX
66
67
99
“B”
0.061 (1,55)
DIA TYP
0.059 (1,50)
132 ¢
“C”
0.013 (0,33)
0.006 (0,15)
Braze
0.040 (1,02)
0.030 (0,76)
0.025 (0,64)
DETAIL “A”
0.020 (0,51) MAX
0.014 (0,36)
0.002 (0,05)
0.010 (0,25)
0.005 (0,12)
DETAIL “B”
0.116 (2,95) MAX
DETAIL “C”
4040231-8/F 04/96
NOTES: B.
C.
D.
E.
F.
All linear dimensions are in inches (millimeters)..
This drawing is subject to change without notice.
Ceramic quad flatpack with flat leads brazed to non-conductive tie bar carrier.
This package can be hermetically sealed with a metal lid.
The terminals will be gold plated.
POST OFFICE BOX 1443
• HOUSTON, TEXAS 77251--1443
29
SMJ320C50/SMQ320C50
DIGITAL SIGNAL PROCESSOR
SGUS020B -- JUNE 1996 -- REVISED SEPTEMBER 2001
MECHANICAL DATA
GFA (S-CPGA-P141)
CERAMIC PIN GRID ARRAY PACKAGE
1.080 (27,43)
SQ
1.040 (26,42)
0.900 (22,86) TYP
0.100 (2,54) TYP
0.050 (1,27) TYP
W
V
U
T
R
P
N
M
L
K
J
H
G
F
E
D
C
B
A
2
0.026 (0,66)
0.006 (0,15)
0.145 (3,68)
0.105 (2,67)
1
4
3
6
5
8
7
10
9
12
11
14
13
18
16
15
17
19
0.034 (0,86) TYP
0.022 (0,56)
0.016 (0,41)
0.140 (3,56)
DIA TYP
0.120 (3,05)
0.048 (1,22) DIA TYP
4 Places
4040133/D 04/96
NOTES: A. All linear dimensions are in inches (millimeters).
B. This drawing is subject to change without notice.
C. Falls within JEDEC MO-128
30
POST OFFICE BOX 1443
• HOUSTON, TEXAS 77251--1443
SMJ320C50/SMQ320C50
DIGITAL SIGNAL PROCESSOR
SGUS020B -- JUNE 1996 -- REVISED SEPTEMBER 2001
MECHANICAL DATA
PQ (S-PQFP-G***)
PLASTIC QUAD FLATPACK
100 LEAD SHOWN
13
1 100
89
14
88
0.012 (0,30)
0.008 (0,20)
0.006 (0,15) M
”D3” SQ
0.025 (0,635)
0.006 (0,16) NOM
64
38
39
0.150 (3,81)
0.130 (3,30)
63
Gage Plane
”D1” SQ
”D” SQ
0.010 (0,25)
0.020 (0,51) MIN
”D2” SQ
0°--8°
0.046 (1,17)
0.036 (0,91)
Seating Plane
0.004 (0,10)
0.180 (4,57) MAX
DIM
”D”
”D1”
”D2”
”D3”
LEADS ***
100
132
MAX
0.890 (22,61)
1.090 (27,69)
MIN
0.870 (22,10)
1.070 (27,18)
MAX
0.766 (19,46)
0.966 (24,54)
MIN
0.734 (18,64)
0.934 (23,72)
MAX
0.912 (23,16)
1.112 (28,25)
MIN
0.888 (22,56)
1.088 (27,64)
NOM
0.600 (15,24)
0.800 (20,32)
4040045/C 11/95
NOTES: A. All linear dimensions are in inches (millimeters).
B. This drawing is subject to change without notice.
C. Falls within JEDEC MO-069
POST OFFICE BOX 1443
• HOUSTON, TEXAS 77251--1443
31
PACKAGE OPTION ADDENDUM
www.ti.com
27-Apr-2018
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (°C)
Device Marking
(4/5)
5962-9455803QXA
NRND
CPGA
GFA
141
1
TBD
Call TI
N / A for Pkg Type
-55 to 125
5962-9455803QX
A
SMJ320C50GFAM5
0
5962-9455803QYA
NRND
CFP
HFG
132
1
TBD
Call TI
N / A for Pkg Type
-55 to 125
5962-9455803QY
A
SMJ320C50HFGM5
0
5962-9455804NZB
NRND
BQFP
PQ
132
1
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-4-260C-72 HR
-55 to 125
5962-9455804NZ
B
SMQ320C50PQM66
5962-9455804QXA
NRND
CPGA
GFA
141
1
TBD
Call TI
Call TI
-55 to 125
5962-9455804QYA
NRND
CFP
HFG
132
1
TBD
Call TI
Call TI
-55 to 125
SMJ320C50GFAM50
NRND
CPGA
GFA
141
1
TBD
Call TI
N / A for Pkg Type
-55 to 125
5962-9455803QX
A
SMJ320C50GFAM5
0
SMJ320C50GFAM66
NRND
CPGA
GFA
141
1
TBD
Call TI
N / A for Pkg Type
-55 to 125
5962-9455804QX
A
SMJ320C50GFAM6
6
SMJ320C50HFGM50
NRND
CFP
HFG
132
1
TBD
Call TI
N / A for Pkg Type
-55 to 125
5962-9455803QY
A
SMJ320C50HFGM5
0
SMJ320C50HFGM66
NRND
CFP
HFG
132
1
TBD
Call TI
N / A for Pkg Type
-55 to 125
5962-9455804QY
A
SMJ320C50HFGM6
6
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
27-Apr-2018
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
MECHANICAL DATA
MCPG015B – FEBRUARY 1996 – REVISED DECEMBER 2001
GFA (S-CPGA-P141)
CERAMIC PIN GRID ARRAY
1.080 (27,43)
SQ
1.040 (26,42)
0.900 (22,86) TYP
0.100 (2,54) TYP
0.050 (1,27) TYP
W
V
U
T
R
P
N
M
L
K
J
H
G
F
E
D
A1 Corner
C
B
A
1
3
2
0.026 (0,66)
0.006 (0,15)
5
4
0.145 (3,68)
0.105 (2,67)
7
6
9
8
11
10
13
12
15
14
17
16
19
18
Bottom View
0.034 (0,86) TYP
0.022 (0,56)
0.016 (0,41)
0.140 (3,56)
DIA TYP
0.120 (3,05)
0.048 (1,22) DIA TYP
4 Places
4040133/E 11/01
NOTES: A.
B.
C.
D.
All linear dimensions are in inches (millimeters).
This drawing is subject to change without notice.
Index mark can appear on top or bottom, depending on package vendor.
Pins are located within 0.010 (0,25) diameter of true position relative to
each other at maximum material condition and within 0.030 (0,76) diameter
relative to the edge of the ceramic.
E. This package can be hermetically sealed with metal lids or with ceramic lids using glass frit.
F. The pins can be gold-plated or solder-dipped.
G. Falls within JEDEC MO-128AB
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
1
MECHANICAL DATA
MBQF001A – NOVEMBER 1995
PQ (S-PQFP-G***)
PLASTIC QUAD FLATPACK
100 LEAD SHOWN
13
89
1 100
14
88
0.012 (0,30)
0.008 (0,20)
0.006 (0,15) M
”D3” SQ
0.025 (0,635)
0.006 (0,16) NOM
64
38
0.150 (3,81)
0.130 (3,30)
39
63
Gage Plane
”D1” SQ
”D” SQ
0.010 (0,25)
0.020 (0,51) MIN
”D2” SQ
0°– 8°
0.046 (1,17)
0.036 (0,91)
Seating Plane
0.004 (0,10)
0.180 (4,57) MAX
LEADS ***
100
132
MAX
0.890 (22,61)
1.090 (27,69)
MIN
0.870 (22,10)
1.070 (27,18)
MAX
0.766 (19,46)
0.966 (24,54)
MIN
0.734 (18,64)
0.934 (23,72)
MAX
0.912 (23,16)
1.112 (28,25)
MIN
0.888 (22,56)
1.088 (27,64)
NOM
0.600 (15,24)
0.800 (20,32)
DIM
”D”
”D1”
”D2”
”D3”
4040045 / C 11/95
NOTES: A. All linear dimensions are in inches (millimeters).
B. This drawing is subject to change without notice.
C. Falls within JEDEC MO-069
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
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