Texas Instruments | SM320C6201B, SMJ320C6201B Digital Signal Processor (Rev. B) | Datasheet | Texas Instruments SM320C6201B, SMJ320C6201B Digital Signal Processor (Rev. B) Datasheet

Texas Instruments SM320C6201B, SMJ320C6201B Digital Signal Processor (Rev. B) Datasheet
SM320C6201B, SMJ320C6201B
DIGITAL SIGNAL PROCESSOR
SGUS031B -- APRIL 2000 -- REVISED AUGUST 2001
D Highest Performance Fixed-Point Digital
D
D
D
D
D
D
Signal Processor (DSP) SM/SMJ320C6201B
-- 5-, 6.7-ns Instruction Cycle Time
-- 150 and 200-MHz Clock Rate
-- Eight 32-Bit Instructions/Cycle
-- 1200 and 1600 MIPS
VelociTI™ Advanced Very Long Instruction
Word (VLIW) C62x™ CPU Core
-- Eight Independent Functional Units:
-- Six ALUs (32-/40-Bit)
-- Two 16-Bit Multipliers (32-Bit Results)
-- Load-Store Architecture With 32 32-Bit
General-Purpose Registers
-- Instruction Packing Reduces Code Size
-- All Instructions Conditional
Instruction Set Features
-- Byte-Addressable (8-, 16-, 32-Bit Data)
-- 32-Bit Address Range
-- 8-Bit Overflow Protection
-- Saturation
-- Bit-Field Extract, Set, Clear
-- Bit-Counting
-- Normalization
1M-Bit On-Chip SRAM
-- 512K-Bit Internal Program/Cache
(16K 32-Bit Instructions)
-- 512K-Bit Dual-Access Internal Data
(64K Bytes) Organized as Two Blocks for
Improved Concurrency
32-Bit External Memory Interface (EMIF)
-- Glueless Interface to Synchronous
Memories: SDRAM and SBSRAM
-- Glueless Interface to Asynchronous
Memories: SRAM and EPROM
Four-Channel Bootloading
Direct-Memory-Access (DMA) Controller
with an Auxiliary Channel
16-Bit Host-Port Interface (HPI)
-- Access to Entire Memory Map
GLP
429-PIN BALL GRID ARRAY (BGA) PACKAGE
(BOTTOM VIEW)
AA
Y
W
V
U
T
R
P
N
M
L
K
J
H
G
F
E
D
C
B
A
3
1
2
5
4
9
7
6
8
11
10
13
12
17
15
14
16
19
18
21
20
D Two Multichannel Buffered Serial Ports
D
D
D
D
D
D
(McBSPs)
-- Direct Interface to T1/E1, MVIP, SCSA
Framers
-- ST-Bus-Switching Compatible
-- Up to 256 Channels Each
-- AC97-Compatible
-- Serial Peripheral Interface (SPI)
Compatible (Motorola™)
Two 32-Bit General-Purpose Timers
Flexible Phase-Locked Loop (PLL) Clock
Generator
IEEE-1149.1 (JTAG†) Boundary-Scan
Compatible
429-Pin BGA Package (GLP Suffix)
CMOS Technology
-- 0.18-μm/5-Level Metal Process
3.3-V I/Os, 1.8-V Internal
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
C62x and VelociTI are trademarks of Texas Instruments Incorporated.
Motorola is a trademark of Motorola, Inc.
† IEEE Standard 1149.1-1990 Standard-Test-Access Port and Boundary Scan Architecture.
Copyright © 2001, Texas Instruments Incorporated
UNLESS OTHERWISE NOTED this document contains PRODUCTION
DATA information current as of publication date. Products conform to
specifications per the terms of Texas Instruments standard warranty.
Production processing does not necessarily include testing of all
parameters.
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unless otherwise noted. On all other products, production
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1
SM320C6201B, SMJ320C6201B
DIGITAL SIGNAL PROCESSOR
SGUS031B -- APRIL 2000 -- REVISED AUGUST 2001
Table of Contents
description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
device characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
functional block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
CPU description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
signal groups description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
signal descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
development support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
device and development support nomenclature . . . . . . . . . 23
documentation support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
clock PLL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
power-supply sequencing . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
absolute maximum ratings over operating case
temperature ranges . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
recommended operating conditions . . . . . . . . . . . . . . . . . . . 28
electrical characteristics over recommended ranges of
supply voltage and operating case temperature . . . . 29
parameter measurement information . . . . . . . . . . . . . . . 30
signal transition levels . . . . . . . . . . . . . . . . . . . . . . . . . . . .
input and output clocks . . . . . . . . . . . . . . . . . . . . . . . . . . .
asynchronous memory timing . . . . . . . . . . . . . . . . . . . . .
synchronous-burst memory timing . . . . . . . . . . . . . . . . .
synchronous DRAM timing . . . . . . . . . . . . . . . . . . . . . . .
HOLD/HOLDA timing . . . . . . . . . . . . . . . . . . . . . . . . . . . .
reset timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
external interrupt timing . . . . . . . . . . . . . . . . . . . . . . . . . .
host-port interface timing . . . . . . . . . . . . . . . . . . . . . . . . .
multichannel buffered serial port timing . . . . . . . . . . . . .
DMAC, timer, power-down timing . . . . . . . . . . . . . . . . . .
JTAG test-port timing . . . . . . . . . . . . . . . . . . . . . . . . . . . .
mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
30
31
34
36
40
44
45
47
48
51
59
60
61
description
The 320C6201B DSP is a member of the fixed-point DSP family in the 320C6000 platform. The
SM/SMJ320C6201B (C6201B) device is based on the high-performance, advanced VelociTI
very-long-instruction-word (VLIW) architecture developed by Texas Instruments (TI™), making this DSP an
excellent choice for multichannel and multifunction applications. With performance of up to 1600 million
instructions per second (MIPS) at a clock rate of 200 MHz, the C6201B offers cost-effective solutions to
high-performance DSP programming challenges. The C6201B is a newer revision of the C6201. The C6201B
DSP possesses the operational flexibility of high-speed controllers and the numerical capability of array
processors. This processor has 32 general-purpose registers of 32-bit word length and eight highly independent
functional units. The eight functional units provide six arithmetic logic units (ALUs) for a high degree of
parallelism and two 16-bit multipliers for a 32-bit result. The C6201B can produce two multiply-accumulates
(MACs) per cycle—for a total of 400 million MACs per second (MMACS). The C6201B DSP also has
application-specific hardware logic, on-chip memory, and additional on-chip peripherals.
The C6201B includes a large bank of on-chip memory and has a powerful and diverse set of peripherals.
Program memory consists of a 64K-byte block that is user-configurable as cache or memory-mapped program
space. Data memory of the C6201B consists of two 32K-byte blocks of RAM for improved concurrency. The
peripheral set includes two multichannel buffered serial ports (McBSPs), two general-purpose timers, a
host-port interface (HPI), and a glueless external memory interface (EMIF) capable of interfacing to SDRAM
or SBSRAM and asynchronous peripherals.
The C6201B has a complete set of development tools which includes: a new C compiler, a third-party Ada 95
compiler, an assembly optimizer to simplify programming and scheduling, and a Windows™ debugger interface
for visibility into source code execution.
TI is a trademark of Texas Instruments Incorporated.
Windows is a registered trademark of the Microsoft Corporation.
2
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DIGITAL SIGNAL PROCESSOR
SGUS031B -- APRIL 2000 -- REVISED AUGUST 2001
device characteristics
Table 1 provides an overview of the C62x DSP. The table shows significant features of each device, including
the capacity of on-chip RAM, the peripherals, the execution time, and the package type with pin count.
Table 1. Characteristics of the C6201B Processor
CHARACTERISTICS
DESCRIPTION
Device Number
320C6201B
On-Chip Memory
512-Kbit Program Memory
512-Kbit Data Memory (organized as two blocks)
Peripherals
2 Multichannel Buffered Serial Ports (McBSPs)
2 General-Purpose Timers
Host-Port Interface (HPI)
External Memory Interface (EMIF)
Cycle Time
6.7 ns (320C6201B 150 MHz),
5 ns (320C6201B 200 MHz)
Package Type
27 mm × 27 mm, 429-Pin Ceramic D-BGA (GLP)
Nominal Voltage
1.8 V Core
3.3 V I/O
functional block diagram
Timers
Interrupt Selector
McBSPs
HPI Control
DMA Control
EMIF Control
Peripheral
Bus
Controller
Host-Port Interface
DMA
Controller
Data Memory
Data Memory
Controller
PLL
CPU
EMIF
Power
Down
Program Memory Controller
BootConfig.
Program Memory/Cache
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SM320C6201B, SMJ320C6201B
DIGITAL SIGNAL PROCESSOR
SGUS031B -- APRIL 2000 -- REVISED AUGUST 2001
CPU description
The CPU fetches VelociTI advanced very-long instruction words (VLIW) (256 bits wide) to supply up to eight
32-bit instructions to the eight functional units during every clock cycle. The VelociTI VLIW architecture features
controls by which all eight units do not have to be supplied with instructions if they are not ready to execute. The
first bit of every 32-bit instruction determines if the next instruction belongs to the same execute packet as the
previous instruction, or whether it should be executed in the following clock as a part of the next execute packet.
Fetch packets are always 256 bits wide; however, the execute packets can vary in size. The variable-length
execute packets are a key memory-saving feature, distinguishing the C62x CPU from other VLIW architectures.
The CPU features two sets of functional units. Each set contains four units and a register file. One set contains
functional units .L1, .S1, .M1, and .D1; the other set contains units .D2, .M2, .S2, and .L2. The two register files
each contain 16 32-bit registers for a total of 32 general-purpose registers. The two sets of functional units, along
with two register files, compose sides A and B of the CPU (see Figure 1 and Figure 2). The four functional units
on each side of the CPU can freely share the 16 registers belonging to that side. Additionally, each side features
a single data bus connected to all the registers on the other side, by which the two sets of functional units can
access data from the register files on the opposite side. While register access by functional units on the same
side of the CPU as the register file can service all the units in a single clock cycle, register access using the
register file across the CPU supports one read and one write per cycle.
Another key feature of the C62x CPU is the load/store architecture, where all instructions operate on registers
(as opposed to data in memory). Two sets of data-addressing units (.D1 and .D2) are responsible for all data
transfers between the register files and the memory. The data address driven by the .D units allows data
addresses generated from one register file to be used to load or store data to or from the other register file. The
C62x CPU supports a variety of indirect addressing modes using either linear- or circular-addressing modes
with 5- or 15-bit offsets. All instructions are conditional, and most can access any one of the 32 registers. Some
registers, however, are singled out to support specific addressing or to hold the condition for conditional
instructions (if the condition is not automatically “true”). The two .M functional units are dedicated for multiplies.
The two .S and .L functional units perform a general set of arithmetic, logical, and branch functions with results
available every clock cycle.
The processing flow begins when a 256-bit-wide instruction fetch packet is fetched from a program memory.
The 32-bit instructions destined for the individual functional units are “linked” together by “1” bits in the least
significant bit (LSB) position of the instructions. The instructions that are “chained” together for simultaneous
execution (up to eight in total) compose an execute packet. A “0” in the LSB of an instruction breaks the chain,
effectively placing the instructions that follow it in the next execute packet. If an execute packet crosses the fetch
packet boundary (256 bits wide), the assembler places it in the next fetch packet, while the remainder of the
current fetch packet is padded with NOP instructions. The number of execute packets within a fetch packet can
vary from one to eight. Execute packets are dispatched to their respective functional units at the rate of one per
clock cycle and the next 256-bit fetch packet is not fetched until all the execute packets from the current fetch
packet have been dispatched. After decoding, the instructions simultaneously drive all active functional units
for a maximum execution rate of eight instructions every clock cycle. While most results are stored in 32-bit
registers, they can be subsequently moved to memory as bytes or half-words as well. All load and store
instructions are byte-, half-word, or word-addressable.
4
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SM320C6201B, SMJ320C6201B
DIGITAL SIGNAL PROCESSOR
SGUS031B -- APRIL 2000 -- REVISED AUGUST 2001
CPU description (continued)
Program Memory
32-Bit Address
256-Bit Data
C62x CPU
Program Fetch
Control
Registers
Instruction Dispatch
Instruction Decode
External Memory
Interface
Data Path A
Data Path B
Register File A
Register File B
Control
Logic
Test
.L1
.S1 .M1 .D1
.D2
.M2 .S2
Data Memory
32-Bit Address
8-, 16-, 32-Bit Data
.L2
Emulation
Interrupts
Additional
Peripherals:
Timers,
Serial Ports,
etc.
Figure 1. 320C62x CPU Block Diagram
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SM320C6201B, SMJ320C6201B
DIGITAL SIGNAL PROCESSOR
SGUS031B -- APRIL 2000 -- REVISED AUGUST 2001
CPU description (continued)
src1
.L1
src2
dst
long dst
long src
ST1
long src
long dst
dst
.S1
src1
Data Path A
8
8
32
8
Register
File A
(A0--A15)
src2
.M1
dst
src1
src2
LD1
DA1
.D1
dst
src1
src2
2X
1X
DA2
.D2
src2
src1
dst
LD2
src2
.M2
src1
dst
src2
Data Path B
src1
dst
long dst
long src
Register
File B
(B0--B15)
.S2
ST2
long src
long dst
dst
.L2
src2
8
32
8
8
src1
Control
Register
File
Figure 2. 320C62x CPU Data Paths
6
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SM320C6201B, SMJ320C6201B
DIGITAL SIGNAL PROCESSOR
SGUS031B -- APRIL 2000 -- REVISED AUGUST 2001
signal groups description
CLKIN
CLKOUT2
CLKOUT1
CLKMODE1
CLKMODE0
PLLFREQ3
PLLFREQ2
PLLFREQ1
PLLV
PLLG
PLLF
Boot Mode
BOOTMODE4
BOOTMODE3
BOOTMODE2
BOOTMODE1
BOOTMODE0
Reset and
Interrupts
RESET
NMI
EXT_INT7
EXT_INT6
EXT_INT5
EXT_INT4
IACK
INUM3
INUM2
INUM1
INUM0
Little ENDIAN
Big ENDIAN
LENDIAN
Clock/PLL
TMS
TDO
TDI
TCK
TRST
EMU1
EMU0
JTAG
Emulation
RSV9
RSV8
RSV7
RSV6
RSV5
RSV4
RSV3
RSV2
RSV1
RSV0
DMA Status
DMAC3
DMAC2
DMAC1
DMAC0
Power-Down
Status
PD
Reserved
Control/Status
HD[15:0]
HCNTL0
HCNTL1
16
Data
HPI
(Host-Port Interface)
Register Select
Control
HHWIL
HBE1
HBE0
Half-Word/Byte
Select
HAS
HR/W
HCS
HDS1
HDS2
HRDY
HINT
Figure 3. CPU and Peripheral Signals
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SM320C6201B, SMJ320C6201B
DIGITAL SIGNAL PROCESSOR
SGUS031B -- APRIL 2000 -- REVISED AUGUST 2001
signal groups description (continued)
ED[31:0]
32
CE3
CE2
CE1
CE0
EA[21:2]
BE3
BE2
BE1
BE0
HOLD
HOLDA
Data
Asynchronous
Memory
Control
Memory Map
Space Select
20
Word Address
ARE
AOE
AWE
ARDY
SBSRAM
Control
SSADS
SSOE
SSWE
SSCLK
SDRAM
Control
SDA10
SDRAS
SDCAS
SDWE
SDCLK
Byte Enables
HOLD/
HOLDA
EMIF
(External Memory Interface)
TOUT1
TINP1
Timer 1
Timer 0
TOUT0
TINP0
Timers
McBSP1
McBSP0
CLKX1
FSX1
DX1
Transmit
Transmit
CLKX0
FSX0
DX0
CLKR1
FSR1
DR1
Receive
Receive
CLKR0
FSR0
DR0
CLKS1
Clock
Clock
CLKS0
McBSPs
(Multichannel Buffered Serial Ports)
Figure 4. Peripheral Signals
8
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SM320C6201B, SMJ320C6201B
DIGITAL SIGNAL PROCESSOR
SGUS031B -- APRIL 2000 -- REVISED AUGUST 2001
Signal Descriptions
SIGNAL
NAME
NO.
DESCRIPTION
TYPE†
CLOCK/PLL
CLKIN
A14
I
Clock Input
CLKOUT1
Y6
O
Clock output at full device speed
CLKOUT2
V9
O
Clock output at half of device speed
CLKMODE1
B17
CLKMODE0
C17
PLLFREQ3
C13
PLLFREQ2
G11
PLLFREQ1
F11
PLLV‡
D12
A§
PLL analog VCC connection for the low-pass filter
PLLG‡
G10
A§
PLL analog GND connection for the low-pass filter
PLLF
C12
A§
PLL low-pass filter connection to external components and a bypass capacitor
TMS
K19
I
TDO
R12
O/Z
TDI
R13
I
JTAG test port data in (features an internal pull-up)
TCK
M20
I
JTAG test port clock
TRST
N18
I
JTAG test port reset (features an internal pull-down)
EMU1
R20
I/O/Z
Emulation pin 1, pull-up with a dedicated 20-kΩ resistor
EMU0
T18
I/O/Z
Emulation pin 0, pull-up with a dedicated 20-kΩ resistor
RESET
J20
I
Device reset
NMI
K21
I
Nonmaskable interrupt
• Edge-driven (rising edge)
EXT_INT7
R16
EXT_INT6
P20
EXT_INT5
R15
I
External interrupts
• Edge-driven (rising edge)
EXT_INT4
R18
IACK
R11
O
Interrupt acknowledge for all active interrupts serviced by the CPU
INUM3
T19
INUM2
T20
INUM1
T14
O
INUM0
T16
Active interrupt identification number
• Valid during IACK for all active interrupts (not just external)
• Encoding order follows the interrupt service fetch packet ordering
I
If high, selects little-endian byte/half-word addressing order within a word
If low, selects big-endian addressing
I
Clock mode select
•
Selects whether the output clock frequency = input clock freq x4 or x1
PLL frequency range (3, 2, and 1)
I
•
The target range for CLKOUT1 frequency is determined by the 3-bit value of the PLLFREQ pins.
JTAG EMULATION
JTAG test port mode select (features an internal pull-up)
JTAG test port data out
RESET AND INTERRUPTS
LITTLE ENDIAN/BIG ENDIAN
LENDIAN
G20
POWER DOWN STATUS
PD
D19
O
Power-down mode 2 or 3 (active if high)
†
I = Input, O = Output, Z = High Impedance, S = Supply Voltage, GND = Ground
‡ PLLV and PLLG signals are not part of external voltage supply or ground. See the CLOCK/PLL documentation for information on how to connect
those pins.
§ A = Analog Signal (PLL Filter)
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SM320C6201B, SMJ320C6201B
DIGITAL SIGNAL PROCESSOR
SGUS031B -- APRIL 2000 -- REVISED AUGUST 2001
Signal Descriptions (Continued)
SIGNAL
NAME
NO.
DESCRIPTION
TYPE†
HOST PORT INTERFACE (HPI)
HINT
H2
O/Z
HCNTL1
J6
I
Host control -- selects between control, address or data registers
HCNTL0
H6
I
Host control -- selects between control, address or data registers
HHWIL
E4
I
Host halfword select -- first or second halfword (not necessarily high or low order)
HBE1
G6
I
Host byte select within word or half-word
HBE0
F6
I
Host byte select within word or half-word
HR/W
D4
I
Host read or write select
HD15
D11
HD14
B11
HD13
A11
HD12
G9
HD11
D10
HD10
A10
HD9
C10
HD8
B9
HD7
F9
HD6
C9
HD5
A9
HD4
B8
HD3
D9
HD2
D8
I/O/Z
Host interrupt (from DSP to host)
Host port data ((used
sed for transfer of data,
data address and control)
HD1
B7
HD0
C7
HAS
L6
I
Host address strobe
HCS
C5
I
Host chip select
HDS1
C4
I
Host data strobe 1
HDS2
K6
I
Host data strobe 2
HRDY
H3
O
Host ready (from DSP to host)
BOOT MODE
†
BOOTMODE4
B16
BOOTMODE3
G14
BOOTMODE2
F15
BOOTMODE1
C18
BOOTMODE0
D17
I
Boot mode
I = Input, O = Output, Z = High Impedance, S = Supply Voltage, GND = Ground
10
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DIGITAL SIGNAL PROCESSOR
SGUS031B -- APRIL 2000 -- REVISED AUGUST 2001
Signal Descriptions (Continued)
SIGNAL
NAME
NO.
DESCRIPTION
TYPE†
EMIF -- CONTROL SIGNALS COMMON TO ALL TYPES OF MEMORY
CE3
Y5
O/Z
CE2
V3
O/Z
Memory space enables
CE1
T6
O/Z
•
Enabled by bits 24 and 25 of the word address
CE0
U2
O/Z
•
Only one asserted during any external data access
BE3
R8
O/Z
Byte enable control
BE2
T3
O/Z
•
Decoded from the two lowest bits of the internal address
BE1
T2
O/Z
•
Byte write enables for most types of memory
BE0
R2
O/Z
•
Can be directly connected to SDRAM read and write mask signal (SDQM)
EA21
L4
EA20
L3
EA19
J2
EA18
J1
EA17
K1
EA16
K2
EA15
L2
EMIF -- ADDRESS
†
EA14
L1
EA13
M1
EA12
M2
EA11
M6
EA10
N4
EA9
N1
EA8
N2
EA7
N6
EA6
P4
EA5
P3
EA4
P2
EA3
P1
EA2
P6
O/Z
External address (word address)
I = Input, O = Output, Z = High Impedance, S = Supply Voltage, GND = Ground
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DIGITAL SIGNAL PROCESSOR
SGUS031B -- APRIL 2000 -- REVISED AUGUST 2001
Signal Descriptions (Continued)
SIGNAL
NAME
NO.
DESCRIPTION
TYPE†
EMIF -- DATA
ED31
U18
ED30
U20
ED29
T15
ED28
V18
ED27
V17
ED26
V16
ED25
T12
ED24
W17
ED23
T13
ED22
Y17
ED21
T11
ED20
Y16
ED19
W15
ED18
V14
ED17
Y15
ED16
R9
ED15
Y14
ED14
V13
ED13
AA13
ED12
T10
ED11
Y13
ED10
W12
ED9
Y12
ED8
Y11
ED7
V10
ED6
AA10
ED5
Y10
ED4
W10
ED3
Y9
ED2
AA9
ED1
Y8
ED0
W9
I/O/Z
External data
EMIF -- ASYNCHRONOUS MEMORY CONTROL
†
ARE
R7
O/Z
Asynchronous memory read enable
AOE
T7
O/Z
Asynchronous memory output enable
AWE
V5
O/Z
Asynchronous memory write enable
ARDY
R4
I
Asynchronous memory ready input
I = Input, O = Output, Z = High Impedance, S = Supply Voltage, GND = Ground
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DIGITAL SIGNAL PROCESSOR
SGUS031B -- APRIL 2000 -- REVISED AUGUST 2001
Signal Descriptions (Continued)
SIGNAL
NAME
NO.
DESCRIPTION
TYPE†
EMIF -- SYNCHRONOUS BURST SRAM CONTROL
SSADS
V8
O/Z
SBSRAM address strobe
SSOE
W7
O/Z
SBSRAM output enable
SSWE
Y7
O/Z
SBSRAM write enable
SSCLK
AA8
O/Z
SBSRAM clock
EMIF -- SYNCHRONOUS DRAM CONTROL
SDA10
V7
O/Z
SDRAM address 10 (separate for deactivate command)
SDRAS
V6
O/Z
SDRAM row address strobe
SDCAS
W5
O/Z
SDRAM column address strobe
SDWE
T8
O/Z
SDRAM write enable
SDCLK
T9
O/Z
SDRAM clock
HOLD
R6
I
Hold request from the host
HOLDA
B15
O
Hold request acknowledge to the host
TOUT1
G2
O
Timer 1 or general-purpose output
EMIF -- BUS ARBITRATION
TIMERS
TINP1
K3
I
Timer 1 or general-purpose input
TOUT0
M18
O
Timer 0 or general-purpose output
TINP0
J18
I
Timer 0 or general-purpose input
DMAC3
E18
DMA ACTION COMPLETE
DMAC2
F19
DMAC1
E20
DMAC0
G16
CLKS1
CLKR1
O
DMA action complete
F4
I
External clock source (as opposed to internal)
H4
I/O/Z
Receive clock
CLKX1
J4
I/O/Z
Transmit clock
DR1
E2
I
Receive data
DX1
G4
O/Z
Transmit data
FSR1
F3
I/O/Z
Receive frame sync
FSX1
F2
I/O/Z
Transmit frame sync
MULTICHANNEL BUFFERED SERIAL PORT 1 (McBSP1)
†
I = Input, O = Output, Z = High Impedance, S = Supply Voltage, GND = Ground
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DIGITAL SIGNAL PROCESSOR
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Signal Descriptions (Continued)
SIGNAL
NAME
NO.
DESCRIPTION
TYPE†
MULTICHANNEL BUFFERED SERIAL PORT 0 (McBSP0)
CLKS0
K18
I
CLKR0
L21
I/O/Z
External clock source (as opposed to internal)
Receive clock
CLKX0
K20
I/O/Z
Transmit clock
DR0
J21
I
Receive data
DX0
M21
O/Z
Transmit data
FSR0
P16
I/O/Z
Receive frame sync
FSX0
N16
I/O/Z
Transmit frame sync
RSV0
N21
I
Reserved for testing, pull-up with a dedicated 20-kΩ resistor
RSV1
K16
I
Reserved for testing, pull-up with a dedicated 20-kΩ resistor
RSV2
B13
I
Reserved for testing, pull-up with a dedicated 20-kΩ resistor
RSV3
B14
I
Reserved for testing, pull-up with a dedicated 20-kΩ resistor
RSV4
F13
I
Reserved for testing, pull-down with a dedicated 20-kΩ resistor
RSV5
C15
O
Reserved (leave unconnected, do not connect to power or ground)
RSV6
F7
I
Reserved for testing, pull-up with a dedicated 20-kΩ resistor
RSV7
D7
I
Reserved for testing, pull-up with a dedicated 20-kΩ resistor
RSV8
B5
I
Reserved for testing, pull-up with a dedicated 20-kΩ resistor
RSV9
F16
O
Reserved (leave unconnected, do not connect to power or ground)
RESERVED FOR TEST
SUPPLY VOLTAGE PINS
C14
C8
E19
E3
H11
H13
H9
J10
J12
J14
DVDD
J19
S
3.3-V
3.3
V supply voltage
J3
J8
K11
K13
K15
K7
K9
L10
L12
L14
†
I = Input, O = Output, Z = High Impedance, S = Supply Voltage, GND = Ground
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DIGITAL SIGNAL PROCESSOR
SGUS031B -- APRIL 2000 -- REVISED AUGUST 2001
Signal Descriptions (Continued)
SIGNAL
NAME
NO.
DESCRIPTION
TYPE†
SUPPLY VOLTAGE PINS (CONTINUED)
L8
M11
M13
M15
M7
M9
N10
N12
N14
DVDD
N19
S
3.3-V
3.3
V supply voltage
S
1 8 V supply voltage
1.8-V
N3
N8
P11
P13
P9
U19
U3
W14
W8
A12
A13
B10
B12
B6
D15
D16
F10
F14
CVDD
F8
G13
G7
G8
K4
M3
M4
A3
A5
A7
A16
†
I = Input, O = Output, Z = High Impedance, S = Supply Voltage, GND = Ground
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DIGITAL SIGNAL PROCESSOR
SGUS031B -- APRIL 2000 -- REVISED AUGUST 2001
Signal Descriptions (Continued)
SIGNAL
NAME
NO.
DESCRIPTION
TYPE†
SUPPLY VOLTAGE PINS (CONTINUED)
A18
AA4
AA6
AA15
AA17
AA19
B2
B4
B19
C1
C3
C20
D2
D21
E1
E6
CVDD
E8
E10
S
1 8 V supply voltage
1.8-V
E12
E14
E16
F5
F17
F21
G1
H5
H17
K5
K17
M5
M17
P5
P17
R21
†
I = Input, O = Output, Z = High Impedance, S = Supply Voltage, GND = Ground
16
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DIGITAL SIGNAL PROCESSOR
SGUS031B -- APRIL 2000 -- REVISED AUGUST 2001
Signal Descriptions (Continued)
SIGNAL
NAME
NO.
DESCRIPTION
TYPE†
SUPPLY VOLTAGE PINS (CONTINUED)
T1
T5
T17
U6
U8
U10
U12
U14
U16
U21
V1
V20
W2
W19
W21
Y3
Y18
Y20
CVDD
AA11
S
1.8-V
1.8
V supply voltage
AA12
F20
G18
H16
H18
L18
L19
L20
N20
P18
P19
R10
R14
U4
V11
V12
V15
W13
†
I = Input, O = Output, Z = High Impedance, S = Supply Voltage, GND = Ground
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DIGITAL SIGNAL PROCESSOR
SGUS031B -- APRIL 2000 -- REVISED AUGUST 2001
Signal Descriptions (Continued)
SIGNAL
NAME
NO.
DESCRIPTION
TYPE†
GROUND PINS
C11
C16
C6
D5
G3
H10
H12
H14
H7
H8
J11
J13
J7
J9
K8
L7
L9
M8
N7
VSS
R3
GND
Ground pins
A4
A6
A8
A15
A17
A19
AA3
AA5
AA7
AA14
AA16
AA18
B3
B18
B20
C2
C19
C21
D1
†
I = Input, O = Output, Z = High Impedance, S = Supply Voltage, GND = Ground
18
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DIGITAL SIGNAL PROCESSOR
SGUS031B -- APRIL 2000 -- REVISED AUGUST 2001
Signal Descriptions (Continued)
SIGNAL
NAME
NO.
DESCRIPTION
TYPE†
GROUND PINS (CONTINUED)
D20
E5
E7
E9
E11
E13
E15
E17
E21
F1
G5
G17
G21
H1
J5
J17
L5
VSS
L17
GND
Ground pins
N5
N17
P21
R1
R5
R17
T21
U1
U5
U7
U9
U11
U13
U15
U17
V2
V21
†
I = Input, O = Output, Z = High Impedance, S = Supply Voltage, GND = Ground
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DIGITAL SIGNAL PROCESSOR
SGUS031B -- APRIL 2000 -- REVISED AUGUST 2001
Signal Descriptions (Continued)
SIGNAL
NAME
NO.
DESCRIPTION
TYPE†
GROUND PINS (CONTINUED)
W1
W3
W20
Y2
Y4
Y19
F18
G19
H15
J15
J16
K10
K12
K14
L11
L13
L15
VSS
M10
GND
Ground pins
M12
M14
N11
N13
N15
N9
P10
P12
P14
P15
P7
P8
R19
T4
W11
W16
W6
†
I = Input, O = Output, Z = High Impedance, S = Supply Voltage, GND = Ground
20
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DIGITAL SIGNAL PROCESSOR
SGUS031B -- APRIL 2000 -- REVISED AUGUST 2001
Signal Descriptions (Continued)
SIGNAL
NAME
NO.
DESCRIPTION
TYPE†
REMAINING UNCONNECTED PINS
D13
D14
D18
D3
D6
F12
G12
G15
NC
H19
H20
Unconnected pins
H21
L16
M16
M19
V19
V4
W18
W4
†
I = Input, O = Output, Z = High Impedance, S = Supply Voltage, GND = Ground
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DIGITAL SIGNAL PROCESSOR
SGUS031B -- APRIL 2000 -- REVISED AUGUST 2001
development support
Texas Instruments offers an extensive line of development tools for the C6000 generation of DSPs, including
tools to evaluate the performance of the processors, generate code, develop algorithm implementations, and
fully integrate and debug software and hardware modules.
The following products support development of C6000-based applications:
Software Development Tools:
Assembly optimizer
Assembler/Linker
Simulator
Optimizing ANSI C compiler
Application algorithms
C/Assembly debugger and code profiler
Hardware Development Tools:
Extended development system (XDS™) emulator (supports C6000 multiprocessor system debug)
EVM (Evaluation Module)
The TMS320 DSP Development Support Reference Guide (SPRU011) contains information about
development-support products for all TMS320 family member devices, including documentation. See this
document for further information on TMS320 documentation or any TMS320 support products from Texas
Instruments. An additional document, the TMS320 Third-Party Support Reference Guide (SPRU052), contains
information about TMS320-related products from other companies in the industry. To receive TMS320 literature,
contact the Product Information Center at (800) 477-8924.
See Table 2 for a complete listing of development-support tools for the C6000. For information on pricing and
availability, contact the nearest TI field sales office or authorized distributor.
Table 2. 320C6000 Development-Support Tools
DEVELOPMENT TOOL
PLATFORM
PART NUMBER
Software
Ada 95 Compiler†
Sun Solaris 2.3™‡
AD0345AS8500RF - Single User
AD0345BS8500RF - Multi-user
C Compiler/Assembler/Linker/Assembly Optimizer
Win32™
TMDX3246855-07
C Compiler/Assembler/Linker/Assembly Optimizer
SPARC™ Solaris™
TMDX324655-07
Win32
TMDS3246851-07
SPARC Solaris
TMDS3246551-07
Win32, Windows NT™
TMDX324016X-07
Simulator
Simulator
XDS510™ Debugger/Emulation Software
Hardware
XDS510 Emulator§
PC
XDS510WS™ Emulator¶
SCSI
TMDS00510
TMDS00510WS
Software/Hardware
EVM Evaluation Kit
PC/Win95/Windows NT
TMDX3260A6201
EVM Evaluation Kit (including TMDX3246855--07)
PC/Win95/Windows NT
TMDX326006201
†
Contact IRVINE Compiler Corporation (949) 250-1366 to order.
‡ NT support estimated availability 1Q00.
§ Includes XDS510 board and JTAG emulation cable. TMDX324016X-07 C-source Debugger/Emulation software is not included.
¶ Includes XDS510WS box, SCSI cable, power supply, and JTAG emulation cable.
XDS, XDS510, and XDS510WS are trademarks of Texas Instruments Incorporated.
Win32 and Windows NT are trademarks of Microsoft Corporation.
SPARC is a trademark of SPARC International, Inc.
Solaris is a trademark of Sun Microsystems, Inc.
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device and development-support tool nomenclature
To designate the stages in the product development cycle, TI assigns prefixes to the part numbers of all TMS320
devices and support tools. Each TMS320 member has one of three prefixes: SMX, SM, or SMJ. Texas
Instruments recommends two of three possible prefix designators for support tools: TMDX and TMDS. These
prefixes represent evolutionary stages of product development from engineering prototypes (SMX/TMDX)
through fully qualified production devices/tools (SMJ/TMDS). This development flow follows.
Device development evolutionary flow:
SMX
Experimental device that is not necessarily representative of the final device’s electrical
specifications, 25°C tested, military/industrial ceramic dimpled Ball Grid Array package
SM
Fully TI-qualified production device; offered in extended temperature ranges: --40°C to +90°C (S
range), and --55°C to +115°C (W range); in ceramic dimpled BGA package
SMJ
Fully SMD-qualified production device, --55°C to +115°C (W temperature range), in the ceramic
dimpled Ball Grid Array package processed to MIL-PRF-38535
Support tool development evolutionary flow:
TMDX
Development-support product that has not yet completed Texas Instruments internal qualification
testing.
TMDS
Fully qualified development-support product
TMX and TMP devices and TMDX development-support tools are shipped against the following disclaimer:
“Developmental product is intended for internal evaluation purposes.”
TMS devices and TMDS development-support tools have been characterized fully, and the quality and reliability
of the device have been demonstrated fully. TI’s standard warranty applies.
Predictions show that prototype devices (SMX or SM) have a greater failure rate than the standard production
devices. Texas Instruments recommends that these devices not be used in any production system because their
expected end-use failure rate still is undefined. Only qualified production devices are to be used.
TI device nomenclature also includes a suffix with the device family name. This suffix indicates the package type
(GLP) and the device speed range in megahertz (for example, 15 is 150 MHz). Figure 5 provides a legend for
reading the complete device name.
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DIGITAL SIGNAL PROCESSOR
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device and development-support tool nomenclature (continued)
SMJ 320
C
6201B
PREFIX
SMX = Experimental device
SMJ = MIL-PRF-38535, QML
SM = Commercial
processing
PACKAGE TYPE†
GLP = 429-ball ceramic BGA
TECHNOLOGY
C = CMOS
†
BGA =
DEVICE SPEED RANGE
15 = 150 MHz
16 = 160 MHz
20 = 200 MHz
TEMPERATURE RANGE
S = --40 to 90°C, extended temperature
W = --55 to 115°C, extended temperature
DEVICE FAMILY
320 = TMS320 family
DEVICE
’6x DSP:
GLP W 15
6201
6201B
6203
6701
Ball Grid Array
Figure 5. TMS320 Device Nomenclature (Including SMJ320C6201B)
documentation support
Extensive documentation supports all TMS320 family generations of devices from product announcement
through applications development. The types of documentation available include: data sheets, such as this
document, with design specifications; complete user’s reference guides for all devices; technical briefs;
development-support tools; and hardware and software applications. The following is a brief, descriptive list of
support documentation specific to the C6x™ devices:
The TMS320C6000 CPU and Instruction Set Reference Guide (literature number SPRU189) describes the
C6000 CPU architecture, instruction set, pipeline, and associated interrupts.
The TMS320C6000 Peripherals Reference Guide (literature number SPRU190) describes the functionality of
the peripherals available on C6x devices, such as the external memory interface (EMIF), host-port interface
(HPI), multichannel buffered serial ports (McBSPs), direct-memory-access (DMA), enhanced
direct-memory-access (EDMA) controller, expansion bus (XB), clocking and phase-locked loop (PLL); and
power-down modes. This guide also includes information on internal data and program memories.
The TMS320C6000 Programmer’s Guide (literature number SPRU198) describes ways to optimize C and
assembly code for C6x devices and includes application program examples.
The TMS320C6x C Source Debugger User’s Guide (literature number SPRU188) describes how to invoke the
C6x simulator and emulator versions of the C source debugger interface and discusses various aspects of the
debugger, including: command entry, code execution, data management, breakpoints, profiling, and analysis.
The TMS320C6x Peripheral Support Library Programmer’s Reference (literature number SPRU273) describes
the contents of the C6x peripheral support library of functions and macros. It lists functions and macros both
by header file and alphabetically, provides a complete description of each, and gives code examples to show
how they are used.
C6x is a trademark of Texas Instruments Incorporated.
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documentation support (continued)
TMS320C6000 Assembly Language Tools User’s Guide (literature number SPRU186) describes the assembly
language tools (assembler, linker, and other tools used to develop assembly language code), assembler
directives, macros, common object file format, and symbolic debugging directives for the C6000 generation of
devices.
The TMS320C6x Evaluation Module Reference Guide (literature number SPRU269) provides instructions for
installing and operating the C6x evaluation module. It also includes support software documentation,
application programming interfaces, and technical reference material.
TMS320C62x Multichannel Evaluation Module User’s Guide (literature number SPRU285) provides
instructions for installing and operating the C62x multichannel evaluation module. It also includes support
software documentation, application programming interfaces, and technical reference material.
TMS320C62x Multichannel Evaluation Module Technical Reference (SPRU308) provides provides technical
reference information for the C62x multichannel evaluation module (McEVM). It includes support software
documentation, application programming interface references, and hardware descriptions for the C62x
McEVM.
TMS320C6000 DSP/BIOS User’s Guide (literature number SPRU303) describes how to use DSP/BIOS tools
and APIs to analyze embedded real-time DSP applications.
Code Composer User’s Guide (literature number SPRU296) explains how to use the Code Composer
development environment to build and debug embedded real-time DSP applications.
Code Composer Studio Tutorial (literature number SPRU301) introduces the Code Composer Studio integrated
development environment and software tools.
The TMS320C6000 Technical Brief (literature number SPRU197) gives an introduction to the C62x/C67x
devices, associated development tools, and third-party support.
A series of DSP textbooks is published by Prentice-Hall and John Wiley & Sons to support DSP research and
education. The TMS320 newsletter, Details on Signal Processing, is published quarterly and distributed to
update TMS320 customers on product information. The TMS320 DSP bulletin board service (BBS) provides
access to information pertaining to the TMS320 family, including documentation, source code, and object code
for many DSP algorithms and utilities. The BBS can be reached at 281/274-2323.
Information regarding TI DSP products is also available on the Worldwide Web at http://www.ti.com uniform
resource locator (URL).
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DIGITAL SIGNAL PROCESSOR
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clock PLL
All of the C62x clocks are generated from a single source through the CLKIN pin. This source clock either drives
the PLL, which generates the internal CPU clock, or bypasses the PLL to become the CPU clock.
To use the PLL to generate the CPU clock, the filter circuit shown in Figure 6 must be properly designed. For
the C6201B, it must be powered by the I/O voltage (3.3 V).
To configure the C62x PLL clock for proper operation, see Figure 6 and Table 3. To minimize the clock jitter, a
single clean power supply should power both the C62x device and the external clock oscillator circuit. The
minimum CLKIN rise and fall times should also be observed. See the input and output clocks section for input
clock timing requirements. Guidelines for EMI filter selection are as follows: maximum attenuation frequency
= 20-30 MHz, maximum dB attenuation = 45-50 db, and minimum dB attenuation above 30 MHz = 20 dB.
0 1 0 -- C6201B CLKOUT1 Frequency Range 130--233 MHz
0 0 1 -- C6201B CLKOUT1 Frequency Range 65--200 MHz
0 0 0 -- C6201B CLKOUT1 Frequency Range 50--140 MHz
PLLV
PLLF
R1
2
GND
10 μF
0.1 μF
(Bypass)
C1
C2
PLLG
CLKIN
C6201B
PLLFREQ3
PLLFREQ2
PLLFREQ1
EMI Filter
1 IN
3 OUT
EMIF
CLKOUT1
CLKOUT
CLKMODE0
CLKMODE1
3.3 V 2.5 V
1 1 -- MULT×4
CLKOUT2
SSCLK
SDCLK
f(CLKOUT)=f(CLKIN)×4
0 1 -- Reserved
1 0 -- Reserved
0 0 -- MULT×1
f(CLKOUT)=f(CLKIN)
NOTES: A. For the C6201B CLKMODE x4, values for C1, C2, and R1 are fixed and apply to all valid frequency ranges of CLKIN and CLKOUT.
B. For CLKMODE x1, the PLL is bypassed and all six external PLL components can be removed. For this case, the PLLV terminal has
to be connected to a clean supply and the PLLG and PLLF terminals should be tied together.
C. Due to overlap of frequency ranges when choosing the PLLFREQ, more than one frequency range can contain the CLKOUT1
frequency. Choose the lowest frequency range that includes the desired frequency. For example, for CLKOUT1 = 133 MHz, a
PLLFREQ value of 000b should be used for the C6201B. For CLKOUT1 = 200 MHz, PLLFREQ should be set to 001b for the
C6201B. PLLFREQ values other than 000b, 001b, and 010b are reserved.
D. For the C6201B, the 3.3-V supply for the EMI filter (and PLLV) must be from the same 3.3-V power plane supplying the I/O voltage,
DVDD.
Figure 6. PLL Block Diagram
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clock PLL (continued)
Table 3. 320C6201B PLL Component Selection Table
†
CLKMODE
CLKIN
RANGE
(MHz)
CPU CLOCK
FREQUENCY
(CLKOUT1)
RANGE (MHz)
CLKOUT2
RANGE
(MHz)
R1
(Ω)
C1
(nF)
C2
(pF)
TYPICAL
LOCK TIME
(μs)†
x4
12.5--50
50--200
25--100
60.4
27
560
75
Under some operating conditions, the maximum PLL lock time may vary as much as 150% from the specified typical value. For example, if the
typical lock time is specified as 100 μs, the maximum value may be as long as 250 μs.
power supply sequencing
TI DSPs do not require specific power sequencing between the core supply and the I/O supply. However,
systems should be designed to ensure that neither supply is powered up for extended periods of time if the other
supply is below the proper operating voltage.
system-level design considerations
System-level design considerations, such as bus contention, may require supply sequencing to be
implemented. In this case, the core supply should be powered up at the same time as, or prior to (and powered
down after), the I/O buffers. This is to ensure that the I/O buffers receive valid inputs from the core before the
output buffers are powered up, thus, preventing bus contention with other chips on the board.
power-supply design considerations
For systems using the C6000™ DSP platform of devices, the core supply may be required to provide in excess
of 2 A per DSP until the I/O supply is powered up. This extra current condition is a result of uninitialized logic
within the DSP(s) and is corrected once the CPU sees an internal clock pulse. With the PLL enabled, as the
I/O supply is powered on, a clock pulse is produced stopping the extra current draw from the supply. With the
PLL disabled, an external clock pulse may be required to stop this extra current draw. A normal current state
returns once the I/O power supply is turned on and the CPU sees a clock pulse. Decreasing the amount of time
between the core supply power up and the I/O supply power up can minimize the effects of this current draw.
A dual-power supply with simultaneous sequencing, such as available with TPS563xx controllers or PT69xx
plug-in power modules, can be used to eliminate the delay between core and I/O power up [see the Using the
TPS56300 to Power DSPs application report (literature number SLVA088)]. A Schottky diode can also be used
to tie the core rail to the I/O rail, effectively pulling up the I/O power supply to a level that can help initialize the
logic within the DSP.
Core and I/O supply voltage regulators should be located close to the DSP (or DSP array) to minimize
inductance and resistance in the power delivery path. Additionally, when designing for high-performance
applications utilizing the C6000™ platform of DSPs, the PC board should include separate power planes for
core, I/O, and ground, all bypassed with high-quality low-ESL/ESR capacitors.
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DIGITAL SIGNAL PROCESSOR
SGUS031B -- APRIL 2000 -- REVISED AUGUST 2001
absolute maximum ratings over operating case temperature range (unless otherwise noted)†
Supply voltage range, CVDD (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . --0.3 V to 2.3 V
Supply voltage range, DVDD (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . --0.3 V to 4 V
Input voltage range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . --0.3 V to 4 V
Output voltage range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . --0.3 V to 4 V
Operating case temperature range TC: (S temp version) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . --40_C to 90_C
(W temp version) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . --55_C to 115_C
Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . --55_C to 150_C
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTE 1: All voltage values are with respect to VSS.
recommended operating conditions
C6201B
NOM
MAX
UNIT
CVDD
Supply voltage
1.71
1.8
1.89
V
DVDD
Supply voltage
3.14
3.30
3.46
V
VSS
Supply ground
0
0
0
V
VIH
High-level input voltage
VIL
Low-level input voltage
0.8
V
IOH
High-level output current
--12
mA
IOL
Low-level output current
12
mA
TC
‡
MIN
Operating case temperature‡
2.0
S temp version
--40
90
W temp version
--55
115
Case temperature is measured at package bottom. There is no direct thermal path from the chip through the lid.
28
V
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_C
SM320C6201B, SMJ320C6201B
DIGITAL SIGNAL PROCESSOR
SGUS031B -- APRIL 2000 -- REVISED AUGUST 2001
electrical characteristics over recommended ranges of supply voltage and operating case
temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
C6201B
MIN
TYP
MAX
UNIT
VOH
High-level output voltage
DVDD = MIN,
IOH = MAX
VOL
Low-level output voltage
DVDD = MIN,
IOL = MAX
0.6
V
II
Input current†
VI = VSS to DVDD
±10
uA
IOZ
Off-state output current
VO = DVDD or 0 V
±10
uA
IDD2V
Supply current, CPU + CPU memory access‡
CVDD = NOM,
CPU clock = 167 MHz
380
mA
IDD2V
Supply current, peripherals§
CVDD = NOM,
CPU clock = 167 MHz
240
mA
IDD3V
Supply current, I/O pins¶
DVDD = NOM,
CPU clock = 167 MHz
90
mA
Ci
Input capacitance
15
pF
Co
Output capacitance
15
pF
2.4
V
†
TMS and TDI are not included due to internal pullups.
TRST is not included due to internal pulldown.
‡ Measured with average CPU activity:
50% of time:
8 instructions per cycle, 32-bit DMEM access per cycle
50% of time:
2 instructions per cycle, 16-bit DMEM access per cycle
§ Measured with average peripheral activity:
50% of time:
Timers at max rate, McBSPs at E1 rate, and DMA burst transfer between DMEM and SDRAM
50% of time: Timers at max rate, McBSPs at E1 rate, and DMA servicing McBSPs
¶ Measured with average I/O activity (30-pF load):
25% of time:
Reads from external SDRAM
25% of time:
Writes to external SDRAM
50% of time:
No activity
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29
SM320C6201B, SMJ320C6201B
DIGITAL SIGNAL PROCESSOR
SGUS031B -- APRIL 2000 -- REVISED AUGUST 2001
PARAMETER MEASUREMENT INFORMATION
IOL
Tester Pin
Electronics
50 Ω
Vref
Output
Under
Test
CT = 30 pF†
IOH
†
Typical distributed load circuit capacitance
Figure 7. TTL-Level Outputs
signal transition levels
All input and output timing parameters are referenced to 1.5 V for both “0” and “1” logic levels.
Vref = 1.5 V
Figure 8. Input and Output Voltage Reference Levels for AC Timing Measurements
30
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SM320C6201B, SMJ320C6201B
DIGITAL SIGNAL PROCESSOR
SGUS031B -- APRIL 2000 -- REVISED AUGUST 2001
INPUT AND OUTPUT CLOCKS
timing requirements for CLKIN (see Figure 9)
C6201B-15
CLKMODE
= x4
NO.
MIN
MAX
C6201B-20
CLKMODE
= x1
CLKMODE
= x4
CLKMODE
= x1
MIN
MIN
MIN
MAX
MAX
UNIT
MAX
1
tc(CLKIN)
Cycle time, CLKIN
26.7
6.67
20
5
ns
2
tw(CLKINH)
Pulse duration, CLKIN high
*9.8
*2.7
*8
*2.35
ns
3
tw(CLKINL)
Pulse duration, CLKIN low
*9.8
4
tt(CLKIN)
Transition time, CLKIN
*2.7
*8
*5
*2.35
*0.6
ns
*5
*0.6
ns
*Not production tested.
1
4
2
CLKIN
3
4
Figure 9. CLKIN Timings
switching characteristics for CLKOUT1†‡ (see Figure 10)
C6201B
NO.
CLKMODE = x4
PARAMETER
MIN
CLKMODE = x1
MAX
MIN
UNIT
MAX
1
tc(CKO1)
Cycle time, CLKOUT1
*P -- 0.7
*P + 0.7
*P -- 0.7
*P + 0.7
ns
2
tw(CKO1H)
Pulse duration, CLKOUT1 high
*(P/2) -- 0.5
*(P/2 ) + 0.5
*PH -- 0.5
*PH + 0.5
ns
3
tw(CKO1L)
Pulse duration, CLKOUT1 low
*(P/2) -- 0.5
*(P/2 ) + 0.5
*PL -- 0.5
*PL + 0.5
ns
4
tt(CKO1)
Transition time, CLKOUT1
*0.6
ns
*0.6
†
PH is the high period of CLKIN in ns and PL is the low period of CLKIN in ns.
P = 1/CPU clock frequency in nanoseconds (ns).
*Not production tested.
‡
1
4
2
CLKOUT1
3
4
Figure 10. CLKOUT1 Timings
PRODUCT PREVIEW information concerns products in the formative or
design phase of development. Characteristic data and other
specifications are design goals. Texas Instruments reserves the right to
change or discontinue these products without notice.
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SM320C6201B, SMJ320C6201B
DIGITAL SIGNAL PROCESSOR
SGUS031B -- APRIL 2000 -- REVISED AUGUST 2001
INPUT AND OUTPUT CLOCKS (CONTINUED)
switching characteristics for CLKOUT2† (see Figure 11)
NO
NO.
C6201B
PARAMETER
MAX
UNIT
1
tc(CKO2)
Cycle time, CLKOUT2
*2P -- 0.7
*2P + 0.7
ns
2
tw(CKO2H)
Pulse duration, CLKOUT2 high
*P -- 0.9
*P + 0.7
ns
3
tw(CKO2L)
Pulse duration, CLKOUT2 low
*P -- 0.7
*P + 0.9
ns
4
tt(CKO2)
Transition time, CLKOUT2
*0.6
ns
†
P = 1/CPU clock frequency in ns.
*Not production tested.
1
4
2
CLKOUT2
3
4
Figure 11. CLKOUT2 Timings
32
MIN
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SM320C6201B, SMJ320C6201B
DIGITAL SIGNAL PROCESSOR
SGUS031B -- APRIL 2000 -- REVISED AUGUST 2001
INPUT AND OUTPUT CLOCKS (CONTINUED)
SDCLK, SSCLK timing parameters
SDCLK timing parameters are the same as CLKOUT2 parameters.
SSCLK timing parameters are the same as CLKOUT1 or CLKOUT2 parameters, depending on SSCLK
configuration.
switching characteristics for the relation of SSCLK, SDCLK, and CLKOUT2 to CLKOUT1
(see Figure 12)†
NO
NO.
C6201B
PARAMETER
1
td(CKO1-SSCLK)
Delay time, CLKOUT1 edge to SSCLK edge
2
td(CKO1-SSCLK1/2)
Delay time, CLKOUT1 edge to SSCLK edge (1/2 clock rate)
3
td(CKO1-CKO2)
Delay time, CLKOUT1 edge to CLKOUT2 edge
4
td(CKO1-SDCLK)
Delay time, CLKOUT1 edge to SDCLK edge
UNIT
MIN
MAX
(P/2) + 0.2
(P/2) + 4.2
ns
(P/2) -- 1
(P/2) + 2.4
ns
*(P/2) -- 1
*(P/2) + 2.4
ns
(P/2) -- 1
(P/2) + 2.4
ns
†
P = 1/CPU clock frequency in ns.
*Not production tested.
CLKOUT1
1
SSCLK
2
SSCLK (1/2rate)
3
CLKOUT2
4
SDCLK
Figure 12. Relation of CLKOUT2, SDCLK, and SSCLK to CLKOUT1
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SM320C6201B, SMJ320C6201B
DIGITAL SIGNAL PROCESSOR
SGUS031B -- APRIL 2000 -- REVISED AUGUST 2001
ASYNCHRONOUS MEMORY TIMING
timing requirements for asynchronous memory cycles† (see Figure 13 and Figure 14)
C6201B
NO
NO.
†
MIN
MAX
UNIT
6
tsu(EDV-CKO1H)
Setup time, read EDx valid before CLKOUT1 high
4.0
ns
7
th(CKO1H-EDV)
Hold time, read EDx valid after CLKOUT1 high
0.8
ns
10
tsu(ARDY-CKO1H)
Setup time, ARDY valid before CLKOUT1 high
3.0
ns
11
th(CKO1H-ARDY)
Hold time, ARDY valid after CLKOUT1 high
1.8
ns
To ensure data setup time, simply program the strobe width wide enough. ARDY is internally synchronized. If ARDY does meet setup or hold
time, it may be recognized in the current cycle or the next cycle. Thus, ARDY can be an asynchronous input.
switching characteristics for asynchronous memory cycles‡ (see Figure 13 and Figure 14)
NO
NO.
PARAMETER
UNIT
MIN
MAX
--0.2
4.0
ns
4.0
ns
1
td(CKO1H-CEV)
Delay time, CLKOUT1 high to CEx valid
2
td(CKO1H-BEV)
Delay time, CLKOUT1 high to BEx valid
3
td(CKO1H-BEIV)
Delay time, CLKOUT1 high to BEx invalid
4
td(CKO1H-EAV)
Delay time, CLKOUT1 high to EAx valid
5
td(CKO1H-EAIV)
Delay time, CLKOUT1 high to EAx invalid
*--0.2
8
td(CKO1H-AOEV)
Delay time, CLKOUT1 high to AOE valid
--0.2
4.0
ns
9
td(CKO1H-AREV)
Delay time, CLKOUT1 high to ARE valid
--0.2
4.0
ns
12
td(CKO1H-EDV)
Delay time, CLKOUT1 high to EDx valid
4.0
ns
13
td(CKO1H-EDIV)
Delay time, CLKOUT1 high to EDx invalid
*--0.2
14
td(CKO1H-AWEV)
Delay time, CLKOUT1 high to AWE valid
--0.2
‡
The minimum delay is also the minimum output hold after CLKOUT1 high.
*Not production tested.
34
C6201B
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*--0.2
ns
4.0
ns
ns
ns
4.0
ns
SM320C6201B, SMJ320C6201B
DIGITAL SIGNAL PROCESSOR
SGUS031B -- APRIL 2000 -- REVISED AUGUST 2001
ASYNCHRONOUS MEMORY TIMING (CONTINUED)
Setup = 2
Not ready = 2
Strobe = 5
HOLD = 1
CLKOUT1
1
1
2
3
4
5
CEx
BE[3:0]
EA[21:2]
7
6
ED[31:0]
8
8
AOE
9
9
ARE
AWE
10
11
10
11
ARDY
Figure 13. Asynchronous Memory Read Timing
Setup = 2
Not ready = 2
Strobe = 5
HOLD = 1
CLKOUT1
1
1
2
3
4
5
CEx
BE[3:0]
EA[21:2]
12
13
ED[31:0]
AOE
ARE
14
14
AWE
10
11
10
11
ARDY
Figure 14. Asynchronous Memory Write Timing
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35
SM320C6201B, SMJ320C6201B
DIGITAL SIGNAL PROCESSOR
SGUS031B -- APRIL 2000 -- REVISED AUGUST 2001
SYNCHRONOUS-BURST MEMORY TIMING
timing requirements for synchronous-burst SRAM cycles (full-rate SSCLK) (see Figure 15)
C6201B
NO
NO.
MIN
MAX
UNIT
7
tsu(EDV-SSCLKH)
Setup time, read EDx valid before SSCLK high
1.7
ns
8
th(SSCLKH-EDV)
Hold time, read EDx valid after SSCLK high
1.5
ns
switching characteristics for synchronous-burst SRAM cycles† (full-rate SSCLK)
(see Figure 15 and Figure 16)
NO
NO.
C6201B
PARAMETER
MIN
MAX
UNIT
1
tosu(CEV-SSCLKH)
Output setup time, CEx valid before SSCLK high
0.5P -- 1.3
ns
2
toh(SSCLKH-CEV)
Output hold time, CEx valid after SSCLK high
0.5P -- 2.3
ns
3
tosu(BEV-SSCLKH)
Output setup time, BEx valid before SSCLK high
0.5P -- 1.3
ns
4
toh(SSCLKH-BEIV)
Output hold time, BEx invalid after SSCLK high
*0.5P -- 2.3
ns
5
tosu(EAV-SSCLKH)
Output setup time, EAx valid before SSCLK high
0.5P -- 1.3
ns
6
toh(SSCLKH-EAIV)
Output hold time, EAx invalid after SSCLK high
*0.5P -- 2.3
ns
9
tosu(ADSV-SSCLKH)
Output setup time, SSADS valid before SSCLK high
0.5P -- 1.3
ns
10
toh(SSCLKH-ADSV)
Output hold time, SSADS valid after SSCLK high
0.5P -- 2.3
ns
11
tosu(OEV-SSCLKH)
Output setup time, SSOE valid before SSCLK high
0.5P -- 1.3
ns
12
toh(SSCLKH-OEV)
Output hold time, SSOE valid after SSCLK high
0.5P -- 2.3
ns
13
tosu(EDV-SSCLKH)
Output setup time, EDx valid before SSCLK high
0.5P -- 1.3
ns
14
toh(SSCLKH-EDIV)
Output hold time, EDx invalid after SSCLK high
*0.5P -- 2.3
ns
15
tosu(WEV-SSCLKH)
Output setup time, SSWE valid before SSCLK high
0.5P -- 1.3
ns
16
toh(SSCLKH-WEV)
Output hold time, SSWE valid after SSCLK high
0.5P -- 2.3
ns
†
When the PLL is used (CLKMODE x4), P = 1/CPU clock frequency in ns. For example, when running parts at 200 MHz, use P = 5 ns.
For CLKMODE x1, 0.5P is defined as PH (pulse duration of CLKIN high) for all output setup times; 0.5P is defined as PL (pulse duration of CLKIN
low) for all output hold times.
*Not production tested.
36
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SM320C6201B, SMJ320C6201B
DIGITAL SIGNAL PROCESSOR
SGUS031B -- APRIL 2000 -- REVISED AUGUST 2001
SYNCHRONOUS-BURST MEMORY TIMING (CONTINUED)
SSCLK
CEx
1
2
3
BE[3:0]
BE1
BE2
BE3
4
BE4
A1
A2
A3
6
A4
5
EA[21:2]
7
8
Q1
ED[31:0]
9
Q2
Q3
Q4
10
SSADS
11
12
SSOE
SSWE
Figure 15. SBSRAM Read Timing (Full-Rate SSCLK)
SSCLK
1
2
CEx
3
BE[3:0]
BE1
BE2
BE3
4
BE4
A1
A2
A3
6
A4
D3
14
D4
5
EA[21:2]
13
ED[31:0]
D1
D2
9
10
15
16
SSADS
SSOE
SSWE
Figure 16. SBSRAM Write Timing (Full-Rate SSCLK)
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SM320C6201B, SMJ320C6201B
DIGITAL SIGNAL PROCESSOR
SGUS031B -- APRIL 2000 -- REVISED AUGUST 2001
SYNCHRONOUS-BURST MEMORY TIMING (CONTINUED)
timing requirements for synchronous-burst SRAM cycles (half-rate SSCLK)
(see Figure 17)
C6201B
NO
NO.
MIN
MAX
UNIT
7
tsu(EDV-SSCLKH)
Setup time, read EDx valid before SSCLK high
2.5
ns
8
th(SSCLKH-EDV)
Hold time, read EDx valid after SSCLK high
1.5
ns
switching characteristics for synchronous-burst SRAM cycles† (half-rate SSCLK)
(see Figure 17 and Figure 18)
NO
NO.
C6201B
PARAMETER
MIN
1
tosu(CEV-SSCLKH)
Output setup time, CEx valid before SSCLK high
2
toh(SSCLKH-CEV)
Output hold time, CEx valid after SSCLK high
3
tosu(BEV-SSCLKH)
Output setup time, BEx valid before SSCLK high
4
toh(SSCLKH-BEIV)
Output hold time, BEx invalid after SSCLK high
5
tosu(EAV-SSCLKH)
Output setup time, EAx valid before SSCLK high
6
toh(SSCLKH-EAIV)
Output hold time, EAx invalid after SSCLK high
9
tosu(ADSV-SSCLKH)
Output setup time, SSADS valid before SSCLK high
10
toh(SSCLKH-ADSV)
Output hold time, SSADS valid after SSCLK high
11
tosu(OEV-SSCLKH)
Output setup time, SSOE valid before SSCLK high
12
toh(SSCLKH-OEV)
Output hold time, SSOE valid after SSCLK high
13
tosu(EDV-SSCLKH)
Output setup time, EDx valid before SSCLK high
14
toh(SSCLKH-EDIV)
Output hold time, EDx invalid after SSCLK high
15
tosu(WEV-SSCLKH)
Output setup time, SSWE valid before SSCLK high
16
toh(SSCLKH-WEV)
Output hold time, SSWE valid after SSCLK high
†
MAX
UNIT
1.5P -- 3
ns
0.5P -- 1.5
ns
1.5P -- 3
ns
*0.5P -- 1.5
ns
1.5P -- 3
ns
*0.5P -- 1.5
ns
1.5P -- 3
ns
0.5P -- 1.5
ns
1.5P -- 3
ns
0.5P -- 1.5
ns
1.5P -- 3
ns
*0.5P -- 1.5
ns
1.5P -- 3
ns
0.5P -- 1.5
ns
When the PLL is used (CLKMODE x4), P = 1/CPU clock frequency in ns. For example, when running parts at 200 MHz, use P = 5 ns.
For CLKMODE x1:
1.5P = P + PH, where P = 1/CPU clock frequency, and PH = pulse duration of CLKIN high.
0.5P = PL, where PL = pulse duration of CLKIN low.
*Not production tested.
PRODUCT PREVIEW information concerns products in the formative or
design phase of development. Characteristic data and other
specifications are design goals. Texas Instruments reserves the right to
change or discontinue these products without notice.
38
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SM320C6201B, SMJ320C6201B
DIGITAL SIGNAL PROCESSOR
SGUS031B -- APRIL 2000 -- REVISED AUGUST 2001
SYNCHRONOUS-BURST MEMORY TIMING (CONTINUED)
SSCLK
1
2
CEx
BE[3:0]
3
BE1
BE2
BE3
BE4
4
EA[21:2]
5
A1
A2
A3
A4
6
7
Q1
ED[31:0]
8
Q2
Q3
9
Q4
10
SSADS
11
12
SSOE
SSWE
Figure 17. SBSRAM Read Timing (1/2 Rate SSCLK)
SSCLK
1
2
CEx
BE[3:0]
3
BE1
BE2
BE3
BE4
4
EA[21:2]
5
A1
A2
A3
A4
Q1
Q2
Q3
Q4
6
13
ED[31:0]
14
9
10
15
16
SSADS
SSOE
SSWE
Figure 18. SBSRAM Write Timing (1/2 Rate SSCLK)
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SM320C6201B, SMJ320C6201B
DIGITAL SIGNAL PROCESSOR
SGUS031B -- APRIL 2000 -- REVISED AUGUST 2001
SYNCHRONOUS DRAM TIMING
timing requirements for synchronous DRAM cycles (see Figure 19)
C6201B
NO
NO.
MIN
7
tsu(EDV-SDCLKH)
Setup time, read EDx valid before SDCLK high
8
th(SDCLKH-EDV)
Hold time, read EDx valid after SDCLK high
MAX
UNIT
0.5
ns
3
ns
switching characteristics for synchronous DRAM cycles† (see Figure 19--Figure 24)
NO
NO.
C6201B
PARAMETER
MIN
1
tosu(CEV-SDCLKH)
Output setup time, CEx valid before SDCLK high
2
toh(SDCLKH-CEV)
Output hold time, CEx valid after SDCLK high
3
tosu(BEV-SDCLKH)
Output setup time, BEx valid before SDCLK high
4
toh(SDCLKH-BEIV)
Output hold time, BEx invalid after SDCLK high
5
tosu(EAV-SDCLKH)
Output setup time, EAx valid before SDCLK high
6
toh(SDCLKH-EAIV)
Output hold time, EAx invalid after SDCLK high
9
tosu(SDCAS-SDCLKH)
Output setup time, SDCAS valid before SDCLK high
10
toh(SDCLKH-SDCAS)
11
tosu(EDV-SDCLKH)
12
toh(SDCLKH-EDIV)
Output hold time, EDx invalid after SDCLK high
13
tosu(SDWE-SDCLKH)
Output setup time, SDWE valid before SDCLK high
14
toh(SDCLKH-SDWE)
Output hold time, SDWE valid after SDCLK high
15
tosu(SDA10V-SDCLKH)
Output setup time, SDA10 valid before SDCLK high
16
toh(SDCLKH-SDA10IV)
Output hold time, SDA10 invalid after SDCLK high
17
tosu(SDRAS-SDCLKH)
Output setup time, SDRAS valid before SDCLK high
18
toh(SDCLKH-SDRAS)
Output hold time, SDRAS valid after SDCLK high
MAX
UNIT
1.5P -- 3.5
ns
0.5P -- 1
ns
1.5P -- 3.5
ns
*0.5P -- 1
ns
1.5P -- 3.5
ns
*0.5P -- 1
ns
1.5P -- 3.5
ns
Output hold time, SDCAS valid after SDCLK high
0.5P -- 1
ns
Output setup time, EDx valid before SDCLK high
1.5P -- 3.5
ns
*0.5P -- 1
ns
1.5P -- 3.5
ns
0.5P -- 1
ns
1.5P -- 3.5
ns
*0.5P -- 1
ns
1.5P -- 3.5
ns
0.5P -- 1
ns
†
When the PLL is used (CLKMODE x4), P = 1/CPU clock frequency in ns. For example, when running parts at 200 MHz, use P = 5 ns.
For CLKMODE x1:
1.5P = P + PH, where P = 1/CPU clock frequency, and PH = pulse duration of CLKIN high.
0.5P = PL, where PL = pulse duration of CLKIN low.
*Not production tested.
PRODUCT PREVIEW information concerns products in the formative or
design phase of development. Characteristic data and other
specifications are design goals. Texas Instruments reserves the right to
change or discontinue these products without notice.
40
POST OFFICE BOX 1443
• HOUSTON, TEXAS 77251--1443
SM320C6201B, SMJ320C6201B
DIGITAL SIGNAL PROCESSOR
SGUS031B -- APRIL 2000 -- REVISED AUGUST 2001
SYNCHRONOUS DRAM TIMING (CONTINUED)
READ
READ
READ
SDCLK
1
2
CEx
3
BE[3:0]
5
EA[15:2]
4
BE1
BE2
CA2
CA3
BE3
6
CA1
7
8
D1
ED[31:0]
15
16
9
10
D2
D3
SDA10
SDRAS
SDCAS
SDWE
Figure 19. Three SDRAM Read Commands
WRITE
WRITE
WRITE
SDCLK
1
2
CEx
3
BE[3:0]
4
BE1
5
EA[15:2]
BE3
CA2
CA3
D2
D3
6
CA1
11
D1
ED[31:0]
BE2
12
15
16
9
10
13
14
SDA10
SDRAS
SDCAS
SDWE
Figure 20. Three SDRAM WRT Commands
POST OFFICE BOX 1443
• HOUSTON, TEXAS 77251--1443
41
SM320C6201B, SMJ320C6201B
DIGITAL SIGNAL PROCESSOR
SGUS031B -- APRIL 2000 -- REVISED AUGUST 2001
SYNCHRONOUS DRAM TIMING (CONTINUED)
ACTV
SDCLK
1
2
CEx
BE[3:0]
5
Bank Activate/Row Address
EA[15:2]
ED[31:0]
15
Row Address
SDA10
17
18
SDRAS
SDCAS
SDWE
Figure 21. SDRAM ACTV Command
DCAB
SDCLK
1
2
15
16
17
18
CEx
BE[3:0]
EA[15:2]
ED[31:0]
SDA10
SDRAS
SDCAS
13
SDWE
Figure 22. SDRAM DCAB Command
42
POST OFFICE BOX 1443
• HOUSTON, TEXAS 77251--1443
14
SM320C6201B, SMJ320C6201B
DIGITAL SIGNAL PROCESSOR
SGUS031B -- APRIL 2000 -- REVISED AUGUST 2001
SYNCHRONOUS DRAM TIMING (CONTINUED)
REFR
SDCLK
1
2
CEx
BE[3:0]
EA[15:2]
ED[31:0]
SDA10
17
18
SDRAS
9
10
SDCAS
SDWE
Figure 23. SDRAM REFR Command
MRS
SDCLK
1
2
5
6
CEx
BE[3:0]
EA[15:2]
MRS Value
ED[31:0]
SDA10
17
18
9
10
13
14
SDRAS
SDCAS
SDWE
Figure 24. SDRAM MRS Command
POST OFFICE BOX 1443
• HOUSTON, TEXAS 77251--1443
43
SM320C6201B, SMJ320C6201B
DIGITAL SIGNAL PROCESSOR
SGUS031B -- APRIL 2000 -- REVISED AUGUST 2001
HOLD/HOLDA TIMING
timing requirements for the HOLD/HOLDA cycles† (see Figure 25)
C6201B
NO
NO.
MIN
MAX
UNIT
1
tsu(HOLDH-CKO1H)
Setup time, HOLD high before CLKOUT1 high
*1
ns
2
th(CKO1H-HOLDL)
Hold time, HOLD low after CLKOUT1 high
*4
ns
†
HOLD is synchronized internally. Therefore, if setup and hold times are not met, it will either be recognized in the current cycle or in the next cycle.
Thus, HOLD can be an asynchronous input.
*Not production tested.
switching characteristics for the HOLD/HOLDA cycles‡ (see Figure 25)
NO
NO.
C6201B
PARAMETER
UNIT
MIN
MAX
*4P
§
ns
*P
*2P
ns
3
tR(HOLDL-BHZ)
Response time, HOLD low to EMIF Bus high impedance
4
tR(BHZ-HOLDAL)
Response time, EMIF Bus high impedance to HOLDA low
5
tR(HOLDH-HOLDAH)
Response time, HOLD high to HOLDA high
*4P
*7P
ns
6
td(CKO1H-HOLDAL)
Delay time, CLKOUT1 high to HOLDA valid
*1
8
ns
7
td(CKO1H-BHZ)
Delay time, CLKOUT1 high to EMIF Bus high impedance¶
*3
*11
ns
*3
*11
ns
*3P
*6P
ns
impedance¶
8
td(CKO1H-BLZ)
Delay time, CLKOUT1 high to EMIF Bus low
9
tR(HOLDH-BLZ)
Response time, HOLD high to EMIF Bus low impedance
‡
P = 1/CPU clock frequency in ns. For example, when running parts at 200 MHz, use P = 5 ns.
*Not production tested.
§ All pending EMIF transactions are allowed to complete before HOLDA is asserted. The worst cases for this is an asynchronous read or write
with external ARDY used or a minimum of eight consecutive SDRAM reads or writes when RBTR8 = 1. If no bus transactions are occurring, then
the minimum delay time can be achieved. Also, bus hold can be indefinitely delayed by setting NOHOLD = 1.
¶ EMIF Bus consists of CE[3:0], BE[3:0], ED[31:0], EA[21:2], ARE, AOE, AWE, SSADS, SSOE, SSWE, SDA10, SDRAS, SDCAS, and SDWE.
DSP Owns Bus
External Requester
DSP Owns Bus
5
9
4
3
CLKOUT1
2
2
1
1
HOLD
6
6
HOLDA
7
8
EMIF Bus†
†
’C62x
Ext Req
’C62x
EMIF Bus consists of CE[3:0], BE[3:0], ED[31:0], EA[21:2], ARE, AOE, AWE, SSADS, SSOE, SSWE, SDA10, SDRAS, SDCAS, and SDWE.
Figure 25. HOLD/HOLDA Timing
44
POST OFFICE BOX 1443
• HOUSTON, TEXAS 77251--1443
SM320C6201B, SMJ320C6201B
DIGITAL SIGNAL PROCESSOR
SGUS031B -- APRIL 2000 -- REVISED AUGUST 2001
RESET TIMING
timing requirements for reset (see Figure 26)
C6201B
NO
NO.
1
MIN
tw(RST)
MAX
UNIT
Width of the RESET pulse (PLL stable)†
*10
CLKOUT1
cycles
Width of the RESET pulse (PLL needs to sync up)‡
250
μs
†
This parameter applies to CLKMODE x1 when CLKIN is stable and applies to CLKMODE x4 when CLKIN and PLL are stable.
‡ This parameter only applies to CLKMODE x4. The RESET signal is not connected internally to the clock PLL circuit. The PLL, however, may
need up to 250 μs to stabilize following device power up or after PLL configuration has been changed. During that time, RESET must be asserted
to ensure proper device operation. See the clock PLL section for PLL lock times.
*Not production tested.
switching characteristics during reset§¶ (see Figure 26)
NO
NO.
§
¶
C6201B
PARAMETER
MIN
2
tR(RST)
Response time to change of value in RESET signal
3
td(CKO1H-CKO2IV)
Delay time, CLKOUT1 high to CLKOUT2 invalid
4
td(CKO1H-CKO2V)
Delay time, CLKOUT1 high to CLKOUT2 valid
5
td(CKO1H-SDCLKIV)
Delay time, CLKOUT1 high to SDCLK invalid
6
td(CKO1H-SDCLKV)
Delay time, CLKOUT1 high to SDCLK valid
7
td(CKO1H-SSCKIV)
Delay time, CLKOUT1 high to SSCLK invalid
8
td(CKO1H-SSCKV)
Delay time, CLKOUT1 high to SSCLK valid
9
td(CKO1H-LOWIV)
Delay time, CLKOUT1 high to low group invalid
10
td(CKO1H-LOWV)
Delay time, CLKOUT1 high to low group valid
11
td(CKO1H-HIGHIV)
Delay time, CLKOUT1 high to high group invalid
12
td(CKO1H-HIGHV)
Delay time, CLKOUT1 high to high group valid
13
td(CKO1H-ZHZ)
Delay time, CLKOUT1 high to Z group high impedance
14
td(CKO1H-ZV)
Low group consists of:
High group consists of:
Z group consists of:
Delay time, CLKOUT1 high to Z group valid
MAX
UNIT
CLKOUT1
cycles
2
*--1
ns
10
*--1
ns
ns
10
*--1
ns
ns
10
*--1
ns
ns
*10
*--1
ns
ns
*10
*--1
ns
ns
*10
ns
IACK, INUM[3:0], DMAC[3:0], PD, TOUT0, and TOUT1
HINT
EA[21:2], ED[31:0], CE[3:0], BE[3:0], ARE, AWE, AOE, SSADS, SSOE, SSWE, SDA10, SDRAS, SDCAS,
SDWE, HD[15:0], CLKX0, CLKX1, FSX0, FSX1, DX0, DX1, CLKR0, CLKR1, FSR0, and FSR1.
HRDY is gated by input HCS.
If HCS = 0 at device reset, HRDY belongs to the high group.
If HCS = 1 at device reset, HRDY belongs to the low group.
*Not production tested.
POST OFFICE BOX 1443
• HOUSTON, TEXAS 77251--1443
45
SM320C6201B, SMJ320C6201B
DIGITAL SIGNAL PROCESSOR
SGUS031B -- APRIL 2000 -- REVISED AUGUST 2001
RESET TIMING (CONTINUED)
CLKOUT1
1
2
2
RESET
3
4
5
6
7
8
9
10
11
12
13
14
CLKOUT2
SDCLK
SSCLK
LOW GROUP†‡
HIGH GROUP†‡
Z GROUP†‡
†
Low group consists of:
High group consists of:
Z group consists of:
‡
HRDY is gated by input HCS.
If HCS = 0 at device reset, HRDY belongs to the high group.
If HCS = 1 at device reset, HRDY belongs to the low group.
IACK, INUM[3:0], DMAC[3:0], PD, TOUT0, and TOUT1
HINT
EA[21:2], ED[31:0], CE[3:0], BE[3:0], ARE, AWE, AOE, SSADS, SSOE, SSWE, SDA10, SDRAS, SDCAS,
SDWE, HD[15:0], CLKX0, CLKX1, FSX0, FSX1, DX0, DX1, CLKR0, CLKR1, FSR0, and FSR1.
Figure 26. Reset Timing
46
POST OFFICE BOX 1443
• HOUSTON, TEXAS 77251--1443
SM320C6201B, SMJ320C6201B
DIGITAL SIGNAL PROCESSOR
SGUS031B -- APRIL 2000 -- REVISED AUGUST 2001
EXTERNAL INTERRUPT TIMING
timing requirements for interrupt response cycles†‡ (see Figure 27)
C6201B
NO
NO.
MIN
MAX
UNIT
2
tw(ILOW)
Width of the interrupt pulse low
*2P
ns
3
tw(IHIGH)
Width of the interrupt pulse high
*2P
ns
†
Interrupt signals are synchronized internally and are potentially recognized one cycle later if setup and hold times are violated. Thus, they can
be connected to asynchronous inputs.
‡ P = 1/CPU clock frequency in ns. For example, when running parts at 200 MHz, use P = 5 ns.
*Not production tested.
switching characteristics during interrupt response cycles§ (see Figure 27)
NO
NO.
C6201B
PARAMETER
MIN
1
tR(EINTH-IACKH)
Response time, EXT_INTx high to IACK high
*9P
4
td(CKO2L-IACKV)
Delay time, CLKOUT2 low to IACK valid
*--4
5
td(CKO2L-INUMV)
Delay time, CLKOUT2 low to INUMx valid
6
td(CKO2L-INUMIV)
Delay time, CLKOUT2 low to INUMx invalid
MAX
UNIT
ns
*--4
6
ns
6
ns
ns
§
P = 1/CPU clock frequency in ns. For example, when running parts at 200 MHz, use P = 5 ns.
When the PLL is used (CLKMODE x4), 0.5P = 1/(2 × CPU clock frequency).
For CLKMODE x1: 0.5P = PH, where PH is the high period of CLKIN.
*Not production tested.
1
CLKOUT2
2
3
EXT_INTx, NMI
Intr Flag
4
4
IACK
6
5
INUMx
Interrupt Number
Figure 27. Interrupt Timing
POST OFFICE BOX 1443
• HOUSTON, TEXAS 77251--1443
47
SM320C6201B, SMJ320C6201B
DIGITAL SIGNAL PROCESSOR
SGUS031B -- APRIL 2000 -- REVISED AUGUST 2001
HOST-PORT INTERFACE TIMING
timing requirements for host-port interface cycles†‡ (see Figure 28, Figure 29, Figure 30, and
Figure 31)
C6201B
NO
NO.
MIN
MAX
UNIT
1
tsu(SEL-HSTBL)
Setup time, select signals§ valid before HSTROBE low
4
ns
2
th(HSTBL-SEL)
Hold time, select signals§ valid after HSTROBE low
2
ns
3
tw(HSTBL)
Pulse duration, HSTROBE low
2P
ns
4
tw(HSTBH)
Pulse duration, HSTROBE high between consecutive accesses
*2P
ns
10
tsu(SEL-HASL)
Setup time, select signals§ valid before HAS low
4
ns
signals§
11
th(HASL-SEL)
Hold time, select
2
ns
12
tsu(HDV-HSTBH)
Setup time, host data valid before HSTROBE high
valid after HAS low
4
ns
13
th(HSTBH-HDV)
Hold time, host data valid after HSTROBE high
2
ns
14
th(HRDYL-HSTBL)
Hold time, HSTROBE low after HRDY low. HSTROBE shoul not be inactivated
until HRDY is active (low); otherwise, HPI writes will not complete properly.
*1
ns
18
tsu(HASL-HSTBL)
Setup time, HAS low before HSTROBE low
*2
ns
19
th(HSTBL-HASL)
Hold time, HAS low after HSTROBE low
*2
ns
†
HSTROBE refers to the following logical operation on HCS, HDS1, and HDS2: [NOT(HDS1 XOR HDS2)] OR HCS.
‡ The effects of internal clock jitter are included at test. There is no need to adjust timing numbers for internal clock jitter. P = 1/CPU clock frequency
in ns. For example, when running parts at 200 MHz, use P = 5 ns.
§ Select signals include: HCNTRL[1:0], HR/W, and HHWIL.
*Not production tested.
switching characteristics during host-port interface cycles†‡ (see Figure 28, Figure 29, Figure 30,
and Figure 31)
NO
NO.
C6201B
PARAMETER
MIN
MAX
UNIT
5
td(HCS-HRDY)
Delay time, HCS to HRDY¶
*1
9
ns
6
td(HSTBL-HRDYH)
Delay time, HSTROBE low to HRDY high#
*3
12
ns
7
toh(HSTBL-HDLZ)
Output hold time, HD low impedance after HSTROBE low for an HPI read
*4
8
td(HDV-HRDYL)
Delay time, HD valid to HRDY low
9
toh(HSTBH-HDV)
Output hold time, HD valid after HSTROBE high
*1
*12
ns
15
td(HSTBH-HDHZ)
Delay time, HSTROBE high to HD high impedance
*3
*12
ns
16
td(HSTBL-HDV)
Delay time, HSTROBE low to HD valid
*2
*12
ns
*3
12
ns
17
td(HSTBH-HRDYH)
Delay time, HSTROBE high to HRDY
ns
*P -- 3 *P + 3
high||
†
ns
HSTROBE refers to the following logical operation on HCS, HDS1, and HDS2: [NOT(HDS1 XOR HDS2)] OR HCS.
‡ The effects of internal clock jitter are included at test. There is no need to adjust timing numbers for internal clock jitter. P = 1/CPU clock frequency
in ns. For example, when running parts at 200 MHz, use P = 5 ns.
¶ HCS enables HRDY, and HRDY is always low when HCS is high. The case where HRDY goes high when HCS falls indicates that HPI is busy
completing a previous HPID write or READ with autoincrement.
# This parameter is used during an HPID read. At the beginning of the first half-word transfer on the falling edge of HSTROBE, the HPI sends the
request to the DMA auxiliary channel, and HRDY remains high until the DMA auxiliary channel loads the requested data into HPID.
|| This parameter is used after the second half-word of an HPID write or autoincrement read. HRDY remains low if the access is not an HPID write
or autoincrement read. Reading or writing to HPIC or HPIA does not affect the HRDY signal.
*Not production tested.
48
POST OFFICE BOX 1443
• HOUSTON, TEXAS 77251--1443
SM320C6201B, SMJ320C6201B
DIGITAL SIGNAL PROCESSOR
SGUS031B -- APRIL 2000 -- REVISED AUGUST 2001
HOST-PORT INTERFACE TIMING (CONTINUED)
HAS
1
1
2
2
HCNTL[1:0]
1
1
2
2
HR/W
1
1
2
2
HHWIL
4
3
HSTROBE†
3
HCS
15
9
7
15
9
16
HD[15:0] (output)
1st Half-Word
5
2nd Half-Word
8
17
HRDY (case 1)
6
8
17
HRDY (case 2)
†
5
5
HSTROBE refers to the following logical operation on HCS, HDS1, and HDS2: [NOT(HDS1 XOR HDS2)] OR HCS.
Figure 28. HPI Read Timing (HAS Not Used, Tied High)
HAS
19
11
19
10
11
10
HCNTL[1:0]
11
10
11
10
HR/W
11
11
10
10
HHWIL
4
3
HSTROBE†
18
18
HCS
7
15
9
16
9
15
HD[15:0] (output)
1st half-word
5
8
2nd half-word
17
5
17
5
HRDY (case 1)
6
8
HRDY (case 2)
†
HSTROBE refers to the following logical operation on HCS, HDS1, and HDS2: [NOT(HDS1 XOR HDS2)] OR HCS.
Figure 29. HPI Read Timing (HAS Used)
POST OFFICE BOX 1443
• HOUSTON, TEXAS 77251--1443
49
SM320C6201B, SMJ320C6201B
DIGITAL SIGNAL PROCESSOR
SGUS031B -- APRIL 2000 -- REVISED AUGUST 2001
HOST-PORT INTERFACE TIMING (CONTINUED)
HAS
1
1
2
HCNTL[1:0]
12
2
12
13
13
HBE[1:0]
1
1
2
2
HR/W
1
1
2
2
HHWIL
3
14
HSTROBE†
3
4
HCS
12
12
13
13
HD[15:0] (input)
1st Half-Word
5
17
2nd Half-Word
5
HRDY
†
HSTROBE refers to the following logical operation on HCS, HDS1, and HDS2: [NOT(HDS1 XOR HDS2)] OR HCS.
Figure 30. HPI Write Timing (HAS Not Used, Tied High)
HAS
12
19
13
12
19
13
HBE[1:0]
11
10
11
10
HCNTL[1:0]
11
10
11
10
HR/W
11
10
11
10
HHWIL
3
14
HSTROBE†
4
18
18
HCS
12
13
12
13
HD[15:0] (input)
5
1st half-word
2nd half-word
17
HRDY
†
HSTROBE refers to the following logical operation on HCS, HDS1, and HDS2: [NOT(HDS1 XOR HDS2)] OR HCS.
Figure 31. HPI Write Timing (HAS Used)y
50
POST OFFICE BOX 1443
• HOUSTON, TEXAS 77251--1443
5
SM320C6201B, SMJ320C6201B
DIGITAL SIGNAL PROCESSOR
SGUS031B -- APRIL 2000 -- REVISED AUGUST 2001
MULTICHANNEL BUFFERED SERIAL PORT TIMING
timing requirements for McBSP†‡(see Figure 32)
C6201B
NO
NO.
MIN
MAX
UNIT
2
tc(CKRX)
Cycle time, CLKR/X
CLKR/X ext
*2P
ns
3
tw(CKRX)
Pulse duration, CLKR/X high or CLKR/X low
CLKR/X ext
*P -- 1
ns
5
tsu(FRH-CKRL)
Setup time,
time external FSR high before CLKR low
6
th(CKRL-FRH)
Hold time,
time external FSR high after CLKR low
7
tsu(DRV-CKRL)
Setup time
time, DR valid before CLKR low
8
th(CKRL-DRV)
Hold time
time, DR valid after CLKR low
10
tsu(FXH-CKXL)
Setup time,
time external FSX high before CLKX low
11
th(CKXL-FXH)
Hold time,
time external FSX high after CLKX low
CLKR int
*9
CLKR ext
2
CLKR int
*6
CLKR ext
3
CLKR int
8
CLKR ext
1
CLKR int
3
CLKR ext
4
CLKX int
9
CLKX ext
2
CLKX int
6
CLKX ext
3
ns
ns
ns
ns
ns
ns
†
CLKRP = CLKXP = FSRP = FSXP = 0. If polarity of any of the signals is inverted, then the timing references of that signal are also inverted.
P = 1/CPU clock frequency in ns. For example, when running parts at 200 MHz, use P = 5 ns.
*Not production tested
‡
POST OFFICE BOX 1443
• HOUSTON, TEXAS 77251--1443
51
SM320C6201B, SMJ320C6201B
DIGITAL SIGNAL PROCESSOR
SGUS031B -- APRIL 2000 -- REVISED AUGUST 2001
MULTICHANNEL BUFFERED SERIAL PORT TIMING (CONTINUED)
switching characteristics for McBSP†‡§ (see Figure 32)
NO
NO.
C6201B
PARAMETER
1
td(CKSH-CKRXH)
Delay time, CLKS high to CLKR/X high for internal CLKR/X
generated from CLKS input
2
tc(CKRX)
Cycle time, CLKR/X
MIN
MAX
3
10
CLKR/X int
2P
1.6¶
ns
ns
Pulse duration, CLKR/X high or CLKR/X low
CLKR/X int
td(CKRH-FRV)
Delay time, CLKR high to internal FSR valid
CLKR int
*--2.5
3
CLKX int
*--2
3
CLKX ext
*3
*9
CLKX int
*--1
*4
CLKX ext
*3
*9
CLKX int
*--1
*4
CLKX ext
*3
*9
Dela time,
Delay
time CLKX high to internal FSX valid
alid
12
tdis(CKXH-DXHZ)
Disable time, DX high impedance following last data bit from
CLKX high
13
td(CKXH-DXV)
Dela time,
Delay
time CLKX high to DX valid
alid
14
td(FXH-DXV)
*C +
ns
tw(CKRX)
4
td(CKXH-FXV)
ns
1¶
3
9
*C --
UNIT
Delay time, FSX high to DX valid
FSX int
*--1
*3
ONLY applies when in data
delay 0 (XDATDLY = 00b) mode
FSX ext
*3
*9
ns
ns
ns
ns
†
CLKRP = CLKXP = FSRP = FSXP = 0. If polarity of any of the signals is inverted, then the timing references of that signal are also inverted.
Minimum delay times also represent minimum output hold times.
§ P = 1/CPU clock frequency in ns. For example, when running parts at 200 MHz, use P = 5 ns.
*Not production tested.
¶ C = H or L
S = sample rate generator input clock = P if CLKSM = 1 (P = 1/CPU clock frequency)
= sample rate generator input clock = P_clks if CLKSM = 0 (P_clks = CLKS period)
H = CLKX high pulse width = (CLKGDV/2 + 1) * S if CLKGDV is even
= (CLKGDV + 1)/2 * S if CLKGDV is odd or zero
L = CLKX low pulse width = (CLKGDV/2) * S if CLKGDV is even
= (CLKGDV + 1)/2 * S if CLKGDV is odd or zero
‡
52
POST OFFICE BOX 1443
• HOUSTON, TEXAS 77251--1443
SM320C6201B, SMJ320C6201B
DIGITAL SIGNAL PROCESSOR
SGUS031B -- APRIL 2000 -- REVISED AUGUST 2001
MULTICHANNEL BUFFERED SERIAL PORT TIMING (CONTINUED)
CLKS
1
2
3
3
CLKR
4
FSR (int)
4
5
6
FSR (ext)
7
DR
2
3
8
Bit(n-1)
(n-2)
(n-3)
3
CLKX
9
FSX (int)
10
11
FSX (ext)
FSX (XDATDLY=00b)
12
DX
Bit 0
14
13
Bit(n-1)
13
(n-2)
(n-3)
Figure 32. McBSP Timings
POST OFFICE BOX 1443
• HOUSTON, TEXAS 77251--1443
53
SM320C6201B, SMJ320C6201B
DIGITAL SIGNAL PROCESSOR
SGUS031B -- APRIL 2000 -- REVISED AUGUST 2001
MULTICHANNEL BUFFERED SERIAL PORT TIMING (CONTINUED)
timing requirements for FSR when GSYNC = 1 (see Figure 33)
C6201B
NO
NO.
MIN
MAX
UNIT
1
tsu(FRH-CKSH)
Setup time, FSR high before CLKS high
4
ns
2
th(CKSH-FRH)
Hold time, FSR high after CLKS high
4
ns
CLKS
1
FSR External
2
CLKR/X (no need to resync)
CLKR/X (needs resync)
Figure 33. FSR Timing When GSYNC = 1
timing requirements for McBSP as SPI master or slave: CLKSTP = 10b, CLKXP = 0†‡ (see Figure 34)
C6201B
MASTER
NO.
MIN
4
tsu(DRV-CKXL)
Setup time, DR valid before CLKX low
5
th(CKXL-DRV)
Hold time, DR valid after CLKX low
†
MAX
POST OFFICE BOX 1443
• HOUSTON, TEXAS 77251--1443
UNIT
MAX
12
2 -- 3P
ns
4
5 + 6P
ns
P = 1/CPU clock frequency in ns. For example, when running parts at 200 MHz, use P = 5 ns.
‡ For all SPI slave modes, CLKG is programmed as 1/2 of the CPU clock by setting CLKSM = CLKGDV = 1.
54
SLAVE
MIN
SM320C6201B, SMJ320C6201B
DIGITAL SIGNAL PROCESSOR
SGUS031B -- APRIL 2000 -- REVISED AUGUST 2001
MULTICHANNEL BUFFERED SERIAL PORT TIMING (CONTINUED)
switching characteristics for McBSP as SPI master or slave: CLKSTP = 10b, CLKXP = 0†‡
(see Figure 34)
C6201B
NO.
MASTER§
PARAMETER
SLAVE
MIN
MAX
th(CKXL-FXL)
Hold time, FSX low after CLKX low¶
T -- 2
*T + 3
2
td(FXL-CKXH)
Delay time, FSX low to CLKX
high#
*L -- 2
L+3
3
td(CKXH-DXV)
Delay time, CLKX high to DX valid
*--2
4
6
tdis(CKXL-DXHZ)
Disable time, DX high impedance following last data bit from
CLKX low
*L -- 2
*L + 3
7
tdis(FXH-DXHZ)
Disable time, DX high impedance following last data bit from
FSX high
8
td(FXL-DXV)
Delay time, FSX low to DX valid
1
MIN
UNIT
MAX
ns
ns
*3P + 4
5P + 17
ns
ns
*P + 3
*3P + 17
ns
*2P + 2
4P + 17
ns
†
P = 1/CPU clock frequency in ns. For example, when running parts at 200 MHz, use P = 5 ns.
‡ For all SPI slave modes, CLKG is programmed as 1/2 of the CPU clock by setting CLKSM = CLKGDV = 1.
§ S = sample rate generator input clock = P if CLKSM = 1 (P = 1/CPU clock frequency)
= sample rate generator input clock = P_clks if CLKSM = 0 (P_clks = CLKS period)
T = CLKX period = (1 + CLKGDV) * S
H = CLKX high pulse width = (CLKGDV/2 + 1) * S if CLKGDV is even
= (CLKGDV + 1)/2 * S if CLKGDV is odd or zero
L = CLKX low pulse width = (CLKGDV/2) * S if CLKGDV is even
= (CLKGDV + 1)/2 * S if CLKGDV is odd or zero
¶ FSRP = FSXP = 1. As a SPI master, FSX is inverted to provide active-low slave-enable output. As a slave, the active-low signal input on FSX
and FSR is inverted before being used internally.
CLKXM = FSXM = 1, CLKRM = FSRM = 0 for master McBSP
CLKXM = CLKRM = FSXM = FSRM = 0 for slave McBSP
*Not production tested.
# FSX should be low before the rising edge of clock to enable slave devices and then begin a SPI transfer at the rising edge of the master clock
(CLKX).
CLKX
1
2
FSX
7
6
DX
8
3
Bit 0
Bit(n-1)
4
DR
Bit 0
(n-2)
(n-3)
(n-4)
5
Bit(n-1)
(n-2)
(n-3)
(n-4)
Figure 34. McBSP Timing as SPI Master or Slave: CLKSTP = 10b, CLKXP = 0
¶
FSRP = FSXP = 1. As a SPI master, FSX is inverted to provide active-low slave-enable output. As a slave, the active-low signal input on FSX
and FSR is inverted before being used internally.
CLKXM = FSXM = 1, CLKRM = FSRM = 0 for master McBSP
CLKXM = CLKRM = FSXM = FSRM = 0 for slave McBSP
# FSX should be low before the rising edge of clock to enable slave devices and then begin a SPI transfer at the rising edge of the master clock
(CLKX).
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55
SM320C6201B, SMJ320C6201B
DIGITAL SIGNAL PROCESSOR
SGUS031B -- APRIL 2000 -- REVISED AUGUST 2001
MULTICHANNEL BUFFERED SERIAL PORT TIMING (CONTINUED)
timing requirements for McBSP as SPI master or slave: CLKSTP = 11b, CLKXP = 0†‡ (see Figure 35)
C6201B
MASTER
NO.
MIN
4
tsu(DRV-CKXH)
Setup time, DR valid before CLKX high
5
th(CKXH-DRV)
Hold time, DR valid after CLKX high
SLAVE
MAX
MIN
UNIT
MAX
12
2 -- 3P
ns
4
5 + 6P
ns
†
P = 1/CPU clock frequency in ns. For example, when running parts at 200 MHz, use P = 5 ns.
‡ For all SPI slave modes, CLKG is programmed as 1/2 of the CPU clock by setting CLKSM = CLKGDV = 1.
switching characteristics for McBSP as SPI master or slave: CLKSTP = 11b, CLKXP = 0†‡
(see Figure 35)
C6201B
NO.
MASTER§
PARAMETER
SLAVE
MIN
MAX
MIN
UNIT
MAX
1
th(CKXL-FXL)
Hold time, FSX low after CLKX low¶
L -- 2
*L + 3
ns
2
td(FXL-CKXH)
Delay time, FSX low to CLKX high#
*T -- 2
T+3
ns
3
td(CKXL-DXV)
Delay time, CLKX low to DX valid
*--2
4
*3P + 4
5P + 17
ns
6
tdis(CKXL-DXHZ)
Disable time, DX high impedance following last data bit
from CLKX low
*--2
*4
*3P + 3
*5P + 17
ns
7
td(FXL-DXV)
Delay time, FSX low to DX valid
*H -- 2
H+4
*2P + 2
4P + 17
ns
†
P = 1/CPU clock frequency in ns. For example, when running parts at 200 MHz, use P = 5 ns.
For all SPI slave modes, CLKG is programmed as 1/2 of the CPU clock by setting CLKSM = CLKGDV = 1.
§ S = sample rate generator input clock = P if CLKSM = 1 (P = 1/CPU clock frequency)
= sample rate generator input clock = P_clks if CLKSM = 0 (P_clks = CLKS period)
T = CLKX period = (1 + CLKGDV) * S
H = CLKX high pulse width = (CLKGDV/2 + 1) * S if CLKGDV is even
= (CLKGDV + 1)/2 * S if CLKGDV is odd or zero
L = CLKX low pulse width = (CLKGDV/2) * S if CLKGDV is even
= (CLKGDV + 1)/2 * S if CLKGDV is odd or zero
¶ FSRP = FSXP = 1. As a SPI master, FSX is inverted to provide active-low slave-enable output. As a slave, the active-low signal input on FSX
and FSR is inverted before being used internally.
CLKXM = FSXM = 1, CLKRM = FSRM = 0 for master McBSP
CLKXM = CLKRM = FSXM = FSRM = 0 for slave McBSP
*Not production tested.
# FSX should be low before the rising edge of clock to enable slave devices and then begin a SPI transfer at the rising edge of the master clock
(CLKX).
‡
CLKX
1
2
6
Bit 0
7
FSX
DX
3
Bit(n-1)
4
DR
Bit 0
(n-2)
(n-3)
(n-4)
5
Bit(n-1)
(n-2)
(n-3)
(n-4)
Figure 35. McBSP Timing as SPI Master or Slave: CLKSTP = 11b, CLKXP = 0
56
POST OFFICE BOX 1443
• HOUSTON, TEXAS 77251--1443
SM320C6201B, SMJ320C6201B
DIGITAL SIGNAL PROCESSOR
SGUS031B -- APRIL 2000 -- REVISED AUGUST 2001
MULTICHANNEL BUFFERED SERIAL PORT TIMING (CONTINUED)
timing requirements for McBSP as SPI master or slave: CLKSTP = 10b, CLKXP = 1†‡ (see Figure 36)
C6201B
MASTER
NO.
MIN
4
tsu(DRV-CKXH)
Setup time, DR valid before CLKX high
5
th(CKXH-DRV)
Hold time, DR valid after CLKX high
SLAVE
MAX
MIN
UNIT
MAX
12
2 -- 3P
ns
4
5 + 6P
ns
†
P = 1/CPU clock frequency in ns. For example, when running parts at 200 MHz, use P = 5 ns.
‡ For all SPI slave modes, CLKG is programmed as 1/2 of the CPU clock by setting CLKSM = CLKGDV = 1.
switching characteristics for McBSP as SPI master or slave: CLKSTP = 10b, CLKXP = 1†‡
(see Figure 36)
C6201B
NO.
MASTER§
PARAMETER
1
th(CKXH-FXL)
Hold time, FSX low after CLKX high¶
2
td(FXL-CKXL)
Delay time, FSX low to CLKX low#
3
td(CKXL-DXV)
Delay time, CLKX low to DX valid
6
tdis(CKXH-DXHZ)
Disable time, DX high impedance following last data bit
from CLKX high
7
tdis(FXH-DXHZ)
Disable time, DX high impedance following last data bit
from FSX high
8
td(FXL-DXV)
Delay time, FSX low to DX valid
SLAVE
MIN
MAX
MIN
UNIT
MAX
T -- 2
*T + 3
ns
*H -- 2
H+3
ns
*--2
4
*H -- 2
*H + 3
*3P + 4
5P + 17
ns
ns
*P + 3
*3P + 17
ns
*2P + 2
4P + 17
ns
†
P = 1/CPU clock frequency in ns. For example, when running parts at 200 MHz, use P = 5 ns.
For all SPI slave modes, CLKG is programmed as 1/2 of the CPU clock by setting CLKSM = CLKGDV = 1.
§ S = sample rate generator input clock = P if CLKSM = 1 (P = 1/CPU clock frequency)
= sample rate generator input clock = P_clks if CLKSM = 0 (P_clks = CLKS period)
T = CLKX period = (1 + CLKGDV) * S
H = CLKX high pulse width = (CLKGDV/2 + 1) * S if CLKGDV is even
= (CLKGDV + 1)/2 * S if CLKGDV is odd or zero
L = CLKX low pulse width = (CLKGDV/2) * S if CLKGDV is even
= (CLKGDV + 1)/2 * S if CLKGDV is odd or zero
¶ FSRP = FSXP = 1. As a SPI master, FSX is inverted to provide active-low slave-enable output. As a slave, the active-low signal input on FSX
and FSR is inverted before being used internally.
CLKXM = FSXM = 1, CLKRM = FSRM = 0 for master McBSP
CLKXM = CLKRM = FSXM = FSRM = 0 for slave McBSP
*Not production tested.
# FSX should be low before the rising edge of clock to enable slave devices and then begin a SPI transfer at the rising edge of the master clock
(CLKX).
‡
CLKX
1
2
FSX
7
6
DX
8
3
Bit 0
Bit(n-1)
4
DR
Bit 0
(n-2)
(n-3)
(n-4)
5
Bit(n-1)
(n-2)
(n-3)
(n-4)
Figure 36. McBSP Timing as SPI Master or Slave: CLKSTP = 10b, CLKXP = 1
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57
SM320C6201B, SMJ320C6201B
DIGITAL SIGNAL PROCESSOR
SGUS031B -- APRIL 2000 -- REVISED AUGUST 2001
MULTICHANNEL BUFFERED SERIAL PORT TIMING (CONTINUED)
timing requirements for McBSP as SPI master or slave: CLKSTP = 11b, CLKXP = 1†‡ (see Figure 37)
C6201B
MASTER
NO.
MIN
4
tsu(DRV-CKXL)
Setup time, DR valid before CLKX low
5
th(CKXL-DRV)
Hold time, DR valid after CLKX low
SLAVE
MAX
MIN
UNIT
MAX
12
2 -- 3P
ns
4
5 + 6P
ns
†
P = 1/CPU clock frequency in ns. For example, when running parts at 200 MHz, use P = 5 ns.
‡ For all SPI slave modes, CLKG is programmed as 1/2 of the CPU clock by setting CLKSM = CLKGDV = 1.
switching characteristics for McBSP as SPI master or slave: CLKSTP = 11b, CLKXP = 1†‡
(see Figure 37)
C6201B
NO.
MASTER§
PARAMETER
SLAVE
MIN
MAX
MIN
UNIT
MAX
1
th(CKXH-FXL)
Hold time, FSX low after CLKX high¶
H -- 2
*H + 3
ns
2
td(FXL-CKXL)
Delay time, FSX low to CLKX low#
*T -- 2
T+1
ns
3
td(CKXH-DXV)
Delay time, CLKX high to DX valid
*--2
4
*3P + 3
5P + 17
ns
6
tdis(CKXH-DXHZ)
Disable time, DX high impedance following last data bit
from CLKX high
*--2
*4
*3P + 3
*5P + 17
ns
7
td(FXL-DXV)
Delay time, FSX low to DX valid
*L -- 2
L+4
*2P + 2
4P + 17
ns
†
P = 1/CPU clock frequency in ns. For example, when running parts at 200 MHz, use P = 5 ns.
For all SPI slave modes, CLKG is programmed as 1/2 of the CPU clock by setting CLKSM = CLKGDV = 1.
§ S = sample rate generator input clock = P if CLKSM = 1 (P = 1/CPU clock frequency)
= sample rate generator input clock = P_clks if CLKSM = 0 (P_clks = CLKS period)
T = CLKX period = (1 + CLKGDV) * S
H = CLKX high pulse width = (CLKGDV/2 + 1) * S if CLKGDV is even
= (CLKGDV + 1)/2 * S if CLKGDV is odd or zero
L = CLKX low pulse width = (CLKGDV/2) * S if CLKGDV is even
= (CLKGDV + 1)/2 * S if CLKGDV is odd or zero
¶ FSRP = FSXP = 1. As a SPI master, FSX is inverted to provide active-low slave-enable output. As a slave, the active-low signal input on FSX
and FSR is inverted before being used internally.
CLKXM = FSXM = 1, CLKRM = FSRM = 0 for master McBSP
CLKXM = CLKRM = FSXM = FSRM = 0 for slave McBSP
*Not production tested.
# FSX should be low before the rising edge of clock to enable slave devices and then begin a SPI transfer at the rising edge of the master clock
(CLKX).
‡
CLKX
1
2
FSX
7
6
DX
3
Bit 0
Bit(n-1)
4
DR
Bit 0
(n-2)
(n-3)
(n-4)
5
Bit(n-1)
(n-2)
(n-3)
(n-4)
Figure 37. McBSP Timing as SPI Master or Slave: CLKSTP = 11b, CLKXP = 1
58
POST OFFICE BOX 1443
• HOUSTON, TEXAS 77251--1443
SM320C6201B, SMJ320C6201B
DIGITAL SIGNAL PROCESSOR
SGUS031B -- APRIL 2000 -- REVISED AUGUST 2001
DMAC, TIMER, POWER-DOWN TIMING
switching characteristics for DMAC outputs (see Figure 38)
NO
NO.
1
C6201B
PARAMETER
td(CKO1H-DMACV)
Delay time, CLKOUT1 high to DMAC valid
MIN
MAX
*2
10
UNIT
ns
*Not production tested.
CLKOUT1
1
1
DMAC[0:3]
Figure 38. DMAC Timing
timing requirements for timer inputs† (see Figure 39)
C6201B
NO
NO.
1
MIN
tw(TINP)
Pulse duration, TINP high or low
MAX
*2P
UNIT
ns
†
P = 1/CPU clock frequency in ns. For example, when running parts at 200 MHz, use P = 5 ns.
*Not production tested.
switching characteristics for timer outputs (see Figure 39)
NO
NO.
2
C6201B
PARAMETER
td(CKO1H-TOUTV)
Delay time, CLKOUT1 high to TOUT valid
MIN
MAX
*2
9
UNIT
ns
*Not production tested.
CLKOUT1
1
TINP
2
2
TOUT
Figure 39. Timer Timing
switching characteristics for power-down outputs (see Figure 40)
NO
NO.
1
C6201B
PARAMETER
td(CKO1H-PDV)
Delay time, CLKOUT1 high to PD valid
MIN
MAX
*2
9
UNIT
ns
*Not production tested.
CLKOUT1
1
1
PD
Figure 40. Power-Down Timing
POST OFFICE BOX 1443
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59
SM320C6201B, SMJ320C6201B
DIGITAL SIGNAL PROCESSOR
SGUS031B -- APRIL 2000 -- REVISED AUGUST 2001
JTAG TEST-PORT TIMING
timing requirements for JTAG test port (see Figure 41)
C6201B
NO
NO.
MIN
MAX
UNIT
1
tc(TCK)
Cycle time, TCK
*50
ns
3
tsu(TDIV-TCKH)
Setup time, TDI/TMS/TRST valid before TCK high
*10
ns
4
th(TCKH-TDIV)
Hold time, TDI/TMS/TRST valid after TCK high
*5
ns
*Not production tested.
switching characteristics for JTAG test port (see Figure 41)
NO
NO.
2
C6201B
PARAMETER
td(TCKL-TDOV)
Delay time, TCK low to TDO valid
MIN
MAX
*0
*15
*Not production tested.
1
TCK
2
2
TDO
3
TDI/TMS/TRST
Figure 41. JTAG Test-Port Timing
60
POST OFFICE BOX 1443
• HOUSTON, TEXAS 77251--1443
4
UNIT
ns
SM320C6201B, SMJ320C6201B
DIGITAL SIGNAL PROCESSOR
SGUS031B -- APRIL 2000 -- REVISED AUGUST 2001
MECHANICAL DATA
GLP (S-CBGA-N429)
CERAMIC BALL GRID ARRAY
27,20
SQ
26,80
25,40 TYP
1,27
AA
Y
W
V
U
T
R
P
N
M
L
K
J
H
G
F
E
D
C
B
A
1,27
1
1,22
1,00
2
3
4
5
6
7
8
9
10
11 13 15 17 19 21
12 14 16 18 20
3,30 MAX
Seating Plane
0,90
0,60
NOTES: A.
B.
C.
D.
E.
F.
∅ 0,10 M
0,70
0,50
0,15
4164732/A 08/98
All linear dimensions are in millimeters.
This drawing is subject to change without notice.
Falls within JEDEC MO-156
Flip chip application only
For 320C6201B (1.8 V core device).
Package weight for GLP is 7.65 grams.
thermal resistance characteristics (S-CBGA package)
NO
°C/W
Air Flow
3.0
N/A
Junction-to-Case, measured to the top of the package lid
7.3
N/A
Junction-to-Ambient
14.5
0
11.8
150 fpm
1
RΘJC
Junction-to-Case, measured to the bottom of solder ball
2
RΘJC
3
RΘJA
4
5
RΘJMA
Junction-to-Moving-Air
Junction
to Moving Air
6
7
RΘJB
Junction-to-Board, measured by soldering a thermocouple to one of the middle
traces on the board at the edge of the package
POST OFFICE BOX 1443
• HOUSTON, TEXAS 77251--1443
11.1
250 fpm
10.2
500 fpm
6.2
N/A
61
PACKAGE OPTION ADDENDUM
www.ti.com
6-Oct-2018
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (°C)
Device Marking
(4/5)
5962-9857801QXA
ACTIVE
CFCBGA
GLP
429
1
TBD
SNPB
N / A for Pkg Type
-55 to 115
5962-9857801QX
A
SMJ320C6201BGL
PW15
SMJ320C6201BGLPW15
ACTIVE
CFCBGA
GLP
429
1
TBD
SNPB
N / A for Pkg Type
-55 to 115
5962-9857801QX
A
SMJ320C6201BGL
PW15
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
6-Oct-2018
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
OTHER QUALIFIED VERSIONS OF SM320C6201B :
• Military: SMJ320C6201B
NOTE: Qualified Version Definitions:
• Military - QML certified for Military and Defense Applications
Addendum-Page 2
MECHANICAL DATA
MCBG004A – SEPTEMBER 1998 – REVISED JANUARY 2002
GLP (S-CBGA-N429)
CERAMIC BALL GRID ARRAY
27,20
SQ
26,80
25,40 TYP
1,27
1
A1 Corner
1,22
1,00
1,27
AA
Y
W
V
U
T
R
P
N
M
L
K
J
H
G
F
E
D
C
B
A
3
2
5
4
9
7
6
8
11 13 15 17 19 21
10 12 14 16 18 20
Bottom View
3,30 MAX
Seating Plane
0,90
0,60
NOTES: A.
B.
C.
D.
∅ 0,10 M
0,70
0,50
0,15
4164732/B 11/01
All linear dimensions are in millimeters.
This drawing is subject to change without notice.
Falls within JEDEC MO-156
Flip chip application only
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
1
IMPORTANT NOTICE AND DISCLAIMER
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IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD
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TI products for your application, (2) designing, validating and testing your application, and (3) ensuring your application meets applicable
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