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Texas Instruments Digital Signal Processor Datasheet
TMS320C40
DIGITAL SIGNAL PROCESSOR
SPRS038 – JANUARY 1996
D
D
D
D
D
D
D
D
D
D
D
D
D
D
Highest Performance Floating-Point Digital
Signal Processor (DSP)
– ’320C40-60:
33-ns Instruction Cycle Time,
330 MOPS, 60 MFLOPS,
30 MIPS, 384M Bytes / s
– ’320C40-50:
40-ns Instruction Cycle Time
– ’320C40-40:
50-ns Instruction Cycle Time
Six Communications Ports
Six-Channel Direct Memory Access (DMA)
Coprocessor
Single-Cycle Conversion to and From
IEEE-754 Floating-Point Format
Single Cycle, 1/x, 1/Ǹ x
Source-Code Compatible With TMS320C3x
Single-Cycle 40-Bit Floating-Point,
32-Bit Integer Multipliers
Twelve 40-Bit Registers, Eight Auxiliary
Registers, 14 Control Registers, and Two
Timers
IEEE 1149.1† (JTAG) Boundary Scan
Compatible
Two Identical External Data and Address
Buses Supporting Shared Memory Systems
and High Data-Rate, Single-Cycle
Transfers:
– High Port-Data Rate of 120M Bytes/s
(’C40-60) (Each Bus)
– 16G-Byte Continuous
Program/ Data / Peripheral Address
Space
– Memory-Access Request for Fast,
Intelligent Bus Arbitration
– Separate Address-Bus, Data-Bus, and
Control-Enable Pins
– Four Sets of Memory-Control Signals
Support Different Speed Memories in
Hardware
325-Pin Ceramic Grid Array (GF Suffix)
Fabricated Using 0.72-µm Enhanced
Performance Implanted CMOS (EPIC)
Technology by Texas Instruments (TI)
Software-Communication-Port Reset
NMI With Bus-Grant Feature
325-PIN GF GRID ARRAY PACKAGE
(BOTTOM VIEW)‡
AR
AP
AN
AM
AL
AK
AJ
AH
AG
AF
AE
AD
AC
AB
AA
Y
W
V
U
T
R
P
N
M
L
K
J
H
G
F
E
D
C
B
A
2
1
4
3
6
5
7
8 10 12 14 16 18 20 22 24 26 28 30 32 34
9 11 13 15 17 19 21 23 25 27 29 31 33 35
Pin A1
‡ See Pin Assignments table and Pin Functions table for location
and description of all pins.
D
D
D
D
Separate Internal Program, Data, and DMA
Coprocessor Buses for Support of Massive
Concurrent Input / Output (I/O) of Program
and Data Throughput, Maximizing
Sustained Central Processing Unit (CPU)
Performance
On-Chip Program Cache and
Dual-Access/Single-Cycle RAM for
Increased Memory-Access Performance
– 512-Byte Instruction Cache
– 8K Bytes of Single-Cycle Dual-Access
Program or Data RAM
– ROM-Based Boot Loader Supports
Program Bootup Using 8-, 16-, or 32-Bit
Memories or One of the Communication
Ports
IDLE2 Clock-Stop Power-Down Mode
5-V Operation
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
† IEEE Standard 1149.1–1990 Standard Test-Access Port and Boundary-Scan Architecture
EPIC and TI are trademarks of Texas Instruments Incorporated.
Copyright  1996, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
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1
TMS320C40
DIGITAL SIGNAL PROCESSOR
SPRS038 – JANUARY 1996
block diagram
Cache
(512 Bytes)
32
RAM Block 1
(4K Bytes)
RAM Block 0
(4K Bytes)
32
32
32
32
ROM Block
(Reserved)
32
32
32
Continued on next page
PDATA Bus
D(31–0)
A(30–0)
DE
AE
STAT(3 – 0)
LOCK
STRB0, STRB1
R / W0, R / W1
PAGE0, PAGE1
RDY0, RDY1
CE0, CE1
PADDR Bus
DDATA Bus
M
U
X
DADDR 1 Bus
DADDR 2 Bus
DMADATA Bus
DMAADDR Bus
32
32
32
MUX
IR
CPU1
PC
X1
X2/CLKIN
CPU2
REG1
ROMEN
RESET
C
P
U
1
NMI
IIOF(3 – 0)
IACK
H1
H3
CVSS
DVDD
DVSS
IVSS
LADVDD
LDDVDD
VDDL
VSSL
SUBS
Controller
RESETLOC0
RESETLOC1
R
E
G
1
R
E
G
2
REG2
40
40
40
40
32-Bit Barrel
Shifter
Multiplier
ALU
40
40
40
40
32
40
Extended
Precision
Registers
(R0–R11)
40
DISP, IR0, IR1
ARAU0
ARAU1
BK
32
32
32
32
32
32
32
Auxiliary
Registers
(AR0–AR7)
32
32
32
32
2
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Other
Registers
(14)
32
TMS320C40
DIGITAL SIGNAL PROCESSOR
SPRS038 – JANUARY 1996
PDATA Bus
LD31 – LD0
LA30 – LA0
LDE
LAE
LSTAT3 – LSTAT0
LLOCK
LSTRB0 – LSTRB1
LR / W0 – LR / W1
LPAGE0 – LPAGE1
LRDY0 – LRDY1
LCE0,LCE1
PADDR Bus
DDATA Bus
M
U
X
DADDR 1 Bus
DADDR 2 Bus
DMADATA Bus
DMAADDR Bus
MUX
DMA Coprocessor
DMA Channel 0
DMA Channel 1
DMA Channel 2
DMA Channel 3
DMA Channel 4
DMA Channel 5
Six DMA Channels
COM Port 0
Input
FIFO
PAU
Output
FIFO
Port-Control Registers
COM Port 5
Input
FIFO
PAU
Output
FIFO
CREQ0
CACK0
CSTRB0
CRDY0
C0D7–C0D0
CREQ5
CACK5
CSTRB5
CRDY5
C5D7– C5D0
Six Communication Ports
32
Peripheral Address Bus
32
Peripheral Data Bus
Continued from previous page
block diagram (continued)
Port-Control Registers
Timer 0
Global-Control Register
Time-Period Register
Timer-Counter Register
TCLK0
Timer 1
Global-Control Register
Time-Period Register
Timer-Counter Register
TCLK1
Port Control
Global
Local
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3
TMS320C40
DIGITAL SIGNAL PROCESSOR
SPRS038 – JANUARY 1996
functions
This section lists signal descriptions for the ’320C40 device. The ’320C40 pin functions table lists each signal,
number of pins, operating mode(s) (that is, input, output, or high-impedance state as indicated by I, O, or Z,
respectively), and function. The signals are grouped according to function.
Pin Functions
NO. OF
PINS
TYPE†
D31 – D0
32
I/O/Z
DE
1
I
A30 – A0
31
O/Z
AE
1
I
Address-bus-enable signal for the global-bus external interface
STAT3 – STAT0
4
O
Status signals for the global-bus external interface
LOCK
1
O
Lock signal for the global-bus external interface
STRB0‡
R / W0‡
1
O/Z
Access strobe 0 for the global-bus external interface
1
O/Z
Read / write signal for STRB0 accesses
PAGE0‡
RDY0‡
1
O/Z
Page signal for STRB0 accesses
1
I
Ready signal for STRB0 accesses
CE0‡
1
I
Control enable for the STRB0, PAGE0, and R / W0 signals
STRB1‡
R / W1‡
1
O/Z
Access strobe 1 for the global-bus external interface
1
O/Z
Read / write signal for STRB1 accesses
PAGE1‡
RDY1‡
1
O/Z
Page signal for STRB1 accesses
1
I
Ready signal for STRB1 accesses
CE1‡
1
I
NAME
DESCRIPTION
GLOBAL-BUS EXTERNAL INTERFACE ( 80 PINS)
32-bit data port of the global-bus external interface
Data-bus-enable signal for the global-bus external interface
31-bit address port of the global-bus external interface
Control enable for the STRB1, PAGE1, and R / W1 signals
LOCAL-BUS EXTERNAL INTERFACE ( 80 PINS)
LD31 – LD0
32
I/O/Z
32-bit data port of the local-bus external interface
LDE
1
I
LA30 – LA0
31
O/Z
Data-bus-enable signal for the local-bus external interface
LAE
1
I
Address-bus-enable signal for the local-bus external interface
LSTAT3 – LSTAT0
4
O
Status signals for the local-bus external interface
LLOCK
1
O
Lock signal for the local-bus external interface
LSTRB0‡
1
O/Z
Access strobe 0 for the local-bus external interface
LR / W0
1
O/Z
Read / write signal for LSTRB0 accesses
LPAGE0
1
O/Z
Page signal for LSTRB0 accesses
LRDY0
1
I
Ready signal for LSTRB0 accesses
LCE0
1
I
Control enable for the LSTRB0, LPAGE0, and LR / W0 signals
LSTRB1‡
1
O/Z
Access strobe 1 for the local-bus external interface
LR / W1
1
O/Z
Read / write signal for LSTRB1 accesses
LPAGE1
1
O/Z
Page signal for LSTRB1 accesses
LRDY1
1
I
Ready signal for LSTRB1 accesses
31-bit address port of the local-bus external interface
LCE1
1
I
Control enable for the LSTRB1, LPAGE1, and LR / W1 signals
† I = input, O = output, Z = high impedance
‡ Signal’s effective address range is defined by the local / global STRB ACTIVE bits.
4
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TMS320C40
DIGITAL SIGNAL PROCESSOR
SPRS038 – JANUARY 1996
Pin Functions ( Continued)
NAME
NO. OF
PINS
TYPE†
DESCRIPTION
COMMUNICATION PORT 0 INTERFACE ( 12 PINS)
C0D7 – C0D0
8
I/O
Communication port 0 data bus
CREQ0
1
I/O
Communication port 0 token-request signal
CACK0
1
I/O
Communication port 0 token-request-acknowledge signal
CSTRB0
1
I/O
Communication port 0 data-strobe signal
CRDY0
1
I/O
Communication port 0 data-ready signal
C1D7 – C1D0
8
I/O
Communication port 1 data bus
CREQ1
1
I/O
Communication port 1 token-request signal
CACK1
1
I/O
Communication port 1 token-request-acknowledge signal
CSTRB1
1
I/O
Communication port 1 data-strobe signal
CRDY1
1
I/O
COMMUNICATION PORT 1 INTERFACE ( 12 PINS)
Communication port 1 data-ready signal
COMMUNICATION PORT 2 INTERFACE ( 12 PINS)
C2D7 – C2D0
8
I/O
Communication port 2 data bus
CREQ2
1
I/O
Communication port 2 token-request signal
CACK2
1
I/O
Communication port 2 token-request-acknowledge signal
CSTRB2
1
I/O
Communication port 2 data-strobe signal
CRDY2
1
I/O
Communication port 2 data-ready signal
COMMUNICATION PORT 3 INTERFACE ( 12 PINS)
C3D7 – C3D0
8
I/O
Communication port 3 data bus
CREQ3
1
I/O
Communication port 3 token-request signal
CACK3
1
I/O
Communication port 3 token-request-acknowledge signal
CSTRB3
1
I/O
Communication port 3 data-strobe signal
CRDY3
1
I/O
Communication port 3 data-ready signal
COMMUNICATION PORT 4 INTERFACE ( 12 PINS)
C4D7 – C4D0
8
I/O
Communication port 4 data bus
CREQ4
1
I/O
Communication port 4 token-request signal
CACK4
1
I/O
Communication port 4 token-request-acknowledge signal
CSTRB4
1
I/O
Communication port 4 data-strobe signal
CRDY4
1
I/O
Communication port 4 data-ready signal
C5D7 – C5D0
8
I/O
Communication port 5 data bus
CREQ5
1
I/O
Communication port 5 token-request signal
CACK5
1
I/O
Communication port 5 token-request-acknowledge signal
CSTRB5
1
I/O
Communication port 5 data-strobe signal
COMMUNICATION PORT 5 INTERFACE ( 12 PINS)
CRDY5
1
I/O
† I = input, O = output, Z = high impedance
Communication port 5 data-ready signal
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TMS320C40
DIGITAL SIGNAL PROCESSOR
SPRS038 – JANUARY 1996
Pin Functions ( Continued)
NAME
NO. OF
PINS
TYPE†
DESCRIPTION
INTERRUPTS, I / O FLAGS, RESET, TIMER ( 12 PINS)
IIOF3 – IIOF0
4
I/O
NMI
1
I
Interrupt and I / O flags
Nonmaskable interrupt. NMI is sensitive to a low-going edge.
IACK
1
O
Interrupt acknowledge
RESET
1
I
Reset signal
RESETLOC1 –
RESETLOC0
2
I
Reset-vector location pins
ROMEN
1
I
On-chip ROM enable ( 0 = disable, 1 = enable)
TCLK0
1
I/O
Timer 0 pin
TCLK1
1
I/O
Timer 1 pin
CLOCK ( 4 PINS)
X1
1
O
Crystal pin
X2 / CLKIN
1
I
Crystal / oscillator pin
H1
1
O
H1 clock
H3
1
O
H3 clock
POWER ( 70 PINS)
CVSS
15
I
Ground pins
DVSS
15
I
Ground pins
IVSS
DVDD
6
I
Ground pins
13
I
GADVDD
3
I
5-VDC supply pins
5-VDC supply pins
GDDVDD
3
I
LADVDD
LDDVDD
3
I
3
I
SUBS
1
I
VDDL
VSSL
4
I
4
I
5-VDC supply pins
Ground pins
TCK
1
I
IEEE 1149.1 test port clock
TDO
1
O/Z
TDI
1
I
IEEE 1149.1 test port data in
TMS
1
I
IEEE 1149.1 test port mode select
TRST
1
I
IEEE 1149.1 test port reset
EMU0
1
I/O
5-VDC supply pins
5-VDC supply pins
5-VDC supply pins
Substrate pin ( tie to ground)
EMULATION ( 7 PINS)
EMU1
1
I/O
† I = input, O = output, Z = high impedance
6
IEEE 1149.1 test port data out
Emulation pin 0
Emulation pin 1
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TMS320C40
DIGITAL SIGNAL PROCESSOR
SPRS038 – JANUARY 1996
GF Package Pin Assignments — Alphabetical Listing
PIN
PIN
PIN
PIN
NAME
NO.
NAME
NO.
NAME
NO.
NAME
A0
D32
C0D6
AN7
C5D4
AM30
A1
B32
C0D7
AK8
C5D5
AP32
A2
D30
C1D0
AL7
C5D6
AM32
A3
C29
C1D1
AP8
C5D7
AL31
A4
B30
C1D2
AM8
CACK0
A5
F28
C1D3
AK12
A6
F24
C1D4
AK10
A7
E29
C1D5
A8
C27
C1D6
A9
D28
A10
A11
PIN
NO.
NAME
CVSS
E35
D31
F32
CVSS
AR25
DE
AA31
CVSS
AE1
DVDD
AR11
CVSS
AR13
DVDD
AR29
AN11
CVSS
A19
DVDD
A13
CACK1
AN13
CVSS
R35
DVDD
A7
CACK2
AM14
CVSS
AL1
DVDD
A17
AN9
CACK3
AM16
D0
U33
DVDD
L35
AL9
CACK4
AK32
D1
V32
DVDD
AR23
C1D7
AP10
CACK5
AJ31
D2
T34
DVDD
A29
B28
C2D0
AM18
CE0
AA33
D3
U31
DVDD
L1
F26
C2D1
AN19
CE1
V34
D4
R33
DVDD
AC1
A12
C25
C2D2
AL19
CRDY0
AP12
D5
P34
DVDD
AR17
A13
E27
C2D3
AP20
CRDY1
AP14
D6
T32
DVDD
A23
A14
B26
C2D4
AM20
CRDY2
AL15
D7
N33
DVDD
AJ1
A15
D26
C2D5
AN21
CRDY3
AL17
D8
R31
DVSS
AJ35
A16
C23
C2D6
AL21
CRDY4
AH30
D9
M34
DVSS
A21
A17
B24
C2D7
AP22
CRDY5
AH32
D10
P32
DVSS
A25
A18
E25
C3D0
AM22
CREQ0
AM10
D11
L33
DVSS
G35
A19
C21
C3D1
AN23
CREQ1
AM12
D12
N31
DVSS
A11
A20
D24
C3D2
AL23
CREQ2
AN15
D13
K34
DVSS
AG1
A21
B22
C3D3
AP24
CREQ3
AN17
D14
M32
DVSS
AM2
A22
E23
C3D4
AM24
CREQ4
AN33
D15
J33
DVSS
R1
A23
C19
C3D5
AN25
CREQ5
AL33
D16
L31
DVSS
AR21
A24
D22
C3D6
AL25
CSTRB0
AL11
D17
M30
DVSS
AR15
A25
B20
C3D7
AP26
CSTRB1
AL13
D18
K32
DVSS
A15
A26
E21
C4D0
AN27
CSTRB2
AP16
D19
H34
DVSS
AR27
A27
B18
C4D1
AM26
CSTRB3
AP18
D20
J31
DVSS
G1
A28
C17
C4D2
AK24
CSTRB4
AM34
D21
G33
DVSS
N35
A29
D20
C4D3
AL27
CSTRB5
AK34
D22
K30
DVSS
AR9
A30
B16
C4D4
AP28
CVSS
AR19
D23
F34
EMU0
AA35
AE
AG31
C4D5
AK26
CVSS
AR7
D24
H32
EMU1
AD34
C0D0
AP4
C4D6
AN29
CVSS
N1
D25
E33
GADVDD
B2
C0D1
AL5
C4D7
AM28
CVSS
AL35
D26
D34
GADVDD
AR1
C0D2
AN5
C5D0
AL29
CVSS
A27
D27
G31
GADVDD
U35
C0D3
AM4
C5D1
AP30
CVSS
A9
D28
C33
GDDVDD
V2
C0D4
AP6
C5D2
AK28
CVSS
E1
D29
H30
GDDVDD
A35
C0D5
AM6
C5D3
AN31
CVSS
J35
D30
E31
GDDVDD
A1
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NO.
7
TMS320C40
DIGITAL SIGNAL PROCESSOR
SPRS038 – JANUARY 1996
GF Package Pin Assignments — Alphabetical Listing (Continued)
PIN
8
PIN
PIN
PIN
NAME
NO.
NAME
NO.
NAME
NO.
NAME
NO.
H1
AC3
LA25
R5
LD26
B4
STAT0
AD32
H3
AC5
LA26
T2
LD27
F8
STAT1
AE33
IACK
W3
LA27
U3
LD28
D6
STAT2
AF34
IIOF0
AN3
LA28
T4
LD29
C3
STAT3
AE31
IIOF1
AL3
LA29
V4
LD30
E5
STRB0
AD30
IIOF2
AH6
LA30
U5
LD31
F6
STRB1
AC33
IIOF3
AK2
B34
LDDVDD
LDDVDD
AR35
SUBS
C31
IVSS
IVSS
LADVDD
LADVDD
AP2
TCK
Y34
AR31
U1
TCLK0
AE3
AD4
TCLK1
AD2
AR5
AB2
IVSS
IVSS
AG35
LADVDD
LAE
AP34
AB4
LDDVDD
LDE
A31
LCE0
AG5
LLOCK
AA5
TDO
AB34
IVSS
IVSS
J1
LCE1
AF2
LOCK
W33
TDI
AC35
A5
LD0
E19
LPAGE0
AH2
TMS
W35
LA0
D2
LD1
C15
LPAGE1
AG3
TRST
AE35
LA1
D4
LD2
D18
LRDY0
AF6
AN1
LA2
E3
LD3
B14
LRDY1
AE5
VDDL
VDDL
LA3
F4
LD4
E17
LR/W0
AH4
LA4
H6
LD5
D16
LR/W1
AF4
LA5
F2
LD6
C13
LSTAT0
AA3
LA6
G5
LD7
E15
LSTAT1
Y4
LA7
G3
LD8
B12
LSTAT2
Y2
H4
LD9
D14
LSTAT3
W5
VSSL
VSSL
AR33
LA8
LA9
H2
LD10
C11
LSTRB0
AJ3
X1
W1
X2 / CLKIN
AA1
LA10
K6
LD11
E13
LSTRB1
AD6
LA11
M6
LD12
B10
NMI
AJ5
LA12
J5
LD13
D12
PAGE0
AG33
LA13
J3
LD14
C9
PAGE1
AB32
LA14
K4
LD15
E11
RDY0
Y32
LA15
K2
LD16
F12
RDY1
W31
LA16
L3
LD17
D10
RESETLOC0
AF30
LA17
L5
LD18
B8
RESETLOC1
AH34
LA18
M2
LD19
E9
RESET
AJ33
LA19
M4
LD20
C7
ROMEN
AK4
LA20
N3
LD21
F10
R / W0
AF32
LA21
N5
LD22
B6
R / W1
AC31
LA22
P2
LD23
D8
LA23
P4
LD24
C5
LA24
R3
LD25
E7
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VDDL
VDDL
VSSL
VSSL
AN35
C35
C1
A3
AR3
A33
TMS320C40
DIGITAL SIGNAL PROCESSOR
SPRS038 – JANUARY 1996
GF Package Pin Assignments — Numerical Listing
PIN
PIN
PIN
PIN
NO.
NAME
NO.
NAME
NO.
NAME
NO.
NAME
A1
GDDVDD
AD30
STRB0
AK24
C4D2
AM30
C5D4
A3
VSSL
IVSS
AD32
STAT0
AK26
C4D5
AM32
C5D6
AD34
EMU1
AK28
C5D2
AM34
CSTRB4
DVDD
CVSS
AE1
CVSS
AK32
CACK4
AN1
AE3
TCLK0
AK34
CSTRB5
AN3
VDDL
IIOF0
A5
A7
A9
A11
A13
A15
A17
A19
A21
A23
A25
DVSS
DVDD
DVSS
AE5
LRDY1
AL1
CVSS
AN5
C0D2
AE31
STAT3
AL3
IIOF1
AN7
C0D6
AE33
STAT1
AL5
C0D1
AN9
C1D5
DVDD
CVSS
AE35
TRST
AL7
C1D0
AN11
CACK0
AF2
LCE1
AL9
C1D6
AN13
CACK1
DVSS
DVDD
DVSS
AF4
LR / W1
AL11
CSTRB0
AN15
CREQ2
AF6
LRDY0
AL13
CSTRB1
AN17
CREQ3
AF30
RESETLOC0
AL15
CRDY2
AN19
C2D1
CVSS
DVDD
AF32
R/W0
AL17
CRDY3
AN21
C2D5
AF34
STAT2
AL19
C2D2
AN23
C3D1
AG1
DVSS
LPAGE1
AL21
C2D6
AN25
C3D5
AG3
AL23
C3D2
AN27
C4D0
A35
IVSS
VSSL
GDDVDD
AG5
LCE0
AL25
C3D6
AN29
C4D6
AA1
X2 / CLKIN
AG31
AE
AL27
C4D3
AN31
C5D3
AA3
LSTAT0
AG33
PAGE0
AL29
C5D0
AN33
CREQ4
A27
A29
A31
A33
AA5
LLOCK
AG35
C5D7
AN35
DE
AH2
IVSS
LPAGE0
AL31
AA31
AL33
CREQ5
AP2
AA33
CE0
AH4
LR/W0
AL35
CVSS
AP4
VDDL
LDDVDD
C0D0
AA35
EMU0
AH6
IIOF2
AM2
DVSS
AP6
C0D4
AB2
AH30
CRDY4
AM4
C0D3
AP8
C1D1
AB4
LADVDD
LAE
AH32
CRDY5
AM6
C0D5
AP10
C1D7
AB32
PAGE1
AH34
RESETLOC1
AM8
C1D2
AP12
CRDY0
AB34
TDO
AJ1
DVDD
AM10
CREQ0
AP14
CRDY1
AC1
DVDD
H1
AJ3
LSTRB0
AM12
CREQ1
AP16
CSTRB2
AJ5
NMI
AM14
CACK2
AP18
CSTRB3
AC3
AC5
H3
AJ31
CACK5
AM16
CACK3
AP20
C2D3
AC31
R/W1
AJ33
RESET
AM18
C2D0
AP22
C2D7
AC33
STRB1
AJ35
DVSS
AM20
C2D4
AP24
C3D3
AC35
TDI
AK2
IIOF3
AM22
C3D0
AP26
C3D7
AD2
TCLK1
AK4
ROMEN
AM24
C3D4
AP28
C4D4
AD4
LDE
AK8
C0D7
AM26
C4D1
AP30
C5D1
AD6
LSTRB1
AK10
C1D4
AM28
C4D7
AP32
C5D5
AK12
C1D3
AP34
LADVDD
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9
TMS320C40
DIGITAL SIGNAL PROCESSOR
SPRS038 – JANUARY 1996
GF Package Pin Assignments — Numerical Listing (Continued)
PIN
PIN
PIN
PIN
NAME
NO.
NAME
NO.
NAME
NO.
NAME
NO.
NAME
AR1
GADVDD
C1
CVSS
H2
LA9
P2
LA22
C3
E3
LA2
H4
LA8
P4
LA23
AR5
VSSL
IVSS
VDDL
LD29
E1
AR3
C5
LD24
E5
LD30
H6
LA4
P32
D10
AR7
CVSS
C7
LD20
E7
LD25
H30
D29
P34
D5
AR9
DVSS
C9
LD14
E9
LD19
H32
D24
R1
DVSS
AR11
DVDD
C11
LD10
E11
LD15
H34
D19
R3
LA24
AR13
CVSS
C13
LD6
E13
LD11
J1
R5
LA25
AR15
C15
LD1
E15
LD7
J3
R31
D8
AR17
DVSS
DVDD
IVSS
LA13
C17
A28
E17
LD4
J5
LA12
R33
D4
AR19
CVSS
C19
A23
E19
LD0
J31
D20
R35
CVSS
AR21
DVSS
DVDD
C21
A19
E21
A26
J33
D15
T2
LA26
AR23
C23
A16
E23
A22
J35
CVSS
T4
LA28
AR25
CVSS
C25
A12
E25
A18
K2
LA15
T32
D6
AR27
DVSS
C27
A8
E27
A13
K4
LA14
T34
D2
AR29
DVDD
C29
A3
E29
A7
K6
LA10
U1
AR31
C31
SUBS
E31
D30
K30
D22
U3
C33
D28
E33
D25
K32
D18
U5
LA30
AR35
IVSS
VSSL
LDDVDD
LDDVDD
LA27
C35
E35
CVSS
K34
D13
U31
D3
B2
GADVDD
D2
VDDL
LA0
F2
LA5
L1
DVDD
U33
D0
B4
LD26
D4
LA1
F4
LA3
L3
LA16
U35
GADVDD
B6
LD22
D6
LD28
F6
LD31
L5
LA17
V2
GDDVDD
B8
LD18
D8
LD23
F8
LD27
L31
D16
V4
LA29
B10
LD12
D10
LD17
F10
LD21
L33
D11
V32
D1
B12
LD8
D12
LD13
F12
LD16
L35
DVDD
V34
CE1
B14
LD3
D14
LD9
F24
A6
M2
LA18
W1
X1
B16
A30
D16
LD5
F26
A11
M4
LA19
W3
IACK
B18
A27
D18
LD2
F28
A5
M6
LA11
W5
LSTAT3
B20
A25
D20
A29
F32
D31
M30
D17
W31
RDY1
B22
A21
D22
A24
F34
D23
M32
D14
W33
LOCK
B24
A17
D24
A20
G1
DVSS
M34
D9
W35
TMS
B26
A14
D26
A15
G3
LA7
N1
CVSS
Y2
LSTAT2
B28
A10
D28
A9
G5
LA6
N3
LA20
Y4
LSTAT1
B30
A4
D30
A2
G31
D27
N5
LA21
Y32
RDY0
B32
A1
D32
A0
G33
D21
N31
D12
Y34
TCK
B34
LADVDD
D34
D26
G35
DVSS
N33
D7
N35
DVSS
AR33
10
PIN
NO.
POST OFFICE BOX 1443
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TMS320C40
DIGITAL SIGNAL PROCESSOR
SPRS038 – JANUARY 1996
memory map
Figure 1 shows the memory map for the ’320C40. Refer to the TMS320C4x User’s Guide (literature number
SPRU063B) for a detailed description of this memory mapping.
00000 0000h
Structure
Depends
Upon
ROMEN Bit
1M
Accessible Local Bus
(External)
00000 0FFFh
00000 1000h
Boot-Loader ROM
(Internal)
Reserved
Peripherals (Internal)
0000F FFFFh
00010 0000h
Peripherals (Internal)
00010 00FFh
00010 0100h
1M
Reserved
Reserved
0001F FFFFh
00020 0000h
Reserved
Reserved
2G
1M
1K RAM BLK 0 (Internal)
1K RAM BLK 1 (Internal)
0002F F7FFh
0002F F800h
0002F FBFFh
0002F FC00h
1K RAM BLK 0 (Internal)
1K RAM BLK 1 (Internal)
0002F FFFFh
00030 0000h
2G–3M
Structure
Identical
Local Bus
(External)
Local Bus
(External)
07FFF FFFFh
08000 0000h
Global Bus (External)
Global Bus (External)
2G
0FFFF FFFFh
(a) Internal ROM Disabled
(ROMEN = 0)
Microprocessor Mode
(b) Internal ROM Enabled
(ROMEN = 1)
Microcomputer Mode
Figure 1. Memory Map for ’320C40
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11
TMS320C40
DIGITAL SIGNAL PROCESSOR
SPRS038 – JANUARY 1996
description
The ’320C40 digital signal processors ( DSPs) are 32-bit, floating-point processors manufactured in 0.72-µm,
double-level metal CMOS technology. The ’320C40 is a part of the fourth generation of DSPs from Texas
Instruments and is designed primarily for parallel processing.
operation
The ’320C40 has six on-chip communication ports for processor-to-processor communication with no external
hardware and simple communication software. This allows connectivity to other ’C4x processors with no
external-glue logic. The communication ports remove input / output bottlenecks, and the independent smart
DMA coprocessor is able to handle the CPU input / output burden.
central processing unit
The ’320C40 CPU is configured for high-speed internal parallelism for the highest sustained performance. The
key features of the CPU are:
D
D
D
D
D
Eight operations/cycle:
–
40/32-bit floating-point / integer multiply
–
40/32-bit floating-point / integer ALU operation
–
Two data accesses
–
Two address register updates
IEEE floating-point conversion
Divide and square-root support
’C3x assembly language compatibility
Byte and halfword accessibility
DMA coprocessor
The DMA coprocessor allows concurrent I/O and CPU processing for the highest sustained CPU performance.
The key features of the DMA processor are:
D
D
D
D
Link pointers allow DMA channels to auto-initialize without CPU intervention.
Parallel CPU operation and DMA transfers
Six DMA channels support memory-to-memory data transfers.
Split-mode operation doubles the available DMA channel to 12 when data transfers to and from a
communication port are required.
communication ports
The ’320C40 is the first DSP with on-chip communication ports for processor-to-processor communication with
no external hardware and simple communication software. The features of the communication ports are:
D
D
D
D
D
12
Direct interprocessor communication and processor I / O
Six communication ports for direct interprocessor communication and processor I/O
20M-bytes/s bidirectional interface on each communication port for high-speed multiprocessor interface
Separate input and output 8-word-deep FIFO buffers for processor-to-processor communication and I/O
Automatic arbitration and handshaking for direct processor-to-processor connection
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TMS320C40
DIGITAL SIGNAL PROCESSOR
SPRS038 – JANUARY 1996
communication-port software reset (’C40 silicon revision ≥ 5.0)
The input and output FIFO levels for a communication port can be flushed by writing at least two back-to-back
values to its communication-port-software reset address as specified in Table 1. This feature is not present in
’C40 silicon revision <5.0. This software reset flushes any word or byte already present in the FIFOs but it does
not affect the status of the communication-port pins. Figure 2 shows an example of
communication-port-software reset.
Table 1. Communication-Port Software-Reset Address
COMMUNICATION PORT
SOFTWARE RESET ADDRESS
0
0x0100043
1
0x0100053
2
0x0100063
3
0x0100073
4
0x0100083
5
0x0100093
; –––––––––––––––––––––––––––––––––––––––––––––-–––;
; RESET1:Flush’s FIFO data for communication port 1;
; –––––––––––––––––––––––––––––––––––––––––––––-–––;
RESET1 push
AR0
; Save registers
push
R0
;
push
RC
;
ldhi
010h,AR0
; Set AR0 to base address of COM 1
or
050h,AR0
;
flush: rpts
1
; Flush FIFO data with back-to-back write
sti
R0,*+AR0(3) ;
rpts
10
; Wait
nop
;
ldi
*+AR0(0),R0 ; Check for new data from other port
and
01FE0h,R0
;
bnz
flush
;
pop
RC
; Restore registers
pop
R0
;
pop
AR0
;
rets
; Return
Figure 2. Example of Communication-Port-Software Reset
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13
TMS320C40
DIGITAL SIGNAL PROCESSOR
SPRS038 – JANUARY 1996
NMI with bus-grant feature (’C40 silicon revision ≥ 5.0)
The ’320C40 devices have a software-configurable feature which allows forcing the internal-peripheral bus to
ready when the NMI signal is asserted. This feature is not present in ’C40 silicon revision < 5.0. The NMI
bus-grant feature is enabled when bits 19 – 18 of the status register (ST) are set to 10b. When enabled, a
peripheral bus-grant signal is generated on the falling edge of NMI. When NMI is asserted and this feature is
not enabled, the CPU stalls on access to the peripheral bus if it is not ready. A stall condition occurs when writing
to a full FIFO or reading an empty FIFO. This feature is useful in correcting communication-port errors when
used in conjunction with the communication-port software-reset feature.
IDLE2 clock-stop power-down mode (’C40 silicon revision ≥ 5.0)
The ’320C40 has a clock-stop mode or power-down mode (IDLE2) to achieve extremely low-power
consumption. When an IDLE2 instruction is executed, the clocks are halted with H1 being held high. To exit
IDLE2, assert one of the IIOF3 – IIOF0 pins configured as an external interrupt instead of a general-purpose I / O.
A macro showing how to generate the IDLE2 opcode is given in Figure 3. During this power-down mode:
D
D
D
No instructions are executed.
The CPU, peripherals, and internal memory retain their previous state.
The external-bus outputs are idle. The address lines remain in their previous state, the data lines are in
the high-impedance state, and the output-control signals are inactive.
; ––––––––––––––––––––––––––––––––––––––––––––-–-–;
; IDLE2: Macro to generate idle2 opcode
;
; –––––––––––––––––––––––––––––––––––––––––––––-––;
IDLE2
.macro
.word
06000001h
.endm
Figure 3. Example of Software Subroutine Using IDLE2
IDLE2 is exited when one of the five external interrupts (NMI and IIOF3 – IIOF0) is asserted low for at least four
input clocks (two H1 cycles). The clocks then start after a delay of two input clocks (one H1 cycle). The clocks
can start in the opposite phase; that is, H1 can be high when H3 was high before the clocks were stopped.
However, the H1 and H3 clocks remain 180° out of phase with each other.
During IDLE2 operation, an external interrupt can be recognized and serviced by the CPU if it is enabled before
entering IDLE2 and asserted for at least two H1 cycles. For the processor to recognize only one interrupt, the
interrupt pin must be configured for edge-trigger mode or asserted less than three cycles in level-trigger mode.
Any external interrupt pin can wake up the device from IDLE2, but for the CPU to recognize that interrupt, it must
also be enabled. If an interrupt is recognized and executed by the CPU, the instruction following the IDLE2
instruction is not executed until after execution of a return opcode.
When the device is in emulation mode, the CPU executes an IDLE2 instruction as if it were an IDLE instruction.
The clocks continue to run for correct operation of the emulator.
14
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TMS320C40
DIGITAL SIGNAL PROCESSOR
SPRS038 – JANUARY 1996
development tools
The ’C40 is supported by a host of parallel-processing development tools for developing and simulating code
easily and for debugging parallel-processing systems. The code generation tools include:
D
D
D
D
An ANSI C compiler optimized with a runtime support library that supports use of communication ports and
DMA.
Third party support for C, C++ and Ada compilers
Several operating systems available for parallel-processing support, as well as DMA and communication
port drivers
An assembler and linker with support for mapping program and data to parallel processors
The simulation tools include:
D
D
Parallel DSP system-level simulation with LAI hardware verification (HV) model and full function (FF) model.
TI software simulator with high-level language debugger interface for simulating a single processor.
The hardware development and verification tools include:
D
D
Parallel processor in-circuit emulator and high-level language debugger: XDS510.
Parallel processor development system (PPDS) with four ’320C40s, local and global memory, and
communication port connections.
silicon revision identification
DSP
TMS320C40GFL
EA XXX
YYYYY
@1991 TI TAIWAN
Device Type
Revision Number and Package Data Code
E XXXXX:
Silicon rev 1.X
EA XXXXX:
Silicon rev 2.X
EB XXXXX:
Silicon rev 3.X
ED XXXXX:
Silicon rev 5.x
Lot Number
(May or may not exist)
POST OFFICE BOX 1443
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15
TMS320C40
DIGITAL SIGNAL PROCESSOR
SPRS038 – JANUARY 1996
absolute maximum ratings over specified temperature range (unless otherwise noted)†
Supply voltage range, VDD (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.3 V to 7 V
Voltage range on any pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.3 V to 7 V
Output voltage range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.3 V to 7 V
Operating case temperature range, TC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to 85°C
Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 55°C to 150°C
† Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTE 1: All voltage values are with respect to VSS.
recommended operating conditions (see Note 2)
VDD
Supply voltages (DDVDD, etc.)
VIH
High level input voltage
High-level
VIL
IOH
Low-level input voltage
X2/CLKIN
MIN
TYP‡
4.75
5
2.6
All other pins
2
§
– 0.3
High-level output current
MAX
UNIT
5.25
VDD + 0.3§
VDD + 0.3§
V
V
0.8
V
– 300
µA
IOL
Low-level output current
TC
Operating case temperature
‡ All typical values are at VDD = 5 V, TA (ambient air temperature)= 25°C.
§ This parameter is characterized but not tested.
NOTE 2: All input and output voltage levels are TTL compatible, except for CLKIN. CLKIN can be driven by CMOS clock.
2
mA
85
°C
electrical characteristics over recommended ranges of supply voltage and operating case
temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VOH
High-level output voltage
VDD = MIN,
IOH = MAX
VOL
Low-level output voltage
VDD = MIN,
IOL = MAX
IZ
Three-state current
VDD = MAX
IIC
Input current, X2 / CLKIN only
VI = VSS to VDD
IIP
Input current
Inputs with internal pullups
(See Note 3)
II
Input current
VI = VSS to VDD
ICC
Supplyy current
TA = 25 °C, VDD = MAX,
(See Note 4)
CI
fx = MAX
MIN
TYP¶
2.4
3
0.3
’320C40-40
’320C40-50
’320C40-60
MAX
V
0.6
V
–20
20
µA
– 30
30
µA
– 400
20
µA
–10
10
µA
350
850
mA
950
15#
Input capacitance
UNIT
pF
CO
Output capacitance
15#
pF
¶ All typical values are at VDD = 5 V, TA (ambient air temperature) = 25°C.
# This parameter is specified by design but not tested.
NOTES: 3. Pins with internal pullup devices: TDI, TCK, TMS. Pin with internal pulldown device: TRST.
4. fx is the input clock frequency. The maximum value (max) for the ’320C40-40, ’320C40-50, and ’320C40-60 is 40, 50 and 60 MHz,
respectively.
16
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TMS320C40
DIGITAL SIGNAL PROCESSOR
SPRS038 – JANUARY 1996
PARAMETER MEASUREMENT INFORMATION
IOL
Tester Pin
Electronics
VLoad
CT
Output
Under
Test
IOH
Where: IOL
IOH
VLoad
CT
=
=
=
=
2 mA (all outputs)
300 µA (all outputs)
2.15 V
80 pF typical load circuit capacitance.
Figure 4. Test Load Circuit
signal transition levels
TTL-level outputs are driven to a minimum logic-high level of 2.4 V and to a maximum logic-low level of 0.6 V.
Output transition times are specified as follows.
For a high-to-low transition on a TTL-compatible output signal, the level at which the output is said to be no
longer high is 2 V and the level at which the output is said to be low is 1 V. For a low-to-high transition, the level
at which the output is said to be no longer low is 1 V and the level at which the output is said to be high is 2 V.
See Figure 5.
2.4 V
2V
1V
0.6 V
Figure 5. TTL-Level Outputs
Transition times for TTL-compatible inputs are specified as follows. For a high-to-low transition on an input
signal, the level at which the input is said to be no longer high is 2 V and the level at which the input is said to
be low is 0.8 V. For a low-to-high transition on an input signal, the level at which the input is said to be no longer
low is 0.8 V and the level at which the input is said to be high is 2 V. See Figure 6.
2V
0.8 V
Figure 6. TTL-Level Inputs
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17
TMS320C40
DIGITAL SIGNAL PROCESSOR
SPRS038 – JANUARY 1996
PARAMETER MEASUREMENT INFORMATION
timing parameter symbology
Timing parameter symbols used herein were created in accordance with JEDEC Standard 100-A. In order to
shorten the symbols, pin names that have both global and local applications are generally represented with ( L)
immediately preceding the basic signal name (for example, ( L)RDYx represents both the global term RDYx and
local term LRDYx). Other pin names and related terminology have been abbreviated as follows, unless
otherwise noted:
18
A
(L)A30 – (L)A0 or (L)Ax
IACK
IACK
AE
(L)AE
IF
IIOF(3 – 0) or IIOFx
ASYNCH
Asynchronous reset signals in the high-impedance state
IIOF
IIOF(3 – 0) or IIOFx
BYTE
Byte transfer
LOCK
(L)LOCK
CA
CACK(0 – 5) or CACKx
P
CD
C(0 – 5)D7 – C(0 – 5)D0 or CxDx
PAGE
tc(H)
(L)PAGE0 and (L)PAGE1 or (L)PAGEx
CE
(L)CE0, (L)CE1, or (L)CEx
RDY
(L)RDY0, (L)RDY1, or (L)RDYx
CI
CLKIN
RESET
RESET
COMM
Asynchronous reset signals
RW
(L)R / W0, (L)R / W1, or (L)R / Wx
CONTROL
Control signals
S
(L)STRB0, (L)STRB1 or (L)STRBx
CRQ
CREQ(0 – 5) or CREQx
ST
(L)STAT3 – (L)STAT0 or (L)STATx
CRDY
CRDY(0 – 5) or CRDYx
TCK
TCK
CS
CSTRB(0 – 5) or CSTRBx
TCLK
TCLK0, TCLK1, or TCLKx
D
(L)D31 – (L)D0 or (L)Dx
TDO
TDO
DE
(L)DE
TMS
TMS / TDI
H
H1, H3
WORD
32-bit word transfer
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TMS320C40
DIGITAL SIGNAL PROCESSOR
SPRS038 – JANUARY 1996
timing for X2/CLKIN, H1, H3 (see Figure 7 and Figure 8)
TMS320C40 - 40
NO
NO.
1
MIN
tf(CI)
tw(CIL)
Fall time, CLKIN
Pulse duration, CLKIN low, tc(CI) = MIN
8
tw(CIH)
tr(CI)
Pulse duration, CLKIN high, tc(CI) = MIN
8
tc(CI)
tf(H)
Cycle time, CLKIN
Pulse duration, H1 and H3 low
8
tw(HL)
tw(HH)
9
tr(H)
Rise time, H1 and H3
td(HL - HH)
Delay time from H1 low to H3 high or
from H3 low to H1 high
2
3
4
5
6
7
9.1
TMS320C40 - 50
MAX
5†
MIN
MAX
5†
7
25
7
20
242.5
3
tc(CI) – 6
tc(CI) – 6
Pulse duration, H1 and H3 high
tc(CI) + 6
tc(CI) + 6
tc(CI) + 6
tc(CI) + 6
4
10
tc(H)
Cycle time, H1 and H3
† This value is specified by design but not tested.
UNIT
ns
ns
ns
5†
ns
16.67
242.5
ns
3
ns
tc(CI) – 6
tc(CI) – 6
tc(CI) + 6
tc(CI) + 6
3
tc(CI) – 6
tc(CI) – 6
MAX
5†
5
5†
242.5
Fall time, H1 and H3
MIN
5
5†
Rise time, CLKIN
TMS320C40 - 60
4
ns
ns
4
ns
–1
4
–1
4
–1
4
ns
50
485
40
485
33.3
485
ns
5
4
1
X2 / CLKIN
3
2
Figure 7. X2 / CLKIN Timing
10
6
9
H1
8
7
9.1
9.1
H3
8
9
6
7
10
Figure 8. H1 and H3 Timings
POST OFFICE BOX 1443
• HOUSTON, TEXAS 77251–1443
19
TMS320C40
DIGITAL SIGNAL PROCESSOR
SPRS038 – JANUARY 1996
memory-read-cycle and memory-write-cycle timing [(L)STRBx = 0] (see Note 5, Figure 9 and
Figure 10)
TMS320C40 - 40
NO
NO.
1
2
3
4
5
6
7
8
8.1
9
MIN
0†
MAX
9
MIN
0†
MAX
9
9
0†
0†
9
0†
UNIT
MIN
0†
MAX
8
ns
8
ns
9
0†
0†
8
ns
9
0†
8
ns
Delay time, H1 low to (L)STRBx low
td(H1H - RWL)
td(H1L - A)
Delay time, H1 high to (L)R / Wx low
0†
0†
Delay time, H1 low to (L)Ax valid
0†
tsu(D-H1L)R
th(H1L-D)R
Setup time, (L)Dx valid before H1 low (read)
15
10
9
ns
Setup time, (L)RDYx valid before H1 low
0
‡
20
0
18†
ns
tsu(RDY-H1L)
th(H1L-RDY)
0
25‡
0
0
0
ns
td(H1L - ST)
Delay time, H1 low to (L)STRBx high
Hold time, (L)Dx after H1 low (read)
Hold time, (L)RDYx after H1 low
Delay time, H1 low to (L)STAT3 – (L)STAT0
valid
Delay time, H1 high to (L)R / Wx high (write)
10
11
th(H1H-D)W
Hold time, (L)Dx after H1 high (write)
12
td(H1H - A)
Delay time, H1 high to address valid on backto-back write cycles
9
TMS320C40 - 60
td(H1L -SL)
td(H1L - SH)
td(H1H-RWH)W
tv(H1L-D)W
9
0†
Valid time, (L)Dx after H1 low (write)
9
0
POST OFFICE BOX 1443
9
8
0†
16
9
13
• HOUSTON, TEXAS 77251–1443
0†
16
0
† This value is specified by design but not tested.
‡ If this setup time is not met, the read / write operation is not assured.
NOTE 5: For consecutive reads, (L)R / Wx stays high and (L)STRBx stays low.
20
TMS320C40 - 50
ns
8
ns
8
ns
13
ns
0
9
ns
8
ns
TMS320C40
DIGITAL SIGNAL PROCESSOR
SPRS038 – JANUARY 1996
H3
H1
1
2
(L)STRBx
(L)R / Wx
5
4
3
(L)Ax
6
(L)Dx
8
7
(L)RDYx
8.1
(L)STATx
Figure 9. Memory-Read-Cycle Timing [(L)STRBx = 0]
POST OFFICE BOX 1443
• HOUSTON, TEXAS 77251–1443
21
TMS320C40
DIGITAL SIGNAL PROCESSOR
SPRS038 – JANUARY 1996
H3
H1
1
2
(L)STRBx
3
9
(L)R / Wx
12
4
(L)Ax
10
11
(L)Dx
8
(L)RDYx
7
(L)STATx
Figure 10. Memory-Write-Cycle Timing [(L)STRBx = 0]
22
POST OFFICE BOX 1443
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TMS320C40
DIGITAL SIGNAL PROCESSOR
SPRS038 – JANUARY 1996
(L)DE-, (L)AE-, and (L)CEx-enable timing (see Figure 11)
TMS320C40 - 40
TMS320C40 - 50
NO.
TMS320C40 - 60
MIN
MAX
MIN
MAX
UNIT
1
td(DEH - DZ)
Delay time, (L)DE high to (L)D0 – (L)D31 in the high-impedance
state
0†
15‡
0†
15‡
ns
2
td(DEL - DV)
Delay time, (L)DE low to (L)D0 – (L)D31 valid
0†
21
0†
16
ns
3
td(AEH - AZ)
Delay time, (L)AE high to (L)A0 – (L)A30 in the high-impedance
state
0†
15‡
0†
15‡
ns
4
td(AEL - AV)
Delay time, (L)AE low to (L)A0 – (L)A30 valid
0†
18
0†
16
ns
5
td(CEH - RWZ)
Delay time, (L)CEx high to (L)R / W0, (L)R / W1 in the
high-impedance state
0†
15‡
0†
15‡
ns
6
td(CEL - RWV)
Delay time, (L)CEx low to (L)R / W0, (L)R / W1 valid
0†
21
0†
16
ns
7
td(CEH - SZ)
Delay time, (L)CEx high to (L)STRB0, (L)STRB1 in the
high-impedance state
0†
15‡
0†
15‡
ns
8
td(CEL - SV)
Delay time, (L)CEx low to (L)STRB0, (L)STRB1 valid
0†
21
0†
16
ns
td(CEH - PAGEZ)
Delay time, (L)CEx high to (L)PAGE0, (L)PAGE1 in the
high-impedance state
0†
15‡
0†
15‡
ns
0†
21
0†
16
ns
9
10 td(CEL - PAGEV) Delay time, (L)CEx low to (L)PAGE0, (L)PAGE1 valid
† This value is specified by design but not tested.
‡ This value is characterized but not tested.
(L)DE
2
1
Hi-Z
(L)Dx
(L)AE
4
3
Hi-Z
(L)Ax
(L)CEx
6
5
Hi-Z
(L)R / Wx
7
8
Hi-Z
(L)STRBx
9
10
Hi-Z
(L)PAGEx
Figure 11. (L)DE -, (L)AE -, and (L)CEx-Enable Timings
POST OFFICE BOX 1443
• HOUSTON, TEXAS 77251–1443
23
TMS320C40
DIGITAL SIGNAL PROCESSOR
SPRS038 – JANUARY 1996
timing for (L)LOCK when executing LDFI or LDII (see Figure 12)
TMS320C40 - 40
NO
NO.
1
MIN
td(H1L - LOCKL)
Delay time, H1 low to (L)LOCK low
MAX
TMS320C40 - 50
MIN
11
MAX
8
LDFI or LDII
External Access
H3
H1
(L)STRBx
(L)R / Wx
(L)Ax
(L)Dx
(L)RDYx
1
(L)LOCK
Figure 12. Timing for (L)LOCK When Executing LDFI or LDII
24
POST OFFICE BOX 1443
• HOUSTON, TEXAS 77251–1443
TMS320C40 - 60
MIN
MAX
8
UNIT
ns
TMS320C40
DIGITAL SIGNAL PROCESSOR
SPRS038 – JANUARY 1996
timing for (L)LOCK when executing STFI or STII (see Figure 13)
TMS320C40 - 40
NO
NO.
1
MIN
td(H1L - LOCKH)
TMS320C40 - 50
MAX
Delay time, H1 low to (L)LOCK high
MIN
11
MAX
8
TMS320C40 - 60
MIN
MAX
8
UNIT
ns
STFI or STII
External Access
H3
H1
(L)STRBx
(L)R / Wx
(L)Ax
(L)Dx
(L)RDYx
1
(L)LOCK
Figure 13. Timing for (L)LOCK When Executing STFI or STII
POST OFFICE BOX 1443
• HOUSTON, TEXAS 77251–1443
25
TMS320C40
DIGITAL SIGNAL PROCESSOR
SPRS038 – JANUARY 1996
timing for (L)LOCK when executing SIGI (see Figure 14)
TMS320C40 - 40
NO
NO.
1
2
MIN
td(H1L - LOCKL)
td(H1L - LOCKH)
MAX
TMS320C40 - 50
MIN
TMS320C40 - 60
MIN
MAX
Delay time, H1 low to (L)LOCK low
11
8
8
Delay time, H1 low to (L)LOCK high
11
8
8
H3
H1
1
2
(L)LOCK
(L)R / Wx
(L)Ax
(L)Dx
(L)RDYx
(L)STATx
Figure 14. Timing for (L)LOCK When Executing SIGI
26
MAX
POST OFFICE BOX 1443
• HOUSTON, TEXAS 77251–1443
UNIT
ns
TMS320C40
DIGITAL SIGNAL PROCESSOR
SPRS038 – JANUARY 1996
timing for (L)PAGE0, (L)PAGE1 during memory access to a different page (see Figure 15)
TMS320C40 - 40
TMS320C40 - 50
NO.
1
2
td(H1L - PAGEH)
td(H1L - PAGEL)
TMS320C40 - 60
UNIT
MIN
MAX
MIN
MAX
Delay time, H1 low to (L)PAGEx high for access to different page
0
9
0
8
ns
Delay time, H1 low to (L)PAGEx low for access to different page
0
9
0
8
ns
H1
(L)R / Wx
(L)STRBx
(L)RDYx
1
2
1
2
(L)PAGEx
(L)Dx
(L)Ax
(L)STATx
(L)STRB1 write to a different page
(L)STRB1 read from a different page
Figure 15. (L)PAGE0, (L)PAGE1 Timing Cycle, Memory Access to a Different Page
POST OFFICE BOX 1443
• HOUSTON, TEXAS 77251–1443
27
TMS320C40
DIGITAL SIGNAL PROCESSOR
SPRS038 – JANUARY 1996
timing for the IIOFx when configured as an output (see Figure 16)
TMS320C40 - 40
NO
NO.
1
MIN
tv(H1L - IIOF)
MAX
H1 low to IIOFx valid
Fetch Load
Instruction
16
Decode
Read
TMS320C40 - 50
MIN
MAX
TMS320C40 - 60
MIN
MAX
14
14
Execute
H3
H1
FLAGx (IIF Register)
1 or 0
1
IIOFx Pins
Figure 16. Timing for the IIOFx When Configured as an Output
28
POST OFFICE BOX 1443
• HOUSTON, TEXAS 77251–1443
UNIT
ns
TMS320C40
DIGITAL SIGNAL PROCESSOR
SPRS038 – JANUARY 1996
timing of IIOFx changing from output to input mode (see Figure 17)
TMS320C40 - 40
TMS320C40 - 50
NO.
MIN
1
2
th(H1L - IIOF)
tsu(IIOF-H1L)
Hold time, IIOFx after H1 low
Setup time, IIOFx before H1 low
3
th(H1L-IIOF)
Hold time, IIOFx after H1 low
† This value is specified by design but not tested.
Buffers Go
From Output
to Input
Execute
Load of IIF
Register
MAX
14†
TMS320C40 - 60
MIN
MAX
14†
UNIT
ns
11
11
ns
0
0
ns
Synchronizer
Delay
Value on IIOF
Seen in IIF
H3
H1
2
3
TYPEx
(IIF Register)
1
IIOFx
Output
FLAGx
(IIF Register)
Data
Sampled
Data
Seen
Figure 17. Change of IIOFx From Output to Input Mode
POST OFFICE BOX 1443
• HOUSTON, TEXAS 77251–1443
29
TMS320C40
DIGITAL SIGNAL PROCESSOR
SPRS038 – JANUARY 1996
timing of IIOFx changing from input to output mode (see Figure 18)
TMS320C40 - 40
NO
NO.
1
MIN
td(H1L - IFIO)
Delay time, H1 low to IIOFx switching from input to
output
MAX
TMS320C40 - 50
MIN
MAX
16
TMS320C40 - 60
MIN
MAX
14
14
TMS320C40 - 50
TMS320C40 - 60
UNIT
ns
Execution of
Load of IIF
Register
H3
H1
TYPEx
(IIF Register)
1
IIOFx
Figure 18. Change of IIOFx From Input to Output Mode
RESET timing (see Figure 19)
TMS320C40 - 40
NO
NO.
Setup time for RESET before CLKIN low
11
11
11
MAX
tc(CI)†
2.1
tsu(RESET-C1L)
td(CIH - H1H)
MAX
tc(CI)†
Delay time, CLKIN high to H1 high
3
10
2
10
2
10
ns
2.2
td(CIH - H1L)
Delay time, CLKIN high to H1 low
3
10
2
10
2
10
ns
tsu(RESETH - H1L)
Setup time for RESET high before H1 low
and after ten H1 clock cycles
3
4.1
13
MIN
13
4.2
td(CIH - H3L)
td(CIH - H3H)
5
td(H1H - DZ)
Delay time, H1 high to (L)Dx in the
high-impedance state
13‡
6
td(H3H - AZ)
Delay time, H3 high to (L)Ax in the
high-impedance state
7
td(H3H - CONTROLH)
8
MIN
UNIT
MAX
tc(CI)†
1
MIN
13
ns
ns
Delay time, CLKIN high to H3 low
3
10
2
10
2
10
ns
Delay time, CLKIN high to H3 high
3
10
2
10
2
10
ns
13‡
13‡
ns
9‡
9‡
9‡
ns
Delay time, H3 high to control signals high
[low for (L)PAGE]
9‡
9‡
9‡
ns
td(H1H - IACKH)
Delay time, H1 high to IACK high
9‡
9‡
9‡
ns
9
td(RESETL - ASYNCH)
Delay time, RESET low to asynchronous
reset signals in the high-impedance state
21‡
21‡
21‡
ns
10
td(RESETH - COMMH)
Delay time, RESET high to asynchronous
reset signals high
15‡
15‡
15‡
ns
† tc(CI), the CLKIN period as shown in Figure 7
‡ This value is characterized but not tested.
30
POST OFFICE BOX 1443
• HOUSTON, TEXAS 77251–1443
CLKIN
RESET
(see Notes A and B)
1
2.2
2.1
3
H1
5
4.1
H3
Ten H1 Clock Cycles
(L)Dx
(see Note C)
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
Control Signals
4.2
(L)Ax
(see Note C)
6
7
Control Signals
(see Note D)
7
(L)PAGEx
(see Note D)
8
IACK
Asynchronous Reset
Signals (see Note E)
Asynchronous Reset
Signals (see Note A)
9
10
9
Figure 19. RESET Timing
SPRS038 – JANUARY 1996
31
ADVANCE INFORMATION
TMS320C40
DIGITAL SIGNAL PROCESSOR
NOTES: A. Asynchronous reset signals that go to a high logic level after RESET returns to a high state include CREQy, CACKx, CSTRBx, and CRDYy (where x = 0, 1 or 2 and
y = 3, 4 or 5).
B. RESET is an asynchronous input and can be asserted at any point during a clock cycle. If the specified timings are met, the exact sequence shown occurs; otherwise,
an additional delay of one clock cycle can occur.
C. For Figure 19 only, (L)Dx includes D31 – D0, LD31 – LD0, and CxD7 – CxD0, (L)Ax includes LA(30 – 0) and A(30 – 0).
D. Control signals LSTRB0, LSTRB1, STRB0, STRB1, (L)STAT3 – (L)STAT0, (L)LOCK, (L)R/W0, and (L)R/W1 go high while (L)PAGE0 and (L)PAGE1 go low.
E. Asynchronous reset signals that go into the high-impedance state after RESET goes low include TCLK0, TCLK1, IIOF3 – IIOF0, and the communication-port control
signals CREQx, CACKy, CSTRBy, and CRDYx (where x = 0, 1 or 2, and y = 3, 4 or 5). At reset, ports 0, 1, and 2 become outputs, while ports 3, 4, and 5 become
inputs.
TMS320C40
DIGITAL SIGNAL PROCESSOR
SPRS038 – JANUARY 1996
timing for IIOFx interrupt response [P = tc(H)] (see Notes 6, 7 and Figure 20)
TMS320C40 - 40
TMS320C40 - 50
NO.
1
tsu(IIOF-H1L )
Setup time, IIOFx before H1 low
2
tw(INT )
Pulse duration, to assure one interrupt is seen
(see Note 8)
MIN
11†
TYP
P
1.5P
MAX
< 2P‡
TMS320C40 - 60
MIN
11†
TYP
P
1.5P
UNIT
MAX
ns
< 2P‡
ns
† If this timing is not met, the interrupt is recognized in the next cycle.
‡ This value applies only to level-triggered interrupts and is specified by design but not tested.
NOTES: 6. IIOFx is an asynchronous input and can be asserted at any point during a clock cycle. If the specified timings are met, the exact
sequence shown occurs; otherwise, an additional delay of one clock cycle can occur.
7. Edge-triggered interrupts require a setup of time (1) and a minimum duration of P. No maximum duration limit exists.
8. Level-triggered interrupts require interrupt-pulse duration of at least 1P wide (P = one H1 period) to assure it will be seen. It must
be less than 2P wide to assure it will be responded to only once. Recommended pulse duration is 1.5P.
Reset or
Interrupt
Vector Read
Fetch First
Instruction of
Service
Routine
H3
H1
IIOFx
1
(see Note A)
First
Instruction
Address
2
FLAGx
(IIF Register)
Address
Vector
Address
Data
NOTE A: The ’C40 can accept an interrupt from the same source every two H1 clock cycles.
Figure 20. IIOFx Interrupt-Response Timing [P = tc(H)]
32
POST OFFICE BOX 1443
• HOUSTON, TEXAS 77251–1443
TMS320C40
DIGITAL SIGNAL PROCESSOR
SPRS038 – JANUARY 1996
timing for IACK (see Note 9 and Figure 21)
TMS320C40 - 40
TMS320C40 - 50
NO.
MIN
MAX
TMS320C40 - 60
MIN
UNIT
MAX
1
td(H1L - IACKL)
Delay time, H1 low to IACK low
9
7
ns
2
td(H1L - IACKH)
Delay time, H1 low to IACK high during first cycle of IACK instruction
data read
9
7
ns
NOTE 9: The IACK output is active for the entire duration of the bus cycle and is, therefore, extended if the bus cycle utilizes wait states.
Fetch IACK
Instruction
Decode IACK
Instruction
IACK Data
Read
Execute IACK
Instruction
H3
H1
1
2
IACK
Address
Data
Figure 21. IACK Timing
POST OFFICE BOX 1443
• HOUSTON, TEXAS 77251–1443
33
TMS320C40
DIGITAL SIGNAL PROCESSOR
SPRS038 – JANUARY 1996
communication-port word-transfer-cycle timing† [P = tc(H)] (see Note 10 and Figure 22)
NO.
TMS320C40 - 40
TMS320C40 - 50†
TMS320C40 - 60†
MIN
MIN
MAX
UNIT
MAX
1
tc(WORD)‡§
Cycle time, word transfer (4 bytes = 1 word)
1.5P + 7
2.5P + 170
1.5P + 7
2.5P + 170
ns
2
td(CRDYL-CSL)W‡
Delay time, CRDYx low to CSTRBx low between
back-to-back write cycles
1.5P + 7
2.5P + 28
1.5P + 7
2.5P + 28
ns
† For these timing values, it is assumed that the receiving ’C4x is ready to receive data. Line propagation delay is not considered.
‡ This value is characterized but not tested.
§ tc(WORD) max = 2.5P + 28 ns + the maximum summed values of 4 × td(CSL-CRDYL)R, 3 × td(CRDYL-CSH), 3 × td(CSH-CRDYH)R, and
3 × td(CRDYH-CSL)W as seen in Figure 23. This timing assumes two ’C4xs are connected.
NOTE 10: These timings apply only to two communicating ’C4xs. When a non-’C4x device communicates with a ’C40, timings can be longer. No
restriction exists in this case on how slow the transfer could be except when using early silicon (C40 PG 1.x or 2.x). Refer to the CSTRB
width restriction in Section 8.9.1 of the TMS320C4x User’s Guide (literature number SPRU063B).
CREQx
CACKx
1
CSTRBx
CxDx
B0
B1
B2
B3
Undef.
B0¶
2
CRDYx
= When signal is an input (clear = when signal is an output).
¶ Begins byte 0 of the next word.
NOTE A: For correct operation during token exchange, the two communicating ’C4xs must have CLKIN frequencies within a factor of 2 of each
other (in other words, at most, one of the ’C4xs can be twice as fast as the other).
Figure 22. Communication-Port Word-Transfer-Cycle Timing [P = tc(H)]
34
POST OFFICE BOX 1443
• HOUSTON, TEXAS 77251–1443
TMS320C40
DIGITAL SIGNAL PROCESSOR
SPRS038 – JANUARY 1996
communication-port byte-cycle timing (write and read) (see Note 11 and Figure 23)
TMS320C40 - 40
TMS320C40 - 50
NO.
MIN
1
Setup time, CxDx valid before CSTRBx low (write)
2
tsu(CD-CSL)W
td(CRDYL - CSH)W
3
th(CRDYL - CD)W
Hold time, CxDx after CRDYx low (write)
4
td(CRDYH - CSL)W
Delay time, CRDYx high to CSTRBx low for subsequent bytes
(write)
5
tc(BYTE)‡
td(CSL - CRDYL)R
Cycle time, byte transfer
tsu(CSH - CD)R
th(CRDYL - CD)R
Setup time, CxDx valid after CSTRBx high (read)
6
7
8
MAX
MIN
12
2
†
0
2
0†
Delay time, CRDYx low to CSTRBx high (write)
TMS320C40 - 60
2
12
44§
12
ns
44§
ns
10
ns
0†
10
0
ns
ns
0†
12
0†
Delay time, CSTRBx low to CRDYx low (read)
ns
2
0†
UNIT
MAX
0
ns
Hold time, CxDx valid after CRDYx low (read)
2
2
ns
td(CSH - CRDYH)R Delay time, CSTRBx high to CRDYx high (read)
0†
10
0†
10
ns
† This value is specified by design but not tested.
‡ tc(BYTE) max = summed maximum values of td(CRDY-CSH), td(CSL-CRDYL)R, td(CSH-CRDYH)R, and td(CRDYH-CSL)W. This assumes
two ’C4xs are connected.
§ This value is characterized but not tested.
NOTE 11: Communication port timing does not include line length delay.
9
CREQx
CACKx
5
5
7
CSTRBx
1
2
9
CxDx
Valid
Data
3
8
6
CRDYx
4
(a) WRITE TIMING
(b) READ TIMING
= When signal is an input (clear = when signal is an output).
Figure 23. Communication-Port Byte-Cycle Timing (Write and Read)
POST OFFICE BOX 1443
• HOUSTON, TEXAS 77251–1443
35
TMS320C40
DIGITAL SIGNAL PROCESSOR
SPRS038 – JANUARY 1996
timing for communication-token transfer sequence, input to an output port [P = tc(H)]
(see Figure 24)†
NO.
TMS320C40 - 40
TMS320C40 - 50
TMS320C40 - 60
MIN
MAX
MIN
UNIT
MAX
1‡
td(CAL - CS)T
Delay time, CACKx low to CSTRBx change from input
to a high-level output
0.5P + 6
1.5P + 22
0.5P+ 6
1.5P + 22
ns
2‡
td(CAL - CRQH)T
Delay time, CACKx low to start of CREQx going high for
token request acknowledge
P+ 5
2P + 22
P+5
2P + 22
ns
3
td(CRQH - CRQ)T
Delay time, start of CREQx going high to CREQx
change from output to an input
0.5P – 5
0.5P +1 3
0.5P – 5
0.5P + 13
ns
4
td(CRQH - CA)T
Delay time, start of CREQx going high to CACKx
change from an input to an output level high
0.5P – 5
0.5P + 13
0.5P – 5
0.5P + 13
ns
4.1
td(CRQH - CD)T
Delay time, start of CREQx going high to CxDx change
from inputs driven to outputs driven
0.5P – 5
0.5P + 13
0.5P – 5
0.5P + 13
ns
4.2
td(CRQH - CRDY)T
Delay time, start of CREQx going high to CRDYx
change from an output to an input
0.5P – 5
0.5P + 13
0.5P – 5
0.5P + 13
ns
5
td(CRQH - CSL)T
Delay time, start of CREQx going high to CSTRBx low
for start of word transfer out
1.5P – 8
1.5P + 9
1.5P – 8
1.5P + 9
ns
6‡
td(CRDYL - CSL)T
Delay time, CRDYx low at end of word input to CSTRBx
low for word output
3.5P + 12
5.5P + 48
3.5P + 12
5.5P + 48
ns
† These values are characterized but not tested.
‡ These timing parameters result from synchronizer delays.
36
POST OFFICE BOX 1443
• HOUSTON, TEXAS 77251–1443
TMS320C40
DIGITAL SIGNAL PROCESSOR
SPRS038 – JANUARY 1996
timing for communication-token transfer sequence, input to an output port [P = tc(H)] (continued)
3
CREQx
2
4
CACKx
5
1
CSTRBx
4.1
Valid Data Out
CxDx
6
CRDYx
4.2
= When signal is an input (clear = when signal is an output).
NOTE A: Before the token exchange, CREQx and CRDYx are output signals asserted by the TMS320C4x that is receiving data. CACKx,
CSTRBx, and CxD7 – CxD0 are input signals asserted by the device sending data to the ’C4x; these are asynchronous with respect
to the H1 clock of the receiving ’320C4x. After token exchange, CACKx, CSTRBx, and CxD7 – CxD0 become output signals, and
CREQx and CRDYx become inputs.
Figure 24. Communication-Token Transfer Sequence, Input to an Output Port [P = tc(H)]
POST OFFICE BOX 1443
• HOUSTON, TEXAS 77251–1443
37
TMS320C40
DIGITAL SIGNAL PROCESSOR
SPRS038 – JANUARY 1996
timing for communication-token transfer sequence, output to an input port [P = tc(H)]
(see Figure 25)†
TMS320C40 - 40
TMS320C40 - 50
NO.
TMS320C40 - 60
MIN
MAX
MIN
MAX
UNIT
1‡
td(CRQL - CAL)T
Delay time, CREQx low to start of CACKx going low for
token-request-acknowledge
P+5
2P + 22
P+5
2P + 22
ns
2‡
td(CRDYL - CAL)T
Delay time, CRDYx low at end of word transfer out to start
of CACKx going low
P+6
2P + 27
P+6
2P + 27
ns
3
td(CAL - CD)I
Delay time, start of CACKx going low to CxDx change from
outputs to inputs
0.5P – 8
0.5P + 8
0.5P – 8
0.5P + 8
ns
4
td(CAL - CRDY)T
Delay time, start of CACKx going low to CRDYx change from
an input to output, high level
0.5P – 8
0.5P + 8
0.5P – 8
0.5P + 8
ns
5
td(CRQH - CRQ)T
Delay time, CREQx high to CREQx change from an input
to output, high level
4
22
4
22
ns
6
td(CRQH - CA)T
Delay time, CREQx high to CACKx change from output to an
input
4
22
4
22
ns
7
td(CRQH - CS)T
Delay time, CREQx high to CSTRBx change from output to
an input
4
22
4
22
ns
8‡
td(CRQH - CRQL)T
Delay time, CREQx high to CREQx low for the next token
request
P–4
2P + 8
P–4
2P + 8
ns
† These values are characterized but not tested.
‡ These timing parameters result from synchronizer delays.
38
POST OFFICE BOX 1443
• HOUSTON, TEXAS 77251–1443
TMS320C40
DIGITAL SIGNAL PROCESSOR
SPRS038 – JANUARY 1996
timing for communication-token transfer sequence, input to an output port [P = tc(H)] (continued)
8
CREQx
1
5
CACKx
6
CSTRBx
3
7
CxDx
Valid Data
Valid Data
4
CRDYx
2
= When signal is an input (clear = when signal is an output).
NOTE A: Before the token exchange, CACKx, CSTRBx, and CxD7 – CxD0 are asserted by the ’C4x sending data. CREQx and CRDYx are
input signals asserted by the ’C4x receiving data and are asynchronous with respect to the H1 clock of the sending ’C4x. After token
exchange, CREQx and CRDYx become outputs, and CSTRBx, CACKx, and CxDx become inputs.
Figure 25. Communication-Token Transfer Sequence, Output to an Input Port [P = tc(H)]
POST OFFICE BOX 1443
• HOUSTON, TEXAS 77251–1443
39
TMS320C40
DIGITAL SIGNAL PROCESSOR
SPRS038 – JANUARY 1996
timer pin timing (see Note 12 and Figure 26)
TMS320C40 - 40
TMS320C40 - 50
NO.
MIN
1
2
tsu(TCLK-H1L) Setup time, TCLKx before H1 low
th(H1L-TCLK) Hold time, TCLKx after H1 low
MAX
10
TMS320C40 - 60
MIN
10
0
ns
0
3
td(H1H-TCLK) Delay time, TCLKx valid after H1 high
NOTE 12: Period and polarity of valid logic level are specified by contents of internal control registers.
UNIT
MAX
ns
13
13
TMS320C40 - 40
TMS320C40 - 50
TMS320C40 - 60
ns
H3
H1
2
3
1
3
Peripheral Pin
Figure 26. Timer Pin Timing Cycle
timing for IEEE-1149.1 test access port (see Figure 27)
NO.
MIN
1
MIN
tsu(TMS - TCKH)
th(TCKH-TMS)
Setup time, TMS / TDI to TCK high
10
10
2
Hold time, TMS / TDI from TCK high
5
5
3
td(TCKL - TDOV)
Delay time, TCK low to TDO valid
0
TCK
1
TMS / TDI
3
2
TDO
Figure 27. IEEE-1149.1 Test Access Port Timings
40
MAX
POST OFFICE BOX 1443
• HOUSTON, TEXAS 77251–1443
15
0
UNIT
MAX
ns
ns
12
ns
PACKAGE OPTION ADDENDUM
www.ti.com
25-Oct-2016
PACKAGING INFORMATION
Orderable Device
Status
(1)
TMS320C40GFL60
NRND
Package Type Package Pins Package
Drawing
Qty
CPGA
GF
325
1
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
TBD
AU
N / A for Pkg Type
Op Temp (°C)
Device Marking
(4/5)
TMS320C40GFL60
@1991 TI
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
25-Oct-2016
OTHER QUALIFIED VERSIONS OF TMS320C40 :
• Catalog: SM320C40
• Military: SMJ320C40
NOTE: Qualified Version Definitions:
• Catalog - TI's standard catalog product
• Military - QML certified for Military and Defense Applications
Addendum-Page 2
MECHANICAL DATA
MCPG013F – JANUARY 1995 – REVISED DECEMBER 2001
GF (S-CPGA-P325)
CERAMIC PIN GRID ARRAY
1.717 (43,61)
TYP
1.683 (42,75)
1.879 (47,73)
SQ
1.841 (46,76)
0.100 (2,54)
AR
AN
AL
AJ
AG
AE
AC
AA
W
U
R
N
L
J
G
E
C
A
A1 Corner
1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35
Bottom View
0.050 (1,27)
0.060 (1,52)
0.040 (1,02)
0.048 (1,22) DIA 4 Places
0.020 (0,51)
0.016 (0,41)
0.080 (2,03) TYP
0.050 (1,27) TYP
0.190 (4,83)
0.170 (4,32)
0.150 (3,81)
TYP
0.026 (0,660)
0.165 (4,19)
0.200 (5,08)
0.006 (0,152)
0.120 (3,05)
0.145 (3,68)
DETAIL A
4040035-2 / F 11/01
NOTES: A.
B.
C.
D.
E.
F.
G.
H.
All linear dimensions are in inches (millimeters).
This drawing is subject to change without notice.
Index mark can appear on top or bottom, depending on package vendor.
Pins are located within 0.010 (0,25) diameter of true position relative to
each other at maximum material condition and within 0.030 (0,76) diameter
relative to the edge of the ceramic.
This package can be hermetically sealed with metal lids or with ceramic lids using glass frit.
The pins can be gold-plated or solder-dipped.
Package thickness of 0.165 (4,19) / 0.120 (3,05) includes package body and lid.
Falls within JEDEC MO-128AK
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
1
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