Texas Instruments | nFBGA Packaging (Rev. B) | Application notes | Texas Instruments nFBGA Packaging (Rev. B) Application notes

Texas Instruments nFBGA Packaging (Rev. B) Application notes
Application Report
SPRAA99B – March 2008 – Revised November 2015
nFBGA Packaging
Robert Furtaw
ABSTRACT
This application report provides technical background on nFBGA packages and explains how to use them
to build advanced board layouts.
Contents
1
Introduction ................................................................................................................... 3
2
PCB Design Considerations ................................................................................................ 5
3
Reliability ...................................................................................................................... 9
4
Surface-Mounting nFBGA Packages .................................................................................... 14
5
Packing and Shipping...................................................................................................... 19
6
Sockets ...................................................................................................................... 25
Appendix A
Frequently Asked Questions ..................................................................................... 32
Appendix B
Package Data Sheets............................................................................................. 34
Appendix C Thermal Modeling Results ....................................................................................... 64
List of Figures
...........................................................................................................
1
Packaging Trends
2
Structure of TI’s nFBGA Package ......................................................................................... 4
3
nFBGA Package Assembly Flow .......................................................................................... 4
4
Package Via to Board Land Area Configuration ......................................................................... 5
5
Effects of Via-to-Land Ratios ............................................................................................... 5
6
Optimum Land Configurations
7
PCB Design Considerations (Conventional)
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
3
............................................................................................. 6
............................................................................. 7
Microvia Structure ........................................................................................................... 7
"Dog Bone" Via Structure ................................................................................................... 8
Buried Vias ................................................................................................................... 8
Daisy-Chained Pinout List (195ZWV nFBGA Package) ................................................................ 9
PCB Layout for Daisy-Chained Unit ..................................................................................... 10
Daisy-Chain Test Configuration .......................................................................................... 10
Thermal Modeling Process................................................................................................ 14
Solder Ball Collapse ....................................................................................................... 16
Recommended Reflow Profile of Pb-Free nFBGA Package ......................................................... 18
Recommended Reflow Profile of Eutectic SnPb nFBGA Package .................................................. 18
Shipping Tray Detail ....................................................................................................... 19
Single Sprocket Tape Dimension ........................................................................................ 23
Reel Dimensions ........................................................................................................... 24
Tape-and-Reel Packing ................................................................................................... 24
Approaches for Contacting the Solder Ball ............................................................................. 26
Pinch Contact for Solder Ball ............................................................................................. 27
Contact Area on Solder Ball .............................................................................................. 28
Witness Marks on Solder Ball ............................................................................................ 29
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26
Effect of Bur-In on Probe Mark ........................................................................................... 30
27
Micro Tuning Fork Contact for 0.5mm Pitch ............................................................................ 30
28
Micro Tuning Fork Contact and Contact Marks on Solder Balls ..................................................... 31
29
Socket Examples: Tuning Fork (Left) and Pinch Style (Right) ....................................................... 31
30
87ZVW Package Outline (6 x 6mm, 0.5mm pitch) ..................................................................... 36
31
72ZST Package Outline (7 x 7mm, 0.5mm pitch) ...................................................................... 37
32
143ZZC Package Outline (7 x 7mm, 0.5mm pitch) .................................................................... 38
33
143ZWU Package Outline (7 x 7mm, 0.5mm pitch) ................................................................... 39
34
143ZWU Daisy Chain Net List ............................................................................................ 39
35
152ZZB Package Outline (7 x 7mm, 0.5mm pitch) .................................................................... 40
36
209ZXN Package Outline (7 x 7mm, 0.4mm pitch) .................................................................... 41
37
113ZVD Package Outline (8 x 8mm, 0.65mm pitch)
42
38
113ZVD Daisy Chain Net List
43
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
..................................................................
............................................................................................
195ZWV Package Outline (8 x 8mm, 0.5mm pitch) ...................................................................
195ZWV Daisy Chain Net List ............................................................................................
225ZWF Package Outline (10 x 10mm, 0.5mm pitch) ................................................................
241ZWG Package Outline (10 x 10mm, 0.5mm pitch) ................................................................
241ZWJ Package Outline (10x10mm, 0.4mm pitch) ..................................................................
241ZWJ Daisy Chain Net List ............................................................................................
289ZWJ Package Outline (10 x 10mm, 0.4mm pitch) .................................................................
289ZWJ Daisy Chain Net List ............................................................................................
360ZWJ Package Outline (10 x 10mm, 0.4mm pitch) .................................................................
360ZWJ Daisy Chain Net List ............................................................................................
145ZWS Package Outline (12 x 12mm, 0.8mm pitch) ................................................................
289ZVL Package Outline (12 x 12mm, 0.5mm pitch) .................................................................
293ZVL Package Outline (12 x 12mm, 0.5mm pitch) .................................................................
318ZVL Package Outline (12 x 12mm, 0.5mm pitch) .................................................................
325ZVL Package Outline (12 x 12mm, 0.5mm pitch) .................................................................
325ZVL Daisy Chain Net List .............................................................................................
385ZWM Package Outline (12 x 12mm, 0.5mm pitch) ................................................................
385ZWK Package Outline (12 x 12mm, 0.5mm pitch) ................................................................
385ZWK Daisy Chain Net List ............................................................................................
289ZWE Package Outline (13 x 13mm, 0.5mm pitch) ................................................................
447ZAC Package Outline (14 x 14mm, 0.5mm pitch) .................................................................
447ZAF Package Outline (14 x 14mm, 0.5mm pitch) .................................................................
361ZWT Package Outline (16 x 16mm, 0.8mm pitch) ................................................................
361ZWT Daisy Chain Net List ............................................................................................
44
44
45
46
47
47
48
49
50
50
51
52
53
54
55
56
57
58
58
59
60
61
62
63
List of Tables
2
.............................................................................................
1
Optimum Land Configurations
2
Package-Level Reliability Tests .......................................................................................... 11
3
Package-Level Reliability Test Results .................................................................................. 11
4
Board-Level Reliability Summary......................................................................................... 12
5
Summary of Significant BLR Improvements ............................................................................ 12
6
Effects of Pad Size and Board Thickness on Fatigue Life ............................................................ 13
7
Number of Units per Shipping Tray ...................................................................................... 20
8
Tape Dimensions
9
Reel Dimensions ........................................................................................................... 24
10
TI’s Strategic Package Line-Up
nFBGA Packaging
..........................................................................................................
..........................................................................................
6
23
34
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Introduction
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1
11
8×8 mm nFBGA Thermal Simulation Result ............................................................................ 64
12
12×12 mm nFBGA Thermal Simulation Result ......................................................................... 64
13
16×16 mm nFBGA Thermal Simulation Result ......................................................................... 65
Introduction
The parallel pursuit of cost reduction and miniaturization in recent years has increased emphasis on very
small integrated circuit (IC) package solutions. This is particularly evident in consumer-based end
equipment using digital signal processor (DSP) solutions such as wireless telephones, laptop computers,
and hard-disk drives. Despite the formal definition, packages with an area similar in size to the IC they
encapsulate are loosely referred to as chip scale packages (CSPs). Figure 1 illustrates this trend.
Package trend (customer requirement)
QFP
0.5 mm pitch
BGA (ball grid array)
1.27 mm ball pitch
QFP
0.4 mm pitch
Fine pitch requirement
• Infra. issue (KGD)
CSP (chip scale pkg.) solution
• Soldering difficulties
Bare chip
(flip chip)
• PWB/ASSY cost up
Fine pitch BGA
(0.5, 0.8, 1.0 mm ball pitch)
QFP-0.5
BGA
Package size
QFP-0.4
CSP
Bare chip (bump)
Pin count
Figure 1. Packaging Trends
CSPs are in many ways an ideal solution to the cost reduction and miniaturization requirements. They
offer enormous area reductions compared to quad flat packages (QFPs) and have increasing potential to
do so without adding to system-level cost. In the best case, CSPs compete today on a cost-per-terminal
basis with QFPs. Various CSPs from Texas Instruments (TI) are now available at cost parity with thin
QFPs.
Texas Instruments produces a laminate-based family of CSPs known as New Fine Pitch Ball Grid Array
packages (also referred to as nFBGA packages). Like most other CSPs, nFBGA packages use solder
alloy balls as the interconnect between the package substrate and the board on which the package is
soldered. The nFBGA family comes in a range of solder ball pitch, and can accommodate various stacked
die configurations, with as many as three die housed in each package. Figure 2 shows the structure of
TI’s nFBGA package.
PACED, ThermCAL are trademarks of Texas Instruments.
All other trademarks are the property of their respective owners.
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Introduction
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Encapsulant
Wire bond
Silicon Die
Die Attach Material
Laminate Substrate
Solder Ball Array
Figure 2. Structure of TI’s nFBGA Package
Texas Instruments addressed several key issues in package assembly to produce a CSP that is not only
physically and mechanically stable but cost-effective for a wide variety of applications. Figure 3 shows a
general flow used to produce TI nFBGA packages.
Same as QFP assembly
Die attach
Wire bond
Encap
Non-Ag paste
Short loop
X’fer mode
BGA unique process
Ball attach
IR reflow
0.30 mm DIA.
Flux wash
Ultrasonic clean
Laser symbol
and singulation
Test
Tray
Figure 3. nFBGA Package Assembly Flow
4
nFBGA Packaging
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PCB Design Considerations
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The nFBGA package has been fully qualified in numerous applications and is being used extensively in
mobile phones, laptops, modems, handheld devices, and office environment equipment. For more
information on using reliable and cost-effective nFBGA packaging in your application, contact your local TI
field sales office.
2
PCB Design Considerations
2.1
Solder Land Areas
Designs of both the nFBGA package itself and the printed circuit board (PCB) are important in achieving
good manufacturability and optimum reliability. In particular, the diameters of the package vias and the
board lands are critical. While the actual sizes of these dimensions are important, their ratio is more
critical. Figure 4 illustrates the package via-to-PCB configuration and Figure 5 illustrates why this ratio is
critical.
nFBGA package
Land on PCB
Package
ball via
A
PCB
B
(Not to scale)
A = Via diameter on package
B = Land diameter on PCB
Ratio A/B should equal 1.0 for optimum reliability.
Figure 4. Package Via to Board Land Area Configuration
Package
PCB
Package
PCB
Package
PCB
Figure 5. Effects of Via-to-Land Ratios
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In the top view of Figure 5, the package via is larger than the PCB via, and the solder ball is prone to
crack prematurely at the PCB interface. In the middle view, the PCB via is larger than the package via,
which leads to cracks at the package surface. In the bottom view, where the ratio is almost 1:1, the
stresses are equalized and neither site is more susceptible to cracking than the other.
Solder lands on the PCB are generally simple round pads. Solder lands are either solder-mask-defined or
non-solder-mask-defined.
• Solder-mask-defined (SMD) land. With this method, the copper pad is made larger than the desired
land area, and the opening size is defined by the opening in the solder mask material. The advantages
normally associated with this technique include more closely controlled size and better copper
adhesion to the laminate. Better size control is the result of photo imaging the stencils for masks. The
chief disadvantage of this method is that the larger copper spot can make routing more difficult.
• Non-solder-mask-defined (NSMD) land. Here, the land area is etched inside the solder mask area.
While the size control is dependent on copper etching and is not as accurate as the solder mask
method, the overall pattern registration is dependent on copper artwork, which is quite accurate. The
tradeoff is between accurate dot placement and accurate dot size.
For an example of optimum land diameters and configurations for a common nFBGA pitch, see Table 1.
A
It is not recommended to use "U" shape PCB land because of trapping void during reflow.
Figure 6. Optimum Land Configurations
Table 1. Optimum Land Configurations
All Measurements in mm
Solder Mask
Type
SMO
Pad Size
Thickness
Aperture
Area Aspect
Ratio
0.4
SMD
0.225
0.300
0.076
0.250
0.82
NSMD
0.300
0.225
SMD
0.300
0.400
0.100
0.300
0.75
NSMD
0.400
0.300
0.127
0.350
0.69
0.152
0.400
0.66
0.152
0.450
0.74
0.65
0.8
1
6
Stencil Design
Ball Pitch
0.5
•
•
Ball Size, SMO, Pad Size and Apertures are Shown in Diameters
PCB Design
SMD
0.350
0.450
NSMD
0.450
0.350
SMD
0.400
0.500
NSMD
0.500
0.400
SMD
0.450
0.550
NSMD
0.550
0.450
Area Ratio = Area of Aperture / Area of Aperture Wall
For optimal release of solder paste, Area Ratio ≥ 0.66 is recommended.
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2.2
Conductor Width/Spacing
Figure 7 presents some design considerations based on commonly used PCB design rules.
Conventionally, the pads are connected by wide copper traces to other devices or to plated through holes
(PTH). As a rule, the mounting pads must be isolated from the PTH. Placing the PTH interstitially to the
land pads often achieves this.
(Not to scale)
0.350 mm
DIA. pad
0.100 mm line
0.65 mm
pitch
0.450 mm DIA.
solder mask
opening
0.254 mm
DIA. hole
NSMD pads
Figure 7. PCB Design Considerations (Conventional)
2.3
High-Density Routing Techniques
A challenge when designing with CSP packages is that as available space contracts, the space available
for signal fanout also decreases. Routing of nFBGA packages can be especially challenging because of
the tight ball pitch and a full array of solder balls that most packages have. By using a few high-density
routing techniques, the PCB designer can minimize many of these design and manufacturing challenges.
2.4
Via Density
Via density, as mentioned earlier, can be a limiting factor when designing high-density boards. Via density
is defined as the number of vias in a particular board area. Using smaller vias increases the routability of
the board by requiring less board space and increasing via density. The invention of the microvia, shown
in Figure 8, has solved many of the problems associated with via density.
Figure 8. Microvia Structure
Microvias are often created using a laser to penetrate the first few layers of dielectric. The laser can
penetrate a 4-mil-thick dielectric layer, creating the 4 μm microvia shown in Figure 8. The layout designer
can now route to the first internal board layer. Two layers (each 4 mils thick) can be laser-drilled, creating
a 200 μm microvia diameter. In this case, routing to the first two internal layers is possible.
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Conventional PCB Design
The relatively large via density on the package periphery, mentioned earlier, is caused by limited options
when routing the signal from the ball. To reduce or eliminate the via density problem on the periphery of
the package, designers can build the PCB vertically from the BGA pad through the internal layers of the
board, as shown in Figure 9. By working vertically and mechanically drilling 250 μm vias between the pads
on the board and the internal layers, designers can create a “pick-and-choose” method. They can pick the
layer and choose the route. A “dog bone” method is used to connect the through-hole via and the pad.
This reduces the risk of trapped voids that can reduce the board mount process margin.
This method requires a very small mechanical drill to create the necessary number of vias for one
package. Although this method is the least expensive, a disadvantage is that the vias go through the
board, creating a matrix of vias on the bottom side of the board, which may limit the use of using the back
side for routing.
Cross-sectional view
Top side view
Layer 1
Layer 2
Layer 3
Layer 4
Layer 5
Layer 6
Figure 9. "Dog Bone" Via Structure
2.6
Advanced Design Methods
Another option is to use a combination of blind and buried vias. Blind vias connect either the top or bottom
side of the board to inner layers. Buried vias usually connect only the inner layers. Figure 10 illustrates
this method using 4-mil laser-drilled microvias in the center of the pads and burying the dog bone on layer
2.
Solder wicks into
blind via filling void
Layer 1
Micro blind vias
Layer 2
Layer 3
Layer 4
Layer 5
Layer 6
10-mil through-hole
buried via
4-mil laser-drilled microvia may be
required to connect discretes on
bottom side of board
Figure 10. Buried Vias
Since the buried via does not extend through the underside of the board, the designer can use another set
of laser-drilled blind microvias, if needed, to connect the bypass capacitors and other discrete components
to the bottom side.
More information on these advanced techniques is available by contacting your local TI field sales office.
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3
Reliability
3.1
Daisy-Chained Units
Daisy-chained units are used to gain experience in the handling and mounting of CSPs for board-reliability
testing, to check PCB electrical layouts, and to confirm the accuracy of the mounting equipment. To
facilitate this, Texas Instruments offers daisy-chained units in all production nFBGA packages.
Each daisy-chained pinout differs slightly depending on package layout. An example is shown in
Figure 11. Daisy-chained packages are wired to provide a continuous path through the package for easy
testing. TI issues a net list for each package, which correlates each ball position with a corresponding wire
pad number. Examples of package net lists for production packages are included in Appendix B.
Figure 11. Daisy-Chained Pinout List (195ZWV nFBGA Package)
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Figure 12 shows a PCB layout for an 80 GQE daisy-chained package. When a daisy-chained package is
assembled on the PCB, a complete circuit is formed, which allows continuity testing. The circuit includes
the solder balls, the metal pattern on the die, the bond wires, and the PCB traces. The entire package or
only a quadrant can be interconnected and tested. A diagram of the test configuration is shown in
Figure 13.
Figure 12. PCB Layout for Daisy-Chained Unit
Tester
Wire bonds
BGA Package
Solder
balls
PCB
Copper traces
Test pads
Figure 13. Daisy-Chain Test Configuration
Reliability is one of the first questions designers ask about any new packaging technology. They want to
know how well the package will survive handling and assembly operation, and how long it will last on the
board. The elements of package reliability and system reliability, while related, focus on different material
properties and characteristics and are tested by different methods.
Package reliability focuses on materials of construction, thermal flows, material adherence/delamination
issues, resistance to high temperatures, moisture resistance and ball/stitch bond reliability. Thorough
engineering of the package is performed to prevent delamination caused by the interaction of the
substrate material and the mold compound.
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TI subjects each nFBGA to rigorous qualification testing before the package is released to production.
These tests are summarized in Table 2. All samples used in these tests are preconditioned according to
guidelines of the Joint Electronic Device Committee (JEDEC) A113 at various levels. Typical data is
presented in Table 3. The nFBGA packages have proven robust and reliable.
Table 2. Package-Level Reliability Tests
Test Environments
Conditions
Read Points
HAST
85RH/85°C
600 hrs., 1000 hrs.
Temp. Cycle
-55/125°C
500 cycles, 750 cycles, 1000 cycles
Thermal Shock
-55/125°C
200 cycles, 500 cycles, 750 cycles, 1000 cycles
HTOL
125°C, Op. voltage
500 hrs., 600 hrs., 1000 hrs.
HTOL (1)
140°C, Op. voltage
500 hrs.
(1)
HTOL
140°C, Op. voltage
500 hrs.
Bake (1)
150°C, 170°C
600 hrs., 1000 hrs., 420 hrs.
HAST (1)
170°C
96 hrs.
(1)
Optional tests. One or more of them may be added to meet customer requirements.
Table 3. Package-Level Reliability Test Results
Package Types
Leads
113ZVD
Body (mm)
Die (mm)
Level
289ZVL
289ZWE
8x8
12x12
13x13
4.2 × 4.2
5.8 × 5.7
10.6 × 8.2 (Die 1) 8.1 ×
7.7 (Die 2)
3
3
3
0/78
0/78
0/83
0/83
0/246
0/245
0/77
0/77
0/77
0/77
Test Environment
T/C, -55/125°C
(500 cycles)
(1000 cycles)
T/S, -55/125°C
(500 cycles)
(1000 cycles)
HAST,
85°C/85%RH
(600 cycles)
(1000 cycles)
0/78
0/78
0/78
0/78
0/77
0/77
150°C Storage
(600 cycles)
(1000 cycles)
0/45
0/45
0/77
0/77
0/77
0/77
HTOL
(1000 hrs.)
0/120
Board-level reliability (BLR) issues generally focus on the complex interaction of various materials under
the influence of heat generated by the operation of electronic devices. Not only is there a complex thermal
situation caused by multiple heat sources, but there are cyclical strains due to expansion mismatches,
warping and transient conditions, non-linear material properties, and solder fatigue behavior influenced by
geometry, metallurgy, stress relaxation phenomenon, and cycle conditions. In addition to material issues,
board and package design can influence reliability. Thermal management from a system level is critical for
optimum reliability, and thermal cycling tests are generally used to predict behavior and reliability. Many of
these are used in conjunction with solder fatigue life models using a modified Coffin-Manson strain rangefatigue life plots (number of cycles to failure has an inverse exponential relationship with the thermal cycle
temperature range).
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In addition to device/package testing, board-level reliability testing has been extensively performed on the
nFBGA packages. Various types of daisy-chained packages were assembled to special boards, with
electrical measurements made in the initial state and then at intervals after temperature cycles were run.
Table 4 shows a summary of a wide range of board-level reliability.
Table 4. Board-Level Reliability Summary
Failures/Sample Size
Conditions (With Solder Paste)
Package
Requirements
TI Mfg Site
Body
Pitch
Die
Temp.
500
Test Site
(mm)
(mm)
(mm)
Cycle (°C)
800
Extended Range
1000
1500
2000
(Cycles)
2500
3000
(Cycles)
ZVD
113 balls
TI Hiji
8×8
0.65
5x5
-40/125
0/36
0/36
0/36
0/36
0/36
0/36
0/36
ZVD
113 balls
TI Hiji
8×8
0.65
4.2x4.2
-40/125
0/48
0/48
0/48
0/48
0/48
0/48
4/43
ZVD
289 balls
TI Hiji
12×12
0.50
9x9
-40/125
0/95
0/95
0/95
0/95
0/95
0/94
0/94
ZVD
289 balls
TI Hiji
12×12
0.50
6.5x6.5
-40/125
0/36
0/36
0/36
0/36
0/36
0/36
1/36
Table 5 summarizes conclusions from the testing. Two important conclusions are that the PCB pad size
needs to match the via size, and that solder paste is needed for attachment to give optimal reliability.
Table 5. Summary of Significant BLR Improvements
Improved BLR →
Condition
Die size
Larger
→
Smaller
Die edge
Over balls
→
Within ball matrix
Ball count
Smaller
→
Larger
Ball size
Smaller
→
Larger
PCB pad size
Over/undersized
→
Matches package via (for NSMD ~90% of via)
Solder paste
None or insufficient
→
Thickness 0.10 nom. (type matches reflow)
3.2
Reliability Calculations
Another important aspect of predicting how a package will perform in any given application is reliability
modeling. Thermal, electrical, and thermomechanical modeling, verified by experimental results, provide
insight into system behavior, shorten package development time, predict system lifetimes, and provide an
important analytical tool. In applications such as BGAs, where the interconnections are made through
solder balls, the useful life of the package is, in most cases, dependent on the useful life of the solder
itself. This is an area that has been studied extensively, and very accurate models for predicting both
solder behavior and interpreting accelerated life testing exist.
The current methodology employed at Texas Instruments includes both extensive model refinement and
constant experimental verification. For a given package, a detailed 2D finite element model (FEM) is
constructed. This model is used to carry out 2D plain strain elastoplastic analysis to predict areas of high
stress. These models also account for the thermal variation of material properties, such as modulus of
elasticity, coefficient of thermal expansion, and Poisson’s Ratio as a function of temperature. These allow
the FEM to calculate the thermomechanical plastic strains in the solder joints for a given thermal loading.
The combination of finite element analysis (FEA), accurate thermal property information, and advanced
statistical methods allows prediction of the number of cycles to failure for various probability levels. Using
the assumption that cyclic fatigue lifetime follows a Weibull distribution, various probability levels can be
calculated. For these calculations, the Weibull shape parameter used is β = 4, which is based on
experimental data calibration. It is also consistent with available experimental data found in the literature
for leadless packages. This then results in the following equation: Nf(×%) = Nf(50%)[ln(10.01×)/ln(0.5)]1/β.
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Using this equation, and using the plastic strain ξp in combination with the S–N curves, the data below is
an example of the accuracy possible with this method:
Sample Finite Element Simulation and Life Prediction:
144 GGU @ T/C: -40/125°C
{Model}→ ξp = 0.353% on the outmost joint → Nf(50%)= 4434 cycles
→ Nf(1%) = 1539 cycles
{BLR Testing}→ -40/125°C (10 min/10 min)
→ Nf(1%) = 1657 cycles
Modeling is most useful in exploring changes in materials, designs, and process parameters without the
need to build experimental units. For example, modeling was used to study the effects of changes in
board thickness and pad size. Table 6 shows the simulated effects of pad size and board thickness on the
fatigue life of a 144-GGU package.
Table 6. Effects of Pad Size and Board Thickness on Fatigue Life
Example1: Effects of pad size on fatigue life
• Package: 144 GGU
• Die: 8.8 x 8.8 x 0.279 mm
• Board: FR-4 board 52 mils thick
Pad Dia.
(mils)
Pad Standoff
(mm)
Solder
Center Dia.
(mm)
Plastic Strain
(%)
Nf (1%) (cycles
to failure)
Difference
12
0.3847
0.4908
0.4400
998
0.88x
13
0.3689
0.4951
0.4127
1134
1
14
0.3523
0.5005
0.3908
1263
1.11x
15
0.3350
0.5060
0.3741
1377
1.21x
Board
Thickness
(mils)
Plastic Strain
(%)
Nf (1%)
(cycles to
failure)
Difference
50
0.4095
1152
1
31
0.4095
1249
1.08x
Example 2: Effects of board thickness on fatigue
life
•
•
•
•
3.3
Package: 144 GGU
Die: 8.8 x 8.8 x 0.279 mm
Board: FR-4
Pad Size: 13 mils
Package Characteristics
Texas Instruments has extensive package characterization capabilities, including an electrical
measurements lab with TDR/LRC (Time Domain Reflectometer/inductance resistance capacitance) and
network analysis capabilities, a thermal measurements lab with JEDEC standard test conditions up to
1000 watts, and extensive electrical, thermal, and mechanical modeling capability. Modeling was
implemented at TI starting in 1984. Stress analysis is done with the Ansys Analysis tool, which provides
full linear, nonlinear, 2D and 3D capabilities for solder reliability, package warpage, and stress analysis
studies. An internally developed tool (PACED™) is used for electrical modeling that gives 2.5D and full 3D
capability for LRC models, transmission lines, lossy dielectrics, and SPICE deck outputs. The thermal
modeling tool was also internally developed (ThermCAL™) and it provides full 3D automatic mesh
generation for most packages.
Complex geometries, transient analysis, and anisotropic materials can be modeled with it. With these
capabilities, a full range of modeling from device level through system level can be provided. Package
modeling is used to predict package performance at the design stage, to provide a package development
tool, to aid qualification by similarity, and as a failure analysis tool.
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Thermal Modeling
Figure 14 outlines the thermal modeling process. Thermal modeling data for sample nFBGA packages can
be found in Appendix C.
Heat Transfer Paths
Package
Chip
PWB
Conduction
Convection
Radiation
(TQFP shown for illustration purposes)
Model's three heat-transfer mechanisms:
- Conduction
- Convection
- Radiation
Method:
- Define solid
- Mesh solid
- Solve large number of simultaneous equations relating
each defined mesh point to each other
Sources of error:
- Convection coefficients
- Material properties
- Solid definition inaccuracies
Figure 14. Thermal Modeling Process
4
Surface-Mounting nFBGA Packages
Surface-mount technology (SMT) has evolved over the past decade from an art into a science with the
development of design guidelines and rules. While these guidelines are specific enough to incorporate
many shared conclusions, they are general enough to allow flexibility in board layouts, solder pastes,
stencils, fixturing, and reflow profiles. From experience, most assembly operations have found nFBGA
packages to be robust, manufacturing-friendly packages that fit easily within existing processes and
profiles. In addition, they do not require special handling. However, as ball pitch becomes smaller, layout
methodology and placement accuracy become more critical. Below is a review of the more important
aspects of surface-mounted CSPs. The suggestions provided may aid in efficient, cost-effective
production.
4.1
Design for Manufacturability (DFM)
A well-designed board that follows the basic surface-mount technology considerations greatly improves
the cost, cycle time, and quality of the end product. Board designers should comprehend the SMTautomated equipment used for assembly, including minimum and maximum dimensional limits and
placement accuracy. Many board shapes can be accommodated, but the front of the board should have a
straight and square edge to help machine sensors detect it. While odd-shaped or small boards can be
assembled, they require panelization or special tooling to process in-line. The more irregular the board —
non-rectangular with no cutouts — the more expensive the assembly cost.
Fiducials (the optical alignment targets that align the module to the automated equipment) should allow
vision-assisted equipment to accommodate the shrink and stretch of the raw board during processing.
They also define the coordinate system for all automated equipment, such as printing and pick-and-place.
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The following guidelines may be helpful:
• Automated equipment requires a minimum of two and preferably three fiducials.
• A wide range of fiducial shapes and sizes can be used. Among the most useful is a circle 1.6 mm in
diameter with an annulus of 3.175/3.71 mm. The outer ring is optional, but no other feature may be
within 0.76 mm of the fiducial.
• The most useful placement for the fiducials is an L configuration, which is orthogonal to optimize the
stretch/shrink algorithms. When possible, the lower left fiducial should be the design origin (coordinate
0,0).
• All components should be within 101.6 mm of a fiducial to assure placement accuracy. For large
boards or panels, a fourth fiducial should be added.
If the edges of the boards are to be used for conveyer transfer, a cleared zone of at least 3.17 mm should
be allowed. Normally, the longest edges of the board are used for this purpose, and the actual width is
dependent on equipment capability. While no component lands or fiducials can be in this area, breakaway
tabs may be.
Interpackage spacing is a key aspect of DFM, and the question of how close you can safely put
components to each other is a critical one. The following component layout considerations are
recommendations based on TI experience:
• There should be a minimum of 0.508 mm between land areas of adjacent components to reduce the
risk of shorting.
• The recommended minimum spacing between SMD discrete component bodies is equal to the height
of the tallest component. This allows for a 45° soldering angle in case manual work is needed.
• Polarization symbols need to be provided for discrete SMDs (diodes, capacitors, and so forth.) next to
the positive pin.
• Pin-1 indicators or features are necessary to determine the keying of SMD components.
• Space between lands (under components) on the backside discrete components should be a minimum
of 0.33 mm. No open vias may be in this space.
• The direction of backside discretes for wave solder should be perpendicular to the direction through
the wave.
• Do not put SMT components on the bottom side that exceed 200 grams per square inch of contact
area with the board.
• If space permits, symbolize all reference designators within the land pattern of the respective
components.
• It is preferable to have all components oriented in well-ordered columns and rows.
• Group similar components together whenever possible.
• Room for testing must be allowed.
4.2
Solder Paste
TI recommends the use of paste when mounting nFBGAs. The use of paste offers the following
advantages:
• It acts as a flux to aid wetting of the solder ball to the PCB land.
• The adhesive properties of the paste will hold the component in place during reflow.
• It helps compensate for minor variations in the planarity of the solder balls.
• Paste contributes to the final volume of solder in the joint, and thus allows this volume to be varied to
give an optimum joint.
Paste selection is normally driven by overall system assembly requirements. In general, the “no clean”
compositions are preferred due to the difficulty in cleaning under the mounted component. Most assembly
operations have found that no changes in existing pastes are required by the addition of nFBGA, but due
to the large variety of board designs and tolerances, it is not possible to say this will be true for any
specific application.
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Nearly as critical as paste selection is stencil design. A proactive approach to stencil design can pay large
dividends in assembly yields and lower costs. In general, nFBGA packages are special cases of BGA
packages, and the general design guidelines for BGA package assembly applies to them as well. There
are some excellent papers on BGA assembly, so only a brief overview of issues especially important to
nFBGA packages is presented here.
The typical stencil hole diameter should be the same size as the land area, and 100-120-μm-thick stencils
have been found to give the best results. Good release and a consistent amount of solder paste and
shapes are critical, especially as ball pitches decrease. The use of metal squeegee blades, or at the very
least, high durometer polyblades, is important in achieving this. Paste viscosity and consistency during
screening are some variables that require close control.
4.3
Solder Ball Collapse
To produce the optimum solder joint, it is important to understand the amount of collapse of the solder
balls, and the overall shape of the joint. These are a function of:
• The diameter of the package solder ball via.
• The volume and type of paste screened onto the PCB.
• The diameter of the PCB land.
• The board assembly reflow conditions.
• The weight of the package.
The original ball height on the package for a typical 0.5-mm-pitch package is 0.20 mm. After the package
is mounted, this typically drops to 0.15 mm, as illustrated in Figure 15.
0.20 ± 0.05 mm
Land on PCB
PCB
0.15 mm typical
PCB
(Not to scale)
Figure 15. Solder Ball Collapse
Controlling the collapse, and thus defining the package standoff, is critical to obtaining the optimum joint
reliability. Generally, a larger standoff gives better solder joint fatigue strength, but this should not be
achieved by reducing the board land diameter. Reducing the land diameter will increase the standoff, but
will also reduce the minimum cross-section area of the joint. This, in turn, will increase the maximum shear
force at the PCB side of the solder joint. Therefore, a reduction of land diameter will normally result in a
worse fatigue life, and should be avoided unless all the consequences are well understood.
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4.4
Reflow
Solder reflow conditions are the next critical step in the mounting process. During reflow, the solvent in the
solder paste evaporates, the flux cleans the metal surfaces, the solder particles melt, wetting of the
surfaces takes place by wicking of molten solder, the solder balls collapse, and finally solidification of the
solder into a strong metallurgical bond completes the process. The desired end result is a uniform solder
structure strongly bonded to both the PCB and the package with small or no voids and a smooth, even
fillet at both ends. Conversely, when all the steps do not carefully fit together, voids, gaps, uneven joint
thickness, discontinuities, and insufficient fillet can occur. While the exact cycle used depends on the
reflow system and paste composition, there are several key points all successful cycles have in common.
The first of these is a warm-up period sufficient to safely evaporate the solvent. This can be done with a
pre-heat or a bake, or, more commonly, a hold in the cycle at evaporation temperatures. If there is less
solvent in the paste (such as in a high-viscosity, high-metal-content paste), then the hold can be shorter.
However, when the hold is not long enough to get all of the solvent out or too fast to allow it to evaporate,
many negative things happen. These range from solder-particle splatter to trapped gases, which can
cause voids and embrittlement. A significant number of reliability problems with solder joints can be solved
with the warm-up step, so it needs careful attention.
The second key point that successful reflow cycles have in common is uniform heating across the
package and the board. Uneven solder thickness and non-uniform solder joints may be an indicator that
the profile needs adjustment. There can also be a problem when different sized components are reflowed
at the same time. Care needs to be taken when profiling an oven to be sure that the indicated
temperatures are representative of what the most difficult to reflow parts are seeing. These problems are
more pronounced with some reflow methods, such as infrared (IR) reflow, than with others, such as forced
hot-air convection.
Finally, successful reflow cycles strike a balance among temperature, timing, and length of cycle.
Mistiming may lead to excessive fluxing activation, oxidation, excessive voiding, or even damage to the
package. Heating the paste too hot, too quickly before it melts can also dry the paste, which leads to poor
wetting. Process development is needed to optimize reflow profiles for each solder paste/flux combination.
The profile shown in Figure 16 is an ideal one for use on a Pb-Free nFBGA package in a forced-airconvection furnace, which is the most highly recommended type. The best results have been found in a
nitrogen atmosphere. The corresponding optimal reflow profile for an nFBGA package exhibiting eutectic
SnPb solder balls is shown in Figure 17.
The guidelines upon which these profiles are based are general. Modification to the ideal reflow profile will
be driven by the interplay of solder-paste particle size and flux percentage with process variables such as
heating rates, peak temperatures, board construction factors, and atmosphere. These modifications are
dependent on specific applications.
It should be noted that while they are more rugged than most CSP-type packages, many nFBGA
packages are still slightly moisture-sensitive at the time of publishing this application report. The time out
of a dry environment should be controlled according to the label on the packing material. This will prevent
moisture absorption problems with the package such as “popcorning,” or delamination.
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Peak Temperature
250º C Max < 10sec
225º C
30~60sec
185º C
165º C
90 ± 30 sec
1 ~ 5°C
sec
175 ± 10C
1 ~ 5°C
sec
90 ± 30 sec
225°C
30 ~ 60 sec
245 ~ 250°C peek
10 sec
RT to 150 ± 10C
Figure 16. Recommended Reflow Profile of Pb-Free nFBGA Package
ºC
Recommended Reflow Profile In Case of SnPb eutectic solder paste
235
Peak Temperature
235ºC Max < 10 sec
200
30~60 sec
160
140
90 +
~ 30 sec
1 ~ 5°C
sec
time
Reflow temperature is defined at package top.
Figure 17. Recommended Reflow Profile of Eutectic SnPb nFBGA Package
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Other concerns with BGA packages are those caused by a PCB bowing or twisting during reflow. As
PCBs get thinner, these problems will become more significant. Potential problems from these effects will
show up as open pins, hourglass solder joints, or solder discontinuities. Proper support of the PCB
through the furnace, balancing the tab attachments to a panel, and, in worst cases, using a weight to
stiffen the PCB can help prevent this. In general, the small size of CSPs create fewer problems than
standard BGAs. It is also true that BGAs generally have fewer problems than leaded components.
4.5
Inspection
The nFBGA packages have been designed to be consistent with very high-yield assembly processes.
Because of their relatively light weight, nFBGA packages tend to self-align during reflow. Since the pitch of
the ball pattern is large compared to that of fine-pitch leaded packages, solder bridging is rarely
encountered. It is recommended that a high-quality solder joint assembly process be developed using the
various inspection and analytical techniques, such as cross-sectioning. Once a quality process has been
developed, detailed inspection should not be necessary. Visual methods, while obviously limited, can offer
valuable clues to the general stability of the process. Electrical checks can confirm interconnection. Both
transmission X-rays and laminographic X-rays have proven to be useful nondestructive tools, if desired.
5
Packing and Shipping
The nFBGA packages are shipped in either of two packing methods:
• Trays
• Tape and Reel
5.1
Tray Packing Method
Thermally resistant plastic trays are one of two methods currently used to ship these packages. Each
family of pats with the same package outline has its own individually designed tray. The trays are
designed to be used with pick-and-place machines. Figure 18 gives typical tray details, and Table 7 shows
the number of units per tray.
The steps following Table 7 illustrate the packing method used to ship trays. Before the trays are sealed in
the aluminum lined plastic bag, they are baked in accordance with the requirements for dry-packing at the
appropriate level.
Figure 18. Shipping Tray Detail
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Table 7. Number of Units per Shipping Tray
Body Size (mm)
Matrix
Units/Tray
Units/Box
8×8
10 × 26
260
2600
10 × 10
8 × 23
184
1840
10 × 10
8 × 21
168
1680
13 × 13
8 × 20
160
1600
7 × 17
7 × 18
126
1260
14 × 14
7 × 17
126
1190
16 × 16
6 v 15
126
900
1. Arrange the stack of trays to be packed with a tray pad on the top and bottom.
Tray
pad
Tray
stack
Tray
pad
2. Strap the tray stack and pads together with four straps—three crosswise and one lengthwise. Then,
place the desiccants and the humidity indicator on top.
Humidity
indicator
Desiccant
packs
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3. Place the lot inside the aluminum-lined bag and vacuum-seal it. Place the necessary labels on the
sealed bag
Aluminum-lined
bag
ESD lable
Moisture-sensitivity label
Bar-code lable
4. Wrap and tap bubble pack around the bag for a snug fit in the inner carton. Place the necessary labels
on the inner carton.
ESD lable
Bar-code lable
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5. Add bubble pack around the inner carton for a snug fit in the skidboard liner.
6. Place four foam corner spacers on the folded skidboard liner before placing it in the outer carton. An
enhanced skidboard liner, which eliminates the need for foam spacers, may be used. Seal outer carton
and apply necessary labels.
5.2
Tape-and-Reel Packing Method
The embossed tape-and-reel method is generally preferred by automatic pick-and-place machines,
although trays remain an option for those customers who prefer them for nFBGA packages. The tape is
made from an antistatic/conductive material. The cover tape, which peels back during use, is heat-sealed
to the carrier tape to keep the devices in their cavities during shipping and handling. The tape-and-reel
packaging used by Texas Instruments is in full compliance with EIA Standard 481-A, “Taping of SurfaceMount Components for Automatic Placement.” The static-inhibiting materials used in the carrier-tape
manufacturing provide device protection from static damage, while the rigid, dust-free polystyrene reels
provide mechanical protection and clean-room compatibility with dereeling equipment currently available
on most high-speed automated placement systems.
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5.3
Tape Format
Typical tape format is shown in Figure 21. The variables used in Figure 19 and Table 8 are defined as
follows: W is the tape width; P is the pocket pitch; A0 is the pocket width; B0 is the pocket length; K0 is the
pocket depth; K is the maximum tape depth; and F is the distance between the drive hole and the
centerline of the pocket.
2.00 ± 0.05
P
K
+ 0.1
1.5 - 0.0
4.0 ± 0.10
0.40
0.8 MIN
F
W
B0
Cover
tape
A0
Carrier tape
embossment
1.5 MIN
Diameter
0 MIN
K0
Direction
of feed
Figure 19. Single Sprocket Tape Dimension
Table 8. Tape Dimensions (1)
Tape Width
(W)
(1)
Pocket Pitch
(P)
Pocket Width
(A0)
Pocket Length
(B0)
Pocket Depth
(K0)
Max. Tape
Depth (K)
Centerline to
Drive Hole (F)
Package
Size
16
8
6.3
6.3
1.35
0.75
7.5
6×6
16
12
8.3
8.3
1.85
1.10
7.5
8×8
24
16
10.3
10.3
1.90
1.10
11.5
10 × 10
24
16
12.3
12.3
2.00
1.10
11.5
12 × 12
24
16
13.3
13.3
2.00
1.30
11.50
13 × 13
24
24
14.3
14.3
1.40
0.70
11.50
14 × 14
All dimensions are in millimeters.
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The reels are shown in Figure 20. In this figure, G is the width of the tape, N is the diameter of the hub,
and T is the total reel thickness.
T MAX
13.0 ± 0.2
+ 0.0
330 - 4.0
N
20.2 MIN
2.5 MIN
1.5 MIN width
TI bar code label
G
Figure 20. Reel Dimensions
Table 9. Reel Dimensions (1)
(1)
Tape Width (G)
Reel Hub Diameter (N)
Reel Total Thickness
(T MAX)
Parts per Reel
16
100
16.4
2500
24
100
24.4
1000
After the parts are loaded into the reel, each individual reel is packed in its own “pizza” box for shipping, as shown in Figure 21.
After the parts are loaded into the reel, each individual reel is packed in its own “pizza” box for shipping,
as shown in Figure 21.
Desiccant
Humidity
indicator
Reeled units
Aluminum
bag
Pizza box
2D Label
Figure 21. Tape-and-Reel Packing
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5.4
Device Insertion
Devices are inserted toward the outer periphery of the tape by placing the side with the device name face
up and the side with the balls attached face down. The pin-1 indicator is placed in the top left-hand corner
of the pocket, next to the sprocket holes.
5.5
Packaging Method
For reels, once the taping has been completed, the end of the leader is fixed onto the reel with tape. The
product name, lot number, quantity, and date code are recorded on the reel and the cardboard box used
for tape delivery. Each reel is separately packed in a cardboard box for delivery.
Trays are packed with five loaded trays and one empty tray on top for support and to keep packages
secure. The stack is secured with stable plastic straps and sealed in a moisture-proof bag.
Customer-specific bar code labels can be added under request or general purchasing specification.
Moisture-sensitive packages are baked before packing and are packed within 8 hours of coming out of the
oven. Both the tape-and-reel and the tray moisture-proof bags are sealed and marked with appropriate
labeling warning that the packages inside the bags are dry-packed and giving the level of moisture
sensitivity.
6
Sockets
6.1
The Design Challenge
The fine pitch of nFBGA packages makes socketing a special challenge. Mechanical, thermal, and
electrical issues must be accommodated by the socket designer. The size of a specific package within the
TI nFBGA family is based on the package construction, and is independent of die size. Therefore, a range
of die sizes and I/Os within a family will have the same package dimensions. Each different family has a
specific I/O pitch and array. For maximum socket versatility, an adapter or “personalizer” can be
customized for each application, allowing a single-socket body to be used with many packages. This
feature is especially useful in the early days as the technology is being developed and adopted as well as
during volume production phase to minimize socket costs.
6.2
Contacting the Ball
A number of different approaches for contacting the solder ball are shown schematically in Figure 22. The
pinch style contact has been used extensively for contacting solder balls in conventional BGAs and is
starting to be proposed also for the most advanced fine pitch CSP packages.
The most common methods used for contacting as small as 0.4 mm pitch CSP packages are either metal
pinch (a) or metal (f). Both methods provide the most reliable solutions with less ball deformation and
small socket form factor at an affordable cost. Texas Instruments Interconnect Business Unit (TI IBU) has
designed both pinch and micro tuning fork (metal type) contacts that satisfy all of these requirements.
Further information on the availability of these sockets can be obtained from your local TI Field Sales
representative.
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a) Metal pinch
b) Metal “Y”
c) Rough bump on flex
d) Conductive
e) Etched pocket in silicon
f) Metal
Figure 22. Approaches for Contacting the Solder Ball
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6.3
Pinch Contact
The contact is designed to grip the solder ball with a pinching action. This not only provides electrical
contact to the solder ball but also helps retain the package in the socket. The contact is shown in
Figure 23. It was made using a beryllium copper alloy. This alloy is used for spring applications that are
exposed to high stresses and temperatures because of its excellent stress relaxation performance and
formability.
Figure 23. Pinch Contact for Solder Ball
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Each contact incorporates two beams that provide an oxide-piercing interface with the sides of the balls
above the central area—the equator. No contact is made on the bottom of the solder ball so the original
package planarity specifications are unchanged. A photo-micrograph of the contact touching the solder
balls is shown in Figure 24.
Figure 24. Contact Area on Solder Ball
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The witness marks left on the solder ball from the contact are shown in Figure 25. This ball was contacted
at room temperature and it is clear that there was no damage to the bottom of the ball or any witness
marks from the contact above the equator.
Figure 25. Witness Marks on Solder Ball
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The effect of burn-in on the probe marks was examined by simulating a cycle and placing a loaded socket
into an oven at 125°C for nine hours. The result is shown in Figure 26. The penetration of the contact into
the solder ball due to the higher temperature is greater but is well within the acceptable range. There was
no visible pickup of solder on the contact tips. The location of the contact pinch is clearly seen in this
photograph.
Figure 26. Effect of Bur-In on Probe Mark
6.4
Micro Tuning Fork Contact
Micro tuning fork contact system with vertical launch secures the solder balls to provide stable electrical
continuity. Figure 27 shows how the micro fork contacts solder ball as well as solder witness marks after
24 hours at 150°C. There is also no contact made on the bottom of the solder ball preventing ball damage
that could affect solder ball planarity specification, as illustrated in Figure 28.
Figure 27. Micro Tuning Fork Contact for 0.5mm Pitch
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Contact Tip
IC Ball Mark (After 24 Hr @ 150 C)
Side View
Top View
Figure 28. Micro Tuning Fork Contact and Contact Marks on Solder Balls
6.5
Texas Instruments Sockets
Pictures below are showing Texas Instruments most advanced 0.8 mm and 0.5 mm pitch showing :
• Very small form factor
• Open top solution for easy automatic loading/unloading operations.
Figure 29. Socket Examples: Tuning Fork (Left) and Pinch Style (Right)
6.6
Conclusion
Some very good progress has been made during the past few years in developing fine pitch CSP
packages sockets for CSP ball pitch. Sockets are now very common and proposed by most sockets
manufacturers with open top or clam shell options.
Texas Instruments Interconnect Business Unit will provide you with a complete range of sockets
technology for CSP package. For further information your local TI Field Sales representative can give you
up-to-date information or please visit web site http://www.ti.com/snc/products/controls/burnin.htm
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nFBGA Packaging
31
Appendix A
SPRAA99B – March 2008 – Revised November 2015
Frequently Asked Questions
A.1
Package Questions
Q
A
Q
A
Q
A
Q
A
Q
A
Q
A
32
Do the solder balls come off during shipping?
No, this has never been observed. The balls are inspected for coplanarity, diameter, and other
physical properties prior to packing for shipment. Because solder is used during the ballattachment process, uniformly high ball-attachment strengths are developed. Also, the ballattachment strength is monitored frequently in the assembly process to prevent ball loss from
vibration and other shipping forces.
Is package repair possible? Are tools available?
Yes, some limited package repair is possible, and there are some semiautomatic M/C tools
available. However, TI does not specify the reliability of repaired packages.
What are the leads that appear on the package edge for? Are they connected to the inner
pattern?
Those leads are used for plating connections during the plating of Ni/Au on the copper trace
during the fabrication of the substrate. Since they do have electrical connection with the inner
pattern, they can be used for test probing and signal analysis. There is no reliability risk with
them.
Is burn-in testing possible? How about ball damage?
There are commercial sockets available for fine pitch package burn-in. For further information
your local TI Field Sales representative can give you up-to-date information. The ball damage
observed falls within specified tolerances, so the testing does not affect board mount.
Is tape-and-reel shipping available?
Yes, tape-and-reel is an available method for shipping nFBGA packages.
How does the packaging cost compare to QFPs?
CSPs are in many ways an ideal solution to cost reduction and miniaturization requirements.
They offer enormous area reductions in comparison to QFPs and have increasing potential to do
so without adding to system-level costs. In the best case, CSPs compete today on a cost-perterminal basis with QFPs. For example, various CSPs from Texas Instruments are now available
at cost parity within QFPs.
nFBGA Packaging
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Assembly Questions
www.ti.com
A.2
Assembly Questions
Q
A
Q
A
Q
A
Q
A
Q
A
Q
A
What alignment accuracy is possible?
Alignment accuracy for the nFBGA package is dependent upon board-level pad tolerance,
placement accuracy, and solder ball position tolerance. Nominal ball position tolerances are
specified at ±50 μm. These packages are self-aligning during solder reflow, so final alignment
accuracy may be better than placement accuracy.
Can the solder joints be inspected after reflow?
Process yields of 5-ppm (parts per million) rejects are typically seen, so no final in-line inspection
is required. Some customers are achieving satisfactory results during process set-up with
lamographic X-ray techniques.
How do the board assembly yields of nFBGAs compare to QFPs?
Many customers are initially concerned about assembly yields. However, once they had nFBGA
packages in production, most of them report improved process yields compared to QFPs. This is
due to the elimination of bent and misoriented leads, and the ability of these packages to selfalign during reflow. The collapsing solder balls also mean that the coplanarity is improved over
leaded components.
Are there specific recommendations for SMT processing?
Texas Instruments recommends alignment with the solder balls for the CSP package, although it
is possible to use the package outline for alignment. Most customers have found they do not
need to change their reflow profile.
Can the boards be repaired?
Yes, there are rework and repair tools and profiles available. TI strongly recommends that
removed packages be discarded.
What size land diameter for these packages should I design on my board?
Land size is the key to board-level reliability, and Texas Instruments strongly recommends
following the design rules included in this document.
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33
Appendix B
SPRAA99B – March 2008 – Revised November 2015
Package Data Sheets
Table 10 shows TI’s strategic package lineup, followed by package data sheets for many of the package
families offered as standard products by Texas Instruments. As new packages are added, they will be
placed on the strategic package lineup. Contact your TI field sales office for information on the most
current offerings. Samples are available for all packages shown in Table 10.
Table 10. TI’s Strategic Package Line-Up
nFBGA Package Product Guide
Pitch
(mm)
Package Size (mm)
6×6
7×7
8×8
0.8
0.65
34
nFBGA Packaging
10×10
12×12
13×13
145ZWS
14×14
16×16
361ZWT
113ZVD
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Appendix B
www.ti.com
Table 10. TI’s Strategic Package Line-Up (continued)
nFBGA Package Product Guide
Package Size (mm)
Pitch
(mm)
6×6
7×7
8×8
10×10
12×12
13×13
14×14
0.5
87ZVW
72ZST
195ZWV
225ZWF
289ZVL
289ZWE
447ZAC
241ZWG
293ZVL
143ZWU
143ZZC
318ZVL
152ZZB
325ZVL
16×16
447ZAF
385ZWK
385ZWM
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35
Appendix B
www.ti.com
Table 10. TI’s Strategic Package Line-Up (continued)
nFBGA Package Product Guide
Pitch
(mm)
Package Size (mm)
6×6
0.4
7×7
209ZXN
8×8
10×10
12×12
13×13
14×14
16×16
241ZWJ
289ZWJ
360ZWJ
Figure 30. 87ZVW Package Outline (6 x 6mm, 0.5mm pitch)
87ZVW Daisy Chain Net List Not Available
36
nFBGA Packaging
SPRAA99B – March 2008 – Revised November 2015
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Appendix B
www.ti.com
Figure 31. 72ZST Package Outline (7 x 7mm, 0.5mm pitch)
72ZST Daisy Chain Net List Not Available
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37
Appendix B
www.ti.com
Figure 32. 143ZZC Package Outline (7 x 7mm, 0.5mm pitch)
143ZZC Daisy Chain Net List Not Available
38
nFBGA Packaging
SPRAA99B – March 2008 – Revised November 2015
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Appendix B
www.ti.com
Figure 33. 143ZWU Package Outline (7 x 7mm, 0.5mm pitch)
Figure 34. 143ZWU Daisy Chain Net List
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39
Appendix B
www.ti.com
Figure 35. 152ZZB Package Outline (7 x 7mm, 0.5mm pitch)
152ZZB Daisy Chain Net List Not Available
40
nFBGA Packaging
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Appendix B
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Figure 36. 209ZXN Package Outline (7 x 7mm, 0.4mm pitch)
209ZXN Daisy Chain Net List Not Available
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41
Appendix B
www.ti.com
Figure 37. 113ZVD Package Outline (8 x 8mm, 0.65mm pitch)
42
nFBGA Packaging
SPRAA99B – March 2008 – Revised November 2015
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Appendix B
www.ti.com
Figure 38. 113ZVD Daisy Chain Net List
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43
Appendix B
www.ti.com
Figure 39. 195ZWV Package Outline (8 x 8mm, 0.5mm pitch)
Figure 40. 195ZWV Daisy Chain Net List
44
nFBGA Packaging
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Appendix B
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Figure 41. 225ZWF Package Outline (10 x 10mm, 0.5mm pitch)
225ZWF Daisy Chain Net List Not Available
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45
Appendix B
www.ti.com
Figure 42. 241ZWG Package Outline (10 x 10mm, 0.5mm pitch)
241ZWG Daisy Chain Net List Not Available
46
nFBGA Packaging
SPRAA99B – March 2008 – Revised November 2015
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Appendix B
www.ti.com
Figure 43. 241ZWJ Package Outline (10x10mm, 0.4mm pitch)
Figure 44. 241ZWJ Daisy Chain Net List
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47
Appendix B
www.ti.com
Figure 45. 289ZWJ Package Outline (10 x 10mm, 0.4mm pitch)
48
nFBGA Packaging
SPRAA99B – March 2008 – Revised November 2015
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Appendix B
www.ti.com
Figure 46. 289ZWJ Daisy Chain Net List
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49
Appendix B
www.ti.com
Figure 47. 360ZWJ Package Outline (10 x 10mm, 0.4mm pitch)
Figure 48. 360ZWJ Daisy Chain Net List
50
nFBGA Packaging
SPRAA99B – March 2008 – Revised November 2015
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Appendix B
www.ti.com
Figure 49. 145ZWS Package Outline (12 x 12mm, 0.8mm pitch)
145ZWS Daisy Chain Net List Not Available
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51
Appendix B
www.ti.com
Figure 50. 289ZVL Package Outline (12 x 12mm, 0.5mm pitch)
289ZVL Daisy Chain Net List Not Available
52
nFBGA Packaging
SPRAA99B – March 2008 – Revised November 2015
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Appendix B
www.ti.com
Figure 51. 293ZVL Package Outline (12 x 12mm, 0.5mm pitch)
293ZVL Daisy Chain Net List Not Available
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53
Appendix B
www.ti.com
Figure 52. 318ZVL Package Outline (12 x 12mm, 0.5mm pitch)
318ZVL Daisy Chain Net List Not Available
54
nFBGA Packaging
SPRAA99B – March 2008 – Revised November 2015
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Appendix B
www.ti.com
Figure 53. 325ZVL Package Outline (12 x 12mm, 0.5mm pitch)
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55
Appendix B
www.ti.com
Figure 54. 325ZVL Daisy Chain Net List
56
nFBGA Packaging
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Appendix B
www.ti.com
Figure 55. 385ZWM Package Outline (12 x 12mm, 0.5mm pitch)
385ZWM Daisy Chain Net List Not Available
SPRAA99B – March 2008 – Revised November 2015
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nFBGA Packaging
57
Appendix B
www.ti.com
Figure 56. 385ZWK Package Outline (12 x 12mm, 0.5mm pitch)
Figure 57. 385ZWK Daisy Chain Net List
58
nFBGA Packaging
SPRAA99B – March 2008 – Revised November 2015
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Appendix B
www.ti.com
Figure 58. 289ZWE Package Outline (13 x 13mm, 0.5mm pitch)
289ZWE Daisy Chain Net List Not Available
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59
Appendix B
www.ti.com
Figure 59. 447ZAC Package Outline (14 x 14mm, 0.5mm pitch)
447ZAC Daisy Chain Net List Not Available
60
nFBGA Packaging
SPRAA99B – March 2008 – Revised November 2015
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Appendix B
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Figure 60. 447ZAF Package Outline (14 x 14mm, 0.5mm pitch)
447ZAF Daisy Chain Net List Not Available
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61
Appendix B
www.ti.com
Figure 61. 361ZWT Package Outline (16 x 16mm, 0.8mm pitch)
62
nFBGA Packaging
SPRAA99B – March 2008 – Revised November 2015
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Appendix B
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Figure 62. 361ZWT Daisy Chain Net List
SPRAA99B – March 2008 – Revised November 2015
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63
Appendix C
SPRAA99B – March 2008 – Revised November 2015
Thermal Modeling Results
Table 11, Table 12, and Table 13 detail thermal modeling results from 8x8mm, 12x12mm, and 16x16mm
nFBGA packages, respectively.
Table 11. 8×8 mm nFBGA Thermal Simulation Result
Power = 1w
Die Size (mm)
2.0 × 2.0 mm
4.0 × 4.0 mm
6.0 × 6.0 mm
Velocity (m/s)
1S0P
2S2P
1S0P
2S2P
1S0P
2S2P
0
140.148
101.061
100.476
61.161
89.286
50.352
1
129.084
97.211
89.269
57.353
78.173
46.554
2
124.432
96.281
84.656
56.439
73.714
45.622
3
121.435
95.611
81.895
55.675
70.399
44.774
0
2.244
2.076
0.625
0.462
0.509
0.342
1
2.238
2.066
0.582
0.429
0.480
0.308
2
2.215
2.062
0.559
0.403
0.441
0.290
3
2.196
2.059
0.545
0.399
0.429
0.278
0
78.144
80.346
32.656
33.063
20.345
21.658
1
75.007
77.987
30.032
32.785
18.921
21.539
2
74.760
77.876
29.997
32.687
18.710
21.437
3
74.616
77.742
29.733
32.200
18.306
21.380
θJC (°C/W)
29.984
—
12.050
—
7.347
—
θJB (°C/W)
77.056
78.643
31.636
33.043
19.899
21.226
θJA (°C/W)
Pusai JT
(°C/W)
Pusai JB
(°C/W)
Table 12. 12×12 mm nFBGA Thermal Simulation Result
Power = 1w
Die Size (mm)
3.0 × 3.0 mm
6.5 × 6.5mm
10.0 × 10.0 mm
Velocity (m/s)
1S0P
2S2P
1S0P
2S2P
1S0P
2S2P
0
89.520
62.812
61.940
35.763
53.538
28.380
1
80.639
59.169
52.553
32.150
44.582
24.786
2
77.284
58.444
49.596
31.427
41.273
24.032
3
75.257
57.923
47.675
30.897
39.314
23.518
0
0.855
0.623
0.373
0.274
0.306
0.216
1
0.791
0.589
0.356
0.239
0.246
0.183
2
0.782
0.588
0.321
0.209
0.236
0.176
3
0.732
0.585
0.300
0.207
0.227
0.156
0
46352
49.411
15.822
18.310
8.886
10.687
1
45.699
49.091
15.689
17.954
8.650
10.422
2
45.553
48.646
15.499
17.922
8.472
10.405
3
45.483
48.208
15.424
17.903
8.287
10.380
θJC (°C/W)
16.586
—
5.742
—
4.428
—
θJB (°C/W)
46.695
47.787
15.894
16.429
8.180
8.604
θJA (°C/W)
Pusai JT
(°C/W)
Pusai JB
(°C/W)
64
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Appendix C
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Table 13. 16×16 mm nFBGA Thermal Simulation Result
Power = 1w
Die Size (mm)
3.0 × 3.0 mm
8.5 × 8.5mm
14.0 × 14.0 mm
Velocity (m/s)
1S0P
2S2P
1S0P
2S2P
1S0P
2S2P
0
88.870
69.542
48.861
27.847
39.056
21.145
1
81.509
66.538
69.164
24.125
31.690
17.579
2
79.283
65.851
36.777
23.404
28.913
16.870
3
77.860
65.395
35.387
22.974
27.514
16.410
0
0.888
0.820
0.290
0.355
0.237
0.181
1
0.828
0.755
0.226
0.280
0.177
0.103
2
0.808
0.740
0.225
0.155
0.164
0.099
3
0.801
0.737
0.218
0.153
0.159
0.098
0
59.993
61.429
11.901
12.620
5.252
5.523
1
59.895
61.026
11.667
11.925
5.231
5.470
2
59.349
59.877
11.270
11.591
4.806
5.267
3
59.284
59.842
11.176
11.584
4.776
5.104
θJC (°C/W)
20.002
—
3.797
—
1.853
—
θJB (°C/W)
57.658
58.886
10.183
10.717
4.898
5.158
θJA (°C/W)
Pusai JT
(°C/W)
Pusai JB
(°C/W)
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Revision History
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Revision History
Changes from A Revision (September 2015) to B Revision .......................................................................................... Page
•
Updates were made in Section 2.2.
....................................................................................................
7
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
66
Revision History
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