Texas Instruments | Board Level Reliability Primer for Embedded Processors_ | Application notes | Texas Instruments Board Level Reliability Primer for Embedded Processors_ Application notes

Texas Instruments Board Level Reliability Primer for Embedded Processors_ Application notes
Application Report
SPRABY2 – March 2015
Board Level Reliability Primer for Embedded Processors
Lee McNally
This application report discusses the fundamentals of board level reliability (BLR) (sometimes referred to
in literature as “second-level reliability”) testing and modeling as applied by the Texas Instruments
Embedded Processing Group.
Introduction ...................................................................................................................
Test Environments ...........................................................................................................
Test Method ..................................................................................................................
Modeling Approach ..........................................................................................................
References ...................................................................................................................
List of Figures
Representative Optical Micrograph Image of Intrinsic Solder Joint Fatigue Failure ................................ 3
Typical Weibull 2-P Plot for Board Level Reliability Temp Cycle Data
Weibull 2-P Contour Plots for Shape (Beta) and Scale (Eta) Parameters ...........................................
BLR is a broad-based topic generally encompassing the thermo-mechanical degradation behavior in time
(application field use) of surface-mounted IC components on printed circuit boards (PCBs). Reliability
characterization activities are normally focused on ball grid array (BGA) or QFN packages, as leaded QFP
technologies, generally being more mature, have been well-characterized in the past and are established
as relatively low BLR risk, except perhaps for the most demanding applications. Unlike component-level
reliability testing with BLR, the distinctive requirement is that the component is surface mounted to the test
board/interposer, ideally emulating thermo-mechanical stresses that the component would be exposed in
the application. (The test board design, construction and materials are selected with this goal.)
BLR thermo-mechanical characterization can include environments such as temperature cycling, thermal
shock, mechanical shock, vibration and mechanical bending. The overriding purpose is to characterize the
“intrinsic” thermo-mechanical fatigue behavior of the region between the package and the PCB commonly
referred to as the “second-level” interface (as opposed to die bumps between the package substrate and
die, which is referred to as “first-level” interface). For example, on a BGA package this would imply failure
in the solder ball or the interface of the solder ball with the package substrate or PCB land pad. The term
“intrinsic” in this context is intended to imply end-of-life behavior (material wear-out), not including early
failures due arising from manufacturing defects either with the component package or the PCB, or,
alternatively, from the surface mount process of the component to the PCB.
All trademarks are the property of their respective owners.
SPRABY2 – March 2015
Submit Documentation Feedback
Board Level Reliability Primer for Embedded Processors
Copyright © 2015, Texas Instruments Incorporated
Test Environments
Test Environments
At Texas Instruments Embedded Processing, the BLR evaluation tests chosen for the particular
component or package are determined by the package technology itself as well as the target end-use
equipment. Temperature cycle testing is included in almost all cases where BLR testing is performed.
Mechanical tests, on the other hand, are more selectively performed depending on the targeted equipment
and customer base. Broadly speaking, special test vehicles called “daisy chains” are constructed for the
purpose of BLR testing and other targeted mechanical evaluations of the package. The “daisy chain”
package usually does not contain the functional die, rather a specially constructed die and substrate with
metal routes and nets that extend from the package substrate through the second-level interface (BGA or
QFN terminals) to the PCB. Depending on the design, the routing of the nets may also extend into the
daisy chain die, which would imply through the “first-level” interface on a bumped device, and the die may
contain various vertical levels of metallization. The “daisy chain” design (including the ball and terminal
footprint) and materials at a minimum should closely match the final production component in terms of
stress and strain profile at the first level interface (solder balls). Specialized BLR test boards are designed
to interface with the test oven electronics and manufactured, again, with the goal of being representative
of the end-use application board.
Test Method
Unless indicated otherwise, TI follows the IPC-9701 specification for Temperature Cycle testing [2].
Changes in resistance are monitored in-situ, for example, virtually real time with monitoring equipment.
This approach is in contrast to non-in-situ, whereby, boards are removed from stress and “readout” of
resistance changes is performed with meters external to the temperature cycle chamber. One of the key
advantages of in-situ is that precise cycles to failure for a given test DUT can be determined, thus,
improving the accuracy of the subsequent reliability modeling. Usual IPC-9701 temp cycle conditions used
by TI are 0°C-100°C or -40°C-125°C (sometimes both), with the selections determined according targeted
application areas for the products under qualification. Ramp and dwell time targets and tolerances are
specified within the IPC-9701 document. The ramp and dwell profile is particularly important in context of
the key failure mechanism of intended focus – solder joint creep.
Factors Affecting Reliability Performance
A myriad of factors can influence the ultimate reliability performance of the system (component surface
mounted to PCB). Among the prominent factors are:
• PCB material (FR4), thickness, layering and design (via under pad)
• PCB land pad design (SMD, non-SMD), paste material and solder stencil thickness
• Use of under-fill and choice of under-fill materials between PCB and component
• Solder ball (BGA) material (eutectic Sn/Pb, SAC387, SAC305)
• Package substrate to BGA interface and attach materials (electrolytic Ni/Au, thin Ni, SOP, Cu-OSP,
• BGA size and diameter, pitch, grid array layout (populated or de-populated grid locations)
• Die dimensions and location of edges with respect to solder ball locations
• Package lid or mold compound materials
The choice of solder ball material is particularly salient in optimization of the package for targeted failure
mechanisms such as impact or shock resistance. No single alloy is ideal for all environments and uses
although usually choices are made based on optimization for a key, primary factor (temperature, vibration,
shock, and so forth) and good or at least acceptable performance for secondary factors. As a general
case, TI’s material selection is optimized for temperature cycle fatigue, SAC305 on current designs and
SAC387 on some legacy designs, but in the case of some products targeted hand-held mobile or other
specialized, targeted applications other alloys have been used (with drop, impact and shock resistance, for
example, in mind as the primary concerns).
Board Level Reliability Primer for Embedded Processors
Copyright © 2015, Texas Instruments Incorporated
SPRABY2 – March 2015
Submit Documentation Feedback
Modeling Approach
Modeling Approach
With materials and design selected, the daisy chain test vehicles manufactured, and BLR test data, the
focus then turns to reliability modeling. Typically, the 2-P (two-parameter) Weibull distribution is used for
lifetime modeling of the BLR test data. The Weibull distribution is often associated with characterizing the
“weakest links” in a “system”. This is notionally the case for solder joint fatigue failures. Mechanical Finite
Element modeling is often undertaken to identify relative strain energy density across the array of solder
ball. The solder balls with the highest strain energy densities are those that (statistically) are expected to
fail first, in other words, the “weakest links”. Normally, about 30-50 component samples are tested and the
testing continues until at least about 2/3 of the units fail (a fail being defined as a pre-requisite percentage
increase in resistance). Early failures are typically due to board manufacturing issues, such as non-wet
solder joints. Failure analysis is regularly performed to confirm these cases. Units failing due to
manufacturing (defect) issues are excluded (censored) from the Weibull model (see Figure 1), the purpose
of which is to characterize the intrinsic fatigue lifetime of the solder joints (usually the BGA to package, or
second-level interface). In cross-sectional terms, this is the location of the highest strain energy density
(particularly at the corners). The fatigue crack propagates across the neck of the solder ball until sufficient
resistance change triggers a failure condition on the monitoring equipment. Note that while the examples
of modeling shown in this document are based on Temperature Cycle testing, mechanical shock and drop
or bend data are plotted by the same tools and techniques.
Figure 1. Representative Optical Micrograph Image of Intrinsic Solder Joint Fatigue Failure
The 2-P Weibull model consists of a Slope parameter and a Scale parameter. Unfortunately, authors use
different terms to represent these parameters in various publications, so the symbols used in a particular
text to identify Slope and Scale must be identified case by case. In Equation 1, F is the Fail Fraction
(Cumulative Distribution Function - CDF, or unreliability), R is the Reliability function (fraction surviving),
Eta is the Scale Parameter (also known as characteristic life), Beta is the shape parameter, and AF is the
acceleration factor (accelerated test to use conditions). Note that “t” (time) is transposable in the BLR
context with “number of cycles” (there is a time equivalent for cycles and vice versa).
SPRABY2 – March 2015
Submit Documentation Feedback
Board Level Reliability Primer for Embedded Processors
Copyright © 2015, Texas Instruments Incorporated
Modeling Approach
Weibull 2-P Fail Fraction (CDF) With Acceleration Factor
æ t ö
F (t ) = 1 - R = 1 - e è AF × h ø
There are two primary methods for plotting the Failure Fraction vs. Time distribution (a process known as
“point estimation”): Maximum Likelihood Estimation (MLE) and Rank Regression. For typical BLR data,
where the majority of the sample has known precise times (cycles) to failure and the majority of the units
(~2/3 or more of the sample), the MLE method is generally recommended. The details are beyond the
scope of this application report. For more information, see Tobias and Trindade, “Applied Reliability” (3rd
Edition), CRC Press, 2012 [4].
Note that while there are available methods to plot reliability graphs “by hand” (without aid of computer
software), it is generally preferable to use computer programs dedicated to the task. Many choices are
available, including dedicated reliability engineering packages (Reliasoft Weibull++ or ALTA) as well as
more general statistical analysis packages with modules targeted to reliability analysis (SAS JMP). These
programs typically offer advanced features such as confidence bound estimates and multiple methods of
point estimation. The acceleration factor for solder joint fatigue, the focal failure mechanism of BLR
temperature cycle test, is described by the Modified Coffin-Manson, also known as Norris-Landzberg,
equation.Section 4.2 is the general AF relationship. “Acc” and “Field” refer to accelerated test and Field
(application) conditions, respectively. T is in degrees °C (or K), with ΔT referring to the difference of
maximum and minimum temperatures for the cycle. ν is the cyclical frequency of the temperature cycle
(cycles/time). Ea is the temperature activation energy and “k” is Boltzmann’s Constant. For eutectic Sn/Pb
solder, the parameter values are well established as m=1/3, n=1.9 and Ea/k = 1414 (for example,
Vaduseven and Fan, “An Accelerated Model for Lead-Free (SAC) Solder Joint Reliability under Thermal
Cycling”, IEEE ETC, 2008). The reported parametric values on Pb-free solder can vary substantially
according to the alloy. For SAC (SnAgCu) alloys in particular, N. Pan et al. have reported m=0.136,
n=2.65 and Ea/k = 2185 (“An Acceleration Model for Sn-Ag-Cu Solder Joint Reliability under Various
Thermal Cycle Conditions”, Proc. SMTA, 2005, pp. 876-883) [3]
Norris-Landzberg Acceleration Factor Equation
æ DTAcc ö æ nField
AF = ç
÷ ç
è Field ø è n Acc
éE æ
-m ê a ç
k è TMax - Field TMax - Acc ø ûú
Note that a useful source for N-L parameters for non-hermetic packages for representative end-equipment
classes is JEDEC document JESD47 (see Annex A for the most current revision I as of July 2014) [1]. For
more information, see the JEDEC web site.
Equation 2 is a representative Weibull 2-P plot of 0/100C BLR Temp Cycle data a Pb-free BGA package
generated using specialized reliability software (Reliasoft Weibull++).
NOTE: The N-L / Modified Coffin Manson acceleration factor has not been applied to the data in
Figure 2.
The Maximum likelihood method is used for point estimation. The blue line is the maximum likelihood fit
for the data. The red lines represent 90% confidence bounds on reliability versus cycles (in the MLE case,
the confidence bounds are calculated using the likelihood ratio method). It is also possible to generate
confidence bounds for time (or cycles) instead of or in addition to reliability. At approximately the mean of
the data, there is typically little difference between the two approaches. The further in time from the mean
of the data in either direction, however, the more difference is observed, and in either case the confidence
bounds widen in relative terms. The choice of the method depends on context and preference. As in the
in-situ BLR T/C case, the precise number of cycles to failure is known for a given unit, the reliability
bounds were chosen.
Board Level Reliability Primer for Embedded Processors
Copyright © 2015, Texas Instruments Incorporated
SPRABY2 – March 2015
Submit Documentation Feedback
Modeling Approach
Figure 2. Typical Weibull 2-P Plot for Board Level Reliability Temp Cycle Data
Modeling software can also be used to compare parameters across datasets and differences in the joint
ranges of parameters according to confidence bound limits. Figure 3 is known as a “Contour Plot”. The
two “ellipses” on the left of the plot represent data generated for two different vendors of package
substrates, and the two ovals on plots for a third vendor. The red and blue lines (on the right) represent
different levels on confidence bounds for the same dataset. The interpretation of the contour plot is that
the line represents the boundary of equal probability for the combination of the two parameters (in this
case scale/Eta and shape/Beta). For instance, for a 90% confidence level contour, if the process of data
collection were repeated an infinite number of times, 90% of the contours generated for the datasets
should contain the true values of the parameters within the areas of the contour. The higher the
percentage of the confidence bound for a given dataset, the greater the perimeter of the line as well as the
area contained within the perimeter of the line. Likewise, a smaller confidence bound contour will be
contained (as a subset) within a larger confidence bound contour.
Finally, some of the most advanced reliability modeling software is capable of simultaneously solving for
maximum likelihood reliability model parameters and acceleration model parameters for multiple datasets
(assuming linear acceleration). For example, suppose the reliability of a new solder alloy or package
technology was undergoing reliability characterization. Multiple datasets would be generated at different
temperature cycle conditions. A kinetic (acceleration) model would then be assumed, for instance Modified
Coffin-Manson in the case of solder joint fatigue. As long as the data generated all are represented by the
same failure mechanism, the best joint fit for the reliability and kinetic parameters would be generated
along with confidence bounds for the reliability estimates for any given application (use) condition. The
caveat on extrapolating to a use condition is that the physics of failure at the use condition and
accelerated test conditions are all the same.
SPRABY2 – March 2015
Submit Documentation Feedback
Board Level Reliability Primer for Embedded Processors
Copyright © 2015, Texas Instruments Incorporated
Figure 3. Weibull 2-P Contour Plots for Shape (Beta) and Scale (Eta) Parameters
1. JEDEC JESD47: Stress-Test-Driven Qualification of Integrated Circuits: www.jedec.org
2. IPC-9701: Performance Test Methods and Qualification Requirements for Surface Mount Solder
Attachments: www.ipc.org
3. Pan et al., “An Acceleration Model for Sn-Ag-Cu Solder Joint Reliability Under Various Thermal Cycle
Conditions”, Proc. SMTA, 2005, pp. 876-883.
4. Tobias and Trindade, “Applied Reliability” (3rd Edition), CRC Press, 2012, pp 248-255.
Board Level Reliability Primer for Embedded Processors
Copyright © 2015, Texas Instruments Incorporated
SPRABY2 – March 2015
Submit Documentation Feedback
Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other
changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest
issue. Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and
complete. All semiconductor products (also referred to herein as “components”) are sold subject to TI’s terms and conditions of sale
supplied at the time of order acknowledgment.
TI warrants performance of its components to the specifications applicable at the time of sale, in accordance with the warranty in TI’s terms
and conditions of sale of semiconductor products. Testing and other quality control techniques are used to the extent TI deems necessary
to support this warranty. Except where mandated by applicable law, testing of all parameters of each component is not necessarily
TI assumes no liability for applications assistance or the design of Buyers’ products. Buyers are responsible for their products and
applications using TI components. To minimize the risks associated with Buyers’ products and applications, Buyers should provide
adequate design and operating safeguards.
TI does not warrant or represent that any license, either express or implied, is granted under any patent right, copyright, mask work right, or
other intellectual property right relating to any combination, machine, or process in which TI components or services are used. Information
published by TI regarding third-party products or services does not constitute a license to use such products or services or a warranty or
endorsement thereof. Use of such information may require a license from a third party under the patents or other intellectual property of the
third party, or a license from TI under the patents or other intellectual property of TI.
Reproduction of significant portions of TI information in TI data books or data sheets is permissible only if reproduction is without alteration
and is accompanied by all associated warranties, conditions, limitations, and notices. TI is not responsible or liable for such altered
documentation. Information of third parties may be subject to additional restrictions.
Resale of TI components or services with statements different from or beyond the parameters stated by TI for that component or service
voids all express and any implied warranties for the associated TI component or service and is an unfair and deceptive business practice.
TI is not responsible or liable for any such statements.
Buyer acknowledges and agrees that it is solely responsible for compliance with all legal, regulatory and safety-related requirements
concerning its products, and any use of TI components in its applications, notwithstanding any applications-related information or support
that may be provided by TI. Buyer represents and agrees that it has all the necessary expertise to create and implement safeguards which
anticipate dangerous consequences of failures, monitor failures and their consequences, lessen the likelihood of failures that might cause
harm and take appropriate remedial actions. Buyer will fully indemnify TI and its representatives against any damages arising out of the use
of any TI components in safety-critical applications.
In some cases, TI components may be promoted specifically to facilitate safety-related applications. With such components, TI’s goal is to
help enable customers to design and create their own end-product solutions that meet applicable functional safety standards and
requirements. Nonetheless, such components are subject to these terms.
No TI components are authorized for use in FDA Class III (or similar life-critical medical equipment) unless authorized officers of the parties
have executed a special agreement specifically governing such use.
Only those TI components which TI has specifically designated as military grade or “enhanced plastic” are designed and intended for use in
military/aerospace applications or environments. Buyer acknowledges and agrees that any military or aerospace use of TI components
which have not been so designated is solely at the Buyer's risk, and that Buyer is solely responsible for compliance with all legal and
regulatory requirements in connection with such use.
TI has specifically designated certain components as meeting ISO/TS16949 requirements, mainly for automotive use. In any case of use of
non-designated products, TI will not be responsible for any failure to meet ISO/TS16949.
Automotive and Transportation
Communications and Telecom
Data Converters
Computers and Peripherals
DLP® Products
Consumer Electronics
Energy and Lighting
Clocks and Timers
Power Mgmt
Space, Avionics and Defense
Video and Imaging
OMAP Applications Processors
TI E2E Community
Wireless Connectivity
Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265
Copyright © 2015, Texas Instruments Incorporated
Was this manual useful for you? yes no
Thank you for your participation!

* Your assessment is very important for improving the work of artificial intelligence, which forms the content of this project

Download PDF