Texas Instruments | to fix Perf Issues Using QoS Knobs for DRA74x, DRA75x, TDA2x & TD3x Device | Application notes | Texas Instruments to fix Perf Issues Using QoS Knobs for DRA74x, DRA75x, TDA2x & TD3x Device Application notes

Texas Instruments to fix Perf Issues Using QoS Knobs for DRA74x, DRA75x, TDA2x & TD3x Device Application notes
Application Report
SPRABX0 – November 2014
Root Causing Performance Failures: A Guide to Fix
Performance Issues Using QoS Knobs for the DRA74x,
DRA75x, TDA2x and TDA3x Family of Devices
Prashant Karandikar, Rahul Gulati, Piyali Goswami, Prithvi Shankar Y.A., Vasant Easwaran, Chaitanya Ghone,
Mihir Mody, Vinay Amancha
ABSTRACT
This application report provides a methodology through which performance issues can be identified and
fixed in systems using DRA74x, DRA75x, TDA2x and TDA3x family of devices.
1
2
3
4
5
Contents
Introduction ................................................................................................................... 1
Observability .................................................................................................................. 2
Overview of QoS Mechanisms ............................................................................................. 3
Case Studies ................................................................................................................. 4
Refeences ................................................................................................................... 11
List of Figures
1
1
High Level Summary of QoS Mechanisms in DRA74x/DRA75x/TDA2x/TDA3x Family of Devices .............. 3
2
Display Bandwidth Profile for a Video Pipe @480p in DRA74x/DRA75x/TDA2x/TDA3x Family of Devices .... 4
3
Display Bandwidth Profile for Concurrent Display Pipelines (4 in this case – 2 video pipelines @ 720p
and 1 video + graphics pipeline @ 480p) in DRA74x/DRA75x/TDA2x Family of Devices ......................... 4
4
Display Subsystem Profile for a Single Display Pipeline With Competing External Memory Traffic From
BB2D for DRA74x/DRA75x/TDA2x/TDA3x Family of Devices ........................................................ 5
5
Effect of Enabling Display Subsystem Dynamic Priority Escalation for DRA74x/DRA75x Family of Devices... 6
6
BB2D Bandwidth Profile With Bandwidth Limiter Enabled for DRA74x/DRA75x Family of Devices ............. 6
7
Concurrent Bandwidth Profile When no Underflow is Observed in Display Subsystem for
DRA74x/DRA75x Family of Devices ...................................................................................... 7
8
IVA Subsystem Bandwidth Profile for 1080p Decode Concurrent With DSP EDMA and System Level
EDMA traffic .................................................................................................................. 8
9
IVA Subsystem Bandwidth Profile for 1080p Decode Concurrent With DSP EDMA and System Level
EDMA Traffic and With IVA Subsystem Bandwidth Regulator Enabled .............................................. 9
10
Impact of Bandwidth Regulator on DSP MDMA Latency ............................................................. 10
11
Write Latency With Dynamic Memory Manager Priority Extension Generator Enabled/Disabled ............... 11
Introduction
Root causing performance failures due to concurrent use case scenarios in a system-on-chip (SoC)
requires collaboration between hardware and software engineers. Typically, system level observability is
required in order to understand any performance issues that may arise due to concurrent traffic scenarios.
Having such an observability capability in the SoC eases identification of root causes related to system
level performance issues. Advanced SoC family of devices like DRA74x, DRA75x, TDA2x and TDA3x
provide several quality-of-service (QoS) knobs that aid to observe and control system resources in the
SoC to assure the needed performance for a use case scenario.
Arteris is a registered trademark of Arteris, Inc.
All other trademarks are the property of their respective owners.
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Observability
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This document covers the issues and solutions related to following different concurrent use case scenarios
for DRA74x, DRA75x, TDA2x and TDA3x family of devices:
• Real-time display subsystem (DSS) underflow
• Pseudo real-time video subsystem performance (fps)
• Pseudo real-time processor subsystem performance
• External memory access latency
NOTE: The level 3 (L3) interconnect is an instantiation of the Network On Chip (NoC) interconnect
from Arteris®, Inc.
All materials and trademarks are used under license from Arteris, Inc. For additional
information, see the Arteris reference manuals, or contact Arteris, Inc.
2
Observability
DRA74x, DRA75x, TDA2x and TDA3x family of SoCs provide observability of performance parameters
like bandwidth and latency by embedding statistics collectors within the SoC. Data from the statistics
collector can be collected using the system trace subsystem (STM) or using an unused CPU in the
system.
The following is a list of typical issues seen while using system trace (STM):
• Lack of availability of the STM debugger connectivity in production and customer boards.
• Fine grained observability requirements in order to identify performance issues. Typically, observability
is required at finer steps of 100 µs, whereas, the basic input/output system (BIOS) or high-level
operating system (HLOS) tasks are scheduled at 2-3 ms. Hence, using BIOS or HLOS-based data
collection may not be as meaningful as required. A particular IP may send high priority bandwidth burst
for 500 µs that gets averaged out while measuring in an HLOS using operating system task
scheduling, which would be of order of 1 ms to 10 ms (depending on HLOS in use).
Considering the above mentioned limitations, the following setup is recommended in boards where the
STM debugger connectivity is not possible:
• Availability of an unused CPU core with access to statistic collector registers within L3 interconnect
• A timer with 100 µs interrupt capability
• A debug console universal asynchronous receiver/transmitter (UART)
• Availability of 1KB-2KB on-chip RAM usage for non-intrusive instrumentation code
For guidelines on how to configure L3 statistics collectors, timers and debug console, see the starterware
APIs. For more information on starterware APIs, contact your TI sales representative.
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Overview of QoS Mechanisms
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3
Overview of QoS Mechanisms
QoS overview
MFlag/MReqPrio Generation
• IP driven
• Control Module
Arbitration Based on
• Bandwidth Regulator (BR)
• Bandwidth Limiter (BL)
• MFlag
Arbitration Based on Emergency
PEG Priority Generation
Arbitration Based on
• CoS
• Emergency
• EMIF algorithm
IP
IP
IP
MPU
Interconnect
DMM
EMIF
EMIF
Figure 1. High Level Summary of QoS Mechanisms in DRA74x/DRA75x/TDA2x/TDA3x Family of Devices
For detailed information regarding QoS mechanisms, see the device-specific data sheets or the relevant
DRA74x/DRA75x/TDA2x/TDA3x QoS application reports.
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Case Studies
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4
Case Studies
4.1
Display Underflow
In this case study, it is observed that the display subsystem exhibits underflow when high bandwidth traffic
from other initiators competes with the display subsystem traffic for accessing the external memory.
4.1.1
Observability
A single DSS pipe configured for 480P ARGB display requires an average bandwidth of approximately 83
MB/s (720*480*4Bytes/Pixel*60fps) during frame time. Considering the blanking periods, the bandwidth
requirement during active period is higher than 83 MB/s.
Figure 2 shows the display subsystem bandwidth profile for a single pipe without any competing external
memory traffic.
DSS Single VID-Single VENC 720x480 70 fps RGB
200
BW (MBps)
150
100
50
28.1
29.1
30.1
31.1
32.1
33.1
34.1
35.1
36.1
37.1
38.1
39.1
40.1
41.1
42.1
43.1
44.1
45.1
46.1
47.1
48.1
49.1
50.1
51.1
52.1
53.1
54.1
55.1
56.1
57.1
58.1
0
Time (ms)
Figure 2. Display Bandwidth Profile for a Video Pipe @480p in DRA74x/DRA75x/TDA2x/TDA3x Family of
Devices
Figure 3 shows the display subsystem bandwidth profile for four concurrent display pipes without any
competing external memory traffic.
2 VID (720p@70fps) + 1 VID & GFX (480p@70 fps)
1200
BW (MBps)
1000
800
600
400
200
0.1
1.7
3.3
4.9
6.5
8.1
9.7
11.3
12.9
14.5
16.1
17.7
19.3
20.9
22.5
24.1
25.7
27.3
28.9
30.5
32.1
33.7
35.3
36.9
38.5
40.1
41.7
43.3
44.9
46.5
48.1
0
Time (ms)
Figure 3. Display Bandwidth Profile for Concurrent Display Pipelines (4 in this case – 2 video pipelines @
720p and 1 video + graphics pipeline @ 480p) in DRA74x/DRA75x/TDA2x Family of Devices
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4.1.2
Issue: Display Subsystem not Meeting Average Bandwidth During Active Time
When concurrent traffic from BB2D is enabled, display subsystem underflow is observed.
Figure 4 depicts the bandwidth profile for display subsystem with a single pipeline and competing external
memory traffic from BB2D.
DSS Underflows with VID 2 1280x720 60 fps +
BB2D 1280x720 3 frame overlay
3500
BW (MBps)
3000
2500
2000
1500
1000
500
0
1.6
3.2
4.8
6.4
8
9.6
11.2
12.8
14.4
16
17.6
19.2
20.8
22.4
24
25.6
27.2
28.8
30.4
32
33.6
35.2
36.8
38.4
40
41.6
43.2
44.8
46.4
48
49.6
0
Time (ms)
BB2D_P1
BB2D_P2
DSS
Figure 4. Display Subsystem Profile for a Single Display Pipeline With Competing External Memory
Traffic From BB2D for DRA74x/DRA75x/TDA2x/TDA3x Family of Devices
Since BB2D uses a memory-to-memory processing, maximum possible traffic from BB2D is injected onto
the L3 interconnect. Considering overall bandwidth available in the system, BB2D gets more than its fair
share in the system.
4.1.3
Possible Solutions
There are two possible solutions to tackle this problem.
4.1.3.1
Solution 1
DSS has an in-built dynamic priority escalation and de-escalation mechanism, MFLAG, which works on
FIFO levels. This mechanism can be enabled by making the pipelines that exhibit underflow issues as
high priority pipelines and setting the low and high threshold at 50% and 75%, respectively. Note that the
graphics pipeline within the display subsystem has a 16 KB FIFO and the three video pipelines viz.
VID1/2/3 have a 32 KB FIFO each.
Use the display subsystem starterware APIs to configure the dynamic priority escalation and de-escalation
as mentioned above.
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Figure 5 depicts the share of BB2D bandwidth dropping when the dynamic priority escalation for display
subsystem has been enabled.
No DSS Underflow with VID 2 High priority and
Mflag set
3500
3000
BW (Mbps)
2500
2000
1500
1000
500
0
1.6
3.2
4.8
6.4
8
9.6
11.2
12.8
14.4
16
17.6
19.2
20.8
22.4
24
25.6
27.2
28.8
30.4
32
33.6
35.2
36.8
38.4
40
41.6
43.2
44.8
46.4
48
49.6
0
Time (ms)
BB2D_P1
BB2D_P2
DSS
Figure 5. Effect of Enabling Display Subsystem Dynamic Priority Escalation for DRA74x/DRA75x Family
of Devices
4.1.3.2
Solution 2
Since the BB2D initiator consumes more than the required bandwidth to complete the task, it finishes its
task ahead of the required time, causing the display subsystem to miss its real-time deadline. The BB2D
initiator bandwidth can be controlled by using a QoS mechanism known as Bandwidth Limiter, an L3
interconnect component.
Use of Bandwidth Limiter for BB2D reduces its average bandwidth consumption, at the expense of
increase in its task duration. However, the Bandwidth Limiter is configured such that the BB2D initiator still
completes its task with sufficient margin with respect to its deadline.
800
600
400
200
0
4.8
5.7
6.6
7.5
8.4
9.3
10.2
11.1
12
12.9
13.8
14.7
15.6
16.5
17.4
18.3
19.2
20.1
21
21.9
22.8
23.7
24.6
25.5
26.4
27.3
28.2
29.1
30
30.9
31.8
32.7
BW (MBps)
Figure 6 depicts the bandwidth profile for BB2D with the bandwidth limiter enabled.
Time (ms)
BB2D P1 with Limiter BW (MB/s)
BB2D P2 with Limiter BW (MB/s)
Figure 6. BB2D Bandwidth Profile With Bandwidth Limiter Enabled for DRA74x/DRA75x Family of
Devices
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Figure 7 depicts the concurrent bandwidth profile for the display subsystem and BB2D with the bandwidth
limiter enabled for BB2D.
No DSS Underflow with BW limiter on BB2D
1000
BW (MBps)
800
600
400
200
0
1.6
3.2
4.8
6.4
8
9.6
11.2
12.8
14.4
16
17.6
19.2
20.8
22.4
24
25.6
27.2
28.8
30.4
32
33.6
35.2
36.8
38.4
40
41.6
43.2
44.8
46.4
48
49.6
0
Time (ms)
BB2D_P1
BB2D_P2
DSS
Figure 7. Concurrent Bandwidth Profile When no Underflow is Observed in Display Subsystem for
DRA74x/DRA75x Family of Devices
4.2
Pseudo Real-Time Video Subsystem Performance (fps)
IVA subsystem, an engine for video compression and decompression, shows varied amounts of traffic for
I/P/B kind of frames. The subsystem performance is based on both compute and data transfer time.
Typically, in a concurrent traffic scenario, the IVA subsystem performance could degrade because of
delays in data transfer to the subsystem. Since the IVA subsystem has a limited amount of buffering
capability, it is inherently immune to certain latency expected in data transfers. In a concurrent scenario, it
is observed that the IVA subsystem does not get the required average data transfer (bandwidth), causing
degradation in the required fps (frames per second).
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4.2.1
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Issue/Observability
Figure 8 depicts the bandwidth profile for IVA subsystem traffic concurrent with DSP EDMA traffic and
System EDMA traffic. The highlighted portion indicates the degradation seen by the IVA subsystem due to
additional traffic. Specifically, the B-Frame takes 34.466 ms for its completion (instead of 33.33 ms)
leading to an fps drop from 30 fps to 29 fps.
IVA Sub-system: 1080p Decode Performance with
Competing Traffic
2500
BW (MBps)
2000
1500
1000
500
0
3.936
7.872
11.808
15.744
19.68
23.616
27.552
31.488
35.424
39.36
43.296
47.232
51.168
55.104
59.04
62.976
66.912
70.848
74.784
78.72
82.656
86.592
90.528
94.464
98.4
102.336
106.272
110.208
114.144
118.08
122.016
0
Time (ms)
B frame exceeding 33 ms
IVAHD with Competing Traffic
DSP EDMA
System EDMA RD Only
Figure 8. IVA Subsystem Bandwidth Profile for 1080p Decode Concurrent With DSP EDMA and System
Level EDMA traffic
4.2.2
Possible Solution: Usage of QoS Knobs to Resolve the Degradation Seen by IVA Subsystem
Bandwidth Regulator dedicated for IVA subsystem within the L3 interconnect provides a mechanism to
dynamically modify the priority of IVA subsystem in the SoC. Considering that the IVA subsystem requires
about 1500 MB/s for video decode for B frames, the bandwidth regulator is configured for this
requirement.
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Figure 9 depicts the impact of enabling the IVA subsystem bandwidth regulator. It is evident that the
performance of B-frames in particular is now well within the 33 ms requirement, thereby, enabling the
overall 30 fps requirement for the IVA subsystem.
For guidelines on how to configure IVA subsystem Bandwidth Regulator within L3 interconnect, see the
starterware APIs.
IVA sub-system with 1080p30 and concurrent
traffic: Bandwidth Regulator enabled
2500
BW (MBps)
2000
1500
1000
500
0
3.444
6.888
10.332
13.776
17.22
20.664
24.108
27.552
30.996
34.44
37.884
41.328
44.772
48.216
51.66
55.104
58.548
61.992
65.436
68.88
72.324
75.768
79.212
82.656
86.1
89.544
92.988
96.432
99.876
103.32
106.764
110.208
0
Time (ms)
IVAHD BW Regulated
DSP EDMA
B frame meeting 33 ms
requirement (now takes 18 ms)
System EDMA RD Only
Figure 9. IVA Subsystem Bandwidth Profile for 1080p Decode Concurrent With DSP EDMA and System
Level EDMA Traffic and With IVA Subsystem Bandwidth Regulator Enabled
4.3
Pseudo Real-Time Processor Subsystem Performance
In general, latency of instruction and data fetches has a significant impact on the processor subsystem
performance. Figure 10 demonstrates the impact of enabling the bandwidth regulator on the processor
subsystem latency. DSP1 is the processor subsystem under consideration in this case. The test case
comprises of running a hand-crafted optimized memcopy routine on the C66x core within the DSP
subsystem available on DRA74x, DRA75x, TDA2x and TDA3x family of devices. Such a test would lead to
an average bandwidth of 2500 MBytes per second in a standalone condition. Due to the addition of
competing EDMA traffic from two EDMA transfer controllers within the DSP2 subsystem, it is observed
that the DSP1 subsystem bandwidth drops to 981 MBytes per second. It is possible to achieve the desired
bandwidth through appropriate configuration of the DSP1 MDMA bandwidth regulator available within the
L3 interconnect. The bandwidth regulator essentially reduces the latency of the DSP1 MDMA port for
instruction and data fetches. It can be observed from Figure 10 that the latency for DSP1 MDMA port
improves from ~180 cycles/transaction to ~110 cycles/transaction after configuring the DSP1 MDMA
bandwidth regulator.
NOTE: The system integrator needs to keep in mind the bandwidth and latency requirements for all
the initiators involved in the concurrent use case scenario in order to determine the
appropriate configuration values for various available QoS elements, like bandwidth
regulators, bandwidth limiters, and so forth. For the various QoS options available on your
device, see Quality of Service (QoS) Knobs for DRA74x, DRA75x & TDA2x Family of
Devices (SPRABX1).
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Impact of Bandwidth Regulator on DSP MDMA
Latency
Latency (L3 Cycles/Transaction)
250
200
150
100
50
0
DSP1 MDMA Latency with Competing EDMA Traffic
DSP1 MDMA Cycles/Transaction with Competing EDMA traffic with BR
DSP1 MDMA Stanalone
Figure 10. Impact of Bandwidth Regulator on DSP MDMA Latency
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4.4
Transactions Stuck in Memory Subsystem for an Extended Time Duration
The case study chosen here comprises of concurrent traffic from 4 x EDMA TC channels. The traffic
pattern is generated such that three EDMA TC are reading from the external memory and the fourth
EDMA TC is writing to the external memory.
Figure 11 depicts the impact of modifying the initiator priority using the priority extension generator (PEG)
feature of the dynamic memory manager (DMM) inside of the memory subsystem on latency observed by
the EDMA TC channel performing write transactions. The DMM is composed of a block aimed at
generating software-programmable initiator-indexed priority extensions for any of the PEG connID groups.
For details of the DMM PEG configuration registers, see the device-specific technical reference manual.
Figure 11. Write Latency With Dynamic Memory Manager Priority Extension Generator Enabled/Disabled
5
Refeences
•
Quality of Service (QoS) Knobs for DRA74x, DRA75x & TDA2x Family of Devices (SPRABX1)
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