Texas Instruments | Implementing DDR2/mDDR PCB Layout on the TMS320DM335 DMSoC (Rev. D) | Application notes | Texas Instruments Implementing DDR2/mDDR PCB Layout on the TMS320DM335 DMSoC (Rev. D) Application notes

Texas Instruments Implementing DDR2/mDDR PCB Layout on the TMS320DM335 DMSoC (Rev. D) Application notes
Application Report
SPRAAL2D – November 2009
Implementing DDR2/mDDR PCB Layout on the
TMS320DM335 DMSoC
DSPS Applications
...........................................................................................................................
ABSTRACT
This application report contains implementation instructions for the DDR2/mDDR interface contained on
the TMS320DM335 Digital Media System-on-Chip (DMSoC) device. The approach to specifying interface
timing for the DDR2/mDDR interface is quite different than on previous devices.
The previous approach specified device timing in terms of data sheet specifications and simulation
models. The system designer was required to obtain compatible memory devices, as well as the
device-specific data sheets and simulation models. This information would then be used to design the
printed circuit board (PCB) using high-speed simulation to close system timing.
For the DM335 DDR2/mDDR interface, the approach is to specify compatible DDR2/mDDR devices and
provide the PCB routing rule solution directly. TI has performed the simulation and system design work to
ensure DDR2/mDDR interface timings are met. This document describes the required routing rules.
The DM335 EVM provides an example of a PCB layout following these routing rules that passes FCC EMI
requirements. You can copy the DDR2/mDDR portion of this layout directly, but the intent is to allow
enough flexibility in the routing rules to meet other PCB requirements.
1
2
Contents
TMS320DM335 .............................................................................................................. 2
References ................................................................................................................. 14
List of Figures
1
DM335 DDR2/mDDR Single-Memory High Level Schematic ......................................................... 5
2
DM335 DDR2/mDDR Dual-Memory High Level Schematic ........................................................... 5
3
DM335 and DDR2/mDDR Device Placement ........................................................................... 6
4
DDR2/mDDR Keepout Region ............................................................................................ 7
5
VREF Routing and Topology
6
7
8
............................................................................................
CK and ADDR_CTRL Routing and Topology..........................................................................
DQS and DQ Routing and Topology ....................................................................................
DQGATE Routing .........................................................................................................
11
11
12
13
List of Tables
1
Compatible JEDEC DDR2/mDDR Devices .............................................................................. 2
2
DM335 Minimum PCB Stack Up .......................................................................................... 3
3
PCB Stack Up Specifications .............................................................................................. 6
4
Placement Specifications .................................................................................................. 7
5
Bulk Bypass Capacitors .................................................................................................... 8
6
High-Speed Bypass Capacitors ........................................................................................... 9
7
Clock Net Class Definitions .............................................................................................. 10
8
Signal Net Class Definitions
9
DDR2/mDDR Signal Terminations ...................................................................................... 10
10
CK and ADDR_CTRL Routing Specification
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....................................................................................
DQGATE Routing Specification .........................................................................................
11
DQS and DQ Routing Specification
12
1
TMS320DM335
1.1
DDR2/mDDR Interface
13
14
This section provides the timing specification for the DDR2/mDDR interface as a PCB design and
manufacturing specification. The design rules constrain PCB trace length, PCB trace skew, signal
integrity, cross-talk, and signal timing. These rules, when followed, result in a reliable DDR2/mDDR
memory system without the need for a complex timing closure process. For more information regarding
guidelines for using this DDR2 specification, Understanding TI's PCB Routing Rule-Based DDR2 Timing
Specification (SPRAAV0).
1.1.1
DDR2/mDDR Interface Schematic
Figure 1 shows the DDR2/mDDR interface schematic for a single-memory DDR2/mDDR system. The
dual-memory system shown in Figure 2. Pin numbers for the DM335 can be obtained from the pin
description section of the TMS320DM335 Digital Media System-on-Chip (DMSoC) Data Manual
(SPRS528) and the DDR2/mDDR device pin numbers can be obtained from their device-specific data
sheets.
1.1.2
Compatible JEDEC DDR2/mDDR Devices
Table 1 shows the parameters of the JEDEC DDR2/mDDR devices that are compatible with this interface.
Generally, the DDR2/mDDR interface is compatible with x16 DDR2/mDDR-400 speed grade DDR2/mDDR
devices.
The DM335 also supports JEDEC DDR2/mDDR x8 devices in the dual chip configuration. In this case,
one chip supplies the upper byte and the second chip supplies the lower byte. Addresses and most control
signals are shared just like regular dual chip memory configurations.
Table 1. Compatible JEDEC DDR2/mDDR Devices
No.
(1)
2
Parameter
Min
Max
1
JEDEC DDR2/mDDR Device Speed Grade
2
JEDEC DDR2/mDDR Device Bit Width
x8
x16
3
JEDEC DDR2/mDDR Device Count
1
2
Unit
DDR2/mDDR400
Notes
See Note
(1)
Bits
Devices
Higher DDR2/mDDR speed grades are supported due to inherent JEDEC DDR2/mDDR backwards compatibility.
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1.1.3
PCB Stackup
The minimum stackup required for routing the DM335 is a six layer stack as shown in Table 2. Additional
layers may be added to the PCB stack up to accommodate other circuitry or to reduce the size of the PCB
footprint.
Table 2. DM335 Minimum PCB Stack Up
Layer
Type
Description
1
Signal
Top Routing Mostly Horizontal
2
Plane
Ground
3
Plane
Power
4
Signal
Internal Routing
5
Plane
Ground
6
Signal
Bottom Routing Mostly Vertical
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Complete stack up specifications are provided in Table 3.
DMSoC
DDR2/mDDR
ODT
DDR_DQ00
T
DQ0
DDR_DQ07
T
DQ7
DDR_DQM0
DDR_DQS0
T
LDM
LDQS
DDR_DQ08
T
T
LDQS
DQ8
NC
DDR_DQ15
T
DQ15
DDR_DQM1
DDR_DQS1
T
UDM
UDQS
DDR_BA0
T
BA0
DDR_BA2
T
BA2
DDR_A00
T
A0
DDR_A13
DDR_CS
DDR_CAS
DDR_RAS
DDR_WE
DDR_CKE
DDR_CLK
DDR_CLK
T
A13
CS
CAS
RAS
WE
CKE
CK
CK
DDR_DQGATE0
DDR_DQGATE1
T
T
UDQS
NC
(C)
T
T
T
T
T
T
T
50 Ω .5%
DDR_ZN
(A)
Vio 1.8
VREF
(D)
0.1 μF
1 K Ω 1%
DDR_VREF
(D)
VREF
(B)
0.1 μF
T
(B)
0.1 μF
(B)
0.1 μF
0.1 μF
(D)
1 K Ω 1%
Terminator, if desired. See terminator comments.
A
Vio1.8 is the power supply for the DDR2/mDDR memories and the DM335 DDR2/mDDR interface.
B
One of these capacitors can be eliminated if the divider and its capacitors are placed near a device VREF pin. In the
case of mDDR, these capacitors can be eliminated completely.
C
Connect A13 signals together when present
D
VREF applies in the case of DDR2 memories. For mDDR, the DMSoC DDR_VREF pin still needs to be connected to
the divider circuit.
Figure 1. DM335 DDR2/mDDR Single-Memory High Level Schematic
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DMSoC
ODT
T
DQ0 - DQ7
BA0-BA2
(C)
A0-A13
DDR_DQM0
DDR_DQS0
T
DM
DQS
DQS
T
NC
Lower Byte
DDR2/mDDR
DDR_DQ00-07
CK
CK
CS
CAS
RAS
WE
CKE
(D)
VREF
BA0-BA2
(C)
A0-A13
T
T
DDR_CLK
DDR_CLK
DDR_CS
DDR_CAS
DDR_RAS
DDR_WE
DDR_CKE
T
DDR_DQM1
DDR_DQS1
T
DDR_DQ08-15
T
DDR_DQGATE0
DDR_DQGATE1
T
CK
CK
CS
CAS
RAS
WE
CKE
T
T
T
T
T
T
DM
DQS
DQS
DQ0 - DQ7
T
NC
DDR_ZN
50 Ω .5%
Upper Byte
DDR2/mDDR
DDR_BA0-BA2
DDR_A00-A13
(A)
Vio 1.8
ODT
(D)
VREF
0.1 μF
1 K Ω 1%
DDR_VREF
(D)
(D)
VREF
(B)
0.1 μF
T
(B)
0.1 μF
(B)
0.1 μF
0.1 μF
1 K Ω 1%
Terminator, if desired. See terminator comments.
A
Vio1.8 is the power supply for the DDR2/mDDR memories and the DM335 DDR2/mDDR interface.
B
One of these capacitors can be eliminated if the divider and its capacitors are placed near a device VREF pin. In the
case of mDDR, these capacitors can be eliminated completely.
C
Connect A13 signals together when present
D
VREF applies in the case of DDR2 memories. For mDDR, the DMSoC DDR_VREF pin still needs to be connected to
the divider circuit.
Figure 2. DM335 DDR2/mDDR Dual-Memory High Level Schematic
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Table 3. PCB Stack Up Specifications
No.
(1)
(2)
(3)
1.1.4
Parameter
Min
Typ
Max
Unit
Notes
1
PCB Routing/Plane Layers
6
2
Signal Routing Layers
3
3
Full ground layers under DDR2/mDDR routing Region
2
4
Number of ground plane cuts allowed within DDR routing region
5
Number of ground reference planes required for each DDR2/mDDR
routing layer
6
Number of layers between DDR2/mDDR routing layer and reference
ground plane
7
PCB Routing Feature Size
4
Mils
8
PCB Trace Width w
4
Mils
8
PCB BGA escape via pad size
18
Mils
9
PCB BGA escape via hole size
8
Mils
10
DMSoC Device BGA pad size
See Note
(1)
11
DDR2/mDDR Device BGA pad size
See Note
(2)
12
Single Ended Impedance, Zo
13
Impedance Control
See Note
(3)
0
1
0
50
Z-5
Z
75
Ω
Z+5
Ω
Please refer to the Flip Chip Ball Grid Array Package Reference Guide (SPRU811) for DMSoC device BGA pad size.
Please refer to the DDR2/mDDR device manufacturer documentation for the DDR2/mDDR device BGA pad size.
Z is the nominal singled ended impedance selected for the PCB specified by item 12.
Placement
Figure 2 shows the required placement for the DM335 device as well as the DDR2/mDDR devices. The
dimensions for Figure 3 are defined in Table 4. The placement does not restrict the side of the PCB that
the devices are mounted on. The ultimate purpose of the placement is to limit the maximum trace lengths
and allow for proper routing space. For single-memory DDR2/mDDR systems, the second DDR2/mDDR
device is omitted from the placement.
X
Y
OFFSET
Y
DDR2/mDDR
Device
Y
OFFSET
DDR2/mDDR
Controller
A1
DM335
A1
Recommended DDR2/mDDR
Device Orientation
Figure 3. DM335 and DDR2/mDDR Device Placement
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Table 4. Placement Specifications
No.
1
2
3
Parameter
Min
X
Y
Max
Unit
1750
Mils
1280
Y Offset
650
Mils
Mils
Notes
See Notes
(1)
,
See Notes
(1)
(2)
,
(2)
See Notes
(1)
.
(2)
,
(3)
(1)
(2)
(3)
(4)
(5)
1.1.5
4
DDR2/mDDR Keepout Region
5
Clearance from non-DDR2/mDDR signal to DDR2/mDDR Keepout
Region
4
w
See Note
(4)
See Note
(5)
See Figure 1 for dimension definitions.
Measurements from center of DMSoC device to center of DDR2/mDDR device.
For single memory systems it is recommended that Y Offset be as small as possible.
DDR2/mDDR Keepout region to encompass entire DDR2/mDDR routing area
Non-DDR2/mDDR signals allowed within DDR2/mDDR keepout region provided they are separated from DDR2/mDDR routing
layers by a ground plane.
DDR2/mDDR Keep Out Region
The region of the PCB used for the DDR2/mDDR circuitry must be isolated from other signals. The
DDR2/mDDR keep out region is defined for this purpose and is shown in Figure 4. The size of this region
varies with the placement and DDR routing. Additional clearances required for the keep out region are
shown in Table 4.
DDR2/mDDR
Device
DDR2/mDDR
Controller
A1
A1
Region should encompass all DDR2/mDDR circuitry and varies
depending on placement. Non-DDR2/mDDR signals should not be
routed on the DDR signal layers within the DDR2/mDDR keep out
region. Non-DDR2/mDDR signals may be routed in the region
provided they are routed on layers separated from DDR2/mDDR
signal layers by a ground layer. No breaks should be allowed in the
reference ground layers in this region. In addition, the 1.8 V power
plane should cover the entire keep out region.
Figure 4. DDR2/mDDR Keepout Region
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Bulk Bypass Capacitors
Bulk bypass capacitors are required for moderate speed bypassing of the DDR2/mDDR and other
circuitry. Table 5 contains the minimum numbers and capacitance required for the bulk bypass capacitors.
Note that this table only covers the bypass needs of the DMSoC and DDR2/mDDR interfaces. Additional
bulk bypass capacitance may be needed for other circuitry.
Table 5. Bulk Bypass Capacitors
No.
1
Parameter
Min
DVDD18 Bulk Bypass Capacitor Count
3
Max
Unit
Notes
Devices
See Note
(1)
2
DVDD18 Bulk Bypass Total Capacitance
30
μF
3
DDR#1 Bulk Bypass Capacitor Count
1
Devices
See Note
(1)
4
DDR#1 Bulk Bypass Total Capacitance
5
DDR#2 Bulk Bypass Capacitor Count
22
μF
1
Devices
See
Notes (1),
(2)
6
DDR#2 Bulk Bypass Total Capacitance
22
μF
See Note
(2)
(1)
(2)
8
These devices should be placed near the device they are bypassing, but preference should be given to the placement of the
high-speed (HS) bypass caps.
Only used on dual-memory systems
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1.1.7
High-Speed Bypass Capacitors
High-speed (HS) bypass capacitors are critical for proper DDR2/mDDR interface operation. It is
particularly important to minimize the parasitic series inductance of the HS bypass cap,
DMSoC/DDR2/mDDR power, and DMSoC/DDR2/mDDR ground connections. Table 6 contains the
specification for the HS bypass capacitors as well as for the power connections on the PCB.
1.1.8
Net Classes
Table 7 lists the clock net classes for the DDR2/mDDR interface. Table 8 lists the signal net classes, and
associated clock net classes, for the signals in the DDR2/mDDR interface. These net classes are used for
the termination and routing rules that follow.
Table 6. High-Speed Bypass Capacitors
No.
(1)
(2)
(3)
(4)
Parameter
Min
1
HS Bypass Capacitor Package Size
2
Distance from HS bypass capacitor to device being bypassed
3
Number of connection vias for each HS bypass capacitor
2
4
Trace length from bypass capacitor contact to connection via
1
5
Number of connection vias for each DDR2/mDDR device power or ground balls
1
6
Trace length from DDR2/mDDR device power ball to connection via
7
DVDD18 HS Bypass Capacitor Count
10
8
DVDD18 HS Bypass Capacitor Total Capacitance
1.2
9
DDR#1 HS Bypass Capacitor Count
10
DDR#1 HS Bypass Capacitor Total Capacitance
11
DDR#2 HS Bypass Capacitor Count
12
DDR#2 HS Bypass Capacitor Total Capacitance
Max
Unit
0402
10 Mils
250
Mils
Vias
30
0.4
8
0.4
(1)
See Note
(2)
See Note
(3)
See Note
(3)
Mils
Vias
35
8
Notes
See Note
Mils
Devices
μF
Devices
μF
Devices
μF
See Notes
(3) (4)
,
See Note
(4)
LxW, 10 mil units, i.e., a 0402 is a 40x20 mil surface mount capacitor
An additional HS bypass capacitor can share the connection vias only if it is mounted on the opposite side of the board.
These devices should be placed as close as possible to the device being bypassed.
Only used on dual-memory systems
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Table 7. Clock Net Class Definitions
Clock Net Class
CK
DMSoC Pin Names
DDR_CLK/DDR_CLK
DQS0
DDR_DQS0
DQS1
DDR_DQS1
Table 8. Signal Net Class Definitions
Clock Net Class
ADDR_CTRL
DMSoC Pin Names
CK
DDR_BA[2:0], DDR_A[13:0], DDR_CS, DDR_CAS, DDR_RAS, DDR_WE,
DDR_CKE
DQ0
DQS0
DDR_DQ[7:0], DDR_DQM0
DQ1
DQS1
DDR_DQ[15:8], DDR_DQM1
CK, DQS0, DQS1
DDR_DQGATE0, DDR_DQGATE1
DQGATE
1.1.9
Associated Clock Net
Class
DDR2/mDDR Signal Termination
No terminations of any kind are required in order to meet signal integrity and overshoot requirements.
Serial terminators are permitted, if desired, to reduce EMI risk; however, serial terminations are the only
type permitted. Table 9 shows the specifications for the series terminators.
Table 9. DDR2/mDDR Signal Terminations
No.
(1)
(2)
(3)
(4)
10
Parameter
Min
Typ
Max
Unit
Notes
10
Ω
See Note
(1)
22
Zo
Ω
See Notes
(2) (3)
,
(1)
0
22
Zo
Ω
See Notes (1),
(2) (3) (4)
, , ,
0
10
Zo
Ω
See Notes
(2) (3)
,
1
CK Net Class
0
2
ADDR_CTRL Net Class
0
3
Data Byte Net Classes (DQS0-DQS1, DQ0-DQ1)
4
DQGATE Net Class (DQGATE)
(1)
,
,
Only series termination is permitted, parallel or SST specifically disallowed.
Terminator values larger than typical only recommended to address EMI issues.
Termination value should be uniform across net class.
When no termination is used on data lines (0 Ωs), the DDR2/mDDR devices must be programmed to operate in 60% strength
mode.
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1.1.10
VREF Routing
VREF is used as a reference by the input buffers of the DDR2/mDDR memories as well as the DM335’s.
VREF is intended to be ½ the DDR2/mDDR power supply voltage and should be created using a resistive
divider as shown in Figure 1. Other methods of creating VREF are not recommended. Figure 5 shows the
layout guidelines for VREF.
VREF Bypass Capacitor
DDR2/mDDR Device
A1
VREF Nominal Minimum
Trace Width is 20 Mils
DM335
Device
A1
Neck down to minimum in BGA escape
regions is acceptable. Narrowing to
accomodate via congestion for short
distances is also acceptable. Best
performance is obtained if the width
of VREF is maximized.
Figure 5. VREF Routing and Topology
1.1.11
DDR2/mDDR CK and ADDR_CTRL Routing
Figure 6 shows the topology of the routing for the CK and ADDR_CTRL net classes. The route is a
balanced T as it is intended that the length of segments B and C be equal. In addition, the length of A
should be maximized.
T
C
A
DDR2/mDDR
Controller
B
A1
DM335
A1
Figure 6. CK and ADDR_CTRL Routing and Topology
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Table 10. CK and ADDR_CTRL Routing Specification
No
(1)
(2)
(3)
Parameter
Min
Typ
(1)
Max
Unit
Notes
25
Mils
See Note
(1)
25
Mils
See Note
(2)
See Note
(3)
4w
See Note
(2)
3w
See Note
(2)
See Note
(1)
1
Center to center CK-CK spacing
2w
2
CK A to B/A to C Skew Length Mismatch
3
CK B to C Skew Length Mismatch
4
Center to center CK to other DDR2/mDDR trace
spacing
5
CK/ADDR_CTRL nominal trace length
6
ADDR_CTRL to CK Skew Length Mismatch
7
ADDR_CTRL to ADDR_CTRL Skew Length Mismatch
8
Center to center ADDR_CTRL to other DDR2/mDDR
trace spacing
9
Center to center ADDR_CTRL to other ADDR_CTRL
trace spacing
10
ADDR_CTRL A to B/A to C Skew Length Mismatch
100
Mils
11
ADDR_CTRL B to C Skew Length Mismatch
100
Mils
4w
CACLM-50
CACLM
CACLM+50
Mils
100
Mils
100
Mils
Series terminator, if used, should be located closest to DMSoC.
Center to center spacing is allowed to fall to minimum (w) for up to 500 mils of routed length to accommodate BGA escape and
routing congestion.
CACLM is the longest Manhattan distance of the CK and ADDR_CTRL net classes.
Figure 7 shows the topology and routing for the DQS and DQ net classes; the routes are point to point.
Skew matching across bytes is not needed nor recommended.
T
A1
E0
T
DDR2/mDDR
Controller
E1
DM335
T
A1
E2
T
E3
Figure 7. DQS and DQ Routing and Topology
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Table 11. DQS and DQ Routing Specification
No.
Parameter
Min
1
Center to center DQS-DQS spacing
2
DQS E Skew Length Mismatch
3
Center to center DQS to other DDR2/mDDR trace spacing
4
DQS/DQ nominal trace length
(1)
Typ
Max
Unit
Notes
2w
25
Mils
4w
DQLM50
DQL
M
DQLM
+50
Mils
See Note
(2)
See Notes
(1)
,
(3)
5
DQ to DQS Skew Length Mismatch
100
Mils
See Note
(3)
6
DQ to DQ Skew Length Mismatch
100
Mils
See Note
(3)
7
Center to center DQ to other DDR2/mDDR trace spacing
See Notes
(2)
,
(5)
,
4w
(4)
8
Center to Center DQ to other DQ trace spacing
3w
See Notes
(2)
9
(1)
(2)
(3)
(4)
(5)
DQ/DQS E Skew Length Mismatch
100
Mils
See Note
(3)
Series terminator, if used, should be located closest to DDR.
Center to center spacing is allowed to fall to minimum (w) for up to 500 mils of routed length to accommodate BGA escape and
routing congestion.
There is no need and it is not recommended to skew match across data bytes, i.e., from DQS0 and data byte 0 to DQS1 and
data byte 1.
DQ's from other DQS domains are considered other DDR2/mDDR trace.
DQLM is the longest Manhattan distance of each of the DQS and DQ net classes.
A1
FL
Figure 8 shows the routing for the DQGATE net classes. Table 12 contains the routing specification.
DDR2/mDDR
Controller
T
A1
DM335
FH
T
Figure 8. DQGATE Routing
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References
www.ti.com
Table 12. DQGATE Routing Specification
No.
1
Parameter
Min
DQGATE Length F
Typ
Max
Unit
CKB0B1
Notes
See Note
(1)
3
Center to center DQGATE to any other trace spacing
4
DQS/DQ nominal trace length
5
DQGATE Skew
4w
DQLM-50
DQLM
DQLM+50
Mils
100
Mils
See Note
(2)
(1)
(2)
2
References
•
•
•
14
CKB0B1 is the sum of the length of the CK net plus the average length of the DQS0 and DQS1 nets.
Skew from CKB0B1
TMS320DM335 Digital Media System-on-Chip (DMSoC) Data Manual (SPRS528)
Understanding TI's PCB Routing Rule-Based DDR2 Timing Specification (SPRAAV0)
Flip Chip Ball Grid Array Package Reference Guide (SPRU811)
Implementing DDR2/mDDR PCB Layout on the TMS320DM335 DMSoC
Copyright © 2009, Texas Instruments Incorporated
SPRAAL2D – November 2009
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