Texas Instruments | Implementing DDR2 PCB Layout on the TMS320C6455/C6454 (Rev. E) | Application notes | Texas Instruments Implementing DDR2 PCB Layout on the TMS320C6455/C6454 (Rev. E) Application notes

Texas Instruments Implementing DDR2 PCB Layout on the TMS320C6455/C6454 (Rev. E) Application notes
Application Report
SPRAAA7E – July 2008
Implementing DDR2 PCB Layout on the
TMS320C6454/5
Michael Shust and Jeff Cobb ..................................................................... High Speed HW Productization
ABSTRACT
This application report contains implementation instructions for the DDR2 interface
contained on the TMS320C6454/5 digital signal processor (DSP) device. The approach
to specifying interface timing for the DDR2 interface is quite different than on previous
devices.
The previous approach specified device timing in terms of data sheet specifications and
simulation models. The system designer was required to obtain compatible memory
devices, as well as the device-specific data sheets and simulation models. This
information would then be used to design the printed circuit board (PCB) using
high-speed simulation to close system timing.
For the C6454/5 DDR2 interface, the approach is to specify compatible DDR2 devices
and provide the PCB routing rule solution directly. TI has performed the simulation and
system design work to ensure DDR2 interface timings are met. This document
describes the required routing rules.
The C6454/5 EVM provides an example of a PCB layout following these routing rules
that passes FCC EMI requirements. You may copy the DDR2 portion of this layout
directly, but the intent is to allow enough flexibility in the routing rules to meet other
PCB requirements.
1
2
Contents
TMS320C6454/5 .................................................................................... 2
References ......................................................................................... 13
List of Figures
1
2
3
4
5
6
7
8
DM647/8 32-Bit DDR2 High Level Schematic .................................................. 3
DM647/8 16-Bit DDR2 High Level Schematic .................................................. 4
C6454/5 and DDR2 Device Placement .......................................................... 5
DDR2 Keepout Region............................................................................. 6
VREF Routing and Topology .................................................................... 10
CK and ADDR_CTRL Routing and Topology ................................................. 10
DQS and DQ Routing and Toplogy ............................................................. 11
DQGATE Routing ................................................................................. 12
List of Tables
1
2
3
4
5
6
7
Compatible JEDEC DDR2 Devices ..............................................................
C6454/5 Minimum PCB Stack Up ................................................................
PCB Stack Up Specifications .....................................................................
Placement Specifications ..........................................................................
Bulk Bypass Capacitors ...........................................................................
High-Speed Bypass Capacitors ..................................................................
Clock Net Class Definitions .......................................................................
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5
6
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Signal Net Class Definitions ....................................................................... 9
DDR2 Signal Terminations ........................................................................ 9
CK and ADDR_CTRL Routing Specification .................................................. 11
DQS and DQ Routing Specification ............................................................ 12
DQGATE Routing Specification ................................................................. 13
8
9
10
11
12
1
TMS320C6454/5
1.1
DDR2 Interface
This section provides the timing specification for the DDR2 interface as a PCB design and manufacturing
specification. The design rules constrain PCB trace length, PCB trace skew, signal integrity, cross-talk,
and signal timing. These rules, when followed, result in a reliable DDR2 memory system without the need
for a complex timing closure process. For more information regarding guidelines for using this DDR2
specification, Understanding TI's PCB Routing Rule-Based DDR2 Timing Specification (SPRAAV0).
1.1.1
DDR2 Interface Schematic
Figure 1 shows the DDR2 interface schematic for a x32 DDR2 memory system. The x16 DDR2 system
schematic is identical except that the high word DDR2 device is deleted. Pin numbers for the C6454/5 can
be obtained from the pin description section of the TMS320C6454 Fixed-Point Digital Signal Processor
Data Manual (SPRS311) and the TMS320C6455 Fixed-Point Digital Signal Processor Data Manual
(SPRS276). The DDR2 device pin numbers can be obtained from their device-specific data sheets.
1.1.2
Compatible JEDEC DDR2 Devices
Table 1 shows the parameters of the JEDEC DDR2 devices that are compatible with this interface.
Generally, the DDR2 interface is compatible with x16 DDR2-533 speed grade DDR2 devices.
Table 1. Compatible JEDEC DDR2 Devices
No.
(1)
(2)
(3)
1.1.3
Parameter
Min
Max
1
JEDEC DDR2 Device Speed Grade
2
JEDEC DDR2 Device Bit Width
3
JEDEC DDR2 Device Count
1
2
4
JEDEC DDR2 Device Ball Count
84
92
Unit
x16
Notes
See Note
(1)
Devices
See Note
(2)
Balls
See Note
(3)
DDR2-533
x16
Bits
Higher DDR2 speed grades are supported due to inherent JEDEC DDR2 backwards compatibility.
1 DDR2 device is used for 16 bit DDR2 memory system. 2 DDR2 devices are used for 32 bit DDR2 memory system.
92 ball devices retained for legacy support. New designs will migrate to 84 ball DDR2 devices. Electrrically the 92 and 84 ball
DDR2 devices are the same.
PCB Stackup
The minimum stackup required for routing the C6454/5 is a six layer stack as shown in Table 2. Additional
layers may be added to the PCB stack up to accommodate other circuity or to reduce the size of the PCB
footprint.
Table 2. C6454/5 Minimum PCB Stack Up
2
Layer
Type
Description
1
Signal
Top Routing Mostly Horizontal
2
Plane
Ground
3
Plane
Power
4
Signal
Internal Routing
5
Plane
Ground
6
Signal
Bottom Routing Mostly Vertical
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Complete stack up specifications are provided in Table 3.
C6454/5
DDR2
DEODT0
DED0
DED7
DSDDQM0
DSDDQS0
NC
T
T
T
T
T
T
DSDDQS0
DED8
T
DED15
DSDDQM1
DSDDQS1
DSDDQS1
T
DSDDQGATE0
DSDDQGATE1
DSDDQGATE2
DSDDQGATE3
T
DEODT1
DED16
DED23
DSDDQM2
DSDDQS2
DSDDQS2
DED24
DED31
DSDDQM3
DSDDQS3
DSDDQS3
T
T
T
BED7
LDM
LDQS
LDQS
BED
BED15
UDM
UDQS
UDQS
DDR2
ODT
NC
T
BED0
T
BED0
LDM
LDQS
LDQS
T
T
T
T
T
T
T
T
BED7
BED15
UDM
UDQS
UDQS
DBA0
T
BA0
BA0
DBA2
DEA0
T
T
BA2
A0
BA2
A0
DEA13
DCE0
DSDCAS
DSDRAS
DSDWE
DSDCKE
DDR2CLKOUT
DDR2CLKOUT
T
T
T
T
T
T
T
T
A13
CS
CAS
RAS
WE
CKE
CK
CK
A13
CS
CAS
RAS
WE
CKE
CK
CK
VREF
VREFSSTL
0.1mF**
T
*
**
ODT
BED0
0.1mF**
0.1mF**
Vio 1.8*
0.1mF
1 K W 1%
VREF
VREF
0.1mF
1 K W 1%
Terminator, if desired. See terminator comments.
Vio1.8 is the power supply for the DDR2 memories and C6455 DDR2 interface.
One of these capacitors can be eliminated if the divider and its capacitors are placed near a device VREF pin.
Figure 1. DM647/8 32-Bit DDR2 High Level Schematic
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C6454/5
DEODT0
DDR2
ODT
NC
DED0
T
BED0
DED7
DSDDQM0
DSDDQS0
T
T
T
BED7
LDM
LDQS
DSDDQS0
DED8
T
T
LDQS
BED8
DED15
DSDDQM1
DSDDQS1
T
T
T
BED15
UDM
UDQS
T
UDQS
DSDDQS1
DSDDQGATE0
DSDDQGATE1
DSDDQGATE2
DSDDQGATE3
DEODT1
DED16
T
NC
1 KΩ
NC
NC
(A)
Vio 1.8
DED23
DSDDQM2
DSDDQS2
DSDDQS2
NC
NC
1 KΩ
DED24
NC
1 KΩ
(A)
Vio 1.8
DED31
DSDDQM3
DSDDQS3
DSDDQS3
NC
NC
1 KΩ
1 KΩ
DBA0
T
BA0
DBA2
DEA0
T
T
BA2
A0
DEA13
DCE0
DSDCAS
DSDRAS
T
T
T
T
A13
CS
CAS
DSDWE
DSDCKE
DDR2CLKOUT
T
T
T
T
WE
CKE
CK
CK
DDR2CLKOUT
VREFSSTL
VREF
(B)
0.1 µF
T
A
B
(A)
RAS
0.1 µF
(B)
Vio 1.8
0.1 µF
VREF
1 K Ω 1%
VREF
0.1 µF
1 K Ω 1%
Terminator, if desired. See terminator comments.
Vio1.8 is the power supply for the DDR2 memory interface.
One of these capacitors can be eliminated if the divider and its capacitors are placed near a device VREF pin.
Figure 2. DM647/8 16-Bit DDR2 High Level Schematic
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Table 3. PCB Stack Up Specifications
No.
(1)
(2)
(3)
1.1.4
Parameter
Min
Typ
Max
Unit
Notes
1
PCB Routing/Plane Layers
6
2
Signal Routing Layers
3
3
Full ground layers under DDR2 routing Region
2
4
Number of ground plane cuts allowed within DDR routing region
5
Number of ground reference planes required for each DDR2 routing
layer
6
Number of layers between DDR2 routing layer and reference ground
plane
7
PCB Routing Feature Size
4
Mils
8
PCB Trace Width w
4
Mils
8
PCB BGA escape via pad size
18
Mils
9
PCB BGA escape via hole size
8
Mils
10
DSP Device BGA pad size
See Note
(1)
11
DDR2 Device BGA pad size
See Note
(2)
12
Single Ended Impedance, Zo
13
Impedance Control
See Note
(3)
0
1
0
50
Z-5
Z
75
Ω
Z+5
Ω
Please refer to the Flip Chip Ball Grid Array Package Reference Guide (SPRU811) for DSP device BGA pad size.
Please refer to the DDR2 device manufacturer documenation for the DDR2 device BGA pad size.
Z is the nominal singled ended impedance selected for the PCB specified by item 12.
Placement
Figure 2 shows the required placement for the C6454/5 device as well as the DDR2 devices. The
dimensions for Figure 3 are defined in Table 4. The placement does not restrict the side of the PCB that
the devices are mounted on. The ultimate purpose of the placement is to limit the maximum trace lengths
and allow for proper routing space. For a 16 bit DDR memory systems, the high word DDR2 device is
omitted from the placement.
X
Y
OFFSET
Y
DDR2
Device
Y
OFFSET
DDR2
Controller
A1
C6454/5
A1
Recommended DDR2 Device
Orientation
Figure 3. C6454/5 and DDR2 Device Placement
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Table 4. Placement Specifications
No.
(1)
(2)
(3)
(4)
(5)
1.1.5
Parameter
Min
Max
Unit
Notes
1
X
1660
Mils
See Notes
(1)
2
Y
1280
Mils
See Notes
(1)
3
Y Offset
650
Mils
See Notes
(2) (3)
,
(1)
4
DDR2 Keepout Region
See Note
(4)
5
Clearance from non-DDR2 signal to DDR2 Keepout Region
See Note
(5)
4
w
,
(2)
,
(2)
.
See Figure 1 for dimension defintions.
Measurements from center of DSP device to center of DDR2 device.
For 16 bit memory systems it is recommended that Y Offset be as small as possible.
DDR2 Keepout region to encompass entire DDR2 routing area
Non-DDR2 signals allowed within DDR2 keepout region provided they are separated from DDR2 routing layers by a ground
plane.
DDR2 Keep Out Region
The region of the PCB used for the DDR2 circuitry must be isolated from other signals. The DDR2 keep
out region is defined for this purpose and is shown in Figure 4. The size of this region varies with the
placement and DDR routing. Additional clearances required for the keep out region are shown in Table 4.
DDR2 Device
DDR2 Controller
A1
A1
Region should encompass all DDR2 circuitry and varies depending
on placement. Non-DDR2 signals should not be routed on the DDR
signal layers within the DDR2 keep out region. Non-DDR2 signals may
be routed in the region provided they are routed on layers separated
from DDR2 signal layers by a ground layer. No breaks should be
allowed in the reference ground layers in this region. In addition, the
1.8 V power plane should cover the entire keep out region.
Figure 4. DDR2 Keepout Region
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1.1.6
Bulk Bypass Capacitors
Bulk bypass capacitors are required for moderate speed bypassing of the DDR2 and other circuitry.
Table 5 contains the minimum numbers and capacitance required for the bulk bypass capacitors. Note
that this table only covers the bypass needs of the DSP and DDR2 interfaces. Additional bulk bypass
capacitance may be needed for other circuitry.
Table 5. Bulk Bypass Capacitors
No.
Parameter
1
DVDD18 Bulk Bypass Capacitor Count
2
DVDD18 Bulk Bypass Total Capacitance
3
DDR#1 Bulk Bypass Capacitor Count
4
DDR#1 Bulk Bypass Total Capacitance
5
DDR#2 Bulk Bypass Capacitor Count
Min
3
Max
Unit
Notes
Devices
See Note
30
µF
1
Devices
10
µF
1
Devices
(1)
See Note
(1)
See
Notes (1),
(2)
6
(1)
(2)
DDR#2 Bulk Bypass Total Capacitance
10
µF
See Note
(2)
These devices should be placed near the device they are bypassing, but preference should be given to the placement of the
high-speed (HS) bypass caps.
Only used on 32-bit wide DDR2 memory systems
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High-Speed Bypass Capacitors
High-Speed (HS) bypass capacitors are critical for proper DDR2 interface operation. It is particularly
important to minimize the parasitic series inductance of the HS bypass cap, DSP/DDR power, and
DSP/DDR ground connections. Table 6 contains the specification for the HS bypass capacitors as well as
for the power connections on the PCB.
1.1.8
Net Classes
Table 7 lists the clock net classes for the DDR2 interface. Table 8 lists the signal net classes, and
associated clock net classes, for the signals in the DDR2 interface. These net classes are used for the
termination and routing rules that follow.
Table 6. High-Speed Bypass Capacitors
No.
Min
HS Bypass Capacitor Package Size
2
Distance from HS bypass capacitor to device being bypassed
3
Number of connection vias for each HS bypass capacitor
2
4
Trace length from bypass capacitor contact to connection via
1
5
Number of connection vias for each DDR2 device power or ground balls
1
6
Trace length from DDR2 device power ball to connection via
7
DVDD18 HS Bypass Capacitor Count
20
8
DVDD18 HS Bypass Capacitor Total Capacitance
1.2
9
DDR#1 HS Bypass Capacitor Count
10
DDR#1 HS Bypass Capacitor Total Capacitance
11
DDR#2 HS Bypass Capacitor Count
12
DDR#2 HS Bypass Capacitor Total Capacitance
(1)
(2)
(3)
(4)
8
Parameter
1
Max
Unit
0402
10 Mils
250
0.4
8
0.4
See Note
(2)
See Note
(3)
See Note
(3)
Mils
Vias
35
8
(1)
Mils
Vias
30
Notes
See Note
Mils
Devices
µF
Devices
µF
Devices
µF
See Notes
(3) (4)
,
See Note
(4)
LxW, 10 mil units, i.e., a 0402 is a 40x20 mil surface mount capacitor
An additional HS bypass capacitor can share the connection vias only if it is mounted on the opposite side of the board.
These devices should be placed as close as possible to the device being bypassed.
Only used on 32-bit wide DDR2 memory systems
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Table 7. Clock Net Class Definitions
Clock Net Class
CK
DDR2CLKOUT/DDR2CLKOUT
DQS0
DSDDQS0/DSDDQS0
DQS1
DSDDQS1/DSDDQS1
(1)
DSDDQS2/DSDDQS2
DQS3 (1)
DSDDQS3/DSDDQS3
DQS2
(1)
DSP Pin Names
Only used on 32-bit wide DDR2 memory systems.
Table 8. Signal Net Class Definitions
Associated Clock Net
Class
DSP Pin Names
CK
DBA[2:0], DEA[13:0], DCE0, DSDCAS, DSDRAS, DSDWE, DSD_CKE
DQ0
DQS0
DED[7:0], DSDDQM0
Clock Net Class
ADDR_CTRL
(1)
1.1.9
DQ1
DQS1
DED[15:8], DSDDQM1
DQ2 (1)
DQS2
DED[23:16], DSDDQM2
DQ3 (1)
DQS3
DED[31:24], DSDDQM3
DQGATEL
CK, DQS0, DQS1
DSDDQGATE0, DSDDQGATE1
DQGATEH (1)
CK, DQS2, DQS3
DSDDQGATE2, DSDDQGATE3
Only used on 32-bit wide DDR2 memory systems.
DDR2 Signal Termination
No terminations of any kind are required in order to meet signal integrity and overshoot requirements.
Serial terminators are permitted, if desired, to reduce EMI risk; however, serial terminations are the only
type permitted. Table 9 shows the specifications for the series terminators.
Table 9. DDR2 Signal Terminations
No.
(1)
(2)
(3)
(4)
Parameter
Min
Typ
Max
Unit
Notes
10
Ω
See Note
(1)
22
Zo
Ω
See Notes
(2) (3)
,
(1)
0
22
Zo
Ω
See Notes (1),
(2) (3) (4)
, , ,
0
10
Zo
Ω
See Notes
(2) (3)
,
1
CK Net Class
0
2
ADDR_CTRL Net Class
0
3
Data Byte Net Classes (DQS0-DQS3, DQ0-DQ3)
4
DQGATE Net Classes (DQGATEL, DQGATEH)
,
(1)
,
Only series termination is permitted, parallel or SST specifically disallowed.
Terminator values larger than typical only recommended to address EMI issues.
Termination value should be uniform across net class.
When no termination is used on data lines (0 Ωs), the DDR2 devices must be programmed to operate in 60% strength mode.
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VREF Routing
VREF is used as a reference by the input buffers of the DDR2 memories as well as the C6454/5’s. VREF
is intended to be 1/2 the DDR2 power supply voltage and should be created using a resistive divider as
shown in Figure 1. Other methods of creating VREF are not recommended. Figure 5 shows the layout
guidelines for VREF.
VREF Bypass Capacitor
DDR2 Device
A1
VREF Nominal Minimum
Trace Width is 20 Mils
C6454/5
Device
A1
Neck down to minimum in BGA escape
regions is acceptable. Narrowing to
accomodate via congestion for short
distances is also acceptable. Best
performance is obtained if the width
of VREF is maximized.
Figure 5. VREF Routing and Topology
1.1.11
DDR2 CK and ADDR_CTRL Routing
Figure 6 shows the topology of the routing for the CK and ADDR_CTRL net classes. The route is a
balanced T as it is intended that the length of segments B and C be equal. In addition, the length of A
should be maximized.
T
C
A
DDR2
Controller
B
A1
C6454/5
A1
Figure 6. CK and ADDR_CTRL Routing and Topology
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Table 10. CK and ADDR_CTRL Routing Specification
No
(1)
(2)
(3)
Parameter
Min
Typ
(1)
Max
Unit
N otes
25
Mils
See Note
(1)
25
Mils
See Note
(2)
CACLM+50
Mils
See Note
(3)
100
Mils
100
Mils
4w
See Note
(2)
3w
See Note
(2)
See Note
(1)
1
Center to center CK-CK spacing
2w
2
CK A to B/A to C Skew Length Mismatch
3
CK B to C Skew Length Mismatch
4
Center to center CK to other DDR2 trace spacing
5
CK/ADDR_CTRL nominal trace length
6
ADDR_CTRL to CK Skew Length Mismatch
7
ADDR_CTRL to ADDR_CTRL Skew Length Mismatch
8
Center to center ADDR_CTRL to other DDR2 trace
spacing
9
Center to center ADDR_CTRL to other ADDR_CTRL
trace spacing
10
ADDR_CTRL A to B/A to C Skew Length Mismatch
100
Mils
11
ADDR_CTRL B to C Skew Length Mismatch
100
Mils
4w
CACLM-50
CACLM
Series terminator, if used, should be located closest to DSP.
Center to center spacing is allowed to fall to minimum (w) for up to 500 mils of routed length to accommodate BGA escape and
routing congestion.
CACLM is the longest Manhattan distance of the CK and ADDR_CTRL net classes.
Figure 7 shows the topology and routing for the DQS and DQ net classes; the routes are point to point.
Skew matching across bytes is not needed nor recommended.
T
T
E0
E1
DDR2
Controller
A1
C6454/5
T
A1
E2
T
E3
Figure 7. DQS and DQ Routing and Toplogy
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Table 11. DQS and DQ Routing Specification
No.
(1)
(2)
(3)
(4)
(5)
(6)
(7)
Parameter
Min
1
Center to center DQS-DQS spacing
2
DQS E Skew Length Mismatch
3
Center to center DQS to other DDR2 trace spacing
4
DQS/DQ nominal trace length
5
Typ
(1)
Max
Unit
Notes
2w
25
Mils
4w
See Note
(2)
DQLM+50
Mils
See Notes (1),
(3) (4) (5)
, ,
DQ to DQS Skew Length Mismatch
100
Mils
See Notes
(4) (5)
,
(3)
6
DQ to DQ Skew Length Mismatch
100
Mils
See Notes
(4) (5)
,
(3)
7
Center to center DQ to other DDR2 trace spacing
4w
See Notes
(2)
8
Center to Center DQ to other DQ trace spacing
3w
See Notes
(7)
9
DQ/DQS E Skew Length Mismatch
See Notes
(4) (5)
,
(3)
DQLM50
DQLM
(6)
(2)
100
Mils
,
,
,
,
,
Series terminator, if used, should be located closest to DDR.
Center to center spacing is allowed to fall to minimum (w) for up to 500 mils of routed length to accommodate BGA escape and
routing congestion.
A 16 bit DDR memory system will have two sets of data net classes, one for data byte 0, and one for data byte 1, each with an
associated DQS (2 DQS's).
A 32 bit DDR memory system will have four sets of data net classes, one each for data bytes 0 through 3, and each associated
with a DQS (4 DQS's).
There is no need and it is not recommended to skew match across data bytes, ie from DQS0 and data byte 0 to DQS1 and data
byte 1.
DQ's from other DQS domains are considered other DDR2 trace.
DQLM is the longest Manhattan distance of each of the DQS and DQ net classes.
Figure 8 shows the routing for the DQGATE net classes. Table 12 contains the routing specification.
FL
A1
DDR2
Controller
T
T
FH
A1
C6454/5
Figure 8. DQGATE Routing
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Table 12. DQGATE Routing Specification
No.
(1)
(2)
(3)
(4)
(5)
2
Parameter
Min
Typ
Max
Unit
Notes
1
DQGATEL Length F
CKB0B1
See Note
2
DQGATEH Length F
CKB2B3
See Notes
(2) (3)
,
3
Center to center DQGATE to any other trace spacing
4
DQS/DQ nominal trace length
DQLM+50
Mils
5
DQGATEL Skew
100
Mils
See Note
6
DQGATEH Skew
100
Mils
See Notes
(5) (3)
,
(1)
4w
DQLM-50
DQLM
(4)
CKB0B1 is the sum of the length of the CK net plus the average length of the DQS0 and DQS1 nets.
CKB2B3 is the sum of the length of the CK net plus the average length of the DQS2 and DQS3 nets.
Only used on 32-bit wide DDR2 memory systems.
Skew from CKB0B1
Skew from CKB2B3
References
•
•
•
•
TMS320C6454 Fixed-Point Digital Signal Processor Data Manual (SPRS311)
TMS320C6455 Fixed-Point Digital Signal Processor Data Manual (SPRS276)
Understanding TI's PCB Routing Rule-Based DDR2 Timing Specification (SPRAAV0)
Flip Chip Ball Grid Array Package Reference Guide (SPRU811)
SPRAAA7E – July 2008
Submit Documentation Feedback
Implementing DDR2 PCB on the TMS320C6454/5
13
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