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Texas Instruments TMS320DM6467 Universal Serial Bus Downstream Host Compliance Testing Application notes
Application Report
SPRAAV9 – May 2008
TMS320DM6467 Universal Serial Bus Downstream Host
Compliance Testing
Zegeye Alemu ........................................................................................................ DSPS Applications
ABSTRACT
This application report describes the TMS320DM6467 embedded Host electrical
compliance of a high-speed (HS) universal serial bus (USB) operation conforming to
the USB 2.0 specification. The non-OTG controller supports the USB 2.0 Host mode
operation at HS, full-speed (FS), and low-speed (LS) . Furthermore, it supports the
USB 2.0 device mode operation at HS and FS. LS operation, when assuming the role
of a device, is not supported.
1
2
3
4
5
Contents
Introduction .......................................................................................... 2
Test Items ........................................................................................... 3
Required Instruments .............................................................................. 4
Test Condition ....................................................................................... 5
References ......................................................................................... 31
List of Figures
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
USB Functional Block Diagram .................................................................. 2
Equipment Setup for High-Speed Downstream Host Signal Quality Testing ............... 6
Downstream Eye Diagram ........................................................................ 7
Downstream Waveform Plot ...................................................................... 8
Rise and Fall Time Patterns....................................................................... 8
Duty Cycle Distortion (DCD) ...................................................................... 9
Random Jitter/Deterministic Jitter/Total Jitter ................................................... 9
Equipment Setup for Downstream Host Packet Parameters Tests ........................ 10
Status Stage of a GET DEVICE DESCRIPTOR Transaction SYNC Field of the
Token Packet ...................................................................................... 11
Inter-Packet-Gap Between the Data Packet of Device and Acknowledge Packet of
the Embedded Host on the Data Stage of the GET DESCRIPTOR Command .......... 12
Inter-Packet-Gap Between the Token Packet and the Data Packet of the Status
Stage of the GET DESCRIPTOR Transaction ................................................ 13
EOP Field of Non-SOP Packet of the Data Packet of the Status Stage of the GET
DESCRIPTOR Command ........................................................................ 14
EOP Field of an SOP Packet .................................................................... 15
Equipment Setup for Downstream Host Chirp and Suspend and Resume Timings .... 16
Downstream Chirp Response Time ............................................................ 17
Chirp-K and Chirp-J Duration .................................................................... 18
Time Between First SOF and Last Chirp-(J or K)............................................. 19
DUT Host Enters Suspend State................................................................ 20
DUT Host Resumes .............................................................................. 21
Equipment Setup for Downstream Test J/K, SEO_NAK ..................................... 22
Equipment Setup for Full-Speed Downstream Host Signal Quality Testing............... 24
Full-Speed Downstream Signal Quality Test .................................................. 25
Waveform Plot ..................................................................................... 26
Full-Speed Eye Diagram ......................................................................... 27
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Introduction
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25
26
27
28
Equipment Setup for Low-Speed Downstream Host Signal Quality Testing ..............
Low-Speed Downstream Signal Quality Test .................................................
Low-Speed Waveform Plot ......................................................................
Low-Speed Eye Diagram ........................................................................
28
29
30
30
List of Tables
1
2
3
4
5
6
7
8
1
Host Electrical Tests Result Summary........................................................... 3
Test Categories ..................................................................................... 3
Required Instruments .............................................................................. 4
Power Supply Voltage and Temperature Condition ............................................ 5
Test Packet Data ................................................................................... 5
Overall Results of Signal Quality Test .......................................................... 6
Result Summary for Full-Speed Downstream Host Signal Quality ......................... 27
Result Summary for Low-Speed Downstream Host Signal Quality Test .................. 31
Introduction
The DM6467 Host high-speed electrical test of the USB is performed on a verification and debug board
(VDB), which is used to validate the device feature and is not optimized for USB characterization. Better
results are expected when using test boards that are optimized for characterization purposes. These
optimized boards follow the board design guidelines as recommended by the USB-IF. In addition, the
DM6467 device is soldered directly to the board instead of residing in a socket as used on the VDB.
The USB functional block diagram is shown in Figure 1.
Endpoint Control
DMA Requests
EP0
Control
-Host
EP0
Control
-Function
Transmit
EP1 - 4
Control
Combine Endpoints
CPU Interface
Interrupts
Interrupt
Control
Receive
Host
Transaction
Scheduler
VBUS
-Slave
mode
EP Reg.
Decoder
Common
Regs
TxRx Macrocell
(UTMI + Level 3
compliant)
Optional
ULPI Link
Wrapper
UTM
Synchronization
Packet
Encode/Decode
Data Sync
Packet Encode
Packet Decode
Timers
CRC Gen/Check
RAM Controller
Rx
Buff
Rx
Buff
Tx
Buff
Tx
Buff
Cycle Control
Cycle Control
FIFO
Decoder
DMA
Controller
(optional)
VBUS
-Master
Mode
RAM
Figure 1. USB Functional Block Diagram
Code Composer Studio is a trademark of Texas Instruments.
Windows is a registered trademark of Microsoft Corporation in the United States and/or other countries.
Tektronix is a registered trademark of Tektronix, Inc.
All other trademarks are the property of their respective owners.
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Test Items
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2
Test Items
Table 1 shows a summary of the test listings results of the compliance tests performed to evaluate the
USB controller operation while operating in Host mode.
Table 1. Host Electrical Tests Result Summary
Test#
Test Items
Result
USB_EL_2
HS Host transmitter data rate 480 Mb/s ± 0.05%
PASS
USB_EL_3
HS Host signal quality test measured at the near end
PASS
USB_EL_6
10% to 90% differential rise and fall time > 500 ps
PASS
USB_EL_7
Monotonic data transitions over the vertical openings in the appropriate EYE pattern
template
PASS
USB_EL_21
SYNC field (packet originating from Host)
PASS
USB_EL_22
Inter-packet gap field (device and Host)
PASS
USB_EL_23
Inter-packet gap field (back-to-back Host)
PASS
USB_EL_25
EOP field (non-SOF packets)
PASS
USB_EL_55
EOP field (SOF packets)
PASS
USB_EL_33
Chirp response time
PASS
USB_EL_29
Chirp-K and chirp-J duration
PASS
USB_EL_31
Time between SOF and last chirp-(JorK)
PASS
USB_EL_39
Host suspend capability/timing
PASS
USB_EL_41
Host resume capability/timing
PASS
USB_EL_8
Test J/K (controller transmits continuous J)
PASS
USB_EL_8
Test K (controller transmits continuous K)
PASS
USB_EL_9
Test_SE0 (controller does not drive data lines)
PASS
---------
Legacy compliance (full-speed signal quality)
PASS
---------
Legacy compliance (low-speed signal quality)
PASS
The tests are classified into six categories (see Table 2). These categories correspond to the electrical
test in the USB2.0 compliance test.
Table 2. Test Categories
Test Items
Categories
HS Host transmitter data rate 480 Mb/s ± 0.05%
HS downstream signal quality test
HS Host signal quality test measured at the near end
10% to 90% differential rise and fall time > 500ps
Monotonic data transitions over the vertical openings in the
appropriate EYE pattern template
SYNC field (packet originating from Host)
Host packet parameters
Inter-packet gap field (device and Host)
Inter-packet gap field (back-to-back Host)
EOP field (non-SOF packets)
EOP field (SOF packets)
Chirp response time
Host chirp timing
Chirp-K and chirp-J duration
Time between SOF and last chirp-(JorK)
Host suspend capability/timing
Host suspend/resume timing
Host resume capability/timing
Test J (controller transmits continuous J)
Host test_J/K/SE0
Test K (controller transmits continuous K)
Test_SE0 (Host stops driving data lines)
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Required Instruments
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Table 2. Test Categories (continued)
Test Items
Categories
Full-speed signal quality
Legacy USB compliance testing
Low-speed signal quality
3
Required Instruments
This section discusses the required instruments used for performing compliance tests. USB
characterization tests are performed using test fixtures produced by Tektronix®.
Note:
It is recommended that you use a scope with a 2 GHz bandwidth for performing the tests.
This will not allow noise magnification to disturb the test. The DSA71604 is a very fast scope
with a maximum operating bandwidth of 16 GHz. Even though the bandwidth needed is user
selectable, during the time this test was performed, the TDSUSB2 software re-configures the
user set bandwidth to the default 16 GHz speed configuration, disrupting the user settings.
This is more important when performing low-speed signal quality testing since the test result
captures differ heavily with a low bandwidth configuration yielding a much better result.
The high-speed electrical test (HSET) is not applicable for use with this solution since it requires an EHCI
USB controller with Windows® XP/2000 running on the device. The DM6467 USB controller is not an
EHCI controller, nor is it not running the required operating system (O/S). For this reason, you are
required to create a similar application to the HSET utility furnished by the USB-IF. This utility should put
the USB controller into the required test modes or configure the USB controller to perform transfers to
create the right test conditions applicable for the test. The method used to invoke these tests is a Host test
program running under Code Composer Studio™ software with test options controlled by variables where
you select the desired test by modifying the variables within the watch window.
Table 3. Required Instruments
Type
Manufacturer
Product
Use
Oscilloscope
Tektronix
DSA71604
To measure USB signals
Differential probe (1)
Tektronix
P7313
Signal quality/receiver sensitivity tests
Single ended FET probe (2)
Tektronix
P6245
Packet parameters/Chirp timings
Measurement application (USB test
software that is part of the scope
application)
Tektronix
TDSUSB V3.1.1 Build
2
USB compliance test software
specifically used for USB
Test fixture
Tektronix
TDSUSBF
071-1832-01
For USB test
Power Supply
-
-
5 V power supply for TDSUSBF
Digital multimeter
-
-
Actual voltage monitor
TI
EVM like board
Non-optimized test board used for
DM6467 device validation
-
-
For full-speed signal quality testing
Test board (VDB)
(1)
4 self powered USB certified high-speed
hubs
1 self powered USB certified full-speed
hub
1 known good USB 2.0 certified compliant
device
-
-
For high-speed testing
1 known good USB 1.1 certified complaint
device
-
-
For full-speed signal quality testing
1 USB mouse
-
-
For low-speed signal quality test
6 five meter USB cable
-
-
For full-speed signal quality testing
(1)
4
For full-speed signal quality testing
Results could change for the better if using an optimized test board.
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4
Test Condition
4.1
Power Supply Voltage/Temperature
Table 4 shows the power supply voltage and temperature conditions:
Table 4. Power Supply Voltage and Temperature Condition
4.2
Parameter
Min
Typ
Max
Unit
USB_VDDA1P2LDO
V
1.14
1.2
1.26
USB_VDDA3P3
3.1
3.3
3.5
V
Operating Temperature
-10
25
95
°C
HS Downstream Signal Quality Test
The HS downstream signal quality test uses the TEST_PACKET to place the DM6467 USB controller in a
test mode where the controller continuously transmits a fixed defined format test packet, which is defined
in the USB 2.0 specification, Section 7.1.20. Even though there are many ways to achieve this task, the
method used here is for the DM6467 to enumerate a known good device (a HS USB Flash drive); at the
end of enumeration, you will force the device to go into TEST_PACKET test mode via the Code Composer
Studio watch window. When this test mode is entered, the device continually transmits the data packet
shown in Table 5.
The oscilloscope, along the embedded TDSUSB2 software, automatically analyzes the test packet signal
quality as observed on the USB bus. For detailed procedures on how to configure the scope as well as the
TDSUSB2 software, see the Host High-Speed Electrical Test Procedure documentation issued by the
USB Implementers Forum (http://www.usb.org/home).
Table 5. Test Packet Data
Data Used for Generating Test Packet
00 00 00 00 00 00 00 00
00 AA AA AA AA AA AA AA
AA EE EE EE EE EE EE EE
EE FE FF FF FF FF FF FF
FF FF FF FF FF 7F BF DF
EF F7 FB FD FC 7E BF DF
EF F7 FB FD 7E
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Test Condition
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Figure 2 displays the equipment setup for high-speed downstream signal quality test.
Tektronix Oscillosope With
TDSUSB2 Application Running
Differential Probe P7313
Host
SQ
Host TDR
Known Good Device
A
A
Host
DUT
J20
J16
DM6467
Flash Drive
Figure 2. Equipment Setup for High-Speed Downstream Host Signal Quality Testing
4.2.1
EL_2: Signal Rate
A USB 2.0 high-speed transmitter data rate must be 480 Mb/s ± 0.05%.
4.2.2
EL_3: Signal Quality/Eye Diagram Test
An eye diagram provides an intuitive view of jitter. It is a composite view of all the bit periods of a captured
waveform superimposed upon each other. The USB 2.0 downstream port on a device, without a captive
cable, must meet template 1 transform waveform requirements measured at a test point close to the port.
4.2.3
EL_6: Rise and Fall Time
A USB 2.0 high-speed driver must have 10% to 90% differential rise and fall times of greater than 500 ps.
4.2.4
EL_7: Monotonic Data Transitions
A USB 2.0 driver must have monotonic data transitions over the vertical openings specified in the
appropriate EYE pattern template. These results were based on USB-IF/waiver limits.
Table 6. Overall Results of Signal Quality Test
Measurement
Name
Minimum
Maximum
Mean
pk-pk
Standard
Deviation
RMS
Pop.
Status
-
-
-
-
-
-
-
Pass
Signal rate
474.1477 Mbps
488.1790
Mbps
479.9187 Mbps
0.0000 bps
2.254397 Mbps
479.9072
Mbps
512
Pass
EOP width
-
-
16.63800 ns
-
-
-
1
Pass
EOP width (bits)
-
-
7.984887
-
-
-
1
Pass
Rise time
-719.3333 ps
2.947333 ns
624.3670 ps
3.666667
ns
346.5622 ps
713.3141 ps
107
Pass
Fall time
458.4421 ps
1.309169 ns
897.5293 ps
850.7271
ps
145.8569 ps
909.1953 ps
108
Pass
Eye diagram test
(1)
6
(1)
Additional Information:
• Consecutive jitter range: 53.98 ps to 33.51 ps RMS jitter 16.98 ps
• KJ paired jitter range: - 36.29 ps to 42.12 pas RMS jitter 13.10 ps
• JK paired jitter range: -37.51 ps to 27.63 ps RMS jitter 12.75 ps
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•
•
•
•
•
Eye diagram/signal eye (Figure 3)
Waveform plot (Figure 4)
Rise/fall time (Figure 5)
Duty cycle distortion (DCD) (Figure 6)
Jitter (Figure 7)
– Random jitter (RJ)
– Deterministic jitter (DJ)
– Total jitter (TJ)
0.5
0.4
Differential Signal. V
0.3
0.2
0.1
0.0
0-.1
-0.2
0.2
-0.4
-0.5
0.0
0.2
0.4
0.6
0.8
10
1.2
1.4
1.6
1.8
20
-9
Time (x 10 )s
Figure 3. Downstream Eye Diagram
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Test Condition
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0.4
0.3
Differential Signal. V
0.2
0.1
0.0
0-.1
-0.2
0.2
-0.4
0.0
0.2
0.4
0.8
0.6
10
-6
Time (x 10 )s
Figure 4. Downstream Waveform Plot
Pattern
10%
10%
Rise Time
Fall Time
Figure 5. Rise and Fall Time Patterns
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Pattern
Data Rate
Duty Cycle Distortion
Figure 6. Duty Cycle Distortion (DCD)
RJ: Random Jitter
(Normal Distribution/Dependent
on the Bit Error Rate)
DJ: Deterministic Jitter
(Non-Normal Distribution)
Histogram
DJ
TJ: Total Jitter (= RJ + DJ)
RJ
RJ
TJ
Figure 7. Random Jitter/Deterministic Jitter/Total Jitter
4.3
Host Packet Parameters
The Host packet parameter tests are comprised of a set of tests that pertains to the fields/elements of
USB packets. Unlike the signal quality test, the Host controller does not need to enter into a test mode. A
single step GET DEVICE DESCRIPTOR control transfer is invoked from the DM6467 DUT Host by
pausing in between transactions to an attached known good high-speed device (Flash drive was used on
this setup). The downstream host high-speed packet parameter test requires the use of the three stages
of the GET DEVICE DESCRIPTOR command: setup, data, and status. The DM6467 DUT Host invokes
the setup stage of the transaction and pauses until it is told to continue. For a GET DEVICE
DESCRIPTOR command, it would be good to measure the Host packet parameters tests from either the
setup stage or the status stage of the transaction since both of these stages comprises of the token and
data packets originating from the Host. The packet delimiter fields, SYNC, EOP fields, and inter-packet
delay are measured from either the setup stage or the status stage of the transaction.
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Test Condition
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Figure 8 displays the equipment setup for the high-speed downstream Host packet parameter tests.
Tektronix Oscillosope With
TDSUSB2 Application Running
Differential Probe P7313
DM6467
Device SQ Test
Power
J92
B
J35
TNIT Test Refresh
J91
S6 Switch Should
be Positioned
to INIT Position.
Should See the
Red LED Lit.
INT
INT LED
J31
A
Flash Drive
B
810 Qual
J310
J34
Host
DUT
J37
Known Good Device
DUT
Segment of Tektronix
Compliance Test Fixture
(TDSUSBF)
Figure 8. Equipment Setup for Downstream Host Packet Parameters Tests
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4.3.1
EL_21: Synchronization (SYNC) Field
The SYNC field for all transmitted packets (not repeated packets) must begin with a 32-bit SYNC field.
Figure 9 displays the status stage of the GET DESCRIPTOR command with the SYNC field of the token
packet zoomed.
Handshake packet SYNC field: PASS
Note:
Measured value: 66.0 ns => 66.0 ns / (1/480*10^6) = 31.68 bits.
Figure 9. Status Stage of a GET DEVICE DESCRIPTOR Transaction SYNC Field of the Token Packet
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Test Condition
4.3.2
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EL_22: Inter-Packet-Gap Field of Device and Host Packets
When transmitting after receiving a packet, hosts and devices must provide an inter-packet-gap of at least
8-bit times and not more than 192-bit times.
To test this parameter, it is important to use a transaction that forces the DM6467 Host to source a packet
in response to a reception of a packet from the known good device. The data stage of the GET
DESCRIPTOR command is ideal transaction to measure the inter-packet-gap existing between the device
responding with its descriptor data and the DUT Host acknowledging the reception by testing the gap time
honored by the DUT Host DM6467 device.
Figure 10 displays the inter-packet-gap observed between the device and embedded Host packets.
Packet gap between device data packet and Host acknowledge packet: PASS
Note:
Measured value: 221.6 ns => 221.6 ns / (1/480*10^6) = 106.368 bits.
Figure 10. Inter-Packet-Gap Between the Data Packet of Device and Acknowledge Packet of the
Embedded Host on the Data Stage of the GET DESCRIPTOR Command
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4.3.3
EL_23: Inter-Packet-Gap Field of Back-to-Back Packets
The Host transmitting two packets in a row must have an inter-packet-gap of at least 88-bit times and not
more than 192-bit times.
Figure 11 displays the inter-packet-gap between the token packet and the zero byte data packet of the
status stage of a GET DESCRIPTOR command sourced from the DUT Host with the inter-packet-gap
zoomed.
Packet gap between the Host token packet and the Host data packet: PASS
Note:
Measured value: 273.2 ns => 273.2 ns / (1/480*10^6) = 131.136 bits.
Figure 11. Inter-Packet-Gap Between the Token Packet and the Data Packet of the Status Stage of the
GET DESCRIPTOR Transaction
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Test Condition
4.3.4
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EL_25: End-of-Packet (EOP) Field of Non-SOF Packets
The EOP for all transmitted packets (except SOF) must be an 8-bit NRZI byte of 01111111 without bit
stuffing. Note, that a longer EOP is waiverable.
The EOP of the token packet or the data packet of the status stage can be used to verify this timing since
both of these packets are sourced by the DUT DM6467 Host during the status stage of a GET
DESCRIPTOR command. Figure 12 displays the EOP field of the data packet of the status stage of the
GET DESCRIPTOR command.
Non-SOP EOP field: PASS.
Note:
Measured value: 17.2 ns => 17.2 ns / (1/480*10^6) = 8.256 bits.
Figure 12. EOP Field of Non-SOP Packet of the Data Packet of the Status Stage of the GET DESCRIPTOR
Command
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4.3.5
EL_55: End-of-Packet (EOP) Field of SOF Packets
The Host transmitting SOF packets must provide a 40-bit EOP without bit stuffing where the first symbol of
the EOP is a transition from the last data symbol. Figure 13 displays the EOP field capture of a SOF
packet.
SOF packet EOP Field: PASS.
Note:
Measured value: 83.6 ns => 83.6 ns / (1/480*10^6) = 40.128 bits
Figure 13. EOP Field of an SOP Packet
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Test Condition
4.4
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Device Chirp Timing
The Host chirp timing is used to validate high-speed detection handshake and happens during reset time.
Some time after the Host resets a high-speed device, the device should indicate its high-speed capability
by generating chirp-K signaling. A high-speed Host follows up by generating a minimum of three sets of
chirp-KJ signaling at full-speed signaling environment. The device should disconnect its 1.5KΩ pull-up
resistor and enable the 45 Ω termination resistors right after the last chirp J from the Host.
To invoke this test, a similar setup used for the device parameter testing, with two single ended FET
probes replacing the differential probe, is used and shown on Figure 14.
There are several ways to perform this test. The method used here is to perform the test during an initial
attachment. However, the embedded Host test software can be programmed to perform a RESET.
Tektronix Oscillosope With
TDSUSB2 Application Running
P6245 Probes
DM6467
A
INT
INT LED
Power
J92
B
J35
INIT Test Refresh
J91
S6 Switch Should
be Positioned
to INIT Position.
Should See the
Red LED Lit.
Flash Drive
B
810 Qual
J310
Device SQ Test
J31
J34
Host
DUT
J37
Known Good Device
DUT
Segment of Tektronix
Compliance Test Fixture
(TDSUSBF)
Figure 14. Equipment Setup for Downstream Host Chirp and Suspend and Resume Timings
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4.4.1
EL_33: Chirp Response Timing
Downstream ports start sending and alternating a sequence of chirp K’s and chirp J’s within 100 µs after
the device chirp K stops. Should be <= 100 µs.
The device chirp K stop time is usually detected when the signal level of the chirp K drops around its high
value.
Chirp response timing is the time between the device’s de-assertion of chirp-K and the start of the
alternate chirp-K and chirp-J sent by the Host.
Figure 15 displays the chirp response time measured for a downstream DM6467 Host device.
Chirp response time: PASS
Note:
Measured value: 2.0 µs
Figure 15. Downstream Chirp Response Time
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Test Condition
4.4.2
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EL_34: Chirp-K and Chirp-J Duration
Downstream ports start sending and alternating a sequence of chirp K’s and chirp J’s within 100 µs after
the device chirp K stops.
Chirp-K and chirp-J duration must be between 40 µs and 60 µs.
Figure 16 displays chirp-K and chirp-J duration measured for the DM6467 Host DUT device.
Chirp-K and chirp-J duration: PASS.
Note:
Measured value: 1.09651 ms.
Figure 16. Chirp-K and Chirp-J Duration
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4.4.3
EL_35: Time Between SOF and Last Chirp-(J or K)
The downstream DM6467 DUT Host should begin sending SOFs within 500 µs and not sooner than 100
µs from the transmission of the last chirp-(J or K).
Figure 17 displays the captured time for this event.
Time between SOF and the last chirp-(J or K): PASS
Note:
Measured value: 346 µs.
Figure 17. Time Between First SOF and Last Chirp-(J or K)
4.5
Host Suspend/Resume Timing
The embedded Host is attached to a known good high-speed device (Flash drive) and finishes up the
enumeration process. The DUT Host does no transaction, but periodically generates a SOF packet to the
attached high-speed device every 125 µs.
The Host DUT is forced to transition to suspend state via the firmware when needed. The results are that
the DM6467 Host DUT stops generating SOF packets.
To exit suspend mode and start the resume process, the DUT Host firmware does the following:
1. Clears the suspend bit
2. Sets the resume bit
3. Leaves the resume bit set for around 20 ms
4. Clears the resume bit
This will end the resume state.
Figure 14 displays the equipment setup for the suspend and resume tests.
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Test Condition
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EL_39: Host Suspend Timing
This is the time interval from the end of the last SOF packet issued by the DUT host to when the device
attached its full-speed pull-up resistor on D+ (transition to full-speed J-state). This time should be between
3.0 ms and 3.125 ms. No measurement is required as this sequence verifies that the Host supports the
suspend state.
The embedded Host is attached to a known good high-speed device (Flash drive) and finishes up the
enumeration process. The DUT Host does no transaction, but periodically generates a SOF packet to the
attached high-speed device every 125 µs. The Host DUT is then forced to transition to suspend state via
the Firmware. The results are that the DM6467 Host DUT stops generating SOF packets.
Figure 18 captures the signal capture of SOF from DUT Host vanishing when it enters into suspend mode
along with the automatic result published by the TDSUSB2 software.
DUT Host support suspend capability: PASS
Note:
Measured Value (by the TDSUSB2 S/W): 3.04 ms.
Suspend Test Result: Pass
Figure 18. DUT Host Enters Suspend State
20
Measurement Name
Suspend Time
USB Limits
Status
Suspend Test
3.0.7894 ms
3.000000 ms to 3.125000 ms
Pass
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4.5.2
EL_41: Host Resume Timing
After resuming a port, the Host must begin sending SOFs within 3 ms of the start of the idle state.
Figure 19 captures the resume signal capture alongside the automatic result generated by the TDSUSB2
software.
DUT Host support resume capability: PASS
Note:
Measured Value: 120.93 µs.
Resume Test Result: Pass
Figure 19. DUT Host Resumes
Measurement Name
Resume TIME
USB Limits
Status
Resume Test
120.9346 µs
3.000000 ms
Pass
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Test Condition
4.6
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DUT Host Test_J/K, SE0
A USB 2.0 Specification compliant controller is required for the controller to support mandatory tests
(where Test_SE0_NAK, Test_J, and Test_K are members of these tests). A digital multimeter is used to
measure the DC voltage level of D+ and D- data lines after placing the controller in one of the test modes
mentioned.
Test_SE0 places the controller in high-speed mode and keeps the controller from driving both D+ and Ddata lines.
Figure 20 displays the equipment setup used for DUT Host Test_J, Test_K, and Test_SE0
Fluke Digital
Multimeter
12.34
810 Qual
A
Flash Drive
B
INT
INT LED
Power
J92
B
J35
INIT Test Refresh
J91
Start With S6
Switch on the INIT
Position and Flip
to TEST Position
Prior to Measuring
J37
Known Good Device
Device SQ Test
J31
Host
DUT
J34
DUT
J310
DM6467
Segment of Tektronix
Compliance Test Fixture
(TDSUSBF)
Figure 20. Equipment Setup for Downstream Test J/K, SEO_NAK
4.6.1
Test_J/ Test_K
4.6.1.1
Test_J
When the D+ is driven high, the output voltage must be 400 mV ± 10% when terminated with precision 45
Ω resistor.
D+ data line DC voltage level: PASS
Note:
Measured value: 0.420 V
D- data line DC voltage level: PASS
Note:
4.6.1.2
Measured value: 0.004 V
Test_K
When the D- is driven high, the output voltage must be 400mV ± 10% when terminated with precision 45
Ω resistor.
D- data line DC voltage level: PASS
Note:
22
Measured value: 0.418 V
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D+ data line DC voltage level: PASS
Note:
4.6.2
Note: Measured value: 0.004 V
EL_9: Test_SE0
When either D+ and D- are not being driven, the output voltage must be 0V ± 10% when terminated with
precision 45 Ω resistors to ground.
D+ data line DC voltage level: PASS
Note:
Measured value: 0.002 V
D- data line DC voltage level: PASS
Note:
4.7
Measured value: 0.002 V
Legacy USB Compliance Testing
An eye diagram provides an intuitive view of jitter. It is a composite view of all the bit periods of a captured
waveform superimposed upon each other. Full-speed and low-speed signal quality tests are good enough
to determine that the embedded high-speed Host is capable of interacting with legacy devices that happen
to be full- or low-speed in nature.
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Test Condition
4.7.1
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Full-Speed Downstream Signal Quality Test
For a full-speed downstream signal quality test, it is necessary to cascade four self-powered high-speed
hubs and one self-powered full-speed hub with five meters of USB cables. The TDSUSB2F fixture is
connected to the embedded Host with a known good five meter USB cable. The self-powered full-speed
hub is directly attached (without using a short cable) to the TDSUSB2F fixture on the opposite side at the
Tier 1 position. The remaining high-speed hubs are cascaded with five meter cables. A known good
full-speed device, in this case a USB 1.1 Flash drive, is connected to the last high-speed hub via a five
meter USB cable. Figure 21 displays the equipment setup for a full-speed downstream signal quality test.
To capture the signal quality test, it is necessary to enumerate the attached USB 1.1 device. Since the
embedded Host is configured to operate at full-speed after the completion of the enumeration process, it
will generate a start of frame packet at the start of every frame. This packet is good enough to perform the
full-speed signal quality test.
Figure 21 displays the equipment setup for the full-speed downstream signal quality test.
Tektronix Oscillosope With
TDSUSB2 Application Running
Full-Speed Only Hub 1
J70
Host
DUT
J72
DM6467
B
A
(Self-Powered) Hub 2
Segment of Tektronix Compliance Test Fixture
(TDSUSBF)
(Self-Powered) Hub 5
(Self-Powered) Hub 3
Known Good Device
Full Speed
Flash Drive
(Self-Powered) Hub 4
Figure 21. Equipment Setup for Full-Speed Downstream Host Signal Quality Testing
24
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Figure 22 displays the screen capture of the waveform plot for the full-speed downstream signal quality
testing along with the result summary.
Figure 22. Full-Speed Downstream Signal Quality Test
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Test Condition
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Figure 23 displays the full-speed waveform plot as it is captured by the TDSUSB2F software.
4.0
3.0
D+ D- Signal, V
2.0
1.0
Ref Pt
0.0
CO Pt
D+
-1.0
DCMD
Diff
-2.0
-3.0
-4.0
0.0
0.5
1.0
1.5
2.0
Time (x 10
2.5
-6
3.0
3.5
)s
Figure 23. Waveform Plot
26
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Figure 24 displays the eye diagram for the full-speed downstream Host.
4.0
3.5
D+ D- Signals, V
3.0
2.5
2.0
1.5
0.1
0.5
0.0
-0.5
0.0
1.0
2.0
4.0
3.0
5.0
6.0
7.0
8.0
-8
Time (x 10 )s
Figure 24. Full-Speed Eye Diagram
Table 7 displays the detailed result for the downstream full-speed signal quality testing.
Table 7. Result Summary for Full-Speed Downstream Host Signal Quality (1)
Measurement
Name
Minimum
Eye diagram test
Signal rate
Crossover voltage
Maximum
Mean
pk-pk
Standard
Deviation
Status
RMS
Pop.
(2)
-
-
-
-
-
-
-
Pass
11.88213 Mbps
12.06564
Mbps
11.99616 Mbps
0.0000 bps
44.92540
kbps
11.99807 Mbps
30
Pass
1.480000 V
1.800000 V
1.668596 V
320.0000
mV
80.36886
mV
1.670423 V
18
EOP width
-
-
165.8684 ns
-
-
-
1
Pass
Consecutive jitter
-517.1158 ps
602.8842 ps
49.24211 ps
1.120000
ns
285.8456 ps
281.6490 ps
17
Pass
Paired JK jitter
-543.4921 ps
657.7778 ps
84.28571 ps
1.201270
ns
373.0448 ps
355.5083 ps
7
Pass
Paired KJ jitter
-480.0000 ps
426.6667 ps
0.0000 s
906.6667
ps
342.5207 ps
320.3988 ps
8
Pass
(1)
(2)
Additional Information:
• Consecutive jitter range: 53.98 ps to 33.51 ps RMS jitter 16.98 ps
• KJ paired jitter range: - 36.29 ps to 42.12 pas RMS jitter 13.10 ps
• JK paired jitter range: -37.51 ps to 27.63 ps RMS jitter 12.75 ps
Because the individual status of the measurements are Pass and performed on Tier 6 (as per USB-IF), the overall result for this
test is PASS.
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Test Condition
4.7.2
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Low-Speed Downstream Signal Quality Test
The best method to capture and analyze low-speed downstream signal quality is to capture both a
keep-alive (low-speed EOP) and a packet. The embedded Host is required to either generate a keep-alive
or send low-speed traffic once per frame whenever a low-speed device is directly attached to achieve this
LOOP GET DESCRIPTOR command is issued from the embedded Host; this is achieved by the Host
issuing the GET DESCRIPTOR Command continually. The scope is configured to trigger on the packets
transmitted by the Host. The triggering part is sometimes found to be hard depending upon the type of
scope and its bandwidth. High bandwidth scopes are not ideal for USB compliance testing.
To achieve a stable trigger, it was necessary on our setup to modify the trigger hold off parameter. For a
stable display of repetitive signals, trigger hold off allows you to match the trigger timing with
pseudo-random bit streams. It was necessary to play with this setting in order to get a stable trigger for the
TDSUSB2 software to measure the signal quality for low-speed downstream configuration. Even though
values larger than 1 ms would also work, it is advisable to obtain a hold off value less than one ms that
allows stable trigger on multiple packets within a frame.
Figure 25 displays the equipment setup for a low-speed downstream signal quality test.
Tektronix Oscillosope With
TDSUSB2 Application Running
P6245 Probes
J70
J72
DM6467
Known Good
Device (Mouse)
B
A
Host
DUT
Segment of Tektronix Compliance Test Fixture
(TDSUSBF)
Figure 25. Equipment Setup for Low-Speed Downstream Host Signal Quality Testing
28
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Figure 26 displays the screen capture of the GET DESCRIPTOR command packet that was used to
trigger on to measure the low-speed signal quality testing as well as the summary of the test result.
Figure 26. Low-Speed Downstream Signal Quality Test
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Test Condition
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Figure 27 displays the low-speed waveform plot as it is captured by the TDSUSB2F software.
4.0
3.0
D+ D- Signal, V
2.0
1.0
Ref Pt
0.0
CO Pt
D+
-1.0
DCMD
Diff
-2.0
-3.0
-4.0
-1.0
-0.5
0.0
0.5
1.0
Time (x 10
-5
1.5
2.0
2.5
)s
Figure 27. Low-Speed Waveform Plot
Figure 28 displays the eye diagram for low-speed downstream Host.
3.6
3.1
D+ D- Signals, V
2.6
2.1
1.6
1.1
0.6
0.1
0.0
1.0
2.0
3.0
4.0
5.0
6.0
-7
Time (x 10 )s
Figure 28. Low-Speed Eye Diagram
30
TMS320DM6467 Universal Serial Bus Downstream Host Compliance Testing
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References
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Table 8 displays the detailed result for the downstream low-speed signal quality testing.
Table 8. Result Summary for Low-Speed Downstream Host Signal Quality Test (1)
Measurement
Name
Minimum
Maximum
Mean
pk-pk
Standard
Deviation
RMS
Pop.
(2)
-
-
-
-
-
-
-
Pass
1.489520 Mbps
1.506821
Mbps
1.499897 Mbps
0.0000 bps
3.801528 kbps
1.500058 Mbps
30
Pass
1.493350 V
1.698076 V
1.609784 V
204.7254
mV
58.72229 mV
1.610808 v
23
Eye diagram test
Signal rate
Crossover voltage
-
-
1.336667 µs
-
-
-
1
Pass
Consecutive jitter
-3.772394 ns
21.20905 ns
117.4377 ps
5.893298
ns
1.339743 ns
1.314198 ns
22
Pass
Paired JK jitter
-2.460405 ns
2.316324 ns
-95.82838 ps
4.776729
ns
1.672752 ns
1.589802 ns
10
Pass
Paired KJ jitter
-2.311418 ns
4.188858 ns
229.0883 ps
6.500276
ns
2.103298 ns
2.008471 ns
10
Pass
Falling edge rate
21.55743 V/µs
24.22496 V/µs
23.03332 V/µs
2.667532
V/µs
746.5416 V/µs
23.04493 V/µs
25
Pass
Rising edge rate
17.62575 V/µs
20.77570 V/µs
19.16116 V/µs
3.149955
V/µs
718.6424 V/µs
19.17407 V/µs
24
Pass
EOP width
(1)
(2)
Additional Information:
• Rising Edge Rate: 19.16116 V/µs (Equivalent rise time = 137.78 ns)
• Falling Edge Rate: 23.03332 V/µs (Equivalent fall time = 114.62 ns)
Because the individual status of the measurements are Pass and performed on Tier 6 (as per USB-IF), the overall result for this
test is PASS.
Note:
5
Status
The actual Tier level for the low-speed device used (mouse) was Tier 1, as is shown on the
equipment setup diagram. During the time when the test was performed, the TDSUSB2
software has a bug that required the Tier number to be selected as Tier 6. Table 8 captures
the test device position as such. This is a display error and does not comprise the integrity of
the test.
References
•
Host High-Speed Electrical Test Procedure documentation issued by the USB Implementers Forum
(http://www.usb.org/home)
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