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Texas Instruments TMS30TCI6488 RAC Internal Precisions Application notes
Application Report
SPRAAM4 – May 2007
TMS320TCI6488 RAC Internal Precisions
Madeleine Saikaly ............................................................................................................................
ABSTRACT
This document provides processing decisions for the RAC internal sub-modules
contained in the TCI6488 DSP device.
1
2
3
4
Contents
RAC Overview ...................................................................................... 1
Front-End Interface ................................................................................ 2
Generic Correlation Co-Processors .............................................................. 2
Back-End Interface................................................................................ 11
List of Figures
1
2
3
1
RAC Overview ...................................................................................... 1
FEI Sample Packet Input Format ................................................................. 2
GCCP Architecture Overview ..................................................................... 3
RAC Overview
The receive accelerator (RAC) module in TCI6488 consists of three sub-modules:
• Front-end interface (FEI) that receives antenna data, repackages and delivers to GCCP0 and GCCP1
• Two generic correlator coprocessors (GCCP) that receive chip-rate antenna streams and provide the
DSP with de-spread symbols and correlation energy results.
• Back-end interface (BEI) with direct access to enhanced direct memory access (EDMA) switch fabric.
The results are put directly into memory for DSP use.
RAC block diagram is shown in Figure 1.
Antenna
Streams
GCCP0
FEI
BEI
GCCP1
FEI CFG
Registers
GCCP
Control
Correlation
Results
BEI CFG
Registers
Figure 1. RAC Overview
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Front-End Interface
2
Front-End Interface
The RAC front-end interface receives packets of antenna samples and the corresponding time stamp and
enables GCCP processing. Typically, packets come from the antenna interface through the EDMA. The
FEI has one input 64-bit data interface with the EDMA and two 128-bit output data interfaces, one with
each GCCP. In addition, the FEI supports access to data memories in each GCCP through one 64-bit
read/write bus.
Each FEI input sample packet contains eight chip periods worth of data. So with every 32-chip iteration
period, the RAC front-end receives at least four packets. The first packet carries samples from chip period
#0 to chip period #7, the second carries samples from chip period #8 to #15, the third carries samples
from chip period #16 to #23 and the last carries samples from chip period #24 to #31.
The antenna samples have an over-sampling factor of 2. The packet format is shown in Figure 2:
MSB
63
LSB
0
Stream 1
Stream 53
S0C3
S0C7
S1C3
S1C7
S0C3
S0C7
S1C3
S1C7
S0C3
S0C7
S1C3
S1C7
S0C2
S0C6
S1C2
S1C6
S0C2
S0C6
S1C2
S1C6
S0C2
S0C6
S1C2
S1C6
S0C1
S0C5
S1C1
S1C5
S0C1
S0C5
S1C1
S1C5
S0C1
S0C5
S1C1
S1C5
S0C0
S0C4
S1C0
S1C4
S0C0
S0C4
S1C0
S1C4
S0C0
S0C4
S1C0
S1C4
8 Bit I
LSB
0
192 Bus Cycles
MSB
15
8 Bit Q
64 Bit
Stream 0
C: Chip
S: Sample
(2x Over Sampled)
Figure 2. FEI Sample Packet Input Format
The FEI buffers the antenna samples, reformats them, and transfers them to the two GCCPs. Data output
from the FEI to the GCCP is still at an over-sampling factor of 2.
3
Generic Correlation Co-Processors
The GCCP data path contains:
• Correlator and adder trees
• Code generator
• Interpolators
• Amplitude and phase adjustors (also know as rotators)
• Coherent accumulators
• Energy translators (generating complex amplitude |x| or power |x|2)
• Non-coherent accumulators
GCCP is built around a task-based correlation engine. A task can be either:
• A finger symbol de-spreading task (FD-SYM)
• A finger delay tracking task (FD-FT)
• A finger power estimation task (FD-FPE)
• A path monitor task (PM)
• A preamble detection task (PD)
• A stream power estimation task (SPE)
Each type of task has specific parameters and uses the data-path differently.
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Here Only 4 Branches are Represented. The Data-Path Contains in Fact 8 Branches.
8 PN Multi/Adder
Trees
32x2x8
2 x 13
||
2 x 13
16
2 x 16
16
Output Queues
2
ROT/ II
MUX
Input Buffer OSF 2
Up to 77 Samples
(Early and Late)
1232 Bits
2 x 13
Interpolator
32
Samples
FrontEnd
I/F
BETI
Data
128
2x16
2 x 32
Scratch
Mem
Code
Gen
90
8x16
8x2x20
2x8
Ctrl
Scratch
Mem
Control Layer
Interrupts to BEII
Task/Macro
Task Param
Mems
Sequencer
TAM/TRM
CFG VBUS I/F
Figure 3. GCCP Architecture Overview
3.1
Preamble Detector
In PD mode, the GCCP is used to generate four coherent or eight non-coherent results per cycle. There
are three search modes:
• Full-chip search
• Half-chip search
• Quarter-chip search
Each search mode can be performed in two ways:
• Non-coherent stage active
• Non-coherent stage inactive
3.1.1
Input buffer
During each iteration period, the front-end interface writes up to 54 [streams] ×32 [chip periods] × 2
[samples per chip period] = 3456 samples to the GCCP input buffer. Each sample is a 16-bit complex
signed integer (I part takes the lowest eight bits and Q part takes the highest eight bits).
As shown in Figure 1 input buffer data width is 64-bit.
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Generic Correlation Co-Processors
3.1.2
Multiplexer
The multiplexer takes the 96-samples (each is 16-bit complex) from the IQ input buffer and generates the
77 samples (each is 16-bit complex IQ) needed for the adder trees.
3.1.3
Code Generator
The code generator in PD mode is different from the common block used in other modes; the short code
generator, OVSF code generator, and pilot bits demodulation are omitted. The long code generator is also
different to meet the RACH preamble/CPCH preamble long code specification.
Data going from the code generator to the adder trees is 32×2 bits wide.
3.1.4
Adder Tree/Correlator
The correlation engine consists of eight parallel independent correlators. During each cycle, each
correlator receives one input iteration packet and one code iteration packet. The input iteration packet
consists of 32 input chips. Each input chip is a complex signed integer (2×8 bits). The code iteration
packet consists of 32 code chips. Each code chip is a complex Boolean (2×1 bits) computed on-line by the
code generator.
The adder tree input consists of: 77 antenna samples (each is 16-bit complex IQ) from the multiplexer,
and a 32-bit I code and a 32-bit Q code from the code generator.
The output of the adder trees consists of 16 I symbols 13-bit wide and 16 Q symbols 13-bit wide going to
the interpolator.
3.1.5
Interpolator
In PD mode, the interpolation is not used for full-chip search or half-chip search; it is only used for
quarter-chip search.
Four branches of 4-tap complex (I, Q) interpolators are each used in parallel, in order to generate four
interpolated results per cycle. Two of these branches can be summed to create an 8-tap interpolator.
Each interpolator receives a packet of correlation results data input from the adder trees, and four sets of
filter coefficients, scalar signed 8-bit integer (4×4×8-bits) coefficients array. Each correlation result is a
complex (I, Q) signed integer (2×13 bits).
Each interpolator generates one interpolated result which is a complex (I, Q) signed integer (2×13 bits). In
total, they output eight complex 13-bit signed integers (8×2×13-bits) to the rotator when non-coherent
memory is enabled; otherwise they output four complex 13-bit signed integers (4×2×13-bits) to the rotator
when non-coherent memory is not active.
3.1.6
Rotator
In PD mode, the rotator is not used for full-chip search or half-chip search; it is only used for quarter-chip
search.
The rotator has eight branches of complex multipliers. Each branch data input consists of a 2×13-bit
complex (I, Q) signed integer from the interpolator and a 2×8-bit complex (I, Q) signed integer from the
phaser.
The output of each branch rotator is a 2×13-bit complex (I, Q) signed integer data going to coherent
memory.
3.1.7
Power Computation
Power computation is not used in the PD mode.
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3.1.8
Coherent Accumulation
In PD mode, all eight components of the coherent accumulation are active and up to eight results are
generated. These are dumped in parallel directly to the output queues if non-coherent accumulation is not
active, or to the amplitude sub-module if non-coherent accumulation is active.
The coherent accumulator receives a packet of rotated results from the rotator. The packet contains up to
eight rotated results. Each rotated result is a 2×13-bit complex (I, Q) signed integer.
The coherent accumulator generates a packet of accumulated results. The packet contains up to eight
accumulated results. Each accumulated result is a 2×16-bit complex (I, Q) signed integer. It can also be
reduced to a 2×8-bit complex (I, Q) signed integer when written into the output queues.
3.1.9
Amplitude Computation
The amplitude sub-module is bypassed when non-coherent accumulation is not-active.
When non-coherent accumulation is active, input to the amplitude sub-module is the eight results from the
coherent accumulation. Each accumulated result is a 2×16-bit complex (I, Q) signed integer.
Output from the amplitude sub-module is the eight amplitude results that are fed to the non-coherent
accumulator. Each amplitude result is a 16-bit scalar unsigned integer.
3.1.10
Non-coherent Accumulation
Up to eight 16-bit scalar unsigned integer amplitude results from the amplitude computation sub-module
are fed to the non-coherent accumulator.
When a non-coherent duration is finished, final results are dumped into the output queues. Each output
non-coherent accumulation result is a 16-bit scalar unsigned integer.
3.1.11
Output Queues
Correlation results, either from coherent accumulation (2×8-bit complex (I, Q) signed integer) or
non-coherent accumulation (16-bit scalar unsigned integer) stages are fed into the output queues.
The output data bus from the queues to the BEI is 128-bit wide.
3.1.12
Mean Value in Post-Processing
This sub-module is in the RAC back-end interface. The mean value is performing the sum of outgoing
offsets results for PD task.
Input is the amplitude 16-bit scalar unsigned integer array.
The output mean value is a 32-bit scalar unsigned integer.
3.2
Path Monitor
In PM mode, the GCCP is used to generate four coherent or eight non-coherent results per cycle. There
are three search modes:
• Full-chip search
• Half-chip search
• Quarter-chip search
Each search mode can be performed in two ways:
• Non-coherent stage active
• Non-coherent stage inactive
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3.2.1
Input Buffer
During each iteration period, the FEI writes up to 54 [streams] × 32 [chip periods] × 2 [samples per chip
period] = 3456 samples to the GCCP input buffer. Each sample is a 16-bit complex signed integer (the I
part takes the lowest eight bits and the Q part takes the highest eight bits).
The input buffer data width is 64-bit, as shown in Figure 1.
3.2.2
Multiplexer
The multiplexer takes the 96 samples (each is 16-bit complex) from the IQ input buffer and generates the
77 samples (each is 16-bit complex IQ) needed for the adder trees.
3.2.3
Code Generator
In
•
•
•
•
PM mode, the following code generator sub-blocks are active:
Long code generator generates gold code scrambling codes
Short code generator generates gold code scrambling codes
OVSF code generator generates OVSF channelisation codes
Pilot bits demodulation uncovers the pilot bit modulation on DPCC
Data going from the code generator to the adder trees is 32×2 bits wide.
3.2.4
Adder Tree/Correlator
The correlation engine consists of eight parallel independent correlators. During each cycle, each
correlator receives one input iteration packet and one code iteration packet. The input iteration packet
consists of 32 input chips. Each input chip is a complex signed integer (2×8 bits). The code iteration
packet consists of 32 code chips. Each code chip is a complex Boolean (2×1 bits) computed on-line by the
code generator.
The adder tree input consists of: 77 antenna samples (each is 16-bit complex IQ) from the multiplexer,
and a 32-bit I code and a 32-bit Q code from the code generator.
The output of the adder trees consists of 16 I symbols 13-bit wide and 16 Q symbols 13-bit wide going to
the interpolator.
3.2.5
Interpolator
In PM mode, the interpolation is not used for full-chip search or half-chip search; it is only used for
quarter-chip search.
Four branches of 4-tap complex (I, Q) interpolators are each used in parallel in order to generate four
interpolated results per cycle. Two of these branches can be summed to create an 8-tap interpolator.
Each interpolator receives a packet of correlation results. The packet contains four results. Each
correlation results is a complex (I, Q) signed integer (2×13 bits).
Each interpolator generates one interpolated result. It is a complex (I, Q) signed integer (2x13 bits).
In total, the Interpolators receive 16×2×13-bits data input from the adder trees and four sets of filter
coefficients scalar signed 8-bit integer (4×4×8-bits) coefficients array. They output eight complex 13-bit
signed integers (8×2×13-bits) to the rotator when non-coherent memory is enabled, otherwise they output
four complex 13-bit signed integers (4×2×13-bits) to the rotator when non-coherent memory is not-active.
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3.2.6
Rotator
In PM mode all eight rotators are active.
The rotator has eight branches of complex multipliers. Each branch data input consists of 2×13-bit
complex (I, Q) signed integer from Interpolation and 2×8-bit complex (I, Q) signed integer from the phaser.
The output of each branch rotator is 2×13-bit complex (I, Q) signed integer data going to coherent
memory.
3.2.7
Power Computation
Power computation is not used in PM mode.
3.2.8
Coherent Accumulation
In PM mode, all eight components of the coherent accumulation are active and up to eight results are
generated. These are dumped in parallel directly to the output queues if non-coherent accumulation is
not-active or to the amplitude sub-module if non-coherent accumulation is active.
The coherent accumulator receives a packet of rotated results from the rotator. The packet contains up to
eight rotated results. Each rotated result is a 2×13-bit complex (I, Q) signed integer.
The coherent accumulator generates a packet of accumulated results. The packet contains up to eight
accumulated results. Each accumulated result is a 2×16-bit complex (I, Q) signed integer. It can also be
reduced to a 2×8-bit complex (I, Q) signed integer when written into the output queues.
3.2.9
Amplitude Computation
The amplitude sub-module is bypassed when non-coherent accumulation is not-active.
When non-coherent accumulation is active, input to the amplitude sub-module is the eight results from the
coherent accumulation. Each accumulated result is a 2×16-bit complex (I, Q) signed integer.
Output from the amplitude sub-module consists of eight amplitude results that are fed to the non-coherent
accumulator. Each amplitude result is a 16-bit scalar unsigned integer.
3.2.10
Non-Coherent Accumulation
Up to eight 16-bit scalar unsigned integer amplitude results from the amplitude computation sub-module
are fed to the non-coherent accumulator.
When a non-coherent duration is finished, final results are dumped into the output queues. Each output
non-coherent accumulation result is a 16-bit scalar unsigned integer.
3.2.11
Output Queues
Correlation results either from coherent accumulation (2×8-bit complex (I, Q) signed integer) or
non-coherent accumulation (16-bit scalar unsigned integer) stages are fed into the output queues.
The output data bus from the queues to the BEI is 128-bit wide.
3.2.12
Mean Value in Post-Processing
This sub-module is in the RAC back-end interface. The mean value is performing the sum of outgoing
offsets results for the PM task.
Input is the amplitude 16-bit scalar unsigned integer array.
The output mean value is a 32-bit scalar unsigned integer.
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3.3
Finger Despreader
The finger despreader (FD) can use the GCCP in two ways, depending on the spreading factor of the
channel:
• For a spreading factor ≥ 32, only up to one symbol is generated per cycle and per iteration period
• For a spreading factor ≤ 16, up to four symbols are generated per cycle
3.3.1
Input Buffer
During each iteration period, the FEI writes up to 54 [streams] × 32 [chip periods] × 2 [samples per chip
period] = 3456 samples to the GCCP input buffer. Each sample is a 16-bit complex signed integer (I part
takes the lowest eight bits and Q part takes the highest eight bits).
As shown in Figure 1 Input buffer data width is 64-bit.
3.3.2
Multiplexer
The muliplexer takes the 96 samples (each is 16-bit complex) from the IQ input buffer and generates the
77 samples (each is 16-bit complex IQ) needed for the adder trees.
3.3.3
Code Generator
In
•
•
•
•
FD mode, the following code generator sub-blocks are active:
Long code generator generates gold code scrambling codes
Short code generator generates gold code scrambling codes
OVSF code generator generates OVSF channelisation codes
Pilot bits demodulation uncovers the pilot bit modulation on DPCCH
Data going from the code generator to the adder trees is 32×2 bits wide.
3.3.4
Adder Tree/Correlator
The correlation engine consists of eight parallel independent correlators. During each cycle, the
correlators receive one input iteration packet and one code iteration packet. The input iteration packet
consists of 32 input chips. Each input chip is a complex signed integer (2×8 bits). The code iteration
packet consists of 32 code chips. Each code chip is a complex Boolean (2×1 bits) computed on-line by the
code generator.
The adder tree input consists of: 77 antenna samples (each is 16-bit complex IQ) from the multiplexer, a
32-bit I code and a 32-bit Q code from the code generator.
The output of the adder trees consists of 16 I symbols 13-bit wide and 16 Q symbols 13-bit wide going to
the interpolator.
3.3.5
Interpolator
In FD mode, for a spreading factor ≥ 32, only one of the 4-tap interpolators is used. For a spreading factor
≤ 16, the four interpolators are active.
Up to four branches of 4-tap complex (I, Q) interpolators each are used in parallel in order to generate up
to four interpolated results per cycle. Two of these branches can be summed to create an 8-tap
interpolator. Each of these interpolators can be bypassed.
Each interpolator receives a packet of correlation results. The packet contains four results. Each
correlation results is a complex (I, Q) signed integer (2×13 bits).
Each interpolator generates one interpolated result. It is a complex (I, Q) signed integer (2×13 bits).
In total, the interpolators receive 16×2×13-bits data input from the adder trees and four sets of filter
coefficients (for 4x oversampling case in FD mode) scalar signed 8-bit integer (4×4×8-bit range)
coefficients array. They output eight complex 13-bit signed integers (8×2×13-bits range) to the rotator.
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3.3.6
Rotator
In FD mode, for a spreading factor ≥ 32, only one rotator is active. For a spreading factor ≤ 16, the four
interpolators are connected to four active rotators.
Each rotator branch data input consists of 2×13-bit complex (I, Q) signed integer from the interpolator and
2×8-bit complex (I, Q) signed integer from the phasor.
The output of each branch rotator is a 2×13-bit complex (I, Q) signed integer data going to coherent
memory.
3.3.7
Power Computation
The power computation sub-module in SPE, FPE16, and FPE32 shares its multipliers with the rotator. The
power computation sub-module receives a packet of correlation results. Correlation results are computed
by the interpolators or by the adder trees.
The input packet contains up to four correlation results. Each correlation result is a 2×13-bit complex (I, Q)
signed integer.
The power computation sub-module generates one power result. A power result is a scalar 16-bit
unsigned integer.
3.3.8
Coherent Accumulation
In FD mode, the coherent accumulation component is used only when the spreading factor ≥ 64.
The coherent accumulator receives a packet of rotated results from the rotator. The packet contains up to
eight rotated results. Each rotated result is a 2×13-bit complex (I, Q) signed integer.
The coherent accumulator generates a packet of accumulated results. The packet contains up to eight
accumulated results. Each accumulated result is a 2×16-bit complex (I, Q) signed integer. It can also be
reduced to a 2×8-bit complex (I, Q) signed integer when written into the output queues.
In FD mode, the symbols are generated at a very high rate and the payload in bytes is minimal. In order to
optimize the transfers, symbols are pre-packed in the coherent scratch. This packing mechanism is done
for data symbols only. FD control symbols (with SF=256) are not pre-packed, so they are written into the
output queues as soon as they are produced.
The packed FD data symbols are filled in the coherent scratch memory to look like a 128-bit word at the
output queue input. In 8-bit mode, the 128-bit word contains eight symbols. In 16-bit mode, it contains four
symbols.
3.3.9
Amplitude Computation
Amplitude computation is not used in FD mode.
3.3.10
Non-Coherent Accumulation
Non-coherent accumulation is not used in FD mode.
3.3.11
Output Queues
Correlation results from coherent accumulation (2×8-bit complex (I, Q) signed integer) stage are fed into
the output queues.
Output data bus from the queues to the back-end interface (BEI) is 128-bit wide.
3.4
Finger Tracking
In finger tracking (FT) mode, the GCCP is used to generate amplitude results on DPCCH fingers. The
spreading factor is set to 256. FT can use GCCP in two ways: non-coherent stage is active or not.
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3.4.1
Input Buffer
During each iteration period, the front-end interface writes up to 54 [streams] × 32 [chip periods] × 2
[samples per chip period] = 3456 samples to the GCCP input buffer. Each sample is a 16-bit complex
signed integer (I part takes the lowest eight bits and Q part takes the highest eight bits).
As shown in Figure 1 Input buffer data width is 64-bit.
3.4.2
Multiplexer
It takes the 96 samples (each is 16-bit complex) from the IQ input buffer and generates the 77 samples
(each is 16-bit complex IQ) needed for the adder trees.
3.4.3
Code Generator
In FT mode, only the long code generator sub-block is active. The short code generator, OVSF code
generator, and pilot bits demodulation are omitted.
Data going from the code generator to the adder trees is 32-bit I code and 32-bit Q code.
3.4.4
Adder Tree/Correlator
In FT mode, up to all eight correlators are used to feed three 4-tap interpolators. The correlation engine
consists of eight parallel independent correlators. During each cycle, each correlator receives one input
iteration packet and one code iteration packet. The input iteration packet consists of 32 input chips. Each
input chip is a complex signed integer (2×8 bits). The code iteration packet consists of 32 code chips.
Each code chip is a complex Boolean (2×1 bits) computed on-line by the code generator.
The adder tree input consists of: 77 antenna samples (each is 16-bit complex IQ) from the multiplexer, a
32-bit I code and a 32-bit Q code from the code generator.
The output of the adder trees consists of 16 I symbols 13-bit wide and 16 Q symbols 13-bit wide going to
the interpolator.
3.4.5
Interpolator
In FT mode, three branches of 4-tap complex (I, Q) interpolators each are used in parallel in order to
generate three interpolated results per cycle.
Each interpolator receives a packet of correlation results. The packet contains four results. Each
correlation results is a complex (I, Q) signed integer (2×13 bits). It also receives three sets of filter
coefficients scalar signed 4×8-bit integers.
Each interpolator generates one interpolated result to the rotator. It is a complex (I, Q) signed integer
(2×13 bits).
3.4.6
Rotator
In FT mode, three rotators are active in order to generate early-on time-late (EOL) measurements on
parallel.
Each rotator branch data input consists of 2×13-bit complex (I, Q) signed integer from interpolator and
2×8-bit complex (I, Q) signed integer from the phasor.
The output of each branch rotator is 2×13-bit complex (I, Q) signed integer data going to coherent
memory.
3.4.7
Power Computation
Power computation is not used in FT mode.
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Back-End Interface
3.4.8
Coherent Accumulation
In FT mode, only three coherent accumulators are used to accumulate over several symbols.
The coherent accumulator receives a packet of rotated results from the rotator. The packet contains three
rotated results. Each rotated result is a 2×13-bit complex (I, Q) signed integer.
The coherent accumulator generates a packet of accumulated results. The packet contains three
accumulated results. Each accumulated result is a 2×16-bit complex (I, Q) signed integer. It can also be
reduced to a 2×8-bit complex (I, Q) signed integer when written into the output queues.
If the non-coherent step is not used, once the coherent accumulation is finished, it dumps results directly
to the output queues.
3.4.9
Amplitude Computation
The amplitude sub-module is bypassed when non-coherent accumulation is not-active. When the
non-coherent stage is used in FT mode, results from coherent accumulation stage are dumped to three
components of the amplitude sub-module and converted to amplitude.
Input to the amplitude sub-module is the three results from the coherent accumulation. Each accumulated
result is a 2×16-bit complex (I, Q) signed integer.
Output from the amplitude sub-module is three amplitude results that are fed to the non-coherent
accumulator. Each amplitude result is a 16-bit scalar unsigned integer.
3.4.10
Non-Coherent Accumulation
If the non-coherent stage is used in FT mode, the amplitude results are accumulated in three of the
non-coherent accumulators.
Three 16-bit scalar unsigned integer amplitude results from the amplitude computation sub-module are fed
to the non-coherent accumulator.
When a non-coherent duration is finished, three final results are dumped into the output queues. Each
output non-coherent accumulation result is a 16-bit scalar unsigned integer.
3.4.11
Output Queues
Correlation results either from coherent accumulation (2×8-bit complex (I, Q) signed integer) or
non-coherent accumulation (16-bit scalar unsigned integer) stages are fed into the output queues.
The output data bus from the queues to the BEI is 128-bit wide.
4
Back-End Interface
The primary mission of the back-end sub-module is to push correlation results coming from GCCP data
queues to any memory destination inside/outside the DSP.
The BEI is connected to both GCCPs through the output queues. It receives new correlation results with
information needed to compute their destination address.
The BEI transfers data by using its own 128-bit master VBUS interface. This interface is connected to
memory through the EDMA switch fabric.
4.1
Mean Value in Post-Processing
This sub-module is in the RAC back-end. The mean value is performing the sum of the outgoing offsets
results for PM and PD tasks.
Input is the amplitude 16-bit scalar unsigned integer array.
The output mean value is a 32-bit scalar unsigned integer.
SPRAAM4 – May 2007
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TMS320TCI6488 RAC Internal Precisions
11
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