Texas Instruments | TMS320C54CST Bootloader (Rev. A) | Application notes | Texas Instruments TMS320C54CST Bootloader (Rev. A) Application notes

Texas Instruments TMS320C54CST Bootloader (Rev. A) Application notes
Application Report
SPRA853A - September 2003
TMS320C54CST Bootloader Technical Reference
Aaron Aboagye
C5000 Applications
ABSTRACT
This document describes the features and operation of the TMS320C54CST bootloader. The
contents of the on-chip read-only memory (ROM) also are discussed.
Contents
1
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
1.1 Bootloader Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
1.2 On-Chip ROM Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
2
Bootloader Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
2.1 Boot Mode Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
2.2 Boot Mode Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
2.2.1 HPI Boot Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
2.2.2 Serial EEPROM Boot Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
2.2.3 Parallel Boot Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
2.2.4 Standard Serial Boot Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
2.2.5 I/O Boot Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
3
Building the Boot Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
4
Reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
List of Figures
Figure 1. Bootloader Mode Selection Process . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Figure 2. Basic Data Width Selection and Data Transfer Process . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Figure 3. HPI Boot Mode Flow Chart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Figure 4. McBSP1 to EEPROM Interface for Serial EEPROM Boot Mode . . . . . . . . . . . . . . . . . . . . . . . 13
Figure 5. Example Read Access for Serial EEPROM Boot Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Figure 6. Parallel Boot Mode Process . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Figure 7. Source Program Data Stream for Parallel Boot in 8-, 16-Bit-Word Mode . . . . . . . . . . . . . . . . 16
Figure 8. Timing Conditions for Serial Port Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Figure 9. Standard Serial Boot From McBSP1 (8-Bit) After BRINT1 = 1 . . . . . . . . . . . . . . . . . . . . . . . . . 18
Figure 10. Standard Serial Boot From McBSP0 (16-Bit) After BRINT0 = 1 . . . . . . . . . . . . . . . . . . . . . . . 18
Figure 11. Source Program Data Stream for 8-, 16-Bit McBSP Boot in Standard Mode . . . . . . . . . . . . 19
Figure 12. I/O Boot Mode Handshake Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Figure 13. I/O Boot Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Figure 14. Example Command File for Hex Conversion Utility . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Trademarks are the property of their respective owners.
1
SPRA853A
List of Tables
Table 1. TMS320C54CST On-Chip ROM Program Space . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Table 2. General Structure of Source Program Data Stream in 16-Bit Mode . . . . . . . . . . . . . . . . . . . . . . 9
Table 3. General Structure of Source Program Data Stream in 8-Bit Mode
1
. . . . . . . . . . . . . . . . . . . . . 10
Introduction
This section describes the purpose and features of the TMS320C54CST (hereafter referred to
as C54CST) digital signal processor (DSP) bootloader. It also discusses the other contents of
the device on-chip ROM and identifies where all of this information is located within that
memory.
1.1
Bootloader Features
The TMS320C54CST bootloader is used to transfer code from an external source into internal or
external program memory following powerup. This allows code to reside in slow non-volatile
memory externally, and be transferred to high-speed memory to be executed. This eliminates
the need for mask programming the C54CST internal ROM, which may not be cost effective in
some applications.
The bootloader provides a variety of ways to download code to accommodate different system
requirements. This includes multiple types of both parallel bus and serial port boot modes,
universal asynchronous receiver/transmitter (UART) boot mode, bootloading through the host
port interface (HPI), and a special C54CST chipset boot mode. Bootloading in both 8-bit byte
and 16-bit word modes are supported.
The bootloader uses various control signals including interrupts, BIO, and XF to determine which
boot mode to use. The boot mode selection process, as well as the specifics of bootloader
operation, are described in detail in section 2 of this document.
1.2
On-Chip ROM Description
On the C54CST device, the on-chip ROM contains several factory-programmed sections
including the bootloader itself and other features. The sections contained in the ROM are:
•
•
Bootloader program (described in this document)
•
Factory test code (reserved code used by TI for testing the device)
•
Interrupt vector table (code that allows indirect vectoring of interrupts)
C54CST algorithms and framework
The C54CST on-chip ROM memory map is shown in Table 1. The ROM is 128K words in size
and is located at the 0x006000−0x03D000 address range in program space when the MP/MC
input pin is low.
2
TMS320C54CST Bootloader Technical Reference
SPRA853A
Table 1. TMS320C54CST On-Chip ROM Program Space
Starting Address
Contents
000_6000
CST code
000_B200
DSP/BIOS image
000_BB20
Bootloader code
000_C000
CST code
000_FF00
Reserved for factory test code
000_FF80
Vector table
001_8000
CST code
002_8000
CST code
003_8000
CST code
2
Bootloader Operation
2.1
Boot Mode Selection
The bootloader program located in the C54CST on-chip ROM is executed following reset when
the device is in microcomputer mode (MP/MC = 0).
The function of the bootloader is to transfer user code from an external source to the program
memory at power up. The bootloader sets up the central processing unit (CPU) status registers
before initiating the boot load. Interrupts are globally disabled (INTM = 1) and the internal
dual-access RAMs are mapped into the program/data space (OVLY = 1). Seven wait states are
initialized for the entire program and data spaces. The bootloader does not change the reset
condition of the bank switching control register (BSCR) prior to loading a boot table.
To accommodate different system requirements, the C54CST offers a variety of different boot
modes. The following is a list of the different boot modes implemented by the bootloader, and a
summary of their functional operation:
•
C54CST Chipset Boot Mode
This mode is used to start the C54CST device in CST chipset mode. Upon detection of this
mode, the bootloader automatically passes control to the C54CST chipset application. No
code is copied in this mode.
•
Host Port Interface (HPI) Boot Mode
The code to be executed is loaded into on-chip memory by an external host processor via
the host port interface. Code execution begins once the execution address loading is
completed.
•
Parallel Boot Modes (8-bit and 16-bit supported)
The bootloader reads the boot table from data space via the external parallel interface bus.
The boot table contains the code sections to be loaded, the destination locations for each of
the code sections, the execution address once loading is completed, and other configuration
information.
TMS320C54CST Bootloader Technical Reference
3
SPRA853A
•
Standard Serial Port Boot Modes (8-bit and 16-bit supported)
The bootloader receives the boot table from one of the multichannel buffered serial ports
(McBSPs) operating in standard mode, and loads the code according to the information
specified in the boot table. McBSP0 supports 16-bit serial receive mode. McBSP1 supports
8-bit serial receive mode.
•
UART Boot Mode (8-bit supported)
The bootloader receives the boot table from the on-chip UART and loads the code according
to the information specified in the boot table. Below are the UART settings used:
−
115200 bits per second
−
8 data bits
−
No parity bit
−
1 stop bit
−
No flow control
•
8-Bit Serial Electrically Erasable Programmable Read-Only Memory (EEPROM)
Boot Mode
The bootloader receives the boot table from a serial EEPROM connected to McBSP1
operating in clockstop mode, and loads the code according to the information specified in the
boot table.
•
Input/Output (I/O) Boot Mode (8-bit and 16-bit supported)
The bootloader reads the boot table from I/O port 0h via the external parallel interface bus
employing an asynchronous handshake protocol using the XF and BIO pins. This allows
data transfers to be performed at a rate dictated by the external device.
The bootloader also offers the following additional features:
−
Reprogrammable software wait state register
In the parallel and I/O boot modes, the bootloader reconfigures the software wait state
register based on a value read from the boot table during the bootload.
−
Reprogrammable bank switching control register
In the parallel and I/O boot modes, the bootloader reconfigures the bank switching
control register based on a value read from the boot table during the bootload.
−
Multiple-section boot
The C54CST bootloader is capable of loading multiple separate code sections. These
sections are not required to occupy a continuous memory space as in some previous
TMS320C54x bootloaders.
The details of all these boot modes are described in the following sections.
Once the bootloader is initiated, it performs a series of checking operations to determine which
boot mode to use. The bootloader first checks for conditions that indicate it should perform an
HPI boot. If the conditions are not met, it goes to the next mode and continues until it finds a
mode which is selected. The flowchart shown in Figure 1 illustrates the process the bootloader
uses to determine the desired boot mode.
TMS320C54x is a trademark of Texas Instruments.
4
TMS320C54CST Bootloader Technical Reference
SPRA853A
Reset
INT1
flag
active
?
No
Yes
Branch to CST
chipset entry point
Yes
McBSP1
?
Valid
keyword
?
No
No
HPI boot
INT2
flag
active
?
Valid
entry
point
?
Yes
Yes
No
No
Yes
McBSP0
?
Valid
keyword
?
No
No
Branch to
entry point
INT3
flag
active
?
Serial EEPROM
boot
Yes
Valid
serial EEPROM
boot
?
No
No
UART
byte
received
?
Yes
No
Is
received
byte 0x08
?
Yes
Yes
Transfer
data
Standard serial
port boot
No
Yes
Yes
Transfer
data
Is
received
byte ‘A’
or ‘a’
?
No
Yes
Read next byte
Read next byte
Is
received
byte 0xAA
?
Is
received
byte ‘T’
or ‘t’
?
Load code
No
Parallel boot
Read source address
from I/O space FFFFh
Valid
parallel
boot
?
No
UART
boot/
UART
CST
chipset
mode
Yes
Yes
Yes
Transfer data
Branch to CST
chipset entry
point
Read source address
from data space FFFFh
Valid
parallel
boot
?
No
No
IO boot
BIO low
?
Yes
Yes
Transfer data
No
Valid
keyword
?
Yes
Transfer
data
No
HPI boot (2nd check)
Initialize serial port
Valid
entry
point
?
No
Set XF low
Yes
Branch to
entry point
Initialize UART
Restart
Restart
Figure 1. Bootloader Mode Selection Process
The bootloader checks each of the boot modes in the following sequence until indications for a
valid boot mode are found:
1. Client-side telephony (CST) chipset mode
2. Host port interface (HPI) boot mode
3. Serial EEPROM boot mode (8-bit)
4. Parallel boot mode
5. Standard serial boot mode via McBSP1 (8-bit)
6. Standard serial boot mode via McBSP0 (16-bit)
TMS320C54CST Bootloader Technical Reference
5
SPRA853A
7. UART boot mode/UART CST chipset mode
8. I/O boot mode
Detailed description of the operation of each of these boot modes can be found in section 2.2.
CST chipset mode
The first boot mode tested is the CST chipset boot mode. 46 CPU cycles after device reset, the
bootloader checks whether the INT1 pin is active. If it is, control is passed to the CST chipset
application. If not, the bootloader moves on to check other boot modes. This is a one-time
check, and the user can subsequently enter CST chipset mode through the UART CST chipset
mode selection (see item 7 listed above).
Host port interface (HPI) boot mode
The next boot mode tested is the HPI boot mode. Unlike some other C54x HPI boot modes,
the C54CST HPI boot mode does not require the setting of the interrupt 2 (INT2) flag for
selection. If INT2 is not active, the bootloader periodically checks various boot sources, including
the HPI boot, until a boot condition is detected. Alternatively, the INT2 flag can be used to force
the bootloader to ignore all boot sources other than HPI. If INT2 is found to be active, the
bootloader assumes that the code will be loaded into on-chip RAM by an external host. The
bootloader waits, polling address 007Fh of the on-chip data RAM, while the host loads its
on-chip random-access memory (RAM). Once it is finished loading the on-chip RAM, the host
writes the PC value into data memory location 007Fh, specifying the address of the entry point.
Note that the PC of the entry point must be a non-zero number. When the bootloader
detects that the entry point has been programmed, the bootloader branches to the specified
start address. If the INT2 flag is not active, the bootloader proceeds to check the next boot
mode.
Serial EEPROM boot mode (8-bit)
The serial EEPROM boot mode is checked using the INT3 flag. If INT3 is found to be active, the
bootloader assumes that the boot table is located in an 8-bit serial EEPROM connected to
McBSP1. The bootloader reads the data value stored at address 0 of the EEPROM. If the data
read contains a valid keyword for the beginning of the boot table, the bootloader proceeds to
load the remainder of the boot table from the serial EEPROM. If the INT3 flag is not active, or no
valid keyword is found, the bootloader proceeds to check the next boot mode.
Parallel boot mode
The next boot modes tested are the parallel boot modes. The boot table is located in data space
and can be located anywhere within the 64k data space address range. The bootloader
determines the location of the boot table by first reading address 0FFFFh in I/O space. The
bootloader uses the value read from I/O space as the address of the boot table in data space.
The beginning of the boot table always contains a keyword that indicates whether 8-bit or 16-bit
boot mode is desired. The valid keyword for 8-bit boot mode is 08AAh. The valid keyword for
16-bit boot mode is 10AAh. If a valid keyword for the boot table is not found, the bootloader
reads address 0FFFFh in data space for a boot table address and checks for a valid keyword at
that location. When a valid keyword is found, the bootloader continues to read the remainder of
the boot table and loads and executes the application code. If no valid keyword is found, the
bootloader proceeds to check the serial boot modes.
C54x is a trademark of Texas Instruments.
6
TMS320C54CST Bootloader Technical Reference
SPRA853A
Standard serial boot mode via McBSP1 (8-bit/16-bit)
Prior to testing for serial or I/O boot modes, the bootloader drives the XF output on the device
low to indicate that it is ready to receive data. Upon this event, a serial host device may begin to
send the boot table information via McBSP0 or McBSP1. When a word is received on one of the
McBSPs, a serial port interrupt flag will be generated in the C54CST. The bootloader uses these
interrupt flags as indication of which McBSP to use for boot load. The C54CST reads the data
received on the McBSP, and if a valid keyword is found, the boot proceeds with the same serial
port and no other boot modes are tested. If neither McBSP responds with received data, the
bootloader proceeds to check the UART boot mode.
UART boot mode/UART CST chipset mode
The UART boot mode/UART CST chipset mode is activated on detection of a received character
in the UART. The first two characters received will determine which type of UART operation is to
be performed. If the first two characters are 0x08 0xAA, then the UART boot mode operation will
be performed to boot code from a host processor. If not, a check is performed to determine
whether the characters are “A T” (not case sensitive). If they are, control of the device is passed
to the CST chipset mode software. However, if the received bytes are in error, control returns to
the bootloader to continue checking for a boot mode.
I/O boot mode
In I/O boot mode, the host device makes a request to send data by driving the BIO input to the
C54CST-low. The bootloader recognizes this request and reads data from I/O port 0h. If the data
read contains a valid keyword for the beginning of the boot table, the C54CST and the host
proceed to load the remainder of the boot table using a handshaking scheme as described in
section 2.2.5.
If a valid boot mode is not found after checking all of the possible boot modes, the bootloader
restarts and continues to recheck each of the boot modes, starting with the standard serial port
boot modes.
The flow chart shown in Figure 2 illustrates the basic process that the bootloader uses to
determine whether 8- or 16-bit data has been selected, transfers the data, and begins program
execution. This process occurs after the bootloader finds what it determines to be a valid boot
mode selected. When using the 8-bit boot modes, bytes must be ordered by most-sigificant byte
first. For parallel 8-bit modes, the bytes must be presented on the lower-order eight bits of the
data bus. Note that the exact sequence used for 8- and 16-bit mode processing differs
somewhat, depending on which specific boot mode is selected. The particular sequence used by
each boot mode is shown in section 2.2, which describes the different boot modes in detail.
TMS320C54CST Bootloader Technical Reference
7
SPRA853A
No
No
W = 10AAh
?
W = xx08h
?
Yes
Yes
16-bit boot mode
Read second word (W)
Load R−1 words to
reinitialize the registers.
In 8-bit mode, a read is
required for each byte of
the word.
W = xxAAh
?
Check other
boot modes
No
Yes
Load XPC of entry point
8-bit boot mode
Load entry point
Load section size R
Yes
R=0
?
No
Branch to entry point
Start program
execution
Load XPC and
destination address
Transfer R words of data
from source to destination
Figure 2. Basic Data Width Selection and Data Transfer Process
Table 2 and Table 3 show the general structure of the boot table that is loaded for the boot
modes. This structure is the same for all the modes, except HPI, in which code is loaded directly
into memory, and therefore does not require the boot table. The first R−1 words include the
keyword, the words used to initialize the registers (the number of which depends on the boot
mode), and the entry-point address of the application code. For each load section that follows,
there is a word that indicates the block size, followed by two words that indicate the 23-bit load
address for the block. When the bootloader encounters a block size of zero (0000h), it branches
to the entry address and begins execution of the application.
Note that these tables are only included to show the basic structure of the boot table. The exact
structure of the boot table varies depending on the boot mode selected. For specific information
about the structure used by each of the boot modes, refer to the section 2.2, which describes the
different boot modes in detail.
8
TMS320C54CST Bootloader Technical Reference
SPRA853A
Table 2. General Structure of Source Program Data Stream in 16-Bit Mode
Word
Contents
1
10AAh (memory width of the source program is 16 bits)
2
Value to set in the register (applied to the specified boot mode)
.
.
.
Value to set in the register
.
XPC value of the entry point (least-significant 7 bits are used as A23−A16)
.
Entry point (PC) (16 bits are used as A15−A0)
R
Block size of the first section to load.
R+1
XPC value of the destination address of the first section (7 bits)
.
Destination address (PC) of the first section (16 bits)
.
First word of the first section of the source program
.
.
.
Last word of the first section of the source program
.
Block size of the second section to load
.
XPC value of the destination address of the second section (7 bits)
.
Destination address (PC) of the second section (16 bits)
First word of the second section of the source program
.
.
.
Last word of the second section of the source program
.
.
.
.
.
Block size of the last section to load
.
XPC value of the destination address of the last section (7 bits)
.
Destination address (PC) of the last section (16 bits)
.
First word of the last section of the source program
.
.
.
Last word of the last section of the source program
n
0000h—indicates the end of source program
TMS320C54CST Bootloader Technical Reference
9
SPRA853A
Table 3. General Structure of Source Program Data Stream in 8-Bit Mode
Byte
10
Contents
1
Most-significant bit (MSB) = 08h, memory width of the source program (8 bits)
2
Least-significant bit (LSB) = 0AAh
3
MSB of the value to set in the register
4
LSB of the value to set in the register
.
.
.
MSB of the value to set in the register
.
LSB of the value to set in the register
.
MSB of the XPC value of the entry point
.
LSB of the XPC value of the entry point (least-significant 7 bits are used)
2R−1
MSB of the entry point (PC)
2R
LSB of the entry point (PC)
2R+1
MSB of the block size of the first section to load
2R+2
LSB of the block size of the first section to load
2R+3
MSB of the XPC value of the destination address of the first section
2R+4
LSB of the XPC value of the destination address of the first section (7 bits)
2R+5
MSB of the destination address (PC) of the first section
2R+6
LSB of the destination address (PC) of the first section
.
MSB of the first word of the first section of the source program
.
.
.
LSB of the last word of the first section of the source program
.
MSB of the block size of the second section to load
.
LSB of the block size of the second section to load
.
MSB of the XPC value of the destination address of the second section
.
LSB of the XPC value of the destination address of the second section (7 bits)
.
MSB of the destination address (PC) of the second section
.
LSB of the destination address (PC) of the second section
.
MSB of the first word of the second section of the source program
.
.
.
LSB of the last word of the second section of the source program
SPRA853A
Table 3. General Structure of Source Program Data Stream in 8-Bit Mode
(Continued)
.
.
.
MSB of the block size of the last section to load
.
LSB of the block size of the last section to load
.
MSB of the XPC value of the destination address of the last section
.
LSB of the XPC value of the destination address of the last section (7 bits)
.
MSB of the destination address (PC) of the last section
.
LSB of the destination address (PC) of the last section
.
MSB of the first word of the last section of the source program
.
.
.
LSB of the last word of the last section of the source program
2n
2n+1
2.2
00h
00h indicates the end of the source program
Boot Mode Options
This section discusses each of the bootloader modes, and how they are selected and used.
2.2.1
HPI Boot Mode
The first boot mode checked after reset is HPI boot mode (see Figure 3). After a reset, the
bootloader initializes data memory address 007Fh to 0, and uses it as a software indication for
when the host has completed loading the application code through the HPI. It then asserts the
host interrupt signal (HINT) low. The bootloader checks to see if the INT2 flag in the interrupt
flag register (IFR) is equal to 1 (active), and if so, initiates HPI boot mode. The INT2 flag can be
equal to 1 if:
• The HINT pin is tied to the INT2 input pin, or
• A valid interrupt to the INT2 input pin is generated within 30 CPU clock cycles after the DSP
fetches the reset vector (if HINT is not tied to INT2).
If the INT2 flag is not set, indicating that the HINT pin is not tied to the INT2 pin or that INT2 is
not asserted within 30 CPU clock cycles, the bootloader checks all boot modes including HPI
mode. If the INT2 flag is set, the bootloader assumes HPI boot mode only and monitors the
entry-point address, as explained below.
In C54CST HPI boot mode, unlike some of the existing C54x HPI boot modes, the host must
download the code to on-chip RAM after the DSP is brought out of reset. While the host is
loading the on-chip RAM, the C54CST checks location 00 007Fh in a continuous loop looking for
a change in the contents of that address. Once the host has finished loading the boot code, it
must perform an additional write to data memory address 00 007Fh to set the entry point (start
address) of the loaded code. Address 00 007Fh contains the lower 16 bits (PC) of the entrypoint (address A15−A0). Note that the PC of the entry point of the loaded code must be a
non-zero number. When the host performs the write to 00 007Fh, the C54CST detects changes
at that address, and uses the new contents of the address to branch to the loaded code.
11
SPRA853A
When HINT has been asserted low, it stays low. The host controller can clear HINT by writing to
the host port interface control register (HPIC). The source program data stream for HPI mode
can only contain the program itself. It cannot include any extra information, such as section size
or register values, since the bootloader does not perform any interaction with the source
program data stream in HPI boot mode. The bootloader simply branches to the start address
specified above and begins execution.
Reset
HINT
tied to
INT2 or valid
interrupt to the
INT2 pin within 30 CLKOUT
cycles after the DSP
fetches the
reset
vector
?
Yes
HPI
valid entry
point
?
No
Yes
No
Check for other
boot modes
No
HPI
valid entry
point
?
Branch to specified
entry point
Yes
Figure 3. HPI Boot Mode Flow Chart
2.2.2
Serial EEPROM Boot Mode
After verifying that HPI boot was not selected, the bootloader checks for the serial EEPROM
boot mode. The serial EEPROM boot mode is selected via the INT3 external interrupt. The
bootloader checks to see if the INT3 flag in the interrupt flag register (IFR) is equal to 1 (active),
and if so, initiates serial EEPROM boot mode. Therefore, proper selection of the boot mode
requires a high-to-low transition on the INT3 pin within 30 CPU cycles after the C54CST is reset.
If an external event is not available in the system to trigger the interrupt, the McBSP1 transmit
pin (BDX1) can be used instead. The BDX1 pin is automatically toggled from high to low within
the first few cycles after reset, and can be externally connected to the INT3 input pin to select
the boot mode. When the C54CST is reset, the BDX1 pin toggles from high to low, causing the
INT3 flag to be set, and thereby selecting the serial EEPROM boot mode. This method of
selects the boot mode is convenient, because it does not require any additional external signals
or components.
To summarize, the INT3 flag can be properly activated if:
•
•
12
The BDX1 pin is tied to the INT3 input pin, as shown in Figure 4, or
A valid interrupt to the INT3 input pin is generated within 30 CPU clock cycles after the DSP
fetches the reset vector (if BDX1 is not tied to INT3).
SPRA853A
The serial EEPROM boot mode is intended for bootloading the C54CST from an SPI based
serial EEPROM. This mode configures McBSP1 in the clock-stop mode, with internal clocks and
frames. The McBSP is then used to sequentially access the serial EEPROM. The EEPROM
must have a four-wire SPI slave-type interface with a 16-bit address. The interface between the
McBSP and EEPROM is shown in Figure 4.
TMS320C5402
Serial EEPROM
BCLKX1
BFSX1
BDR1
BDX1
INT3
SCK
CS
SO
SI
Optional connection for enabling the
bootmode
Figure 4. McBSP1 to EEPROM Interface for Serial EEPROM Boot Mode
The McBSP clock rate is set to fCLKOUT/250, or 400 Khz for a 100-Mhz device. This low bit
rate ensures compatibility with most SPI-based serial EEPROM devices. The McBSP is
configured with CLKSTP = 3, CLKXP = 0, and CLKXM = 1, for use as an SPI master. The
relevant interface timings for this mode are given in the McBSP section of the C54CST
data sheet.
For each access, the McBSP transmits a 32-bit packet consisting of the 8-bit read instruction
(03h), followed by the 16-bit address to be read from, then followed be a “place holder” byte.
The EEPROM ignores the last 8 bits in the packet, and uses this slot to shift out the addressed
byte on the SO output pin. An example read access is shown in Figure 5.
BCLKX1/
SCK
0
1
2
3
4
5
6
7
1
1
8
9
10
21
22
23
A1
A0
24
25
26
27
28
29
30
31
D7
D6
D5
Data
D4 D3
D2
D1
D0
BFSX1/
SS
EEPROM instruction
BDX1/
SI
SO/
BDR1
0
0
0
0
0
0
Address
A15 A14 A13
A2
Figure 5. Example Read Access for Serial EEPROM Boot Mode
The bootloader starts reading from address 0 of the serial EEPROM and checks for a valid boot
table. When the bootloader reads and validates the keyword from the beginning of the boot
table, it proceeds to read the remainder of the boot table. The serial EEPROM boot mode uses
the same boot table as the standard 8-bit serial boot mode. The bitstream for this boot table is
described in section 2.2.4.
The serial EEPROM boot mode can be used to load multiple sections into any valid program
space address range, including extended program space. Since the serial EEPROM has a 16-bit
address, the maximum possible size of the boot table is 64K bytes, or 32K 16-bit words. This
limits the amount of code that can be directly loaded using this boot mode.
After the serial EEPROM boot process completes, the XF signal is toggled low. If the EEPROM
has an active-low HOLD input, this event can be used to automatically disable the EEPROM
after bootloading. Note that If no valid keyword is found after the first two reads, the boot
process is aborted and the bootloader proceeds to check the next boot mode.
13
SPRA853A
2.2.3
Parallel Boot Mode
After verifying that the serial EEPROM boot was not selected, the bootloader checks for parallel
boot mode. Parallel boot mode reads the desired boot table from data space via the external
parallel interface (external-memory interface), and transfers the code to program space. The
bootloader supports parallel boot of 8- or 16-bit-wide data. The software wait-state register
(SWWSR) and bank-switch control register (BSCR) are reconfigurable in both of these boot
modes. This allows the bootloader to boot from faster EEPROM, with fewer software wait states.
The bootloader uses a default setting of seven wait states.
The bootloader gets the source address from either I/O port 0FFFFh or data memory address
0FFFFh. Since the source address read from either of these locations is 16 bits wide, the boot
table can reside in any valid external address range of the 64-K data space. Figure 6 shows the
sequence of actions in the parallel boot mode.
NOTE: f a parallel boot is not desired, the data pin, D0, of the C54CST can be pulled high with
a weak pullup resistor, to avoid inadvertently booting from data or I/O space. Otherwise, some
other method should be used to ensure that a valid keyword is not read unexpectedly.
14
SPRA853A
Parallel boot
Read boot table address
from 0FFFFh in I/O space
Read first word from the boot
table address in data space
10AAh
?
Yes
16-bit parallel
boot mode from
data space
Yes
Read next
location in
boot table
No
xx08h
?
No
xxAAh
?
Yes
8-bit parallel
boot mode from
data space
Yes
8-bit parallel
boot mode from
data space
No
Read source address from
0FFFFh in data space
Read first word from the source
address in data space
10AAh
?
Yes
16-bit parallel
boot mode from
data space
No
Read MSB of source address from
0FFFEh in data space
Read LSB of source address from
0FFFFh in data space
Read first word from the source
address in data space
xx08h
?
Yes
No
Read next
byte from
boot table
xxAAh
?
No
Check for serial boot modes
Figure 6. Parallel Boot Mode Process
Since the bootloader does not know the memory width before it reads the first word of the boot
table, it must check both the data memory LSB (0FFFFh) and MSB (0FFFEh) to obtain the
correct source address. Figure 7 shows the source program data stream for parallel boot mode
using 8- or 16-bit-word mode.
15
SPRA853A
After the bootloader reads and validates the keyword from the beginning of the boot table, the
next two words are the desired values for the software wait-state register (SWWSR) and the
bank switching control register (BSCR). These register values are loaded and become active
before the remainder of the boot table is read, so changes to these settings will affect the rest of
the boot process.
08AAh or 10AAh
Initialize value of SWWSR16
Initialize value of BSCR16
Entry point (XPC)7
Entry point(PC)16
Size of first section16
Destination of first section (XPC)7
Destination of first section(PC)16
Code word(1)16
.
.
Code word(N)16
Size of last section16
Destination of last section (XPC)7
Destination of last section(PC)16
Code word(1)16
.
Code word(N)16
0000h (indicates the end of the boot table)
Figure 7. Source Program Data Stream for Parallel Boot in 8-, 16-Bit-Word Mode
2.2.4
Standard Serial Boot Mode
The bootloader is capable of loading data in standard serial port mode from McBSP0 or
McBSP1. McBSP0 is used to perform 16-bit transfers. McBSP1 is used to perform 8-bit
transfers.
In standard serial boot mode, the bootloader initializes the serial port to a configuration
consistent with the TI C54x standard serial port. The bootloader also sets the XF pin low to
indicate that the serial port is ready to receive data. The DSP then polls the interrupt flag register
(IFR) to determine which serial port has data input (BRINT0, or BRINT1). When the desired
serial port has been identified, the bootloader continues to read the same port to load the entire
boot table.
16
SPRA853A
On the TMS320C548/549 bootloader, the bootloader would read configuration words from the
boot table and reconfigure the serial port before completing the boot table. On the C54CST, the
serial port is not reconfigured at any point during the read of the boot table. To maintain
compatibility with the hex conversion utility, the C54CST bootloader ignores the register
configuration entries in the serial boot table.
The following conditions (illustrated in Figure 8) must be met to insure proper operation.
•
The serial port receive clock (BCLKR) is supplied externally and cannot exceed 1/2 the frequency of the C54CST CPU clock.
•
A minimum delay time of 40 CPU clocks should be provided between the transmission of
each word. This can be achieved by either slowing the receive clock frequency, or providing
additional clocks between transmitted words.
These conditions provide the required delay for receiving consecutive words in the bootloader.
BCLKR
A minimum of 40 CPU clocks
should separate each frame
BFSR
BDR
8/16
8/16
Figure 8. Timing Conditions for Serial Port Operation
Figure 9 and Figure 10 show the serial boot process from each of the supported serial ports.
The bootloader polls the serial port status registers and, when the received data ready flag
(RRDY) is active, the data receive register (BDRR) is read.
17
SPRA853A
BPRINT1 = 1
No
Check for
McBSP0 boot
DRR = 08h
?
No
Yes
Read next
byte
DRR = 0AAh
?
Yes
8-bit serial
boot
Read 4 dummy words for
hex utility compatibility
Transfer code from serial
port to program space
Figure 9. Standard Serial Boot From McBSP1 (8-Bit) After BRINT1 = 1
BPRINT0 = 1
No
DRR = 10AAh
?
Check for
I/O boot
Yes
16-bit serial
boot
Read 4 dummy words for
hex utility compatibility
Transfer code from serial
port to program space
Figure 10. Standard Serial Boot From McBSP0 (16-Bit) After BRINT0 = 1
18
SPRA853A
Figure 11 shows the boot table for serial boot modes as 16-bit words. For 8-bit mode, each word
is transmitted to the serial port most-sigificant byte first, followed by the least-significant byte.
08AAh or 10AAh
Dummy Word for Compatibility − Ignored
Dummy Word for Compatibility − Ignored
Dummy Word for Compatibility − Ignored
Dummy Word for Compatibility − Ignored
Entry point (XPC)7
Entry point(PC)16
Size of first section16
Destination of first section (XPC)7
Destination of first section(PC)16
Code word(1)16
.
.
Code word(N)16
Size of second section16
Destination of second section (XPC)7
Destination of second section(PC)16
Code word(1)16
.
.
Code word(N)16
.
.
Size of last section16
Destination of last section (XPC)7
Destination of last section(PC)16
Code word(1)16
.
.
Code word(N)16
0000h (indicates the end of the boot table)
Figure 11. Source Program Data Stream for 8-, 16-Bit McBSP Boot in Standard Mode
19
SPRA853A
2.2.5
I/O Boot Mode
I/O boot mode provides the capability to bootload via the external parallel interface using I/O port
0h. This mode is in initiated by the external host driving the BIO pin low. The C54CST
communicates with the external device using BIO and XF as handshake signals. When BIO
goes low, the DSP reads data from I/O address 0h, drives the XF pin high to indicate to the host
that the data has been received, and writes the input data to the destination address. The
C54CST then waits for the BIO pin to be driven high, and then low again, by the external host for
the next data transfer.
This mode asynchronously transfers code from I/O port 0h to internal or external program
memory. This allows a slow host processor to easily communicate with the device by
polling/driving the XF/BIO lines. Words may be either 16 or 8 bits long.
Figure 12 shows the handshake protocol required to successfully transfer each word via I/O
address 0h. The first handshake sequence shown in the figure requests and acknowledges the
use of I/O boot mode. This sequence is performed after reset prior to sending any boot table
contents. The second handshake sequence is used to load all of the words in the boot table.
Upon reaching the end of the boot table, the DSP transfers control to the entry-point address
specified in the boot table.
BIO
XF
DSP
ready
for I/O
boot
mode
Host
request
for I/O
boot
mode
DSP
ack
Host
ack
DSP
ready
to
receive
data
Host
data
ready
DSP
ack
of data
received
Host
ack
of
end of
transfer
Figure 12. I/O Boot Mode Handshake Protocol
If the 8-bit transfer mode is selected, the lower eight data lines are read from I/O address 0h.
The upper bytes on the data bus are ignored. The C54CST reads two 8-bit words to form a
16-bit word. The order of transmission to the DSP is most-sigificant byte first ,followed by the
least-significant byte. Figure 13 shows the events in an I/O boot.
20
SPRA853A
I/O boot
Yes
Data = 10AAh
?
No
No
Data = 08h
?
Restart bootloader
Yes
16-bit I/O mode
Data = AAh
?
Yes
8-bit I/O mode
Read boot table
and transfer code
Branch to entry
point and begin
Figure 13. I/O Boot Mode
For both 8-bit and 16-bit I/O modes, the structure of the boot table is the same as that shown for
the parallel boot modes in Figure 7.
A minimum delay of ten CPU clock cycles is provided between the XF rising edge and the write
operation to the destination address. This allows the host processor time to turn off its data
buffers before the C54CST initiates a write operation (in case the destination is external
memory). Note that the C54CST only drives the external bus when XF is high.
3
Building the Boot Table
To use the features of the C54CST bootloader, you must generate a boot table, which contains
the complete data stream the bootloader needs. The boot table is generated by the hex
conversion utility tool, which is provided with the TMS320C54x assembly language tools
package. The contents of the boot table vary, depending on the boot mode and the options
selected when running the hex conversion utility.
NOTE: You must use version 1.20 or higher of the C54x code generation tools to generate the
proper boot table for the C54CST. Previous versions of the code generation tools do not support
the enhanced bootloader options for the C54CST and may produce a version of the boot table
intended for earlier C54x devices without generating warnings or errors. Contact Texas
Instruments for information about upgrades to earlier versions of the code generation tools.
21
SPRA853A
To build the C54CST boot table, follow these steps:
Step 1: Assemble (or compile) the code using the −v548 assembler option. This option
marks the object files produced by the assembler specifically for the devices with enhanced bootloader functions, including the C54CST. The hex conversion utility uses this
information to generate the correct format for the boot table. If this option is not included
during assembly, the hex conversion utility may produce a version of the boot table intended for earlier C54x devices without generating warnings or errors.
Step 2: Link the file. Each block of the boot table data corresponds to an initialized section in
the common object file format (COFF) file. Uninitialized sections are not converted by
the hex conversion utility.
Step 3: Run the hex conversion utility. Choose the appropriate options for the desired boot
mode, and run the hex conversion utility to convert the COFF file produced by the linker
into a boot table. See the TMS320C54x Assembly Language Tools User’s Guide
(SPRU102) for a detailed description of the procedure for generating a boot table and
using the options.
An example command file for the hex conversion utility is shown in Figure 14.
myfile.out
/* Input COFF file name.
−e 0300h
/* Entry point symbol.
−a
/* ASCII hex output format.
−boot
/* Bootload all sections in the input file.
−bootorg SERIAL /* Create a serial port boot table.
−memwidth 8
/* EEPROM width is 8 bits.
−o myfile.hex
/* Output file name.
Figure 14. Example Command File for Hex Conversion Utility
When the hex conversion utility is invoked with the example command file of Figure 14, it
creates an ASCII hex file called myfile.hex, which can be used for programming a serial
EEPROM. All of the sections from the input file are placed in the boot table, and the entry point
is set to address 0300h.
4
Reference
1. TMS320C54x Assembly Language Tools User’s Guide (SPRU102).
22
IMPORTANT NOTICE
Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications,
enhancements, improvements, and other changes to its products and services at any time and to discontinue
any product or service without notice. Customers should obtain the latest relevant information before placing
orders and should verify that such information is current and complete. All products are sold subject to TI’s terms
and conditions of sale supplied at the time of order acknowledgment.
TI warrants performance of its hardware products to the specifications applicable at the time of sale in
accordance with TI’s standard warranty. Testing and other quality control techniques are used to the extent TI
deems necessary to support this warranty. Except where mandated by government requirements, testing of all
parameters of each product is not necessarily performed.
TI assumes no liability for applications assistance or customer product design. Customers are responsible for
their products and applications using TI components. To minimize the risks associated with customer products
and applications, customers should provide adequate design and operating safeguards.
TI does not warrant or represent that any license, either express or implied, is granted under any TI patent right,
copyright, mask work right, or other TI intellectual property right relating to any combination, machine, or process
in which TI products or services are used. Information published by TI regarding third-party products or services
does not constitute a license from TI to use such products or services or a warranty or endorsement thereof.
Use of such information may require a license from a third party under the patents or other intellectual property
of the third party, or a license from TI under the patents or other intellectual property of TI.
Reproduction of information in TI data books or data sheets is permissible only if reproduction is without
alteration and is accompanied by all associated warranties, conditions, limitations, and notices. Reproduction
of this information with alteration is an unfair and deceptive business practice. TI is not responsible or liable for
such altered documentation.
Resale of TI products or services with statements different from or beyond the parameters stated by TI for that
product or service voids all express and any implied warranties for the associated TI product or service and
is an unfair and deceptive business practice. TI is not responsible or liable for any such statements.
Following are URLs where you can obtain information on other Texas Instruments products and application
solutions:
Products
Amplifiers
Applications
amplifier.ti.com
Audio
www.ti.com/audio
Data Converters
dataconverter.ti.com
Automotive
www.ti.com/automotive
DSP
dsp.ti.com
Broadband
www.ti.com/broadband
Interface
interface.ti.com
Digital Control
www.ti.com/digitalcontrol
Logic
logic.ti.com
Military
www.ti.com/military
Power Mgmt
power.ti.com
Optical Networking
www.ti.com/opticalnetwork
Microcontrollers
microcontroller.ti.com
Security
www.ti.com/security
Telephony
www.ti.com/telephony
Video & Imaging
www.ti.com/video
Wireless
www.ti.com/wireless
Mailing Address:
Texas Instruments
Post Office Box 655303 Dallas, Texas 75265
Copyright  2003, Texas Instruments Incorporated
Was this manual useful for you? yes no
Thank you for your participation!

* Your assessment is very important for improving the work of artificial intelligence, which forms the content of this project

Download PDF

advertising