Texas Instruments | Using IBIS Models for Timing Analysis (Rev. A) | Application notes | Texas Instruments Using IBIS Models for Timing Analysis (Rev. A) Application notes

Texas Instruments Using IBIS Models for Timing Analysis (Rev. A) Application notes
Application Report
SPRA839A - April 2003
Using IBIS Models for Timing Analysis
C6000 Hardware Applications
ABSTRACT
Today’s high-speed interfaces require strict timings and accurate system design. To achieve
the necessary timings for a given system, input/output buffer information specification (IBIS)
models must be used. These models accurately represent the device drivers under various
process conditions. Board characteristics, such as impedance, loading, length, number of
nodes, etc., affect how the device driver behaves. This application report discusses how to
properly use IBIS models to attain accurate timing analysis for a given system. This report
focuses on the use of SDRAM with a TMS320C6000 DSP, but is applicable to all interfaces
that have setup and hold parameters.
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Contents
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
Establishing a Reference Point . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Understanding the Tester . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
3.1 Tester Load Adjustment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
3.2 Using Data Sheet Timing on a Real System Board . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
3.3 Variations Between Device Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
The Reference Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
4.1 Understanding Vref Measured on Tester vs. Real Board . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
4.2 Translating Data Sheet Reference Voltage From Vref to VIL/VIH . . . . . . . . . . . . . . . . . . . . . . . 11
Noise Margins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
IBIS Calculation Methods . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
6.1 Input Setup of the SDRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
6.2 Input Hold of the SDRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
6.3 Input Setup of the DSP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
6.4 Input Hold of the DSP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Summary of AC Timing Analysis Procedures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
7.1 Gathering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
7.2 IBIS Simulations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
7.2.1 IBIS Simulations for DSP Outputs on the Board . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
7.2.2 IBIS Simulations for DSP Outputs With Test Load . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
7.2.3 IBIS Simulations for SDRAM Outputs on the Board . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
7.2.4 IBIS Simulations for SDRAM Outputs With Test Load . . . . . . . . . . . . . . . . . . . . . . . . . . 22
7.3 Calculations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
7.3.1 Input Setup of the SDRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
7.3.2 Input Hold of the SDRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
7.3.3 Input Setup of the DSP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
7.3.4 Input Hold of the DSP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Conclusion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Trademarks are the property of their respective owners.
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SPRA839A
List of Figures
Figure 1. DSP Writes (Control Signals and/or Data Signals) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Figure 2. DSP Reads (Data Signals Only) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Figure 3. Board Route/Loading vs Tester Route/Loading . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Figure 4. Signal Delay With Heavier Load Than Tester Load (C0 < A0) . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Figure 5. Signal Delay With Lighter Load Than Tester Load (C0 > A0) . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Figure 6. Data Sheet Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Figure 7. Adding Tester Load Adjustment to Obtain Timing at SDRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Figure 8. Interpolation Using Vref . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Figure 9. Difficulty in Defining Single (tref, Vref) on Boards Without Clean Waveforms . . . . . . . . . . . . 11
Figure 10. Translating Input Requirement to VIL/VIH Reference Volage . . . . . . . . . . . . . . . . . . . . . . . . . 12
Figure 11. Noise Margin for a Typical Signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Figure 12. Input Setup of the SDRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Figure 13. Input Hold of the SDRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Figure 14. Input Setup of the DSP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Figure 15. Input Hold of the DSP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Figure 16. Example DSP-SDRAM Interface Board Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Figure 17. IBIS Representation of DSP Output on a Board . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Figure 18. IBIS Representation of DSP Output With Test Load . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Figure 19. IBIS Representation of SDRAM Output on a Board . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Figure 20. IBIS Representation of SDRAM Output With Test Load . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
List of Tables
Table 1.
Table 2.
Table 3.
Table 4.
1
SDRAM Input Setup Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
SDRAM Input Hold Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
DSP Input Setup Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
DSP Input Hold Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Introduction
Digital signal processors (DSPs) and memories are tested to specifications given by their
respective data sheets. These tests are performed under specific operating conditions given by
the data sheets. Any variation from these specific operating conditions will cause a change in
behavior from which the device was tested. These operating conditions include temperature,
voltage, frequency, capacitive loading, impedance, etc.
Input/output buffer information specification (IBIS) is a fast and accurate way of modeling a
buffer’s behavior over all process conditions. IBIS models are generated based on V/I curves
derived from full-circuit simulations and/or bench-top testing. In order to use IBIS models, a
simulation package, from companies such as Hyperlynx or Mentor Graphics, must be
purchased. These simulation packages give accurate information on signal integrity issues that
may occur based on system, board, and component-level characteristics.
For example, a DSP tester has a given test load. If a board has more or less loading than that of
the tester, the timings will be skewed from what was originally intended. This can hurt or help the
system, depending on which way the timing is skewed, and what parameter is of concern.
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Using IBIS Models for Timing Analysis
SPRA839A
Important to this application report is that of impedance and loading. It is assumed that
frequency remains constant, the voltage remains well within the data sheet specification range,
and the temperature remains at or near room condition (well within the specification limits,
normally 0_C and 90_C).
Systems that use multiple sychronous dynamic random-access memory (SDRAM) chips to fill
the bus width will have to do IBIS simulations on each component. This must be done since
there is no longer a point-to-point connection between the DSP and the SDRAM. The variations
in trace lengths create differences in timings between the multiple components. Users must
perform IBIS simulations to ensure signal integrity.
This application report discusses the various reference points for timings that are important to
both the DSP and the SDRAM. In section 3, an overview of the tester used to test the DSP
and/or the SDRAM is given along with an explanation of the timing variation between the tester
and a typical board. Reference voltages and noise margins impact the timings presented by both
the tester and a typical board. An understanding of why this occurs is briefly discussed in
sections 4 and 5. Section 6 of this application report encompasses the formulas used to
establish setup and hold times for both the DSP and the SDRAM, based on IBIS Simulations.
Section 7 summarizes the AC timing analysis procedures.
2
Establishing a Reference Point
Data sheet timings are measured from the pins of the device connected to the test board with a
given tester load. On a real system board, these timings change as loading increases or
decreases from the loading on the tester board. Before going into further details (in section 3) on
how timings differ on a real system board versus the test board, this section discusses how to
establish a reference point. A reference point must be established when modeling a board that
varies from the original test board model. As a matter of convenience, the reference point is
taken from just inside the master device, the DSP. The reference point represents the time in
which the DSP output buffer is enabled.
Figure 1 gives a high-level drawing of how a DSP write to SDRAM can be represented in a real
system board. The point, denoted by t0, is the point in which all timings will be referenced. The
points A, B, D, and E are measured at the pins of the DSP and SDRAM, respectively. Point F
describes the point at which the output buffer turns on relative to time t0. Xn is an internal timing
delay that is represented by a constant value, fixed by the design of the DSP. Assume that the
design of the DSP sets Xn to –3.1 ns. Also assume that the output buffer at A had an internal
delay of 0.2 ns, and the output buffer at D had an internal delay of 0.3 ns. Calculations would
show that the time at point A is (t0 + 0.2) ns, or simply 0.2 ns relative to t0, Similarly, calculations
would show that the time at point D is (t0 + Xn + 0.3) ns = (t0 – 3.1 + 0.3) ns, or simply –2.8 ns
relative to t0. The output setup time for the DSP is calculated from when the data transitions at
point D, to when the clock transitions at point A. In this case, the output setup time is [0.2 –
(–2.8)] ns = 3 ns.
Xn will be different for hold times, since this uses different internal logic to gate the buffers.
Using IBIS Models for Timing Analysis
3
SPRA839A
t0
A
B
EMIF Clock
F
D
E
Xn
Control / Data
SDRAM
Digital Signal Processor
Figure 1. DSP Writes (Control Signals and/or Data Signals)
In the case of DSP reads, the DSP outputs the clock, control, and address signals as shown in
Figure 1. Upon receiving the read command, the SDRAM outputs the data signals. Figure 2
gives a high-level drawing of how the SDRAM outputs data relative to the clock from the DSP.
Yn represents the internal timing delay generated by the SDRAM. The SDRAM measures input
and output timings with respect to the clock signal at the pin of the device. For example, the
output hold time of the SDRAM starts as soon as the clock signal at point B passes a given
reference voltage, Vref. The hold time ends at point D as soon as the signal crosses Vref.
Assume that the output hold design of the SDRAM sets Yn to 1.8 ns. Also assume that the input
buffer at B has a delay of 0.3 ns, and the output buffer at D has a delay of 0.4 ns. Calculations
would show that, in Figure 2, the time at point D relative to point B is [0.3 + Yn + 0.4] ns = [0.3 +
1.8 + 0.4] = 2.5 ns, giving an SDRAM output hold time of 2.5 ns in this example.
A
B
t0
EMIF Clock
E
D
F
Yn
Data
SDRAM
Digital Signal Processor
Figure 2. DSP Reads (Data Signals Only)
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Using IBIS Models for Timing Analysis
SPRA839A
Both the DSP and the SDRAM measure input and output timings with respect to the clock signal
at the pin of the device. Output times are measured when Vref is crossed at the data/control
signal relative to when Vref is crossed at the clock. Input times are measured when the
data/control signal goes valid (setup times) or invalid (hold times) relative to when Vref is crossed
at the clock.
3
Understanding the Tester
3.1
Tester Load Adjustment
As mentioned in previous sections, the tester loading must be accounted for when performing
timing analysis on a real system board. The tester loading must be subtracted out of the board
routes in order to accurately reflect the change in loading. Figure 3 gives a simplistic view of how
the board route varies from the tester loading.
A
B
t0
Y
Device
input
Device
output
Typical point-to-point board route
C
Transmission line
t0
Cref
Device
output
Tester load circuit
(see Note)
Typical tester route
NOTE: Tester load circuit differs on the various devices. Refer to the device data sheet for the exact tester load circuit.
Figure 3. Board Route/Loading vs Tester Route/Loading
In Figure 3, the top figure shows a typical point-to-point board route. The output from the DSP
(point A) drives a load consisting of the transmission line and the load at point B. The line delay,
Y, is a function of the board routing and characteristics. The bottom figure shows a typical tester
circuit. Refer to the device data sheet for the exact tester circuit. Typical testers will subtract off
line delays and provide data sheet output timings at the pins of the device (point C) given the
capacitive loading of the tester. Data sheet timings are obtained when a signal crosses the
reference voltage Vref at point C. You cannot take the data sheet timing measured at point C and
assume it applies to the timing at point A or point B on your board. This is because, in most
cases, the board has a different capacitive loading than the tester circuit. A system board with
loadings smaller than the tester loading will cause faster timings to point B, compared to the
data sheet timing measured at point C. A system board with larger loadings will cause slower
timings to point B, compared to the data sheet timing measured at point C.
Using IBIS Models for Timing Analysis
5
SPRA839A
By providing the proper board route characteristics (Y) and IBIS models for the DSP and the
SDRAM, IBIS simulations can be used to measure the actual timings at point B and C,
respectively. IBIS simulators have the ability to give absolute timings or reference timings.
Absolute timings are measured from when the buffer is turned on at t0. Reference timings are
measured from when the output pin under test reaches the reference voltage. For example,
absolute timing at point B is measured from t0, while reference timing at point B is measured
from when the output at A reaches the reference voltage. For AC timing analysis, use absolute
timings in IBIS simulations to establish a common reference point for both the system board
circuit and the tester circuit. Absolute timings are represented by a subscript 0. Performing IBIS
simulations with the proper IBIS models and board route characteristics, you can obtain B0, the
absolute delay measured from t0 to B. Similarly, you can perform IBIS simulations to obtain C0,
the absolute delay from t0 to C. The following equation gives the difference between the actual
timing seen at the pin of the SDRAM (B0) and the data sheet timing (C0):
Difference between timing at SDRAM and data sheet = B0 – C0
As shown in Figure 3, the board delay Y is represented by this equation:
(1)
(2)
Y = B0 – A0
This shows that, if board loading is equivalent to the tester loading (C0 = A0 ), the difference
between the timing at SDRAM and data sheet = B0 – C0 = B0 – A0 . In other words, the delay
caused by the tester is equivalent to the delay caused by the board loading. If board loading is
smaller than the tester load (C0 > A0 ), then B0 is smaller, making the difference between the
timing at SDRAM and data sheet smaller. The opposite is true as well. Larger board loading
(C0 < A0 ) will cause B0 to be larger; thus, the difference between the timing at SDRAM and the
data sheet will also be larger. Figure 4 and Figure 5 show how the loading affects a given line
with respect to the rising clock signal. Parameters C0 and Y are constant in Figure 4 and
Figure 5. Parameter A0 is different in Figure 4 and Figure 5, assuming different loading at
point B.
ECLK
tpd-max
Signal w /Test Load
C0 (fixed, given test load)
Unloaded Signal
(varies, based on
loading at B)
A0
Signal on Board at Point A
Y
(fixed, given
board trace)
B0
Signal on Board at Point B
Figure 4. Signal Delay With Heavier Load Than Tester Load (C0 < A0 )
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Using IBIS Models for Timing Analysis
SPRA839A
ECLK
tpd-max
Signal w /Test Load
C0 (fixed, given test load)
Unloaded Signal
A0
A0 + Y (varies, based on
loading at B)
Signal on Board at Point A
Y
(fixed, given board trace)
B0
Signal on Board at Point B
Figure 5. Signal Delay With Lighter Load Than Tester Load (C0 > A0 )
Note that B0 and C0 are calculated from absolute timing in IBIS simulation. The difference
(B0 * C0) is a constant for a given board trace and input/output buffer. (B0 * C0) is referred to
here as the tester load adjustment.
Tester load adjustment = B0 – C0
(3)
This shows that for a given pin, if you know the time t1 when the signal transitions at point C, you
can easily find out time t2 when the signal transitions at point B by simply adding the tester load
adjustment, which is a constant for a given pin and board trace:
t2 = t1 + (B0 – C0 )
(4)
The next section explains how to make use of the tester load adjustment in AC timing analysis.
3.2
Using Data Sheet Timing on a Real System Board
The data sheet does not provide the internal reference t0 and the absolute time, C0, at which a
signal switches (see Figure 3). Instead, the data sheet provides data/control signal timing, with
respect to the clock signal at the pin of the device, given a tester load. Figure 6 shows how the
data sheet timing is obtained, using propagation delay as an example.
Using IBIS Models for Timing Analysis
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SPRA839A
C(Qn)
t0
Transmission line
Cref
Data/
control
output
Tester load circuit
(see Note)
C(Clk)
Transmission line
t0
Cref
Clock
output
Tester load circuit
(see Note)
Data sheet propagation delay = C0(Qn) – C0(Clk)
NOTE: Tester load circuit differs on the various devices. Refer to the device data sheet for the exact tester load circuit.
Figure 6. Data Sheet Timing
For the remainder of this application report, the term “tpd” is used to represent the propagation
delay from the clock signal to the data/control signal. tpd is measured from when the data/control
switches relative to when the clock transitions. To understand AC timing in the DSP-to-SDRAM
write example, you must translate the data sheet timing (tpd at the DSP pin with tester loading)
to tpd at the input pin of the SDRAM, to decide whether the SDRAM input timing requirements
can be met in a real system board. Section 3.1 provides a tester load adjustment (B0 – C0) that
shows the difference in timing between when a signal switches at point B vs. C (Figure 3). You
need to use this tester load adjustment to translate data sheet timing to tpd at the SDRAM pin.
As shown in Figure 6, the tpd in the data sheet is calculated from:
tpd (datasheet) = C0 (Qn ) – C0 (Clk)
(5)
On the real system board, the tpd at the SDRAM input pin is:
tpd (at SDRAM) = B0 (Qn ) – B0 (Clk)
(6)
In the above equations, the only unknown is tpd(at SDRAM). Parameter tpd(datasheet) is
provided in the data sheet, and parameters C0(Qn), C0(Clk), B0(Qn), and B0(Clk) are obtained
from IBIS simulations with the proper board trace and IBIS models. You know that given C0—the
time when a signal switches at C—you can calculate the time when a signal switches at the
SDRAM pin by adding the tester load adjustment, as seen in equation 4 in section 3.1.
Therefore, you obtain:
B0 (Qn ) = C0 (Qn ) + [B0 (Qn ) – C0 (Qn )]
8
; Add tester load adjustment
(7)
B0 (Clk) = C0 (Clk) + [B0 (Clk) – C0 (Clk)] ; Add tester load adjustment
(8)
Using IBIS Models for Timing Analysis
SPRA839A
This means tpd(at SDRAM) can be calculated as follows:
tpd (at SDRAM)
= B0 (Qn ) – B0 (Clk)
; Equation 6
= {C0 (Qn ) + [B0 (Qn ) – C0 (Qn )]} – {C0 (Clk) + [B0 (Clk) – C0 (Clk)] } ; Substitute equations 7 and 8.
; Rearrange.
= C0 (Qn ) – C0 (Clk) + [B0 (Qn ) – C0 (Qn )] – [B0 (Clk) – C0 (Clk)]
= tpd (datasheet) + [B0 (Qn ) – C0 (Qn )] – [B0 (Clk) – C0 (Clk)]
; Substitute equation 5.
Figure 7 presents this calculation graphically to show how the tester load adjustment is added to
the data sheet timing to derive timing at the SDRAM pin.
ECLK
at point C
tpd(datasheet) from data sheet
Data
at point C
ECLK at point B
(SDRAM)
B0(Clk) – C0(Clk) from IBIS simulation (tester load
adjustment for Clk)
B0(Qn) – C0(Qn) from IBIS simulation
(tester load adjustment for Data)
tpd(at SDRAM)
Data at point B
(SDRAM)
Figure 7. Adding Tester Load Adjustment to Obtain Timing at SDRAM
3.3
Variations Between Device Pins
For any given pin, Qn, the value of C0 will be constant. C0(Qn) may vary between the different
pins due to variations within the component packages. This variation between pins is generally
small, but must be taken into account when calculating the timings. For simplicity, the average
value for C0 for all Qn can be used, and a factor of margin can be added to compensate for this
simplification. If more exact timings are desired, C0(Qn) should be calculated for each signal
trace.
For each pin, C0 is calculated by placing the specific pin on the tester load given in the data
sheet. You can obtain the value C0 for a given pin by performing IBIS simulation using this
simple setup. For each pin, the IBIS file provides its input/output characteristic at three
conditions—weak, strong, and typical. You should perform at least two independent IBIS
simulation runs—one using weak conditions, and one using strong conditions. The independent
weak and strong runs will give you the worst-case scenarios. The delay from t0 to point C0
(Figure 3) is measured with respect to the reference voltage given by the data sheets. The
reference voltage is discussed in the next section.
Using IBIS Models for Timing Analysis
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SPRA839A
4
The Reference Voltage
A point that needs discussion is that of the reference voltage, Vref. Control and data signals are
latched at the rising edge of the clock signal. The question of where exactly between VIL and VIH
does the SDRAM or the DSP latch the data must be examined. There is no exact answer.
Process variations cause inconsistencies between similar devices. In order to keep device
characteristics consistent, a reference voltage is given by the data sheet to show how signals
are measured on the tester. This reference voltage is used as a starting point for calculating
device characteristics, such as setup and hold. For example, the data sheet may provide
tpd(Clk-Data) = 3 ns. This means that the delay between the clock crossing Vref at point C
(Figure 3) and the data crossing Vref at point C is 3 ns. Some IBIS packages will only calculate
when devices achieve valid logic levels (VIL and VIH) from the time in which the buffer is enabled
(t0). Using these times, in conjunction with the Vref stated in the data sheet, the time it takes to
get to Vref can be interpolated. Figure 8 shows how this is done.
Figure 8 shows an example IBIS simulation of a particular device pin. The first IBIS simulation
run produces the left waveform (buffer in strong condition), and the second simulation run
produces the right waveform (buffer in weak condition). Vref, VIL, and VIH are parameters from
the data sheet. Timing parameters tref, til, and tih are obtained from IBIS simulations at point Vref,
VIL, and VIH, respectively. As shown in Figure 8, the interpolation formula applies because the
given waveforms are clean and the slope from (til, VIL) to (tref, Vref) can be assumed to be the
same as the slope from (tref, Vref) to (tih, VIH). This assumption applies to the individual strong
and weak waveforms.
As stated in the data sheets, AC timings are calculated based off of Vref. Therefore, Vref should
be used when estimating the timings generated by the DSP or SDRAM on a given board. The
use of strong and weak buffers should not be mixed when interpolating Vref.
V
Strong condition
3.30
Weak condition
VIH
Interpolation:
Vref
tref =
(Vref – VIL) x (tih – til)
(VIH – VIL)
VIL
0
t0
t
tref,strong tref,weak
Figure 8. Interpolation Using Vref
10
Using IBIS Models for Timing Analysis
+ til
SPRA839A
4.1
Understanding Vref Measured on Tester vs. Real Board
The data sheet defines a reference voltage, Vref , at point C in Figure 3, from which all
AC timings are calculated. The corresponding timing reference, tref , can be calculated using
IBIS simulations. This is possible because, on the tester, the signals have point-to-point
connections (device under test connected to the tester), resulting in clean waveforms similar to
the ones shown in Figure 8, where the transition between VIL and VIH is smooth and monotonic.
Therefore, a single tref that corresponds to Vref can easily be located. A real system board,
however, may not provide clean, point-to-point connections. As a result, it may be very difficult to
define a tref that corresponds to Vref at point B (Figure 3). Figure 9 shows this problem where the
signal between VIL and VIH is not monotonic.
V
3.30
VIH
Vref
Non-monotonic waveform at
point B makes it difficult to
determine tref at reference
voltage Vref.
VIL
0
t0
t
tref = ?
Figure 9. Difficulty in Defining Single (tref, Vref) on Boards Without Clean Waveforms
For proper operation, you must perform IBIS simulations to ensure that the clock signal at
point B (input to SDRAM) is monotonic between VIL and VIH in a real system board, similar to
the signal in Figure 8. Because clock signals are required to be monotonic, the reference
voltage, Vref, can easily be identified, as shown in Figure 8. Data and control signals, however,
are not required to be monotonic. The only requirement for data/control signals is that they must
meet the input setup and hold time requirement of the end device. Figure 9 may therefore apply
to the data/control signals. You need to use voltages other than Vref as a reference voltage at
point B in a real system board. This is discussed in the next section.
4.2
Translating Data Sheet Reference Voltage From Vref to VIL/VIH
As shown in section 4.1, data/control signals at point B (input of the end device) may not be
clean. You must adjust the data sheet input requirement from using Vref to using VIL/VIH as a
reference voltage. For a rising data/control signal, VIL should be used as the new reference
voltage because the rising signal is no longer considered a logic-low the moment it goes above
VIL. Similarly, for a falling data/control signal, VIH should be used as the new reference voltage
because the falling signal is no longer considered a logic-high the moment it goes below VIH.
Using IBIS Models for Timing Analysis
11
SPRA839A
Figure 10 gives an example of how to translate the data input hold requirement for a different
reference voltage. Input hold requirement (tih) is measured from the clock switching at Vref to the
data switching at Vref, measured at the input pin of the device. This is shown at point (tih, Vref) in
Figure 10. For a rising data signal, you need to translate tih to the new reference voltage t1,
shown as point (t1, VIL). For a falling data signal, you need to translate tih to the new reference
voltage t2, shown as point (t2, VIH). The tester provides input signals to the device under test at a
specified input slew rate, measured in the unit volt per nanosecond (V/ns) and shown as slope
m in Figure 10. The algebraic equations in this figure show the calculation of t1 and t2 based on
the tester input slew rate m, Vref, VIL, VIH, and the data sheet tih.
Because data signals can be either falling and rising, you need to define the new input hold
requirement as the worst of t1 or t2. Larger input hold requirements are more stringent, therefore
you should pick the larger of t1 or t2 as your new input hold requirement referenced at the new
reference voltage VIL or VIH, respectively. In the typical case where Vref = 1.5 V, VIL = 0.8 V, VIH
= 2.0 V, t2 becomes the new input hold requirement because it is larger (and more stringent)
than t1. As mentioned in section 4.1, clock signals are monotonic; therefore, they can use the
Vref reference. Only data/control signals need to be translated to use the VIL/VIH voltage
reference.
Clk
(0,Vref)
Calculating the adjusted tih (which equals t1 or t2)
Data/Control
(rising waveform)
tih = input hold requirement from data sheet
(tih,Vref)
(t1,VIL)
t1 = tih – (1/m) * (Vref – VIL) where m is a positive value
t2 = tih – (1/m) * (Vref – VIH) where m is a negative value
New input hold requirement is the greater of t1 or t2.
(t2,VIH)
(tih,Vref)
Data/Control
(falling waveform)
t
t=0
t=t2 (adjusted tih)
NOTE: All slopes (input slew rate or transition time) are m V/ns, as specified in the data sheet.
All signals are measured at the input of the device under test.
All points in this figure are labeled as (time, voltage).
Figure 10. Translating Input Requirement to VIL/VIH Reference Volage
5
Noise Margins
IBIS simulations do not model noise levels within a system. Certain levels of noise, such as
cross-talk, can be accounted for; but ground bounce, electromagnetic interference (EMI), and
general power supply noise are not modeled. These uncertain noise sources must be taken into
account when analyzing IBIS models. Figure 11 shows the noise margin for a typical signal
during a falling edge with moderate amounts of ringing. For proper operation, the board designer
must ensure that a signal is well within a valid high or low level.
12
Using IBIS Models for Timing Analysis
SPRA839A
V
3.30
VIH
Vref
Noise margin
Signal logic level
undefined in this
region
VIL
t
0
t0
Figure 11. Noise Margin for a Typical Signal
Sporadic noise can easily achieve 100 mV-150 mV levels, depending on the environment in
which the board is running. A shift of 150 mV on the ground plane can cause a signal to
transition from a valid logic level to an invalid state, possibly causing an unknown behavior. A
typical method of accounting for noise margin is to adjust the VIL and VIH levels within the IBIS
simulation. Standard voltage levels for VIL and VIH are 0.8 V and 2.0 V, respectively. Using a
VIL voltage of 0.6 V and a VIH voltage of 2.5 V are common numbers when adjusting for noise
margins. Boards should be designed to ensure logic-low signals are well below the adjusted
VIL = 0.6 V, and logic-high signals are well above the adjusted VIH = 2.5 V. This is a more
stringent board-design requirement that provides an extra noise margin of 0.2 V for the logic-low
signals, and a noise margin of 0.5 V for the logic-high signals.
To do so, edit the device IBIS models by changing Vinl from 0.8 V to 0.6 V, and Vinh from 2.0 V to
2.5 V. Then run IBIS simulations to obtain absolute timings at point B (Figure 3) measured at
VIL = 0.6 V and VIH = 2.5 V.
6
IBIS Calculation Methods
Both the DSP and SDRAM have minimum timing requirements that must be adhered to.
Switching characteristics are guaranteed by the part as long as the minimum operating
conditions and requirements are met. The switching characteristics of one component must
meet the requirements of the other component in order for a system to work properly.
It is important to emphasize here that switching characteristics, as well as timing requirements,
are measured at the pins of the DSP and/or the SDRAM.
The clock line is an output of the DSP. There are no specific setup and hold-time requirements
associated with this line. It is important that transition specifications given by the DSP meet the
requirements needed by the SDRAM. Clock trace routing plays an important role in the system
design process.
Using IBIS Models for Timing Analysis
13
SPRA839A
Control signals, including ADDRESS, RAS, CAS, CS, WE, etc., are outputs of the DSP. The
switching characteristics of these signals must align with the SDRAM input requirements at the
pins of the SDRAM.
Data signals are both outputs and inputs to the DSP. The switching characteristics of the DSP
data output buffers must align with the SDRAM input requirements. The same signals must have
the SDRAM data output buffers meeting the DSP data input requirements. For most DSPs, the
output data signals have the same switching characteristics as the control signals.
Four critical parameters must be met when designing for a high-speed interface to SDRAM.
These four parameters are:
•
tisu of the SDRAM (input setup time)
•
tih of the SDRAM (input hold time)
•
tisu of the DSP (input setup time)
•
tih of the DSP (input hold time)
Calculations for these parameters are discussed in sections 6.1 through 6.4. For the multiple
data and control pins, the values for C0(Qn) can be averaged to a constant to make calculations
easier, or preferably, you can use the worst case of C0(Qn). This should be taken into account
when figuring acceptable margin values. The values for C0 and B0 must be calculated using an
IBIS simulation package. B0 will vary based on board characteristics and the system
environment. Therefore, accurate accounting of noise and other system margins are necessary
when using the IBIS simulation package to calculate these numbers.
6.1
Input Setup of the SDRAM
An input setup time is required by the control signals during reads and writes to the SDRAM, as
well as the data signals when the DSP is writing to the SDRAM. To verify that setup times to the
SDRAM are met, the margin defined in the following equation must be greater than zero. Refer
to Figure 3 for points B and C.
Tester Load Adjustment
for Control/Data Lines
margin + ECLK Per *
Tester Load Adjustment
for Clock Signal
ǒƪB0,weak (Qn) * C0,weak (Qn)ƫ max ) tPd*Max * ƪB0,strong (Clk) * C0,strong (Clk) ƫǓ * tisu(SDRAM )
The above variables and constants are described in Table 1.
14
Using IBIS Models for Timing Analysis
(9)
SPRA839A
Table 1. SDRAM Input Setup Parameters
SDRAM Input Setup Constants
ECLKPer
:
EMIF clock period
tisu(SDRAM)
:
Input setup requirement by the SDRAM. This parameter is derived from the SDRAM data sheet, and
then adjusted from Vref voltage reference to VIL/VIH voltage reference (see section 4.2).
tpd-max
:
Maximum propagation delay given by the DSP. This parameter is obtained from the DSP data sheet.
C0,weak(Qn)
:
DSP data/control buffer propagation delay of a weak process buffer, measured from t0 to when the
signal crosses the reference voltage using only the DSP test load. Calculated using an IBIS simulation
package, along with DSP IBIS model.
C0,strong(Clk)
:
DSP clock buffer propagation delay of a strong process buffer, measured from t0 to the when the signal
crosses the reference voltage using only the DSP test load. Calculated using an IBIS simulation
package, along with DSP IBIS model.
SDRAM Input Setup Variables
B0,weak(Qn)
:
DSP data/control buffer propagation delay of a weak process buffer, measured from t0 to when the
signal reaches a valid logic level on the board at SDRAM pin (point B). Calculated using an IBIS
simulation package, along with DSP and SDRAM IBIS models.
B0,strong(Clk)
:
DSP clock buffer propagation delay of a strong process buffer, measured from t0 to when the signal
crosses the reference voltage Vref on the board at SDRAM pin (point B). Calculated using an IBIS
simulation package, along with DSP and SDRAM IBIS models.
The input setup of the SDRAM is a minimum requirement; therefore, the sum of all the
parameters on the right side of the equation must be greater than zero. The only variables that
can be adjusted are the clock and signal buffer propagation delays B0(Qn) and B0(Clk). These
are adjusted by varying the trace characteristics, such as length, impedance, etc. In other words,
they can be adjusted by varying line delay Y in Figure 3.
When calculating the setup time to the SDRAM, the worst possible setup time is when the clock
line is fast and the control/data lines are slow. In order to simulate this, a strong clock line is
used in conjunction with a weak control/data line. This assumes that the clock signals are
monotonic and the reflections are minimal.
Figure 12 shows the SDRAM input setup timing graphically.
Clk (at point C
with tester load)
tpd-max
Qn (at point C
with tester load)
B0,strong(Clk) – C0,strong(Clk) tester load adjustment
Clk
(SDRAM pin)
B0,weak(Qn) – C0,weak(Qn) tester load adjustment
tisu(SDRAM) + margin
Qn
(SDRAM pin)
Figure 12. Input Setup of the SDRAM
Using IBIS Models for Timing Analysis
15
SPRA839A
Because of the multiple control and data signals, each trace must be calculated (using the
method discussed above) to find the maximum difference between the board and test load. This
maximum difference will result in the worst-case setup time to the SDRAM. Although all the data
lines may use similar buffers within a given device, the package characteristics cause variations
in the output signal at the pins. When calculating the difference between the board propagation
delay and the test load propagation delay, it is important to use the same pin. Using separate
pins to make this calculation will result in incorrect simulations.
6.2
Input Hold of the SDRAM
An input hold time is also required by the control signals during reads and writes to the SDRAM,
as well as the data signals when the DSP is writing to the SDRAM. To verify that hold times to
the SDRAM are met, the margin defined in the following equation must be greater than zero.
Tester Load Adjustment
for Control/Data Lines
margin + ƪB 0,strong (Q n) * C 0,strong (Q n)ƫ
Tester Load Adjustment
for Clock Signal
min ) t Pd*Min
* ƪ B 0,weak (Clk) * C 0,weak (Clk) ƫ * t ih( SDRAM )
(10)
The above variables and constants are described in Table 2.
Table 2. SDRAM Input Hold Parameters
SDRAM Input Hold Constants
tih(SDRAM)
:
Input hold requirement by the SDRAM. This parameter is derived from the SDRAM data sheet, and
then adjusted from Vref voltage reference to VIL/VIH voltage reference (see section 4.2).
tpd-min
:
Minimum propagation delay given by the DSP. This parameter is obtained from the DSP data sheet.
C0,strong(Qn)
:
DSP data/control buffer propagation delay of a strong process buffer, measured from to when the
signal crosses the reference voltage using only the DSP test load. Calculated using an IBIS
simulation package, along with DSP IBIS model.
C0,weak(Clk)
:
DSP clock buffer propagation delay of a weak process buffer, measured from t0 to when the signal
crosses the reference voltage using only the DSP test load. Calculated using an IBIS simulation
package, along with DSP IBIS model.
SDRAM Input Hold Variables
B0,strong(Qn)
:
DSP data/control buffer propagation delay of a strong process buffer, measured from t0 to when the
signal goes to an invalid logic level on the board at the SDRAM input (point B). Calculated using
an IBIS simulation package, along with DSP and SDRAM IBIS models.
B0,weak(Clk)
:
DSP clock buffer propagation delay of a weak process buffer, measured from t0 to when the signal
crosses the reference voltage on the board at the SDRAM input (point B). Calculated using an IBIS
simulation package, along with DSP and SDRAM IBIS models.
16
Using IBIS Models for Timing Analysis
SPRA839A
The input hold of the SDRAM is a minimum requirement; therefore the sum of all the parameters
on the right side of the equation must be greater than zero. The only variables that can be
adjusted are the clock and signal buffer propagation delays. These are adjusted by varying the
trace characteristics (the delay Y) in Figure 3.
The worst-case input hold to the SDRAM is achieved when the clock signal is slow and the
control/data signals are fast. Assuming monotonic signals and minimal reflections on the traces,
a weak clock buffer and a strong control/data buffer should be used to simulate this worst-case
situation.
Figure 13 shows the SDRAM input setup timing graphically.
Clk (at point C
with test load)
tpd-min
Qn (at test point C
with test load)
B0,weak(Clk) * C0,weak(Clk)
Clk
(at SDRAM pin)
B0,strong(Qn) * C0,strong(Qn) tester load adjustment
tih(SDRAM) + margin
Qn
(at SDRAM pin)
Figure 13. Input Hold of the SDRAM
Because of the multiple control and data signals, each trace must be calculated (using the
method discussed above) to find the minimum difference between the board and test load. This
minimum difference will result in the worst-case hold time to the SDRAM.
6.3
Input Setup of the DSP
DSP reads are different than writes, in the sense that reads have to take into account the
propagation delay of the SDRAM as well as the board route delays to and from the DSP. The
DSP input setup is required only when the SDRAM outputs data to the DSP. To verify that setup
times to the DSP are met, the margin defined in the following equation must be greater than
zero.
Tester Load Adjustment
for Data Lines
ǒ
margin + ECLK Per * ƪB 0,weak (Q n) * C 0,weak (Q n)ƫ
Tester Load Adjustment
for Clock Signal
max
Ǔ
) t Acc ) ƪ B 0,weak (Clk) * C 0,weak (Clk) ƫ * t isu( DSP )
(11)
The above variables and constants are described in Table 3.
Using IBIS Models for Timing Analysis
17
SPRA839A
Table 3. DSP Input Setup Parameters
DSP Input Setup Constants
ECLKPer
:
EMIF clock period
tisu(DSP)
:
Input setup requirement by the DSP. This parameter is derived from the DSP data sheet, and then
adjusted from Vref voltage reference to VIL/VIH voltage reference (see section 4.2).
tAcc
:
Maximum access time given by the SDRAM. This parameter is obtained from the SDRAM data sheet.
C0,weak(Qn)
:
SDRAM data buffer propagation delay of a weak process buffer, measured from when the SDRAM
output buffer is enabled/disabled to when the signal crosses the reference voltage using only the
SDRAM test load. Calculated using an IBIS simulation package, along with SDRAM IBIS model.
C0,weak(Clk)
:
DSP clock buffer propagation delay of a weak process buffer, measured from t0 to when the signal
crosses the reference voltage using only the DSP test load. Calculated using an IBIS simulation
package, along with DSP IBIS model.
DSP Input Setup Variables
B0,weak(Qn)
:
SDRAM Data buffer propagation delay of a weak process buffer, measured from when the SDRAM
output buffer is enabled to when the signal reaches a valid logic level on the board at the pin of
the DSP. Calculated using an IBIS simulation package, along with SDRAM and DSP IBIS models.
B0,weak(Clk)
:
DSP clock buffer propagation delay of a weak process buffer, measured from t0 to when the signal
crosses the reference voltage on the board at the SDRAM pin. Calculated using an IBIS simulation
package, along with SDRAM and DSP IBIS models.
The input setup of the DSP is a minimum requirement; therefore the sum of all the parameters
on the right side of the equation must be greater than zero. The only variables that can be
adjusted are the clock and signal buffer propagation delays. These are adjusted by varying the
trace characteristics, such as length, impedance, etc.
In the case of DSP reads from SDRAM, the worst-case input setup occurs when both the clock
buffer and the SDRAM data buffers are slow. This means that weak buffers should be used for
calculation purposes. Again, the assumption of minimal reflections and signal monotonicity
remains.
Figure 14 shows the DSP input setup timing graphically.
Clk (at point C with
DSP test load)
tAcc(SDRAM)
Qn (at point C with
SDRAM test load)
B0,weak(Clk) * C0,weak(Clk)
Clk
(at SDRAM pin)
B0,weak(Qn) * C0,weak(Qn)
tisu(DSP) + margin
Qn
(at DSP pin)
Figure 14. Input Setup of the DSP
18
Using IBIS Models for Timing Analysis
SPRA839A
Because of the multiple data signals, each trace must be calculated (using the method
discussed above) to find the maximum difference between the board and test load. This
maximum difference will result in the worst-case setup time to the DSP.
6.4
Input Hold of the DSP
To verify that hold times to the DSP are met, the margin defined in the following equation must
be greater than zero.
Tester Load Adjustment
for Data Lines
margin + ƪB 0,strong (Q n) * C 0,strong (Q n)ƫ
Tester Load Adjustment
for Clock Signal
min ) t oh
) ƪ B 0,strong (Clk) * C 0,strong (Clk) ƫ * t ih( DSP )
(12)
The above variables and constants are described in Table 4.
Table 4. DSP Input Hold Parameters
DSP Input Hold Constants
tih(DSP)
:
Input hold requirement by the DSP. This parameter is derived from the DSP data sheet, and then
adjusted from Vref voltage reference to VIL/VIH voltage reference (see section 4.2).
toh
:
Minimum hold time given by the SDRAM. This parameter is obtained from the SDRAM data sheet.
C0,strong(Qn)
:
SDRAM data buffer propagation delay of a strong process buffer, measured from when the SDRAM
output buffer is enabled/disabled to when the signal crosses the reference voltage using only the
SDRAM test load. Calculated using an IBIS simulation package, along with SDRAM IBIS model.
C0,strong(Clk)
:
DSP clock buffer propagation delay of a strong process buffer, measured from t0 to when the signal
crosses the reference voltage using only the DSP test load. Calculated using an IBIS simulation
package, along with DSP IBIS model.
DSP Input Hold Variables
B0,strong(Qn)
:
SDRAM data buffer propagation delay of a strong process buffer, measured from when the SDRAM
data buffer is disabled to the when the signal goes to an invalid logic level on the board at pin of
the DSP. Calculated using an IBIS simulation package, along with DSP and SDRAM IBIS models.
B0,strong(Clk)
:
DSP clock buffer propagation delay of a strong process buffer, measured from t0 to when the signal
crosses the reference voltage on the board at the pin of the DSP. Calculated using an IBIS
simulation package, along with DSP and SDRAM IBIS models.
The input hold of the DSP is a minimum requirement; therefore the sum of all the parameters on
the right side of the equation must be greater than zero. The only variables that can be adjusted
are the clock and signal buffer propagation delays. These are adjusted by varying the trace
characteristics.
Input hold times to the DSP are worse when the clock line and the signal lines are fast.
Therefore, strong buffers should be used in the calculation of DSP input hold time. Again, the
assumption of minimal reflections and signal monotonicity remains.
Figure 15 shows the DSP input hold timing graphically.
Using IBIS Models for Timing Analysis
19
SPRA839A
Clk (at point C with
DSP test load)
toh(SDRAM)
Qn (at point C with
SDRAM test load)
B0,strong(Clk) * C0,strong(Clk)
Clk
(at SDRAM pin)
tih(DSP) + margin
B0,strong(Qn) * C0,strong(Qn)
Qn
(at DSP pin)
Figure 15. Input Hold of the DSP
Because of the multiple data signals, each trace must be calculated (using the method
discussed above) to find the minimum difference between the board and test load. This
minimum difference will result in the worst-case hold time to the DSP.
7
Summary of AC Timing Analysis Procedures
This section provides a summary of the procedures for AC timing analysis according to the
method discussed in this application report. The subsections provide detailed explanation of the
three steps involved: gathering information, IBIS simulations, and analysis.
7.1
Gathering Information
The first step in AC timing analysis is to gather all of the relevant information, including:
1. Data sheets for the DSP and SDRAM
2. IBIS models for the DSP and SDRAM
3. Board layout and characteristics
Figure 16 shows the board layout and trace characteristics for an example interface. The Rs in
the figure are series termination resistors used to achieve signal integrity. The actual value
varies depending on the board and input/output (I/O) buffer.
DSP EMIF
SDRAM
0.5 in
Rs
0.5 in
Rs
0.5 in
Rs
1 in
ECLKOUT
Control/
address
CLK
ED[31:0]
Ranges from 0.5 to 2.5 in
Control/
address
Ranges from 0.5 to 2.5 in
DQ[31:0]
NOTE: Assume that all traces in this example have a characteristic impedance of Z0 = 50W, and require a 33-W series termination
resistor (Rs) for signal integrity. Actual value of Rs depends on trace and input/output buffer characteristics.
Figure 16. Example DSP-SDRAM Interface Board Characteristics
20
Using IBIS Models for Timing Analysis
SPRA839A
7.2
IBIS Simulations
Before performing IBIS simulations on the DSP-SDRAM interface, you should first modify the
IBIS models’ VIL and VIH levels to account for noise margin, as discussed in section 5. Edit Vinl
to 0.6 V, and Vinh to 2.5 V.
7.2.1
IBIS Simulations for DSP Outputs on the Board
The DSP outputs ECLKOUT and control/address to the SDRAM. In addition, the DSP outputs
data ED[31:0] for a DSP write. Each of these signals can be represented in the IBIS package, as
shown in Figure 17.
A
B
Rs
t0
Board trace
Board trace
DSP IBIS
model (output)
SDRAM IBIS
model (input)
Figure 17. IBIS Representation of DSP Output on a Board
Perform IBIS simulations to obtain the absolute timing at point B (parameter B0) at the SDRAM
pin. For the clock signal, which must be monotonic at point B, measure the time B0 at the
reference voltage, Vref. For data/control, which may not be monotonic at point B, measure the
time B0 at the new reference voltage VIL/VIH, as discussed in section 4.
You should perform simulations twice: once with the weakest output drive strength to obtain
parameter (B0,weak), and once with the strongest output drive strength to obtain parameter
(B0,strong). See also section 3.3 for considerations on variations between the pins.
In summary, this step provides measurements for these parameters:
B0,strong(Clk) for Table 1 and Table 4
B0,weak(Clk) for Table 2 and Table 3
B0,strong(control/address) for Table 2 and Table 4
B0,weak(control/address) for Table 1 and Table 3
B0,strong(Qn) for Table 2
B0,weak(Qn) for Table 1
7.2.2
IBIS Simulations for DSP Outputs With Test Load
For each of the signals in section 7.2.1, the DSP data sheet provides measurement with the test
load. Figure 18 shows how this is represented in the IBIS package.
C
t0
Transmission line
Cref
DSP IBIS model
(output)
Tester load circuit
(see Note)
NOTE: Tester load circuit differs on the various devices. Refer to the device data sheet for the exact tester load circuit.
Figure 18. IBIS Representation of DSP Output With Test Load
Using IBIS Models for Timing Analysis
21
SPRA839A
Perform IBIS simulations to obtain the absolute timing at point C (parameter C0) with the DSP
test load. Measure the time C0 at the data sheet reference voltage, Vref.
You should perform simulations twice: once with the weakest output drive strength to obtain
parameter (C0,weak), and once with the strongest output drive strength to obtain parameter
(C0,strong). See also section 3.3 for considerations on variations between the pins.
In summary, this step provides measurements for these parameters:
C0,strong(Clk) for Table 1 and Table 4
C0,weak(Clk) for Table 2 and Table 3
C0,strong(control/address) for Table 2 and Table 4
C0,weak(control/address) for Table 1 and Table 3
C0,strong(Qn) for Table 2
C0,weak(Qn) for Table 1
7.2.3
IBIS Simulations for SDRAM Outputs on the Board
The SDRAM outputs data DQ[31:0] for a DSP read. Each of these signals can be represented in
the IBIS package as shown in Figure 19.
B
A
Rs
Board trace
Board trace
DSP IBIS
model (input)
SDRAM IBIS
model (output)
Figure 19. IBIS Representation of SDRAM Output on a Board
Perform IBIS simulations to obtain the absolute timing at point B (parameter B0) at the DSP pin.
Because the data signal may not be monotonic at the DSP pin (point B), measure the time B0 at
the new reference voltage VIL/VIH, as discussed in section 4.
You should perform simulations twice: once with the weakest output drive strength to obtain
parameter (B0,weak), and once with the strongest output drive strength to obtain parameter
(B0,strong). See also section 3.3 for considerations on variations between the pins.
In summary, this step provides measurements for these parameters:
B0,strong(Qn) for Table 4
B0,weak(Qn) for Table 3
7.2.4
IBIS Simulations for SDRAM Outputs With Test Load
For the data signals in section 7.2.4, the SDRAM data sheet provides measurement with the test
load. Figure 20 shows how this is represented in the IBIS package.
22
Using IBIS Models for Timing Analysis
SPRA839A
C
t0
Cref
SDRAM IBIS
model (output)
Tester load circuit
(see Note)
NOTE: Tester load circuit differs on the various devices. Refer to the device data sheet for the exact tester load circuit.
Figure 20. IBIS Representation of SDRAM Output With Test Load
Perform IBIS simulations to obtain the absolute timing at point C (parameter C0) with the
SDRAM test load. Measure the time C0 at the data sheet reference voltage, Vref.
You should perform simulations twice: once with the weakest output drive strength to obtain
parameter (C0,weak), and once with the strongest output drive strength to obtain parameter
(C0,strong). See also section 3.3 for considerations on variations between the pins.
In summary, this step provides measurements for these parameters:
C0,strong(Qn) for Table 4
C0,weak(Qn) for Table 3
7.3
Calculations
With the data gathered in the above sections, you are now ready to perform timing analysis, as
discussed in section 6.
7.3.1
Input Setup of the SDRAM
Fill out Table 1 in section 6.1:
•
Enter the desired EMIF clock period ECLKPer.
•
Enter the input setup requirement derived from the SDRAM data sheet. Do not directly input
the value from the SDRAM data sheet. Instead, adjust the data sheet value by translating it
from voltage reference Vref to VIL/VIH as discussed in section 4. For example, assuming that
the SDRAM datasheet specifies:
–
Tester input slew rate or transition time of 1 V/ns at the input pin
–
Reference voltage (Vref) is 1.5 V.
–
VIL = 0.8 V, VIH = 2.0 V
–
Input setup requirement (tisu) of 2 ns referenced at Vref
Using IBIS Models for Timing Analysis
23
SPRA839A
The adjusted SDRAM input setup requirement referenced at VIL/VIH is calculated according
to the formula in Figure 10:
–
t1 = tisu – (1/m) * (Vref – VIL) = 2 – (1/1) * (1.5 – 0.8) = 1.3 ns
–
t2 = tisu – (1/m) * (Vref – VIH) = 2 – [1/(–1)] * (1.5 – 2.0) = 1.5 ns
t2 is a larger number, and therefore a more stringent new tisu requirement. Enter t2 into Table 1.
•
Enter the tpd-max from the DSP data sheet.
•
Enter the B0 and C0 parameters obtained in sections 7.2.1 and 7.2.2.
Then, calculate the SDRAM input setup margin using the formula in section 6.1.
7.3.2
Input Hold of the SDRAM
Fill out Table 2 in section 6.2:
•
Enter the input hold requirement derived from the SDRAM data sheet. Do not directly input
the value from the SDRAM data sheet. Instead, adjust the data sheet value by translating it
from voltage reference Vref to VIL/VIH, as discussed in section 4.
•
Enter the tpd-min from the DSP data sheet.
•
Enter the B0 and C0 parameters obtained in sections 7.2.1 and 7.2.2.
Then, calculate the SDRAM input hold margin using the formula in section 6.2.
7.3.3
Input Setup of the DSP
Fill out Table 3 in section 6.3:
•
Enter the desired EMIF clock period ECLKPer.
•
Enter the input setup requirement derived from the DSP data sheet. Do not directly input the
value from the DSP data sheet. Instead, adjust the data sheet value by translating it from
voltage reference Vref to VIL/VIH, as discussed in section 4.
•
Enter the tAcc from the SDRAM data sheet.
•
Enter the B0 and C0 parameters obtained in sections 7.2.1 through 7.2.4.
Then, calculate the DSP input setup margin using the formula in section 6.3.
7.3.4
Input Hold of the DSP
Fill out Table 4 in section 6.4:
•
Enter the input hold requirement derived from the DSP data sheet. Do not directly input the
value from the DSP data sheet. Instead, adjust the data sheet value by translating it from
voltage reference Vref to VIL/VIH, as discussed in section 4.
•
Enter the toh from the SDRAM data sheet.
•
Enter the B0 and C0 parameters obtained in sections 7.2.1 through 7.2.4.
Then, calculate the DSP input hold margin using the formula in section 6.4.
24
Using IBIS Models for Timing Analysis
SPRA839A
8
Conclusion
Using the equations discussed in this application report, IBIS models and simulations can be
used to reflect timings for point-to-point connections between an SDRAM and a DSP. Iterations
on these equations may be necessary to obtain desired signal integrity and the proper timings
for both setup and hold to the SDRAM and the DSP. This technique is not limited to SDRAMs or
the EMIF interface. All DSP signals have characteristic setup and hold times that must be
adhered to. Using the techniques discussed in this application report, IBIS analysis can used to
determine proper timing relations for all relevant signals.
An understanding of the tester is needed to properly back calculate timings, to correct for
variations in loading on the signals. Noise level margins can be accounted for by modifying the
valid logic levels. The equations discussed in this application report give a representation of how
much margin can be expected. Acceptable margin levels must be determined based on system
environment and operating conditions.
Using IBIS Models for Timing Analysis
25
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