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Texas Instruments EDRAM Memory Controller for the TMS320C31 DSP Application Report Application notes
EDRAMtMemory Controller for
the TMS320C31 DSP
Application
Report
1998
Digital Signal Processor Solutions
Printed in U.S.A., January 1998
SPRA172
EDRAMtMemory Controller for the
TMS320C31 DSP
Enhanced Memory Systems
1850 Ramtron Drive, Colorado Springs, CO 80921
web: http://www.edram.com
SPRA172
January 1998
Printed on Recycled Paper
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Copyright  1998, Texas Instruments Incorporated
Contents
1
EDRAM Controller Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
2
EDRAM Controller Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
3
Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
iii
List of Figures
1
2
3
4
5
6
7
TMS320C31 System Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
EDRAM Controller Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Address Multiplexer Using Two 74FCT541CT Buffers . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
EDRAM Controller State Machine . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
TMS320C31 Read-Miss and Read-Hit Cycles @ 50 MHz . . . . . . . . . . . . . . . . . . . . . 14
TMS320C31 Refresh After Idle Cycle @ 50 MHz . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
TMS320C31 Write Cycle – 50 MHz . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
1
2
3
TMS320C31 Read-Miss and Read-Hit Cycles @ 50 MHz . . . . . . . . . . . . . . . . . . . . . 15
TMS320C31 Refresh After Idle Cycle @ 50 MHz . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
TMS320C31 Write Cycle – 50 MHz . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
List of Tables
iv
EDRAMt Memory Controller for the TMS320C31 DSP
ABSTRACT
This report provides an overview of a controller chip set to improve processor
memory management and transactions while using the Texas Instruments (TI )
TMS320C31 digital signal processor (DSP). This application uses a minimum
number of wait states which increases processor throughput.
t
TI is a trademark of Texas Instruments Incorporated
EDRAM is a registered trademark of Enhanced Memory Systems, Inc..
EDRAM Memory Controller for the TMS320C31 DSP
1
EDRAM Controller Design
1 EDRAM Controller Design
This Enhanced DRAM controller design supports TMS320C31 DSP
memory transactions with a minimum of wait states. This EDRAM controller
is designed to support one EDRAM bank of 2M bytes; however, memory size
can expanded by adding additional control outputs to the logic. Figure 1
shows a functional block diagram of the TMS320C31 DSP System. The
TMS320C31 DSP primary-bus interface can be programmed to control wait
states and hold operations. The memory-control register for the local bus is
programmed with the following parameters:
•
•
•
SWW is programmed to respond only to the external RDY input for wait
states (SWW=00). The internal RDY wtcnt is ignored.
WTCNT does not need to be programmed since software
programmable wait states are not used.
BNKCMP is set as shown below:
EDRAM
MSBs Defining a Bank
Bank Size
BNKCMP
512K x 8
23–8
256
10000
The TMS320C31 supports the following memory transactions:
• 32-bit page-read hit
• 32-bit page-read miss
• 32-bit write (hit or miss)
To support these bus transactions, the EDRAM controller must interface with
the following processor control and address signals:
• A18–A0 – address bus
• STRB – external-access strobe
• R/W – read-write-mode outputs
• RDY – ready input
• RESET – reset input
• H1CLK – processor-clock output
• TCLK0 – timer zero output clock/pulse
2
SPRA172
EDRAM Controller Design
RESET
H1CLK
TCLK0
D(31-0)
TMS320C31
STRB
R/W
RDY
A(23–X)
STRB
A(7-0)
A(15–8)
COLSEL
EDRAM Controller
Column
Buffer
26V12
From ADDRESS
DECODER
WRG
RE
F
ROWSEL
CAL
Row
Buffer
WE
A(18-16)
MA(7-0)
A(10-8)
(4) DM2203-12
512K x 8
S
Figure 1. TMS320C31 System Block Diagram
EDRAM Memory Controller for the TMS320C31 DSP
3
EDRAM Controller Design
The controller generates the following signals to control the EDRAM:
•
•
•
•
•
•
•
•
ROWSEL – multiplexed row-address enable
COLSEL – multiplexed column-address enable
RE – row enable
CAL – column-address strobe
WE – write enable
WRG – combined W/R and G
F – refresh
S – chip select
The EDRAM W/R and G control lines are tied together to form WRG. The
ROWSEL, COLSEL, CAL, WE, WRG, and F logic signals are supplied from
the 26V12 PLD.
S is an enable pin for the EDRAM and should be active for the desired
page(s) of DSP memory. Because of the limited number of outputs of the
PAL26V12, S is not included within the PAL. A simple decode might be to
connect STRB to S where all external memory accesses enable the
EDRAM, or in combination with an upper address line. Note that disabling
the EDRAM will also lower the EDRAM power consumption. Optionally, the
S input signal can be tied to ground if EDRAM power consumption is not an
issue.
4
SPRA172
EDRAM Controller Functional Description
2 EDRAM Controller Functional Description
This section describes the EDRAM controller block diagram shown in
Figure 2. The refresh counter is formed by using an internal timer in the
TMS320C31 DSP to generate a refresh signal every 64 µs for the state
machine. This refresh signal triggers an F refresh on the next available bus
cycle. Up to three wait states can be inserted for the processor while a bus
transaction is occurring.
Figure 3, the address multiplexer, selects a row and a column address for
the EDRAM multiplex address lines under control of the state machine. The
multiplexer is implemented using the two 74FCT541CT 8-bit buffer chips.
These chips were selected for their short throughput delay time (4.1 ns) and
short select-delay time (5.8 ns), respectively. A column address is
connected to pins A7–A0 for 512K x 8 EDRAM. The row address comprises
the 11 local address bits above the column address. Address lines A10–A8
of the EDRAM are connected directly to A18–A16 of the TMS320C31 DSP.
During column select times, the upper address lines are ignored so there is
no need to feed these address lines through a buffer.
Address
Bus
A0–A18
Address
Buffers
MA(10–8)
MA(7–0)
EDRAM
RDY
Row/Column
Select
H1CLK,
STRB, R/W, TCLK0
RESET
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
Combinational
Logic
State
Machine
CAL, WE, WRG, RE, F
Figure 2. EDRAM Controller Block Diagram
EDRAM Memory Controller for the TMS320C31 DSP
5
EDRAM Controller Functional Description
A(15–8)
A(7–0)
ÁÁÁÁÁÁ
ÁÁÁÁÁÁ
ÁÁÁÁÁÁ
ROWSEL
FCT541CT
ÁÁÁÁÁÁ
ÁÁÁÁÁÁ
ÁÁÁÁÁÁ
COLSEL
FCT541CT
MA(7–0)
Figure 3. Address Multiplexer Using Two 74FCT541CT Buffers
The state machine operates synchronously with the rising edge of H1CLK.
STRB*R/W
STRB
Read
Miss
Idle
STRB*R/W
R1
REFRESH
I1
STRB*R/W
STRB*R/W
Write
W1
F1
REFRESH
W2
STRB
STRB*R/W
REFRESH
F2
R2
Read
Hit
Figure 4. EDRAM Controller State Machine
6
SPRA172
EDRAM Controller Functional Description
The following memory-control sequences are selected, based on
control-input-line status. Read and write sequences are described. All logic
states are determined at the rising edge of H1CLK.
• Reset Sequence – When RESET is at logic 0, the processor is in the
reset state. The EDRAM controller continuously executes F refresh
cycles until RESET returns to logic 1 level. This meets the EDRAM
initialization requirements of eight F refresh cycles during start up. It is
assumed that a startup control program is run immediately following a
reset. This program must configure the TMS320C31 to perform two
read-miss cycles to different row addresses for each internal EDRAM
bank. Row address bits A8 and A9 define the four internal EDRAM
banks. This startup procedure must be performed for proper EDRAM
operation.
• Page-read-miss sequence – Starting from the idle state, when STRB is
at logic 0 and R/W is at logic 1, a page-read-miss sequence is executed.
The row address is selected, and WRG signal is set to logic 0. The RE
signal is then clocked to load a new page of memory into the internal
DRAM cache column, which takes 30-ns. RDY is brought to logic 1 at
the start of cycle R1 to insert a wait state for the processor. Data is
available to the processor at the end of cycle two. Because of the
TMS320C31 addressing system, one wait state is inserted when a read
cycle follows a write cycle.
• Page-read-hit sequence – Starting from the R1 state, when STRB is at
logic 0 and R/W is logic 1, a page-read-hit sequence is executed. The
column address is selected, and WRG is brought to logic 0 to gate data
onto the data bus. The EDRAM can support back-to-back page reads
from cache in zero wait states. The TMS320C31 processor holds STRB
at logic 0 during back-to-back page hit reads since the programmable
bank switching feature is being used. On a page-read miss, STRB goes
to logic 1, which also causes an idle state to be inserted.
• Write sequence – If STRB is at logic 0 and R/W is also at logic 0, a write
sequence is executed. The row address is selected and write-data
operation is stable and the WE signal is clocked to post the write data
operation into an internal latch. When CAL falls, write data is written to
the EDRAM array. Following the write-data operation, RE is brought to
logic 1 to terminate the write-data cycle. The write operation is
completed in two cycles or zero wait states. The EDRAM supports
back-to-back writes in two cycles or zero wait states.
EDRAM Memory Controller for the TMS320C31 DSP
7
EDRAM Controller Functional Description
•
•
•
•
Refresh sequence – If TCKL0 input is at logic 1, an F refresh sequence
is performed after any current memory cycles are completed. The
TCKL0 output is at logic 1 for 40 ns and it then goes to logic 0 and
remains at logic 0 until the next refresh period. The F pin is brought to
logic 0 and RE is clocked to perform an internal refresh using the
internal-refresh counter. A refresh sequence is executed every 62-µs.
During a refresh sequence, RDY is held at logic 1 to cause the processor
to wait. The processor may need to wait for up to three wait states to
complete the current memory transaction.
Idle – If STRB is at logic 1 (except at the start of the W2 state), this
indicates the cycle is an idle cycle. The WRG is brought to logic 1 to
disable the EDRAM outputs from the data bus until the next active cycle.
Chip select (S) – The S is generated using a NAND, NOR or equivalent
gate to decode the Q2–Q0 state machine outputs. S is brought to
logic 1 during the idle and refresh states to reduce power consumption.
This circuit is optional and S can be tied to ground if reduced power
consumption is not desired.
Programming the TMS320C31 DSP Timer – The timer global-control
register must be programmed immediately after power up so that the
refresh counter can be initialized properly. The TCLK0 output is used to
generate a 40-ns minimum high pulse every 62-µs. The bit values to be
programmed are as follows:
CLKSRC = 1
f(Timer clock)
12.5MHz
FUNC
= 1
period register ____________ = ________ =
C/P
= 0
fINT
16KHz
I/O
= 1
HLD
= 1
INV
= 0
Period Register Value = 780d
780
The remaining bit fields can remain at their default values after power up.
The interrupt-enable register does not need to be programmed to generate
an interrupt when timer zero generates a high pulse every 62-µs. The timer
must be started immediately after power up by setting the GO/HLD bits in
the timer-global-control register to 11. When the counter value equals the
value set in the period register, a 40-ns logic 1 pulse is output on TCLK0 pin.
This logic 1 pulse causes the REF_PENDING register output-logic level to
remain at logic 1 starting with the next rising edge of H1CLK. This level is
cleared only after a refresh sequence is performed. The TMS320C31 DSP
timer does not need to be restarted and no interrupt is generated. A refresh
sequence is not started until after the second cycle of a read-miss or write
sequence, if one is in progress.
8
SPRA172
EDRAM Controller Functional Description
Timing of the EDRAM controller is shown in Figure 5, Figure 6, and Figure 7.
The EDRAM controller operates with a 50-MHz TMS320C31 DSP system
using the 12-ns version of the EDRAM as shown. The EDRAM–controller
parameters are for a 26V12-7 programmable logic device (PLD) and
Pericom 74FCT541CT 8-bit buffers. The TMS320C31DSP timing
parameters are from the TMS320C31 DSP Data Manual (literature number
SPRU031D).
EDRAM Memory Controller for the TMS320C31 DSP
9
Summary
3 Summary
An EDRAM controller for the 50 MHz and 60 MHz versions of the TI
TMS320C31 DSP can be implemented using a simple PLD and two Pericom
74FCT541CT data buffers. The controller supports one EDRAM bank of 2M
bytes (using DM2203 components) and can be expanded easily to include
more memory. The EDRAM system as shown in this application report
achieves zero wait states on read-hit cycles and on all write cycles.
System cost is reduced significantly by using an internal timer in the
TMS320C31 to generate the refresh signals. The EDRAM achieves near
12 ns static RAM (SRAM) performance, while providing much lower memory
cost at 4M-bit density. The EDRAM/TMS320C31 DSP provides an excellent
ratio of cost/performance for DSP applications.
Example 1. PLD Equations
*
*
*
*
TMS320C31 PLD Equations – 25 MHz Bus
26V12–7 PLD
Revision 2.0
Vantis MACH–XL 5.0 Compiler
INPUT H1CLK;
INPUT TCLK0;
LOW_TRUE INPUT RESET;
LOW_TRUE INPUT RW;
LOW_TRUE INPUT STRB;
LOW_TRUE
LOW_TRUE
LOW_TRUE
LOW_TRUE
LOW_TRUE
LOW_TRUE
LOW_TRUE
LOW_TRUE
OUTPUT
OUTPUT
OUTPUT
OUTPUT
OUTPUT
OUTPUT
OUTPUT
OUTPUT
RDY;
RE;
CAL;
WE;
WRG;
F;
ROWSEL;
COLSEL;
NODE q2..q0 CLOCKED_BY H1CLK;
D_FLOP NODE REF_PENDING CLOCKED_BY H1CLK;
MACRO ON
MACRO OFF
1;
0;
* Equations
* We need to store the current cycle state to generate EDRAM
* timings
STATE_MACHINE TMS320C31
STATE_BITS [q2..q0]
CLOCKED_BY H1CLK;
10
SPRA172
Summary
STATE IDLE:
REF_PENDING = OFF;
RDY = STRB * RW;
RE = OFF;
CAL = OFF;
WE = OFF;
WRG = OFF;
F = OFF;
ROWSEL = ON;
COLSEL = OFF;
IF (RESET) THEN
GOTO REFRESH1;
ELSE
IF (TCLK0) THEN
GOTO REFRESH1;
ELSE
IF (STRB) THEN
IF (RW) THEN
GOTO WRITE1;
ELSE
GOTO READ1;
END IF;
END IF;
END IF;
END IF;
STATE REFRESH1 :
REF_PENDING = OFF;
RDY = OFF;
RE = /H1CLK;
CAL = OFF;
WE = OFF;
WRG = OFF;
F = ON;
ROWSEL = OFF;
COLSEL = OFF;
GOTO REFRESH2;
STATE REFRESH2 :
REF_PENDING = OFF;
RDY = OFF;
RE = H1CLK;
CAL = OFF;
WE = OFF;
WRG = OFF;
F = OFF;
ROWSEL = OFF;
COLSEL = OFF;
GOTO IDLE;
EDRAM Memory Controller for the TMS320C31 DSP
11
Summary
STATE READ1 :
RDY = /H1CLK;
RE = /H1CLK;
CAL = OFF;
WE = OFF;
WRG = ON;
F = OFF;
ROWSEL = H1CLK;
COLSEL = /H1CLK;
REF_PENDING = TCLK0;
GOTO READ2;
STATE READ2 :
RDY = /H1CLK;
RE = /H1CLK;
CAL = OFF;
WE = OFF;
WRG = ON;
F = OFF;
ROWSEL = OFF;
COLSEL = ON;
REF_PENDING = TCLK0
IF (RESET) THEN
GOTO IDLE
ELSE IF (TCLK0 + REF_PENDING) THEN
GOTO REFRESH1;
ELSE IF (STRB * /RW) THEN
GOTO READ2;
ELSE
GOTO IDLE;
END IF;
STATE WRITE1 :
RDY = OFF;
RE = /H1CLK;
CAL = OFF;
WE = /H1CLK;
WRG = OFF;
F = OFF;
ROWSEL = H1CLK;
COLSEL = /H1CLK;
REF_PENDING = TCLK0;
GOTO WRITE2;
STATE WRITE2 :
RDY = STRB * RW;
RE = H1CLK;
CAL = H1CLK;
WE = H1CLK;
WRG = OFF;
F = OFF;
ROWSEL = OFF;
COLSEL = ON;
12
SPRA172
Summary
REF_PENDING = TCLK0;
IF (RESET) THEN
GOTO IDLE;
ELSE IF (TCLK0 + REF_PENDING)
THEN GOTO REFRESH1;
ELSE IF (/STRB * RW)
THEN GOTO WRITE1;
ELSE IF (STRB * /RW)
THEN GOTO READ1;
ELSE IF (/STRB * /RW)
THEN GOTO IDLE;
ELSE GOTO IDLE;
END IF;
END TMS320C31;
EDRAM Memory Controller for the TMS320C31 DSP
13
Summary
0 ns
STATE
50 ns
100 ns
TMS320C31 Read Miss + Read Hit Cycle – 50 MHz
1
2
3
IDLE
R1
150 ns
200 ns
R3
R2
IDLE
H1CLK
tSTRB
tSTRB
STRB
tRWV
tRWV
R/W
tADDR
tADDR
Address 1
A[0:23]
Address 2
tCO
tRH
tRSU
tCO
tCO
tCO
tCO
tRSU
tRH
tRH
tCO
RDY
tCO
tCO
ROWSEL
tCO
tCO
COLSEL
tCO
tCO
tC
tASR
tRE
tRAH
tRP
RE
tCOBUF
Row Addr.
MA[0:8]
tCOBUF
tCOBUF
tPDBUF
Col Address1
Col Address2
tMSU
tDSU
tCO
WR(G)
tAC
tDH
tDH
tDSU
tGQV
DATA1
D[0:31]
tCO
tAC
DATA2
WE
CAL
Figure 5. TMS320C31 Read-Miss and Read-Hit Cycles @ 50 MHz
14
SPRA172
Summary
Table 1. TMS320C31 Read-Miss and Read-Hit Cycles @ 50 MHz
NO.
NAME
FORMULA
MIN
MAX
MARGIN
5
COMMENTS
1
V
tASR
5
Setup time, row address
3
C
tRSU
6
2
V
tRAH
1,5
4
C
tRH
0
6
<4.><4.><4.>
Hold time, RDY after H1 high
5
C
tASR
5
5
<7.>
Setup time, row address
6
D
tSTRB
4
4
Valid time, H1CLK to STRB
7
D
tADDR
9
9
Valid time, H1CLK to address
8
D
tRWV
4
4
9
C
tRE
30
30
<8.>
Active time, row enable
10
C
tRAH
1
1
<3.>
Hold time, row enable
11
C
tC
55
55
<7.>
Cycle time, row enable
12
D
tAC
12
12
13
D
tGQV
5
14
C
tRP
20
20
<2.>
Precharge time, row
15
C
tMSU
5
5
<13.>
Setup time, F and W/R mode select
16
D
tCOBUF
6
6
17
C
tDSU
10
10
18
C
tDH
0
19
D
tPDBUF
20
D
tCO
5
<8.><8.><8.>
1,5
Setup time, RDY before H1 high
Hold time, row address
Valid time, H1CLK to R/W
12
Access time, column address
5
Access time, output enable
6
Delay time, clock to output
<6.><5.>
Setup time, ’C31 data
0
<3.>
Hold time, ’C31 data
4
4
4 <3.><3.>
Delay time, propagation
4,6
4
6
Delay time, clock to output
EDRAM Memory Controller for the TMS320C31 DSP
15
Summary
0 ns
25 ns
50 ns
IDLE
STATE
75 ns
125 ns
100 ns
1
2
F1
F2
H1CLK
STRB
R/W
A[0:23]
tRH
tRH
tRSU
tRSU
RDY
ROWSEL
tCO
tCO
COLSEL
tCO
tC
tMH
tRE
tRP
RE
tCO
tCO
F
CAL(WE)
MA[0:8]
WR(G)
D[0:31)
Figure 6. TMS320C31 Refresh After Idle Cycle @ 50 MHz
16
SPRA172
Summary
Table 2. TMS320C31 Refresh After Idle Cycle @ 50 MHz
NAME
NO.
1
V
2
V
3
C
4
C
5
C
6
C
7
C
8
C
9
C
10
D
FORMULA
MIN
MAX
MARGIN
COMMENTS
tASR
tRAH
5
5
Setup time, row address
1
1
Hold time, row address
tRSU
tRH
6
6
<3.><2.>
Setup time, RDY before H1 high
0
0
<14><8.>
Hold time, RDY after H1 high
tRE
tC
30
30
<8.>
Active time, row enable
55
55
<3.>
Cycle time, row enable
tMSU
tMH
5
5
<13.>
Setup time, F and W/R mode select
5
5
<13.>
Hold time, F and W/R mode select
tRP
tCO
20
20
<–2.>
Precharge time, row
4,6
4
6
Delay time, clock to output
EDRAM Memory Controller for the TMS320C31 DSP
17
Summary
0 ns
STATE
50 ns
100 ns
TMS320C31 Write Cycle – 50 MHz
1
2
3
W1
W2
W1
IDLE
150 ns
200 ns
W2
H1CLK
tSTRB
tSTRB
tSTRB
tSTRB
STRB
tRWV
tRWV
R/W
tAddr
tADDR
Address 1
A[0:23]
tPD
tADDR
Address 2
tCO
tRH
tRSU
tRSU
tRH
RDY
tCO
tCO
tCO
tCO
ROWSEL
tCO
tCO
tCO
tCO
COLSEL
tCO
tCRP
tASR
tCO
tRE
tCO
tRP
tCHR
tC
tCO
tCHR
tRAH
tASR
RE
ttCO
CO
tRAH
tCO
tPC
tCO
tCAH
tCHW
tASC
tCO
tCAE
CAL
tCO
tCO
tWC
tWP
tWI
tSTRB
WE
tCOBUF
tBOFF
tBOFF
tCOBUF
Col Address 1
MA[0:8]
Row Address
WR(/G)
tCOBUF
tCOBUF
tDV
tDS
tDH31
tDH
Col Address 2
Row Address
tDV
tDH31
tDS
tDH
D[0:31]
DATA 1
DATA 2
Figure 7. TMS320C31 Write Cycle – 50 MHz
18
SPRA172
Summary
Table 3. TMS320C31 Write Cycle – 50 MHz
NAME
FORMULA
MIN
MAX
MARGIN
COMMENTS
1
C
tRSU
6
6
<0.><1.>
Setup time, RDY before H1 high
2
C
tRAH
0
0
<4.><8.>
Hold time, RDY after H1 high
3
C
tASR
5
5
<7.><7.>
Setup time, row address
4
D
tSTRB
2,4
2
5
C
tRE
30
30
6
C
tRAH
1
1
7
C
tC
55
55
8
C
tASC
5
9
C
tDH31
0
10
C
tCRP
11
D
12
13
4
Valid time, H1CLK to STRB
<8.>
Hold time, row address
<1.><3.>
Cycle time, row enable
<23.>
Cycle time, row enable
5
(7.>
Setup time, column address
0
<12.><2.>
Hold time, ’C31 data
5
5
<22.>
Setup time, column address latch to
row enable
tRWV
2,7
2
7
Valid time, H1CLK to R/W
D
tADDR
2,9
2
9
Valid time, H1CLK to address
D
tBOFF
4
4
4
Buffer output invalid
14
D
tCOBUF
6
6
6
Delay time, clock to output
15
D
tDV
12
14
14
16
C
tBP
20
20
<18.>
Precharge time, row
17
C
tCHB
–2
–2
<0.><0.>
Setup time, CAL high to RE high
18
D
tCO
4,6
4
19
D
tPD
3,7
3
7
20
C
tDS
5
5
6 <25.><25.>
21
C
tDH
0
0
<16.><26.>
Hold time, ’C31 data
22
C
tCAH
0
0
<44.>
Hold time, column address
23
C
tCAE
5
5
<13.>
Active time, column address latch
24
C
tPC
12
12
<66.>
Cyce time, column address latch
25
C
tWP
5
5
<33.>
Active time, write enable
26
C
tWC
12
12
<66.>
Cycle time, write enable
27
C
tCH
5
5
<53.>
Column address latch high time
(latch transparent)
28
C
tWI
5
5
<33.>
Inactive time, write enable
29
C
tCHW
0
0
<–2.>
Column address latch high to write
enable low
Valid time, ’C31 data
Delay time, clock to output
Delay time, propagation
Setup time, ’C31 data
EDRAM Memory Controller for the TMS320C31 DSP
19
20
SPRA172
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