Texas Instruments | EDRAM Controller for the 60MHz TMS320C40 DSP | Application notes | Texas Instruments EDRAM Controller for the 60MHz TMS320C40 DSP Application notes

Texas Instruments EDRAM Controller for the 60MHz TMS320C40 DSP Application notes
®
EDRAM Controller for the
60 MHz TMS320C40 DSP
APPLICATION REPORT: SPRA290
Digital Signal Processing Solutions
June 1998
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Copyright © 1998, Texas Instruments Incorporated
TRADEMARKS
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Quickcache is a registered trademark of Enhanced Memory Systems.
EDRAM is a registered trademark of Enhanced Memory Systems. Revision 2.0.
Other brands and names are the property of their respective owners.
CONTACT INFORMATION
US TMS320 HOTLINE
(281) 274-2320
US TMS320 FAX
(281) 274-2324
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(281) 274-2323
US TMS320 email
dsph@ti.com
Contents
Abstract ......................................................................................................................... 7
Product Support............................................................................................................ 8
Related Documentation............................................................................................. 8
World Wide Web ....................................................................................................... 8
Email......................................................................................................................... 8
Introduction...................................................................................................................9
EDRAM Controller Design.......................................................................................... 11
EDRAM Controller Functional Description............................................................... 12
Summary ..................................................................................................................... 17
Figures
Figure 1
Figure 2
Figure 3
Figure 4
Figure 5
Figure 6
Figure 7
TMS320C40 System Block Diagram ............................................................... 10
Row/Column Address Multiplexing.................................................................. 13
EDRAM Controller State Machine ................................................................... 13
TMS320C40 Read Miss Followed by a Read Hit Cycle – 30 MHz Bus............ 17
TMS320C40 Write Cycle – 30 MHz Bus.......................................................... 18
TMS320C40 Back to Back Write Cycles – 30 MHz Bus .................................. 21
TMS320C40 Refresh Cycle – 30 MHz Bus ..................................................... 23
Tables
Table 1
Table 2
Table 3
Table 4
Table 5
Table 6
Performance Comparison at 30 MHz Memory Bus Clock.................................. 9
STRB0 PAGESIZE.......................................................................................... 11
Read Miss Followed by a Read Hit Cycle – 30 MHz Bus................................. 19
Write Cycle...................................................................................................... 20
Back to Back Write Cycles – 30 MHz Bus ....................................................... 22
Refresh Cycle ................................................................................................. 23
EDRAM® Controller for the 60 MHz
TMS320C40 DSP
Abstract
The popular Texas Instruments (TIä) TMS320C4X family of 32-bit
floating-point digital signal processors (DSPs) has a memory bus
that operates at 30 MHz. The 32-bit local external memory bus
supports a maximum read bandwidth of 120 Mbytes per second
and a maximum write bandwidth of 60 Mbytes per second. The
processor has two on-board programmable timers to simplify the
generation of a refresh clock. The TMS320C40 is available in 50
and 60 MHz clock speed options.
The enhanced DRAM (EDRAM) memory with Quickcache® from
Enhanced Memory Systems provides high performance for the
TMS320C40 DSP at 60 MHz processor clock rates. Its fast 12ns
access time requires no wait states for any read within a page.
Unless preceded by a write, the EDRAM’s fast random access
performance allows read hit cycles to be completed with no wait
states. This performance is achieved with a single non-interleaved
memory bank consisting of as few as four 512K x 8 components
(2Mbytes). Fast 12ns SRAM memory used for DSP external
memory has slightly better performance but is more expensive at
this memory size. Standard DRAM memory is too slow for most
high performance DSP applications.
This application report describes the design of the 60 MHz
EDRAM controller.
EDRAM® Controller for the 60 MHz TMS320C40 DSP
7
SPRA290
Product Support
Related Documentation
The following list specifies product names, part numbers, and
literature numbers of corresponding TI documentation.
q TMS320C40 Digital Signal Processor Data Sheet, January
1998, Literature number SPRS038
q TMS320C4x User's Guide, March 1996, Literature number
SPRU063
World Wide Web
Our World Wide Web site at www.ti.com contains the most up to
date product information, revisions, and additions. Users
registering with TI&ME can build custom information pages and
receive new product updates automatically via email.
Email
For technical issues or clarification on switching products, please
send a detailed email to dsph@ti.com. Questions receive prompt
attention and are usually answered within one business day.
8
EDRAM® Controller for the 60 MHz TMS320C40 DSP
SPRA290
Introduction
The Texas Instruments TMS320C4X family of 32-bit floating-point
digital signal processors are popular for DSP applications. These
processors have a memory bus that operates at 30 MHz. The 32bit local external memory bus supports a maximum read
bandwidth of 120 Mbytes per second and a maximum write
bandwidth of 60 Mbytes per second. The processor has two onboard programmable timers to simplify the generation of a refresh
clock. The TMS320C40 is available in 50 and 60 MHz clock speed
options.
The enhanced DRAM (EDRAM) memory with Quickcache® from
Enhanced Memory Systems provides high performance for the
TMS320C40 DSP at 60 MHz processor clock rates. Its fast 12ns
access time requires no wait states for any read within a page.
Unless it is preceded by a write, the EDRAM’s fast random access
performance allows read hit cycles to be completed with no wait
states. This performance is achieved with a single non-interleaved
memory bank consisting of as few as four 512K x 8 components
(2Mbytes). Fast 12ns SRAM memory used for DSP external
memory has slightly better performance but is more expensive at
this memory size. Standard DRAM memory is too slow for most
high performance DSP applications.
Table 1. Performance Comparison at 30 MHz Memory Bus Clock
Transaction
EDRAM (12ns)
†
SRAM (12ns)
Page Read Hit
1 Cycle
1 Cycle
Page Read Miss
2 Cycles
1 Cycle
Write
2 Cycles
2 Cycles
†
† If preceded by a write, add one cycle
A single 26V12-7 PAL device and two FCT buffers (FCT541CT)
are the only components necessary to interface a single 2Mbyte
bank of EDRAM to the local memory bus. The controller design
supports a 60 MHz processor clock rate using 12ns EDRAM.
Figure 1 shows the system block diagram.
EDRAM® Controller for the 60 MHz TMS320C40 DSP
9
SPRA290
Figure 1. TMS320C40 System Block Diagram
/RESET
H1CK
PAGE0#
TCLK0
STRBO#
R/W0#
RDY0#
TMS320C20060
A(18:16) A(23:0)
S#
WRG#
ROWSEL#
RE#
COLSEL#
F#
Col Buffer
CALWE#
Row Buffer
EDRAM Controller
26v12-7
MA(7:0)
MA(10:8)
D(31:0)
10
(4) DM2203-12
512K x 8
EDRAM® Controller for the 60 MHz TMS320C40 DSP
SPRA290
EDRAM Controller Design
The objective of this controller design is to support TMS320C40
memory transactions with minimum wait states. The controller is
designed to support one EDRAM bank of 2 Mbytes. Memory size
can be expanded by adding additional control outputs to the logic.
The TMS320C40 local bus interface is programmable to control
wait states and HOLD operation. The memory interface control
register for the local bus should be programmed with the following
parameters:
q
q
q
SWW is programmed to respond only to the external RDY#
input for wait states (SWW=00). The internal /RDYWTCNT is
ignored.
WTCNT does not need to be programmed since software
programmable wait states are not used.
STRB0 PAGESIZE is set as shown in the table below:
Table 2. STRB0 PAGESIZE
EDRAM
MSBs Defining a
Bank
LSBs Defining a
Column
Bank Size
STRB0# PAGE
SIZE
512K x 8
A(30:8)
A(7:0)
256
01000
The TMS320C40 supports the following memory transactions:
q
q
q
32-bit Page Read Hit
32-bit Page Read Miss
32-bit Write
To support these bus transactions, the EDRAM and/or EDRAM
memory controller must interface with the following processor
control and address signals:
A18-A0
STRB0#
PAGE0#
R/W0#
RDY0#
Reset#
H1CLK
TCLK0
Address Bus
External Access Strobe
Page Detect Output
Read/Write Mode Outputs
Ready Input
Reset Input
Processor Clock Output
Timer Zero Output Clock/Pulse
EDRAM® Controller for the 60 MHz TMS320C40 DSP
11
SPRA290
The controller generates the following signals to control the
EDRAM:
ROWSEL#
COLSEL#
RE#
CALWE#
WRG#
F#
S#
Multiplexed Row Address Enable
Multiplexed Column Address Enable
Row Enable
Column Address Strobe/Write Enable
Combined W/R and /G
Refresh
Chip Select
The EDRAM W/R and /G control lines are tied together to form
WRG#. The ROWSEL#, COLSEL#, CALWE#, WRG# and F#
signals are supplied from the 26V12 PAL. S# can be generated
from the PLD or from NAND or NOR gates. When the memory
interface is in either the idle or any refresh state, the S# output is
brought high to reduce the EDRAM power consumption.
Optionally, S# can be tied to ground if the EDRAM power
consumption is not an issue. If S# is not used, the EDRAM
controller can fit into a 22V10 PLD.
EDRAM Controller Functional Description
This section describes the EDRAM controller block diagram
shown in Figure 1. The Refresh Counter is formed using an
internal timer in the C40 to generate the periodic refresh signal
every 40µsec for the state machine. This refresh signal will trigger
an F# refresh on the next available bus cycle. Up to three wait
states may be inserted to the processor while a bus transaction is
occurring. The Address Multiplexer selects the row or column
address to the EDRAM multiplex address lines under control of
the state machine. The multiplexer is implemented using two
74FCT541CT 8-bit buffer chips. These chips were selected
because of their fast through delay (4.1ns) and fast select delay
(5.8ns). Column address is connected to A(7:0) for 512K x 8
EDRAM. The row address comprises the 11 local address bits
above the column address.
Address lines A(10:0) of the EDRAM are connected directly to
A(18:16) of the C40 DSP, respectively. The upper address lines
are ignored during column time, so there is no need to feed these
address lines through a buffer.
12
EDRAM® Controller for the 60 MHz TMS320C40 DSP
SPRA290
Figure 2. Row/Column Address Multiplexing
A(18-16)
A(15-8)
A(7-0)
ROWSEL
FCT541CT
COLSEL
FCT541CT
Tpd = 4.1 ns
Toe = 5.8 ns
MA(7-0)
MA(10-8)
The State Machine operates synchronously with the rising edge of
the H1CLK.
Figure 3. EDRAM Controller State Machine
Idle
I1
Write
W1
Read
Miss
R1
F1
F2
Refresh
R2
Read
Hit
One of the following memory control sequences is selected based
on the control input status. Read and write sequences are
described. All states are determined at the rising edge of H1CLK.
EDRAM® Controller for the 60 MHz TMS320C40 DSP
13
SPRA290
Reset
Sequence
Page Read
Miss Sequence
Page Read Hit
Sequence
14
When Reset# is low, the processor is in its reset
state. The EDRAM controller continuously
executes F# refresh cycles until Reset# returns
high. This meets the EDRAM initialization
requirement of eight F# refresh cycles during
startup. It is assumed that a startup control
program will be run immediately following reset.
This program must configure the TMS320C40 to
perform two read miss cycles to different row
addresses for each internal EDRAM bank. Row
address bits A8 and A9 define the four internal
EDRAM banks. This startup procedure must be
performed for proper EDRAM operation.
Stating from the idle state, when STRB0# is low
and R/W# is high, a page read miss sequence is
executed. The row address will be selected, and
WRG# signal will be brought low. The RE# signal
is then asserted clocked to latch the row
address. RDY0# is held high until the middle of
cycle R1 to insert a wait state for the processor.
Data is available to the processor at the end of
cycle two. Because of the TMS320C40’s
addressing scheme, one wait state is inserted
when a read cycle follows a write cycle.
Starting from the R2 state, when STRB# is low,
R/W# is high, and PAGE0# is low, a page read
hit sequence is executed. The column address is
selected, and WRG# is brought low to gate data
on to the data bus. The EDRAM can support
back-to-back in-page reads from cache in zero
wait states. The TMS320C40 processor will hold
STRB# and PAGE0# low on back-to-back page
hit reads. On a page read miss, STRB0# and
PAGE0# will go high to cause a page read miss
sequence to be executed.
EDRAM® Controller for the 60 MHz TMS320C40 DSP
SPRA290
Write
Sequence
Refresh
Sequence
Idle
Chip Select
(S#)
Programming
the
TMS320C40
Timer
If STRB# is low and R/W# is low, a write
sequence is executed. The row address is
selected, and WRG# is brought high. The RE#
signal is asserted to latch the row address. When
the column address and write data are stable,
the CALWE# signal is asserted to latch the
column address and write data. Following the
write, RE# and CALWE# are brought high to
terminate the write cycle. The write is completed
in two cycles or zero wait states. The EDRAM
supports single and back-to-back writes in two
cycles or zero wait states. The C40 does not
support single cycle writes, therefore PAGE0# is
not used on write cycles.
If the TCLK0 input is high, an F# refresh
sequence is performed after any current memory
cycles are completed. The TCLK0 output will be
high for 40ns and stay low until the next refresh
period. The F# pin is brought low and RE# is
clocked to perform an internal refresh using the
internal refresh counter. A refresh is executed
every 40µsec. During the refresh sequence,
RDY# is held high to cause the processor to
wait. The processor may need to wait for up to
three wait states to complete the current memory
transaction.
If STRB# is high (except during the W2 state),
this indicates the cycle is an idle cycle. The
WRG# signal is brought high to disable the
EDRAM outputs from the data bus until the next
active cycle.
The S# can be generated from the PLD or by
using simple NAND or NOR gates. S# is brought
high during the idle and refresh states to reduce
the power consumption. This circuit is optional.
S# can be tied to ground if reduced power
consumption is not desired or if the pin count
must be reduced.
The Timer Global Control Register must be
programmed immediately after power up so that
the refresh counter can be initialized properly.
The TCLK0 output is used to generate a 40ns
minimum high pulse every 40µsec.
EDRAM® Controller for the 60 MHz TMS320C40 DSP
15
SPRA290
The following bit values are programmed:
CLKSRC=1
FUNC-0
I/O=0
HLD=1
Period Register Value=600
period register =
f INT
15 MHz
=
= 600
f(Timer Clock) 25 KHz
The remaining bit fields can be left at their default values after
power up. The interrupt enable register does not need to be
programmed to generate an interrupt when timer zero generates a
high pulse every 40µsec. The timer must be started immediately
after power up by setting the GO/HLD bits in the Timer Global
Control Register to “11”. When the counter value equals the value
set in the period register, a 40ns high pulse will be output on
TCLK0 pin. This high pulse will cause the EDRAM state machine
to record a pending refresh on the next rising edge of H1CLK. It
will be cleared after a refresh sequence is performed. The C40
timer does not need to be restarted and no interrupt will be
generated. A refresh sequence will not be started until after the
second cycle of a read miss or write sequence, if one is in
progress.
The attached timing diagrams show the timing of the EDRAM
controller operating in a 60 MHz TMS320C40 system with the
12ns version of the EDRAM. The EDRAM controller parameters
are for 26V12-7 PLD and 74FCT541CT 8 – buffers. The
TMS320C40 timing parameters are taken from the TI TMS320C4x
User’s Guide, 1996.
16
EDRAM® Controller for the 60 MHz TMS320C40 DSP
SPRA290
Summary
A simple EDRAM controller for the 60 MHz Texas Instruments
TMS320C40 DSP can be implemented using a simple PLD device
and two FCT buffers. The controller supports one EDRAM bank of
2M bytes (using DM2203 components) and can easily be
expanded to more memory. The EDRAM system achieves zero
wait states on read hit cycles and on all write cycles.
System cost is reduced by utilizing an internal timer in the
TMS320C40 to generate the refresh signal. The EDRAM achieves
near 12ns SRAM performance while providing much lower
memory cost at 4Mb density. The EDRAM provides the best
price/performance for DSP applications.
Figure 4. TMS320C40 Read Miss Followed by a Read Hit Cycle – 30 MHz Bus
0ns
50ns
100ns
150ns
TMS320C40 Read Miss + Read Miss Cycle = 30 MHz Bus
STATE
R1
IDLE
R2
R2
IDLE
H1CLK
tSTRB
tSTRB
tRWV
tRWV
LSTBR0#
R/W0#
tPAGE
tPAGE
LPAGE0#
LA(30-0)
tADDR
tADDR
Address 1
Address 2
tCO
tRSU
tCO
tRH
RDY0#
tCO
tCO
tCO
tCO
ROW SEL
COL SEL
tCO
tMSU
tCO
tC
tRE
tRP
/RE
MA(10:0)
tRAH
tASR
tPDBUF
Rcw Addr
tBOFF
tCOBUF
Col 1
tBOFF
tCOBUF
tPDBUF
Col 2
tMSU
tPD
tPD
WRG#
tAC
tRAQ
tGQV
D(31-0)
tDH
tDSU
DATA 1
tPD
tAC
tDH
tDSU
DATA 2
tGQZ
tCO
S#
Note:
Based on the 26V12-7 PLD and 12ns EDRAM.
EDRAM® Controller for the 60 MHz TMS320C40 DSP
17
SPRA290
Figure 5. TMS320C40 Write Cycle – 30 MHz Bus
0ns
50ns
100ns
150ns
TMS320C40 Write Cycle - 30 MHz Bus
STATE
IDLE
IDLE
W1
IDLE
IDLE
H1CLK
tSTRB
tSTRB
LSTRB0#
tRWV
tRWV
R/W0#
tPAGE
tPAGE
LPAGE0#
tADDR
Address 2
tADDF
LA(30-0)
Address 1
tCO
tRSU
tPD
tRH
RDY0#
tCO
tCO
tCO
tCO
ROWSEL
COLSEL
tCO
tO
tCO
tRE
tCHR
tRP
/RE
tCO
tCAE
tCO
CALWE#
MA(10:0)
tCAH
tASC
tBOFF
tCOBUF
tRAH
Col 1
tASR
tPDBUF
Row Addr
tBOFF
tCOBUF
tMSU
tPD
tPD
WRG#
D(31-0)
tPD
tDOH
tDH
tDOUT
DATA 1
tSSR
tPD
tCO
S#
Note: Based on the 26V12-7 PLD and 12ns EDRAM.
18
EDRAM® Controller for the 60 MHz TMS320C40 DSP
SPRA290
Table 3. Read Miss Followed by a Read Hit Cycle – 30 MHz Bus
Row
Name
Formula
Min
Max
Margin
Comment
1
D
tSTRB
[0,8]
0
8
H1CLK Falling to STRB Valid
2
D
tADDR
[0,8]
0
8
H1CLK Falling to Address Valid
8
3
D
tRWV
[0,8]
0
4
C
tRE
[30,]
30
5
C
tC
[50,]
50
6
D
tAC
12
12
12
7
D
tGQV
5
5
5
8
C
tRP
[20,]
20
H1CLK Falling to R/W Valid
<1.33,>
Row Enable Active Time
<45.67,>
Row Enable Cycle time
Column Address Access Time
Output Enable Access Time
<42.33,>
Row Precharge Time
<-0.33,><0.33,>
/F and W/R Mode Select Setup Time
9
C
tMSU
[5,]
5
10
D
tCO
[3,5]
3
5
Clock to Output Delay
11
D
tBOFF
4
4
4
Buffer Disable Delay
5
12
D
tCOBUF
5
5
13
C
tDSU
[9,]
9
Buffer Enable Delay
14
C
tDH
[0,]
0
15
D
tPDBUF
4
4
16
C
tASR
[5,]
5
<2.67,>
Row Address Setup Time
17
C
tRAH
[1,]
1
<17.67,>
Row Address Hold time
18
D
tPD
[4,7]
4
7
Propagation Delay
19
D
tPAGE
[0,8]
0
8
H1CLK Falling to PAGE Valid
<2.33,><0.33,>
Data Setup Time to H1CLK
<11.62,><4,>
Data Hold Time from H1CLK
4
Buffer Propagation Delay
20
D
tRAC
30
30
30
Row Enable Access Time
21
D
tGQZ
[0,5]
0
5
Output Turn-Off Delay From Output
22
C
tRSU
[18,]
18
<10.33,>
Ready Setup Time to H1CLK Falling
23
C
tRH
[0,]
0
<19.67,>
Ready Hold Time From H1CLK
Falling
EDRAM® Controller for the 60 MHz TMS320C40 DSP
19
SPRA290
Table 4. Write Cycle
Row
Name
Formula
Min
Max
Margin
Comment
1
D
tSTRB
[0,8]
0
8
H1CLK Falling to STRB Valid
2
D
tADDR
[0,8]
0
8
H1CLK Falling to Address Valid
3
D
tRWV
[0,8]
0
8
4
C
tRE
[30,]
30
5
C
tC
[50,]
50
<3.33,>
Row Enable Cycle Time
6
C
tRP
[20,]
20
<0,>
Row Precharge Time
7
C
tMSU
[5,]
5
8
D
tCO
[3,5]
3
H1CLK Falling to R/W Valid
<1.33,>
<16.33,>
5
Row Enable Active Time
/F and W/R Mode Select Setup Time
Clock to Output Delay
9
D
tBOFF
[3,5]
3
5
Buffer Disable delay
10
D
tCOBUF
[3.6]
3
6
Buffer Enable Delay
11
D
tPDBUF
4
4
4
Buffer Propagation Delay
12
C
tASR
[5,]
5
<36,>
Row Address Setup Time
13
C
tRAH
[1,]
1
<0,>
Row Address Hold Time
14
D
tPD
[4,7]
4
7
Propagation Delay
15
D
tPAGE
[0,8]
0
8
H1CLK Falling to PAGE Valid
16
D
tDOUT
13
13
13
17
C
tASC
[5,]
5
<3.67,>
Column Address Setup Time
18
C
tDS
[5,]
5
<18.33,>
Data Input Setup Time
19
C
tDH
[0,]
0
<11.67,>
Data Input Hold Time
20
D
tDOH
0
0
21
C
tCAE
[5,]
5
H1CLK Falling Data Output Valid
0
Data Output Hold Time
<9.67,>
Column Address Latch Active Time
22
C
tCAH
[0,]
0
<17.67,>
Column Address Hold Time
23
C
tRSU
[18,]
18
<0.33,>
Ready Setup Time to H1CLK Falling
24
C
tRH
[0,]
0
<3,>
Ready Hold Time from H1CLK Falling
25
G
tCHR
(-[2,])
26
C
tSSR
[5,]
20
-2
5
/CAL Inactive Lead Time to /RE Inactive
<-0.33,>
Select Setup Time to Row Enable
EDRAM® Controller for the 60 MHz TMS320C40 DSP
SPRA290
Figure 6. TMS320C40 Back to Back Write Cycles – 30 MHz Bus
0ns
50ns
100ns
150ns
200ns
TMS320C40 Write Cycle + Write Cycle - 30 MHz Bus
STATE
ID L E
W1
ID L E
ID L E
W1
ID L E
ID L E
H1CLK
tSTRB
tSTRB
tSTRB
tSTRB
tSTF
tSTRB
LSTRB0#
tRWV
tRWV
R/W 0#
tPAGE
tPAGE
LPAGE0#
tADDR
tADDR
tADDR
LA(30-0)
A d d re s s 1
A d d re s s 2
tCO
tRSU
tPD
tRSU
tPD
tRH
tCO
tRH
RDY0#
tCO
tCO
tCO
tCO
tCO
tCO
tCO
tCO
tCO
tCO
tCHP
ROWSEL
COLSEL
tCO
tCO
tRE
tCHP
tRP
/RE
tCO
tCO
tCAE
tCO
tCAE
tCO
CALWE#
tCAH
tASC
tBCFF
tCOBUF
tRAH
tASR
tPDBUF
MA(10:0)
Row 1
tASC
tBOFF
tCOBUF
tRAH
tASR
tPDBUF tCAH
Col 2
tPDBUF
Col 2
tMSU
tPD
tPD
WRG#
tDOH
tDS
tDOUT tDH
D(31-0)
S#
DATA 1
tSSR
tPD
tDOH
tDS
tDOUT tDH
DATA 2
tCO
Note: Based on the 26V12-7 PLD and 12ns EDRAM.
EDRAM® Controller for the 60 MHz TMS320C40 DSP
21
SPRA290
Table 5. Back to Back Write Cycles – 30 MHz Bus
Row
Name
Formula
Min
Max
Margin
Comment
1
D
tSTRB
[0,8]
0
8
H1CLK Falling to STRB Valid
2
D
tADDR
[0,8]
0
8
H1CLK Falling to Address Valid
8
3
D
tRWV
[0,8]
0
4
C
tRE
[30,]
30
H1CLK Falling to R/W Valid
5
C
tC
[50,]
50
<11.29,>
Row Enable Cycle Time
6
C
tRP
[20,]
20
<7.95,>
Row Precharge time
7
C
tMSU
[5,]
5
<16.33,>
/F and W/R Mode Select Setup
Time
8
D
tCO
[3,5]
3
<1.33,>
5
Row Enable Active Time
Clock to Output Delay
9
D
tBOFF
[3,5]
3
5
Buffer Disable delay
10
D
tCOBUF
[3.6]
3
6
Buffer Enable Delay
4
11
D
tPDBUF
4
4
12
C
tASR
[5,]
5
13
C
tRAH
[1,]
1
14
D
tPD
[5,7]
5
Buffer Propagation Delay
<36,><2.67,>
<0,><0,>
7
Row Address Setup Time
Row Address Hold Time
Propagation Delay
15
D
tPAGE
[0,8]
0
8
H1CLK Falling to PAGE Valid
16
D
tDOUT
13
13
13
Data Output Valid Delay
17
C
tASC
[5,]
5
<3.67,><3.67,>
Column Address Setup Time
18
C
tDS
[5,]
5
<18.33,><18.33,>
Data Setup Time
19
C
tDH
[0,]
0
<11.67,><11.67,>
Data Hold Time
20
D
tDOH
0
0
21
C
tCAE
[5,]
5
<9.67,><9.67,>
Column Address Latch Active Time
22
C
tCAH
[0,]
0
<32.33,><32.33,>
Column Address Hold Time
23
C
tRSU
[18,]
18
<0.33,><0.33,>
Ready Setup Time to H1CLK
Falling
24
C
tRH
[0,]
0
<3,><3,>
Ready Hold Time from H1CLk
Falling
25
G
tCHR
(-[2,])
26
C
tSSR
[5,]
22
0
Data Output Hold Time
-2
5
/CAL Inactive Lead Time to /RE
Inactive
<-0.33,>
Select Setup Time to Row Enable
EDRAM® Controller for the 60 MHz TMS320C40 DSP
SPRA290
Figure 7. TMS320C40 Refresh Cycle – 30 MHz Bus
0ns
50ns
25ns
100ns
75ns
125ns
TMS320C40 Refresh Cycle - 30 M Hz Bus
1
IDLE
STATE
2
F2
F1
IDLE
H1CLK
tRH
tRH
tRSU
tRSU
RDY0#
tCO
tCO
tMSU
tRP
tRE
tMH
tRP
RE#
tCO
tCO
S#
Notes: 1)
2)
All other signals are “don’t care.”
Based on the 26V12-7 and FCT541 buffers.
Table 6. Refresh Cycle
Row
1
C
Name
Formula
Min
tRSU
[6]
Max
Margin
Comment
6
<7.33,><3.67,>
Setup, RDY# Before H1CLK Rising
Hold, RDY# After H1CLK Rising
2
C
tRH
[0,]
0
<10.67,><7.33,>
3
C
tRE
[30,]
30
<1.33,>
Row Enable Active Time
4
C
tC
[55,]
55
<2,>
Row Enable Cycle Time
5
C
tMSU
[5,]
5
<9.67,>
/F and W/R Mode Select Setup Time
6
C
tMH
[5,]
5
<9.67,>
/F and W/R Mode Select Hold Time
7
C
tRP
[20,]
20
<3.67,>
Row Precharge time
8
D
tCO
[3,5]
3
5
EDRAM® Controller for the 60 MHz TMS320C40 DSP
Clock to Output Delay
23
SPRA290
"
"
"
"
TMS320C40 PLD Equations - 60 MHz Core, 30 MHz Bus
26V12-7
Revision 2.0
Enhanced Memory Systems
INPUT H1CLK;
LOW_TRUE INPUT
LOW_TRUE INPUT
LOW_TRUE INPUT
LOW_TRUE INPUT
INPUT TCLK0;
LOW_TRUE
LOW_TRUE
LOW_TRUE
LOW_TRUE
LOW_TRUE
LOW_TRUE
LOW_TRUE
LOW_TRUE
RESET;
RW0;
STRB0;
PAGE0;
OUTPUT
OUTPUT
OUTPUT
OUTPUT
OUTPUT
OUTPUT
OUTPUT
OUTPUT
RDY0;
RE ;
CALWE;
WRG ;
F ;
S ;
ROWSEL ;
COLSEL ;
NODE q2..q0 CLOCKED_BY H1CLK;
D_FLOP NODE REF_PENDING CLOCKED_BY H1CLK;
MACRO ON 1;
MACRO OFF 0;
" Equations
WRG = /RW0;
" We need to store the current cycle state to generate EDRAM timings
STATE_MACHINE TMS320C40
STATE_BITS [q2..q0]
CLOCKED_BY H1CLK;
STATE IDLE :
REF_PENDING = OFF;
RDY0 = OFF;
RE = OFF;
CALWE = OFF;
F = OFF;
S = STRB0;
ROWSEL = ON;
COLSEL = OFF;
IF (RESET) THEN
GOTO READ1;
ELSE
IF (TCLK0) THEN
GOTO REFRESH1;
ELSE
24
EDRAM® Controller for the 60 MHz TMS320C40 DSP
SPRA290
IF (STRB0) THEN
IF (RW0) THEN
GOTO WRITE1;
ELSE
GOTO READ1;
END IF;
END IF;
END IF;
END IF;
STATE REFRESH1 :
REF_PENDING = OFF;
RDY0 = OFF;
RE = /H1CLK;
CALWE = OFF;
F = ON;
S = OFF;
ROWSEL = OFF;
COLSEL = OFF;
GOTO REFRESH2;
STATE REFRESH2 :
REF_PENDING = OFF;
RDY0 = OFF;
RE = H1CLK;
CALWE = OFF;
F = OFF;
S = OFF;
ROWSEL = OFF;
COLSEL = OFF;
GOTO IDLE;
STATE READ1 :
REF_PENDING = (TCLK0 + REF_PENDING);
RDY0 = /H1CLK;
RE = ON;
CALWE = OFF;
F = OFF;
S = ON;
ROWSEL = /H1CLK;
COLSEL = H1CLK;
GOTO READ2;
STATE READ2 :
RDY0 = ON;
RE = OFF;
EDRAM® Controller for the 60 MHz TMS320C40 DSP
25
SPRA290
CALWE = OFF;
F = OFF;
S = ON;
ROWSEL = OFF;
COLSEL = ON;
IF (RESET) THEN
GOTO IDLE;
ELSE
IF (TCLK0 + REF_PENDING ) THEN GOTO REFRESH1;
ELSE
IF (/RW0 * /PAGE0) THEN
GOTO READ1;
ELSE
IF (/RW0 * PAGE0) THEN
GOTO READ2;
ELSE
IF (RW0) THEN
GOTO WRITE1;
ELSE
GOTO IDLE;
END IF;
END IF;
END IF;
END IF;
END IF;
STATE WRITE1:
REF_PENDING = (TCLK0 + REF_PENDING);
RDY0 = /H1CLK;
RE = ON;
CALWE = /H1CLK;
F = OFF;
S = ON;
ROWSEL = ON;
COLSEL = OFF;
GOTO IDLE;
END TMS320C40;
26
EDRAM® Controller for the 60 MHz TMS320C40 DSP
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