Texas Instruments | TMS320C40 DMA Memory Transfer Timing | Application notes | Texas Instruments TMS320C40 DMA Memory Transfer Timing Application notes

Texas Instruments TMS320C40 DMA Memory Transfer Timing Application notes
TMS320 DSP
DESIGNER’S NOTEBOOK
TMS320C40 DMA
Memory Transfer Timing
APPLICATION BRIEF: SPRA212
Daniel Chen
Digital Signal Processing Products
Semiconductor Group
Texas Instruments
January 1993
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Contents
Abstract......................................................................................................................... 7
Design Problem ............................................................................................................ 8
Solution......................................................................................................................... 8
Tables
Table 1. Timing and Cycle Count for DMA Transfers – Destination: On-Chip......... 9
Table 2. Timing and Cycle Count for DMA Transfers – Destination: Local Bus.... 10
Table 3. Timing and Cycle Count for DMA Transfers – Destination: Global Bus.. 10
TMS320C40 DMA Memory Transfer
Timing
Abstract
This document discusses how many cycles it takes the DMA to
read/write to external memory. Several tables are given to allow the
developer to determine this information for several different types of
configurations.
TMS320C40 DMA Memory Transfer Timing
7
Design Problem
How many cycles does it take the DMA to read/write to external
memory?
Solution
To maximize CPU computational power and unload the CPU of the
data transfer burden, the TMS320C40 provides six DMA channels
(12 DMA channels in split mode) to handle data transfer
concurrently with CPU operations. These DMA channels and the
CPU share the internal/external buses. Hence, a user-configurable
DMA fixed/rotate priority arbitration scheme and CPU/DMA priority
scheme are created to prioritize the bus resource conflict situations
(see TMS320C4x User’s Guide, Section 9 for more information).
The combination of bus resource conflicts can make DMA memory
transfer timing very complicated. However, there are certain
guidelines to follow to calculate the transfer timing for certain DMA
setups. The single-channel DMA memory transfer timing with no
CPU or other DMA channel conflict is discussed below. The actual
DMA transfer timing can be obtained by combining the singlechannel DMA transfer timing with bus resource conflict situations.
When the DMA memory transfer has no conflict with the CPU or any
other DMA channels, the number of cycles of a DMA transfer is
dependent upon whether the source and destination location are
designated as on-chip memory, peripheral, or external ports. When
an external port is used, the DMA transfer speed is affected by two
factors: the external bus wait state and the read/write conflict (i.e., if
a write is followed by a read, the read takes two cycles).
Tables 1 through 3 show the number of cycles a DMA transfer
requires from different sources to different destinations. Each entry
in the table represents the total cycles required to do the T transfers,
assuming that there are no pipeline conflicts.
Each table below illustrates the timing of the DMA transfer.
8
SPRA212
Table 1. Timing and Cycle Count for DMA Transfers – Destination: On-Chip
Cycles (H1)
1
Source On-chip
Destination Onchip
R
Source Local
Bus
Destination Onchip
R
2
3
4
R
W
W
7
8
R
W
R
W
R
6
R
R R
Cr Cr
Source Global
Bus
Destination Onchip
5
9
10
R
W
R
R
Cr
14
R
R
Cr
15
R
W
R
R
Cr
R
Cr
R
R
Cr
R
Cr
W
R
R
Cr
R
Cr
W
Source
Destination: On-chip
On-chip
Local Bus
Global bus
[(1 + Cr) + 1] T
Notes: 1)
2)
3)
4)
5)
6)
7)
8)
9)
13
W
W
R R R R R
Cr Cr
Cr Cr
W
W
12
R
W
R R
Cr Cr
11
(1+1) T
[(1 + Cr) + 1] T
T = Number of transfers
Cr = Source-read wait states
Cw = Destination-write wait states
|R| = Single-cycle reads
|W| = Single-cycle writes
|R.R| = Multi-cycle reads
|W.W| = Multi-cycle writes
|Cr| = Number of wait cycles for a read
|Cw| = Number of wait cycles for a write
Externally, on the global and local buses, writes take at least two
cycles. However, the CPU/DMA requires one cycle to perform the
write to the external memory bus. Therefore the DMA/ CPU can
transfer data on the next cycle. For example, the DMA transfers
1024 words from internal memory RAM block 1 to one-wait-state
memory on the global bus while the CPU runs from memory on the
local bus and fetches operands from RAM block 0. DMA transfer
time is calculated from Table 2 as 1 + (2 + 1) 1024 = 1 + 3072 =
3073 cycles.
TMS320C40 DMA Memory Transfer Timing
9
Table 2. Timing and Cycle Count for DMA Transfers – Destination: Local Bus
Cycles (H1) 1
2
3
Source Onchip
Destination
Local Bus
R
Source
Local Bus
Destination
Local Bus
R R R
Cr Cr
Source
Global Bus
Destination
Local Bus
R R R
Cr Cr
4
5
6
R
W W
7
8
9
10
R
W W W
Cw Cw
W
W
W
W W
Cw Cw
R
R
R
Cr Cr
W W
Cw Cw
W
12
13
14
R
W W
Cw Cw
R
W
11
R
R
W
W
W
W
R
Cr
R
Cr
R
R
Cr Cr
W W
Cw Cw
15
R
W W
Cw Cw
W
W
W W
Cw Cw
W
W
R
W
W
W W
Cw Cw
Source
Destination: Local Bus
On-chip
Local Bus
1 + (2 + Cw) T
[(2 + Cr) + (2 + Cw)] T – 1
Global bus
[(1 + Cr) + (2 + Cw)] + [2 + max(Cr, Cw)] (T – 1)
Table 3. Timing and Cycle Count for DMA Transfers – Destination: Global Bus
Cycles (H1)
1
Source Onchip
Destination
Global Bus
R
2
3
10
SPRA212
5
6
R
W W
Source Local R R R
Bus
Cr Cr
Destination
Global Bus
Source
Global Bus
Destination
Global Bus
4
7
8
9
R
W W
Cw Cw
R
W
W
W
W
R
R
Cr Cr
W W
Cw
R R
Cr Cr
W
W
W W
Cw Cw
10
11
12
13
14
R
W W
Cw Cw
R
W
W
R
R
15
R
W
W
R
Cr
W
R
Cr
W
R
Cr
R
Cr
W W
Cw Cw
W
W
W
R
W
W
W
Cw
W
W
W W
Cw Cw
Source
Destination: Global Bus
On-chip
Local Bus
Global bus
1 + (2 + Cw) T
[(1 + Cr) + (2 + Cw)] + [2 + max(Cr, Cw)] (T –1)
[(2 + Cr) + (2 + Cw)] T – 1
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