Texas Instruments | Feature Phone Based on TMS320LC203 | Application notes | Texas Instruments Feature Phone Based on TMS320LC203 Application notes

Texas Instruments Feature Phone Based on TMS320LC203 Application notes
Feature Phone based on
TMS320LC203
Literature Number: BPRA050
Texas Instruments Europe
March 1997
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Copyright © 1997, Texas Instruments Incorporated
Contents
Contents
1. Introduction ..............................................................................................................1
2. Hardware..................................................................................................................2
2.1 System Overview ..........................................................................................2
2.2 Connections to the Parallel Port....................................................................3
2.3 On-Chip UART ..............................................................................................5
2.4 Multiplexing the Serial Port............................................................................5
2.5 Variable System Clock .................................................................................6
3. Software: Initialization & Test.................................................................................7
3.1 Communication between DSP and PC via RS232 ........................................7
3.2 Serial Port and TLV320AC36 ........................................................................7
3.3 Testing the external SRAM ...........................................................................7
Appendix A. Source Code .....................................................................................11
Appendix B. PAL Programming .............................................................................21
Appendix C. Schematics .......................................................................................25
Feature Phone based on TMS320LC203
iii
Contents
List of Figures
Figure 1: System Overview ............................................................................................... 2
Figure 2: System Memory Map ......................................................................................... 4
iv
Literature Number: BPRA050
Contents
List of Tables
Table 1: Status of memory select signals..........................................................................3
Table 2: Variable frequency for CLKIN..............................................................................6
Table 3: TMS320C203 clock options.................................................................................6
Feature Phone based on TMS320LC203
v
Contents
vi
Literature Number: BPRA050
1. Introduction
Feature Phone based on TMS320LC203
ABSTRACT
This application report describes a feature phone design based on the
TMS320LC203. The LC203 is a 3V member of the TMS320C2xx DSP
family combining low cost and low power consumption with a computing
power of 20 MIPS. Three independent onchip ports, UART, Serial Port
and Parallel Port, allow designing with minimal external logic saving cost,
board space and assuring fast access times.
This report discusses mainly the realization of an evaluation board for
testing typical pay-phone algorithms such as signaling, speech
processing and data transmission. Examples are given how to handle
the different peripherals of the DSP regarding HW and SW issues. Basic
initialization and test routines together with the board schematics
complete this application description.
1. Introduction
In recent years, semiconductor manufacturers have succeeded in increasing the
computing power of Digital Signal Processors up to 2 billion instructions per second.
Such fast processing is not needed in every application.
For feature phones, price per unit and power consumption are the most important
criteria.
The 3-V DSP TMS320LC203 satisfies both ( low power and low cost), while its
computing power of 20 million instructions per second is more than sufficient for these
types of applications.
This report is based on an evaluation board developed for test and emulation of
typical payphone algorithms such as signaling, speech processing and data
transmission between the central office and the payphone.
This paper will mainly discuss the realization of the hardware, giving examples of how
to connect and initialize each port of the DSP. The schematics are included in the
appendix.
Chapter 3 gives a short description of the software that has been used for the testing
and initialization of the DSP’s interfaces. The source code also is included in the
appendix.
Feature Phone based on TMS320LC203
1
2. Hardware
2. Hardware
2.1 System Overview
For any feature phone application, multiple interfaces to peripheral devices are
needed. The TMS320C2xx family provides up to four totally independent ports.
Therefore, even complex systems can be realized with a minimum of external logic saving costs, board space and ensuring fast access times.
The TMS320LC203 used in this design provides an on-chip UART for communication
with a host processor, a 16-bit wide parallel port and a single synchronous serial port.
The parallel port is used to interface external memory to the DSP. The serial port
handles the data traffic between DSP and analog interfaces. In this application the
serial port is multiplexed between the two CODECs necessary for the line and
handset interfaces.
The JTAG port provides direct access to the DSP and optimizes test and emulation
capabilities of the system. In addition a seven-segment LED display gives the
designer the opportunity to monitor the status of the DSP.
ADDRESS
JTAG
TMS320LC303
DATA
DSP
External
Program Memory
64K x 16 SRAM
RS232
4x
IDT71V256SA
TLV320AC36/37
VBAP
Line Interface
M
U
X
TLV320AC36/37
VBAP
Handset Interface
External
Data Memory
64K x 16 SRAM
4x
IDT71V256SA
TIL311
7 Segment LED
I/O Space
Global
Data Memory
32K x 8 EPROM
1x
Mx27L256
Figure 1: System Overview
2
Literature Number: BPRA050
2. Hardware
2.2 Connections to the Parallel Port
The total space accessible from the DSP by the parallel port is divided in ‘Program’,
‘Data’, ‘Global Data’ and ‘I/O’. With each access to external devices the ‘LC203
selects one of these spaces by driving the appropriate memory select strobes (PS\,
DS\, IS\ and BR\) low:
Table 1: Status of memory select signals
Enabled Space
Program
Data
Global Data
I/O
PS\
Low
High
High
High
DS\
High
Low
Low
High
IS\
High
High
High
Low
BR\
High
High
Low
High
The address and data lines are shared by all external spaces.
The four SRAM devices U12 to U15 (see Appendix C p.28) build the external
program memory. PS\ combined with A15 gives the appropriate chip select signals for
the upper (addresses 0x8000 to 0xffff) and lower (addresses 0x0000 to 0x7fff)
memory banks.
WE\ is connected to the write enable input of the SRAMs.
The EPROM U16 is placed in the global data memory. It is accessed only during the
boot load process. Once the program is transferred onto the faster SRAM in program
space the GREG register will be changed to enable the full range of data memory.
BR\ is connected to the chip enable of the EPROM.
Because DS\ is low during global data accesses and data memory accesses, it is not
possible to use DS\ alone as chip enable for the SRAMs providing the external Data
memory (U8, U9, U10 and U11). Bus conflicts would occur during the access to the
EPROM.
Therefore, DS\ combined with BR\ and A15 constitute the chip select for data
memory, A15 being the selection signal for upper and lower memory banks.
The 7-segment LED display, U17, is the only external component in the IO space of
the DSP. IS\ is connected directly to the strobe input of the LED.
Feature Phone based on TMS320LC203
3
2. Hardware
Program
0x0000
0x003F
0x0040
Data
Interrupts
(External)
On-Chip
DARAM B2
0x007F
0x0080
Reserved
0x00FF
0x0100
On-Chip DARAM
B0 (CNF=0)
Reserved (CNF=1)
On-Chip DARAM
B0’ (CNF=0)
Reserved (CNF=1)
On-Chip
DARAM B1
0x01FF
0x0200
0x02FF
0x03FF
I/O
Memory mapped
Registers and
Reserved
0x005F
0x0060
0x0300
Global Data
External SRAM
U12 and U13
0x0400
LED
On-Chip
DARAM B1
0x04FF
0x0500
Reserved
0x07FF
0x0800
External SRAM
U8 and U9
0x7FFF
0x8000
0xFDFF
0xFE00
0xFEFF
0xFF00
0xFFFF
On-Chip DARAM
B0
(CNF=1)
External SRAM
U14 and U15
(CNF=0)
On-Chip DARAM
B0’
(CNF=1)
External SRAM
U14 and U15
(CNF=0)
External SRAM
U10 and U11
External EPROM
U16
(8 bit wide)
Memory mapped
Registers and
Reserved
Figure 2: System Memory Map
4
Literature Number: BPRA050
2. Hardware
2.3 On-Chip UART
The TMS320LC203 includes a complete UART on chip. This application uses only the
TX and RX pin for a direct connection to a host via a RS232 interface. The handshake
signals I/O0 to I/O4 are connected to a header for general purposes.
2.4 Multiplexing the Serial Port
Feature phone applications need two independent analog channels. One for the line
interface and one for the handset. As the ‘C203 provides only one synchronous serial
port it must be multiplexed between the two VBAPs (Voice Band Audio Processors).
The master clock frequency for the VBAPs is generated by the binary ripple counter
SN74HC4060 (U6, Appendix C, p.29). As this frequency defines the internal filters of
the TLV320AC36/37 it must be exactly at 2.048MHz. This frequency is also used to
clock the data in and out of the serial port. The frame sync pulse FSX for the transmit
channel is generated by the DSP. The same pulse triggers the receive channel (FSR).
The frame sync for the VBAPs is multiplexed with the XF output of the DSP. The PAL
device, U18, combines FSX and XF with the following equations:
For the line interface:
FSL = FSX & XF
For the handset:
FSH = FSX & !XF
The generated frame syncs trigger the receive and transmit operations of the serial
port, at the same time toggling the selection of the VBAPs.
FSX must provide the necessary 8kHz sampling frequency for the VBAPs. The QI
(16kHz) of the binary counter (U6) is connected to the DSP via interrupt INT2\.
Each time the DSP receives this interrupt it writes the next value to the transmit
register and triggers the FSX pulse. If XF is toggled with every INT2 each VBAP
receives the frame sync pulses with a frequency of 8kHz which ensures the proper
operation of the devices.
Due to the very efficient interrupt handling of the TMS320C203, the times between
two frame sync pulses do not differ significantly, but it must be ensured that no
interrupts with higher priority than INT2 occur while the VBAPs are active.
Feature Phone based on TMS320LC203
5
2. Hardware
2.5 Variable System Clock
The clock of the DSP is generated by a programmable oscillator. The inputs A, B and
C ( See Appendix C, p.27) vary the output frequency on pin #2 as shown in table 2.
Pin #1 always outputs the specified frequency of the device.
Table 2: Variable frequency for CLKIN
C
Inputs
B
Outputs
A
D
F
SW4
SW3
GND
pin #2
pin #1
L
L
L
L
H
H
H
H
L
L
H
H
L
L
H
H
L
H
L
H
L
H
L
H
F/2
F/4
F/8
F/16
F/32
F/64
F/128
F/256
10MHz
(5MHz)
2.5MHz
(1.25MHz)
625kHz
(312.5kHz)
156.25kHz
(78.125kHz)
20MHz
20MHz
20MHz
20MHz
20MHz
20MHz
20MHz
20MHz
The pins DIV1 and DIV2 of the DSP specify the factor between the frequency on
CLKIN and the DSP clock.
Table 3: TMS320C203 clock options
Parameter
Internal divided by two with external crystal
PLL multiply by one
PLL multiply by two
PLL multiply by four
6
Literature Number: BPRA050
DIV2
DIV1
SW5
SW6
L
L
H
H
L
H
L
H
3. Software: Initialization & Test
3. Software: Initialization & Test
The following chapter describes the programs for initialization and test routines written
during the development of the board. The source code can be found in Appendix A of
this report.
3.1 Communication between DSP and PC via RS232
Windows ‘Terminal’ software is used to establish communication between the DSP
and the PC. The keyboard and monitor are used as input and output devices
respectively . The DSP transfers its data to the PC via the RS232 interface driven by
the on-chip UART.
The exchange of data between the DSP and the PC is controlled by polling the DR
and THRE bits of the IOSR registers of the on-chip UART. When the DR bit is set, it
indicates that a character has been received. Similarly, when the THRE bit is set, it
indicates that the transmit register is empty ( i.e. a character has been transmitted).
When receiving data, the function ISRXREADY() is called, waiting until a character is
received before attempting to read the ASDTR register in the UART.
When transmitting data, the function ISTXREADY() is called, and waits until ASDTR
register is empty before attempting to write to it.
3.2 Serial Port and TLV320AC36
The two TLV320AC36 are connected to the DSP via the serial port. The XF signal is
used to switch between the two CODECS. Only the received serial port interrupt is
used since the transmit and receive functions of the serial port are synchronized by
tying together the FSX and FSR pins.
This paragraph describes the operation of the serial port in our test program. An
external interrupt, INT2, is received every 62.5µs (16kHz). The interrupt service
routine for INT2 turns on one of the VBAPs by toggling the XF pin and outputs an old
sample stored in BUFFER. Since the transmit and receive blocks of the serial port are
synchronized, a new sample will arrive at the serial port generating a receive interrupt.
The interrupt service routine will read the new sample from the serial port and store it
in BUFFER.
To perform the serial port test, an audio source may be connected to ANALOG IN. If
speakers are connected to ANALOG OUT they should reproduce the same waveform
as that applied to ANALOG IN.
3.3 Testing the external SRAM
In this test program the DSP reads and writes to external memory. Each stored value
is checked for errors and any faults encountered increment the error counters.
The program starts by initializing a data word to 0xffffh. This data memory is copied
into program memory, and immediately copied back from program to data memory.
This procedure is repeated for all the external program and data SRAMS.
Next, the program starts a different test. The DSP executes 8 consecutive writes to
the external data space. The data written alternates between 0x5555 and 0xaaaa with
Feature Phone based on TMS320LC203
7
3. Software: Initialization & Test
each cycle. The DSP reads out this data and stores the sum of the eight values in the
accumulator to check it. This procedure is repeated until the DSP reaches the end of
the external memory space. The program executes the same routine with 0x0000 and
0xffff as values to be written.
8
Literature Number: BPRA050
References
References
1. Voice-Band -Audio -Processor Application Report, G. Davis and R.
MacDonald, Texas Instruments 1994
2. TLV320AC36/37 3V Voice-Band Audio Processor, Texas Instruments 1994,
SLWS006
3. TMS320C2xx data sheet, Texas Instruments 1995, SPRS025
4. TMS320C2xx User’s Guide, Texas Instruments 1995, SPRU127B
5. Power Supply Circuits, Texas Instruments 1996, SLVD002
6. Digital Design Workshop, E. Haseloff and P. Forstner, Texas Instruments 1995
Feature Phone based on TMS320LC203
9
3. Software: Initialization & Test
10
Literature Number: BPRA050
Appendix A. Source Code
Appendix A. Source Code
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
;
Memory Test for LC203 Board
;
;
File Name: memtst.asm
;
;
;
;
Description: This program is used to check the correct
;
;
operation of the SRAMs in the board. Different values
;
;
are written to Data memory, then transferred to Program
;
;
memory and finally checked to see if any errors have
;
;
occurred. The ER_COUNT variable holds the number
;
;
of times a faulty memory cell has been found.
;
;
The file Make.bat will assemble and link memtst.asm
;
;
creating the memtst.out
;
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
IMR
GREG
IFR
WSGR
Ex_dat
Ex_prg
memsize
.set
.set
.set
.set
.set
.set
.set
TEMP_VAL .usect
ER_COUNT .set
TEST_VAL .set
ADDR
.set
tstdat .usect
tstprg .usect
INIT
.text
NOP
ldp
splk
lst
splk
lst
splk
splk
splk
out
splk
splk
OUT
4h
5h
6h
0fffch
0800h
0600h
0f000h
"temp",3
TEMP_VAL+1
TEMP_VAL+2
TEMP_VAL+3
"test_d",memsize
"test_p",memsize
#0
#2E00h,TEMP_VAL
#0,TEMP_VAL
#21FCh,TEMP_VAL
#1,TEMP_VAL
#0,IMR
#0,GREG
#0E00h,TEMP_VAL
TEMP_VAL,WSGR
#0ffffh,TEST_VAL
#0,ER_COUNT
ER_COUNT, 0001h
;
;
;
;
;
;
;
Int Mask register
Global Mask register
Int Flag register
Wait State Generator reg
External data address
External prog address
memory size to be tested
;
;
;
;
Temporary value
Error counter
test value
current program space address
;
;
;
;
;
;
;
;
;
;
;
;
ARP=1,OVM=1,INTM=1,DP=0
Init ST0
ARB=1,CNF=0,SXM=0,XF=1,PM=0
Init ST1
No Interrupts selected
Disable Global Memory
Init WSGR
7 WS I/0, 0 WS Data, 0 WS Prog
Initial Test Value ffffh
Initialised number of errors
write error counter to LED
Feature Phone based on TMS320LC203
11
Appendix A. Source Code
START
LOOP
lar
larp
lar
lar
lacl
sacl
sar
lacl
tblw
tblr
lacl
sub
mar
bcnd
ar3,#memsize
ar0
ar0,#Ex_dat
ar1,#Ex_prg
TEST_VAL
*
ar1,TEMP_VAL
TEMP_VAL
; transfers
*
*
TEST_VAL
*+,ar1
*+,ar0
COUNT,NEQ
;
;
;
;
;
;
;
;
Initialised loop counter
ar0 active pointer
ar0=Start External Data memory
ar1=Start External Prog memory
load Acc with test value
store value in Data mem
load ar1 into TEMP_VAL
store TEMP_VAL into acc to perform
;
;
;
;
transfer from data to prog
tranfer from prog to data
Load Acc with test value
Test the prog memory
; If error occur update error count
CONT
mar
*,ar3
; make counter active
banz
LOOP,ar0
; check if counter is zero
NOP
NOP
;Start test for 8 consecutive reads and 8 consecutive writes
LACC
SACH
LAR
LAR
MAR
CONS1: LACC
SACL
LACC
OR
SACL
SACH
SACL
SACH
SACL
SACH
SACL
SACH
SAR
LACL
SUB
SACL
LAR
LACC
ADD
ADD
ADD
ADD
ADD
ADD
ADD
ADD
AND
BCND
C1:
MAR
BANZ
#memsize, 13
TEMP_VAL
AR3, TEMP_VAL
AR4, #Ex_dat
*,AR4
#05555h
TEMP_VAL
TEMP_VAL, 16
#0aaaah
*+
*+
*+
*+
*+
*+
*+
*+
AR4,ADDR
ADDR
#8
ADDR
AR4, ADDR
*+
*+
*+
*+
*+
*+
*+
*+
#4
#0ffffh
ERR_CONS1, NEQ
*, AR3
CONS1,*-,AR4
LACC
SACH
LAR
LAR
MAR
CONS2: LACC
SACL
LACC
#memsize, 13
TEMP_VAL
AR3, TEMP_VAL
AR4, #Ex_dat
*,AR4
#0ffffh
TEMP_VAL
TEMP_VAL, 16
12
Literature Number: BPRA050
; load memorisize devided by 8
; in AR3 as loop counter
; load start address of data memory
; activate AR4
; load 0x5555aaaa in accumulator
;
;
;
;
;
;
;
;
;
;
write
write
write
write
write
write
write
write
reset
value
0xaaaa
0x5555
0xaaaa
0x5555
0xaaaa
0x5555
0xaaaa
0x5555
AR4 to the address of first
written in this loop
; read and accumulate all values
; written before
;
;
;
;
;
the sum + 4 should give 0x40000
check is lower 16bit are zero
if not increment error counter
decrement loop counter and repeat
the test for the whole data memory
; same as above with 0xffff and
; 0x0000 as values to be written
Appendix A. Source Code
C2:
SACL
SACH
SACL
SACH
SACL
SACH
SACL
SACH
SAR
LACL
SUB
SACL
LAR
LACC
ADD
ADD
ADD
ADD
ADD
ADD
ADD
ADD
AND
BCND
MAR
BANZ
B
*+
*+
*+
*+
*+
*+
*+
*+
AR4,ADDR
ADDR
#8
ADDR
AR4, ADDR
*+
*+
*+
*+
*+
*+
*+
*+
#4
#0ffffh
ERR_CONS2, NEQ
*, AR3
CONS2,*-,AR4
START
; repeat the whole test
ERR_CONS1 lacl
add
sacl
OUT
B
ERR_CONS2 lacl
add
sacl
OUT
B
ER_COUNT
#1
ER_COUNT
ER_COUNT, 0001h
C1
ER_COUNT
#1
ER_COUNT
ER_COUNT, 0001h
C2
;
;
;
;
Load counter in acc
add 1 to acc
store back in counter
write error counter to LED
;
;
;
;
Load counter in acc
add 1 to acc
store back in counter
write error counter to LED
COUNT
ER_COUNT
#1
ER_COUNT
ER_COUNT, 0001h
CONT
;
;
;
;
Load counter in acc
add 1 to acc
store back in counter
write error counter to LED
lacl
add
sacl
OUT
b
.sect
b
"vectors"
INIT
Feature Phone based on TMS320LC203
13
Appendix A. Source Code
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
;
;
;
Serial Port Test for LC203 Board
;
;
File: sp.asm
;
;
;
;
Description: This file is used to check the correct
;
;
operation between the on-chip serial port and the two
;
;
VBAPS. An Audio source is connected to the ANALOG IN ;
;
and the speakers should be connected to ANALOG OUT
;
;
The serial port will take samples from the ANALOG IN
;
;
and output the same sample to the ANALOG OUT.
;
;
The speaker output should be the same as that applied to
;
;
the input.
;
;
The multiplexing between the two VBAPS is achieved as
;
;
follows:
;
;
INT2 provides a 16kHz interrupt which toggles
;
;
the XF flag. The XF flag selects one of the VBAPS
;
;
thereby giving an 8KhkHz sampling rate to each VBAP
;
;
A file called MAKE.BAT will assemble, and link SP.ASM
;
;
producing SP.OUT
;
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
IMR
GREG
IFR
ICR
SDTR
.set
.set
.set
.set
.set
4h
5h
6h
0ffech
0fff0h
SSPCR
WSGR
.set
.set
0fff1h
0fffch
TEMP_VAL .usect
"temp",3
RX_READY .set
TEMP_VAL+1
BUFFER
.set
TEMP_VAL+1
INIT
.text
NOP
ldp
splk
lst
splk
lst
splk
splk
out
splk
splk
out
splk
out
splk
out
lacl
sacl
setc
splk
clrc
14
#0
#2E00h,TEMP_VAL
#0,TEMP_VAL
#21FCh,TEMP_VAL
#1,TEMP_VAL
#000Ah ,IMR
#0001h,TEMP_VAL
TEMP_VAL,ICR
#0,GREG
#0E00h,TEMP_VAL
TEMP_VAL,WSGR
#000ah,TEMP_VAL
TEMP_VAL,SSPCR
#003ah,TEMP_VAL
TEMP_VAL,SSPCR
#0
RX_READY
XF
#0000h,TEMP_VAL
INTM
Literature Number: BPRA050
; Int Mask register
; Global Mask register
; Int Flag register
;ICR reg
; Synch Serial Port
; Transmit/Receive Reg
; Synch Serial Port Control Reg
; Wait State Generator reg
; Temporary value
; Receive Flag
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
ARP=1,OVM=1,INTM=1,DP=0
Init ST0
ARB=1,CNF=0,SXM=0,XF=1,PM=0
Init ST1
INT2/INT3 and Serial Port Receive
Interrupt selected
INT2 selected
Init ICR reg
Disable Global Memory
Init WSGR
7 WS I/0, 0 WS Data, 0 WS Prog
Loop Back Mode Selected
Init SSPCR
Boot up SSPCR
Init SSPCR
;
;
;
;
Init RX_READY flag
Selects the VBAP
TEMP_VAL = 0
Enable interrupts
Appendix A. Source Code
START
b START
INT2
sst
lacl
xor
sacl
lst
;lacl
;sub
;bcnd
;lacl
;add
;sacl
;clrc
;ret
OUTPUT out
splk
clrc
ret
RECVINT in
clrc
ret
rs
int1
int2_3
tint
rint
xint
txrxint
int8
int9
int10
int11
int12
int13
int14
int15
int16
trap
nmi
int20
int21
int22
int23
int24
int25
int26
int27
int28
int29
int30
int31
#1,TEMP_VAL
TEMP_VAL
#0010h
TEMP_VAL
#1,TEMP_VAL
TEMP_VAL
#1
OUTPUT,EQ
TEMP_VAL
#1
TEMP_VAL
INTM
;Load ST1 in TEMP_VAL
;Load ACC with ST1
;Toggle XF bit from ST1
BUFFER,SDTR
#0000h,TEMP_VAL
INTM
;
;
;
;
BUFFER,SDTR
INTM
; Input new data value
; Enable interrupts
; return
.sect
"vectors"
b
INIT
b
int1
b
INT2
b
tint
b
RECVINT
b
xint
b
txrxint
.space 2*16
b
int8
b
int9
b
int10
b
int11
b
int12
b
int13
b
int14
b
int15
b
int16
b
trap
b
nmi
.space 2*16
b
int20
b
int21
b
int22
b
int23
b
int24
b
int25
b
int26
b
int27
b
int28
b
int29
b
int30
b
int31
;Restore ST1
;Load int2 interrupt counter
;Check if two int2 have occurred
; add one to counter
; store back
;enable interrupts
;
;
;
;
;
;
;
;
;
;
Output old data value
zero the counter
Enable interrupts
return
reset
int1/hold
int2
timer
Synch receive
Synch transmit
Asynch Tran/Rec
reserved interrupt for emulator
None maskable interrupt
reserved interrupt for emulator
Feature Phone based on TMS320LC203
15
Appendix A. Source Code
/******************************************************************/
/*
LC203 UART TEST
*/
/*
File Names: uart.c,uart1.h,initp.asm
*/
/*
*/
/*
Description: This program is used to check the correct
*/
/*
operation of the on-chip UART. A Windows based
*/
/*
application is needed to establish communication
*/
/*
between the PC and the UART. The executable
*/
/*
file UART.TRM is used in this case. From the
*/
/*
communications menu choose, 9600 Baud Rate, 1 Stop bit,
*/
/*
,no parity check, 8 bit data, no flow control.
*/
/*
Connect an RS-232 cable from the PC to the Board.
*/
/*
Start the emulator with UART.OUT. Once UART.OUT is
*/
/*
running on the DSP, click on the Windows application
*/
/*
UART.TRM.
*/
/*
The following message should appear on the screen:
*/
/*
*/
/*
*** LC203 Test Platform ***
*/
/*
Type a character
*/
/*
The char should be displayed in the screen
*/
/*
To stop the test press (s)
*/
/*
*/
/*
A file called MAKE.BAT will compile, assemble, and link
*/
/*
the necessary files creating the UART.OUT.
*/
/******************************************************************/
#include "uart1.h"
void
main(void)
{
#define max 100
char C, COMMAND;
char s[max];
int i,n;
int DONE = 0;
void INIT(void);
/* Initialization routine
INIT();
sendinteger (0xa);
/* Set cursor begining of current line
sendinteger (0xd);
/* Set cursor to next line
sendinteger (0xa);
/* Set cursor begining of current line
sendinteger (0xd);
/* Set cursor to next line
sendstring(" *** LC203 Test Platform ***",27);
sendinteger (0xa);
/* Set cursor begining of current line
sendinteger (0xd);
/* Set cursor to next line
sendinteger (0xa);
/* Set cursor begining of current line
sendinteger (0xd);
/* Set cursor to next line
sendstring(" Type a character ",18);
sendinteger (0xa);
/* Set cursor begining of current line
sendinteger (0xd);
/* Set cursor to next line
sendstring(" The char should be display in the screen",41);
sendinteger (0xa);
/* Set cursor begining of current line
sendinteger (0xd);
/* Set cursor to next line
sendstring(" To stop the test press (s) ",28);
sendinteger (0xa);
/* Set cursor begining of current line
sendinteger (0xd);
/* Set cursor to next line
while (!DONE)
{
COMMAND = receivechar();
switch (COMMAND)
{
case ’s’: case ’S’:
DONE =1;
break;
}
sendchar (COMMAND);
}
16
Literature Number: BPRA050
*/
*/
*/
*/
*/
*/
*/
*/
*/
*/
*/
*/
*/
*/
*/
Appendix A. Source Code
/******************************************************************/
/*
Filename: UART1.h
*/
/******************************************************************/
#include "c:\dsp\c2xx\lib\string.h"
#include "c:\dsp\c2xx\lib\ioports.h"
ioport int portfff4;
void ISTXREADY(void);
void ISRXREADY(void);
unsigned char reply;
void sendinteger (int i)
{
ISTXREADY();
portfff4 = i;
}
void sendchar ( char c)
{
ISTXREADY();
portfff4 = c;
}
void sendstring ( char s[],int length)
{
int c,i;
i = 0;
while ( --length >= 0)
sendchar(s[i++]);
}
char receivechar(void)
{
ISRXREADY();
reply = portfff4;
return (reply);
}
Feature Phone based on TMS320LC203
17
Appendix A. Source Code
*******************************************************************
*
UART TEST PROGRAM LC203 BOARD
*
*
File Name intp.asm
*
*******************************************************************
IMR
.set
GREG .set
IFR
.set
ADTR .set
ASPCR .set
IOSR .set
BRD
.set
WSGR .set
TEMP_VAL
STAT1
4h
5h
6h
0fff4h
0fff5h
0fff6h
0fff7h
0fffch
.usect "temp",2
.set TEMP_VAL+1
;
;
;
;
;
;
;
;
;
;
IMR reg
GREG reg
IFR reg
ADTR reg
ASPCR reg
IOSR reg
BRD reg
WSGR reg
Temp value
ST1 storage
.def
.def
.def
.ref
_INIT
_ISTXREADY
_ISRXREADY
_c_int0
ldp
setc
clrc
clrc
setc
SPM
splk
splk
splk
splk
out
splk
out
splk
out
splk
out
splk
out
ret
#0
INTM
CNF
SXM
OVM
0
#0000h,IMR
#0ffffh,IFR
#0,GREG
#0e00h,TEMP_VAL
TEMP_VAL,WSGR
#0082h,TEMP_VAL
TEMP_VAL,BRD
#0000h,TEMP_VAL
TEMP_VAL,IOSR
#0000h,TEMP_VAL
TEMP_VAL,ASPCR
#2000h,TEMP_VAL
TEMP_VAL,ASPCR
;Set dp=0
;turn off interrupts
;Map B0 in data space
;No sign extension
;No overflow allowed
;No product shift
;Turn off interrupts
;Clear all pending interrupt
;Disable all global mem
;7 WS I/O, 0 WS DAT, 0 WS PRG
;Init WSGR
;9600 Baud Rate
;Init BDR
;Reset TEMP_VAL
;Init IOSR
;Reset UART
;Init ASPCR
;Boot the UART
;UART is now turned on
_ISRXREADY
READ_RX
SST
IN
BIT
BCND
LACL
AND
SACL
LST
RET
#1,STAT1
TEMP_VAL,IOSR
TEMP_VAL,0111b
READ_RX,NTC
STAT1
#0f7ffh
STAT1
#1,STAT1
;
;
;
;
;
;
;
;
;
Store ST1 in TEMP_VAL
Read the IOSR register
Test DR bit from IOSR
wait until TC=1
Load accumulator with ST1
Set TC=0
Store ST1 in TEMP_VAL
Restore ST1
Return
_ISTXREADY
READ_TX
SST
IN
BIT
BCND
#1,STAT1
TEMP_VAL,IOSR
TEMP_VAL,0100b
READ_TX,NTC
;
;
;
;
Store ST1 in TEMP_VAL
Read the IOSR register
Test THRE bit from IOSR
wait until TC=1
_INIT
18
Literature Number: BPRA050
Appendix A. Source Code
LACL
AND
SACL
LST
RET
STAT1
#0f7ffh
STAT1
#1,STAT1
.sect "vectors"
rs
b
_c_int0
int1
b
int1
int2_3
b
int2_3
tint
b
tint
rint
b
rint
xint
b
xint
txrxint
b
txrxint
.space
2*16
int8
b
int8
int9
b
int9
int10
b
int10
int11
b
int11
int12
b
int12
int13
b
int13
int14
b
int14
int15
b
int15
int16
b
int16
trap
b
trap
nmi
b
nmi
.space 2*16
int20
b
int20
int21
b
int21
int22
b
int22
int23
b
int23
int24
b
int24
int25
b
int25
int26
b
int26
int27
b
int27
int28
b
int28
int29
b
int29
int30
b
int30
int31
b
int31
;
;
;
;
;
Load accumulator with ST1
Set TC=0
Store ST1 in TEMP_VAL
Restore ST1
Return
;
;
;
;
;
;
;
;
reset
int1/hold
int2/int3
timer
Synch receive
Synch transmit
Asynch Tran/Rec
reserved interrupt for emulator
;
;
None maskable interrupt
reserved interrupt for emulator
Feature Phone based on TMS320LC203
19
Appendix A. Source Code
/*
TMS320LC203 UART LINK COMMAND FILE
uart.obj
intp.obj
-m uart.map
-o uart.out
-stack 512
-cr
-i c:\dsp\c2xx\lib
-l c:\dsp\c2xx\lib\rts2xx.lib
*/
MEMORY
{
PAGE 0 :
VECS
CODE
EXT_PRG
BLK_B0
BLK_B0M
:
:
:
:
:
o
o
o
o
o
=
=
=
=
=
0x0000
0x0040
0x0600
0xFE00
0xFF00
,
,
,
,
,
l
l
l
l
l
=
=
=
=
=
0x0040
0x05C0
0xf7ff
0x0100
0x0100
/*
/*
/*
/*
/*
/*
Program space
Vector area
1.4K CODE
External Prog
BLK B0
BLK B0’
*/
*/
*/
*/
*/
*/
PAGE 1 :
MEM_REG
BLK_B2
BLK_B0
BLK_B0M
BLK_B1
BLK_B1M
EXT_DAT
:
:
:
:
:
:
:
o
o
o
o
o
o
o
=
=
=
=
=
=
=
0x0000
0x0060
0x0100
0x0200
0x0300
0x0400
0x0800
,
,
,
,
,
,
,
l
l
l
l
l
l
l
=
=
=
=
=
=
=
0x0060
0x0020
0x0100
0x0100
0x0100
0x0100
0xf7ff
/*
/*
/*
/*
/*
/*
/*
/*
Data space
Mem Map Reg
BLK B2
BLK B0
BLK B0’
BLK B1
BLK B1’
Ext Data
*/
*/
*/
*/
*/
*/
*/
*/
/*
/*
/*
/*
/*
int vectors
code
Init data
Uninit data
Temp Storage
}
SECTIONS {
vectors
.text
.data
.bss
temp
.cinit
.stack
.const
:
:
:
:
:
:
:
:
{}
{}
{}
{}
{}
{}
{}
{}
}
20
Literature Number: BPRA050
>
>
>
>
>
>
>
>
VECS
CODE
BLK_B0
BLK_B1
BLK_B2
EXT_PRG
EXT_DAT
EXT_DAT
PAGE
PAGE
PAGE
PAGE
PAGE
PAGE
PAGE
PAGE
0
0
0
1
1
0
1
1
*/
*/
*/
*/
*/
Appendix B. PAL Programming
Appendix B. PAL Programming
MODULE module_name
gpt3 DEVICE ’p16v8as’;
"INPUTS
A15,BR,DS,PS
IS,XF,FSX
PIN 2,3,4,5;
PIN 6,7,8;
"OUTPUTS
PSL,PSU,DSL,DSU,FSL,FSH
PIN 12,19,18,17,16,15;
X,C,Z=.X.,.C.,.Z.;
EQUATIONS
!PSL
!PSU
= !PS & !A15;
= !PS & A15;
!DSL
!DSU
= !DS & !A15 & BR;
= !DS & A15 & BR # !IS & A15;
!FSL
!FSH
= !(FSX & !XF);
= !(FSX & XF);
TEST_VECTORS ([A15,BR,DS,PS,IS,XF,FSX] -> [PSL,PSU,DSL,DSU,FSL,FSH])
[
[
[
[
0,
1,
1,
1,
0,
1,
1,
0,
0,
0,
1,
0,
0,
0,
1,
1,
0,
1,
0,
1,
0,
1,
0,
1,
0]
1]
1]
0]
->
->
->
->
[
[
[
[
0 ,
1 ,
1,
1,
1
0
1
1
,
,
,
,
1
1
1
1
,
,
,
,
1
0
0
1
,
,
,
,
0
0
1
0
,
,
,
,
0
1
0
0
];
];
];
];
END module_name
Feature Phone based on TMS320LC203
21
Appendix B. PAL Programming
22
Literature Number: BPRA050
Appendix C. Schematics
Appendix C. Schematics
Feature Phone based on TMS320LC203
23
24
Literature Number: BPRA050
1
2
3
4
6
5
EARAL
Vdd
+
C1
U4
+
2
Vs+
J2
1
6
2
7
3
8
4
9
5
D
C1+
C1-
1uF
C4
6
+
Vs-
C2+
C2-
1uF
14
7
T1OUT
T2OUT
13
8
DB9
R1IN
R2IN
T1IN
T2IN
R1OUT
R2OUT
C2
1uF
R19
10K
1
3
R1
10K
+
C3
1uF
EARGSL
4
5
SW1A
1
U7
16
LNSELL
15
FS_L
13
12
14
FS_L
8
9
7
LINSEL
DIP-SW8
11
10
12
9
FS_L
MAX3232
Vdd
Vdd
MCLK
MCLK
DOUT
FSX
TSX/DCLKX
11
PDN
R4
10K
R5
10K
R6
10K
R7
10K
R8
10K
D
PHONEPLUG1
EMUTEL
MMUTEL
MICINL
R13
10K
17
VMID
R3
10K
EARBL
EMUTEL
MMUTEL
20
19
18
MICBIAS
MICGS
MICIN
CLK
1
R20
2K7
10
6
EARMUTE
MICMUTE
DIN
FSR
DCLKR
J3
2
4
3
EARA
EARGS
EARB
TLV320AC36
Vdd
U3
11
10
9
4
DIP-SW8
D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
D10
D11
D12
D13
D14
D15
C47
10uF
C
J4
SW1E
5
DIP-SW8
DIV2
6
DIP-SW8
SW1G
7
DIP-SW8
SW1H
8
DIP-SW8
DIV1
BIO
BIO
I/O0
I/O1
I/O2
I/O3
BOOT*
I/O0
I/O1
I/O2
I/O3
R9
22K
U2
3
7
2
B
93
95
96
97
8
9
12
13
5
3
10
Vcc
+
PHONEPLUG1
U1
SW1F
SW2
SW-PB
C
GNDa
SW1D
Vdd
B
R14
10K
470pF
22
23
24
26
27
28
29
31
32
33
34
36
38
39
40
41
12
3
DIP-SW8
C7
1uF
D[0..15]
CT
SEN
RESIN
C6
100nF
REF
RST
RSET
TOUT
1
6
5
RESET*
TLC7705IP
C5
100nF
Vdd Vdd
R11 R12
10K 10K
Vdd
TOUT
92
1
99
2
100
79
77
76
78
82
80
81
Vdd
TX
RX
IO0/DTR
IO1/DSR
IO2/RTS
IO3/CTS
XF
CLKX
CLKR
FSR
DR
FSX
DX
CLKIN/X2
X1
DIV2
DIV1
PLL5V
HOLDA
INT3
INT2
HOLD/INT1
NMI
TOUT
TEST
BIO
BOOT
RS
CLKOUT1
READY
DS
IS
PS
BR
WE
RD
STRB
R/W
TRST
EMU1/OFF
EMU0
TCK
TDO
TDI
TMS
Vdd
GNDa
D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
D10
D11
D12
D13
D14
D15
13
SW1C
C57
3
A
DSBL
2
B
D
1
C
F
14.31818 PROG OSC
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
A15
14
C
5
6
7
98
87
84
85
86
89
90
6
20
19
18
17
15
XF
MCLK
XF
DR
FSX
DX
R2
10K
SW1B
2
LNSELH
FSX
R15
10K
15
S1
DIP-SW8
Vdd
INT3
FS
INT1
NMI
CLKOUT
U5
INT3
FS
INT1
NMI
15
FS_H
13
12
14
FS_H
8
9
7
MCLK
11
CLKOUT
49
51
52
53
43
44
45
46
47
FS_H
1
LINSEL
EARA
EARGS
EARB
DOUT
FSX
TSX/DCLKX
EARMUTE
MICMUTE
DIN
FSR
DCLKR
MICBIAS
MICGS
MICIN
CLK
PDN
VMID
2
4
3
EARAH
EARGSH
EARBH
10
6
EMUTEH
MMUTEH
20
19
18
R18
TDO
TCK
EMU0
1
3
5
7
9
11
13
2
4
6
8
10
12
14
B
EMUTEH
MMUTEH
M1
2k
R17
10k
MICROPHONE
C45
.33uF
GNDa
TLV320AC36
C46
1uF
C58
470pF
55
56
57
58
60
61
62
64
66
67
68
69
71
72
73
74
J1
SPEAKER
17
TMS320LC203
TMS
TDI
R16
2K7
TRST
GNDa
DS
IS
PS
BR
WE
EMU1
HEADER 7X2
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
A15
A
DS
IS
PS
BR
WE
A
Title
A[0..15]
Size
Feature Phone based on TMS320LC203
Number
Revision
B
Date:
File:
1
2
3
4
21-Oct-1996
C:\ADVSCH\2XX\APLC203.SCH
5
Feature Phone based on TMS320LC203
Sheet1 of 6
Drawn By: Michael Seidl
6
25
1.0
1
2
3
4
Data RAM
0000-7FFF
D
5
6
Program RAM
8000-FFFF
Global ROM
8000-FFFF
0000-7FFF
D
A[0..14]
U8
A14
A13
A12
A11
A10
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
1
26
2
23
21
24
25
3
4
5
6
7
8
9
10
A14
A13
A12
A11
A10
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
U10
OE
CS
WE
I/O0
I/O1
I/O2
I/O5
I/O4
I/O3
I/O6
I/O7
22
20
27
11
12
13
17
16
15
18
19
A14
A13
A12
A11
A10
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
D0
D1
D2
D3
D4
D5
D6
D7
1
26
2
23
21
24
25
3
4
5
6
7
8
9
10
IDT71V256SA
A14
A13
A12
A11
A10
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
U12
OE
CS
WE
I/O0
I/O1
I/O2
I/O5
I/O4
I/O3
I/O6
I/O7
22
20
27
11
12
13
17
16
15
18
19
A14
A13
A12
A11
A10
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
D0
D1
D2
D3
D4
D5
D6
D7
1
26
2
23
21
24
25
3
4
5
6
7
8
9
10
IDT71V256SA
A14
A13
A12
A11
A10
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
U14
OE
CS
WE
I/O0
I/O1
I/O2
I/O5
I/O4
I/O3
I/O6
I/O7
22
20
27
11
12
13
17
16
15
18
19
A14
A13
A12
A11
A10
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
D0
D1
D2
D3
D4
D5
D6
D7
1
26
2
23
21
24
25
3
4
5
6
7
8
9
10
IDT71V256SA
A14
A13
A12
A11
A10
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
U16
OE
CS
WE
I/O0
I/O1
I/O2
I/O5
I/O4
I/O3
I/O6
I/O7
22
20
27
A14
A13
A12
A11
A10
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
D0
D1
D2
D3
D4
D5
D6
D7
11
12
13
17
16
15
18
19
27
26
2
23
21
24
25
3
4
5
6
7
8
9
10
A14
E
A13
G
A12
A11
A10
A9
DQ1
A8
DQ2
A7
DQ3
A6
DQ4
A5
DQ5
A4
DQ6
A3
DQ7
A2
DQ8
A1
A0
MX27L256
IDT71V256SA
20
22
BR
11
12
13
15
16
17
18
19
D0
D1
D2
D3
D4
D5
D6
D7
C
C
WE
DSL
DSU
PSL
PSU
BR
IS
U17
U9
A14
A13
A12
A11
A10
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
B
1
26
2
23
21
24
25
3
4
5
6
7
8
9
10
A14
A13
A12
A11
A10
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
U11
OE
CS
WE
I/O0
I/O1
I/O2
I/O5
I/O4
I/O3
I/O6
I/O7
22
20
27
11
12
13
17
16
15
18
19
A14
A13
A12
A11
A10
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
D8
D9
D10
D11
D12
D13
D14
D15
IDT71V256SA
1
26
2
23
21
24
25
3
4
5
6
7
8
9
10
A14
A13
A12
A11
A10
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
U13
OE
CS
WE
I/O0
I/O1
I/O2
I/O5
I/O4
I/O3
I/O6
I/O7
22
20
27
11
12
13
17
16
15
18
19
A14
A13
A12
A11
A10
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
D8
D9
D10
D11
D12
D13
D14
D15
IDT71V256SA
1
26
2
23
21
24
25
3
4
5
6
7
8
9
10
A14
A13
A12
A11
A10
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
U15
OE
CS
WE
I/O0
I/O1
I/O2
I/O5
I/O4
I/O3
I/O6
I/O7
22
20
27
11
12
13
17
16
15
18
19
D8
D9
D10
D11
D12
D13
D14
D15
IDT71V256SA
A14
A13
A12
A11
A10
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
1
26
2
23
21
24
25
3
4
5
6
7
8
9
10
A14
A13
A12
A11
A10
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
OE
CS
WE
22
20
27
B
I/O0
I/O1
I/O2
I/O5
I/O4
I/O3
I/O6
I/O7
D8
D9
D10
D11
D12
D13
D14
D15
11
12
13
17
16
15
18
19
8
4
10
BLNK
L_DEC
R_DEC
STR
A
B
C
D
5
3
2
13
12
IS
D0
D1
D2
D3
TIL311
IDT71V256SA
D[0..15]
A
A
Title
Size
Feature Phone based on TMS320LC203
Number
Revision
B
Date:
File:
1
26
Literature Number: BPRA050
2
3
4
5
21-Oct-1996
C:\ADVSCH\2XX\203MEM.SCH
Sheet 2 of 6
Drawn By: Michael Seidl
6
1.0
1
2
3
4
6
5
D
D
U21
10K
Vdd
9
8
7
6
5
4
3
2
1
9
8
7
6
5
4
3
2
1
R8
R7
R6
R5
R4
R3
R2
R1
COM
Vdd
R8
R7
R6
R5
R4
R3
R2
R1
COM
U22
10K
J8
Vdd
I/O0
I/O1
I/O2
I/O3
U18
1
A15
BR
DS
PS
IS
XF
FSX
A15
BR
DS
PS
IS
XF
FSX
C
2
3
4
5
6
7
8
9
10
CLK
Vcc
I0
I1
I2
I3
I4
I5
I6
I7
I/O0
I/O1
I/O2
I/O3
I/O4
I/O5
I/O6
I/O7
GND
20
19
18
17
16
15
14
13
12
PSU
DSL
DSU
FS_L
FS_H
PSU
DSL
DSU
FS_L
FS_H
PSL
PSL
11
OE
!PSU* = !PS* & A15
!DSL* = !DS* & !A15 & BR*
!DSU* = !DS* & A15 & BR* | !IS* & A15
!FS_L = !(FSX & !XF)
!FS_H = !(FSX & XF)
!PSL* = !PS* & !A15
TOUT
EMUTEL
MMUTEL
EMUTEH
MMUTEH
INT3
PALLV16V8-10PC
INT1
NMI
CLKOUT
BIO
U6
FS
FS
B
MCLK
7
5
4
6
14
13
15
1
2
3
9
QD
QE
QF
QG
QH
QI
QJ
QL
QM
QN
CKO
CKI
33K
R21
10M
TOUT
EMUTEL
MMUTEL
EMUTEH
MMUTEH
INT3
FS
INT1
NMI
CLKOUT
BIO
47
R22
11
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
I/O0
I/O1
I/O2
I/O3
C
28PIN
33pF
U23
2.048MHz
C46
CKO
CLR
B
10
12
15pF
SN74HC4060
A
A
Title
Size
Feature Phone based on TMS320LC203
Number
Revision
B
Date:
File:
1
2
3
4
21-Oct-1996
C:\ADVSCH\2XX\203LOGIC.SCH
5
Feature Phone based on TMS320LC203
1.0
Sheet 3 of 6
Drawn By: Michael Seidl
6
27
2
3
Vdda
U19
TLV2217-33
Vdd
1
D
L1
1
2
C14
10uF
+
Vin
3
C44
10uF
1
+
C43
22uF
6
5
U20
uA7805AC
Vcc
+3.3V
GND
Ferrite Bead
+
4
J7
+5V
Vin
3
GND
1
+
D
1
2
3
4
C42
10uF
1
2
2
4 HEADER
L2
2
Ferrite Bead
GNDa
Vcca
Vdd
1
L3
2
Ferrite Bead
+
C54
10uF
+
C55
10uF
GNDa
C
Close to TMS320LC203
C8
100nF
C9
100nF
C
Vdd
C10
100nF
Close to Osc. and TLC7705
C11
100nF
C12
100nF
C13
100nF
C25
100nF
Vdd
C26
100nF
Close to TLV320AC3x
C27
100nF
Vdda
C28
100nF
C29
100nF
GNDa
Vdd
Close to memory devices
Vdd
Vcc
Close to PAL
Close to LED display
B
Vdd
Close to TL061
+
C16
100nF
C17
100nF
C18
100nF
C19
100nF
C20
100nF
C21
100nF
C22
100nF
C23
100nF
C24
100nF
C30
100nF
Vcca
Close to MAX3232
C40
100nF
C41
4.7uF
B
C56
100nF
GNDa
A
A
Title
Size
Feature Phone based on TMS320LC203
Number
Revision
B
Date:
File:
1
28
Literature Number: BPRA050
2
3
4
5
21-Oct-1996
C:\ADVSCH\2XX\203POWER.SCH
Sheet4 of 6
Drawn By: Michael Seidl
6
1.0
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