Texas Instruments | Interfacing the TLC32040 Family to the TMS320 Family (Rev. A) | Application notes | Texas Instruments Interfacing the TLC32040 Family to the TMS320 Family (Rev. A) Application notes

Texas Instruments Interfacing the TLC32040 Family to the TMS320 Family (Rev. A) Application notes
Interfacing the TLC32040
Family to the TMS320 Family
SLAU001A
July 1995
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Contents
Section
Title
Page
1
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
2
TLC32040 Interface to the TMS32010/E15 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.1 Hardware . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.1.1 Parts List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.1.2 Hardware Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.2 Software . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.2.1 Initializing the Digital Signal Processor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.2.2 Communicating with the TLC32040 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.2.3 TLC32040 Secondary Communication . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3
3
3
4
4
4
4
5
3
TLC32040 Interface to the TMS32020/C25 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.1 Hardware Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.2 Software . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.2.1 Initializing the TMS32020/C25 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.2.2 Communicating with the TLC32040 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.2.3 Secondary Communications – Special Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7
7
7
8
8
8
4
TLC32040 Interface to the TMS320C17 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.1 Hardware Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.2 Software . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.2.1 Initializing the TMS320C17 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.2.2 AIC Communications and Interrupt Management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.2.3 Secondary Communications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
11
11
12
12
12
13
5
Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Appendices
Title
Page
A
TLC32040 and TMS32010 Flowcharts and Communication Program . . . . . . . . . . . . . . . . . . . . . . . . . 17
B
TLC32040 and TMS32020 Flowcharts and Communication Program . . . . . . . . . . . . . . . . . . . . . . . . . 23
C
TLC32040 and TMS320C17 Flowcharts and Communication Program . . . . . . . . . . . . . . . . . . . . . . . . 35
iii
iv
1
Introduction
The TLC32040 and TLC32041 analog interface circuits are designed to provide a high level of system
integration and performance. The analog interface circuits combine high resolution A/D and D/A converters,
programmable filters, digital control and timing circuits as well as programmable input amplifiers and
multiplexers. Emphasis is placed on making the interface to digital signal processors (the TMS320 family) and
most microprocessors as simple as possible. This application report describes the software and circuits
necessary to interface to numerous members of the TMS320 family. It presents three circuits for interfacing
the TLC32040 Analog Interface Circuit to the TMS320 family of digital signal processors. Details of the
hardware and software necessary for these interfaces are provided.
To facilitate the discussion of the software the following definitions and naming conventions are used:
1. >nnnn – a number represented in hexadecimal.
2. Interrupt service routine – a subroutine called in direct response to a processor interrupt.
3. Interrupt subroutine – any routine called by the interrupt service routine.
4. Application program (application routine) – the user’s application dependent software (e.g., digital
filtering routines, signal generation routines, etc.)
1
2
2
TLC32040 Interface to the TMS32010/E15
2.1
Hardware
Because the TLC32040 (Analog Interface Circuit) is a serial-I/O device, the interface to the TMS32010, which
has no serial port, requires a small amount of glue-logic. The circuit shown in Figure 1 accomplishes the
serial-to-parallel conversion for the AIC operating in synchronous mode.
2.1.1
Parts List
The interface circuit for the TMS32010 uses the following standard logic circuits:
1.
2.
3.
4.
5.
6.
One SN74LS138 3-to-8-line address decoder
One SN74LS02 Quad NOR-Gate
One SN74LS00 Quad NAND-Gate
One SN74LS04 Hex Inverter
One SN74LS74 Dual D-Flip-Flop
Two SN74LS299 8-bit Shift Registers
TLC32040
74LS299
TMS32010/C15
S1
DEN
G2
S1
Y0
Y1
G1
S1
QH’
U2
G2
h
8
U1
SHIFT
CLK
SR
a
A0/PA0
A1/PA1
A2/PA2
G2
L6
A
B
C
74LS299
S1
G2
L2
L1
S1
D16
16
QH’
U3
G2
h
8
SR
D0
a
L3
WE
Q D
U3
DR
74LS74
L4
L5
MSTRCLK
EODX
CLKOUT
INT
Figure 1. AIC Interface to TMS32010/E15
3
2.1.2
Hardware Description
The SN74LS138 is used to decode the addresses of the ports to which the TLC32040 and the interface logic
have been mapped. If no other ports are needed in the development system, this device may be eliminated and
the address lines of the TMS32010 used directly in place of Y1 and Y0 (see Figure 1).
Since the interface circuits are only addressed when the TMS32010 executes an IN or an OUT instruction, gates
L1, L2, L3, L4, and L5 are required to enable reading and writing to the shift registers only on these instructions.
The TBLW instruction is prohibited because it has the same timing as the OUT instruction. Flip-flop U4 ensures
that the setup and hold times of SN74LS299 shift registers are met.
Although not shown in the circuit diagram, it is recommended that the CLR pins of the SN74LS299 shift
registers as well as the RESET pin of the AIC be tied to the power-up reset circuit shown in the AIC data sheet.
This ensures that the registers are clear when the AIC begins to transfer data and decrease the possibility that
the AIC will shift in bad data which could cause the AIC to shut down or behave in an unexpected manner.
2.2
Software
The flowcharts for the communication program along with the TMS32010 program listing are presented in
Appendix A. If this software is to be used, and application program that moves data into and out of the transmit
and receive registers must be supplied.
2.2.1
Initializing the Digital Signal Processor
As shown in the flowcharts in Appendix A, the program begins with an initialization routine which clears both
the transmit/receive-end flag and the secondary communication flag, and stores the addresses of the interrupt
subroutines. The program uses the MPYK...PAC instruction sequence to load data memory locations with the
12-bit address of the subroutines. This sequence is only necessary if the subroutines are to reside in program
memory locations larger than > 00FF. Otherwise, the instructions LACK and SACL may be used to initialize
the subroutine-address storage locations.
2.2.2
Communicating with the TLC32040
After the storage registers and status register have been initialized, the interrupt is enabled and control is passed
to the user’s application routine (i.e., the system-dependent software that processes received data and prepares
data for transmission). The program ignores the first interrupt that occurs after interrupts are enabled (page 22,
line 207, IGINT routine), allowing the AIC to stabilize after a reset. The application routine should not write
to the shift registers while data is moving into (and out of) them. In addition, it should ensure that no primary
data is written to the shift registers between a primary and secondary data-communication pair. The first
objecive can be accomplished by writing to the SN74LS299 shift registers as quickly as possible after the
receive interrupt. The number of instruction cycles between the data transfers can be calculated from the
conversion frequency. By counting instruction cycles in the application program, it is possible to determine
whether the data transfer will conflict with the OUT instruction to the shift register. The second objective can
be accomplished by monitoring SNDFLG in the application program. If SNDFLG is true (>00FF), secondary
communication has not been completed.
When the processors receives an interrupt, the program counter is pushed onto the hardware stack and then the
program counter is set to > 0002, the location of the interrupt service routine, INTSVC (page 19, line 46). The
interrupt service routine then saves the contents of the accumulator and the status register and calls the interrupt
subroutine to which XVECT points. If secondary communication is to follow the upcoming primary
communication, XVECT, is set by the application program to refer to SINT1, otherwise, XVECT defaults to
NINT (i.e., the normal interrupt routine).
4
Because the interrupt subroutine makes one subroutine call and uses two levels of the hardware stack, the
application program can only use two levels of nesting (i.e., if stack extension is not used). This means that any
subroutine called by the application program can only call subroutines containing no instructions that use the
hardware stack (e.g., TBLW) and that make no other subroutine calls. In addition, if the application program
and communication program are being implemented on an XDS series emulator, the emulator consumes one
level of the hardware stack and allows the application program only one level of nesting (i.e., one level of
subroutine calls).
As shown in the flowcharts in Appendix A, the normal interrupt routine reads the A/D data from the shift
registers and then sets the receive/transmit end-flag (RXEFLG). The application program must write the
outgoing D/A data word to the shift registers at a time convenient to the application routine. It should have the
restriction that the data be written before the next data transfer.
2.2.3
TLC32040 Secondary Communication
If it is necessary to write to the control register of the AIC or configure any of the AIC internal counters, the
application program must initiate a primary/secondary communication pair. This can be accomplished by
placing a data word in which bits 0 and 1 are both high into DXMT, placing the secondary control word (see
program listing page 19) in D2ND, and placing the address of the secondary communication subroutine,
SINT1, in XVECT. When the next interrupt occurs, the interrupt subroutine will call routine SINT1. SINT1
reads the A/D information from the shift registers and writes the secondary communication word to the shift
registers.
5
6
3
TLC32040 Interface to the TMS32020/C25
3.1
Hardware Description
Because the TLC32040 is designed specifically to interface with the serial port of the TMS32020/C25, the
interface requires no external hardware. Except for CLKR and CLKX, there is a one-to-one correspondence
between the serial port control and data pins of TMS32020 and TLC32040. CLKR and CLKX are tied together
since both the transmit and the receive operations are synchronized with SHIFT CLK of the TLC32040. The
interface circuit, along with the communication program (page 26), allows the AIC to communicate with the
TMS32020/C25 in both synchronous and asynchronous modes. See Figures 2, 3, and 4.
3.2
Software
The program listed in Appendix B allows the AIC to communicate with the TMS32020 in synchronous or
asynchronous mode. Although originally written for the TMS32020, it will work just as well for the
TMS320C25.
5V
TLC32020/C25
TLC32040
WORD/BYTE
MSTR CLK
FSX
DX
FSR
DR
SHIFT CLK
CLKOUT
FSX
DX
FSR
DR
CLKX
CLKR
Figure 2. AIC Interface to TMS32020/C25
SHIFT CLK
FSR, FSX
DR
DX
D15
D15
D14
D13
D12
D11
D2
D1
D0
D14
D13
D12
D11
D2
D1
D0
EODR, EODX
The sequence of operation is:
1. The FSX or FSR pin is brought low.
2. One 16-bit word is transmitted or one 16-bit byte is received.
3. The FSX or FSR pin is brought high.
4. The EODX or EODR pin emits a low-going pulse as shown.
Figure 3. Operating Sequence for AIC-TMC32020/C25 Interface
7
FSX
FSR
Figure 4. Asynchronous Communication AIC-TMS32020/C25 Interface
3.2.1
Initializing the TMS32020/C25
This program starts by calling the initialization routine. The working storage registers for the communication
program and the transmit and receive registers of the DSP are cleared, and the status registers and interrupt
mask register of the TMS32020/C25 are set (see program flow charts in Appendix B). The addresses of the
transmit and receive interrupt subroutines are placed in their storage locations, and the addresses of the routines
which ignore the first transmit and receive interrupts are placed in the transmit and receive subroutine pointers
(XVECT and RVECT). The TMS32020/C25 serial port is configured to allow transmission of 16-bit data
words (FO), the serial port format bit of the TMS32020/C25 must be set to zero) with an externally generated
frame synchronization (FSX and FXR are inputs, TXM bit is set to 0).
3.2.2
Communicating with the TLC32040
After the TMS32020/C25 has been initialized, interrupts are enabled and the program calls subroutine IGR.
The processor is instructed to wait for the first transmit and receive interrupts (XINT and RINT) and ignore
them. After the TMS32020 has received both a receive and a transmit interrupt, the IGR routine will transfer
control back to the main program and IGR will not be called again.
If the transmit interrupt is enabled, the processor branches to location 28 in program memory at the end of a
serial transmission. This is the location of the transmit interrupt service routine. The program context is saved
by storing the status registers and the contents of the accumulator. Then the interrupt service routine calls the
interrupt subroutine whose address is stored in the transmit interrupt pointer (XVECT).
A similar procedure occurs on completion of a serial receive. If the receive interrupt is enabled, the processor
branches to location 26 in program memory. As with the transmit interrupt service routine (XINT, page 30, line
226), the receive interrupt service routine (page 30, line 194) saves context and then calls the interrupt
subroutine whose address is stored in the receive interrupt pointer (RVECT). It is important that during the
execution of either the receive or transmit interrupt service routines, all interrupts are disabled and must be
re-enabled when the interrupt service routine ends.
The main program is the application program. Procedures such as digital filtering, tone-generation and
detection, and secondary communication judgment can be placed in the application program. In the program
listing shown in Appendix B, a subroutine (C2ND) is provided which will prepare for secondary
communication. If secondary communication is required, the user must first write the data with the secondary
code to the DXMT register. This data word should have the two least significant bits set high (e.g., >0003). The
first 14 bits transmitted will go to the D/A converter and the last two bits indicate to the AIC that secondary
communication will follow. After writing to the SXMT register, the secondary communication word should
be written to the D2ND register.
This data may be used to program the AIC internal counters or to reconfigure the AIC (e.g., to change from
synchronous to asynchronous mode or to bypass the bandpass filter). After both data words are stored in their
respective registers, the application program can then call the subroutine C2ND which will prepare the
TMS32020 to transmit the secondary communication word immediately after primary communication.
3.2.3
8
Secondary Communicating – Special Considerations
This communication program disables the receive interrupt (RINT) when secondary communication is
requested. Because of the critical timing between the primary and secondary communication words and
because RINT carries a higher priority than the transmit interrupt, the receive interrupt cannot be allowed to
interrupt the processor before the secondary data word can be written to the data-transmit register. If this
situation were to occur, the AIC would not receive the correct secondary control word and the AIC could be
shut down.
In many applications, the AIC internal registers need only be set at the beginning of operation, (i.e., just after
initialization). Thereafter, the DSP only communicates with the AIC using primary communication. In cases
such as these, the communication program can be greatly simplified.
9
10
4
TMS32040 Interface to the TMS320C17
4.1
Hardware Description
As shown in Figure 5, the TMS320C17 interfaces directly with the TLC32040. However, because the
TMS320C17 responds more slowly to interrupts than the TMS32010/E15 or the TMS32020/C25, additional
circuit connections are necessary to ensure that the TMS320C17 can respond to the interrupt, accomplish the
context-switching that is required when an interrupt is serviced, and proceed with the interrupt vector. This
must all be accomplished within the strict timing requirements imposed by the TLC32040. To meet these
requirements, FSX of the TLC32040 is connected to the EXINT pin of the TMS320C17. This allows the
TMS320C17 to recognize the transmit interrupt before the transmission is complete. This allows the interrupt
service routine to complete its context-switching while the data is being transferred. The interrupt service
routine branches to the interrupt subroutines only after the FSX flag bit has been set. This signals the end of
data transmission.
The other hardware modification involves connecting the EODX pin of the TLC32040 to the BIO pin of the
TMS320C17. Because the TMS320C17 serial port accepts data in 8-bit bytes (see Figure 6) and the TLC32040
controls the byte sequence (i.e., which byte is transmitted first, the high-order byte or the low-order byte) it is
important that the TMS320C17 be able to distinguish between the two transmitted bytes. The EODX signal
is asserted only once during each transmission pair, making it useful for marking the end of a transmission pair
and synchronizing the TMS320C17 with the AIC byte sequence. After synchronization has been established,
the BIO line is no longer needed by the interface program and may be used elsewhere.
Because the TMS320C17 serial port operates only in byte mode, 16-bit transmit data should be separated into
two 8-bit bytes and stored in separate registers before a transmit interrupt is acknowledged. Alternatively, the
data can be prepared inside the interrupt service routine before the interrupt subroutine is called. From the time
that the interrupt is recognized to the end of the data transmission is equivalent to 28 TMS320C17 instruction
cycles.
TLC320C17
TLC32040
WORD/BYTE
EXINT
FSX
CLK OUT
DX0
FSR
DR0
SCLK
FSX
MSTR CLK
DX
FSR
DR
SHIFT CLK
Figure 5. AIC Interface to TMS320C17
11
SHIFT CLK
FSR, FSX
DR
DX
D15
D15
D14
D13
D9
D14
D13
D9
D8
D8
D7
D6
D2
D1
D0
D7
D6
D2
D1
D0
EODR, EODX
The sequence of operation is:
1. The FSX or FSR pin is brought low.
2. One 8-bit word is transmitted or one 8-bit byte is received.
3. The EODX or EODR pins are brought low.
4. The FSX or FSR emit a positive frame-sync pulse that is four shift clock cycles wide.
5. One 8-bit byte is transmitted and one 8-bit byte is received.
6. The EODX and EODR pins are brought high.
7. The FSX and FSR pins are brought high.
Figure 6. Operating Sequence for AIC-TMS320C17
4.2
Software
The software listed in Appendix C only allows the AIC to communicate with the TMS320C17 in synchronous
mode. This communication program is supplied with an application routine, DLB (Appendix C, program
listing line 253), which returns the most recently received data word back to the AIC (digital loopback).
4.2.1
Initializing the TMS320C17
The program begins with an initialization routine (INIT, page 40, line 120). Interrupts are disabled and all the
working storage registers used by the communication program are cleared. Both transmit registers are cleared,
the constants used by the program are initialized and the addresses of the subroutines called by the program
are placed in data memory. This enables the interrupt service routine to call subroutines located in
program-memory addresses higher than 255. After the initialization is complete, the TMS320C17 monitors
the FSX interrupt flag in the control register to establish synchronization with the AIC.
4.2.2
AIC Communications and Interrupt Management
Because the AIC FSX pin is tied to the EXINT line of the TMS320C17 and the delay through the interrupt
multiplexer, the interrupt service routine is called four instruction cycles after the falling edge of FSX. The
interrupt service routine (INTSVC, Appendix C, program listing, line 90) completes its context switching and
then monitors the lower control register, polling the FSX flag bit that indicates the end of the 8-bit serial data
transfer. If the FSX flag bit is set, the transfer is complete. After this bit is set, control is transferred to the
interrupt subroutine whose address is stored in VECT. The serial communication must be complete before data
is read from the data receive register.
When no secondary communication is to follow, the interrupt subroutines, NINT1 and NINT2, are called. If
data has been stored in DXMT2 (the low-order eight bits of the transmit data word), which does not indicate
that secondary communication is to follow, the interrupt service routine calls NINT1 when the first 8-bit serial
transfer is complete. NINT1 immediately writes the second byte of transmit data, (i.e., the contents of DXMT2)
to transmit data register 0 (TR0). It then moves the first byte of the received data (i.e., the high-order byte of
the A/D conversion result) into DRCV1. NINT1 then stores in VECT the address of NINT2. NINT2 is called
at the end of the next 8-bit data transfer and resets the FSX interrupt flag bit by writing a logic high to it. The
next interrupt (a falling edge of EXINT) occurs before the interrupt service routine returns control to the main
12
program. This is an acceptable situation since the TMS320C17, on leaving the interrupt service routine,
recognizes that an interrupt has occurred and immediately responds by servicing the interrupt.
The interrupt subroutine NINT2 is similar in operation to NINT1. It stores the low-order byte of receive data
(bits 7 through 0 of the A/D conversion result) and stores the address of the next interrupt subroutine in VECT.
NINT2 does not write to the transmit data register, TR0. This task has been left to the application program. After
the transmit data has been prepared by the main program and the data has been stored in DXMT1 and DXMT2,
the main program stores the first byte of the transmit data in transmit data register 0 (TR0).
4.2.3
Secondary Communications
The interrupt subroutines SINT1 through SINT4 are called when secondary communication is required. For
secondary communication, DXMT1 and DXMT2 will hold the primary communication word. DXMT3 and
DXMT4 will hold the secondary communication word. VECT, the subroutine pointer should then be initialized
to the address of SINT1. As with the normal (primary communication only) interrupt subroutines (i.e., NINT1
and NINT2), the secondary communication routines will change VECT to point to the succeeding routine (e.g.,
SINT1 will point to SINT2, SINT2 will point to SINT3, etc.).
13
14
5
Summary
The TLC32040 is an excellent choice for many digital signal processing applications such as speech
recognition/storage systems and industrial process control. The different serial modes of the AIC
(synchronous, asynchronous, 8- and 16-bit) allow it to interface easily with all of the serial port members of
the TMS320 family as well as other processors.
15
16
A
A.1
TLC32040 and TMS32010 Flowcharts and
Communication Program
Flowcharts
Begin
NINT
*
Initialize
Receive Data
Read Shift Register
Enable Interrupt
Modify Interrupt
Location
No
Data
Transfer
End?
**
Set Secondary
Flag
Yes
Return
Secondary
Communication?
Yes
c. SECONDARY DATA COMMUNICATIONS 1
No
NINT
Write Transmit
Data
to Shift Register
***
Modify Interrupt
Location
User Area
***
Set Receive and
Transmit End Flag
a. MAIN
NINT
Receive Data
Read Shift Register
Clear Secondary
Flag
Return
d. SECONDARY DATA COMMUNICATIONS 2
Set Receive and
Transmit End Flag
Return
b. PRIMARY INTERRUPT ROUTINE
* Set, if need secondary.
** Modify to call SINT2.
*** Modify to call NINT.
**** Must execute before transfer beginning.
17
A.2
Communication Program List
0001
0002
0003
0004
0005
0006
0007
0008
0009
0010
0011
0012
0013
0014
0015
0016
0017
0018
0019
0020
0021
0022
0023
0024
0025
0026
0027
0028
0029 0000
0030 0000
0001
0031
0032
0033
0034
0035
0036
0037
0038
0039
0040
0041
0042
0043
18
0002
0003
0004
0005
0006
0007
0008
0009
000A
000C
000D
000E
000F
00FF
0001
F900
000D
*********************************************************
* When using this program, the circuit in the TLC32040 *
* data sheet or its equivalent circuit must be fused
*
* port 1 are reserved for data receiving and data
*
* transmitting. The TBLW command is prohibited because *
* it has the same timing as the OUT command. TLC32040 is *
* used only in synchronous mode.
*
*********************************************************
*
RXEFLG
EQU
>02
receive and xmit end flag.
SNDFLG
EQU
>03
secondary communication flag.
DRCV
EQU
>04
receive data storage.
DXMT
EQU
>05
xmit data storage.
D2ND
EQU
>06
secondary data storage.
XVECT
EQU
>07
interrupt address storage.
ACHSTK
EQU
>08
ACCH stack.
ACLSTK
EQU
>09
ACCL stack.
SSTSTK
EQU
>0A
Status stack.
ANINT
EQU
>0C
interrupt address 1
ASINT1
EQU
>0D
interrupt address 2
ASINT2
EQU
>0E
interrupt address 3
TMP0
EQU
0F
temporary register.
*
SET
EQU
>FF
ONE
EQU
>01
*
=================
*
Reset vector.
=================
AORG >0000 program start address.
B
EPIL jump to initialization.
*********************************************************
* =================
*
* Interrupt vector.
*
* =================
*
* When secondary communication, modify the content of
*
* XVECT to the address of secondary communication and
*
* store secondary data in D2ND.
*
* ex.
*
*
LAC
ASINT1,0 modify XVECT
*
*
SACL XVECT,0
*
*
|
*
*
LAC
D2ND,0
store secondary data.
*
*********************************************************
0044
0045
0046
0047
0048
0049
0050
0051
0052
0053
0054
0055
0056
0057
0058
0059
0060
0061
0062
0063
0064
0065
0066
0067
0068
0069
0070
0071
0072
0073
0074
0075
0076
0077
0078
0079
0080
0081
0082
0083
0084
0085
0086
0087
0088
0089
0090
0091
0092
0093
0094
0095
0096
0097
0002
0002
0002
0003
0004
0005
0006
0007
0008
0009
000A
000B
000C
000D
000D
000D
000E
000E
000F
0010
0011
0012
0013
0014
0014
0015
0016
0017
0017
0018
0019
001A
001A
001B
001C
001D
001D
001E
001F
001F
AORG
>0002
interrupt vector.
7C0A
6E01
5808
5009
2007
7F8C
6508
7A09
7B0A
7F82
7F8D
INTSVC
SST
SSTSTK
push status register.
LDPK ONE
set data pointer one.
SACH ACHSTK
push ACCH.
SACL ACLSTK
push ACCL.
LAC
XVECT,0
load interruput address.
CALA
branch to interruupt routine.
ZALH ACHSTK
pop ACCH
OR
ACLSTK
pop ACCL.
LST
SSTSTK
pop stack register.
EINT
enable interrupt.
RET
return from interrupt routine.
*********************************************************
*
============================
*
*
Initialization after reset.
*
*
===========================
*
*
*
*
Data RAM locations 82H(130) through 8FH(143),
*
*
12 words of page 1, are reserved for this
*
*
program. The user must set the status register
*
*
by adding the SST command at the end of the
*
*
the initialization routine.
*
*********************************************************
*
*
*
AORG $
initial program.
6E01
EPIL
LDPK
ONE
set data page pointer one.
7E01
500F
6A0F
802C
7F8E
500C
LACK
SACL
LT
MPYK
PAC
SACl
ONE
TMP0
TMP0
NINT
save normal communication
address to its storage.
8030
7F8E
500D
MPYK
PAC
SACL
SINT1
8037
7F8E
500E
MPYK
PAC
SACL
SINT2
803A
7F8E
5007
MPYK
PAC
SACL
IGINT
7F89
5002
ZAC
SACL
RXFLG,0
5003
SACL
SNDFLG,0
ANINT
save secondary communication
address1 to its storage.
ASINT1
save secondary communication
address2 to its storage.
ASINT2
ignore interrupt once after
master reset.
XVECT
clear flags.
19
0098
0099
0100
0101
0102
0103
0104
0105
0106
0107
0108
0109
0110
0111
0112
0113
0114
0115
0116
0117
0118
0119
0120
0121
0122
0123
0124
0125
0126
0127
0128
0129
0130
0131
0132
0133
0020
0020
0020
0020
0021
0021
0022
0023
0024
0024
0025
0026
0027
0027
0028
0028
0029
002A
002A
002B
0134
0135
0136
0137
0138
0139
0140
0141
0142
0143
0144 002C
0145 002C
0146 002D
20
7F82
2002
FF00
0021
EINT
enable interrupt.
*
*********************************************************
*
==============
*
*
Main program.
*
*
=============
*
*
*
* This program allows the user two levels of nesting
*
* since one level is used as stack for the interrupt. *
* When the RXEFLG flag is false then no data transfer *
* has ocurred, if it is true then data transfer has
*
* finished. User rountines such as digital filter,
*
* secondary-data-communication judgement etc., must be *
* placed in this location. Depending on the sampling
*
* rate (conversion rate), these user routines must
*
* write the xmit data to the shift registers within
*
* approximately 500 instruction cycles. If the user
*
* requires secondary communication, it will be
*
* necessary to delay the OUT instruction until the
*
* secondary data transfer has finished.
*
*********************************************************
MAIN LAC
RXEFLG,0 wait for interrupt.
BZ
MAIN
2003
FE00
0028
LAC
BNZ
SNDFLG,0
MAIN1
skip OUT instruction during
secondary communication.
4905
OUT
DXMT,PA1
write xmit data to shift register.
7F89
5002
MAIN1 ZAC
SACL
F900
0021
B
clear flags.
RXEFLG
MAIN
loop.
*
*********************************************************
*
===========================
*
*
Normal interrupt rountine.
*
*
==========================
*
*
destroy ACC, DP.
*
*
*
* Write the contents of DXMT to the ’LS299s, receive
*
* DAC data in DRCV, and set RXEFLG flag.
*
*********************************************************
4004
NINT
IN
DRCV,PA0 receive data from shift register.
0147
0148
0149
0150
0151
0152
0153
0154
0155
0156
0157
0158
0159
0160
0161
0162
0163
0164
0165
0166
0167
0168
0169
0170
0171
0172
0173
0174
0175
0176
0177
0178
0179
0180
0181
0182
0183
0184
0185
0186
0187
0188
0189
0190
0191
0192
0193
0194
0195
002D
002E
002F
002F
0030
0030
0031
0031
7EFF
5002
LACK
SACL
set receive and xmit ended flag.
7F8D
RET
return.
*
*********************************************************
*
==============================================
*
*
Secondary communication interrupt routine 1.
*
*
==============================================
*
*
destroy ACC,DP
*
*
*
* Write the contents of D2ND to the ’LS299s, receive
*
* data in DRCV, and modify XVECT for secondary
*
* communication interrupt.
*
*********************************************************
4004
SINT1 IN
4906
OUT
DRCV,PA0 receive data from shift register.
200E
5007
LAC
SACL
D2ND,PA1 write secondary data to shift
register.
ASINT2,0 modify interrupt location.
XVECT
secondary communication 2
7EFF
5003
LACK
SACL
SET
SNDFLG,0
7F8D
RET
*
0032
0033
0034
0034
0035
0036
0036
0037
SET
RXEFLG
set secondary communication flag.
return.
*********************************************************
*
==============================================
*
*
Secondary communication interrupt routine 2.
*
*
==============================================
*
*
destroy ACC,DP
*
*
*
* Modify XVECT for normal communication, and set
*
* RXEFLG flag.
*
*********************************************************
0037
0037
0038
0039
0039
003A
003B
003B
003C
003D
003D
003E
200C
5007
SINT2 LAC
SACL
ANINT
XVECT
modify interrupt location
normal communication.
7EFF
SACL
LACK
RXEFLG
SET
set receive and xmit ended flag.
7F89
5003
ZAC
SACL
7F8D
RET
clear secondary communication flag.
SNDFLG,0
return.
21
0196
0197
0198
0199
0200
0201
0202
0203
0204
0205
0206 003E
0207 003E
0208 003F
0209 0040
0210 0040
0211 0041
0212
NO ERRORS,
22
*********************************************************
*
===========================================
*
*
Ignoring the first interrupt after reset.
*
*
===========================================
*
*
destroy ACC,DP.
*
*
*
* Ignore the first interrupt after reset. the TLC32040 *
* receives zero as DAC data but no ADC data in DRCV.
*
*
*
*********************************************************
200C
5007
IGINT LAC
SACL
7F8D
RET
END
NO WARNINGS
ANINT
XVECT
modify interrupt location
normal communication.
return.
B
B.1
TLC32040 and TMS32020 Flowcharts and
Communication Program
Flowcharts
INIT
RINT
Set ST0 Status Register
1
Push ACC, ST0
Set ST1 Status Register
2
Load RINT Vector Address
Clear B2 Internal Register
3
Call RCV or IGNRR
Mask IMR Masking Register
4
Pop ACC, ST0
Set Content of Each Vector
5
Enable Interrupt
Return
a. INITIALIZATION
6
Return
b. RECEIVED INTERRUPT SERVICE ROUTINE
INIT
Save Receive Data as AIC Code
INIT
Set Receive Flag
Set FRE Flag
Return
Return
c. RECEIVE SUBROUTINE
d. IGNORE INTERRUPT
1 – Alterable AR pointer and OVM.
2 – Alterable CNF, SXM and XF.
3 – Must clear at least 108 through 127, 19 of internal RAM.
4 – If IMR is changed by user program. INST must be changed.
5 – Their contents will be changed by their routine locations.
6 – IGNRR is executed only once after reset.
23
XNIT
Push ACC, ST0
NRM
Load XINT Vector Address
Write Transmit Data to DXR
Call NRM, S1, S2, IGNRX
7
Set Transmit Flag
Return
Pop ACC, ST0
f. PRIMARY TRANSMISSION ROUTINE
Enable Interrupt
S2
Return
e. TRANSMIT INTERRUPT SERVICE ROUTINE
Clear DXR Register
S1
Clear Secondary Flag
Write Secondary Data to DXR
Modify XINT Vector Address
Modify XINT Vector Address
8
Return
g. PRIMARY-SECONDARY COMMUNICATIONS 1
7 – IGNRX is executed only once after reset.
8 – Modify to S2 address.
9 – Modify to NRM address.
24
Modify IMR Interrupt Masking Register
Return
h. PRIMARY-SECONDARY COMMUNICATIONS 2
9
C2ND
Is Transmit Data
Secondary Code
No
IGNRX
Yes
Set Secondary Flag
Set FXE Flag
Disable Other Interrupt
Modify XINT Vector Address
10
Modify XINT Vector Address
Return
11
I. IGNORE TRANSMIT INTERRUPT
Return
10 – Modify to NRM address.
11 – Modify to S1 address.
j. SECONDARY COMMUNICATION JUDGEMENT
IGR
Finish First
RINT?
No
Yes
Finish First
SINT?
No
Yes
Return
k. IGNORE FIRST INTERRUPTS
25
B.2
Communication Program List
0001
0002
0003
0004
0005
0006
0007
0008
0009
0010
0011
0012
0013
0014
0015
0016
0017
0018
0019
0020
0021
0022
0023
0024
0025
0026
0027
0028
0029
0030
0031
0032
0033
0034
0035
0036
0037
0038
0039
0040
0041
0042
0043
0044
0045
0046
0047
0048
0049
0050
0051
0052
0053
0054
26
0000
0001
0004
006C
006D
006F
0070
0071
0072
0073
0074
0075
0076
0077
0078
0079
007A
007B
007C
007D
007E
007F
************************************************************
* ===========================================
*
* TLC32040 & TMS32020 communication program.
*
* ===========================================
*
*
by H.Okubo & W.Rowand
*
*
version 1.1
7/22/88.
*
*
*
* This is a TMS32020 – TLC32040 communication program
*
* that can be used in many systems. To use this program
*
* the TMS32020 and the TLC32040 (AIC) must be connected
*
* as shown in the publication: Linear and Interface
*
* Circuit Applications, Volume 3. The program reserves
*
* TMS32020 internal data memory 108 through 127 (B2) as
*
* flags and storage. When secondary communication is
*
* needed, every maskable interrupt except XINT is
*
* disabled until that communication finishes.
*
*
*
* If you have any questions, please let us know.
*
************************************************************
*
*
* =======================
* Memory mapped register.
* =======================
*
DRR EQU0
* data receive register address.
DXR EQU
1
* data xmit register address.
IMR EQU
4
* interrupt mask register address.
*
* ==============================================
*
Reserved onchip RAM as flags and storages.
*
(block B2 108 through 127.)
* ==============================================
*
FXE EQU
108
* ignore first XINT flag.
FRE EQU
109
* ignore first RINT flag.
TMPO EQU
111
* temporary register.
ACCHST EQU
12
* stack for ACCH.
CCLST EQU
113
* stack for ACCL.
SSTST EQU
114
* stack for STO register.
INTST EQU
115
* stack for IMR register.
RVECT EQU
116
* vector for RINT.
XVECT EQU
117
* vector for XINT.
VRCV EQU
118
* RINT vector storage.
VNRM EQU
119
* XINT vector storage.
VS1 EQU
120
* secondary vector storagel.
VS2 EQU
121
* secondary vector storage2.
DRCV EQU
122
* receive data storage.
DXMT EQU
123
* xmit data storage.
D2ND EQU
124
* secondary data storage.
FRCV EQU
125
* receive flag.
FXMT EQU
126
* xmit flag.
F2ND EQU
127
* secondary communication flag.
*
0055
0056
0057
0058 0000
0059 0000
0001
0060
0061
0062
0063
0064
0065 001A
0066 001A
00IB
0067
0068
0069
0070
0071
0072 ODIC
0073 001C
001D
0074
0075
0076 0020
0077
0078
0079
0080
0081
0082
0083 0020
0021
0084 0022
0085 0023
0024
0086
*******************************************************
* Processor starts at this address after reset.
*
*
*
AORG
0
* program start address.
*
FF80
B
STRT
* jump to initialization routine. *
0020
*******************************************************
*
*******************************************************
* Receive interrupt location.
*
*
*
AORG
26 * Rint vector.
*
FF80
B
RINT
* jump to receive interrupt
*
004A
* routine.
*
*******************************************************
*
*******************************************************
* Transmit interrupt location.
*
*
*
AORG
28 * Xint vector.
*
FF80
B
XINT * jump to xmit interrupt routine. *
005A
*******************************************************
*
AORG
32 * start initial program.
*
*******************************************************
* User must initialize DSP with the routine INIT.
*
* The user may modify this routine to suit his
*
* requirements as he likes.
*
*******************************************************
FE80 STRT
CALL INIT
*
0025
CE00
EINT
* enable interrupt.
FE80
CALL IGR
008D
*
27
0087
****************************************************************
0088
*
=================
*
0089
*
User area
*
0090
*
=================
*
0091
*
*
0092
* This program allows the user two levels of nesting,
*
0093
* since two levels are used as stack for the interrupt.
*
0094
* When the FXMT flag is false no data has occurred
*
0095
* When the FRCV flag is false, no data has been
*
0096
* received. As those flags are not reset by any
*
0097
* routine in this program, the user must reset the
*
0098
* flags if he chooses to use them and note that >00ff
*
0099
* means true, >0000 means false. User routines such as
*
0100
* digital filtering, FFTs etc. must be placed in this
*
0101
* location. Depending on the sampling rate (conver*
0102
* sion rate), these user routines must write the xmit
*
0103
* data to the DXMT registers within approximately 500
*
0104
* instruction cycles. If the user requires secondary
*
0105
* communication, data with the secondary code (xxx
*
0106
* xxxx xxxx xx11) should first be written to DXMT and
*
0107
* then secondary data should be written to D2ND. Next,
*
0108
* a call should be made to C2ND to set up SVECT and the
*
0109
* F2ND flag to perform the secondary communication.
*
0110
* Note that all maskable interrupts except XINT are
*
0111
* disabled until secondary communication has completed.
*
0112
****************************************************************
0113
*
0114
****************************************************************
0115
*
======================
*
0116
*
Initialization routine.
*
0117
*
======================
*
0118
* This routine initializes the status registers, flags,
*
0119
* vector storage contents and internal data locations
*
0120
* 96 through 107. Note that the user can modify these
*
0121
* registers (i.e., STO ST1 IMR), as long as the contents
*
0122
*do not conflict with the operation of the AIC.
*
0123
***********************************************************
0124 0025 C800 INIT LDPK 0
* set status0 register.
0125 0026 D00I LALK >OE00,0
* 0000 1110 0000 D000B
0027 OE00
0126 0028 606F SACL TMPO,0
* ARP=0 AR pointer 0
0127 0029 506F LST
TMPO
* OV =0 (Overflow reg–clear)
0128
*
* OVM=1 (Overflow mode set to 1)
0129
*
* ? =1 Not affected.
0130
*
* INTM=1 Not affected
0131
*
* DP 000000000 page 0
0132
*
0133
*
* set statusl register.
0134
*
0135 002A D00I LALK >03F0
* 0000 0011 1111 0000B
002B 03F0
0136 002C 606F SACL TMPO,0
* APB=0
0137 002D 516F LST1 TMPO
* CNF=0 (Set B0 data memory)
0138 002E
28
0139
0140
0141
0142
0143
0144
0145
0146
0147
0148
0149
0150
0151
0152
0153
0154
0155
0156
0157
0158
0159
0160
0161
0162
0163
0164
0165
*
*
*
*
*
*
*
*
*
002E
002F
0030
0031
0032
0033
CA00
6001
6000
C060
CBIF
6OA0
ZAC
SACL DXR,0
SACL DRR,0
LARK AR0,96
RPTK 31
SACL +,0
*
*
*
0034 CA30
0035 6004
0036 6073
0037 D001
0038 0067
0166 0039 6077
0167
0168 003A D001
003B 006C
0169 003C 6078
0170
0171 003D D001
003E 0071
0172 003F 6079
0173
0174 0040 D001
0041 0055
0175 0042 6076
0176
0177 0043 D001
0044 0094
0178 0045 6074
0179
0180 0046 D001
0047 0099
0181 0048 6075
0182 0049 CE26
0183 004A
*
*
*
*
*
*
TC =0
SXM=1 (enable sign extend mode.)
D9–D5=111111 not affected.
F=1 (XF pin status.)
F0=0 (16–bit data transfer mode.)
TXM=0 (FSX input)
* clear registers
*
*
* clear Block B2.
*
*
Interrupt masking
LACK
SACL
SACL
>30
* 0000 0000 0011 0000B
IMR,0
* INT ________|| ||||
INTST,0 * RINT_________| ||||
* TINT___________||||
* INT2____________|||
* INT1_____________||
* INTO______________|
LALK
NRM,0
* normal xint routine address.
SACL
VNRM,0
*
LALK
Sl,0
* secondary xint routine address 1.
SACL
VS1,0
*
LALK
S2,0
* secondary xint routine address 2.
SACL
VS2,0
*
LALK
RCV,0
* rint routine address.
SACL
VRCV,0
LALK
IGNRR,0 * set ignore first rint address.
SACL
RVECT,0
LALK
IGNRX,0 * set ignore first xint address.
SACL
RET
XVECT,0
*
*
*
*
*
*
*
* return.
29
0184
0185
0186
0187
0188
0189
0190
0191
0192
0193
0194
0195
0196
0197
0198
0199
0200
0201
0202
0203
0204
0205
0206
0207
0208
0209
0210
0211
0212
0213
0214
0215
0216
0217
0218
0219
0220
0221
0222
0223
0224
0225
0226
0227
0228
0229
0230
0231
0232
0233
0234
0235
0236
0237
0238
30
004A
004B
004C
004D
004E
004F
0050
0051
0052
0053
0054
7872
C800
6071
6870
2074
CE24
4171
4870
5072
CE00
CE26
0055
0056
0057
0058
0059
2000
607A
CAFF
607D
CE26
005A
005B
005C
005D
005E
005F
0060
0061
0062
0063
0064
0065
0066
7872
C800
6071
6870
207C
6001
2075
CE24
4171
4870
5072
CE00
CE26
*
***********************************************************
*
============================
*
*
Receive interrupt routine.
*
*
============================
*
* This routine stores receive data in its storage DRCV *
* (112 page0) and sets the receive flag FRCV (125 page0)*
* As two levels of nesting are used, this routine
*
* allows the user two levels, without stack extension . *
***********************************************************
RINT SST
SSTST
* push STO register.
LDPK 0
* data pointer page 0.
SACL ACCLST,0
* push ACCL.
SACH ACCHST,0
* push ACCH.
LAC
RVECT,0
* load ACC vector address.
CALA
ZALS ACCLST
* pop ACC
ADDH ACCHST
LST
SSTST
* pop ST register.
EINT
* enable interrupts.
RET
* return.
*
RCV
LAC
DRR,0
* load data from DRR.
SACL DRCV,0
* save it to its storage.
LACK >FF
* set receive flag.
SACL FRCV
*
RET
* return.
*
***********************************************************
*
===========================
*
*
xmit interrupt routine.
*
*
===========================
*
* This routine writes xmit data C%the contents of DXMT *
* (123 page0)) to the DXR register according to the type*
* of communication, i.e. normal communication or secondary *
* communication. For normal communication, call the normal *
* communication routine (NRM). For secondary, call the *
* secondary communication routines (Sl and S2). Because *
* these routines use two levels of nesting, the user is *
* allowed two levels of nesting if stack extension is
*
* not used.
*
***********************************************************
XINT SST
SSTST
* push ST register.
LDPK 0
* data pointer page 0.
SACL ACCLST,0
* push ACCL.
SACH ACCHST,0
* push ACCH.
LAC
D2ND,0
* preload dxr with secondary
SACL DXR,0
* communication data.
LAC
XVECT,0
* load vector address.
CALA
* call xmit routine.
ZALS ACCLST
* POP ACC
ADDH ACCHST
LST
SSTST
* pop ST register.
EINT
* enable interrupt.
RET
* return.
0239
0240
0241
0242
0243
0244
0245
0246
0247
0248
0249
0250
0251
0252
0253
0254
0255
0256
0257
0258
0259
0260
0261
0262
0263
0264
0265
0266
0267
0268
0269
0270
0271
0272
0273
0274
0275
0276
0277
0278
0279
0280
0281
0282
0283
0284
0285
0286
0287
0288
0067
0068
0069
006A
006B
207B
6001
CAFF
607E
CE26
006C
006D
006E
006F
0070
207
6001
2079
6075
CE26
0071
0072
0073
0074
0075
0076
0077
0078
0079
007A
CA00
6001
607F
CAFF
607E
2077
6075
2073
6004
CE26
***********************************************************
*
=============================
*
*
Normal data write routine.
*
*
=============================
*
* This routine is called when normal communication occurs.*
* This routine writes xmit data to DXR, and sets the
*
* transmit flag (126 page0).
*
***********************************************************
*
NRM
LAC DXMT,0
* write DXR data.
SACL DXR,0
LACK >FF
* set flag.
SACL FXMT
RET
* return.
***********************************************************
*
==================================
*
Secondary data write routine 1.
*
*
==================================
*
* This routine is called when secondary communication
*
* occurs. It writes secondary data to DXR, and modifies *
* the content of XVECT(117 page0) for continuing secondary *
* communication.
*
***********************************************************
S1
LAC D2ND,0
* write DXR 2nd data.
SACL DXR,0
LAC VS2,0
* modify for next XINT.
SACL XVECT,0
RET
* return.
*
***********************************************************
*
==================================
*
*
Secondary data writing routine 2.
*
*
==================================
*
*
* This routine is called when secondary communication
*
* occurs. It writes dummy data to DXR to ensure that
*
* secondary communication is not inadvertently
*
* initiated on the next XINT. It also modifies the
*
* content of XVECT for normal communication.
*
***********************************************************
S2
ZAC
* clear data for protection.
SACL DXR,0
* of double secondary communication.
SACL F2ND
* clear secondary flag.
LACK >FF
* set xmit end flag.
SACL FXMT,0
LAC VNRM,0
* set normal communication vector.
SACL XVECT,0
LAC INTST,0
* enable all interrupts.
SACL IMR,0
RET
* return.
31
0289
0290
0291
0292
0293
0294
0295
0296
0297
0298
0299
0300
0301
0302
0303
0304
0305
0306
0307
0308
007B
007C
007D
007E
007F
0080
0081
0082
0309 0083
0310
0311 0084
0312 0085
0313 0086
0314 0087
0315 0088
0316 0089
0317 00BA
0318 008B
0319 00BC
0320
0321
0322
0323
0324
0325
0326
0327
0328
0329
0330
0331 008D
0332 008E
008F
0333 0090
0334 0091
0092
0335 0093
0336 0094
32
C800
CA03
606F
207B
4E6F
106F
F680
0084
CE26
*
***********************************************************
*
======================
*
*
Check secondary code. destroy DP pointer. *
*
======================
ACC.
*
*
*
* This routine checks whether the data in DXMT (123 pageo)*
* has secondary code or not. If secondary code exists, *
* then disable maskable interrupts except XINT, modify the*
* contents of XVECT(117 page0) for secondary communi*
* cation, and set secondary flag. Note that we recommend*
* calling this routine to send control words to the AIC.*
***********************************************************
C2ND
LDPK 0
* data page pointer 0.
LACK 03
SACL TMPO
LAC DXMT,0
* is this data secondary code
AND TMPO
SUB TMPO,0
BZ C2ND1
* if yes, then next.
RET
* else return.
*
CAFF C2NDI LACK >FF
* set secondary flag.
607F
SACL F2ND,0
CA20
LACK >20
* enable only XINT.
6004
SACL IMR,0
2078
LAC VSI,0
* modify vector address for secondary
6075
SACL XVECT,0
* communication.
207B
LAC DXMT,0
* write primary data to DXR.
6001
SACL DXR,0
CE26
RET
* return.
*
***********************************************************
*
*
*
======================
*
*
Check first interrupt
*
*
======================
*
*
*
* This routine checks if both first interrupts have
*
* occurred. If this routine is called after reset, it
*
* waits for both interrupts then returns.
*
***********************************************************
206D IGR
LAC FRE,0
* check first interrupt after
F680
BZ IGR
* master reset.
008D
206C
LAC FXE,0
F680
BZ IGR
008D
CE26
RET
0337
*
0338
***********************************************************
0339
*
==========================
*
0340
*
Ignore interrupt routine.
*
0341
*
==========================
*
0342
* These routines are used so that the first RINT and
*
0343
* XINT after the %DSP reset can be ignored. They set
*
0344
* flags and modify each vector address to the normal
*
0345
* interrupt address but do not read or write to the
*
0346
* serial ports. Note that the first data that the AIC will*
0347
* receive after the DSP reset is >0000.
*
0348
***********************************************************
0349 0094 CAFF IGNRR LACK >FF
0350 0095 606D
SACL FRE,0
0351 0096 2076
LAC VRCV,0
* set normal receive address.
0352 0097 6074
SACL RVECT,0
*
0353 0098 CE26
RET
* return.
0354
*
0355 0099 CAFF IGNRX LACK >FF
0356 009A 606C
SACL FXE,0
0357 009B 2077
LAC VNRM,0
* set normal xmit address.
0358 009C 6075
SACL XVECT,0
*
0359 009D CE26
RET
* return.
0360
*
0361
END
NO ERRORS, NO WARNINGS
33
34
C
C.1
TLC32040 and TMS320C17 Flowcharts and
Communication Program
Flowcharts
Begin
Begin
Initialize
Push Status Register
Wait for First EODX Pulse
Push Accumulator
Enable Interrupt
Clear FSX Flag
Write Secondary Communication
Is Transfer
Complete?
No
Modify Interrupt Location. *SINT1
Yes
No
Call Subroutine Referenced
by Vector
Data
Transfer
End?
Pop Accumulator
Yes
More
Secondary
COM?
No
Yes
Pop Status
Return
User Area
b. INTERRUPT SERVICE ROUTINE
a. MAIN
35
NINT1
NINT2
Write Transmit Low Byte
Get Receive Low Byte
Get Receive High Byte
Modify Interrupt Location. *NINT1
Modify Interrupt Location. *NINT2
Clear Transfer End Flag
Clear Transfer End Flag
Return
Return
d. PRIMARY COMMUNICATION 2
c. PRIMARY COMMUNICATION 1
SINT1
Write Transmit Low Byte
Get Receive High Byte
Modify Interrupt Location. *SINT2
SINT2
Write Secondary Data High Byte
Get Receive Low Byte
Modify Interrupt Location. *SINT3
Return
Clear Transfer End Flag
f. PRIMARY-SECONDARY COMMUNICATION 2
Return
e. PRIMARY-SECONDARY COMMUNICATION 1
36
SINT3
SINT4
Write Secondary Data Low Byte
Modify Interrupt Location. *NINT1
Modify Interrupt Location. *SINT4
Clear Transmit Low Byte Storage Location
Clear Transfer End Flag
Clear Transfer End Flag
Return
Return
g. PRIMARY-SECONDARY COMMUNICATION 3
h. PRIMARY-SECONDARY COMMUNICATION 4
DLB
Data
Transfer
Complete?
No
Yes
Move Receive High-Byte to
Transmit High-Byte
Move Receive Low-Byte to
Transmit Low-Byte
Write Transmit High-Byte to
Transmit Register Buffer
i. DIGITAL LOOPBACK
37
C.2
Communication Program List
0001
0002
0003
0004
0005
0006
0007
0008
0009
0010
0011
0012
0013
0014
0015
0016
0017
0018
0019
0020
0021
0022
0023
0024
0025
0026
0027
0028
0029
0030
0031
0032
0033
0034
0035
0036
0037
0038
0039
0040
0041
0042
0043
0044
0045
0046
0047
0048
0049
0050
0051
0052
0053
0054
38
0000
0001
0002
0003
0004
0005
0006
0007
0008
0009
D00A
000B
000C
000D
000E
000F
***********************************************************
*
*
*=========================================================*
*
TLC32040 to TMS32OC17 Communication Program
*
*
version 1.2
*
*
revised 7/22/88
*
*
*
*
by Hironori Okubo and Woody Rowand
*
*
Texas Instruments
*
*
(214) 997–3460
*
*=========================================================*
*
*
* This program uses the circuit published in the Volume *
* 3 of the Linear and Interface Circuit Applications
*
* book with the following modification:
*
*
*
*
1. INT– of the TMS32OC17 must be connected to
*
*
EODX– of the TLC32040.
*
*
*
*
*
* In this configuration, the program will allow the
*
* TLC32040 to communicate with the TLC32OC17 with the
*
* restriction that all interrupts except INT– are
*
* prohibited and only synchronous communication can
*
* occur. The program allows the user two levels of
*
* nesting in the main program; the remaining two levels *
* are reserved for the interrupt vector and subroutines.*
*
*
* If desired, this program may be used with the TMS32011*
* digital signal processor with the following change.
*
* Since the TMS32011 has only sixteen words of data RAM *
* on data page 1, all of the registers used by this
*
* program should be moved to data page 0, except for
*
* SSTSTK (the temporary storage location for the status *
* register) which must remain on page %I (since the
*
* SST instruction always addresses page 1).
*
*
*
***********************************************************
SSTSTK EQU >00
stack for status (SST) register.
ACHSTK EQU >01
stack for accumulator high (ACCH).
ACLSTK EQU >02
stack for accumulator low (ACCL).
RXEFLG EQU >03
xmit/receive in progress.
DRCV1
EQU >04
storage for high byte receive data.
DRCV2
EQU >05
storage for low byte receive data.
DXMT1
EQU >06
storage for high byte xmit data.
DXMT2
EQU >07
storage for low byte xmit data.
DXMT3
EQU >08
storage for high byte secndry data.
DXMT4
EQU >09
storage for low byte secndry data.
VECT
EQU >OA
storage for interrupt vector addr.
ANINT1 EQU >OB
storage for normal xmit/rcv vect 1.
ANINT2 EQU >OC
storage for normal xmit/rcv vect 2.
ASINTI EQU >OD
storage for secndry xmit/rcv vect 1.
ASINT2 EQU >OE
storage for secndry xmit/rcv vect 2.
ASINT3 EQU >OF
storage for secndry xmit/rcv vect 3.
0055 0000
0056
0010
0057
0011
0058
0012
0059
0013
0060
0014
0061
0015
0062
00FF
0063
0064
0065
0066 0000
0067 0000 F900
0001 0013
0068
00020069
0070
0071
0072
0073
0074
0075
0076
0077
0078
0079
0080
0081
0082
0083
0084
0085
0086
0087
0088
0089
0090
0091
0092
0093
0094
0095
0096
0097
0098
0002
0002
0003
0004
0005
0006
0007
0008
0009
000A
000B
0099 000C
0100
0101 000C
0102 000D
0103
0104
0105
0106
0107
000E
000F
0010
0011
0012
6EOI
7C00
5801
5002
4813
4011
2011
7912
FF00
0007
ASINT4 EQU
>10
storage for secndry xmit/rcv vect 4.
CNTREG EQU
>11
storage for control register.
MXINT
EQU
>12
storage for xmit interrupt mask.
CLRX
EQU
>13
storage for xmit interrupt clear
CLRX1
EQU
>14
storage for xmit intrpt clear/mask.
TEMP
EQU
>15
temporary register.
FLAG
EQU
>FF
flag set.
*
=========================
*
Branch to initialization routine.
*
=========================
AORG
>0000
B
INIT branch to initialization routine.
*********************************************************************
* ========================
*
*
Interrupt service routine.
*
* ========================
*
*
*
*
To initiate secondary communication, change the
*
*
contents of VECT to the address of the secondary *
*
communication subroutine and store the
*
*
in DXMT3 and DXMT4.
*
*
*
*
*
* e.g.
*
*
LAC ASINTI
modify VECT.
*
*
SACL
VECT
*
*
|
*
*
LAC Hl
store high-byte of
*
*
SACL
DXMT3
secondary information in
*
*
LAC H2
DXMT4 store low-byte in DXMT4.
*
*
SACL
DXMT4
*
*
*
*********************************************************
AORG >02
INTSVC LDPK 1
SST
SSTSTK
push status register.
SACH ACHSTK
push accumulator high.
SACL ACLSTK
push accumulator low.
OUT
CLRXPAO
make sure FSX–flag is clear.
WAIT1
IN
CNTREG,PAO read control register.
LAC
CNTREG,0
load accumulator with control
AND
MXINT
reg mask-off xmit interrupt
BZ
WAIT1
flag loop until xmit interrupt
flag is recognized.
*
200A
7F8C
LAC
CALA
VECT
6501
7A02
7B00
7F82
7F8D
ZALH
OR
LST
EINT
RET
ACHSTK
ACLSTK
SSTSTK
load acc with interrupt vector.
call appropriate xmit/rcv
routines
pop accumulator high.
pop accumulator low.
pop status register.
enable interrupts.
return to main program.
39
0108
0109
0110
0111
0112
0113
0114
0115
0116
0117
0118
0119
0120
0121
0122
0123
0124
0125
0126
0127
0128
0129
0130
0131
0132
0133
0134
0135
0136
0137
0138
0139
0140
0141
0142
0143
0144
0145
0146
0147
0148
0149
0150
0151
0152
0153
0154
0155
0156
0157
0158
0159
0160
0161
0162
0163
0164
40
0013
0013
0014
0015
0016
0017
0018
0019
001A
001B
001C
001D
001E
001F
0020
0021
0022
0023
0024
0025
0026
0027
0028
0029
002A
002B
00IC
002D
002E
002F
0030
0031
0032
0033
0034
0035
0036
0037
0038
0039
003A
003B
003C
003D
003E
003F
7F81
6EOl
7F89
6880
7083
5OA8
5OA8
5OA8
5OA8
5OA8
5OA8
5OA8
5088
4906
4906
7EO4
5012
7EOl
5015
6Al5
80A1
7F8E
6713
8OA2
7F8E
6714
809D
7F8E
500A
8077
7F8E
500B
807D
7F8E
500C
8084
7F8E
500D
808A
7F8E
500E
8090
7FBE
600F
A095
***********************************************************
*
==============================
*
*
Initialization after reset.
*
*
==============================
*
*
*
*
Data RAM locations >80 through >92 are reserved
*
*
by this program. The user must set the status
*
*
register at the end of this program with the SST
*
*
command or a combination of SOVM, LDPK etc.
*
*
*
***********************************************************
INIT DINT
disable interrupts.
LDPK
1
set data page pointer one.
ZAC
clear registers.
LARP
0
LARK
0,RXEFLG+>80
SACL
*+
SACL
*+
SACL
*+
SACL
*+
SACL
*+
SACL
*+
SACL
*+
SACL
*
OUT
DXMT1,PAl
clear transmit registers.
OUT
DXMT1,PAI
LACK
?00000100
SACL
MXINT
initialize xmit–int mask.prepare
LACK
1
for serial port initialization
SACL
TEMP
and initialization of registers
LT
TEMP
containing 16-bit constants.
MPYK
CLX1
initialize interrupt flag clear.
PAC
TBLR
CLRX
MPYK
CLX2
initialize interrupt flag clear
PAC
with interrupts disabled.
TBLR
CLRX1
MPYK
IGN
PAC
SACL
VECT
initialize interrupt vector.
MPYK
NINT1
save normal communication
PAC
address to its storage.
SACL
ANINT1
MPYK
NINT2
save normal communication
PAC
address 2 to its storage.
SACL
ANINT2
MPYK
SINTI
save secondary communication
PAC
address 1 to its storage.
SACL
ASINT1
MPYK
SINT2
save secondary communication
PAC
address 2 to its storage.
SACL
ASINT2
MPYK
SINT3
save secondary communication
PAC
address 3 to its storage.
SACL
ASINT3
MPYK
SINT4
save secondary communication
0165
0166
0167
0168
0169
0170
0171
0172
0173
0174
0175
0176
0177
0178
0179
0180
0181
0182
0183
0184
0040 CE14
0041 6010
0042
PAC
SACL
address 4 to its storage.
ASINT4
***********************************************************
* ==========================================
*
*
Synchronize high/low byte transmission.
*
* ==========================================
*
*
*
* The time between FSX– interrupts is approximately
*
* ten microseconds (50 cycles). Wait for first if
*
* FSX–, this is the first interrupt, delay 60 cycles
*
* (past the second interrupt). If it is the second
*
* interrupt, no harm done.
*
*
*
***********************************************************
OUT
CLRX1,PAO clear interrupt flags, disable int.
IGNOR
IN
CNTREG,PAO read control register.
LAC
CNTREG
wait
AND
MXINT
for
BZ
IGNOR
FSX– flag.
0042
0043
0044
0045
0046
0047
0185 0048
0186 0048
0187 0049
E014
8011
2011
4E12
F680
0043
C014
5500 IGNOR1
LARK
NOP
0,20
0188 004A
004B
0189 004C
0190 004C
0191 004D
0192 004D
0193
0194
0195
0196
0197
0198
0199
0200
0201
0202
0203
0204
0205
0206
0207
0208
0209
0210
0211
0212
0213 004E
0214 004F
0215 0050
0216 0051
0217 0052
FB90
0049
BANZ
IGNOR1
E013
OUT CLRX,PAO
CEDO
CA00
6006
CA03
5007
7E24
wait 60 cycles (20 × 3 cycles) in
case FSX– int. is first of the
pair.
if FSXI– int was the second, delay
anyway.
EINT
enable interrupt.
***********************************************************
*
==============================
*
*
Main program (user area)
*
*
==============================
*
*
*
* This program allows the user two levels of nesting,
*
* since one level is used as stack for the interrupt and *
* the interrupt service routine makes one subroutine
*
* call. User routines such as digital filtering, FFTS,
*
* and secondary communication judgement may be placed
*
* here. The number of instruction cycles between
*
* interrupts varies with the sampling rate. In the
*
* power-up condition this is approximately 500 cycles.
*
*
*
* In the example below, the first two transmissions send *
* secondary information to the AIC. The first configures *
* the TB and RB registers. The second configures the
*
* control register.
*
*
*
***********************************************************
MAIN
ZAC
prepare first control word.
SACL DXMTI
LACK >03
SACL
DXMT2
should be xxxx xx11.
LACK
>24
41
0218
0219
0220
0221
0222
0223
0224
0225
0226
0227
0228
0229
0230
0231
0232
0233
0234
0235
0236
0237
0238
0239
0240
0241
0242
0243
0244
0245
0246
0247
0248
0249
0250
0251
0252
0253
0254
0255
0256
0257
0258
0259
0260
0261
0262
0263
0264
0076
0265
42
0053
0054
0055
0056
0057
0057
0058
0059
005A
005B
005C
005D
005E
005E
005F
0060
0061
0062
0063
0064
0065
0066
0067
0068
0069
006A
006B
006C
006D
006E
006E
006F
0070
0071
0072
0073
0074
0075
006B
0077
5008
7E92
5009
200D
SACL
LACK
SACL
LAC
DXMT3
>92
DXMT4
ASINT1
500A
4906
*
7F89
5003
2003
FF00
005B
SACL
OUT
VECT
communications.
DXMTI,PAI
store first transmit byte in
transmit buffer.
set VECT for secondary
ZAC
SACL RXEFLG
clear xmit/rcv end flag.
MAIN1 LAC
RXEFLG
BZ
MAINI
wait for data transfer to
complete.
7F89
ZAC
prepare second control word.
5006
SACL DXMT1
7EO3
LACK >03
5007
SACL DXMT2
7E00
LACK >00
5008
SACL DXMT3
7E67
LACK >67
5009
SACL DXMT4
200D
LAC
ASINTI
500A
SACL VECT
4906
OUT
DXMTI,PAL
7F89
ZAC
5003
SACL RXEFLG
clear xmit/rcv end flag.
**********************************************************
* ========================= *
*
Digital loop–back program *
* ========================= *
*
*
* This program serves as an example of what can
*
* be done in the user area. *
*
*
***********************************************************
2003 DLB
LAC
RXEFLG
wait for data transfer to complete.
FF00
BZ
DLB
006B
2004
5006
2005
5007
4906
*
7F89
5003
F900
LAC
SACL
LAC
SACL
OUT
ZAC
SACL
B
DRCV1
move receive data to transmit
DXMT1
registers.
DRCV2
DXMT2
DXMTI,PAL
write first transmit byte to
transmit buffer.
RXEFLG
DLB
clear rcv/xmit-end flag.
0266
0267
0268
0269
0270
0271
0272
0273
0274
0275
0276
0277
0278
0279
0280
0281
0282
0283
0284
0285
0286
***********************************************************
===================================
*
*
Normal interrupt routines.
*
*
===================================
*
*
*
*
These routines destroy the contents of the
*
*
accumulator and the data page pointer, making it *
*
necessary to save these before the routines begin *
*
*
*
Write the contents of DXMT2 to the transmit buffer *
*
and read the receive buffer into DRCV1.
*
*
*
***********************************************************
0077
0077
0078
0079
007A
007B
007C
007D
4907
4104
200C
500A
4813
7F8D
4105
NINT1 OUT
DXMT2,PAI
IN
DRCVI,PAI
LAC
ANINT2
SACL VECT
OUT CLRX,PAO
RET
NINT2 IN
DRCV2,PAI
0287
0288
0289
0290
0291
0292
0293
0294
0295
0296
0297
0298
0299
0300
0301
0302
0303
0304
0305
0306
007E
007F
0080
0081
0082
0083
200B
500A
4813
7EFF
5003
7F8D
0307
0308
0309
0310
0311
0086
0087
0088
0089
008A
200E
500A
4813
7F8D
4908
0312
0313
0314
0315
0316
0317
0318
008B
008C
008D
008E
008F
0090
0091
4105
200F
500A
4813
7F8D
4909
2010
LAC ANINTI
SACL VECT
OUT CLRX, PAO
clear xmit interrupt flag.
LACK FLAG
SACL RXEFLG
set xmi%t/rcv end flag.
RET
***********************************************************
*
===================================
*
*
Secondary interrupt routines
*
*
===================================
*
*
These routines destroy the contents of the
*
*
accumulator and the data page pointer.
*
*
*
The following routines write the low byte of
*
*
the primary data word and the high and low byte *
*
of the secondary data word. They also read the *
*
A/D information in the receive registers.
*
***********************************************************
SINT1 OUT
DXMT2,PAl
write xmit-data-low to xmit reg.
IN
DRCVI,PA1
read receive-data-high from rcv
reg
LAC
ASINT2
prepare next interrupt vector.
SACL
VECT
OUT
CLRX,PAO
clear xmit interrupt flag.
RET
SINT2 OUT
DXMT3,PAI
write secondary-data-high to
xmit.
IN
DRCV2,PAl
read receive-data-low from rcv.
LAC
ASINT3
prepare next interrupt vector.
SACL
VECT
OUT
CLRX,PAO
clear xmit interrupt flag.
RET
SINT3 OUT
DXMT4,PAI
write secondary-data-low to xmit
LAC
ASINT4
prepare next interrupt vector.
0084 4907
0085 4104
write xmit-low to xmit register.
read rcv-data-high from rcv reg.
prepare next interrupt vector.
clear xmit interrupt flag.
read receive-data-low from rcv
reg.
prepare next interrupt vector.
43
0319 0092 500A SACL VECT
0320 0093 4813
OUT
CLRX,PAO
clear xmit interrupt flag.
0321 0094 7F8D
RET
0322 0095 200B SINT4 LAC
ANINT1
prepare next interrupt vector.
0323 0096 500A
SACL
VECT
0324 0097 4813
OUT
CLRX,PAO
clear xmit interrupt flag.
0325 0098 7F89
ZAC
0326 0099 5007
SACL
DXMT2
clear DXMT2 immediately to
eliminate
0327 009A 7EFF
LACK
FLAG
unnexpected secondary
communications
0328 009B 5003
SACL
RXEFLG
set xmit / rcv end flag.
0329 009C 7FBD
RET
0330
***********************************************************
0331
* ===================================
*
0332
* Ignore first interrupt.
*
0333
* ===================================
*
0334
*
This routine is used to ignore the first data
*
0335
*
transmission and also to synchronize the AIC
*
0336
*
with the processor.
0337
***********************************************************
0338 009D 200B IGN LAC
ANINT1
0339 009E 500A
SACL
VECT
0340 009F 4813
OUT
CLRX,0
0341 00AO 7F8D
RET
0342
***********************************************************
0343
*
*
0344
*
CONTROL REGISTER INFORMATION
*
0345
*
*
0346
*
SERIAL–PORT CONFIG. INT. MASK INT. FLAG
*
0347
*
| 1 0 0 0 1 1 1 0 | | 0 0 0 1 0 1 0 0 |
*
0348
*
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
*
0349
*
|
| | | |___INT
*
0350
*
| _XF status
| | |_____ FSR
*
0351
*
|___________ FSX
*
0352
*
|___________ FR
*
0353
*
*
0354
*
(write l’s to clear)
*
0355
***********************************************************
0356 00Al 8ElF CLXI DATA
>8EIF
0357 00A2 8EOF CLX2 DATA
>8EOF
0358
END
NO ERRORS, NO WARNINGS
44
0317 009D 200B IGN LAC
ANINT1
0318 009E 500A
SACL
VECT
0319 009F 4813
OUT
CLRX,0
0320 00AO 7F8D
RET
0321
***********************************************************
0322
*
*
0323
*
CONTROL REGISTER INFORMATION
*
0324
*
*
0325
*
SERIAL–PORT CONFIG. INT. MASK INT. FLAG
*
0326
*
| 1 0 0 0 1 1 1 0 | | 0 0 0 1 0 1 0 0 |
*
0327
*
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
*
0328
*
|
| | | |___INT
*
0329
*
| _XF status
| | |_____ FSR
*
0330
*
|___________ FSX
*
0331
*
|___________ FR
*
0332
*
*
0333
*
(write l’s to clear)
*
0334
***********************************************************
0335 00Al 8ElF CLXI DATA
>8EIF
0336 00A2 8EOF CLX2 DATA
>8EOF
0337
END
NO ERRORS, NO WARNINGS
45
46
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