Texas Instruments | AM437x and AMIC120 ARM® Cortex™-A9 Processors (Rev. I) | User Guides | Texas Instruments AM437x and AMIC120 ARM® Cortex™-A9 Processors (Rev. I) User guides

Texas Instruments AM437x and AMIC120 ARM® Cortex™-A9 Processors (Rev. I) User guides
AM437x and AMIC120 ARM® Cortex™-A9
Processors
Technical Reference Manual
Literature Number: SPRUHL7I
April 2014 – Revised December 2019
Contents
Preface ..................................................................................................................................... 136
Revision History ........................................................................................................................ 137
1
Introduction ..................................................................................................................... 139
1.1
2
Memory Map .................................................................................................................... 140
2.1
3
3.2
3.3
6
2
141
141
143
144
150
....................................................................................................... 152
Introduction ................................................................................................................
3.1.1 Features ...........................................................................................................
Integration..................................................................................................................
3.2.1 Clocking, Reset and Power Management ...................................................................
Functional Description....................................................................................................
3.3.1 Cortex-A9 MPCore ..............................................................................................
153
154
156
156
161
161
Interconnects ................................................................................................................... 167
4.1
5
ARM Cortex-A9 Memory Map ...........................................................................................
2.1.1 L3 Memory Map ..................................................................................................
2.1.2 L4_WKUP Memory Map ........................................................................................
2.1.3 L4_PER Peripheral Memory Map..............................................................................
2.1.4 L4 Fast Peripheral Memory Map...............................................................................
ARM MPU Subsystem
3.1
4
AM437x Family ............................................................................................................ 139
1.1.1 Device Features.................................................................................................. 139
1.1.2 Device Identification ............................................................................................. 139
Introduction ................................................................................................................
4.1.1 Terminology ......................................................................................................
4.1.2 L3 Interconnect ...................................................................................................
4.1.3 L4 Interconnect ...................................................................................................
168
168
168
173
..................................................................................................................... 174
5.1
Introduction ................................................................................................................ 175
5.2
Functional Description.................................................................................................... 175
5.2.1 Architecture ....................................................................................................... 175
5.2.2 Functionality ...................................................................................................... 176
5.2.3 Memory Map ..................................................................................................... 177
5.2.4 Start-up and Configuration...................................................................................... 182
5.2.5 Booting ............................................................................................................ 184
5.2.6 Memory Booting.................................................................................................. 196
5.2.7 Peripheral Booting ............................................................................................... 231
5.2.8 Low Latency NOR Booting ..................................................................................... 238
5.2.9 Image Format .................................................................................................... 240
5.2.10 Table of Contents ............................................................................................... 241
5.2.11 Services for HLOS Support – API ........................................................................... 242
5.2.12 Tracing ........................................................................................................... 245
Power, Reset, and Clock Management (PRCM) ..................................................................... 249
6.1
Introduction ............................................................................................................... 250
6.2
Device Power-Management Architecture Building Blocks .......................................................... 250
6.3
Clock Management ...................................................................................................... 250
6.3.1 Module Interface and Functional Clocks ..................................................................... 250
Initialization
Contents
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6.4
6.5
6.6
6.7
6.8
6.9
6.10
6.11
6.12
6.3.2 Module-Level Clock Management ............................................................................
6.3.3 Clock Domain ....................................................................................................
Power Management .....................................................................................................
6.4.1 Power Domain ...................................................................................................
6.4.2 Power Domain Management ..................................................................................
6.4.3 Power Modes .....................................................................................................
6.4.4 Main Oscillator Control During DeepSleep ...................................................................
6.4.5 Wakeup Sources/Events ........................................................................................
6.4.6 Functional Sequencing for Power Management with Wakeup Processor................................
6.4.7 I/O Power Management and Daisy Chaining ................................................................
PRCM Module Overview ................................................................................................
6.5.1 Interface Descriptions ...........................................................................................
Clock Generation and Management....................................................................................
6.6.1 Terminology ......................................................................................................
6.6.2 Clock Structure ...................................................................................................
6.6.3 ADPLLS ...........................................................................................................
6.6.4 ADPLLLJ (Low Jitter DPLL) ...................................................................................
6.6.5 M2 and N2 Change On-the-Fly ...............................................................................
6.6.6 Spread Spectrum Clocking (SSC) .............................................................................
6.6.7 Core PLL Description............................................................................................
6.6.8 Peripheral PLL Description .....................................................................................
6.6.9 MPU PLL Description ...........................................................................................
6.6.10 Display PLL Description .......................................................................................
6.6.11 DDR PLL Description ..........................................................................................
6.6.12 EXTDEV PLL Description .....................................................................................
6.6.13 PLL Bypass Modes .............................................................................................
6.6.14 CLKOUT Signals ................................................................................................
6.6.15 32-kHz Clock Structure ........................................................................................
6.6.16 ADC0, ADC1, DCAN, and McASP Clocking ................................................................
Reset Management .......................................................................................................
6.7.1 Overview .........................................................................................................
6.7.2 Reset Concepts and Definitions ..............................................................................
6.7.3 Global Power On Reset (Cold Reset) .........................................................................
6.7.4 Global Warm Reset ..............................................................................................
6.7.5 Reset Characteristics............................................................................................
6.7.6 EMAC Switch Reset Isolation ..................................................................................
6.7.7 Reset Priority .....................................................................................................
6.7.8 Trace Functionality Across Reset..............................................................................
6.7.9 RTC PORz ........................................................................................................
Power-Up/Down Sequence ..............................................................................................
IO State ....................................................................................................................
Voltage and Power Domains ............................................................................................
6.10.1 Voltage Domains ................................................................................................
6.10.2 Power Domains .................................................................................................
Device Modules and Power Management Attributes List ...........................................................
6.11.1 Power Domain Power Down Sequence .....................................................................
6.11.2 Power Domain Power-Up Sequence .........................................................................
Power Management Registers ..........................................................................................
6.12.1 PRCM_PRM_CEFUSE Registers ............................................................................
6.12.2 PRCM_PRM_DEVICE Registers .............................................................................
6.12.3 PRCM_PRM_GFX Registers..................................................................................
6.12.4 PRM_MPU Registers...........................................................................................
6.12.5 PRCM_PRM_PER Registers..................................................................................
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Contents
251
254
256
256
257
259
263
264
264
267
268
269
270
270
270
272
273
275
275
280
282
284
285
286
287
288
288
290
292
293
293
293
294
296
299
301
301
301
301
301
302
302
302
302
303
306
306
307
307
310
326
331
337
3
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6.13
7
7.3
9.2
9.3
9.4
ARM Cortex-A9 Interrupts .............................................................................................. 1112
PWM Events ............................................................................................................. 1116
GPMC .....................................................................................................................
9.1.1 Introduction ......................................................................................................
9.1.2 Integration .......................................................................................................
9.1.3 Functional Description .........................................................................................
9.1.4 GPMC High-Level Programming Model Overview .........................................................
9.1.5 Use Cases.......................................................................................................
9.1.6 GPMC Registers ...............................................................................................
OCMC-RAM ..............................................................................................................
9.2.1 Introduction ......................................................................................................
9.2.2 Integration .......................................................................................................
EMIF ......................................................................................................................
9.3.1 Introduction ......................................................................................................
9.3.2 Integration .......................................................................................................
9.3.3 EMIF Functional Description ..................................................................................
9.3.4 EMIF Registers .................................................................................................
ELM .......................................................................................................................
9.4.1 Introduction ......................................................................................................
9.4.2 Integration .......................................................................................................
9.4.3 Functional Description .........................................................................................
9.4.4 Basic Programming Model ....................................................................................
9.4.5 ELM Registers ..................................................................................................
1119
1119
1122
1124
1203
1214
1225
1337
1337
1338
1339
1339
1340
1342
1362
1537
1537
1538
1539
1542
1547
Enhanced Direct Memory Access (EDMA) .......................................................................... 1583
10.1
10.2
4
638
638
638
640
641
648
649
649
Memory Subsystem ......................................................................................................... 1118
9.1
10
Introduction ................................................................................................................
Functional Description....................................................................................................
7.2.1 Pad Control Registers ...........................................................................................
7.2.2 EDMA Event Multiplexing .......................................................................................
7.2.3 Device Control and Status ......................................................................................
7.2.4 DDR IO Control Settings ........................................................................................
Registers ...................................................................................................................
7.3.1 CONTROL_MODULE Registers ...............................................................................
Interrupts ....................................................................................................................... 1111
8.1
8.2
9
414
415
429
439
439
442
447
469
471
474
558
560
Control Module ................................................................................................................. 637
7.1
7.2
8
6.12.6 PRCM_PRM_RTC Registers..................................................................................
6.12.7 PRM_WKUP Registers ........................................................................................
6.12.8 PRCM_PRM_IRQ Registers ..................................................................................
Clock Module Registers ..................................................................................................
6.13.1 PRCM_CM_CEFUSE Registers ..............................................................................
6.13.2 PRCM_CM_DEVICE Registers ...............................................................................
6.13.3 CM_DPLL Registers............................................................................................
6.13.4 PRCM_CM_GFX Registers ...................................................................................
6.13.5 PRCM_CM_MPU Registers ...................................................................................
6.13.6 CM_PER Registers .............................................................................................
6.13.7 PRCM_CM_RTC Registers ...................................................................................
6.13.8 CM_WKUP Registers ..........................................................................................
Introduction ...............................................................................................................
10.1.1 EDMA3 Controller Block Diagram ..........................................................................
10.1.2 Third-Party Channel Controller (TPCC) Overview ........................................................
10.1.3 Third-Party Transfer Controller (TPTC) Overview ........................................................
Integration ................................................................................................................
Contents
1584
1584
1585
1586
1587
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10.3
10.4
10.5
11
1587
1588
1590
1590
1593
1595
1607
1610
1611
1613
1616
1617
1623
1627
1629
1632
1632
1633
1633
1633
1633
1635
1651
1654
1654
1737
1790
1790
1791
1793
ADC0: Touchscreen Controller ......................................................................................... 1795
11.1
11.2
11.3
11.4
11.5
12
10.2.1 Third-Party Channel Controller (TPCC) Integration ......................................................
10.2.2 Third-Party Transfer Controller (TPTC) Integration .......................................................
Functional Description ..................................................................................................
10.3.1 Functional Overview ..........................................................................................
10.3.2 Types of EDMA3 Transfers ..................................................................................
10.3.3 Parameter RAM (PaRAM) ...................................................................................
10.3.4 Initiating a DMA Transfer .....................................................................................
10.3.5 Completion of a DMA Transfer ..............................................................................
10.3.6 Event, Channel, and PaRAM Mapping .....................................................................
10.3.7 EDMA3 Channel Controller Regions .......................................................................
10.3.8 Chaining EDMA3 Channels ..................................................................................
10.3.9 EDMA3 Interrupts .............................................................................................
10.3.10 Memory Protection ..........................................................................................
10.3.11 Event Queues ................................................................................................
10.3.12 EDMA3 Transfer Controller (EDMA3TC) .................................................................
10.3.13 Event Dataflow ...............................................................................................
10.3.14 EDMA3 Prioritization ........................................................................................
10.3.15 EDMA3 Operating Frequency (Clock Control) ...........................................................
10.3.16 Reset Considerations .......................................................................................
10.3.17 Power Management .........................................................................................
10.3.18 Emulation Considerations ..................................................................................
10.3.19 EDMA Transfer Examples ..................................................................................
10.3.20 EDMA Events ................................................................................................
Registers .................................................................................................................
10.4.1 EDMA3CC Registers .........................................................................................
10.4.2 EDMA3TC Registers ..........................................................................................
Appendix A ...............................................................................................................
10.5.1 Debug Checklist ...............................................................................................
10.5.2 Miscellaneous Programming/Debug Tips ..................................................................
10.5.3 Setting Up a Transfer .........................................................................................
Introduction ...............................................................................................................
11.1.1 TSC_ADC (ADC0) Features .................................................................................
11.1.2 Unsupported TSC_ADC_SS (ADC0) Features ...........................................................
Integration ................................................................................................................
11.2.1 TSC_ADC (ADC0) Connectivity Attributes .................................................................
11.2.2 TSC_ADC (ADC0) Clock and Reset Management .......................................................
11.2.3 TSC_ADC (ADC0) Pin List...................................................................................
Functional Description ..................................................................................................
11.3.1 Hardware Synchronized or Software Enabled ............................................................
11.3.2 Open Delay and Sample Delay .............................................................................
11.3.3 Averaging of Samples (1, 2, 4, 8, and 16) .................................................................
11.3.4 One-Shot (Single) or Continuous Mode ...................................................................
11.3.5 Interrupts .......................................................................................................
11.3.6 DMA Requests ................................................................................................
11.3.7 Analog Front End (AFE) Functional Block Diagram .....................................................
Operational Modes ......................................................................................................
11.4.1 PenCtrl and PenIRQ ..........................................................................................
ADC0 Registers .........................................................................................................
11.5.1 ADC0 Registers ...............................................................................................
1796
1796
1796
1797
1797
1798
1798
1799
1799
1799
1799
1799
1799
1800
1800
1802
1803
1806
1806
ADC1: Magnetic Card Reader ........................................................................................... 1841
12.1
Introduction ............................................................................................................... 1842
12.1.1 MagneticCard Reader Features ............................................................................. 1842
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12.2
12.3
12.4
13
14
6
12.1.2 Unsupported Features ........................................................................................
Integration ................................................................................................................
12.2.1 MagneticCard Reader Connectivity Attributes.............................................................
12.2.2 MagneticCard Reader Clock and Reset Management ...................................................
12.2.3 MagneticCard Reader Pin List...............................................................................
Functional Description ..................................................................................................
12.3.1 FSM Sequencer Functional Description....................................................................
12.3.2 AFE Functional Description ..................................................................................
12.3.3 FIFOs and DMA ...............................................................................................
12.3.4 Power Management ..........................................................................................
12.3.5 Magnetic Card Operation (Use Cases).....................................................................
12.3.6 Simultaneous Control of ADC0 ..............................................................................
Registers .................................................................................................................
12.4.1 ADC1 Registers ...............................................................................................
1843
1844
1844
1845
1845
1846
1846
1851
1855
1855
1856
1857
1858
1858
................................................................................................ 1932
13.1 Introduction ............................................................................................................... 1933
13.1.1 DSS Features .................................................................................................. 1933
13.1.2 Unsupported Features ........................................................................................ 1934
13.2 Integration ................................................................................................................ 1935
13.2.1 DSS Connectivity Attributes ................................................................................. 1935
13.2.2 DSS Clock and Reset Management ........................................................................ 1935
13.2.3 DSS Pin List ................................................................................................... 1936
13.3 Functional Description .................................................................................................. 1937
13.3.1 Block Diagram ................................................................................................. 1937
13.3.2 Display Subsystem Environment ............................................................................ 1938
13.3.3 Display Controller Functionalities ........................................................................... 1957
13.3.4 RFBI Functionalities .......................................................................................... 1980
13.3.5 Hardware Requests ........................................................................................... 1984
13.4 Programming Model .................................................................................................... 1986
13.4.1 Display Subsystem Reset .................................................................................... 1986
13.4.2 Display Subsystem Configuration Phase .................................................................. 1986
13.4.3 Display Controller Basic Programming Model ............................................................. 1986
13.4.4 RFBI Basic Programming Model ............................................................................ 2008
13.5 Use Cases................................................................................................................ 2017
13.5.1 How to Configure the Scaling Unit in the DISPC Module ................................................ 2017
13.5.2 Display Low-Power Refresh Settings ....................................................................... 2029
13.6 Registers ................................................................................................................. 2033
13.6.1 DSS_DISPC Registers ....................................................................................... 2033
13.6.2 DSS_TOP Registers .......................................................................................... 2123
13.6.3 DSS_RFBI Registers ......................................................................................... 2130
Camera (VPFE) ............................................................................................................... 2152
14.1 Introduction ............................................................................................................... 2153
14.1.1 VPFE Features ................................................................................................ 2153
14.1.2 Unsupported Features ........................................................................................ 2153
14.2 Integration ................................................................................................................ 2154
14.2.1 VPFE Connectivity Attributes ................................................................................ 2154
14.2.2 VPFE Clock and Reset Management ...................................................................... 2155
14.2.3 VPFE Pin List .................................................................................................. 2155
14.3 Functional Description .................................................................................................. 2156
14.3.1 External IO Interface .......................................................................................... 2156
14.3.2 VPFE Data / Image Processing ............................................................................. 2162
14.4 Programming Model .................................................................................................... 2177
14.4.1 Enabling and Disabling the VPFE Controller .............................................................. 2177
Display Subsystem (DSS)
Contents
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14.5
15
2177
2180
2180
2180
Ethernet Subsystem ........................................................................................................ 2216
15.1
15.2
15.3
15.4
15.5
16
14.4.2 Configuring VPFE Registers .................................................................................
14.4.3 VPFE Limitations ..............................................................................................
Registers .................................................................................................................
14.5.1 VPFE Registers ...............................................................................................
Introduction ...............................................................................................................
15.1.1 Features ........................................................................................................
15.1.2 Unsupported Features ........................................................................................
Integration ................................................................................................................
15.2.1 Ethernet Switch Connectivity Attributes ....................................................................
15.2.2 Ethernet Switch Clock and Reset Management ..........................................................
15.2.3 Ethernet Switch Pin List ......................................................................................
15.2.4 Ethernet Switch RMII Clocking Details .....................................................................
15.2.5 GMII Interface Signal Connections and Descriptions ....................................................
15.2.6 RMII Signal Connections and Descriptions ................................................................
15.2.7 RGMII Signal Connections and Descriptions ..............................................................
Functional Description ..................................................................................................
15.3.1 CPSW_3G Subsystem .......................................................................................
15.3.2 CPSW_3G......................................................................................................
15.3.3 Ethernet Mac Sliver (CPGMAC_SL) .......................................................................
15.3.4 Command IDLE ...............................................................................................
15.3.5 RMII Interface ..................................................................................................
15.3.6 RGMII Interface ................................................................................................
15.3.7 Common Platform Time Sync (CPTS) .....................................................................
15.3.8 MDIO ............................................................................................................
Software Operation .....................................................................................................
15.4.1 Transmit Operation............................................................................................
15.4.2 Receive Operation ............................................................................................
15.4.3 Initializing the MDIO Module .................................................................................
15.4.4 Writing Data to a PHY Register .............................................................................
15.4.5 Reading Data from a PHY Register ........................................................................
15.4.6 Initialization and Configuration of CPSW ..................................................................
Ethernet Subsystem Registers ........................................................................................
15.5.1 CPSW_ALE Registers ........................................................................................
15.5.2 CPSW_CPDMA Registers ...................................................................................
15.5.3 CPSW_CPTS Registers ......................................................................................
15.5.4 CPSW_STATS Registers ....................................................................................
15.5.5 CPDMA_STATERAM Registers.............................................................................
15.5.6 CPSW_PORT Registers .....................................................................................
15.5.7 CPSW_SL Registers ..........................................................................................
15.5.8 CPSW_SS Registers .........................................................................................
15.5.9 CPSW_WR Registers ........................................................................................
15.5.10 MDIO Registers ..............................................................................................
2217
2217
2218
2219
2220
2221
2222
2222
2223
2225
2227
2229
2229
2234
2276
2278
2278
2279
2280
2285
2288
2288
2290
2291
2291
2292
2292
2293
2293
2303
2356
2372
2372
2406
2464
2478
2492
2528
Universal Serial Bus (USB) ............................................................................................... 2545
16.1
16.2
16.3
Introduction ...............................................................................................................
16.1.1 Features ........................................................................................................
16.1.2 Unsupported Features ........................................................................................
Integration ................................................................................................................
16.2.1 USB Clock and Reset Management ........................................................................
16.2.2 USB Pin List ...................................................................................................
Use Cases................................................................................................................
16.3.1 USB Operational Mode Determination .....................................................................
16.3.2 Typical Pin Connections of AM437x Device ...............................................................
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Contents
2546
2546
2546
2547
2548
2548
2549
2549
2550
7
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16.4
17
17.2
17.3
17.4
17.5
18.2
2553
2553
2553
2554
2555
2556
2556
2558
2558
2564
2565
2568
2570
2573
2573
2576
2577
2582
2584
2585
2587
2589
2589
2590
2591
2591
2591
2594
2595
2595
Mailbox ...................................................................................................................
18.1.1 Introduction .....................................................................................................
18.1.2 Integration ......................................................................................................
18.1.3 Functional Description ........................................................................................
18.1.4 Programming Guide ..........................................................................................
18.1.5 MAILBOX Registers ..........................................................................................
Spinlock...................................................................................................................
18.2.1 SPINLOCK Registers .........................................................................................
2651
2651
2652
2654
2658
2661
2720
2720
Timers ........................................................................................................................... 2756
19.1
19.2
8
Introduction ...............................................................................................................
17.1.1 MMCSD Features .............................................................................................
17.1.2 Unsupported MMCSD Features .............................................................................
Integration ................................................................................................................
17.2.1 MMCSD Connectivity Attributes .............................................................................
17.2.2 MMCSD Clock and Reset Management ...................................................................
17.2.3 MMCSD Pin List ...............................................................................................
Functional Description ..................................................................................................
17.3.1 MMC/SD/SDIO Functional Modes ..........................................................................
17.3.2 Resets ..........................................................................................................
17.3.3 Power Management ..........................................................................................
17.3.4 Interrupt Requests ............................................................................................
17.3.5 DMA Modes ...................................................................................................
17.3.6 Mode Selection ................................................................................................
17.3.7 Buffer Management ...........................................................................................
17.3.8 Transfer Process ..............................................................................................
17.3.9 Transfer or Command Status and Error Reporting .......................................................
17.3.10 Auto Command 12 Timings ................................................................................
17.3.11 Transfer Stop .................................................................................................
17.3.12 Output Signals Generation .................................................................................
17.3.13 Card Boot Mode Management .............................................................................
17.3.14 CE-ATA Command Completion Disable Management .................................................
17.3.15 Test Registers ................................................................................................
17.3.16 MMC/SD/SDIO Hardware Status Features ..............................................................
Low-Level Programming Models ......................................................................................
17.4.1 Surrounding Modules Global Initialization .................................................................
17.4.2 MMC/SD/SDIO Controller Initialization Flow ..............................................................
17.4.3 Operational Modes Configuration ...........................................................................
MMC/SD Registers ......................................................................................................
17.5.1 MMCSD Registers ............................................................................................
Interprocessor Communication......................................................................................... 2650
18.1
19
2551
2551
2551
2551
Multimedia Card (MMC) .................................................................................................... 2552
17.1
18
16.3.3 VBUS Voltage Sourcing Control ............................................................................
16.3.4 Pull-up/Pull-down Resistors ..................................................................................
16.3.5 Clock, PLL, and PHY Initialization ..........................................................................
Reference Documentation .............................................................................................
DMTimer ..................................................................................................................
19.1.1 Introduction .....................................................................................................
19.1.2 Integration ......................................................................................................
19.1.3 Functional Description ........................................................................................
19.1.4 DMTIMER Registers ..........................................................................................
DMTimer 1ms ............................................................................................................
19.2.1 Introduction .....................................................................................................
19.2.2 Integration ......................................................................................................
Contents
2757
2757
2759
2764
2775
2795
2795
2797
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19.3
19.4
19.5
20
2799
2807
2831
2831
2832
2834
2835
2839
2839
2840
2842
2850
2850
2888
2888
2889
2891
2898
Pulse-Width Modulation Subsystem (PWMSS) .................................................................... 2915
20.1
20.2
20.3
20.4
21
19.2.3 Functional Description ........................................................................................
19.2.4 DMTIMER_1MS Registers ...................................................................................
Sync Timer (32k) ........................................................................................................
19.3.1 Introduction .....................................................................................................
19.3.2 Integration ......................................................................................................
19.3.3 Functional Description ........................................................................................
19.3.4 SYNCTIMER Registers .......................................................................................
Real-Time Clock (RTC) .................................................................................................
19.4.1 Introduction .....................................................................................................
19.4.2 Integration ......................................................................................................
19.4.3 Functional Description ........................................................................................
19.4.4 Use Cases .....................................................................................................
19.4.5 RTC Registers .................................................................................................
WATCHDOG .............................................................................................................
19.5.1 Introduction .....................................................................................................
19.5.2 Integration ......................................................................................................
19.5.3 Functional Description ........................................................................................
19.5.4 WDT Registers ................................................................................................
Pulse-Width Modulation Subsystem (PWMSS) .....................................................................
20.1.1 Introduction .....................................................................................................
20.1.2 Integration ......................................................................................................
20.1.3 PWMSS Registers ............................................................................................
Enhanced PWM (ePWM) Module .....................................................................................
20.2.1 Introduction .....................................................................................................
20.2.2 Functional Description ........................................................................................
20.2.3 Use Cases .....................................................................................................
20.2.4 PWMSS_EPWM Registers ..................................................................................
Enhanced Capture (eCAP) Module ...................................................................................
20.3.1 Introduction .....................................................................................................
20.3.2 Functional Description ........................................................................................
20.3.3 Use Cases .....................................................................................................
20.3.4 Registers .......................................................................................................
20.3.5 PWMSS_ECAP Registers ...................................................................................
Enhanced Quadrature Encoder Pulse (eQEP) Module ............................................................
20.4.1 Introduction .....................................................................................................
20.4.2 Functional Description ........................................................................................
20.4.3 PWMSS_EQEP Registers ...................................................................................
2916
2916
2918
2921
2926
2926
2930
2990
3014
3050
3050
3051
3060
3076
3076
3092
3092
3095
3113
Universal Asynchronous Receiver/Transmitter (UART) ........................................................ 3140
21.1
21.2
21.3
Introduction ...............................................................................................................
21.1.1 UART Mode Features ........................................................................................
21.1.2 IrDA Mode Features ..........................................................................................
21.1.3 CIR Mode Features ...........................................................................................
21.1.4 Unsupported UART Features ................................................................................
Integration ................................................................................................................
21.2.1 UART Connectivity Attributes ................................................................................
21.2.2 UART Clock and Reset Management ......................................................................
21.2.3 UART Pin List ..................................................................................................
Functional Description ..................................................................................................
21.3.1 Block Diagram .................................................................................................
21.3.2 Clock Configuration ...........................................................................................
21.3.3 Software Reset ................................................................................................
21.3.4 Power Management ..........................................................................................
SPRUHL7I – April 2014 – Revised December 2019
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Contents
3141
3141
3141
3141
3141
3143
3143
3144
3146
3147
3147
3148
3148
3148
9
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21.4
21.5
22
21.3.5 Interrupt Requests ............................................................................................
21.3.6 FIFO Management ............................................................................................
21.3.7 Mode Selection ................................................................................................
21.3.8 Protocol Formatting ...........................................................................................
UART/IrDA/CIR Basic Programming Model .........................................................................
21.4.1 UART Programming Model ..................................................................................
21.4.2 IrDA Programming Model ....................................................................................
UART Registers .........................................................................................................
21.5.1 UART Registers ...............................................................................................
3150
3153
3161
3167
3190
3190
3196
3199
3199
................................................................................................................................ 3255
Introduction ............................................................................................................... 3256
22.1.1 I2C Features ................................................................................................... 3256
22.1.2 Unsupported I2C Features ................................................................................... 3256
22.2 Integration ................................................................................................................ 3257
22.2.1 I2C Connectivity Attributes ................................................................................... 3257
22.2.2 I2C Clock and Reset Management ......................................................................... 3258
22.2.3 I2C Pin List ..................................................................................................... 3258
22.3 Functional Description .................................................................................................. 3259
22.3.1 Functional Block Diagram .................................................................................... 3259
22.3.2 I2C Master/Slave Contoller Signals ......................................................................... 3259
22.3.3 I2C Reset ....................................................................................................... 3260
22.3.4 Data Validity ................................................................................................... 3261
22.3.5 START & STOP Conditions.................................................................................. 3262
22.3.6 I2C Operation .................................................................................................. 3262
22.3.7 Arbitration ...................................................................................................... 3264
22.3.8 I2C Clock Generation and I2C Clock Synchronization ................................................... 3264
22.3.9 Prescaler (SCLK/ICLK) ....................................................................................... 3265
22.3.10 Noise Filter ................................................................................................... 3265
22.3.11 I2C Interrupts ................................................................................................. 3265
22.3.12 DMA Events .................................................................................................. 3266
22.3.13 Interrupt and DMA Events .................................................................................. 3266
22.3.14 FIFO Management .......................................................................................... 3266
22.3.15 How to Program I2C......................................................................................... 3271
22.3.16 I2C Behavior During Emulation ............................................................................ 3272
22.4 I2C Registers ............................................................................................................ 3272
22.4.1 I2C Registers .................................................................................................. 3272
HDQ/1-Wire Interface ....................................................................................................... 3325
23.1 Introduction ............................................................................................................... 3326
23.1.1 HDQ1W Features ............................................................................................. 3326
23.2 Integration ................................................................................................................ 3327
23.2.1 HDQ1W Connectivity Attributes ............................................................................. 3327
23.2.2 HDQ1W Clock and Reset Management ................................................................... 3327
23.2.3 HDQ1W Pin List ............................................................................................... 3327
23.3 Functional Description .................................................................................................. 3329
23.3.1 HDQ/1-Wire Functional Interface ........................................................................... 3329
23.3.2 HDQ and 1-Wire (SDQ) Protocols .......................................................................... 3329
23.3.3 HDQ/1-Wire Block Diagram .................................................................................. 3332
23.3.4 HDQ Mode (Default) .......................................................................................... 3333
23.3.5 1-Wire Mode ................................................................................................... 3335
23.3.6 Module Power Saving ........................................................................................ 3336
23.3.7 System Power Management and Wakeup ................................................................. 3336
23.4 Programming Model .................................................................................................... 3338
23.4.1 Module Initialization Sequence .............................................................................. 3338
I2C
22.1
23
10
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23.5
23.6
24
3338
3339
3340
3342
3342
3344
3344
Multichannel Audio Serial Port (McASP) ............................................................................ 3352
24.1
24.2
24.3
24.4
25
23.4.2 HDQ Protocol Basic Programming Model .................................................................
23.4.3 1-Wire Mode (SDQ) Basic Programming Model ..........................................................
23.4.4 Power Management ..........................................................................................
Use Cases................................................................................................................
23.5.1 How to Configure the HDQ/1-Wire when Connected with a BQ27000 Gauge........................
HDQ/1-Wire Registers ..................................................................................................
23.6.1 HDQ1W Registers ............................................................................................
Introduction ...............................................................................................................
24.1.1 Purpose of the Peripheral ....................................................................................
24.1.2 Features ........................................................................................................
24.1.3 Protocols Supported .........................................................................................
24.1.4 Unsupported McASP Features ..............................................................................
Integration ................................................................................................................
24.2.1 McASP Connectivity Attributes ..............................................................................
24.2.2 McASP Clock and Reset Management ....................................................................
24.2.3 McASP Pin List ................................................................................................
Functional Description ..................................................................................................
24.3.1 Overview .......................................................................................................
24.3.2 Functional Block Diagram ....................................................................................
24.3.3 Industry Standard Compliance Statement .................................................................
24.3.4 Definition of Terms ............................................................................................
24.3.5 Clock and Frame Sync Generators .........................................................................
24.3.6 Signal Descriptions............................................................................................
24.3.7 Pin Multiplexing ................................................................................................
24.3.8 Transfer Modes ................................................................................................
24.3.9 General Architecture ..........................................................................................
24.3.10 Operation .....................................................................................................
24.3.11 Reset Considerations .......................................................................................
24.3.12 Setup and Initialization ......................................................................................
24.3.13 Interrupts ......................................................................................................
24.3.14 EDMA Event Support .......................................................................................
24.3.15 Power Management .........................................................................................
24.3.16 Emulation Considerations ..................................................................................
McASP Registers........................................................................................................
24.4.1 MCASP Registers .............................................................................................
3353
3353
3353
3354
3354
3355
3355
3356
3356
3357
3357
3358
3361
3365
3367
3371
3371
3372
3379
3383
3400
3400
3405
3407
3409
3409
3410
3410
Controller Area Network (CAN) ......................................................................................... 3472
25.1
25.2
25.3
Introduction ...............................................................................................................
25.1.1 DCAN Features ................................................................................................
25.1.2 Unsupported DCAN Features ...............................................................................
Integration ................................................................................................................
25.2.1 DCAN Connectivity Attributes ...............................................................................
25.2.2 DCAN Clock and Reset Management ......................................................................
25.2.3 DCAN Pin List .................................................................................................
Functional Description ..................................................................................................
25.3.1 CAN Core ......................................................................................................
25.3.2 Message Handler .............................................................................................
25.3.3 Message RAM .................................................................................................
25.3.4 Message RAM Interface ......................................................................................
25.3.5 Registers and Message Object Access ....................................................................
25.3.6 Module Interface...............................................................................................
25.3.7 Dual Clock Source ............................................................................................
25.3.8 CAN Operation ................................................................................................
SPRUHL7I – April 2014 – Revised December 2019
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3473
3473
3473
3474
3474
3475
3475
3476
3476
3477
3477
3477
3477
3477
3477
3478
11
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25.4
26
3484
3485
3487
3489
3490
3490
3493
3498
3506
3508
3513
3513
3513
Multichannel Serial Port Interface (McSPI).......................................................................... 3584
26.1
26.2
26.3
26.4
27
25.3.9 Dual Clock Source ............................................................................................
25.3.10 Interrupt Functionality .......................................................................................
25.3.11 Local Power-Down Mode ...................................................................................
25.3.12 Parity Check Mechanism ...................................................................................
25.3.13 Debug/Suspend Mode ......................................................................................
25.3.14 Configuration of Message Objects ........................................................................
25.3.15 Message Handling ...........................................................................................
25.3.16 CAN Bit Timing ...............................................................................................
25.3.17 Message Interface Register Sets ..........................................................................
25.3.18 Message RAM ...............................................................................................
25.3.19 GIO Support ..................................................................................................
DCAN Registers .........................................................................................................
25.4.1 DCAN Registers ...............................................................................................
Introduction ...............................................................................................................
26.1.1 McSPI Features ...............................................................................................
26.1.2 Unsupported McSPI Features ...............................................................................
Integration ................................................................................................................
26.2.1 McSPI Connectivity Attributes ...............................................................................
26.2.2 McSPI Clock and Reset Management .....................................................................
26.2.3 McSPI Pin List .................................................................................................
Functional Description ..................................................................................................
26.3.1 SPI Transmission .............................................................................................
26.3.2 Master Mode ..................................................................................................
26.3.3 Slave Mode ....................................................................................................
26.3.4 Interrupts .......................................................................................................
26.3.5 DMA Requests ................................................................................................
26.3.6 Emulation Mode ..............................................................................................
26.3.7 Power Saving Management .................................................................................
26.3.8 System Test Mode ...........................................................................................
26.3.9 Reset ...........................................................................................................
26.3.10 Access to Data Registers ..................................................................................
26.3.11 Programming Aid ...........................................................................................
26.3.12 Interrupt and DMA Events .................................................................................
McSPI Registers .........................................................................................................
26.4.1 MCSPI Registers ..............................................................................................
3585
3585
3585
3586
3587
3587
3587
3589
3589
3596
3613
3617
3618
3619
3620
3621
3621
3622
3622
3623
3623
3623
QSPI .............................................................................................................................. 3677
27.1
27.2
27.3
27.4
Introduction ...............................................................................................................
27.1.1 QSPI Features .................................................................................................
27.1.2 Unsupported Features ........................................................................................
Integration ................................................................................................................
27.2.1 QSPI Connectivity Attributes.................................................................................
27.2.2 QSPI Clock and Reset Management .......................................................................
27.2.3 QSPI Pin List...................................................................................................
QSPI Functional Description ...........................................................................................
27.3.1 QSPI Block Diagram ..........................................................................................
27.3.2 QSPI Clock Configuration ....................................................................................
27.3.3 QSPI Interrupt Requests .....................................................................................
27.3.4 QSPI Memory Regions .......................................................................................
QSPI Registers ..........................................................................................................
27.4.1 QSPI Registers ................................................................................................
3678
3678
3678
3679
3679
3679
3679
3680
3680
3685
3685
3687
3687
3687
28
General-Purpose Input/Output .......................................................................................... 3709
12
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28.1
28.2
28.3
28.4
29
Graphics Accelerator (SGX)
29.1
29.2
29.3
30
Introduction ...............................................................................................................
28.1.1 Purpose of the Peripheral ....................................................................................
28.1.2 GPIO Features ................................................................................................
28.1.3 Unsupported GPIO Features ................................................................................
Integration ................................................................................................................
28.2.1 GPIO Connectivity Attributes ................................................................................
28.2.2 GPIO Clock and Reset Management .......................................................................
28.2.3 GPIO Pin List ..................................................................................................
Functional Description ..................................................................................................
28.3.1 Operating Modes ..............................................................................................
28.3.2 Clocking and Reset Strategy ................................................................................
28.3.3 Interrupt and Wake-up Features ............................................................................
28.3.4 General-Purpose Interface Basic Programming Model ..................................................
GPIO Registers ..........................................................................................................
28.4.1 GPIO Registers ................................................................................................
3710
3710
3710
3710
3711
3712
3713
3714
3715
3715
3715
3716
3719
3724
3724
............................................................................................. 3751
Introduction ...............................................................................................................
29.1.1 POWERVR SGX Main Features ............................................................................
29.1.2 SGX 3D Features .............................................................................................
29.1.3 Universal Scalable Shader Engine (USSE) – Key Features ............................................
29.1.4 Unsupported Features ........................................................................................
Integration ................................................................................................................
29.2.1 SGX530 Connectivity Attributes .............................................................................
29.2.2 SGX530 Clock and Reset Management ...................................................................
29.2.3 SGX530 Pin List ...............................................................................................
Functional Description ..................................................................................................
29.3.1 SGX Block Diagram...........................................................................................
29.3.2 SGX Elements Description ...................................................................................
3752
3752
3753
3754
3754
3755
3755
3755
3756
3757
3757
3757
Programmable Real-Time Unit Subsystem and Industrial Communication Subsystem (PRUICSS) ............................................................................................................................. 3759
30.1
30.2
30.3
30.4
30.5
Introduction ...............................................................................................................
30.1.1 Features ........................................................................................................
Integration ................................................................................................................
30.2.1 PRU-ICSS Connectivity Attributes ..........................................................................
30.2.2 PRU-ICSS Clock and Reset Management.................................................................
30.2.3 PRU-ICSS Pin List ............................................................................................
PRU-ICSS Memory Map Overview ...................................................................................
30.3.1 Local Memory Map ............................................................................................
30.3.2 Global Memory Map ..........................................................................................
Functional Description ..................................................................................................
30.4.1 PRU Cores .....................................................................................................
30.4.2 Interrupt Controller (INTC) ...................................................................................
30.4.3 Industrial Ethernet Peripheral (IEP) .........................................................................
30.4.4 Universal Asynchronous Receiver/Transmitter ............................................................
30.4.5 ECAP ...........................................................................................................
30.4.6 MII_RT ..........................................................................................................
30.4.7 MDIO ............................................................................................................
Registers .................................................................................................................
30.5.1 PRU_ICSS_PRU_CTRL Registers .........................................................................
30.5.2 PRU_ICSS_PRU_DEBUG Registers .......................................................................
30.5.3 PRU_ICSS_INTC Registers .................................................................................
30.5.4 PRU_ICSS_IEP Registers ...................................................................................
30.5.5 PRU_ICSS_UART Registers ................................................................................
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Contents
3760
3762
3763
3765
3765
3766
3768
3768
3769
3771
3771
3812
3822
3831
3844
3845
3865
3866
3866
3877
3942
4006
4068
13
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30.5.6
30.5.7
30.5.8
30.5.9
31
PRU_ICSS_ECAP Registers ................................................................................
PRU_ICSS_MII_RT Registers ...............................................................................
PRU_ICSS_MDIO Registers ................................................................................
PRU_ICSS_CFG Registers ..................................................................................
4086
4086
4111
4111
Debug Subsystem ........................................................................................................... 4144
31.1
31.2
31.3
31.4
31.5
Chip Architecture Specification ........................................................................................
31.1.1 Debug Resource Manager (DRM) ..........................................................................
31.1.2 On-Chip Debug and Trace ...................................................................................
31.1.3 Debugger Connection ........................................................................................
31.1.4 Primary Debug Support ......................................................................................
31.1.5 Suspend ........................................................................................................
31.1.6 Power, Reset and Clock Management Debug Support ..................................................
31.1.7 Performance Monitoring ......................................................................................
31.1.8 Trace Datapath ................................................................................................
31.1.9 Processor Trace ...............................................................................................
31.1.10 Crash Dump ..................................................................................................
System Instrumentation ................................................................................................
31.2.1 MIPI STM .......................................................................................................
31.2.2 Trace Exported to an External Trace Receiver ...........................................................
31.2.3 Trace Captured into On-chip Trace Buffer .................................................................
31.2.4 Software Instrumentation .....................................................................................
31.2.5 CTools System Bus Watchpoint and Traffic Monitors (OCP_WP)......................................
31.2.6 L3 NoC Statistics Collector ..................................................................................
31.2.7 Hardware Masters .............................................................................................
Concurrent Debug Mode ...............................................................................................
Memory Mapping ........................................................................................................
DRM Registers ..........................................................................................................
31.5.1 DEBUGSS_DRM_SUSPEND_CTRL0 Register (Offset = 200h) [reset = 0h] .........................
31.5.2 DEBUGSS_DRM_SUSPEND_CTRL1 Register (Offset = 204h) [reset = 0h] .........................
31.5.3 DEBUGSS_DRM_SUSPEND_CTRL2 Register (Offset = 208h) [reset = 0h] .........................
31.5.4 DEBUGSS_DRM_SUSPEND_CTRL3 Register (Offset = 20Ch) [reset = 0h] ........................
31.5.5 DEBUGSS_DRM_SUSPEND_CTRL4 Register (Offset = 210h) [reset = 0h] .........................
31.5.6 DEBUGSS_DRM_SUSPEND_CTRL5 Register (Offset = 214h) [reset = 0h] .........................
31.5.7 DEBUGSS_DRM_SUSPEND_CTRL6 Register (Offset = 218h) [reset = 0h] .........................
31.5.8 DEBUGSS_DRM_SUSPEND_CTRL7 Register (Offset = 21Ch) [reset = 0h] ........................
31.5.9 DEBUGSS_DRM_SUSPEND_CTRL8 Register (Offset = 220h) [reset = 0h] .........................
31.5.10 DEBUGSS_DRM_SUSPEND_CTRL10 Register (Offset = 228h) [reset = 0h] ......................
31.5.11 DEBUGSS_DRM_SUSPEND_CTRL11 Register (Offset = 22Ch) [reset = 0h] .....................
31.5.12 DEBUGSS_DRM_SUSPEND_CTRL12 Register (Offset = 230h) [reset = 0h] ......................
31.5.13 DEBUGSS_DRM_SUSPEND_CTRL13 Register (Offset = 234h) [reset = 0h] ......................
31.5.14 DEBUGSS_DRM_SUSPEND_CTRL14 Register (Offset = 238h) [reset = 0h] ......................
31.5.15 DEBUGSS_DRM_SUSPEND_CTRL15 Register (Offset = 23Ch) [reset = 0h] .....................
31.5.16 DEBUGSS_DRM_SUSPEND_CTRL16 Register (Offset = 240h) [reset = 0h] ......................
31.5.17 DEBUGSS_DRM_SUSPEND_CTRL17 Register (Offset = 244h) [reset = 0h] ......................
31.5.18 DEBUGSS_DRM_SUSPEND_CTRL18 Register (Offset = 248h) [reset = 0h] ......................
31.5.19 DEBUGSS_DRM_SUSPEND_CTRL19 Register (Offset = 24Ch) [reset = 0h] .....................
31.5.20 DEBUGSS_DRM_SUSPEND_CTRL24 Register (Offset = 260h) [reset = 0h] ......................
31.5.21 DEBUGSS_DRM_SUSPEND_CTRL27 Register (Offset = 26Ch) [reset = 0h] .....................
31.5.22 DEBUGSS_DRM_SUSPEND_CTRL28 Register (Offset = 270h) [reset = 0h] ......................
31.5.23 DEBUGSS_DRM_SUSPEND_CTRL29 Register (Offset = 274h) [reset = 0h] ......................
4145
4145
4145
4149
4152
4154
4155
4156
4156
4156
4159
4159
4159
4160
4160
4161
4162
4163
4168
4168
4169
4170
4172
4173
4174
4175
4176
4177
4178
4179
4180
4181
4182
4183
4184
4185
4186
4187
4188
4189
4190
4191
4192
4193
4194
A
Glossary ........................................................................................................................ 4195
14
Contents
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List of Figures
3-1.
MPU Subsystem Block Diagram ........................................................................................ 153
3-2.
MPU Subsystem Clocking Scheme .................................................................................... 156
3-3.
WFI/WFE Control Register .............................................................................................. 158
3-4.
WkupGenEnb Registers ................................................................................................. 159
3-5.
L2 Usage as SRAM
4-1.
4-2.
5-1.
5-2.
5-3.
5-4.
5-5.
5-6.
5-7.
5-8.
5-9.
5-10.
5-11.
5-12.
5-13.
5-14.
5-15.
5-16.
5-17.
5-18.
5-19.
5-20.
5-21.
5-22.
5-23.
5-24.
5-25.
5-26.
5-27.
5-28.
6-1.
6-2.
6-3.
6-4.
6-5.
6-6.
6-7.
6-8.
6-9.
6-10.
6-11.
6-12.
......................................................................................................
L3 Topology ...............................................................................................................
L4 Topology ...............................................................................................................
Public ROM Code Architecture .........................................................................................
Public ROM Code Boot Procedure .....................................................................................
ROM Memory Map .......................................................................................................
Public L3 RAM Memory Map ............................................................................................
The ROM Exception Handling Flow ....................................................................................
ROM Code Startup Sequence ..........................................................................................
ROM Code Booting Procedure..........................................................................................
Memory Booting...........................................................................................................
Image Shadowing on GP Device .......................................................................................
GPMC NOR Timings .....................................................................................................
GPMC NAND Timings ...................................................................................................
NAND Device Detection .................................................................................................
NAND Invalid Blocks Detection .........................................................................................
NAND Read Sector Procedure..........................................................................................
NAND ECC Scheme Selection Procedure ............................................................................
ECC Data Mapping for 2KB Page and 8b BCH Encoding ..........................................................
ECC Data Mapping for 4KB Page and 16b BCH Encoding .........................................................
MMC/SD Booting .........................................................................................................
MMC/SD Detection Procedure ..........................................................................................
SD/MMC Booting, Get Booting File ....................................................................................
MBR Detection Procedure ...............................................................................................
MBR, Get Partition ........................................................................................................
FAT Detection Procedure ................................................................................................
Peripheral Booting Procedure ...........................................................................................
USB Initialization Procedure.............................................................................................
Image Transfer for USB Boot ...........................................................................................
Low Latency NOR Boot ..................................................................................................
Image Formats on GP Devices .........................................................................................
Functional and Interface Clocks ........................................................................................
Generic Clock Domain ...................................................................................................
Clock Domain State Transitions ........................................................................................
Generic Power Domain Architecture ...................................................................................
High Level System View for RTC-only Mode .........................................................................
DeepSleep System View ................................................................................................
IPC Mechanism ...........................................................................................................
Internal Clocking Architecture ...........................................................................................
ADPLLS ....................................................................................................................
Basic Structure of the ADPLLLJ ........................................................................................
Effect of the SSC in Frequency .........................................................................................
Effect of the SSC in the Time Domain .................................................................................
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List of Figures
163
169
173
175
177
178
180
182
183
185
197
198
199
204
205
209
210
211
211
212
214
215
217
219
219
222
231
236
237
239
240
250
255
255
257
261
265
266
271
272
274
276
277
15
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16
6-13.
Peak Reduction Caused by Spreading ................................................................................ 277
6-14.
Core PLL Structure ....................................................................................................... 280
6-15.
Peripheral PLL Structure ................................................................................................. 283
6-16.
MPU Subsystem PLL Structure ......................................................................................... 284
6-17.
Display PLL Structure .................................................................................................... 285
6-18.
DDR PLL Structure ....................................................................................................... 286
6-19.
EXTDEV PLL Structure .................................................................................................. 287
6-20.
CLKOUT Architecture .................................................................................................... 289
6-21.
Watchdog Timer Clock Selection ....................................................................................... 290
6-22.
Timer Clock Selection .................................................................................................... 291
6-23.
RTC, VTP and Debounce Clock Selection ............................................................................ 292
6-24.
ADC0, ADC1, DCAN, and McASP Clock Selection .................................................................. 293
6-25.
PORz ....................................................................................................................... 295
6-26.
External Buffer for nRESETIN_OUT ................................................................................... 295
6-27.
External System Reset ................................................................................................... 297
6-28.
Warm Reset Sequence (External Warm Reset Source)............................................................. 298
6-29.
Warm Reset Sequence (Internal Warm Reset Source)
6-30.
PRCM_PM_CEFUSE_PWRSTCTRL Register ....................................................................... 308
6-31.
PRCM_PM_CEFUSE_PWRSTST Register ........................................................................... 309
6-32.
PRCM_RM_CEFUSE_CONTEXT Register ........................................................................... 310
6-33.
PRCM_PRM_RSTCTRL Register ...................................................................................... 312
6-34.
PRCM_PRM_RSTST Register .......................................................................................... 313
6-35.
PRCM_PRM_RSTTIME Register ....................................................................................... 314
6-36.
PRCM_PRM_SRAM_COUNT Register................................................................................ 315
6-37.
PRCM_PRM_LDO_SRAM_CORE_SETUP Register ................................................................ 316
6-38.
PRCM_PRM_LDO_SRAM_CORE_CTRL Register .................................................................. 318
6-39.
PRCM_PRM_LDO_SRAM_MPU_SETUP Register .................................................................. 319
6-40.
PRCM_PRM_LDO_SRAM_MPU_CTRL Register .................................................................... 321
6-41.
PRCM_PRM_IO_COUNT Register..................................................................................... 322
6-42.
PRCM_PRM_IO_PMCTRL Register ................................................................................... 323
6-43.
PRCM_PRM_VC_VAL_BYPASS Register ............................................................................ 325
6-44.
PRCM_PRM_EMIF_CTRL Register
6-45.
PRCM_PRM_PM_GFX_PWRSTCTRL Register ..................................................................... 327
6-46.
PRCM_PRM_PM_GFX_PWRSTST Register ......................................................................... 328
6-47.
PRCM_PRM_RM_GFX_RSTCTRL Register ......................................................................... 329
6-48.
PRCM_PRM_RM_GFX_RSTST Register ............................................................................. 330
6-49.
PRCM_PRM_RM_GFX_CONTEXT Register ......................................................................... 331
6-50.
PRCM_PM_MPU_PWRSTCTRL Register ............................................................................ 332
6-51.
PRCM_PM_MPU_PWRSTST Register ................................................................................ 334
6-52.
PRCM_RM_MPU_RSTST Register .................................................................................... 336
6-53.
PRCM_RM_MPU_CONTEXT Register ................................................................................ 337
6-54.
PRCM_PM_PER_PWRSTCTRL Register............................................................................. 340
6-55.
PRCM_PM_PER_PWRSTST Register ................................................................................ 342
6-56.
PRCM_RM_PER_RSTCTRL Register ................................................................................. 344
6-57.
PRCM_RM_PER_RSTST Register
6-58.
PRCM_RM_PER_L3_CONTEXT Register ............................................................................ 346
6-59.
PRCM_RM_PER_L3_INSTR_CONTEXT Register .................................................................. 347
6-60.
PRCM_RM_PER_OCMCRAM_CONTEXT Register ................................................................. 348
6-61.
PRCM_RM_PER_VPFE0_CONTEXT Register ...................................................................... 349
List of Figures
.............................................................
...................................................................................
....................................................................................
298
326
345
SPRUHL7I – April 2014 – Revised December 2019
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6-62.
PRCM_RM_PER_VPFE1_CONTEXT Register ...................................................................... 350
6-63.
PRCM_RM_PER_TPCC_CONTEXT Register
6-64.
PRCM_RM_PER_TPTC0_CONTEXT Register ...................................................................... 352
6-65.
PRCM_RM_PER_TPTC1_CONTEXT Register ...................................................................... 353
6-66.
PRCM_RM_PER_TPTC2_CONTEXT Register ...................................................................... 354
6-67.
PRCM_RM_PER_DLL_AGING_CONTEXT Register ................................................................ 355
6-68.
PRCM_RM_PER_L4HS_CONTEXT Register ........................................................................ 356
6-69.
PRCM_RM_PER_GPMC_CONTEXT Register ....................................................................... 357
6-70.
PRCM_RM_PER_ADC1_CONTEXT Register ........................................................................ 358
6-71.
PRCM_RM_PER_MCASP0_CONTEXT Register .................................................................... 359
6-72.
PRCM_RM_PER_MCASP1_CONTEXT Register .................................................................... 360
6-73.
PRCM_RM_PER_MMC2_CONTEXT Register ....................................................................... 361
6-74.
PRCM_RM_PER_QSPI_CONTEXT Register
362
6-75.
PRCM_RM_PER_USB_OTG_SS0_CONTEXT Register
363
6-76.
6-77.
6-78.
6-79.
6-80.
6-81.
6-82.
6-83.
6-84.
6-85.
6-86.
6-87.
6-88.
6-89.
6-90.
6-91.
6-92.
6-93.
6-94.
6-95.
6-96.
6-97.
6-98.
6-99.
6-100.
6-101.
6-102.
6-103.
6-104.
6-105.
6-106.
6-107.
6-108.
6-109.
6-110.
.......................................................................
........................................................................
...........................................................
PRCM_RM_PER_USB_OTG_SS1_CONTEXT Register ...........................................................
PRCM_RM_PER_PRU_ICSS_CONTEXT Register .................................................................
PRCM_RM_PER_L4LS_CONTEXT Register.........................................................................
PRCM_RM_PER_DCAN0_CONTEXT Register ......................................................................
PRCM_RM_PER_DCAN1_CONTEXT Register ......................................................................
PRCM_RM_PER_PWMSS0_CONTEXT Register ...................................................................
PRCM_RM_PER_PWMSS1_CONTEXT Register ...................................................................
PRCM_RM_PER_PWMSS2_CONTEXT Register ...................................................................
PRCM_RM_PER_PWMSS3_CONTEXT Register ...................................................................
PRCM_RM_PER_PWMSS4_CONTEXT Register ...................................................................
PRCM_RM_PER_PWMSS5_CONTEXT Register ...................................................................
PRCM_RM_PER_ELM_CONTEXT Register .........................................................................
PRCM_RM_PER_GPIO1_CONTEXT Register.......................................................................
PRCM_RM_PER_GPIO2_CONTEXT Register.......................................................................
PRCM_RM_PER_GPIO3_CONTEXT Register.......................................................................
PRCM_RM_PER_GPIO4_CONTEXT Register.......................................................................
PRCM_RM_PER_GPIO5_CONTEXT Register.......................................................................
PRCM_RM_PER_HDQ1W_CONTEXT Register .....................................................................
PRCM_RM_PER_I2C1_CONTEXT Register .........................................................................
PRCM_RM_PER_I2C2_CONTEXT Register .........................................................................
PRCM_RM_PER_MAILBOX0_CONTEXT Register .................................................................
PRCM_RM_PER_MMC0_CONTEXT Register .......................................................................
PRCM_RM_PER_MMC1_CONTEXT Register .......................................................................
PRCM_RM_PER_SPI0_CONTEXT Register .........................................................................
PRCM_RM_PER_SPI1_CONTEXT Register .........................................................................
PRCM_RM_PER_SPI2_CONTEXT Register .........................................................................
PRCM_RM_PER_SPI3_CONTEXT Register .........................................................................
PRCM_RM_PER_SPI4_CONTEXT Register .........................................................................
PRCM_RM_PER_SPINLOCK_CONTEXT Register .................................................................
PRCM_RM_PER_TIMER2_CONTEXT Register .....................................................................
PRCM_RM_PER_TIMER3_CONTEXT Register .....................................................................
PRCM_RM_PER_TIMER4_CONTEXT Register .....................................................................
PRCM_RM_PER_TIMER5_CONTEXT Register .....................................................................
PRCM_RM_PER_TIMER6_CONTEXT Register .....................................................................
PRCM_RM_PER_TIMER7_CONTEXT Register .....................................................................
SPRUHL7I – April 2014 – Revised December 2019
Submit Documentation Feedback
Copyright © 2014–2019, Texas Instruments Incorporated
List of Figures
351
364
365
366
367
368
369
370
371
372
373
374
375
376
377
378
379
380
381
382
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385
386
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391
392
393
394
395
396
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398
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6-111. PRCM_RM_PER_TIMER8_CONTEXT Register ..................................................................... 399
6-112. PRCM_RM_PER_TIMER9_CONTEXT Register ..................................................................... 400
401
6-114. PRCM_RM_PER_TIMER11_CONTEXT Register
402
6-115.
403
6-116.
6-117.
6-118.
6-119.
6-120.
6-121.
6-122.
6-123.
6-124.
6-125.
6-126.
6-127.
6-128.
6-129.
6-130.
6-131.
6-132.
6-133.
6-134.
6-135.
6-136.
6-137.
6-138.
6-139.
6-140.
6-141.
6-142.
6-143.
6-144.
6-145.
6-146.
6-147.
6-148.
6-149.
6-150.
6-151.
6-152.
6-153.
6-154.
6-155.
6-156.
6-157.
6-158.
6-159.
18
...................................................................
...................................................................
PRCM_RM_PER_UART1_CONTEXT Register ......................................................................
PRCM_RM_PER_UART2_CONTEXT Register ......................................................................
PRCM_RM_PER_UART3_CONTEXT Register ......................................................................
PRCM_RM_PER_UART4_CONTEXT Register ......................................................................
PRCM_RM_PER_UART5_CONTEXT Register ......................................................................
PRCM_RM_PER_USBPHYOCP2SCP0_CONTEXT Register .....................................................
PRCM_RM_PER_USBPHYOCP2SCP1_CONTEXT Register .....................................................
PRCM_RM_PER_EMIF_CONTEXT Register ........................................................................
PRCM_RM_PER_DLL_CONTEXT Register ..........................................................................
PRCM_RM_PER_DSS_CONTEXT Register .........................................................................
PRCM_RM_PER_CPGMAC0_CONTEXT Register .................................................................
PRCM_RM_PER_OCPWP_CONTEXT Register .....................................................................
PRCM_RM_RTC_CONTEXT Register ................................................................................
PRCM_RM_WKUP_RSTCTRL Register ..............................................................................
PRCM_RM_WKUP_RSTST Register ..................................................................................
PRCM_RM_WKUP_DBGSS_CONTEXT Register ...................................................................
PRCM_RM_WKUP_ADC0_CONTEXT Register .....................................................................
PRCM_RM_WKUP_L4WKUP_CONTEXT Register .................................................................
PRCM_RM_WKUP_PROC_CONTEXT Register ....................................................................
PRCM_RM_WKUP_SYNCTIMER_CONTEXT Register ............................................................
PRCM_RM_WKUP_TIMER0_CONTEXT Register ..................................................................
PRCM_RM_WKUP_TIMER1_CONTEXT Register ..................................................................
PRCM_RM_WKUP_WDT1_CONTEXT Register .....................................................................
PRCM_RM_WKUP_I2C0_CONTEXT Register .......................................................................
PRCM_RM_WKUP_UART0_CONTEXT Register ...................................................................
PRCM_RM_WKUP_GPIO0_CONTEXT Register ....................................................................
PRCM_REVISION Register .............................................................................................
PRCM_PRM_IRQSTS_MPU Register .................................................................................
PRCM_PRM_IRQEN_MPU Register ..................................................................................
PRCM_PRM_IRQSTS_WKUP_PROC Register......................................................................
PRCM_PRM_IRQEN_WKUP_PROC Register .......................................................................
PRCM_CM_CEFUSE_CLKSTCTRL Register ........................................................................
PRCM_CM_CEFUSE_CLKCTRL Register............................................................................
PRCM_CM_CLKOUT1_CTRL Register ...............................................................................
PRCM_CM_DLL_CTRL Register .......................................................................................
PRCM_CM_CLKOUT2_CTRL Register ...............................................................................
PRCM_CM_DPLL_DPLL_CLKSEL_TIMER1_CLK Register .......................................................
PRCM_CM_DPLL_CLKSEL_TIMER2_CLK Register................................................................
PRCM_CM_DPLL_CLKSEL_TIMER3_CLK Register................................................................
PRCM_CM_DPLL_CLKSEL_TIMER4_CLK Register................................................................
PRCM_CM_DPLL_CLKSEL_TIMER5_CLK Register................................................................
PRCM_CM_DPLL_CLKSEL_TIMER6_CLK Register................................................................
PRCM_CM_DPLL_CLKSEL_TIMER7_CLK Register................................................................
PRCM_CM_DPLL_CLKSEL_TIMER8_CLK Register................................................................
PRCM_CM_DPLL_CLKSEL_TIMER9_CLK Register................................................................
6-113. PRCM_RM_PER_TIMER10_CONTEXT Register
List of Figures
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405
406
407
408
409
410
411
412
413
414
415
417
418
419
420
421
422
423
424
425
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427
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429
430
431
433
435
437
440
441
443
445
446
449
450
451
452
453
454
455
456
457
SPRUHL7I – April 2014 – Revised December 2019
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6-160. PRCM_CM_DPLL_CLKSEL_TIMER10_CLK Register .............................................................. 458
6-161. PRCM_CM_DPLL_CLKSEL_TIMER11_CLK Register .............................................................. 459
6-162. PRCM_CM_DPLL_CLKSEL_WDT1_CLK Register .................................................................. 460
6-163. PRCM_CM_DPLL_CLKSEL_SYNCTIMER_CLK Register.......................................................... 461
...................................................................
...........................................................
PRCM_CM_DPLL_CLKSEL_GFX_FCLK Register ..................................................................
PRCM_CM_DPLL_CLKSEL_GPIO0_DBCLK Register .............................................................
PRCM_CM_CLKSEL_PRU_ICSS_OCP_CLK Register .............................................................
PRCM_CM_CLKSEL_ADC1_CLK Register ..........................................................................
PRCM_CM_DPLL_CLKSEL_DLL_AGING_CLK Register ..........................................................
PRCM_CM_DPLL_CLKSEL_USBPHY32KHZ_GCLK Register ....................................................
PRCM_CM_GFX_L3_CLKSTCTRL Register .........................................................................
PRCM_CM_GFX_CLKCTRL Register .................................................................................
PRCM_CM_MPU_CLKSTCTRL Register .............................................................................
PRCM_CM_MPU_CLKCTRL Register ................................................................................
PRCM_CM_PER_L3_CLKSTCTRL Register .........................................................................
PRCM_CM_PER_L3_CLKCTRL Register ............................................................................
PRCM_CM_PER_L3_INSTR_CLKCTRL Register ...................................................................
PRCM_CM_PER_OCMCRAM_CLKCTRL Register .................................................................
PRCM_CM_PER_VPFE0_CLKCTRL Register .......................................................................
PRCM_CM_PER_VPFE1_CLKCTRL Register .......................................................................
PRCM_CM_PER_TPCC_CLKCTRL Register ........................................................................
PRCM_CM_PER_TPTC0_CLKCTRL Register .......................................................................
PRCM_CM_PER_TPTC1_CLKCTRL Register .......................................................................
PRCM_CM_PER_TPTC2_CLKCTRL Register .......................................................................
PRCM_CM_PER_DLL_AGING_CLKCTRL Register ................................................................
PRCM_CM_PER_L4HS_CLKCTRL Register .........................................................................
PRCM_CM_PER_L3S_CLKSTCTRL Register .......................................................................
PRCM_CM_PER_GPMC_CLKCTRL Register .......................................................................
PRCM_CM_PER_ADC1_CLKCTRL Register ........................................................................
PRCM_CM_PER_MCASP0_CLKCTRL Register ....................................................................
PRCM_CM_PER_MCASP1_CLKCTRL Register ....................................................................
PRCM_CM_PER_MMC2_CLKCTRL Register .......................................................................
PRCM_CM_PER_QSPI_CLKCTRL Register .........................................................................
PRCM_CM_PER_USB_OTG_SS0_CLKCTRL Register ............................................................
PRCM_CM_PER_USB_OTG_SS1_CLKCTRL Register ............................................................
PRCM_CM_PER_PRU_ICSS_CLKSTCTRL Register ..............................................................
PRCM_CM_PER_PRU_ICSS_CLKCTRL Register ..................................................................
PRCM_CM_PER_L4LS_CLKSTCTRL Register ......................................................................
PRCM_CM_PER_L4LS_CLKCTRL Register .........................................................................
PRCM_CM_PER_DCAN0_CLKCTRL Register ......................................................................
PRCM_CM_PER_DCAN1_CLKCTRL Register ......................................................................
PRCM_CM_PER_PWMSS0_CLKCTRL Register ....................................................................
PRCM_CM_PER_PWMSS1_CLKCTRL Register ....................................................................
PRCM_CM_PER_PWMSS2_CLKCTRL Register ....................................................................
PRCM_CM_PER_PWMSS3_CLKCTRL Register ....................................................................
PRCM_CM_PER_PWMSS4_CLKCTRL Register ....................................................................
PRCM_CM_PER_PWMSS5_CLKCTRL Register ....................................................................
6-164. PRCM_CM_DPLL_CLKSEL_MAC_CLK Register
462
6-165. PRCM_CM_DPLL_CLKSEL_CPTS_RFT_CLK Register
463
6-166.
464
6-167.
6-168.
6-169.
6-170.
6-171.
6-172.
6-173.
6-174.
6-175.
6-176.
6-177.
6-178.
6-179.
6-180.
6-181.
6-182.
6-183.
6-184.
6-185.
6-186.
6-187.
6-188.
6-189.
6-190.
6-191.
6-192.
6-193.
6-194.
6-195.
6-196.
6-197.
6-198.
6-199.
6-200.
6-201.
6-202.
6-203.
6-204.
6-205.
6-206.
6-207.
6-208.
SPRUHL7I – April 2014 – Revised December 2019
Submit Documentation Feedback
Copyright © 2014–2019, Texas Instruments Incorporated
List of Figures
465
466
467
468
469
470
471
473
474
477
478
479
480
481
482
483
484
485
486
487
488
489
491
492
493
494
495
496
497
498
499
500
501
504
505
506
507
508
509
510
511
512
19
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6-209. PRCM_CM_PER_ELM_CLKCTRL Register .......................................................................... 513
6-210. PRCM_CM_PER_GPIO1_CLKCTRL Register ....................................................................... 514
6-211. PRCM_CM_PER_GPIO2_CLKCTRL Register ....................................................................... 515
6-212. PRCM_CM_PER_GPIO3_CLKCTRL Register ....................................................................... 516
6-213. PRCM_CM_PER_GPIO4_CLKCTRL Register ....................................................................... 517
6-214. PRCM_CM_PER_GPIO5_CLKCTRL Register ....................................................................... 518
6-215. PRCM_CM_PER_HDQ1W_CLKCTRL Register
.....................................................................
519
6-216. PRCM_CM_PER_I2C1_CLKCTRL Register .......................................................................... 520
6-217. PRCM_CM_PER_I2C2_CLKCTRL Register .......................................................................... 521
6-218. PRCM_CM_PER_MAILBOX0_CLKCTRL Register .................................................................. 522
.......................................................................
PRCM_CM_PER_MMC1_CLKCTRL Register .......................................................................
PRCM_CM_PER_SPI0_CLKCTRL Register..........................................................................
PRCM_CM_PER_SPI1_CLKCTRL Register..........................................................................
PRCM_CM_PER_SPI2_CLKCTRL Register..........................................................................
PRCM_CM_PER_SPI3_CLKCTRL Register..........................................................................
PRCM_CM_PER_SPI4_CLKCTRL Register..........................................................................
PRCM_CM_PER_SPINLOCK_CLKCTRL Register ..................................................................
PRCM_CM_PER_TIMER2_CLKCTRL Register......................................................................
PRCM_CM_PER_TIMER3_CLKCTRL Register......................................................................
PRCM_CM_PER_TIMER4_CLKCTRL Register......................................................................
PRCM_CM_PER_TIMER5_CLKCTRL Register......................................................................
PRCM_CM_PER_TIMER6_CLKCTRL Register......................................................................
PRCM_CM_PER_TIMER7_CLKCTRL Register......................................................................
PRCM_CM_PER_TIMER8_CLKCTRL Register......................................................................
PRCM_CM_PER_TIMER9_CLKCTRL Register......................................................................
PRCM_CM_PER_TIMER10_CLKCTRL Register ....................................................................
PRCM_CM_PER_TIMER11_CLKCTRL Register ....................................................................
PRCM_CM_PER_UART1_CLKCTRL Register .......................................................................
PRCM_CM_PER_UART2_CLKCTRL Register .......................................................................
PRCM_CM_PER_UART3_CLKCTRL Register .......................................................................
PRCM_CM_PER_UART4_CLKCTRL Register .......................................................................
PRCM_CM_PER_UART5_CLKCTRL Register .......................................................................
PRCM_CM_PER_USBPHYOCP2SCP0_CLKCTRL Register ......................................................
PRCM_CM_PER_USBPHYOCP2SCP1_CLKCTRL Register ......................................................
PRCM_CM_PER_EMIF_CLKSTCTRL Register......................................................................
PRCM_CM_PER_EMIF_CLKCTRL Register .........................................................................
PRCM_CM_PER_DLL_CLKCTRL Register ..........................................................................
PRCM_CM_PER_LCDC_CLKSTCTRL Register .....................................................................
PRCM_CM_PER_DSS_CLKSTCTRL Register ......................................................................
PRCM_CM_PER_DSS_CLKCTRL Register ..........................................................................
PRCM_CM_PER_CPSW_CLKSTCTRL Register ....................................................................
PRCM_CM_PER_CPGMAC0_CLKCTRL Register ..................................................................
PRCM_CM_PER_OCPWP_L3_CLKSTCTRL Register .............................................................
PRCM_CM_PER_OCPWP_CLKCTRL Register .....................................................................
PRCM_CM_RTC_CLKSTCTRL Register .............................................................................
PRCM_CM_RTC_CLKCTRL Register .................................................................................
PRCM_CM_L3_AON_CLKSTCTRL Register .........................................................................
PRCM_CM_WKUP_DBGSS_CLKCTRL Register ...................................................................
6-219. PRCM_CM_PER_MMC0_CLKCTRL Register
6-220.
6-221.
6-222.
6-223.
6-224.
6-225.
6-226.
6-227.
6-228.
6-229.
6-230.
6-231.
6-232.
6-233.
6-234.
6-235.
6-236.
6-237.
6-238.
6-239.
6-240.
6-241.
6-242.
6-243.
6-244.
6-245.
6-246.
6-247.
6-248.
6-249.
6-250.
6-251.
6-252.
6-253.
6-254.
6-255.
6-256.
6-257.
20
List of Figures
523
524
525
526
527
528
529
530
531
532
533
534
535
536
537
538
539
540
541
542
543
544
545
546
547
548
549
550
551
552
553
554
556
557
558
559
560
563
564
SPRUHL7I – April 2014 – Revised December 2019
Submit Documentation Feedback
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www.ti.com
.......................................................................
PRCM_CM_L3S_ADC0_CLKSTCTRL Register......................................................................
PRCM_CM_WKUP_ADC_TSC_CLKCTRL Register ................................................................
PRCM_CM_WKUP_ADC0_CLKCTRL Register ......................................................................
PRCM_CM_L4_WKUP_AON_CLKSTCTRL Register ...............................................................
PRCM_CM_WKUP_L4WKUP_CLKCTRL Register ..................................................................
PRCM_CM_WKUP_M3_CLKCTRL Register .........................................................................
PRCM_CM_WKUP_PROC_CLKCTRL Register .....................................................................
PRCM_CM_WKUP_SYNCTIMER_CLKCTRL Register .............................................................
PRCM_CM_WKUP_CLKDIV32K_CLKCTRL Register ..............................................................
PRCM_CM_WKUP_USBPHY0_CLKCTRL Register ................................................................
PRCM_CM_WKUP_USBPHY1_CLKCTRL Register ................................................................
PRCM_CM_WKUP_CLKSTCTRL Register ...........................................................................
PRCM_CM_WKUP_TIMER0_CLKCTRL Register ...................................................................
PRCM_CM_WKUP_TIMER1_CLKCTRL Register ...................................................................
PRCM_CM_WKUP_WDT0_CLKCTRL Register .....................................................................
PRCM_CM_WKUP_WDT1_CLKCTRL Register .....................................................................
PRCM_CM_WKUP_I2C0_CLKCTRL Register .......................................................................
PRCM_CM_WKUP_UART0_CLKCTRL Register ....................................................................
PRCM_CM_WKUP_CTRL_CLKCTRL Register ......................................................................
PRCM_CM_WKUP_GPIO0_CLKCTRL Register .....................................................................
PRCM_CM_CLKMODE_DPLL_CORE Register .....................................................................
PRCM_CM_IDLEST_DPLL_CORE Register .........................................................................
PRCM_CM_CLKSEL_DPLL_CORE Register ........................................................................
PRCM_CM_DIV_M4_DPLL_CORE Register .........................................................................
PRCM_CM_DIV_M5_DPLL_CORE Register .........................................................................
PRCM_CM_DIV_M6_DPLL_CORE Register .........................................................................
PRCM_CM_SSC_DELTAMSTEP_DPLL_CORE Register ..........................................................
PRCM_CM_SSC_MODFREQDIV_DPLL_CORE Register .........................................................
PRCM_CM_CLKMODE_DPLL_MPU Register .......................................................................
PRCM_CM_IDLEST_DPLL_MPU Register ...........................................................................
PRCM_CM_CLKSEL_DPLL_MPU Register ..........................................................................
PRCM_CM_DIV_M2_DPLL_MPU Register ...........................................................................
PRCM_CM_SSC_DELTAMSTEP_DPLL_MPU Register ...........................................................
PRCM_CM_SSC_MODFREQDIV_DPLL_MPU Register ...........................................................
PRCM_CM_CLKMODE_DPLL_DDR Register .......................................................................
PRCM_CM_IDLEST_DPLL_DDR Register ...........................................................................
PRCM_CM_CLKSEL_DPLL_DDR Register ..........................................................................
PRCM_CM_DIV_M2_DPLL_DDR Register ...........................................................................
PRCM_CM_DIV_M4_DPLL_DDR Register ...........................................................................
PRCM_CM_SSC_DELTAMSTEP_DPLL_DDR Register ............................................................
PRCM_CM_SSC_MODFREQDIV_DPLL_DDR Register ...........................................................
PRCM_CM_CLKMODE_DPLL_PER Register ........................................................................
PRCM_CM_IDLEST_DPLL_PER Register............................................................................
PRCM_CM_CLKSEL_DPLL_PER Register ...........................................................................
PRCM_CM_DIV_M2_DPLL_PER Register ...........................................................................
PRCM_CM_CLKSEL2_DPLL_PER Register .........................................................................
PRCM_CM_SSC_DELTAMSTEP_DPLL_PER Register ............................................................
PRCM_CM_SSC_MODFREQDIV_DPLL_PER Register ............................................................
6-258. PRCM_CM_L3S_TSC_CLKSTCTRL Register
566
6-259.
567
6-260.
6-261.
6-262.
6-263.
6-264.
6-265.
6-266.
6-267.
6-268.
6-269.
6-270.
6-271.
6-272.
6-273.
6-274.
6-275.
6-276.
6-277.
6-278.
6-279.
6-280.
6-281.
6-282.
6-283.
6-284.
6-285.
6-286.
6-287.
6-288.
6-289.
6-290.
6-291.
6-292.
6-293.
6-294.
6-295.
6-296.
6-297.
6-298.
6-299.
6-300.
6-301.
6-302.
6-303.
6-304.
6-305.
6-306.
SPRUHL7I – April 2014 – Revised December 2019
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Copyright © 2014–2019, Texas Instruments Incorporated
List of Figures
568
569
570
571
572
573
574
575
576
577
578
580
581
582
583
584
585
586
587
588
590
591
592
593
594
595
596
597
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600
601
602
603
604
606
607
608
609
610
611
612
613
614
615
616
617
618
21
www.ti.com
6-307. PRCM_CM_CLKDCOLDO_DPLL_PER Register .................................................................... 619
6-308. PRCM_CM_CLKMODE_DPLL_DISP Register ....................................................................... 620
6-309. PRCM_CM_IDLEST_DPLL_DISP Register ........................................................................... 622
6-310. PRCM_CM_CLKSEL_DPLL_DISP Register .......................................................................... 623
6-311. PRCM_CM_DIV_M2_DPLL_DISP Register
..........................................................................
624
6-312. PRCM_CM_SSC_DELTAMSTEP_DPLL_DISP Register ........................................................... 625
6-313. PRCM_CM_SSC_MODFREQDIV_DPLL_DISP Register ........................................................... 626
6-314. PRCM_CM_CLKMODE_DPLL_EXTDEV Register
..................................................................
627
6-315. PRCM_CM_IDLEST_DPLL_EXTDEV Register ...................................................................... 628
6-316. PRCM_CM_CLKSEL_DPLL_EXTDEV Register
.....................................................................
629
6-317. PRCM_CM_DIV_M2_DPLL_EXTDEV Register ...................................................................... 630
6-318. PRCM_CM_CLKSEL2_DPLL_EXTDEV Register .................................................................... 631
6-319. PRCM_CM_SSC_DELTAMSTEP_DPLL_EXTDEV Register ....................................................... 632
633
6-321.
634
6-322.
7-1.
7-2.
7-3.
7-4.
7-5.
7-6.
7-7.
7-8.
7-9.
7-10.
7-11.
7-12.
7-13.
7-14.
7-15.
7-16.
7-17.
7-18.
7-19.
7-20.
7-21.
7-22.
7-23.
7-24.
7-25.
7-26.
7-27.
7-28.
7-29.
7-30.
7-31.
7-32.
7-33.
22
......................................................
PRCM_CM_SHADOW_FREQ_CONFIG1 Register ..................................................................
PRCM_CM_SHADOW_FREQ_CONFIG2 Register ..................................................................
Event Crossbar ............................................................................................................
USB Charger Detection ..................................................................................................
ADC0 External Hardware Events .......................................................................................
ADC1 External Hardware Events .......................................................................................
CTRL_REVISION Register ..............................................................................................
CTRL_HWINFO Register ................................................................................................
CTRL_SYSCONFIG Register ...........................................................................................
CTRL_STS Register ......................................................................................................
CTRL_MPU_L2 Register ................................................................................................
CTRL_CORE_SLDO Register ..........................................................................................
CTRL_MPU_SLDO Register ............................................................................................
CTRL_CLK32KDIVRATIO Register ....................................................................................
CTRL_BANDGAP Register ..............................................................................................
CTRL_BANDGAP_TRIM Register......................................................................................
CTRL_PLL_CLKINPULOW Register ...................................................................................
CTRL_MOSC Register ...................................................................................................
CTRL_DEEPSLEEP Register ...........................................................................................
CTRL_DPLL_PWR_SW_STS Register ................................................................................
CTRL_DISPLAY_PLL_SEL Register...................................................................................
CTRL_DEVICE_ID Register .............................................................................................
CTRL_DEV_FEATURE Register .......................................................................................
CTRL_INIT_PRIORITY_0 Register.....................................................................................
CTRL_INIT_PRIORITY_1 Register.....................................................................................
CTRL_DEV_ATTR Register .............................................................................................
CTRL_TPTC_CFG Register .............................................................................................
CTRL_USB_CTRL0 Register ...........................................................................................
CTRL_USB_STS0 Register .............................................................................................
CTRL_USB_CTRL1 Register ...........................................................................................
CTRL_USB_STS1 Register .............................................................................................
CTRL_MAC_ID0_LO Register ..........................................................................................
CTRL_MAC_ID0_HI Register ...........................................................................................
CTRL_MAC_ID1_LO Register ..........................................................................................
CTRL_MAC_ID1_HI Register ...........................................................................................
6-320. PRCM_CM_SSC_MODFREQDIV_DPLL_EXTDEV Register
List of Figures
636
640
643
646
647
656
657
658
659
661
662
663
664
665
666
667
668
669
670
671
672
673
674
675
676
677
678
680
681
683
684
685
686
687
SPRUHL7I – April 2014 – Revised December 2019
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www.ti.com
7-34.
CTRL_DCAN_RAMINIT Register ....................................................................................... 688
7-35.
CTRL_USB_CTRL2 Register ........................................................................................... 689
7-36.
CTRL_GMII_SEL Register
7-37.
CTRL_MPUSS Register ................................................................................................. 692
7-38.
CTRL_TIMER_CASCADE Register .................................................................................... 693
7-39.
CTRL_PWMSS Register ................................................................................................. 694
7-40.
CTRL_MREQPRIO_0 Register ......................................................................................... 695
7-41.
CTRL_MREQPRIO_1 Register ......................................................................................... 696
7-42.
CTRL_VDD_MPU_OPP_050 Register
7-43.
7-44.
7-45.
7-46.
7-47.
7-48.
7-49.
7-50.
7-51.
7-52.
7-53.
7-54.
7-55.
7-56.
7-57.
7-58.
7-59.
7-60.
7-61.
7-62.
7-63.
7-64.
7-65.
7-66.
7-67.
7-68.
7-69.
7-70.
7-71.
7-72.
7-73.
7-74.
7-75.
7-76.
7-77.
7-78.
7-79.
7-80.
7-81.
7-82.
..............................................................................................
................................................................................
CTRL_VDD_MPU_OPP_100 Register ................................................................................
CTRL_VDD_MPU_OPP_120 Register ................................................................................
CTRL_VDD_MPU_OPP_TURBO Register............................................................................
CTRL_VDD_MPU_OPP_NITRO Register.............................................................................
CTRL_VDD_CORE_OPP_050 Register ...............................................................................
CTRL_VDD_CORE_OPP_100 Register ...............................................................................
CTRL_USB_VID_PID Register .........................................................................................
CTRL_CONF_GPMC_AD0 Register ...................................................................................
CTRL_CONF_GPMC_AD1 Register ...................................................................................
CTRL_CONF_GPMC_AD2 Register ...................................................................................
CTRL_CONF_GPMC_AD3 Register ...................................................................................
CTRL_CONF_GPMC_AD4 Register ...................................................................................
CTRL_CONF_GPMC_AD5 Register ...................................................................................
CTRL_CONF_GPMC_AD6 Register ...................................................................................
CTRL_CONF_GPMC_AD7 Register ...................................................................................
CTRL_CONF_GPMC_AD8 Register ...................................................................................
CTRL_CONF_GPMC_AD9 Register ...................................................................................
CTRL_CONF_GPMC_AD10 Register .................................................................................
CTRL_CONF_GPMC_AD11 Register .................................................................................
CTRL_CONF_GPMC_AD12 Register .................................................................................
CTRL_CONF_GPMC_AD13 Register .................................................................................
CTRL_CONF_GPMC_AD14 Register .................................................................................
CTRL_CONF_GPMC_AD15 Register .................................................................................
CTRL_CONF_GPMC_A0 Register .....................................................................................
CTRL_CONF_GPMC_A1 Register .....................................................................................
CTRL_CONF_GPMC_A2 Register .....................................................................................
CTRL_CONF_GPMC_A3 Register .....................................................................................
CTRL_CONF_GPMC_A4 Register .....................................................................................
CTRL_CONF_GPMC_A5 Register .....................................................................................
CTRL_CONF_GPMC_A6 Register .....................................................................................
CTRL_CONF_GPMC_A7 Register .....................................................................................
CTRL_CONF_GPMC_A8 Register .....................................................................................
CTRL_CONF_GPMC_A9 Register .....................................................................................
CTRL_CONF_GPMC_A10 Register ...................................................................................
CTRL_CONF_GPMC_A11 Register ...................................................................................
CTRL_CONF_GPMC_WAIT0 Register ................................................................................
CTRL_CONF_GPMC_WPN Register ..................................................................................
CTRL_CONF_GPMC_BE1N Register .................................................................................
CTRL_CONF_GPMC_CSN0 Register .................................................................................
CTRL_CONF_GPMC_CSN1 Register .................................................................................
SPRUHL7I – April 2014 – Revised December 2019
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Copyright © 2014–2019, Texas Instruments Incorporated
List of Figures
691
697
698
699
700
701
702
703
704
705
707
709
711
713
715
717
719
721
723
725
727
729
731
733
735
737
739
741
743
745
747
749
751
753
755
757
759
761
763
765
767
769
23
www.ti.com
7-83.
CTRL_CONF_GPMC_CSN2 Register ................................................................................. 771
7-84.
CTRL_CONF_GPMC_CSN3 Register ................................................................................. 773
7-85.
CTRL_CONF_GPMC_CLK Register ................................................................................... 775
7-86.
CTRL_CONF_GPMC_ADVN_ALE Register .......................................................................... 777
7-87.
CTRL_CONF_GPMC_OEN_REN Register ........................................................................... 779
7-88.
CTRL_CONF_GPMC_WEN Register .................................................................................. 781
7-89.
CTRL_CONF_GPMC_BE0N_CLE Register
7-90.
CTRL_CONF_DSS_DATA0 Register .................................................................................. 785
7-91.
CTRL_CONF_DSS_DATA1 Register .................................................................................. 787
7-92.
CTRL_CONF_DSS_DATA2 Register .................................................................................. 789
7-93.
CTRL_CONF_DSS_DATA3 Register .................................................................................. 791
7-94.
CTRL_CONF_DSS_DATA4 Register .................................................................................. 793
7-95.
CTRL_CONF_DSS_DATA5 Register .................................................................................. 795
7-96.
CTRL_CONF_DSS_DATA6 Register .................................................................................. 797
7-97.
CTRL_CONF_DSS_DATA7 Register .................................................................................. 799
7-98.
CTRL_CONF_DSS_DATA8 Register .................................................................................. 801
7-99.
CTRL_CONF_DSS_DATA9 Register .................................................................................. 803
................................................................................
................................................................................
CTRL_CONF_DSS_DATA12 Register ................................................................................
CTRL_CONF_DSS_DATA13 Register ................................................................................
CTRL_CONF_DSS_DATA14 Register ................................................................................
CTRL_CONF_DSS_DATA15 Register ................................................................................
CTRL_CONF_DSS_VSYNC Register .................................................................................
CTRL_CONF_DSS_HSYNC Register .................................................................................
CTRL_CONF_DSS_PCLK Register ....................................................................................
CTRL_CONF_DSS_AC_BIAS_EN Register ..........................................................................
CTRL_CONF_MMC0_DAT3 Register .................................................................................
CTRL_CONF_MMC0_DAT2 Register .................................................................................
CTRL_CONF_MMC0_DAT1 Register .................................................................................
CTRL_CONF_MMC0_DAT0 Register .................................................................................
CTRL_CONF_MMC0_CLK Register ...................................................................................
CTRL_CONF_MMC0_CMD Register ..................................................................................
CTRL_CONF_MII1_COL Register .....................................................................................
CTRL_CONF_MII1_CRS Register .....................................................................................
CTRL_CONF_MII1_RXERR Register..................................................................................
CTRL_CONF_MII1_TXEN Register ....................................................................................
CTRL_CONF_MII1_RXDV Register ...................................................................................
CTRL_CONF_MII1_TXD3 Register ....................................................................................
CTRL_CONF_MII1_TXD2 Register ....................................................................................
CTRL_CONF_MII1_TXD1 Register ....................................................................................
CTRL_CONF_MII1_TXD0 Register ....................................................................................
CTRL_CONF_MII1_TXCLK Register ..................................................................................
CTRL_CONF_MII1_RXCLK Register ..................................................................................
CTRL_CONF_MII1_RXD3 Register ....................................................................................
CTRL_CONF_MII1_RXD2 Register ....................................................................................
CTRL_CONF_MII1_RXD1 Register ....................................................................................
CTRL_CONF_MII1_RXD0 Register ....................................................................................
CTRL_CONF_RMII1_REFCLK Register ..............................................................................
783
7-100. CTRL_CONF_DSS_DATA10 Register
805
7-101. CTRL_CONF_DSS_DATA11 Register
807
7-102.
809
7-103.
7-104.
7-105.
7-106.
7-107.
7-108.
7-109.
7-110.
7-111.
7-112.
7-113.
7-114.
7-115.
7-116.
7-117.
7-118.
7-119.
7-120.
7-121.
7-122.
7-123.
7-124.
7-125.
7-126.
7-127.
7-128.
7-129.
7-130.
7-131.
24
..........................................................................
List of Figures
811
813
815
817
819
821
823
825
827
829
831
833
835
837
839
841
843
845
847
849
851
853
855
857
859
861
863
865
867
SPRUHL7I – April 2014 – Revised December 2019
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7-132. CTRL_CONF_MDIO_DATA Register .................................................................................. 869
7-133. CTRL_CONF_MDIO_CLK Register .................................................................................... 871
7-134. CTRL_CONF_SPI0_SCLK Register
...................................................................................
873
7-135. CTRL_CONF_SPI0_D0 Register ....................................................................................... 875
7-136. CTRL_CONF_SPI0_D1 Register ....................................................................................... 877
7-137. CTRL_CONF_SPI0_CS0 Register ..................................................................................... 879
7-138. CTRL_CONF_SPI0_CS1 Register ..................................................................................... 881
7-139. CTRL_CONF_ECAP0_IN_PWM0_OUT Register .................................................................... 882
7-140. CTRL_CONF_UART0_CTSN Register ................................................................................ 883
7-141. CTRL_CONF_UART0_RTSN Register ................................................................................ 885
7-142. CTRL_CONF_UART0_RXD Register .................................................................................. 887
7-143. CTRL_CONF_UART0_TXD Register .................................................................................. 889
7-144. CTRL_CONF_UART1_CTSN Register ................................................................................ 891
7-145. CTRL_CONF_UART1_RTSN Register ................................................................................ 893
7-146. CTRL_CONF_UART1_RXD Register .................................................................................. 895
7-147. CTRL_CONF_UART1_TXD Register .................................................................................. 897
7-148. CTRL_CONF_I2C0_SDA Register ..................................................................................... 899
7-149. CTRL_CONF_I2C0_SCL Register ..................................................................................... 900
7-150. CTRL_CONF_MCASP0_ACLKX Register ............................................................................ 901
7-151. CTRL_CONF_MCASP0_FSX Register ................................................................................ 903
7-152. CTRL_CONF_MCASP0_AXR0 Register .............................................................................. 905
7-153. CTRL_CONF_MCASP0_AHCLKR Register .......................................................................... 907
7-154. CTRL_CONF_MCASP0_ACLKR Register ............................................................................ 909
7-155. CTRL_CONF_MCASP0_FSR Register ................................................................................ 911
7-156. CTRL_CONF_MCASP0_AXR1 Register .............................................................................. 913
..........................................................................
CTRL_CONF_CAM0_HD Register .....................................................................................
CTRL_CONF_CAM0_VD Register .....................................................................................
CTRL_CONF_CAM0_FIELD Register .................................................................................
CTRL_CONF_CAM0_WEN Register ..................................................................................
CTRL_CONF_CAM0_PCLK Register ..................................................................................
CTRL_CONF_CAM0_DATA8 Register ................................................................................
CTRL_CONF_CAM0_DATA9 Register ................................................................................
CTRL_CONF_CAM1_DATA9 Register ................................................................................
CTRL_CONF_CAM1_DATA8 Register ................................................................................
CTRL_CONF_CAM1_HD Register .....................................................................................
CTRL_CONF_CAM1_VD Register .....................................................................................
CTRL_CONF_CAM1_PCLK Register ..................................................................................
CTRL_CONF_CAM1_FIELD Register .................................................................................
CTRL_CONF_CAM1_WEN Register ..................................................................................
CTRL_CONF_CAM1_DATA0 Register ................................................................................
CTRL_CONF_CAM1_DATA1 Register ................................................................................
CTRL_CONF_CAM1_DATA2 Register ................................................................................
CTRL_CONF_CAM1_DATA3 Register ................................................................................
CTRL_CONF_CAM1_DATA4 Register ................................................................................
CTRL_CONF_CAM1_DATA5 Register ................................................................................
CTRL_CONF_CAM1_DATA6 Register ................................................................................
CTRL_CONF_CAM1_DATA7 Register ................................................................................
CTRL_CONF_CAM0_DATA0 Register ................................................................................
7-157. CTRL_CONF_MCASP0_AHCLKX Register
915
7-158.
917
7-159.
7-160.
7-161.
7-162.
7-163.
7-164.
7-165.
7-166.
7-167.
7-168.
7-169.
7-170.
7-171.
7-172.
7-173.
7-174.
7-175.
7-176.
7-177.
7-178.
7-179.
7-180.
SPRUHL7I – April 2014 – Revised December 2019
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Copyright © 2014–2019, Texas Instruments Incorporated
List of Figures
919
921
923
925
927
929
931
933
935
937
939
941
943
945
947
949
951
953
955
957
959
961
25
www.ti.com
7-181. CTRL_CONF_CAM0_DATA1 Register ................................................................................ 963
7-182. CTRL_CONF_CAM0_DATA2 Register ................................................................................ 965
7-183. CTRL_CONF_CAM0_DATA3 Register ................................................................................ 967
7-184. CTRL_CONF_CAM0_DATA4 Register ................................................................................ 969
7-185. CTRL_CONF_CAM0_DATA5 Register ................................................................................ 971
7-186. CTRL_CONF_CAM0_DATA6 Register ................................................................................ 973
7-187. CTRL_CONF_CAM0_DATA7 Register ................................................................................ 975
7-188. CTRL_CONF_UART3_RXD Register .................................................................................. 977
7-189. CTRL_CONF_UART3_TXD Register .................................................................................. 979
7-190. CTRL_CONF_UART3_CTSN Register ................................................................................ 981
7-191. CTRL_CONF_UART3_RTSN Register ................................................................................ 983
...................................................................................... 985
...................................................................................... 987
CTRL_CONF_GPIO5_10 Register ..................................................................................... 989
CTRL_CONF_GPIO5_11 Register ..................................................................................... 991
CTRL_CONF_GPIO5_12 Register ..................................................................................... 993
CTRL_CONF_GPIO5_13 Register ..................................................................................... 995
CTRL_CONF_SPI4_SCLK Register ................................................................................... 997
CTRL_CONF_SPI4_D0 Register ....................................................................................... 999
CTRL_CONF_SPI4_D1 Register ..................................................................................... 1001
CTRL_CONF_SPI4_CS0 Register .................................................................................... 1003
CTRL_CONF_SPI2_SCLK Register .................................................................................. 1005
CTRL_CONF_SPI2_D0 Register ..................................................................................... 1007
CTRL_CONF_SPI2_D1 Register ..................................................................................... 1009
CTRL_CONF_SPI2_CS0 Register .................................................................................... 1011
CTRL_CONF_XDMA_EVT_INTR0 Register ........................................................................ 1013
CTRL_CONF_XDMA_EVT_INTR1 Register ........................................................................ 1014
CTRL_CONF_CLKREQ Register ..................................................................................... 1015
CTRL_CONF_NRESETIN_OUT Register ........................................................................... 1016
CTRL_CONF_NNMI Register ......................................................................................... 1017
CTRL_CONF_TMS Register........................................................................................... 1018
CTRL_CONF_TDI Register ............................................................................................ 1019
CTRL_CONF_TDO Register........................................................................................... 1020
CTRL_CONF_TCK Register ........................................................................................... 1021
CTRL_CONF_NTRST Register ....................................................................................... 1022
CTRL_CONF_EMU0 Register ......................................................................................... 1023
CTRL_CONF_EMU1 Register ......................................................................................... 1024
CTRL_CONF_OSC1_IN Register ..................................................................................... 1025
CTRL_CONF_OSC1_OUT Register .................................................................................. 1026
CTRL_CONF_RTC_PORZ Register .................................................................................. 1027
CTRL_CONF_EXT_WAKEUP0 Register ............................................................................ 1028
CTRL_CONF_PMIC_POWER_EN0 Register ....................................................................... 1029
CTRL_CONF_USB0_DRVVBUS Register ........................................................................... 1030
CTRL_CONF_USB1_DRVVBUS Register ........................................................................... 1032
CTRL_CQDETECT_STS Register .................................................................................... 1034
CTRL_DDR_IO Register ............................................................................................... 1036
CTRL_CQDETECT_STS2 Register .................................................................................. 1037
CTRL_VTP Register .................................................................................................... 1038
CTRL_VREF Register .................................................................................................. 1039
7-192. CTRL_CONF_GPIO5_8 Register
7-193. CTRL_CONF_GPIO5_9 Register
7-194.
7-195.
7-196.
7-197.
7-198.
7-199.
7-200.
7-201.
7-202.
7-203.
7-204.
7-205.
7-206.
7-207.
7-208.
7-209.
7-210.
7-211.
7-212.
7-213.
7-214.
7-215.
7-216.
7-217.
7-218.
7-219.
7-220.
7-221.
7-222.
7-223.
7-224.
7-225.
7-226.
7-227.
7-228.
7-229.
26
List of Figures
SPRUHL7I – April 2014 – Revised December 2019
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7-230. CTRL_TPCC_EVT_MUX_0_3 Register .............................................................................. 1040
7-231. CTRL_TPCC_EVT_MUX_4_7 Register .............................................................................. 1041
7-232. CTRL_TPCC_EVT_MUX_8_11 Register ............................................................................ 1042
7-233. CTRL_TPCC_EVT_MUX_12_15 Register ........................................................................... 1043
7-234. CTRL_TPCC_EVT_MUX_16_19 Register ........................................................................... 1044
7-235. CTRL_TPCC_EVT_MUX_20_23 Register ........................................................................... 1045
7-236. CTRL_TPCC_EVT_MUX_24_27 Register ........................................................................... 1046
7-237. CTRL_TPCC_EVT_MUX_28_31 Register ........................................................................... 1047
7-238. CTRL_TPCC_EVT_MUX_32_35 Register ........................................................................... 1048
7-239. CTRL_TPCC_EVT_MUX_36_39 Register ........................................................................... 1049
7-240. CTRL_TPCC_EVT_MUX_40_43 Register ........................................................................... 1050
7-241. CTRL_TPCC_EVT_MUX_44_47 Register ........................................................................... 1051
7-242. CTRL_TPCC_EVT_MUX_48_51 Register ........................................................................... 1052
7-243. CTRL_TPCC_EVT_MUX_52_55 Register ........................................................................... 1053
7-244. CTRL_TPCC_EVT_MUX_56_59 Register ........................................................................... 1054
7-245. CTRL_TPCC_EVT_MUX_60_63 Register ........................................................................... 1055
7-246. CTRL_TIMER_EVT_CAPT Register.................................................................................. 1056
7-247. CTRL_ECAP_EVT_CAPT Register................................................................................... 1057
7-248. CTRL_ADC0_EVT_CAPT Register ................................................................................... 1058
7-249. CTRL_ADC1_EVT_CAPT Register ................................................................................... 1059
7-250. CTRL_RESET_ISO Register .......................................................................................... 1060
7-251. CTRL_DPLL_PWR_SW Register ..................................................................................... 1061
7-252. CTRL_DDR_CKE Register
............................................................................................
1063
7-253. CTRL_VSLDO Register ................................................................................................ 1064
7-254. CTRL_WAKEPROC_TXEV_EOI Register ........................................................................... 1065
....................................................................................
CTRL_IPC_MSG_REG1 Register ....................................................................................
CTRL_IPC_MSG_REG2 Register ....................................................................................
CTRL_IPC_MSG_REG3 Register ....................................................................................
CTRL_IPC_MSG_REG4 Register ....................................................................................
CTRL_IPC_MSG_REG5 Register ....................................................................................
CTRL_IPC_MSG_REG6 Register ....................................................................................
CTRL_IPC_MSG_REG7 Register ....................................................................................
CTRL_IPC_MSG_REG8 Register ....................................................................................
CTRL_IPC_MSG_REG9 Register ....................................................................................
CTRL_IPC_MSG_REG10 Register ...................................................................................
CTRL_IPC_MSG_REG11 Register ...................................................................................
CTRL_IPC_MSG_REG12 Register ...................................................................................
CTRL_IPC_MSG_REG13 Register ...................................................................................
CTRL_IPC_MSG_REG14 Register ...................................................................................
CTRL_IPC_INTR Register .............................................................................................
CTRL_DPLL_PWR_SW_CTRL2 Register ...........................................................................
CTRL_DPLL_PWR_SW_STS2 Register .............................................................................
CTRL_RESET_MISC Register ........................................................................................
CTRL_DDR_ADDRCTRL_IOCTRL Register ........................................................................
CTRL_DDR_ADDRCTRL_WD0_IOCTRL Register ................................................................
CTRL_DDR_ADDRCTRL_WD1_IOCTRL Register ................................................................
CTRL_DDR_DATA0_IOCTRL Register ..............................................................................
CTRL_DDR_DATA1_IOCTRL Register ..............................................................................
7-255. CTRL_IPC_MSG_REG0 Register
1066
7-256.
1067
7-257.
7-258.
7-259.
7-260.
7-261.
7-262.
7-263.
7-264.
7-265.
7-266.
7-267.
7-268.
7-269.
7-270.
7-271.
7-272.
7-273.
7-274.
7-275.
7-276.
7-277.
7-278.
SPRUHL7I – April 2014 – Revised December 2019
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Copyright © 2014–2019, Texas Instruments Incorporated
List of Figures
1068
1069
1070
1071
1072
1073
1074
1075
1076
1077
1078
1079
1080
1081
1082
1083
1084
1085
1086
1087
1088
1090
27
www.ti.com
7-279. CTRL_DDR_DATA2_IOCTRL Register .............................................................................. 1092
7-280. CTRL_DDR_DATA3_IOCTRL Register .............................................................................. 1094
7-281. CTRL_EMIF_SDRAM_CONFIG_EXT Register ..................................................................... 1096
7-282. CTRL_EMIF_SDRAM_STS_EXT Register .......................................................................... 1098
1099
7-284. CTRL_DISPPLL_TEN Register
1101
7-285.
7-286.
7-287.
7-288.
7-289.
7-290.
7-291.
7-292.
7-293.
9-1.
9-2.
9-3.
9-4.
9-5.
9-6.
9-7.
9-8.
1102
1103
1104
1105
1106
1107
1108
1109
1110
1121
1122
1126
1127
1127
1132
1135
1137
9-9.
Read to Read for an Address-Data Multiplexed Device, On Different CS, Without Bus Turnaround (CS0n
Attached to Fast Device) ............................................................................................... 1139
9-10.
Read to Read / Write for an Address-Data Multiplexed Device, On Different CS, With Bus Turnaround ... 1139
9-11.
Read to Read / Write for a Address-Data or AAD-Multiplexed Device, On Same CS, With Bus
Turnaround ............................................................................................................... 1140
9-12.
Asynchronous Single Read Operation on an Address/Data Multiplexed Device ............................... 1149
9-13.
Two Asynchronous Single Read Accesses on an Address/Data Multiplexed Device (32-Bit Read Split
Into 2 × 16-Bit Read).................................................................................................... 1150
9-14.
Asynchronous Single Write on an Address/Data-Multiplexed Device ............................................ 1151
9-15.
Asynchronous Single-Read on an AAD-Multiplexed Device
9-16.
9-17.
9-18.
9-19.
9-20.
9-21.
9-22.
9-23.
9-24.
9-25.
9-26.
9-27.
9-28.
9-29.
9-30.
9-31.
9-32.
28
................................................................................
.......................................................................................
CTRL_DISPPLL_TENIV Register .....................................................................................
CTRL_DISPPLL_M2NDIV Register...................................................................................
CTRL_DISPPLL_MN2DIV Register...................................................................................
CTRL_DISPPLL_FRACDIV Register .................................................................................
CTRL_DISPPLL_BWCTRL Register .................................................................................
CTRL_DISPPLL_FRACCTRL Register ..............................................................................
CTRL_DISPPLL_STS Register........................................................................................
CTRL_DISPPLL_M3DIV Register.....................................................................................
CTRL_DISPPLL_RAMPCTRL Register ..............................................................................
GPMC Block Diagram ..................................................................................................
GPMC Integration .......................................................................................................
GPMC to 16-Bit Address/Data-Multiplexed Memory................................................................
GPMC to 16-Bit Non-multiplexed Memory ...........................................................................
GPMC to 8-Bit NAND Device ..........................................................................................
Chip-Select Address Mapping and Decoding Mask ................................................................
Wait Behavior During an Asynchronous Single Read Access (GPMCFCLKDivider = 1) ......................
Wait Behavior During a Synchronous Read Burst Access ........................................................
7-283. CTRL_DISPPLL_CLKCTRL Register
......................................................
Asynchronous Single Write on an AAD-Multiplexed Device .......................................................
Synchronous Single Read (GPMCFCLKDIVIDER = 0) ............................................................
Synchronous Single Read (GPMCFCLKDIVIDER = 1) ............................................................
Synchronous Multiple (Burst) Read (GPMCFCLKDIVIDER = 0)..................................................
Synchronous Multiple (Burst) Read (GPMCFCLKDIVIDER = 1)..................................................
Synchronous Single Write on an Address/Data-Multiplexed Device .............................................
Synchronous Multiple Write (Burst Write) in Address/Data-Multiplexed Mode ..................................
Synchronous Multiple Write (Burst Write) in Address/Address/Data-Multiplexed Mode .......................
Asynchronous Single Read on an Address/Data-Nonmultiplexed Device .......................................
Asynchronous Single Write on an Address/Data-Nonmultiplexed Device .......................................
Asynchronous Multiple (Page Mode) Read ..........................................................................
NAND Command Latch Cycle .........................................................................................
NAND Address Latch Cycle ...........................................................................................
NAND Data Read Cycle ................................................................................................
NAND Data Write Cycle ................................................................................................
Hamming Code Accumulation Algorithm (1 of 2) ...................................................................
Hamming Code Accumulation Algorithm (2 of 2) ...................................................................
List of Figures
1152
1154
1156
1157
1159
1160
1161
1162
1163
1165
1166
1167
1172
1173
1174
1175
1179
1180
SPRUHL7I – April 2014 – Revised December 2019
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9-33.
ECC Computation for a 256-Byte Data Stream (Read or Write) .................................................. 1180
9-34.
ECC Computation for a 512-Byte Data Stream (Read or Write) .................................................. 1181
9-35.
128 Word16 ECC Computation
1182
9-36.
256 Word16 ECC Computation
1182
9-37.
9-38.
9-39.
9-40.
9-41.
9-42.
9-43.
9-44.
9-45.
9-46.
9-47.
9-48.
9-49.
9-50.
9-51.
9-52.
9-53.
9-54.
9-55.
9-56.
9-57.
9-58.
9-59.
9-60.
9-61.
9-62.
9-63.
9-64.
9-65.
9-66.
9-67.
9-68.
9-69.
9-70.
9-71.
9-72.
9-73.
9-74.
9-75.
9-76.
9-77.
9-78.
9-79.
9-80.
9-81.
.......................................................................................
.......................................................................................
Manual Mode Sequence and Mapping ...............................................................................
NAND Page Mapping and ECC: Per-Sector Schemes.............................................................
NAND Page Mapping and ECC: Pooled Spare Schemes .........................................................
NAND Page Mapping and ECC: Per-Sector Schemes, with Separate ECC ....................................
NAND Read Cycle Optimization Timing Description ...............................................................
Programming Model Top-Level Diagram .............................................................................
NOR Interfacing Timing Parameters Diagram .......................................................................
GPMC Connection to an External NOR Flash Memory ............................................................
Synchronous Burst Read Access (Timing Parameters in Clock Cycles) ........................................
Asynchronous Single Read Access (Timing Parameters in Clock Cycles) ......................................
Asynchronous Single Write Access (Timing Parameters in Clock Cycles) ......................................
GPMC_REVISION Register ...........................................................................................
GPMC_SYSCONFIG Register ........................................................................................
GPMC_SYSSTATUS Register ........................................................................................
GPMC_IRQSTATUS Register .........................................................................................
GPMC_IRQENABLE Register .........................................................................................
GPMC_TIMEOUT_CONTROL Register .............................................................................
GPMC_ERR_ADDRESS Register ....................................................................................
GPMC_ERR_TYPE Register ..........................................................................................
GPMC_CONFIG Register ..............................................................................................
GPMC_STATUS Register ..............................................................................................
GPMC_CONFIG1_i Register ..........................................................................................
GPMC_CONFIG2_i Register ..........................................................................................
GPMC_CONFIG3_i Register ..........................................................................................
GPMC_CONFIG4_i Register ..........................................................................................
GPMC_CONFIG5_i Register ..........................................................................................
GPMC_CONFIG6_i Register ..........................................................................................
GPMC_CONFIG7_i Register ..........................................................................................
GPMC_NAND_COMMAND_i Register ...............................................................................
GPMC_NAND_ADDRESS_i Register ................................................................................
GPMC_NAND_DATA_i Register ......................................................................................
GPMC_PREFETCH_CONFIG1 Register ............................................................................
GPMC_PREFETCH_CONFIG2 Register ............................................................................
GPMC_PREFETCH_CONTROL Register ...........................................................................
GPMC_PREFETCH_STATUS Register ..............................................................................
GPMC_ECC_CONFIG Register .......................................................................................
GPMC_ECC_CONTROL Register ....................................................................................
GPMC_ECC_SIZE_CONFIG Register ...............................................................................
GPMC_ECC1_RESULT Register .....................................................................................
GPMC_ECC2_RESULT Register .....................................................................................
GPMC_ECC3_RESULT Register .....................................................................................
GPMC_ECC4_RESULT Register .....................................................................................
GPMC_ECC5_RESULT Register .....................................................................................
GPMC_ECC6_RESULT Register .....................................................................................
GPMC_ECC7_RESULT Register .....................................................................................
SPRUHL7I – April 2014 – Revised December 2019
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List of Figures
1187
1192
1193
1194
1201
1204
1211
1215
1217
1219
1221
1228
1229
1230
1231
1232
1233
1234
1235
1236
1237
1238
1241
1242
1244
1246
1247
1249
1250
1251
1252
1253
1255
1256
1257
1258
1259
1260
1262
1264
1266
1268
1270
1272
1274
29
www.ti.com
9-82.
GPMC_ECC8_RESULT Register ..................................................................................... 1276
9-83.
GPMC_ECC9_RESULT Register ..................................................................................... 1278
9-84.
GPMC_BCH_RESULT0_0 Register .................................................................................. 1280
9-85.
GPMC_BCH_RESULT1_0 Register .................................................................................. 1281
9-86.
GPMC_BCH_RESULT2_0 Register .................................................................................. 1282
9-87.
GPMC_BCH_RESULT3_0 Register .................................................................................. 1283
9-88.
GPMC_BCH_RESULT0_1 Register .................................................................................. 1284
9-89.
GPMC_BCH_RESULT1_1 Register .................................................................................. 1285
9-90.
GPMC_BCH_RESULT2_1 Register .................................................................................. 1286
9-91.
GPMC_BCH_RESULT3_1 Register .................................................................................. 1287
9-92.
GPMC_BCH_RESULT0_2 Register .................................................................................. 1288
9-93.
GPMC_BCH_RESULT1_2 Register .................................................................................. 1289
9-94.
GPMC_BCH_RESULT2_2 Register .................................................................................. 1290
9-95.
GPMC_BCH_RESULT3_2 Register .................................................................................. 1291
9-96.
GPMC_BCH_RESULT0_3 Register .................................................................................. 1292
9-97.
GPMC_BCH_RESULT1_3 Register .................................................................................. 1293
9-98.
GPMC_BCH_RESULT2_3 Register .................................................................................. 1294
9-99.
GPMC_BCH_RESULT3_3 Register .................................................................................. 1295
9-100. GPMC_BCH_RESULT0_4 Register .................................................................................. 1296
9-101. GPMC_BCH_RESULT1_4 Register .................................................................................. 1297
9-102. GPMC_BCH_RESULT2_4 Register .................................................................................. 1298
9-103. GPMC_BCH_RESULT3_4 Register .................................................................................. 1299
9-104. GPMC_BCH_RESULT0_5 Register .................................................................................. 1300
9-105. GPMC_BCH_RESULT1_5 Register .................................................................................. 1301
9-106. GPMC_BCH_RESULT2_5 Register .................................................................................. 1302
9-107. GPMC_BCH_RESULT3_5 Register .................................................................................. 1303
9-108. GPMC_BCH_RESULT0_6 Register .................................................................................. 1304
9-109. GPMC_BCH_RESULT1_6 Register .................................................................................. 1305
9-110. GPMC_BCH_RESULT2_6 Register .................................................................................. 1306
9-111. GPMC_BCH_RESULT3_6 Register .................................................................................. 1307
9-112. GPMC_BCH_SWDATA Register...................................................................................... 1308
9-113. GPMC_BCH_RESULT4_0 Register .................................................................................. 1309
9-114. GPMC_BCH_RESULT5_0 Register .................................................................................. 1310
9-115. GPMC_BCH_RESULT6_0 Register .................................................................................. 1311
9-116. GPMC_BCH_RESULT4_1 Register .................................................................................. 1312
9-117. GPMC_BCH_RESULT5_1 Register .................................................................................. 1313
9-118. GPMC_BCH_RESULT6_1 Register .................................................................................. 1314
9-119. GPMC_BCH_RESULT4_2 Register .................................................................................. 1315
9-120. GPMC_BCH_RESULT5_2 Register .................................................................................. 1316
9-121. GPMC_BCH_RESULT6_2 Register .................................................................................. 1317
9-122. GPMC_BCH_RESULT4_3 Register .................................................................................. 1318
9-123. GPMC_BCH_RESULT5_3 Register .................................................................................. 1319
9-124. GPMC_BCH_RESULT6_3 Register .................................................................................. 1320
9-125. GPMC_BCH_RESULT4_4 Register .................................................................................. 1321
9-126. GPMC_BCH_RESULT5_4 Register .................................................................................. 1322
9-127. GPMC_BCH_RESULT6_4 Register .................................................................................. 1323
9-128. GPMC_BCH_RESULT4_5 Register .................................................................................. 1324
9-129. GPMC_BCH_RESULT5_5 Register .................................................................................. 1325
9-130. GPMC_BCH_RESULT6_5 Register .................................................................................. 1326
30
List of Figures
SPRUHL7I – April 2014 – Revised December 2019
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9-131. GPMC_BCH_RESULT4_6 Register .................................................................................. 1327
9-132. GPMC_BCH_RESULT5_6 Register .................................................................................. 1328
9-133. GPMC_BCH_RESULT6_6 Register .................................................................................. 1329
9-134. GPMC_BCH_RESULT0_7 Register .................................................................................. 1330
9-135. GPMC_BCH_RESULT1_7 Register .................................................................................. 1331
9-136. GPMC_BCH_RESULT2_7 Register .................................................................................. 1332
9-137. GPMC_BCH_RESULT3_7 Register .................................................................................. 1333
9-138. GPMC_BCH_RESULT4_7 Register .................................................................................. 1334
9-139. GPMC_BCH_RESULT5_7 Register .................................................................................. 1335
9-140. GPMC_BCH_RESULT6_7 Register .................................................................................. 1336
9-141. EMIF Block Diagram .................................................................................................... 1342
9-142. FIFO Block Diagram .................................................................................................... 1343
9-143. EMIF4D_MOD_ID_REV Register ..................................................................................... 1367
9-144. EMIF4D_STS Register ................................................................................................. 1368
9-145. EMIF4D_SDRAM_CONFIG Register ................................................................................. 1369
9-146. EMIF4D_SDRAM_CONFIG_2 Register .............................................................................. 1371
9-147. EMIF4D_SDRAM_REFRESH_CTRL Register ...................................................................... 1372
9-148. EMIF4D_SDRAM_REFRESH_CTRL_SHADOW Register ........................................................ 1373
9-149. EMIF4D_SDRAM_TIMING_1 Register ............................................................................... 1374
9-150. EMIF4D_SDRAM_TIMING_1_SHADOW Register ................................................................. 1375
9-151. EMIF4D_SDRAM_TIMING_2 Register ............................................................................... 1376
9-152. EMIF4D_SDRAM_TIMING_2_SHADOW Register ................................................................. 1377
9-153. EMIF4D_SDRAM_TIMING_3 Register ............................................................................... 1378
9-154. EMIF4D_SDRAM_TIMING_3_SHADOW Register ................................................................. 1379
9-155. EMIF4D_LPDDR2_NVM_TIMING Register
.........................................................................
1380
9-156. EMIF4D_LPDDR2_NVM_TIMING_SHADOW Register ............................................................ 1381
9-157. EMIF4D_POWER_MANAGEMENT_CTRL Register ............................................................... 1382
9-158. EMIF4D_POWER_MANAGEMENT_CTRL_SHADOW Register ................................................. 1384
9-159. EMIF4D_LPDDR2_MODE_REG_DATA Register .................................................................. 1385
9-160. EMIF4D_LPDDR2_MODE_REG_CONFIG Register ............................................................... 1386
9-161. EMIF4D_OCP_CONFIG Register ..................................................................................... 1387
.......................................................................
.......................................................................
EMIF4D_IODFT_TEST_LOGIC_GLOBAL_CTRL Register .......................................................
EMIF4D_IODFT_TEST_LOGIC_CTRL_MISR_RESULT Register ...............................................
EMIF4D_IODFT_TEST_LOGIC_ADDR_MISR_RESULT Register ...............................................
EMIF4D_IODFT_TEST_LOGIC_DATA_MISR_RESULT_1 Register ............................................
EMIF4D_IODFT_TEST_LOGIC_DATA_MISR_RESULT_2 Register ............................................
EMIF4D_IODFT_TEST_LOGIC_DATA_MISR_RESULT_3 Register ............................................
EMIF4D_PERFORMANCE_CTR_1 Register .......................................................................
EMIF4D_PERFORMANCE_CTR_2 Register .......................................................................
EMIF4D_PERFORMANCE_CTR_CONFIG Register ..............................................................
EMIF4D_PERFORMANCE_CTR_MASTER_REGION_SELECT Register ......................................
EMIF4D_PERFORMANCE_CTR_TIME Register...................................................................
EMIF4D_MISC_REG Register ........................................................................................
EMIF4D_DLL_CALIB_CTRL Register ................................................................................
EMIF4D_DLL_CALIB_CTRL_SHADOW Register ..................................................................
EMIF4D_END_OF_INTR Register ....................................................................................
EMIF4D_SYSTEM_OCP_INTR_RAW_STS Register ..............................................................
9-162. EMIF4D_OCP_CONFIG_VALUE_1 Register
1388
9-163. EMIF4D_OCP_CONFIG_VALUE_2 Register
1389
9-164.
1390
9-165.
9-166.
9-167.
9-168.
9-169.
9-170.
9-171.
9-172.
9-173.
9-174.
9-175.
9-176.
9-177.
9-178.
9-179.
SPRUHL7I – April 2014 – Revised December 2019
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Copyright © 2014–2019, Texas Instruments Incorporated
List of Figures
1392
1393
1394
1395
1396
1397
1398
1399
1400
1401
1402
1403
1404
1405
1406
31
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9-180. EMIF4D_LOW_LAT_OCP_INTR_RAW_STS Register ............................................................ 1407
9-181. EMIF4D_SYSTEM_OCP_INTR_STS Register...................................................................... 1408
9-182. EMIF4D_LOW_LAT_OCP_INTR_STS Register .................................................................... 1409
9-183. EMIF4D_SYSTEM_OCP_INTR_EN_SET Register ................................................................ 1410
9-184. EMIF4D_LOW_LAT_OCP_INTR_EN_SET Register ............................................................... 1411
9-185. EMIF4D_SYSTEM_OCP_INTR_EN_CLR Register ................................................................ 1412
9-186. EMIF4D_LOW_LAT_OCP_INTR_EN_CLR Register ............................................................... 1413
9-187. EMIF4D_SDRAM_OUTPUT_IMPEDANCE_CALIBRATION_CONFIG Register ............................... 1414
9-188. EMIF4D_TEMPERATURE_ALERT_CONFIG Register ............................................................ 1415
9-189. EMIF4D_OCP_ERROR_LOG Register .............................................................................. 1416
9-190. EMIF4D_READ_WRITE_LEVELING_RAMP_WINDOW Register................................................ 1417
9-191. EMIF4D_READ_WRITE_LEVELING_RAMP_CTRL Register .................................................... 1418
9-192. EMIF4D_READ_WRITE_LEVELING_CTRL Register .............................................................. 1419
9-193. EMIF4D_DDR_PHY_CTRL_1 Register .............................................................................. 1420
9-194. EMIF4D_DDR_PHY_CTRL_1_SHADOW Register
................................................................
1422
9-195. EMIF4D_PRIORITY_TO_CLASS_OF_SERVICE_MAPPING Register .......................................... 1424
9-196. EMIF4D_CONNECTION_ID_TO_CLASS_OF_SERVICE_1_MAPPING Register ............................. 1425
9-197. EMIF4D_CONNECTION_ID_TO_CLASS_OF_SERVICE_2_MAPPING Register ............................. 1426
9-198. EMIF4D_ECC_CTRL_REG Register ................................................................................. 1427
9-199. EMIF4D_ECC_ADDR_RANGE_1 Register.......................................................................... 1428
9-200. EMIF4D_ECC_ADDR_RANGE_2 Register.......................................................................... 1429
9-201. EMIF4D_READ_WRITE_EXECUTION_THR Register............................................................. 1430
9-202. EMIF4D_COS_CONFIG Register ..................................................................................... 1431
9-203. EMIF4D_1B_ECC_ERR_CNT Register .............................................................................. 1432
9-204. EMIF4D_1B_ECC_ERR_THRSH Register .......................................................................... 1433
9-205. EMIF4D_1B_ECC_ERR_DIST_1 Register .......................................................................... 1434
1435
9-207. EMIF4D_2B_ECC_ERR_ADDR_LOG Register
1436
9-208.
1437
9-209.
9-210.
9-211.
9-212.
9-213.
9-214.
9-215.
9-216.
9-217.
9-218.
9-219.
9-220.
9-221.
9-222.
9-223.
9-224.
9-225.
9-226.
9-227.
9-228.
32
....................................................................
....................................................................
EMIF4D_PHY_STS_1 Register .......................................................................................
EMIF4D_PHY_STS_2 Register .......................................................................................
EMIF4D_PHY_STS_3 Register .......................................................................................
EMIF4D_PHY_STS_4 Register .......................................................................................
EMIF4D_PHY_STS_5 Register .......................................................................................
EMIF4D_PHY_STS_6 Register .......................................................................................
EMIF4D_PHY_STS_7 Register .......................................................................................
EMIF4D_PHY_STS_8 Register .......................................................................................
EMIF4D_PHY_STS_9 Register .......................................................................................
EMIF4D_PHY_STS_10 Register ......................................................................................
EMIF4D_PHY_STS_11 Register ......................................................................................
EMIF4D_PHY_STS_12 Register ......................................................................................
EMIF4D_PHY_STS_13 Register ......................................................................................
EMIF4D_PHY_STS_14 Register ......................................................................................
EMIF4D_PHY_STS_15 Register ......................................................................................
EMIF4D_PHY_STS_16 Register ......................................................................................
EMIF4D_PHY_STS_17 Register ......................................................................................
EMIF4D_PHY_STS_18 Register ......................................................................................
EMIF4D_PHY_STS_19 Register ......................................................................................
EMIF4D_PHY_STS_20 Register ......................................................................................
EMIF4D_PHY_STS_21 Register ......................................................................................
9-206. EMIF4D_1B_ECC_ERR_ADDR_LOG Register
List of Figures
1438
1439
1440
1441
1442
1443
1444
1445
1446
1447
1448
1449
1450
1451
1452
1453
1454
1455
1456
1457
SPRUHL7I – April 2014 – Revised December 2019
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9-229. EMIF4D_PHY_STS_22 Register ...................................................................................... 1458
9-230. EMIF4D_PHY_STS_23 Register ...................................................................................... 1459
9-231. EMIF4D_PHY_STS_24 Register ...................................................................................... 1460
9-232. EMIF4D_PHY_STS_25 Register ...................................................................................... 1461
9-233. EMIF4D_PHY_STS_26 Register ...................................................................................... 1462
9-234. EMIF4D_PHY_STS_27 Register ...................................................................................... 1463
9-235. EMIF4D_PHY_STS_28 Register ...................................................................................... 1464
9-236. EMIF4D_EXT_PHY_CTRL_1 Register ............................................................................... 1465
9-237. EMIF4D_EXT_PHY_CTRL_1_SHADOW Register ................................................................. 1466
9-238. EMIF4D_EXT_PHY_CTRL_2 Register ............................................................................... 1467
9-239. EMIF4D_EXT_PHY_CTRL_2_SHADOW Register ................................................................. 1468
9-240. EMIF4D_EXT_PHY_CTRL_3 Register ............................................................................... 1469
9-241. EMIF4D_EXT_PHY_CTRL_3_SHADOW Register ................................................................. 1470
9-242. EMIF4D_EXT_PHY_CTRL_4 Register ............................................................................... 1471
9-243. EMIF4D_EXT_PHY_CTRL_4_SHADOW Register ................................................................. 1472
9-244. EMIF4D_EXT_PHY_CTRL_5 Register ............................................................................... 1473
9-245. EMIF4D_EXT_PHY_CTRL_5_SHADOW Register ................................................................. 1474
9-246. EMIF4D_EXT_PHY_CTRL_6 Register ............................................................................... 1475
9-247. EMIF4D_EXT_PHY_CTRL_6_SHADOW Register ................................................................. 1476
9-248. EMIF4D_EXT_PHY_CTRL_7 Register ............................................................................... 1477
9-249. EMIF4D_EXT_PHY_CTRL_7_SHADOW Register ................................................................. 1478
9-250. EMIF4D_EXT_PHY_CTRL_8 Register ............................................................................... 1479
9-251. EMIF4D_EXT_PHY_CTRL_8_SHADOW Register ................................................................. 1480
9-252. EMIF4D_EXT_PHY_CTRL_9 Register ............................................................................... 1481
9-253. EMIF4D_EXT_PHY_CTRL_9_SHADOW Register ................................................................. 1482
9-254. EMIF4D_EXT_PHY_CTRL_10 Register ............................................................................. 1483
9-255. EMIF4D_EXT_PHY_CTRL_10_SHADOW Register................................................................ 1484
9-256. EMIF4D_EXT_PHY_CTRL_11 Register ............................................................................. 1485
9-257. EMIF4D_EXT_PHY_CTRL_11_SHADOW Register................................................................ 1486
9-258. EMIF4D_EXT_PHY_CTRL_12 Register ............................................................................. 1487
9-259. EMIF4D_EXT_PHY_CTRL_12_SHADOW Register................................................................ 1488
9-260. EMIF4D_EXT_PHY_CTRL_13 Register ............................................................................. 1489
9-261. EMIF4D_EXT_PHY_CTRL_13_SHADOW Register................................................................ 1490
9-262. EMIF4D_EXT_PHY_CTRL_14 Register ............................................................................. 1491
9-263. EMIF4D_EXT_PHY_CTRL_14_SHADOW Register................................................................ 1492
9-264. EMIF4D_EXT_PHY_CTRL_15 Register ............................................................................. 1493
9-265. EMIF4D_EXT_PHY_CTRL_15_SHADOW Register................................................................ 1494
9-266. EMIF4D_EXT_PHY_CTRL_16 Register ............................................................................. 1495
9-267. EMIF4D_EXT_PHY_CTRL_16_SHADOW Register................................................................ 1496
9-268. EMIF4D_EXT_PHY_CTRL_17 Register ............................................................................. 1497
9-269. EMIF4D_EXT_PHY_CTRL_17_SHADOW Register................................................................ 1498
9-270. EMIF4D_EXT_PHY_CTRL_18 Register ............................................................................. 1499
9-271. EMIF4D_EXT_PHY_CTRL_18_SHADOW Register................................................................ 1500
9-272. EMIF4D_EXT_PHY_CTRL_19 Register ............................................................................. 1501
9-273. EMIF4D_EXT_PHY_CTRL_19_SHADOW Register................................................................ 1502
9-274. EMIF4D_EXT_PHY_CTRL_20 Register ............................................................................. 1503
9-275. EMIF4D_EXT_PHY_CTRL_20_SHADOW Register................................................................ 1504
9-276. EMIF4D_EXT_PHY_CTRL_21 Register ............................................................................. 1505
9-277. EMIF4D_EXT_PHY_CTRL_21_SHADOW Register................................................................ 1506
SPRUHL7I – April 2014 – Revised December 2019
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33
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9-278. EMIF4D_EXT_PHY_CTRL_22 Register ............................................................................. 1507
9-279. EMIF4D_EXT_PHY_CTRL_22_SHADOW Register................................................................ 1508
9-280. EMIF4D_EXT_PHY_CTRL_23 Register ............................................................................. 1509
9-281. EMIF4D_EXT_PHY_CTRL_23_SHADOW Register................................................................ 1510
9-282. EMIF4D_EXT_PHY_CTRL_24 Register ............................................................................. 1511
9-283. EMIF4D_EXT_PHY_CTRL_24_SHADOW Register................................................................ 1512
9-284. EMIF4D_EXT_PHY_CTRL_25 Register ............................................................................. 1513
9-285. EMIF4D_EXT_PHY_CTRL_25_SHADOW Register................................................................ 1514
9-286. EMIF4D_EXT_PHY_CTRL_26 Register ............................................................................. 1515
9-287. EMIF4D_EXT_PHY_CTRL_26_SHADOW Register................................................................ 1516
9-288. EMIF4D_EXT_PHY_CTRL_27 Register ............................................................................. 1517
9-289. EMIF4D_EXT_PHY_CTRL_27_SHADOW Register................................................................ 1518
9-290. EMIF4D_EXT_PHY_CTRL_28 Register ............................................................................. 1519
9-291. EMIF4D_EXT_PHY_CTRL_28_SHADOW Register................................................................ 1520
9-292. EMIF4D_EXT_PHY_CTRL_29 Register ............................................................................. 1521
9-293. EMIF4D_EXT_PHY_CTRL_29_SHADOW Register................................................................ 1522
9-294. EMIF4D_EXT_PHY_CTRL_30 Register ............................................................................. 1523
9-295. EMIF4D_EXT_PHY_CTRL_30_SHADOW Register................................................................ 1524
9-296. EMIF4D_EXT_PHY_CTRL_31 Register ............................................................................. 1525
9-297. EMIF4D_EXT_PHY_CTRL_31_SHADOW Register................................................................ 1526
9-298. EMIF4D_EXT_PHY_CTRL_32 Register ............................................................................. 1527
9-299. EMIF4D_EXT_PHY_CTRL_32_SHADOW Register................................................................ 1528
9-300. EMIF4D_EXT_PHY_CTRL_33 Register ............................................................................. 1529
9-301. EMIF4D_EXT_PHY_CTRL_33_SHADOW Register................................................................ 1530
9-302. EMIF4D_EXT_PHY_CTRL_34 Register ............................................................................. 1531
9-303. EMIF4D_EXT_PHY_CTRL_34_SHADOW Register................................................................ 1532
9-304. EMIF4D_EXT_PHY_CTRL_35 Register ............................................................................. 1533
9-305. EMIF4D_EXT_PHY_CTRL_35_SHADOW Register................................................................ 1534
9-306. EMIF4D_EXT_PHY_CTRL_36 Register ............................................................................. 1535
9-307. EMIF4D_EXT_PHY_CTRL_36_SHADOW Register................................................................ 1536
9-308. ELM Integration .......................................................................................................... 1538
9-309. ELM_REVISION Register .............................................................................................. 1552
9-310. ELM_SYSCONFIG Register ........................................................................................... 1553
9-311. ELM_SYSSTS Register ................................................................................................ 1554
9-312. ELM_IRQSTS Register ................................................................................................. 1555
..................................................................................................
ELM_LOCATION_CONFIG Register .................................................................................
ELM_PAGE_CTRL Register ...........................................................................................
ELM_SYNDROME_FRAGMENT_0_0 Register .....................................................................
ELM_SYNDROME_FRAGMENT_1_0 Register .....................................................................
ELM_SYNDROME_FRAGMENT_2_0 Register .....................................................................
ELM_SYNDROME_FRAGMENT_3_0 Register .....................................................................
ELM_SYNDROME_FRAGMENT_4_0 Register .....................................................................
ELM_SYNDROME_FRAGMENT_5_0 Register .....................................................................
ELM_SYNDROME_FRAGMENT_6_0 Register .....................................................................
ELM_LOCATION_STS_0 Register ...................................................................................
ELM_ERROR_LOCATION_0_0 Register ............................................................................
ELM_ERROR_LOCATION_1_0 Register ............................................................................
ELM_ERROR_LOCATION_2_0 Register ............................................................................
9-313. ELM_IRQEN Register
9-314.
9-315.
9-316.
9-317.
9-318.
9-319.
9-320.
9-321.
9-322.
9-323.
9-324.
9-325.
9-326.
34
List of Figures
1556
1557
1558
1559
1560
1561
1562
1563
1564
1565
1566
1567
1568
1569
SPRUHL7I – April 2014 – Revised December 2019
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9-327. ELM_ERROR_LOCATION_3_0 Register ............................................................................ 1570
9-328. ELM_ERROR_LOCATION_4_0 Register ............................................................................ 1571
9-329. ELM_ERROR_LOCATION_5_0 Register ............................................................................ 1572
9-330. ELM_ERROR_LOCATION_6_0 Register ............................................................................ 1573
9-331. ELM_ERROR_LOCATION_7_0 Register ............................................................................ 1574
9-332. ELM_ERROR_LOCATION_8_0 Register ............................................................................ 1575
9-333. ELM_ERROR_LOCATION_9_0 Register ............................................................................ 1576
..........................................................................
..........................................................................
ELM_ERROR_LOCATION_12_0 Register ..........................................................................
ELM_ERROR_LOCATION_13_0 Register ..........................................................................
ELM_ERROR_LOCATION_14_0 Register ..........................................................................
ELM_ERROR_LOCATION_15_0 Register ..........................................................................
EDMA3 Controller Block Diagram.....................................................................................
TPCC Integration ........................................................................................................
TPTC Integration ........................................................................................................
EDMA3 Channel Controller (EDMA3CC) Block Diagram ..........................................................
EDMA3 Transfer Controller (EDMA3TC) Block Diagram ..........................................................
Definition of ACNT, BCNT, and CCNT ..............................................................................
A-Synchronized Transfers (ACNT = n, BCNT = 4, CCNT = 3)....................................................
AB-Synchronized Transfers (ACNT = n, BCNT = 4, CCNT = 3) ..................................................
PaRAM Set ...............................................................................................................
Channel Options Parameter (OPT) ...................................................................................
Linked Transfer ..........................................................................................................
Link-to-Self Transfer ....................................................................................................
DMA Channel and QDMA Channel to PaRAM Mapping...........................................................
QDMA Channel to PaRAM Mapping .................................................................................
Shadow Region Registers .............................................................................................
Interrupt Diagram ........................................................................................................
Error Interrupt Operation ...............................................................................................
PaRAM Set Content for Proxy Memory Protection Example ......................................................
Channel Options Parameter (OPT) Example ........................................................................
Proxy Memory Protection Example ...................................................................................
EDMA3 Prioritization ....................................................................................................
Block Move Example ...................................................................................................
Block Move Example PaRAM Configuration.........................................................................
Subframe Extraction Example .........................................................................................
Subframe Extraction Example PaRAM Configuration ..............................................................
Data Sorting Example ..................................................................................................
Data Sorting Example PaRAM Configuration .......................................................................
Servicing Incoming McASP Data Example ..........................................................................
Servicing Incoming McASP Data Example PaRAM Configuration ...............................................
Servicing Peripheral Burst Example ..................................................................................
Servicing Peripheral Burst Example PaRAM Configuration .......................................................
Servicing Continuous McASP Data Example ........................................................................
Servicing Continuous McASP Data Example PaRAM Configuration .............................................
Servicing Continuous McASP Data Example Reload PaRAM Configuration ...................................
Ping-Pong Buffering for McASP Data Example ....................................................................
Ping-Pong Buffering for McASP Example PaRAM Configuration.................................................
9-334. ELM_ERROR_LOCATION_10_0 Register
1577
9-335. ELM_ERROR_LOCATION_11_0 Register
1578
9-336.
1579
9-337.
9-338.
9-339.
10-1.
10-2.
10-3.
10-4.
10-5.
10-6.
10-7.
10-8.
10-9.
10-10.
10-11.
10-12.
10-13.
10-14.
10-15.
10-16.
10-17.
10-18.
10-19.
10-20.
10-21.
10-22.
10-23.
10-24.
10-25.
10-26.
10-27.
10-28.
10-29.
10-30.
10-31.
10-32.
10-33.
10-34.
10-35.
10-36.
SPRUHL7I – April 2014 – Revised December 2019
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List of Figures
1580
1581
1582
1584
1587
1588
1591
1592
1593
1594
1595
1597
1599
1606
1607
1612
1613
1615
1619
1622
1626
1626
1627
1634
1635
1635
1636
1636
1637
1638
1639
1639
1640
1641
1642
1643
1643
1646
1646
35
www.ti.com
.........................................
Ping-Pong Buffering for McASP Example Ping PaRAM Configuration ..........................................
Intermediate Transfer Completion Chaining Example ..............................................................
Single Large Block Transfer Example ................................................................................
Smaller Packet Data Transfers Example.............................................................................
PID Register .............................................................................................................
CCCFG Register ........................................................................................................
SYSCONFIG Register ..................................................................................................
DCHMAP_0 to DCHMAP_63 Register ...............................................................................
QCHMAP_0 to QCHMAP_7 Register ................................................................................
DMAQNUM_0 to DMAQNUM_7 Register............................................................................
QDMAQNUM Register..................................................................................................
QUEPRI Register........................................................................................................
EMR Register ............................................................................................................
EMRH Register ..........................................................................................................
EMCR Register ..........................................................................................................
EMCRH Register ........................................................................................................
QEMR Register ..........................................................................................................
QEMCR Register ........................................................................................................
CCERR Register ........................................................................................................
CCERRCLR Register ...................................................................................................
EEVAL Register .........................................................................................................
DRAE0 Register .........................................................................................................
DRAEH0 Register .......................................................................................................
DRAE1 Register .........................................................................................................
DRAEH1 Register .......................................................................................................
DRAE2 Register .........................................................................................................
DRAEH2 Register .......................................................................................................
DRAE3 Register .........................................................................................................
DRAEH3 Register .......................................................................................................
QRAE_0 to QRAE_3 Register .........................................................................................
Q0E_0 to Q0E_15 Register ............................................................................................
Q1E_0 to Q1E_15 Register ............................................................................................
Q2E_0 to Q2E_15 Register ............................................................................................
QSTAT_0 to QSTAT_2 Register ......................................................................................
QWMTHRA Register ....................................................................................................
CCSTAT Register .......................................................................................................
MPFAR Register ........................................................................................................
MPFSR Register ........................................................................................................
MPFCR Register ........................................................................................................
MPPAG Register ........................................................................................................
MPPA_0 to MPPA_3 Register .........................................................................................
ER Register ..............................................................................................................
ERH Register ............................................................................................................
ECR Register ............................................................................................................
ECRH Register ..........................................................................................................
ESR Register ............................................................................................................
ESRH Register ..........................................................................................................
CER Register ............................................................................................................
10-37. Ping-Pong Buffering for McASP Example Pong PaRAM Configuration
10-38.
10-39.
10-40.
10-41.
10-42.
10-43.
10-44.
10-45.
10-46.
10-47.
10-48.
10-49.
10-50.
10-51.
10-52.
10-53.
10-54.
10-55.
10-56.
10-57.
10-58.
10-59.
10-60.
10-61.
10-62.
10-63.
10-64.
10-65.
10-66.
10-67.
10-68.
10-69.
10-70.
10-71.
10-72.
10-73.
10-74.
10-75.
10-76.
10-77.
10-78.
10-79.
10-80.
10-81.
10-82.
10-83.
10-84.
10-85.
36
List of Figures
1647
1648
1649
1650
1650
1656
1657
1659
1660
1661
1662
1667
1670
1671
1672
1673
1674
1675
1676
1677
1678
1679
1680
1681
1682
1683
1684
1685
1686
1687
1688
1689
1690
1691
1692
1693
1694
1696
1697
1698
1699
1701
1703
1704
1705
1706
1707
1708
1709
SPRUHL7I – April 2014 – Revised December 2019
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10-86. CERH Register .......................................................................................................... 1710
............................................................................................................
..........................................................................................................
10-89. EECR Register ..........................................................................................................
10-90. EECRH Register ........................................................................................................
10-91. EESR Register...........................................................................................................
10-92. EESRH Register .........................................................................................................
10-93. SER Register ............................................................................................................
10-94. SERH Register ..........................................................................................................
10-95. SECR Register ..........................................................................................................
10-96. SECRH Register ........................................................................................................
10-97. IER Register .............................................................................................................
10-98. IERH Register ...........................................................................................................
10-99. IECR Register ...........................................................................................................
10-100. IECRH Register ........................................................................................................
10-101. IESR Register ..........................................................................................................
10-102. IESRH Register ........................................................................................................
10-103. IPR Register ............................................................................................................
10-104. IPRH Register ..........................................................................................................
10-105. ICR Register ............................................................................................................
10-106. ICRH Register ..........................................................................................................
10-107. IEVAL Register .........................................................................................................
10-108. QER Register ...........................................................................................................
10-109. QEER Register .........................................................................................................
10-110. QEECR Register .......................................................................................................
10-111. QEESR Register .......................................................................................................
10-112. QSER Register .........................................................................................................
10-113. QSECR Register .......................................................................................................
10-114. PID Register ............................................................................................................
10-115. TCCFG Register .......................................................................................................
10-116. SYSCONFIG Register .................................................................................................
10-117. TCSTAT Register ......................................................................................................
10-118. ERRSTAT Register ....................................................................................................
10-119. ERREN Register .......................................................................................................
10-120. ERRCLR Register .....................................................................................................
10-121. ERRDET Register .....................................................................................................
10-122. ERRCMD Register .....................................................................................................
10-123. RDRATE Register .....................................................................................................
10-124. SAOPT Register .......................................................................................................
10-125. SASRC Register .......................................................................................................
10-126. SACNT Register .......................................................................................................
10-127. SADST Register........................................................................................................
10-128. SABIDX Register .......................................................................................................
10-129. SAMPPRXY Register..................................................................................................
10-130. SACNTRLD Register ..................................................................................................
10-131. SASRCBREF Register ................................................................................................
10-132. SADSTBREF Register ................................................................................................
10-133. DFCNTRLD Register ..................................................................................................
10-134. DFSRCBREF Register ................................................................................................
10-87. EER Register
1711
10-88. EERH Register
1712
SPRUHL7I – April 2014 – Revised December 2019
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List of Figures
1713
1714
1715
1716
1717
1718
1719
1720
1721
1722
1723
1724
1725
1726
1727
1728
1729
1730
1731
1732
1733
1734
1735
1736
1737
1739
1740
1741
1742
1744
1745
1746
1747
1748
1749
1750
1752
1753
1754
1755
1756
1757
1758
1759
1760
1761
37
www.ti.com
................................................................................................
10-136. DFOPT0 Register ......................................................................................................
10-137. DFSRC0 Register ......................................................................................................
10-138. DFCNT0 Register ......................................................................................................
10-139. DFDST0 Register ......................................................................................................
10-140. DFBIDX0 Register .....................................................................................................
10-141. DFMPPRXY0 Register ................................................................................................
10-142. DFOPT1 Register ......................................................................................................
10-143. DFSRC1 Register ......................................................................................................
10-144. DFCNT1 Register ......................................................................................................
10-145. DFDST1 Register ......................................................................................................
10-146. DFBIDX1 Register .....................................................................................................
10-147. DFMPPRXY1 Register ................................................................................................
10-148. DFOPT2 Register ......................................................................................................
10-149. DFSRC2 Register ......................................................................................................
10-150. DFCNT2 Register ......................................................................................................
10-151. DFDST2 Register ......................................................................................................
10-152. DFBIDX2 Register .....................................................................................................
10-153. DFMPPRXY2 Register ................................................................................................
10-154. DFOPT3 Register ......................................................................................................
10-155. DFSRC3 Register ......................................................................................................
10-156. DFCNT3 Register ......................................................................................................
10-157. DFDST3 Register ......................................................................................................
10-158. DFBIDX3 Register .....................................................................................................
10-159. DFMPPRXY3 Register ................................................................................................
11-1. TSC_ADC (ADC0) Integration .........................................................................................
11-2. Functional Block Diagram ..............................................................................................
11-3. Sequencer FSM .........................................................................................................
11-4. Example Timing Diagram for Sequencer.............................................................................
11-5. ADC0_REVISION Register ............................................................................................
11-6. ADC0_SYSCONFIG Register .........................................................................................
11-7. ADC0_IRQSTS_RAW Register .......................................................................................
11-8. ADC0_IRQSTS Register ...............................................................................................
11-9. ADC0_IRQEN_SET Register ..........................................................................................
11-10. ADC0_IRQEN_CLR Register ..........................................................................................
11-11. ADC0_IRQWAKEUP Register .........................................................................................
11-12. ADC0_DMAEN_SET Register .........................................................................................
11-13. ADC0_DMAEN_CLR Register.........................................................................................
11-14. ADC0_CTRL Register ..................................................................................................
11-15. ADC0_ADCSTAT Register .............................................................................................
11-16. ADC0_ADCRANGE Register ..........................................................................................
11-17. ADC0_ADC_CLKDIV Register ........................................................................................
11-18. ADC0_ADC_MISC Register ...........................................................................................
11-19. ADC0_STEPEN Register ..............................................................................................
11-20. ADC0_IDLECONFIG Register .........................................................................................
11-21. ADC0_TS_CHARGE_STEPCONFIG Register ......................................................................
11-22. ADC0_TS_CHARGE_DELAY Register ..............................................................................
11-23. ADC0_STEPCONFIG_0 Register .....................................................................................
11-24. ADC0_STEPDELAY_0 Register ......................................................................................
10-135. DFDSTBREF Register
38
List of Figures
1762
1763
1765
1766
1767
1768
1769
1770
1772
1773
1774
1775
1776
1777
1779
1780
1781
1782
1783
1784
1786
1787
1788
1789
1790
1797
1801
1804
1805
1808
1809
1810
1812
1814
1816
1818
1819
1820
1821
1823
1824
1825
1826
1827
1828
1830
1832
1833
1835
SPRUHL7I – April 2014 – Revised December 2019
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......................................................................................
ADC0_FIFOTHR_0 Register...........................................................................................
ADC0_DMAREQ_0 Register ..........................................................................................
ADC0_FIFO0DATA Register ..........................................................................................
ADC0_FIFO1DATA Register ..........................................................................................
MagneticCard Reader Integration .....................................................................................
FSM Sequencer .........................................................................................................
Example Timing Diagram for FSM Sequencer ......................................................................
Input Bias Resistors, Bias Supply, and Preamplifier Schematic ..................................................
AFE Functional Block Diagram ........................................................................................
ADC1_FIFO0DATA Register ..........................................................................................
Integration of ADC0 and ADC1 in Simultaneous Mode ............................................................
ADC1_REVISION Register ............................................................................................
ADC1_CLKDIV Register ...............................................................................................
ADC1_STEPCONFIG1 Register ......................................................................................
ADC1_STEPDELAY1 Register ........................................................................................
ADC1_STEPCONFIG2 Register ......................................................................................
ADC1_STEPDELAY2 Register ........................................................................................
ADC1_STEPCONFIG3 Register ......................................................................................
ADC1_STEPDELAY3 Register ........................................................................................
ADC1_STEPCONFIG4 Register ......................................................................................
ADC1_STEPDELAY4 Register ........................................................................................
ADC1_STEPCONFIG5 Register ......................................................................................
ADC1_STEPDELAY5 Register ........................................................................................
ADC1_STEPCONFIG6 Register ......................................................................................
ADC1_STEPDELAY6 Register ........................................................................................
ADC1_STEPCONFIG7 Register ......................................................................................
ADC1_STEPDELAY7 Register ........................................................................................
ADC1_STEPCONFIG8 Register ......................................................................................
ADC1_STEPDELAY8 Register ........................................................................................
ADC1_STEPCONFIG9 Register ......................................................................................
ADC1_STEPDELAY9 Register ........................................................................................
ADC1_STEPCONFIG10 Register .....................................................................................
ADC1_STEPDELAY10 Register ......................................................................................
ADC1_STEPCONFIG11 Register .....................................................................................
ADC1_STEPDELAY11 Register ......................................................................................
ADC1_STEPCONFIG12 Register .....................................................................................
ADC1_STEPDELAY12 Register ......................................................................................
ADC1_STEPCONFIG13 Register .....................................................................................
ADC1_STEPDELAY13 Register ......................................................................................
ADC1_STEPCONFIG14 Register .....................................................................................
ADC1_STEPDELAY14 Register ......................................................................................
ADC1_STEPCONFIG15 Register .....................................................................................
ADC1_STEPDELAY15 Register ......................................................................................
ADC1_STEPCONFIG16 Register .....................................................................................
ADC1_STEPDELAY16 Register ......................................................................................
DSS Integration ..........................................................................................................
Display Subsystem Full Schematic ...................................................................................
LCD Support Parallel Interface (RFBI Mode) ........................................................................
11-25. ADC0_FIFOCOUNT_0 Register
1836
11-26.
1837
11-27.
11-28.
11-29.
12-1.
12-2.
12-3.
12-4.
12-5.
12-6.
12-7.
12-8.
12-9.
12-10.
12-11.
12-12.
12-13.
12-14.
12-15.
12-16.
12-17.
12-18.
12-19.
12-20.
12-21.
12-22.
12-23.
12-24.
12-25.
12-26.
12-27.
12-28.
12-29.
12-30.
12-31.
12-32.
12-33.
12-34.
12-35.
12-36.
12-37.
12-38.
12-39.
12-40.
12-41.
13-1.
13-2.
13-3.
SPRUHL7I – April 2014 – Revised December 2019
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Copyright © 2014–2019, Texas Instruments Incorporated
List of Figures
1838
1839
1840
1844
1847
1851
1852
1853
1857
1858
1860
1871
1876
1878
1879
1881
1882
1884
1885
1887
1888
1890
1891
1893
1894
1896
1897
1899
1900
1902
1903
1905
1906
1908
1909
1911
1912
1914
1915
1917
1918
1920
1921
1923
1935
1937
1942
39
www.ti.com
13-4.
External Generation of TE Signal Based on Logical OR Operation Between HSYNC and VSYNC (ActiveHigh) ...................................................................................................................... 1943
13-5.
LCD Support Parallel Interface (Bypass Mode) ..................................................................... 1944
13-6.
LCD Pixel Data Monochrome4 Passive Matrix ...................................................................... 1945
13-7.
LCD Pixel Data Monochrome8 Passive Matrix ...................................................................... 1946
13-8.
LCD Pixel Data Color Passive Matrix................................................................................. 1946
13-9.
LCD Pixel Data Color12 Active Matrix ................................................................................ 1947
13-10. LCD Pixel Data Color16 Active Matrix ................................................................................ 1948
13-11. LCD Pixel Data Color18 Active Matrix ................................................................................ 1948
13-12. LCD Pixel Data Color24 Active Matrix ................................................................................ 1949
13-13. RFBI Data Stall Signal Diagram ....................................................................................... 1949
13-14. RFBI Data Stall Signal Diagram With Handcheck .................................................................. 1950
13-15. Command Data Write ................................................................................................... 1950
13-16. Display Data Read ...................................................................................................... 1951
13-17. Read to Write and Write to Read
.....................................................................................
1951
13-18. Active Matrix Timing Diagram of Configuration 1 (Start of Frame) ............................................... 1952
13-19. Active Matrix Timing Diagram of Configuration 1 (Between Lines) ............................................... 1952
13-20. Active Matrix Timing Diagram of Configuration 1 (Between Frames) ............................................ 1953
13-21. Active Matrix Timing Diagram of Configuration 1 (End of Frame) ................................................ 1953
13-22. Active Matrix Timing Diagram of Configuration 2 (Start of Frame) ............................................... 1953
13-23. Active Matrix Timing Diagram of Configuration 2 (Between Lines) ............................................... 1954
13-24. Active Matrix Timing Diagram of Configuration 2 (Between Frames) ............................................ 1954
13-25. Active Matrix Timing Diagram of Configuration 2 (End of Frame) ................................................ 1954
13-26. Active Matrix Timing Diagram of Configuration 3 (Start of Frame) ............................................... 1955
13-27. Active Matrix Timing Diagram of Configuration 3 (Between Lines) ............................................... 1955
13-28. Active Matrix Timing Diagram of Configuration 3 (Between Frames) ............................................ 1955
13-29. Active Matrix Timing Diagram of Configuration 3 (End of Frame) ................................................ 1955
13-30. Passive Matrix Timing Diagram (Start of Frame) ................................................................... 1956
13-31. Passive Matrix Timing Diagram (Between Lines) ................................................................... 1956
13-32. Passive Matrix Timing Diagram (Between Frames) ................................................................ 1956
13-33. Passive Matrix Timing Diagram (End of Frame) .................................................................... 1956
13-34. Display Controller Architecture Overview ............................................................................ 1957
13-35. Palette/Gamma Correction Architecture.............................................................................. 1961
13-36. YCbCr 4:2:2 to YCbCr 4:4:4 (0- or 180-Degree Rotation) ......................................................... 1964
13-37. YCbCr 4:2:2 to YCbCr 4:4:4 (90- or 270-Degree Rotation)
.......................................................
1964
13-38. Interpolation of the Missing Chrominance Component ............................................................. 1964
13-39. YCbCr to RGB Registers (VIDFULLRANGE = 0) ................................................................... 1965
13-40. YCbCr to RGB Registers (VIDFULLRANGE = 1) ................................................................... 1965
13-41. Color Space Conversion Macro-Architecture ........................................................................ 1966
13-42. Video Upsampling ....................................................................................................... 1967
13-43. Resampling Macro-Architecture (3-Coefficient Processing) ....................................................... 1968
1971
13-45. Display Attributes in Normal Mode
1971
13-46.
1972
13-47.
13-48.
13-49.
13-50.
13-51.
40
...................................................................................
...................................................................................
Overlay Manager in Alpha Mode .....................................................................................
Display Attributes in Alpha Mode......................................................................................
Alpha Blending Macro Architecture with Pre-multiplied Alpha Support ..........................................
Video Source Transparency Example ................................................................................
Graphics Destination Transparency Example .......................................................................
Color Phase Rotation Matrix ...........................................................................................
13-44. Overlay Manager in Normal Mode
List of Figures
1973
1974
1976
1976
1977
SPRUHL7I – April 2014 – Revised December 2019
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...........................................................................
13-53. RFBI Architecture Overview ...........................................................................................
13-54. Overlay Optimization: Case 1..........................................................................................
13-55. Overlay Optimization: Case 2..........................................................................................
13-56. Overlay Optimization: Case 3..........................................................................................
13-57. Overlay Optimization: Case 4..........................................................................................
13-58. Timing Values Description (Active Matrix Display)..................................................................
13-59. PCDmin Formulas (V Down-Sampling Only) ........................................................................
13-60. Color Phase Rotation Matrix ...........................................................................................
13-61. Color Phase Rotation Matrix (R Component Only) .................................................................
13-62. Color Phase Rotation Matrix (G Component Only) .................................................................
13-63. Color Phase Rotation Matrix (B Component Only) .................................................................
13-64. Diagonal Matrix Configuration .........................................................................................
13-65. Example - Diagonal Matrix Configuration ............................................................................
13-66. Image With and Without CPR (Diagonal Matrix) ....................................................................
13-67. Example - Image With and Without CPR (Standard Matrix).......................................................
13-68. How to Use RFBI ........................................................................................................
13-69. RFBI Initial Configuration ...............................................................................................
13-70. RFBI Output Enable.....................................................................................................
13-71. Vertical Filtering Macro Architecture (Three Taps) .................................................................
13-72. Vertical Filtering Macro Architecture (Five Taps) ...................................................................
13-73. Horizontal Filtering Macro Architecture (Five Taps) ................................................................
13-74. Vertical Up-/Down-Sampling Algorithm ...............................................................................
13-75. Horizontal Up-/Down-Sampling Algorithm ...........................................................................
13-76. QVGA LCD Timings.....................................................................................................
13-77. DISPC_REVISION Register ...........................................................................................
13-78. DISPC_SYSCFG Register .............................................................................................
13-79. DISPC_SYSSTS Register..............................................................................................
13-80. DISPC_IRQSTS Register ..............................................................................................
13-81. DISPC_IRQEN Register ................................................................................................
13-82. DISPC_CTRL Register .................................................................................................
13-83. DISPC_CFG Register ..................................................................................................
13-84. DISPC_DEFAULT_COLOR_0 Register ..............................................................................
13-85. DISPC_TRANS_COLOR_0 Register .................................................................................
13-86. DISPC_LINE_STS Register ...........................................................................................
13-87. DISPC_LINE_NUMBER Register .....................................................................................
13-88. DISPC_TIMING_H Register ...........................................................................................
13-89. DISPC_TIMING_V Register ...........................................................................................
13-90. DISPC_POL_FREQ Register ..........................................................................................
13-91. DISPC_DIVISOR Register .............................................................................................
13-92. DISPC_GLOBAL_ALPHA Register ...................................................................................
13-93. DISPC_SIZE_DIG Register ............................................................................................
13-94. DISPC_SIZE_LCD Register ...........................................................................................
13-95. DISPC_GFX_BA_0 Register...........................................................................................
13-96. DISPC_GFX_POSITION Register ....................................................................................
13-97. DISPC_GFX_SIZE Register ...........................................................................................
13-98. DISPC_GFX_ATTRS Register ........................................................................................
13-99. DISPC_GFX_FIFO_THR Register ....................................................................................
13-100. DISPC_GFX_FIFO_SIZE_STS Register ...........................................................................
13-52. Color Phase Rotation Macro Architecture
SPRUHL7I – April 2014 – Revised December 2019
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List of Figures
1978
1981
1991
1992
1992
1993
2000
2002
2004
2004
2004
2004
2005
2005
2006
2007
2015
2016
2017
2018
2019
2020
2021
2022
2033
2037
2038
2040
2041
2044
2046
2049
2052
2053
2054
2055
2056
2057
2058
2060
2061
2062
2063
2064
2065
2066
2067
2069
2070
41
www.ti.com
13-101. DISPC_GFX_ROW_INC Register ................................................................................... 2071
13-102. DISPC_GFX_PIXEL_INC Register .................................................................................. 2072
13-103. DISPC_GFX_WINDOW_SKIP Register ............................................................................ 2073
13-104. DISPC_GFX_TBL_BA Register ...................................................................................... 2074
13-105. DISPC_VID1_BA_0 to DISPC_VID1_BA_1 Register ............................................................. 2075
..................................................................................
DISPC_VID1_SIZE Register .........................................................................................
DISPC_VID1_ATTRS Register ......................................................................................
DISPC_VID1_FIFO_THR Register ..................................................................................
DISPC_VID1_FIFO_SIZE_STS Register ...........................................................................
DISPC_VID1_ROW_INC Register...................................................................................
DISPC_VID1_PIXEL_INC Register .................................................................................
DISPC_VID1_FIR Register ...........................................................................................
DISPC_VID1_PICTURE_SIZE Register ............................................................................
DISPC_VID1_ACCU_0 to DISPC_VID1_ACCU_1 Register .....................................................
DISPC_VID1_FIR_COEF_H_0 Register............................................................................
DISPC_VID1_FIR_COEF_HV_0 Register ..........................................................................
DISPC_VID1_CONV_COEF0 Register .............................................................................
DISPC_VID1_CONV_COEF1 Register .............................................................................
DISPC_VID1_CONV_COEF2 Register .............................................................................
DISPC_VID1_CONV_COEF3 Register .............................................................................
DISPC_VID1_CONV_COEF4 Register .............................................................................
DISPC_VID2_BA_0 to DISPC_VID2_BA_1 Register .............................................................
DISPC_VID2_POSITION Register ..................................................................................
DISPC_VID2_SIZE Register .........................................................................................
DISPC_VID2_ATTRS Register ......................................................................................
DISPC_VID2_FIFO_THR Register ..................................................................................
DISPC_VID2_FIFO_SIZE_STS Register ...........................................................................
DISPC_VID2_ROW_INC Register...................................................................................
DISPC_VID2_PIXEL_INC Register .................................................................................
DISPC_VID2_FIR Register ...........................................................................................
DISPC_VID2_PICTURE_SIZE Register ............................................................................
DISPC_VID2_ACCU_0 to DISPC_VID2_ACCU_1 Register .....................................................
DISPC_VID2_FIR_COEF_H_0 Register............................................................................
DISPC_VID2_FIR_COEF_HV_0 Register ..........................................................................
DISPC_VID2_CONV_COEF0 Register .............................................................................
DISPC_VID2_CONV_COEF1 Register .............................................................................
DISPC_VID2_CONV_COEF2 Register .............................................................................
DISPC_VID2_CONV_COEF3 Register .............................................................................
DISPC_VID2_CONV_COEF4 Register .............................................................................
DISPC_DATA_CYCLE_0 Register ..................................................................................
DISPC_VID1_FIR_COEF_V_0 to DISPC_VID1_FIR_COEF_V_7 Register ...................................
DISPC_VID2_FIR_COEF_V_0 to DISPC_VID2_FIR_COEF_V_7 Register ...................................
DISPC_CPR_COEF_R Register .....................................................................................
DISPC_CPR_COEF_G Register ....................................................................................
DISPC_CPR_COEF_B Register .....................................................................................
DISPC_GFX_PRELOAD Register ...................................................................................
DISPC_VID1_PRELOAD Register ..................................................................................
DISPC_VID2_PRELOAD Register ..................................................................................
13-106. DISPC_VID1_POSITION Register
13-107.
13-108.
13-109.
13-110.
13-111.
13-112.
13-113.
13-114.
13-115.
13-116.
13-117.
13-118.
13-119.
13-120.
13-121.
13-122.
13-123.
13-124.
13-125.
13-126.
13-127.
13-128.
13-129.
13-130.
13-131.
13-132.
13-133.
13-134.
13-135.
13-136.
13-137.
13-138.
13-139.
13-140.
13-141.
13-142.
13-143.
13-144.
13-145.
13-146.
13-147.
13-148.
13-149.
42
List of Figures
2076
2077
2078
2081
2082
2083
2084
2085
2086
2087
2088
2089
2090
2091
2092
2093
2094
2095
2096
2097
2098
2101
2102
2103
2104
2105
2106
2107
2108
2109
2110
2111
2112
2113
2114
2115
2116
2117
2118
2119
2120
2121
2122
2123
SPRUHL7I – April 2014 – Revised December 2019
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13-150. DSS_REVISIONNUMBER Register ................................................................................. 2124
13-151. DSS_SYSCONFIG Register .......................................................................................... 2125
13-152. DSS_SYSSTS Register ............................................................................................... 2126
...............................................................................................
13-154. DSS_CTRL Register ..................................................................................................
13-155. DSS_CLK_STS Register .............................................................................................
13-156. RFBI_REVISION Register ............................................................................................
13-157. RFBI_SYSCONFIG Register .........................................................................................
13-158. RFBI_SYSSTS Register ..............................................................................................
13-159. RFBI_CTRL Register ..................................................................................................
13-160. RFBI_PIXEL_CNT Register ..........................................................................................
13-161. RFBI_LINE_NUMBER Register ......................................................................................
13-162. RFBI_CMD Register ...................................................................................................
13-163. RFBI_PARAM Register ...............................................................................................
13-164. RFBI_DATA Register ..................................................................................................
13-165. RFBI_READ Register .................................................................................................
13-166. RFBI_STS Register ....................................................................................................
13-167. RFBI_CONFIG_0 Register ...........................................................................................
13-168. RFBI_ONOFF_TIME_0 Register ....................................................................................
13-169. RFBI_CYCLE_TIME_0 Register .....................................................................................
13-170. RFBI_DATA_CYCLE1_0 Register ...................................................................................
13-171. RFBI_DATA_CYCLE2_0 Register ...................................................................................
13-172. RFBI_DATA_CYCLE3_0 Register ...................................................................................
13-173. RFBI_VSYNC_WIDTH Register .....................................................................................
13-174. RFBI_HSYNC_WIDTH Register .....................................................................................
14-1. VPFE Integration ........................................................................................................
14-2. CCD Controller Frame and Control Signal Definitions .............................................................
14-3. BT.656 Signal Interface ................................................................................................
14-4. Data Processing in Raw Data Mode ..................................................................................
14-5. Color Patterns ...........................................................................................................
14-6. Input Formatter ..........................................................................................................
14-7. Optical Black Averaging & Application ...............................................................................
14-8. Black Clamping and Black Level Compensation ....................................................................
14-9. Output Formatter ........................................................................................................
14-10. A-Law Table..............................................................................................................
14-11. Image De-interfacing ....................................................................................................
14-12. Non-inversed vs Inversed Format .....................................................................................
14-13. Data Processing in YUV/BT656 Modes ..............................................................................
14-14. CCD Controller ..........................................................................................................
14-15. Black Clamping and Block Level Compensation ....................................................................
14-16. Output Formatter ........................................................................................................
14-17. VDPOL is 0...............................................................................................................
14-18. VDPOL is 1...............................................................................................................
14-19. CCDC_VD2_INT Interrupt..............................................................................................
14-20. VPFE_REVISION Register ............................................................................................
14-21. VPFE_PCR Register ....................................................................................................
14-22. VPFE_SYNMODE Register ............................................................................................
14-23. VPFE_HD_VD_WID Register .........................................................................................
14-24. VPFE_PIX_LINES Register ............................................................................................
13-153. DSS_IRQSTS Register
SPRUHL7I – April 2014 – Revised December 2019
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List of Figures
2127
2128
2129
2131
2132
2133
2134
2136
2137
2138
2139
2140
2141
2142
2143
2145
2146
2147
2148
2149
2150
2151
2154
2158
2159
2162
2162
2163
2164
2165
2166
2167
2171
2172
2174
2175
2175
2176
2179
2179
2179
2182
2183
2184
2186
2187
43
www.ti.com
14-25. VPFE_HORZ_INFO Register .......................................................................................... 2188
14-26. VPFE_VERT_START Register ........................................................................................ 2189
14-27. VPFE_VERT_LINES Register ......................................................................................... 2190
14-28. VPFE_CULLING Register .............................................................................................. 2191
14-29. VPFE_HSIZE_OFF Register........................................................................................... 2192
2193
14-31.
2195
14-32.
14-33.
14-34.
14-35.
14-36.
14-37.
14-38.
14-39.
14-40.
14-41.
14-42.
14-43.
14-44.
14-45.
14-46.
14-47.
15-1.
15-2.
15-3.
15-4.
15-5.
15-6.
15-7.
15-8.
15-9.
15-10.
15-11.
15-12.
15-13.
15-14.
15-15.
15-16.
15-17.
15-18.
15-19.
15-20.
15-21.
15-22.
15-23.
15-24.
15-25.
15-26.
44
..............................................................................................
VPFE_SDR_ADDR Register...........................................................................................
VPFE_CLAMP Register ................................................................................................
VPFE_DCSUB Register ................................................................................................
VPFE_COLPTN Register ..............................................................................................
VPFE_BLKCMP Register ..............................................................................................
VPFE_VDINT Register .................................................................................................
VPFE_ALAW Register ..................................................................................................
VPFE_REC656IF Register .............................................................................................
VPFE_CCDCFG Register ..............................................................................................
VPFE_DMA_CNTL Register ...........................................................................................
VPFE_SYSCONFIG Register .........................................................................................
VPFE_CONFIG Register ...............................................................................................
VPFE_IRQ_EOI Register ..............................................................................................
VPFE_IRQ_STS_RAW Register ......................................................................................
VPFE_IRQ_STS Register ..............................................................................................
VPFE_IRQ_EN_SET Register.........................................................................................
VPFE_IRQ_EN_CLR Register ........................................................................................
Ethernet Switch Integration ............................................................................................
Ethernet Switch RMII Clock Detail ....................................................................................
MII Interface Connections ..............................................................................................
RMII Interface Connections ............................................................................................
RGMII Interface Connections ..........................................................................................
CPSW_3G Block Diagram .............................................................................................
Tx Buffer Descriptor Format ...........................................................................................
Rx Buffer Descriptor Format ...........................................................................................
VLAN Header Encapsulation Word ...................................................................................
CPTS Block Diagram ...................................................................................................
Event FIFO Misalignment Condition ..................................................................................
HW1/4_TSP_PUSH Connection ......................................................................................
Port TX State RAM Entry...............................................................................................
Port RX DMA State .....................................................................................................
CPSW_ALE_IDVER Register .........................................................................................
CPSW_ALE_CTRL Register ...........................................................................................
CPSW_ALE_PRESCALE Register ...................................................................................
CPSW_ALE_UNKNOWN_VLAN Register ...........................................................................
CPSW_ALE_TBLCTL Register ........................................................................................
CPSW_ALE_TBLW2 Register .........................................................................................
CPSW_ALE_TBLW1 Register .........................................................................................
CPSW_ALE_TBLW0 Register .........................................................................................
CPSW_ALE_PORTCTL_0 to CPSW_ALE_PORTCTL_5 Register ..............................................
CPSW_TX_IDVER Register ...........................................................................................
CPSW_TX_CTRL Register ............................................................................................
CPSW_TX_TEARDOWN Register ....................................................................................
14-30. VPFE_SDOFST Register
List of Figures
2196
2198
2199
2201
2202
2203
2204
2205
2207
2208
2210
2211
2212
2213
2214
2215
2219
2223
2224
2226
2227
2235
2240
2243
2247
2280
2282
2283
2289
2290
2294
2295
2297
2298
2299
2300
2301
2302
2303
2306
2307
2308
SPRUHL7I – April 2014 – Revised December 2019
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15-27. CPSW_RX_IDVER Register ........................................................................................... 2309
15-28. CPSW_RX_CTRL Register ............................................................................................ 2310
...................................................................................
...........................................................................
CPSW_DMACTRL Register ...........................................................................................
CPSW_DMASTS Register .............................................................................................
CPSW_RX_BUFFER_OFFSET Register ............................................................................
CPSW_EMCTRL Register .............................................................................................
CPSW_TX_PRI0_RATE Register .....................................................................................
CPSW_TX_PRI1_RATE Register .....................................................................................
CPSW_TX_PRI2_RATE Register .....................................................................................
CPSW_TX_PRI3_RATE Register .....................................................................................
CPSW_TX_PRI4_RATE Register .....................................................................................
CPSW_TX_PRI5_RATE Register .....................................................................................
CPSW_TX_PRI6_RATE Register .....................................................................................
CPSW_TX_PRI7_RATE Register .....................................................................................
CPSW_TX_INTSTAT_RAW Register ................................................................................
CPSW_TX_INTSTAT_MASKED Register ...........................................................................
CPSW_TX_INTMASK_SET Register .................................................................................
CPSW_TX_INTMASK_CLR Register ................................................................................
CPSW_CPDMA_IN_VECTOR Register ..............................................................................
CPSW_CPDMA_EOI_VECTOR Register ............................................................................
CPSW_RX_INTSTAT_RAW Register ................................................................................
CPSW_RX_INTSTAT_MASKED Register ...........................................................................
CPSW_RX_INTMASK_SET Register ................................................................................
CPSW_RX_INTMASK_CLR Register ................................................................................
CPSW_DMA_INTSTAT_RAW Register ..............................................................................
CPSW_DMA_INTSTAT_MASKED Register .........................................................................
CPSW_DMA_INTMASK_SET Register ..............................................................................
CPSW_DMA_INTMASK_CLR Register ..............................................................................
CPSW_RX0_PENDTHRESH Register ...............................................................................
CPSW_RX1_PENDTHRESH Register ...............................................................................
CPSW_RX2_PENDTHRESH Register ...............................................................................
CPSW_RX3_PENDTHRESH Register ...............................................................................
CPSW_RX4_PENDTHRESH Register ...............................................................................
CPSW_RX5_PENDTHRESH Register ...............................................................................
CPSW_RX6_PENDTHRESH Register ...............................................................................
CPSW_RX7_PENDTHRESH Register ...............................................................................
CPSW_RX0_FREEBUFFER Register................................................................................
CPSW_RX1_FREEBUFFER Register................................................................................
CPSW_RX2_FREEBUFFER Register................................................................................
CPSW_RX3_FREEBUFFER Register................................................................................
CPSW_RX4_FREEBUFFER Register................................................................................
CPSW_RX5_FREEBUFFER Register................................................................................
CPSW_RX6_FREEBUFFER Register................................................................................
CPSW_RX7_FREEBUFFER Register................................................................................
CPSW_CPTS_IDVER Register .......................................................................................
CPSW_CPTS_CTRL Register.........................................................................................
CPSW_RFTCLK_SEL Register .......................................................................................
15-29. CPSW_RX_TEARDOWN Register
2311
15-30. CPSW_CPDMA_SOFT_RESET Register
2312
15-31.
15-32.
15-33.
15-34.
15-35.
15-36.
15-37.
15-38.
15-39.
15-40.
15-41.
15-42.
15-43.
15-44.
15-45.
15-46.
15-47.
15-48.
15-49.
15-50.
15-51.
15-52.
15-53.
15-54.
15-55.
15-56.
15-57.
15-58.
15-59.
15-60.
15-61.
15-62.
15-63.
15-64.
15-65.
15-66.
15-67.
15-68.
15-69.
15-70.
15-71.
15-72.
15-73.
15-74.
15-75.
SPRUHL7I – April 2014 – Revised December 2019
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Copyright © 2014–2019, Texas Instruments Incorporated
List of Figures
2313
2315
2317
2318
2319
2320
2321
2322
2323
2324
2325
2326
2327
2328
2329
2330
2331
2332
2333
2334
2335
2336
2337
2338
2339
2340
2341
2342
2343
2344
2345
2346
2347
2348
2349
2350
2351
2352
2353
2354
2355
2356
2357
2358
2359
45
www.ti.com
15-76. CPSW_CPTS_PUSH Register ........................................................................................ 2360
15-77. CPSW_CPTS_LOAD_VAL Register .................................................................................. 2361
15-78. CPSW_CPTS_LOAD_EN Register ................................................................................... 2362
15-79. CPSW_CPTS_COMP_VAL Register ................................................................................. 2363
15-80. CPSW_CPTS_COMP_LENGTH Register ........................................................................... 2364
15-81. CPSW_CPTS_INTSTAT_RAW Register............................................................................. 2365
15-82. CPSW_CPTS_INTSTAT_MASKED Register
.......................................................................
2366
15-83. CPSW_CPTS_INT_EN Register ...................................................................................... 2367
15-84. CPSW_CPTS_EVT_POP Register ................................................................................... 2368
15-85. CPSW_CPTS_EVT_LOW Register ................................................................................... 2369
15-86. CPSW_CPTS_EVT_MID Register .................................................................................... 2370
15-87. CPSW_CPTS_EVT_HIGH Register .................................................................................. 2371
15-88. CPSW_STATERAM_TX0_HDP Register ............................................................................ 2375
15-89. CPSW_STATERAM_TX1_HDP Register ............................................................................ 2376
15-90. CPSW_STATERAM_TX2_HDP Register ............................................................................ 2377
15-91. CPSW_STATERAM_TX3_HDP Register ............................................................................ 2378
15-92. CPSW_STATERAM_TX4_HDP Register ............................................................................ 2379
15-93. CPSW_STATERAM_TX5_HDP Register ............................................................................ 2380
15-94. CPSW_STATERAM_TX6_HDP Register ............................................................................ 2381
15-95. CPSW_STATERAM_TX7_HDP Register ............................................................................ 2382
15-96. CPSW_STATERAM_RX0_HDP Register ............................................................................ 2383
15-97. CPSW_STATERAM_RX1_HDP Register ............................................................................ 2384
15-98. CPSW_STATERAM_RX2_HDP Register ............................................................................ 2385
15-99. CPSW_STATERAM_RX3_HDP Register ............................................................................ 2386
15-100. CPSW_STATERAM_RX4_HDP Register .......................................................................... 2387
15-101. CPSW_STATERAM_RX5_HDP Register .......................................................................... 2388
15-102. CPSW_STATERAM_RX6_HDP Register .......................................................................... 2389
15-103. CPSW_STATERAM_RX7_HDP Register .......................................................................... 2390
15-104. CPSW_STATERAM_TX0_CP Register............................................................................. 2391
15-105. CPSW_STATERAM_TX1_CP Register............................................................................. 2392
15-106. CPSW_STATERAM_TX2_CP Register............................................................................. 2393
15-107. CPSW_STATERAM_TX3_CP Register............................................................................. 2394
15-108. CPSW_STATERAM_TX4_CP Register............................................................................. 2395
15-109. CPSW_STATERAM_TX5_CP Register............................................................................. 2396
15-110. CPSW_STATERAM_TX6_CP Register............................................................................. 2397
15-111. CPSW_STATERAM_TX7_CP Register............................................................................. 2398
15-112. CPSW_STATERAM_RX0_CP Register ............................................................................ 2399
15-113. CPSW_STATERAM_RX1_CP Register ............................................................................ 2400
15-114. CPSW_STATERAM_RX2_CP Register ............................................................................ 2401
15-115. CPSW_STATERAM_RX3_CP Register ............................................................................ 2402
15-116. CPSW_STATERAM_RX4_CP Register ............................................................................ 2403
15-117. CPSW_STATERAM_RX5_CP Register ............................................................................ 2404
15-118. CPSW_STATERAM_RX6_CP Register ............................................................................ 2405
15-119. CPSW_STATERAM_RX7_CP Register ............................................................................ 2406
15-120. CPSW_PORT_P0_CTRL Register .................................................................................. 2409
15-121. CPSW_PORT_P0_MAX_BLKS Register ........................................................................... 2410
15-122. CPSW_PORT_P0_BLK_CNT Register ............................................................................. 2411
15-123. CPSW_PORT_P0_TX_IN_CTL Register ........................................................................... 2412
15-124. CPSW_PORT_P0_VLAN Register .................................................................................. 2413
46
List of Figures
SPRUHL7I – April 2014 – Revised December 2019
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........................................................................
CPSW_PORT_P0_CPDMA_TX_PRI_MAP Register .............................................................
CPSW_PORT_P0_CPDMA_RX_CH_MAP Register .............................................................
CPSW_PORT_P0_RX_DSCP_PRI_MAP0 Register..............................................................
CPSW_PORT_P0_RX_DSCP_PRI_MAP1 Register..............................................................
CPSW_PORT_P0_RX_DSCP_PRI_MAP2 Register..............................................................
CPSW_PORT_P0_RX_DSCP_PRI_MAP3 Register..............................................................
CPSW_PORT_P0_RX_DSCP_PRI_MAP4 Register..............................................................
CPSW_PORT_P0_RX_DSCP_PRI_MAP5 Register..............................................................
CPSW_PORT_P0_RX_DSCP_PRI_MAP6 Register..............................................................
CPSW_PORT_P0_RX_DSCP_PRI_MAP7 Register..............................................................
CPSW_PORT_P1_CTRL Register ..................................................................................
CPSW_PORT_P1_TS_CTL2 Register ..............................................................................
CPSW_PORT_P1_MAX_BLKS Register ...........................................................................
CPSW_PORT_P1_BLK_CNT Register .............................................................................
CPSW_PORT_P1_TX_IN_CTL Register ...........................................................................
CPSW_PORT_P1_VLAN Register ..................................................................................
CPSW_PORT_P1_TX_PRI_MAP Register ........................................................................
CPSW_PORT_P1_TS_SEQ_MTYPE Register ....................................................................
CPSW_PORT_P1_SA_LO Register ................................................................................
CPSW_PORT_P1_SA_HI Register .................................................................................
CPSW_PORT_P1_SEND_PERCENT Register ...................................................................
CPSW_PORT_P1_RX_DSCP_PRI_MAP0 Register..............................................................
CPSW_PORT_P1_RX_DSCP_PRI_MAP1 Register..............................................................
CPSW_PORT_P1_RX_DSCP_PRI_MAP2 Register..............................................................
CPSW_PORT_P1_RX_DSCP_PRI_MAP3 Register..............................................................
CPSW_PORT_P1_RX_DSCP_PRI_MAP4 Register..............................................................
CPSW_PORT_P1_RX_DSCP_PRI_MAP5 Register..............................................................
CPSW_PORT_P1_RX_DSCP_PRI_MAP6 Register..............................................................
CPSW_PORT_P1_RX_DSCP_PRI_MAP7 Register..............................................................
CPSW_PORT_P2_CTRL Register ..................................................................................
CPSW_PORT_P2_TS_CTL2 Register ..............................................................................
CPSW_PORT_P2_MAX_BLKS Register ...........................................................................
CPSW_PORT_P2_BLK_CNT Register .............................................................................
CPSW_PORT_P2_TX_IN_CTL Register ...........................................................................
CPSW_PORT_P2_VLAN Register ..................................................................................
CPSW_PORT_P2_TX_PRI_MAP Register ........................................................................
CPSW_PORT_P2_TS_SEQ_MTYPE Register ....................................................................
CPSW_PORT_P2_SA_LO Register ................................................................................
CPSW_PORT_P2_SA_HI Register .................................................................................
CPSW_PORT_P2_SEND_PERCENT Register ...................................................................
CPSW_PORT_P2_RX_DSCP_PRI_MAP0 Register..............................................................
CPSW_PORT_P2_RX_DSCP_PRI_MAP1 Register..............................................................
CPSW_PORT_P2_RX_DSCP_PRI_MAP2 Register..............................................................
CPSW_PORT_P2_RX_DSCP_PRI_MAP3 Register..............................................................
CPSW_PORT_P2_RX_DSCP_PRI_MAP4 Register..............................................................
CPSW_PORT_P2_RX_DSCP_PRI_MAP5 Register..............................................................
CPSW_PORT_P2_RX_DSCP_PRI_MAP6 Register..............................................................
CPSW_PORT_P2_RX_DSCP_PRI_MAP7 Register..............................................................
15-125. CPSW_PORT_P0_TX_PRI_MAP Register
15-126.
15-127.
15-128.
15-129.
15-130.
15-131.
15-132.
15-133.
15-134.
15-135.
15-136.
15-137.
15-138.
15-139.
15-140.
15-141.
15-142.
15-143.
15-144.
15-145.
15-146.
15-147.
15-148.
15-149.
15-150.
15-151.
15-152.
15-153.
15-154.
15-155.
15-156.
15-157.
15-158.
15-159.
15-160.
15-161.
15-162.
15-163.
15-164.
15-165.
15-166.
15-167.
15-168.
15-169.
15-170.
15-171.
15-172.
15-173.
SPRUHL7I – April 2014 – Revised December 2019
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Copyright © 2014–2019, Texas Instruments Incorporated
List of Figures
2414
2415
2416
2417
2418
2419
2420
2421
2422
2423
2424
2425
2427
2428
2429
2430
2431
2432
2433
2434
2435
2436
2437
2438
2439
2440
2441
2442
2443
2444
2445
2447
2448
2449
2450
2451
2452
2453
2454
2455
2456
2457
2458
2459
2460
2461
2462
2463
2464
47
www.ti.com
15-174. CPSW_SL_IDVER Register .......................................................................................... 2466
15-175. CPSW_SL_MACCTRL Register ..................................................................................... 2467
15-176. CPSW_SL_MACSTS Register ....................................................................................... 2470
2471
15-178.
2472
15-179.
15-180.
15-181.
15-182.
15-183.
15-184.
15-185.
15-186.
15-187.
15-188.
15-189.
15-190.
15-191.
15-192.
15-193.
15-194.
15-195.
15-196.
15-197.
15-198.
15-199.
15-200.
15-201.
15-202.
15-203.
15-204.
15-205.
15-206.
15-207.
15-208.
15-209.
15-210.
15-211.
15-212.
15-213.
15-214.
15-215.
15-216.
15-217.
15-218.
15-219.
15-220.
15-221.
15-222.
48
................................................................................
CPSW_SL_RX_MAXLEN Register ..................................................................................
CPSW_SL_BOFFTEST Register ....................................................................................
CPSW_SL_RX_PAUSE Register ....................................................................................
CPSW_SL_TX_PAUSE Register ....................................................................................
CPSW_SL_EMCTRL Register .......................................................................................
CPSW_SL_RX_PRI_MAP Register .................................................................................
CPSW_SL_TX_GAP Register .......................................................................................
CPSW_SS_ID_VER Register ........................................................................................
CPSW_SS_CTRL Register ...........................................................................................
CPSW_SS_SOFT_RESET Register ................................................................................
CPSW_SS_STAT_PORT_EN Register .............................................................................
CPSW_SS_PTYPE Register .........................................................................................
CPSW_SS_SOFT_IDLE Register ...................................................................................
CPSW_SS_THRU_RATE Register ..................................................................................
CPSW_SS_GAP_THRESH Register................................................................................
CPSW_SS_TX_START_WDS Register ............................................................................
CPSW_SS_FLOW_CTRL Register..................................................................................
CPSW_SS_VLAN_LTYPE Register .................................................................................
CPSW_SS_TS_LTYPE Register ....................................................................................
CPSW_SS_DLR_LTYPE Register ..................................................................................
CPSW_SS_STS Register .............................................................................................
CPSW_WR_IDVER Register .........................................................................................
CPSW_WR_SOFT_RESET Register ...............................................................................
CPSW_WR_CTRL Register ..........................................................................................
CPSW_WR_INT_CTRL Register ....................................................................................
CPSW_WR_C0_RX_THRESH_EN Register ......................................................................
CPSW_WR_C0_RX_EN Register ...................................................................................
CPSW_WR_C0_TX_EN Register ...................................................................................
CPSW_WR_C0_MISC_EN Register ................................................................................
CPSW_WR_C1_RX_THRESH_EN Register ......................................................................
CPSW_WR_C1_RX_EN Register ...................................................................................
CPSW_WR_C1_TX_EN Register ...................................................................................
CPSW_WR_C1_MISC_EN Register ................................................................................
CPSW_WR_C2_RX_THRESH_EN Register ......................................................................
CPSW_WR_C2_RX_EN Register ...................................................................................
CPSW_WR_C2_TX_EN Register ...................................................................................
CPSW_WR_C2_MISC_EN Register ................................................................................
CPSW_WR_C0_RX_THRESH_STAT Register ...................................................................
CPSW_WR_C0_RX_STAT Register ................................................................................
CPSW_WR_C0_TX_STAT Register ................................................................................
CPSW_WR_C0_MISC_STAT Register .............................................................................
CPSW_WR_C1_RX_THRESH_STAT Register ...................................................................
CPSW_WR_C1_RX_STAT Register ................................................................................
CPSW_WR_C1_TX_STAT Register ................................................................................
CPSW_WR_C1_MISC_STAT Register .............................................................................
15-177. CPSW_SL_SOFT_RESET Register
List of Figures
2473
2474
2475
2476
2477
2478
2479
2480
2481
2482
2483
2484
2485
2486
2487
2488
2489
2490
2491
2492
2494
2495
2496
2497
2498
2499
2500
2501
2502
2503
2504
2505
2506
2507
2508
2509
2510
2511
2512
2513
2514
2515
2516
2517
SPRUHL7I – April 2014 – Revised December 2019
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15-223. CPSW_WR_C2_RX_THRESH_STAT Register ................................................................... 2518
15-224. CPSW_WR_C2_RX_STAT Register ................................................................................ 2519
15-225. CPSW_WR_C2_TX_STAT Register ................................................................................ 2520
15-226. CPSW_WR_C2_MISC_STAT Register ............................................................................. 2521
15-227. CPSW_WR_C0_RX_IMAX Register ................................................................................ 2522
................................................................................
15-229. CPSW_WR_C1_RX_IMAX Register ................................................................................
15-230. CPSW_WR_C1_TX_IMAX Register ................................................................................
15-231. CPSW_WR_C2_RX_IMAX Register ................................................................................
15-232. CPSW_WR_C2_TX_IMAX Register ................................................................................
15-233. CPSW_WR_RGMII_CTL Register...................................................................................
15-234. MDIO_VER Register ..................................................................................................
15-235. MDIO_CTRL Register .................................................................................................
15-236. MDIO_ALIVE Register ................................................................................................
15-237. MDIO_LINK Register ..................................................................................................
15-238. MDIO_LINKINTRAW Register .......................................................................................
15-239. MDIO_LINKINTMASKED Register ..................................................................................
15-240. MDIO_USERINTRAW Register ......................................................................................
15-241. MDIO_USERINTMASKED Register .................................................................................
15-242. MDIO_USERINTMASKSET Register ...............................................................................
15-243. MDIO_USERINTMASKCLR Register ...............................................................................
15-244. MDIO_USERACCESS0 Register ....................................................................................
15-245. MDIO_USERPHYSEL0 Register ....................................................................................
15-246. MDIO_USERACCESS1 Register ....................................................................................
15-247. MDIO_USERPHYSEL1 Register ....................................................................................
16-1. USB 2.0 Subsystem (USB2SS) Functional Block Diagram ........................................................
16-2. USB Dual-Role (Host or Device) ......................................................................................
16-3. USB Host Only...........................................................................................................
16-4. USB Device Only ........................................................................................................
17-1. MMCSD Module SDIO Application....................................................................................
17-2. MMCSD (4-bit) Card Application ......................................................................................
17-3. MMCSD Module MMC Application ....................................................................................
17-4. MMC/SD1/2 Connectivity to an MMC/SD Card .....................................................................
17-5. MMC/SD0 Connectivity to an MMC/SD Card........................................................................
17-6. Sequential Read Operation (MMC Cards Only) .....................................................................
17-7. Sequential Write Operation (MMC Cards Only) .....................................................................
17-8. Multiple Block Read Operation (MMC Cards Only) ................................................................
17-9. Multiple Block Write Operation (MMC Cards Only) ................................................................
17-10. Command Token Format ...............................................................................................
17-11. 48-Bit Response Packet (R1, R3, R4, R5, R6) ......................................................................
17-12. 136-Bit Response Packet (R2) ........................................................................................
17-13. Data Packet for Sequential Transfer (1-Bit) .........................................................................
17-14. Data Packet for Block Transfer (1-Bit) ...............................................................................
17-15. Data Packet for Block Transfer (4-Bit) ................................................................................
17-16. Data Packet for Block Transfer (8-Bit) ................................................................................
17-17. DMA Receive Mode .....................................................................................................
17-18. DMA Transmit Mode ....................................................................................................
17-19. Buffer Management for a Write ........................................................................................
17-20. Buffer Management for a Read .......................................................................................
15-228. CPSW_WR_C0_TX_IMAX Register
SPRUHL7I – April 2014 – Revised December 2019
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Copyright © 2014–2019, Texas Instruments Incorporated
List of Figures
2523
2524
2525
2526
2527
2528
2530
2531
2533
2534
2535
2536
2537
2538
2539
2540
2541
2542
2543
2544
2547
2550
2550
2550
2554
2554
2555
2558
2558
2560
2560
2561
2561
2562
2562
2562
2563
2563
2563
2564
2571
2572
2574
2575
49
www.ti.com
17-21. Busy Timeout for R1b, R5b Responses .............................................................................. 2578
17-22. Busy Timeout After Write CRC Status
...............................................................................
2578
17-23. Write CRC Status Timeout ............................................................................................. 2579
17-24. Read Data Timeout ..................................................................................................... 2579
17-25. Boot Acknowledge Timeout When Using CMD0 .................................................................... 2580
17-26. Boot Acknowledge Timeout When CMD Held Low ................................................................. 2580
17-27. Auto CMD12 Timing During Write Transfer .......................................................................... 2582
17-28. Auto Command 12 Timings During Read Transfer ................................................................. 2583
........................................................................................
Output Driven on Rising Edge .........................................................................................
Boot Mode With CMD0 .................................................................................................
Boot Mode With CMD Line Tied to 0 .................................................................................
MMC/SD/SDIO Controller Software Reset Flow ....................................................................
MMC/SD/SDIO Controller Bus Configuration Flow .................................................................
MMC/SD/SDIO Controller Card Identification and Selection - Part 1 ............................................
MMC/SD/SDIO Controller Card Identification and Selection - Part 2 ............................................
SD_SYSCONFIG Register .............................................................................................
SD_SYSSTATUS Register .............................................................................................
SD_CSRE Register .....................................................................................................
SD_SYSTEST Register ................................................................................................
SD_CON Register .......................................................................................................
SD_PWCNT Register ...................................................................................................
SD_SDMASA Register .................................................................................................
SD_BLK Register........................................................................................................
SD_ARG Register .......................................................................................................
SD_CMD Register.......................................................................................................
SD_RSP10 Register ....................................................................................................
SD_RSP32 Register ....................................................................................................
SD_RSP54 Register ....................................................................................................
SD_RSP76 Register ....................................................................................................
SD_DATA Register .....................................................................................................
SD_PSTATE Register ..................................................................................................
SD_HCTL Register ......................................................................................................
SD_SYSCTL Register ..................................................................................................
SD_STAT Register ......................................................................................................
SD_IE Register ..........................................................................................................
SD_ISE Register ........................................................................................................
SD_AC12 Register ......................................................................................................
SD_CAPA Register .....................................................................................................
SD_CUR_CAPA Register ..............................................................................................
SD_FE Register .........................................................................................................
SD_ADMAES Register .................................................................................................
SD_ADMASAL Register ................................................................................................
SD_ADMASAH Register ...............................................................................................
SD_REV Register .......................................................................................................
Mailbox Integration ......................................................................................................
Mailbox Block Diagram .................................................................................................
MLB_REVISION Register ..............................................................................................
MLB_SYSCONFIG Register ...........................................................................................
17-29. Output Driven on Falling Edge
17-30.
17-31.
17-32.
17-33.
17-34.
17-35.
17-36.
17-37.
17-38.
17-39.
17-40.
17-41.
17-42.
17-43.
17-44.
17-45.
17-46.
17-47.
17-48.
17-49.
17-50.
17-51.
17-52.
17-53.
17-54.
17-55.
17-56.
17-57.
17-58.
17-59.
17-60.
17-61.
17-62.
17-63.
17-64.
17-65.
18-1.
18-2.
18-3.
18-4.
50
List of Figures
2585
2586
2587
2588
2592
2593
2594
2595
2597
2599
2600
2601
2605
2609
2610
2611
2612
2613
2615
2616
2617
2618
2619
2620
2623
2626
2628
2633
2636
2639
2641
2643
2644
2646
2647
2648
2649
2652
2655
2662
2663
SPRUHL7I – April 2014 – Revised December 2019
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18-5.
MLB_MESSAGE_0 Register........................................................................................... 2664
18-6.
MLB_MESSAGE_1 Register........................................................................................... 2665
18-7.
MLB_MESSAGE_2 Register........................................................................................... 2666
18-8.
MLB_MESSAGE_3 Register........................................................................................... 2667
18-9.
MLB_MESSAGE_4 Register........................................................................................... 2668
18-10. MLB_MESSAGE_5 Register........................................................................................... 2669
18-11. MLB_MESSAGE_6 Register........................................................................................... 2670
18-12. MLB_MESSAGE_7 Register........................................................................................... 2671
............................................................................................
MLB_FIFOSTS_1 Register ............................................................................................
MLB_FIFOSTS_2 Register ............................................................................................
MLB_FIFOSTS_3 Register ............................................................................................
MLB_FIFOSTS_4 Register ............................................................................................
MLB_FIFOSTS_5 Register ............................................................................................
MLB_FIFOSTS_6 Register ............................................................................................
MLB_FIFOSTS_7 Register ............................................................................................
MLB_MSGSTS_0 Register ............................................................................................
MLB_MSGSTS_1 Register ............................................................................................
MLB_MSGSTS_2 Register ............................................................................................
MLB_MSGSTS_3 Register ............................................................................................
MLB_MSGSTS_4 Register ............................................................................................
MLB_MSGSTS_5 Register ............................................................................................
MLB_MSGSTS_6 Register ............................................................................................
MLB_MSGSTS_7 Register ............................................................................................
MLB_IRQSTS_RAW_0 Register ......................................................................................
MLB_IRQSTS_CLR_0 Register .......................................................................................
MLB_IRQEN_SET_0 Register.........................................................................................
MLB_IRQEN_CLR_0 Register ........................................................................................
MLB_IRQSTS_RAW_1 Register ......................................................................................
MLB_IRQSTS_CLR_1 Register .......................................................................................
MLB_IRQEN_SET_1 Register.........................................................................................
MLB_IRQEN_CLR_1 Register ........................................................................................
MLB_IRQSTS_RAW_2 Register ......................................................................................
MLB_IRQSTS_CLR_2 Register .......................................................................................
MLB_IRQEN_SET_2 Register.........................................................................................
MLB_IRQEN_CLR_2 Register ........................................................................................
MLB_IRQSTS_RAW_3 Register ......................................................................................
MLB_IRQSTS_CLR_3 Register .......................................................................................
MLB_IRQEN_SET_3 Register.........................................................................................
MLB_IRQEN_CLR_3 Register ........................................................................................
SPINLOCK_REV Register .............................................................................................
SPINLOCK_SYSCONFIG Register ...................................................................................
SPINLOCK_SYSTS Register ..........................................................................................
SPINLOCK_REG_0 Register ..........................................................................................
SPINLOCK_REG_1 Register ..........................................................................................
SPINLOCK_REG_2 Register ..........................................................................................
SPINLOCK_REG_3 Register ..........................................................................................
SPINLOCK_REG_4 Register ..........................................................................................
SPINLOCK_REG_5 Register ..........................................................................................
18-13. MLB_FIFOSTS_0 Register
2672
18-14.
2673
18-15.
18-16.
18-17.
18-18.
18-19.
18-20.
18-21.
18-22.
18-23.
18-24.
18-25.
18-26.
18-27.
18-28.
18-29.
18-30.
18-31.
18-32.
18-33.
18-34.
18-35.
18-36.
18-37.
18-38.
18-39.
18-40.
18-41.
18-42.
18-43.
18-44.
18-45.
18-46.
18-47.
18-48.
18-49.
18-50.
18-51.
18-52.
18-53.
SPRUHL7I – April 2014 – Revised December 2019
Submit Documentation Feedback
Copyright © 2014–2019, Texas Instruments Incorporated
List of Figures
2674
2675
2676
2677
2678
2679
2680
2681
2682
2683
2684
2685
2686
2687
2688
2690
2692
2694
2696
2698
2700
2702
2704
2706
2708
2710
2712
2714
2716
2718
2721
2722
2723
2724
2725
2726
2727
2728
2729
51
www.ti.com
18-54. SPINLOCK_REG_6 Register .......................................................................................... 2730
18-55. SPINLOCK_REG_7 Register .......................................................................................... 2731
18-56. SPINLOCK_REG_8 Register .......................................................................................... 2732
18-57. SPINLOCK_REG_9 Register .......................................................................................... 2733
2734
18-59. SPINLOCK_REG_11 Register
2735
18-60.
2736
18-61.
18-62.
18-63.
18-64.
18-65.
18-66.
18-67.
18-68.
18-69.
18-70.
18-71.
18-72.
18-73.
18-74.
18-75.
18-76.
18-77.
18-78.
18-79.
19-1.
19-2.
19-3.
19-4.
19-5.
19-6.
19-7.
19-8.
19-9.
19-10.
19-11.
19-12.
19-13.
19-14.
19-15.
19-16.
19-17.
19-18.
19-19.
19-20.
19-21.
19-22.
19-23.
52
........................................................................................
........................................................................................
SPINLOCK_REG_12 Register ........................................................................................
SPINLOCK_REG_13 Register ........................................................................................
SPINLOCK_REG_14 Register ........................................................................................
SPINLOCK_REG_15 Register ........................................................................................
SPINLOCK_REG_16 Register ........................................................................................
SPINLOCK_REG_17 Register ........................................................................................
SPINLOCK_REG_18 Register ........................................................................................
SPINLOCK_REG_19 Register ........................................................................................
SPINLOCK_REG_20 Register ........................................................................................
SPINLOCK_REG_21 Register ........................................................................................
SPINLOCK_REG_22 Register ........................................................................................
SPINLOCK_REG_23 Register ........................................................................................
SPINLOCK_REG_24 Register ........................................................................................
SPINLOCK_REG_25 Register ........................................................................................
SPINLOCK_REG_26 Register ........................................................................................
SPINLOCK_REG_27 Register ........................................................................................
SPINLOCK_REG_28 Register ........................................................................................
SPINLOCK_REG_29 Register ........................................................................................
SPINLOCK_REG_30 Register ........................................................................................
SPINLOCK_REG_31 Register ........................................................................................
Timer Block Diagram ...................................................................................................
Timer0 Integration .......................................................................................................
Timer2-7 Integration ....................................................................................................
Timer8-11 Integration ...................................................................................................
TCRR Timing Value .....................................................................................................
Capture Wave Example for CAPT_MODE = 0 ......................................................................
Capture Wave Example for CAPT_MODE = 1 ......................................................................
Timing Diagram of Pulse-Width Modulation with SCPWM = 0 ....................................................
Timing Diagram of Pulse-Width Modulation with SCPWM = 1 ....................................................
Timer Cascading Details ...............................................................................................
Timer Sync Event Detail ................................................................................................
DMTIMER_TIDR Register..............................................................................................
DMTIMER_TIOCP_CFG Register ....................................................................................
DMTIMER_IRQ_EOI Register .........................................................................................
DMTIMER_IRQSTS_RAW Register ..................................................................................
DMTIMER_IRQSTS Register ..........................................................................................
DMTIMER_IRQEN_SET Register.....................................................................................
DMTIMER_IRQEN_CLR Register ....................................................................................
DMTIMER_IRQWAKEEN Register ...................................................................................
DMTIMER_TCLR Register .............................................................................................
DMTIMER_TCRR Register ............................................................................................
DMTIMER_TLDR Register .............................................................................................
DMTIMER_TTGR Register ............................................................................................
18-58. SPINLOCK_REG_10 Register
List of Figures
2737
2738
2739
2740
2741
2742
2743
2744
2745
2746
2747
2748
2749
2750
2751
2752
2753
2754
2755
2758
2759
2760
2761
2764
2765
2766
2767
2768
2774
2775
2777
2778
2779
2780
2781
2782
2783
2784
2785
2787
2788
2789
SPRUHL7I – April 2014 – Revised December 2019
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19-24. DMTIMER_TWPS Register ............................................................................................ 2790
19-25. DMTIMER_TMAR Register ............................................................................................ 2791
19-26. DMTIMER_TCAR1 Register ........................................................................................... 2792
19-27. DMTIMER_TSICR Register ............................................................................................ 2793
19-28. DMTIMER_TCAR2 Register ........................................................................................... 2794
19-29. Block Diagram ........................................................................................................... 2796
19-30. DMTimer 1 ms Integration
.............................................................................................
2797
19-31. TCRR Timing Value ..................................................................................................... 2799
19-32. 1ms Module Block Diagram ............................................................................................ 2800
19-33. Capture Wave Example for CAPT_MODE 0 ........................................................................ 2802
19-34. Capture Wave Example for CAPT_MODE 1 ........................................................................ 2802
19-35. Timing Diagram of Pulse-Width Modulation, SCPWM Bit = 0 ..................................................... 2804
19-36. Timing Diagram of Pulse-Width Modulation, SCPWM Bit = 1 ..................................................... 2804
19-37. Wake-up Request Generation ......................................................................................... 2806
......................................................................................
.............................................................................
DMTIMER_1MS_TISTAT Register ...................................................................................
DMTIMER_1MS_TISR Register .......................................................................................
DMTIMER_1MS_TIER Register .......................................................................................
DMTIMER_1MS_TWER Register .....................................................................................
DMTIMER_1MS_TCLR Register ......................................................................................
DMTIMER_1MS_TCRR Register .....................................................................................
DMTIMER_1MS_TLDR Register ......................................................................................
DMTIMER_1MS_TTGR Register .....................................................................................
DMTIMER_1MS_TWPS Register .....................................................................................
DMTIMER_1MS_TMAR Register .....................................................................................
DMTIMER_1MS_TCAR1 Register ....................................................................................
DMTIMER_1MS_TSICR Register .....................................................................................
DMTIMER_1MS_TCAR2 Register ....................................................................................
DMTIMER_1MS_TPIR Register .......................................................................................
DMTIMER_1MS_TNIR Register ......................................................................................
DMTIMER_1MS_TCVR Register .....................................................................................
DMTIMER_1MS_TOCR Register .....................................................................................
DMTIMER_1MS_TOWR Register.....................................................................................
SyncTimer32K Integration..............................................................................................
Reset Resynchronization Timing ......................................................................................
SYNCTIMER32K_SYNCNT_REV Register..........................................................................
SYNCTIMER32K_SYSCONFIG Register ............................................................................
SYNCTIMER32K_CR Register ........................................................................................
RTC Integration ..........................................................................................................
RTC Block Diagram .....................................................................................................
RTC Functional Block Diagram........................................................................................
Kick Register State Machine Diagram ................................................................................
Flow Control for Updating RTC Registers ...........................................................................
Compensation Illustration ..............................................................................................
RTCSS_SECONDS_REG Register...................................................................................
RTCSS_MINUTES_REG Register ....................................................................................
RTCSS_HOURS_REG Register ......................................................................................
RTCSS_DAYS_REG Register.........................................................................................
19-38. DMTIMER_1MS_TIDR Register
2809
19-39. DMTIMER_1MS_TIOCP_CFG Register
2810
19-40.
2811
19-41.
19-42.
19-43.
19-44.
19-45.
19-46.
19-47.
19-48.
19-49.
19-50.
19-51.
19-52.
19-53.
19-54.
19-55.
19-56.
19-57.
19-58.
19-59.
19-60.
19-61.
19-62.
19-63.
19-64.
19-65.
19-66.
19-67.
19-68.
19-69.
19-70.
19-71.
19-72.
SPRUHL7I – April 2014 – Revised December 2019
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List of Figures
2812
2813
2814
2815
2817
2818
2819
2820
2822
2823
2824
2825
2826
2827
2828
2829
2830
2832
2835
2836
2837
2838
2840
2842
2842
2845
2847
2848
2852
2853
2854
2855
53
www.ti.com
19-73. RTCSS_MONTHS_REG Register .................................................................................... 2856
19-74. RTCSS_YEARS_REG Register ....................................................................................... 2857
19-75. RTCSS_WEEKS_REG Register ...................................................................................... 2858
19-76. RTCSS_ALARM_SECONDS_REG Register ........................................................................ 2859
19-77. RTCSS_ALARM_MINUTES_REG Register ......................................................................... 2860
...........................................................................
19-79. RTCSS_ALARM_DAYS_REG Register ..............................................................................
19-80. RTCSS_ALARM_MONTHS_REG Register .........................................................................
19-81. RTCSS_ALARM_YEARS_REG Register ............................................................................
19-82. RTCSS_CTRL_REG Register .........................................................................................
19-83. RTCSS_STS_REG Register ...........................................................................................
19-84. RTCSS_INTRS_REG Register ........................................................................................
19-85. RTCSS_COMP_LSB_REG Register .................................................................................
19-86. RTCSS_COMP_MSB_REG Register ................................................................................
19-87. RTCSS_OSC_REG Register ..........................................................................................
19-88. RTCSS_SCRATCH0_REG Register .................................................................................
19-89. RTCSS_SCRATCH1_REG Register .................................................................................
19-90. RTCSS_SCRATCH2_REG Register .................................................................................
19-91. RTCSS_KICK0R Register..............................................................................................
19-92. RTCSS_KICK1R Register..............................................................................................
19-93. RTCSS_REVISION Register ..........................................................................................
19-94. RTCSS_SYSCONFIG Register .......................................................................................
19-95. RTCSS_IRQWAKEEN Register .......................................................................................
19-96. RTCSS_ALARM2_SECONDS_REG Register ......................................................................
19-97. RTCSS_ALARM2_MINUTES_REG Register .......................................................................
19-98. RTCSS_ALARM2_HOURS_REG Register ..........................................................................
19-99. RTCSS_ALARM2_DAYS_REG Register ............................................................................
19-100. RTCSS_ALARM2_MONTHS_REG Register.......................................................................
19-101. RTCSS_ALARM2_YEARS_REG Register .........................................................................
19-102. RTCSS_PMIC Register ...............................................................................................
19-103. RTCSS_DEBOUNCE Register .......................................................................................
19-104. Public WDTimer Integration ..........................................................................................
19-105. 32-Bit Watchdog Timer Functional Block Diagram ................................................................
19-106. Watchdog Timers General Functional View ........................................................................
19-107. WDT_WIDR Register ..................................................................................................
19-108. WDT_WDSC Register .................................................................................................
19-109. WDT_WDST Register .................................................................................................
19-110. WDT_WISR Register ..................................................................................................
19-111. WDT_WIER Register ..................................................................................................
19-112. WDT_WCLR Register .................................................................................................
19-113. WDT_WCRR Register ................................................................................................
19-114. WDT_WLDR Register .................................................................................................
19-115. WDT_WTGR Register .................................................................................................
19-116. WDT_WWPS Register ................................................................................................
19-117. WDT_WDLY Register .................................................................................................
19-118. WDT_WSPR Register .................................................................................................
19-119. WDT_WIRQSTATRAW Register ....................................................................................
19-120. WDT_WIRQSTAT Register ...........................................................................................
19-121. WDT_WIRQENSET Register.........................................................................................
19-78. RTCSS_ALARM_HOURS_REG Register
54
List of Figures
2861
2862
2863
2864
2865
2867
2868
2869
2870
2871
2872
2873
2874
2875
2876
2877
2878
2879
2880
2881
2882
2883
2884
2885
2886
2887
2889
2891
2892
2899
2900
2901
2902
2903
2904
2905
2906
2907
2908
2909
2910
2911
2912
2913
SPRUHL7I – April 2014 – Revised December 2019
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........................................................................................
PWMSS Integration .....................................................................................................
PWMSS Synchronization...............................................................................................
IDVER Register ..........................................................................................................
SYSCONFIG Register ..................................................................................................
CLKCONFIG Register ..................................................................................................
CLKSTATUS Register ..................................................................................................
Multiple ePWM Modules................................................................................................
Submodules and Signal Connections for an ePWM Module ......................................................
ePWM Submodules and Critical Internal Signal Interconnects ...................................................
Time-Base Submodule Block Diagram ...............................................................................
Time-Base Submodule Signals and Registers ......................................................................
Time-Base Frequency and Period ....................................................................................
Time-Base Counter Synchronization Scheme 1 ....................................................................
Time-Base Up-Count Mode Waveforms .............................................................................
Time-Base Down-Count Mode Waveforms ..........................................................................
Time-Base Up-Down-Count Waveforms, TBCTL[PHSDIR = 0] Count Down on Synchronization Event ...
Time-Base Up-Down Count Waveforms, TBCTL[PHSDIR = 1] Count Up on Synchronization Event .......
Counter-Compare Submodule .........................................................................................
Counter-Compare Submodule Signals and Registers..............................................................
Counter-Compare Event Waveforms in Up-Count Mode ..........................................................
Counter-Compare Events in Down-Count Mode ....................................................................
19-122. WDT_WIRQENCLR Register
2914
20-1.
2918
20-2.
20-3.
20-4.
20-5.
20-6.
20-7.
20-8.
20-9.
20-10.
20-11.
20-12.
20-13.
20-14.
20-15.
20-16.
20-17.
20-18.
20-19.
20-20.
20-21.
2919
2922
2923
2924
2925
2927
2928
2929
2933
2935
2937
2938
2940
2941
2941
2942
2943
2943
2946
2946
20-22. Counter-Compare Events in Up-Down-Count Mode, TBCTL[PHSDIR = 0] Count Down on
Synchronization Event ................................................................................................. 2947
20-23. Counter-Compare Events in Up-Down-Count Mode, TBCTL[PHSDIR = 1] Count Up on Synchronization
Event ..................................................................................................................... 2947
20-24. Action-Qualifier Submodule ............................................................................................ 2948
20-25. Action-Qualifier Submodule Inputs and Outputs .................................................................... 2949
20-26. Possible Action-Qualifier Actions for EPWMxA and EPWMxB Outputs
.........................................
2950
20-27. Up-Down-Count Mode Symmetrical Waveform ..................................................................... 2953
20-28. Up, Single Edge Asymmetric Waveform, With Independent Modulation on EPWMxA and
EPWMxB—Active High ................................................................................................. 2954
20-29. Up, Single Edge Asymmetric Waveform With Independent Modulation on EPWMxA and
EPWMxB—Active Low ................................................................................................. 2956
20-30. Up-Count, Pulse Placement Asymmetric Waveform With Independent Modulation on EPWMxA ........... 2958
20-31. Up-Down-Count, Dual Edge Symmetric Waveform, With Independent Modulation on EPWMxA and
EPWMxB — Active Low ................................................................................................ 2960
20-32. Up-Down-Count, Dual Edge Symmetric Waveform, With Independent Modulation on EPWMxA and
EPWMxB — Complementary .......................................................................................... 2962
20-33. Up-Down-Count, Dual Edge Asymmetric Waveform, With Independent Modulation on EPWMxA—Active
Low ........................................................................................................................ 2964
20-34. Dead-Band Generator Submodule .................................................................................... 2966
20-35. Configuration Options for the Dead-Band Generator Submodule ................................................ 2967
20-36. Dead-Band Waveforms for Typical Cases (0% < Duty < 100%).................................................. 2969
20-37. PWM-Chopper Submodule
............................................................................................
2970
20-38. PWM-Chopper Submodule Signals and Registers ................................................................. 2971
20-39. Simple PWM-Chopper Submodule Waveforms Showing Chopping Action Only ............................... 2972
20-40. PWM-Chopper Submodule Waveforms Showing the First Pulse and Subsequent Sustaining Pulses ...... 2972
20-41. PWM-Chopper Submodule Waveforms Showing the Pulse Width (Duty Cycle) Control of Sustaining
Pulses ..................................................................................................................... 2973
20-42. Trip-Zone Submodule ................................................................................................... 2974
SPRUHL7I – April 2014 – Revised December 2019
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List of Figures
55
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20-43. Trip-Zone Submodule Mode Control Logic .......................................................................... 2977
20-44. Trip-Zone Submodule Interrupt Logic................................................................................. 2977
20-45. Event-Trigger Submodule .............................................................................................. 2978
20-46. Event-Trigger Submodule Inter-Connectivity to Interrupt Controller .............................................. 2979
20-47. Event-Trigger Submodule Showing Event Inputs and Prescaled Outputs....................................... 2979
20-48. Event-Trigger Interrupt Generator ..................................................................................... 2981
20-49. HRPWM System Interface ............................................................................................. 2982
20-50. Resolution Calculations for Conventionally Generated PWM ..................................................... 2983
20-51. Operating Logic Using MEP ........................................................................................... 2984
20-52. Required PWM Waveform for a Requested Duty = 40.5% ........................................................ 2986
2988
20-54.
2988
20-55.
20-56.
20-57.
20-58.
20-59.
20-60.
20-61.
20-62.
20-63.
20-64.
20-65.
20-66.
20-67.
20-68.
20-69.
20-70.
20-71.
20-72.
20-73.
20-74.
20-75.
20-76.
20-77.
20-78.
20-79.
20-80.
20-81.
20-82.
20-83.
20-84.
20-85.
20-86.
20-87.
20-88.
20-89.
20-90.
20-91.
56
..............................
High % Duty Cycle Range Limitation Example when PWM Frequency = 1 MHz ..............................
Simplified ePWM Module...............................................................................................
EPWM1 Configured as a Typical Master, EPWM2 Configured as a Slave .....................................
Control of Four Buck Stages. Here FPWM1≠ FPWM2≠ FPWM3≠ FPWM4 ..................................................
Buck Waveforms for (Note: Only three bucks shown here) .......................................................
Control of Four Buck Stages. (Note: FPWM2 = N × FPWM1) ...........................................................
Buck Waveforms for (Note: FPWM2 = FPWM1))...........................................................................
Control of Two Half-H Bridge Stages (FPWM2 = N × FPWM1) ..........................................................
Half-H Bridge Waveforms for (Note: Here FPWM2 = FPWM1 ) ..........................................................
Control of Dual 3-Phase Inverter Stages as Is Commonly Used in Motor Control .............................
3-Phase Inverter Waveforms for (Only One Inverter Shown) .....................................................
Configuring Two PWM Modules for Phase Control .................................................................
Timing Waveforms Associated With Phase Control Between 2 Modules .......................................
Control of a 3-Phase Interleaved DC/DC Converter ................................................................
3-Phase Interleaved DC/DC Converter Waveforms for ...........................................................
Controlling a Full-H Bridge Stage (FPWM2 = FPWM1) ...................................................................
ZVS Full-H Bridge Waveforms ........................................................................................
TBCTL Register .........................................................................................................
TBSTS Register .........................................................................................................
TBPHSHR Register .....................................................................................................
TBPHS Register .........................................................................................................
TBCNT Register .........................................................................................................
TBPRD Register .........................................................................................................
CMPCTL Register .......................................................................................................
CMPAHR Register ......................................................................................................
CMPA Register ..........................................................................................................
CMPB Register ..........................................................................................................
AQCTLA Register .......................................................................................................
AQCTLB Register .......................................................................................................
AQSFRC Register .......................................................................................................
AQCSFRC Register .....................................................................................................
DBCTL Register .........................................................................................................
DBRED Register ........................................................................................................
DBFED Register .........................................................................................................
TZSEL Register..........................................................................................................
TZCTL Register..........................................................................................................
TZEINT Register ........................................................................................................
TZFLG Register .........................................................................................................
20-53. Low % Duty Cycle Range Limitation Example When PWM Frequency = 1 MHz
List of Figures
2990
2991
2992
2993
2995
2996
2998
2999
3001
3002
3005
3006
3007
3008
3011
3012
3015
3017
3018
3019
3020
3021
3022
3024
3025
3026
3027
3029
3031
3032
3033
3035
3036
3037
3038
3039
3040
SPRUHL7I – April 2014 – Revised December 2019
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20-92. TZCLR Register ......................................................................................................... 3041
20-93. TZFRC Register ......................................................................................................... 3042
20-94. ETSEL Register
.........................................................................................................
3043
20-95. ETPS Register ........................................................................................................... 3044
20-96. ETFLG Register ......................................................................................................... 3045
20-97. ETCLR Register ......................................................................................................... 3046
20-98. ETFRC Register ......................................................................................................... 3047
20-99. PCCTL Register ......................................................................................................... 3048
20-100. HRCTL Register........................................................................................................ 3049
20-101. Multiple eCAP Modules ............................................................................................... 3051
20-102. Capture and APWM Modes of Operation .......................................................................... 3052
20-103. Capture Function Diagram ........................................................................................... 3053
20-104. Event Prescale Control ................................................................................................ 3054
20-105. Prescale Function Waveforms ....................................................................................... 3054
20-106. Continuous/One-shot Block Diagram ............................................................................... 3055
20-107. Counter and Synchronization Block Diagram ..................................................................... 3056
20-108. Interrupts in eCAP Module............................................................................................ 3058
20-109. PWM Waveform Details Of APWM Mode Operation ............................................................. 3059
............................................
Capture Sequence for Absolute Time-Stamp, Rising and Falling Edge Detect ..............................
Capture Sequence for Delta Mode Time-Stamp, Rising Edge Detect .........................................
Capture Sequence for Delta Mode Time-Stamp, Rising and Falling Edge Detect ...........................
PWM Waveform Details of APWM Mode Operation .............................................................
Multichannel PWM Example Using 4 eCAP Modules ............................................................
Multiphase (channel) Interleaved PWM Example Using 3 eCAP Modules ....................................
TSCTR Register........................................................................................................
CTRPHS Register .....................................................................................................
CAP1 Register .........................................................................................................
CAP2 Register .........................................................................................................
CAP3 Register .........................................................................................................
CAP4 Register .........................................................................................................
ECCTL1 Register ......................................................................................................
ECCTL2 Register ......................................................................................................
ECEINT Register .......................................................................................................
ECFLG Register........................................................................................................
ECCLR Register .......................................................................................................
ECFRC Register .......................................................................................................
REVID Register ........................................................................................................
Optical Encoder Disk .................................................................................................
QEP Encoder Output Signal for Forward/Reverse Movement ...................................................
Index Pulse Example .................................................................................................
Functional Block Diagram of the eQEP Peripheral ...............................................................
Functional Block Diagram of Decoder Unit .........................................................................
Quadrature Decoder State Machine ................................................................................
Quadrature-clock and Direction Decoding .........................................................................
Position Counter Reset by Index Pulse for 1000 Line Encoder (QPOSMAX = 3999 or F9Fh) .............
Position Counter Underflow/Overflow (QPOSMAX = 4) ........................................................
Software Index Marker for 1000-line Encoder (QEPCTL[IEL] = 1) ..............................................
Strobe Event Latch (QEPCTL[SEL] = 1) ...........................................................................
20-110. Capture Sequence for Absolute Time-Stamp, Rising Edge Detect
3061
20-111.
3063
20-112.
20-113.
20-114.
20-115.
20-116.
20-117.
20-118.
20-119.
20-120.
20-121.
20-122.
20-123.
20-124.
20-125.
20-126.
20-127.
20-128.
20-129.
20-130.
20-131.
20-132.
20-133.
20-134.
20-135.
20-136.
20-137.
20-138.
20-139.
20-140.
SPRUHL7I – April 2014 – Revised December 2019
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List of Figures
3065
3067
3069
3071
3074
3077
3078
3079
3080
3081
3082
3083
3085
3087
3088
3089
3090
3091
3092
3093
3093
3096
3097
3099
3099
3101
3102
3104
3105
57
www.ti.com
20-141. eQEP Position-compare Unit ........................................................................................ 3106
20-142. eQEP Position-compare Event Generation Points ................................................................ 3107
20-143. eQEP Position-compare Sync Output Pulse Stretcher........................................................... 3107
20-144. eQEP Edge Capture Unit ............................................................................................ 3109
20-145. Unit Position Event for Low Speed Measurement (QCAPCTL[UPPS] = 0010) ............................... 3109
20-146. eQEP Edge Capture Unit - Timing Details ......................................................................... 3110
20-147. eQEP Watchdog Timer ............................................................................................... 3111
20-148. eQEP Unit Time Base ................................................................................................ 3112
20-149. EQEP Interrupt Generation .......................................................................................... 3112
20-150. QPOSCNT Register ................................................................................................... 3114
20-151. QPOSINIT Register .................................................................................................... 3115
20-152. QPOSMAX Register ................................................................................................... 3116
20-153. QPOSCMP Register ................................................................................................... 3117
20-154. QPOSILAT Register ................................................................................................... 3118
20-155. QPOSSLAT Register .................................................................................................. 3119
20-156. QPOSLAT Register .................................................................................................... 3120
20-157. QUTMR Register ....................................................................................................... 3121
20-158. QUPRD Register ....................................................................................................... 3122
20-159. QWDTMR Register .................................................................................................... 3123
20-160. QWDPRD Register .................................................................................................... 3124
20-161. QDECCTL Register .................................................................................................... 3125
20-162. QEPCTL Register ...................................................................................................... 3126
20-163. QCAPCTL Register .................................................................................................... 3128
20-164. QPOSCTL Register .................................................................................................... 3129
20-165. QEINT Register ........................................................................................................ 3130
20-166. QFLG Register ......................................................................................................... 3131
20-167. QCLR Register ......................................................................................................... 3132
20-168. QFRC Register ......................................................................................................... 3133
20-169. QEPSTS Register...................................................................................................... 3134
20-170. QCTMR Register ....................................................................................................... 3135
20-171. QCPRD Register ....................................................................................................... 3136
20-172. QCTMRLAT Register .................................................................................................. 3137
20-173. QCPRDLAT Register .................................................................................................. 3138
20-174. REVID Register ........................................................................................................ 3139
21-1.
UART/IrDA Module — UART Application ............................................................................ 3143
21-2.
UART/IrDA Module — IrDA/CIR Application......................................................................... 3143
21-3.
UART/IrDA/CIR Functional Specification Block Diagram .......................................................... 3148
21-4.
FIFO Management Registers .......................................................................................... 3153
21-5.
RX FIFO Interrupt Request Generation .............................................................................. 3155
21-6.
TX FIFO Interrupt Request Generation
21-7.
Receive FIFO DMA Request Generation (32 Characters) ......................................................... 3157
21-8.
Transmit FIFO DMA Request Generation (56 Spaces) ............................................................ 3157
21-9.
Transmit FIFO DMA Request Generation (8 Spaces).............................................................. 3158
..............................................................................
3156
21-10. Transmit FIFO DMA Request Generation (1 Space) ............................................................... 3159
21-11. Transmit FIFO DMA Request Generation Using Direct TX DMA Threshold Programming. (Threshold = 3;
Spaces = 8) .............................................................................................................. 3160
21-12. DMA Transmission ...................................................................................................... 3160
21-13. DMA Reception .......................................................................................................... 3161
21-14. UART Data Format...................................................................................................... 3168
58
List of Figures
SPRUHL7I – April 2014 – Revised December 2019
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21-15. Baud Rate Generation .................................................................................................. 3168
21-16. IrDA SIR Frame Format ................................................................................................ 3174
21-17. IrDA Encoding Mechanism ............................................................................................. 3175
21-18. IrDA Decoding Mechanism............................................................................................. 3176
21-19. SIR Free Format Mode ................................................................................................. 3176
21-20. MIR Transmit Frame Format........................................................................................... 3177
21-21. MIR BAUD Rate Adjustment Mechanism ............................................................................ 3178
21-22. SIP Pulse ................................................................................................................. 3178
21-23. FIR Transmit Frame Format ........................................................................................... 3178
21-24. Baud Rate Generator ................................................................................................... 3179
......................................................................................................
SIRC Bit Encoding ......................................................................................................
RC-5 Standard Packet Format ........................................................................................
SIRC Packet Format ....................................................................................................
SIRC Bit Transmission Example ......................................................................................
CIR Mode Block Components .........................................................................................
CIR Pulse Modulation...................................................................................................
CIR Modulation Duty Cycle ............................................................................................
Variable Pulse Duration Definitions ...................................................................................
UART_THR Register....................................................................................................
UART_RHR Register ...................................................................................................
UART_DLL Register ....................................................................................................
UART_IER_IRDA Register .............................................................................................
UART_IER_CIR Register ..............................................................................................
UART_IER Register.....................................................................................................
UART_DLH Register ....................................................................................................
UART_EFR Register ....................................................................................................
UART_IIR Register ......................................................................................................
UART_IIR_CIR Register ...............................................................................................
UART_FCR Register....................................................................................................
UART_LCR Register ....................................................................................................
UART_MCR Register ...................................................................................................
UART_XON1_ADDR1 Register .......................................................................................
UART_XON2_ADDR2 Register .......................................................................................
UART_LSR_CIR Register ..............................................................................................
UART_LSR_IRDA Register ............................................................................................
UART_LSR Register ....................................................................................................
UART_TCR Register....................................................................................................
UART_MSR Register ...................................................................................................
UART_XOFF1 Register ................................................................................................
UART_SPR Register....................................................................................................
UART_TLR Register ....................................................................................................
UART_XOFF2 Register ................................................................................................
UART_MDR1 Register .................................................................................................
UART_MDR2 Register .................................................................................................
UART_TXFLL Register .................................................................................................
UART_SFLSR Register ................................................................................................
UART_RESUME Register..............................................................................................
UART_TXFLH Register.................................................................................................
21-25. RC-5 Bit Encoding
3183
21-26.
3183
21-27.
21-28.
21-29.
21-30.
21-31.
21-32.
21-33.
21-34.
21-35.
21-36.
21-37.
21-38.
21-39.
21-40.
21-41.
21-42.
21-43.
21-44.
21-45.
21-46.
21-47.
21-48.
21-49.
21-50.
21-51.
21-52.
21-53.
21-54.
21-55.
21-56.
21-57.
21-58.
21-59.
21-60.
21-61.
21-62.
21-63.
SPRUHL7I – April 2014 – Revised December 2019
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Copyright © 2014–2019, Texas Instruments Incorporated
List of Figures
3184
3184
3184
3185
3187
3187
3189
3201
3202
3203
3204
3205
3206
3207
3208
3210
3211
3212
3213
3214
3215
3216
3217
3218
3219
3221
3222
3223
3224
3225
3226
3227
3228
3229
3230
3231
3232
59
www.ti.com
21-64. UART_RXFLL Register ................................................................................................. 3233
21-65. UART_SFREGL Register .............................................................................................. 3234
21-66. UART_SFREGH Register .............................................................................................. 3235
21-67. UART_RXFLH Register ................................................................................................ 3236
21-68. UART_BLR Register .................................................................................................... 3237
21-69. UART_UASR Register.................................................................................................. 3238
3239
21-71. UART_SCR Register
3240
21-72.
3241
21-73.
21-74.
21-75.
21-76.
21-77.
21-78.
21-79.
21-80.
21-81.
21-82.
21-83.
21-84.
21-85.
22-1.
22-2.
22-3.
22-4.
22-5.
22-6.
22-7.
22-8.
22-9.
22-10.
22-11.
22-12.
22-13.
22-14.
22-15.
22-16.
22-17.
22-18.
22-19.
22-20.
22-21.
22-22.
22-23.
22-24.
22-25.
22-26.
22-27.
60
...............................................................................................
...................................................................................................
UART_SSR Register....................................................................................................
UART_EBLR Register ..................................................................................................
UART_MVR Register ...................................................................................................
UART_SYSC Register ..................................................................................................
UART_SYSS Register ..................................................................................................
UART_WER Register ...................................................................................................
UART_CFPS Register ..................................................................................................
UART_RXFIFO_LVL Register .........................................................................................
UART_TXFIFO_LVL Register .........................................................................................
UART_IER2 Register ...................................................................................................
UART_ISR2 Register ...................................................................................................
UART_FREQ_SEL Register ...........................................................................................
UART_MDR3 Register .................................................................................................
UART_TX_DMA_THR Register .......................................................................................
I2C0 Integration and Bus Application .................................................................................
I2C(1–2) Integration and Bus Application ............................................................................
I2C Functional Block Diagram .........................................................................................
Multiple I2C Modules Connected ......................................................................................
Bit Transfer on the I2C Bus ............................................................................................
Start and Stop Condition Events ......................................................................................
I2C Data Transfer .......................................................................................................
I2C Data Transfer Formats.............................................................................................
Arbitration Procedure Between Two Master Transmitters .........................................................
Synchronization of Two I2C Clock Generators ......................................................................
Receive FIFO Interrupt Request Generation ........................................................................
Transmit FIFO Interrupt Request Generation .......................................................................
Receive FIFO DMA Request Generation ............................................................................
Transmit FIFO DMA Request Generation (High Threshold).......................................................
Transmit FIFO DMA Request Generation (Low Threshold) .......................................................
I2C_REVNB_LO Register ..............................................................................................
I2C_REVNB_HI Register ...............................................................................................
I2C_SYSC Register .....................................................................................................
I2C_IRQSTS_RAW Register ..........................................................................................
I2C_IRQSTS Register ..................................................................................................
I2C_IRQEN_SET Register .............................................................................................
I2C_IRQEN_CLR Register .............................................................................................
I2C_WE Register ........................................................................................................
I2C_DMARXEN_SET Register ........................................................................................
I2C_DMATXEN_SET Register ........................................................................................
I2C_DMARXEN_CLR Register ........................................................................................
I2C_DMATXEN_CLR Register ........................................................................................
21-70. UART_ACREG Register
List of Figures
3242
3243
3244
3245
3246
3247
3248
3249
3250
3251
3252
3253
3254
3257
3257
3259
3260
3261
3262
3262
3263
3264
3265
3267
3267
3268
3269
3269
3274
3275
3276
3278
3284
3286
3288
3290
3293
3294
3295
3296
SPRUHL7I – April 2014 – Revised December 2019
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22-28. I2C_DMARXWAKE_EN Register ..................................................................................... 3297
22-29. I2C_DMATXWAKE_EN Register...................................................................................... 3299
22-30. I2C_SYSS Register ..................................................................................................... 3301
22-31. I2C_BUF Register ....................................................................................................... 3302
22-32. I2C_CNT Register ....................................................................................................... 3304
22-33. I2C_DATA Register ..................................................................................................... 3305
22-34. I2C_CON Register ...................................................................................................... 3306
22-35. I2C_OA Register
........................................................................................................
3309
22-36. I2C_SA Register ......................................................................................................... 3310
22-37. I2C_PSC Register ....................................................................................................... 3311
.....................................................................................................
I2C_SCLH Register .....................................................................................................
I2C_SYSTEST Register ................................................................................................
I2C_BUFSTAT Register ................................................................................................
I2C_OA1 Register .......................................................................................................
I2C_OA2 Register .......................................................................................................
I2C_OA3 Register .......................................................................................................
I2C_ACTOA Register ...................................................................................................
I2C_SBLOCK Register .................................................................................................
HDQ1W Integration .....................................................................................................
HDQ/1-Wire Typical Application System Overview .................................................................
HDQ Break-Pulse Timing Diagram ...................................................................................
1-Wire (SDQ) Reset Timing Diagram .................................................................................
HDQ/1-Wire Transmitted Bit Timing ..................................................................................
HDQ/1-Wire Communication Sequence..............................................................................
HDQ/1-Wire Block Diagram ............................................................................................
Protocol Registers Description ........................................................................................
Environment ..............................................................................................................
HDQ/1-Wire Configuration in HDQ Mode ............................................................................
Software Reset Flowchart ..............................................................................................
HDQ1W_REVISION Register .........................................................................................
HDQ1W_TX_DATA Register ..........................................................................................
HDQ1W_RX_DATA Register ..........................................................................................
HDQ1W_CTRL_STS Register.........................................................................................
HDQ1W_INT_STS Register ...........................................................................................
HDQ1W_SYSCONFIG Register ......................................................................................
HDQ1W_SYSSTS Register ............................................................................................
McASP0–1 Integration ..................................................................................................
McASP Block Diagram .................................................................................................
McASP to Parallel 2-Channel DACs ..................................................................................
McASP to 6-Channel DAC and 2-Channel DAC ....................................................................
McASP to Digital Amplifier .............................................................................................
McASP as Digital Audio Encoder .....................................................................................
McASP as 16 Channel Digital Processor ............................................................................
TDM Format–6 Channel TDM Example ..............................................................................
TDM Format Bit Delays from Frame Sync ...........................................................................
Inter-Integrated Sound (I2S) Format ..................................................................................
Biphase-Mark Code (BMC) ............................................................................................
S/PDIF Subframe Format ..............................................................................................
22-38. I2C_SCLL Register
3312
22-39.
3313
22-40.
22-41.
22-42.
22-43.
22-44.
22-45.
22-46.
23-1.
23-2.
23-3.
23-4.
23-5.
23-6.
23-7.
23-8.
23-9.
23-10.
23-11.
23-12.
23-13.
23-14.
23-15.
23-16.
23-17.
23-18.
24-1.
24-2.
24-3.
24-4.
24-5.
24-6.
24-7.
24-8.
24-9.
24-10.
24-11.
24-12.
SPRUHL7I – April 2014 – Revised December 2019
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Copyright © 2014–2019, Texas Instruments Incorporated
List of Figures
3314
3318
3319
3320
3321
3322
3323
3327
3329
3330
3330
3331
3331
3332
3333
3342
3342
3343
3345
3346
3347
3348
3349
3350
3351
3355
3358
3359
3359
3360
3360
3360
3361
3362
3362
3363
3364
61
www.ti.com
24-13. S/PDIF Frame Format .................................................................................................. 3365
24-14. Definition of Bit, Word, and Slot ....................................................................................... 3366
24-15. Bit Order and Word Alignment Within a Slot Examples ............................................................ 3366
3367
24-17.
3368
24-18.
24-19.
24-20.
24-21.
24-22.
24-23.
24-24.
24-25.
24-26.
24-27.
24-28.
24-29.
24-30.
24-31.
24-32.
24-33.
24-34.
24-35.
24-36.
24-37.
24-38.
24-39.
24-40.
24-41.
24-42.
24-43.
24-44.
24-45.
24-46.
24-47.
24-48.
24-49.
24-50.
24-51.
24-52.
24-53.
24-54.
24-55.
24-56.
24-57.
24-58.
24-59.
24-60.
24-61.
62
.........................................................................
Transmit Clock Generator Block Diagram ...........................................................................
Receive Clock Generator Block Diagram ............................................................................
Frame Sync Generator Block Diagram ...............................................................................
Burst Frame Sync Mode................................................................................................
Transmit DMA Event (AXEVT) Generation in TDM Time Slots ...................................................
Individual Serializer and Connections Within McASP ..............................................................
Receive Format Unit ....................................................................................................
Transmit Format Unit ...................................................................................................
McASP I/O Pin Control Block Diagram ...............................................................................
Processor Service Time Upon Transmit DMA Event (AXEVT) ...................................................
Processor Service Time Upon Receive DMA Event (AREVT) ....................................................
McASP Audio FIFO (AFIFO) Block Diagram ........................................................................
Data Flow Through Transmit Format Unit, Illustrated ..............................................................
Data Flow Through Receive Format Unit, Illustrated ...............................................................
Transmit Clock Failure Detection Circuit Block Diagram ...........................................................
Receive Clock Failure Detection Circuit Block Diagram ...........................................................
Serializers in Loopback Mode .........................................................................................
Interrupt Multiplexing ....................................................................................................
Audio Mute (AMUTE) Block Diagram .................................................................................
DMA Events in an Audio Example–Two Events (Scenario 1) .....................................................
DMA Events in an Audio Example–Four Events (Scenario 2) ....................................................
DMA Events in an Audio Example ....................................................................................
MCASP_REV Register .................................................................................................
MCASP_PWRIDLESYSCONFIG Register ...........................................................................
MCASP_PFUNC Register..............................................................................................
MCASP_PDIR Register ................................................................................................
MCASP_PDOUT Register .............................................................................................
MCASP_PDIN Register ................................................................................................
MCASP_PDCLR Register ..............................................................................................
MCASP_GBLCTL Register ............................................................................................
MCASP_AMUTE Register .............................................................................................
MCASP_DLBCTL Register ............................................................................................
MCASP_DITCTL Register .............................................................................................
MCASP_RGBLCTL Register ..........................................................................................
MCASP_RMASK Register .............................................................................................
MCASP_RFMT Register ...............................................................................................
MCASP_AFSRCTL Register...........................................................................................
MCASP_ACLKRCTL Register .........................................................................................
MCASP_AHCLKRCTL Register .......................................................................................
MCASP_RTDM Register ...............................................................................................
MCASP_RINTCTL Register ...........................................................................................
MCASP_RSTAT Register ..............................................................................................
MCASP_RSLOT Register ..............................................................................................
MCASP_RCLKCHK Register ..........................................................................................
MCASP_REVTCTL Register...........................................................................................
24-16. Definition of Frame and Frame Sync Width
List of Figures
3369
3370
3372
3374
3379
3380
3380
3382
3384
3385
3387
3390
3392
3396
3398
3399
3405
3406
3408
3408
3409
3412
3413
3414
3415
3417
3419
3420
3422
3424
3426
3427
3428
3430
3431
3433
3434
3435
3436
3437
3439
3441
3442
3443
SPRUHL7I – April 2014 – Revised December 2019
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24-62. MCASP_XGBLCTL Register........................................................................................... 3444
.............................................................................................
...............................................................................................
MCASP_AFSXCTL Register ...........................................................................................
MCASP_ACLKXCTL Register .........................................................................................
MCASP_AHCLKXCTL Register .......................................................................................
MCASP_XTDM Register ...............................................................................................
MCASP_XINTCTL Register............................................................................................
MCASP_XSTAT Register ..............................................................................................
MCASP_XSLOT Register ..............................................................................................
MCASP_XCLKCHK Register ..........................................................................................
MCASP_XEVTCTL Register ...........................................................................................
MCASP_DITCSRA0 to MCASP_DITCSRA5 Register .............................................................
MCASP_DITCSRB0 to MCASP_DITCSRB5 Register .............................................................
MCASP_DITUDRA0 to MCASP_DITUDRA5 Register .............................................................
MCASP_DITUDRB0 to MCASP_DITUDRB5 Register .............................................................
MCASP_SRCTL0 to MCASP_SRCTL5 Register ...................................................................
MCASP_XBUF0 to MCASP_XBUF5 Register ......................................................................
MCASP_RBUF0 to MCASP_RBUF5 Register ......................................................................
MCASP_WFIFOCTL Register .........................................................................................
MCASP_WFIFOSTS Register .........................................................................................
MCASP_RFIFOCTL Register ..........................................................................................
MCASP_RFIFOSTS Register .........................................................................................
DCAN Integration........................................................................................................
DCAN Block Diagram ...................................................................................................
CAN Module General Initialization Flow ..............................................................................
CAN Bit-Timing Configuration .........................................................................................
CAN Core in Silent Mode ..............................................................................................
CAN Core in Loopback Mode .........................................................................................
CAN Core in External Loopback Mode ...............................................................................
CAN Core in Loop Back Combined With Silent Mode .............................................................
CAN Interrupt Topology 1 ..............................................................................................
CAN Interrupt Topology 2 ..............................................................................................
Local Power-Down Mode Flow Diagram .............................................................................
CPU Handling of a FIFO Buffer (Interrupt Driven) ..................................................................
Bit Timing .................................................................................................................
The Propagation Time Segment ......................................................................................
Synchronization on Late and Early Edges ...........................................................................
Filtering of Short Dominant Spikes ....................................................................................
Structure of the CAN Core’s CAN Protocol Controller .............................................................
Data Transfer Between IF1/IF2 Registers and Message RAM ...................................................
DCAN_CTL Register ....................................................................................................
DCAN_ES Register .....................................................................................................
DCAN_ERRC Register .................................................................................................
DCAN_BTR Register ...................................................................................................
DCAN_INT Register ....................................................................................................
DCAN_TEST Register ..................................................................................................
DCAN_PERR Register .................................................................................................
DCAN_ABOTR Register ...............................................................................................
24-63. MCASP_XMASK Register
3446
24-64. MCASP_XFMT Register
3447
24-65.
3449
24-66.
24-67.
24-68.
24-69.
24-70.
24-71.
24-72.
24-73.
24-74.
24-75.
24-76.
24-77.
24-78.
24-79.
24-80.
24-81.
24-82.
24-83.
24-84.
25-1.
25-2.
25-3.
25-4.
25-5.
25-6.
25-7.
25-8.
25-9.
25-10.
25-11.
25-12.
25-13.
25-14.
25-15.
25-16.
25-17.
25-18.
25-19.
25-20.
25-21.
25-22.
25-23.
25-24.
25-25.
25-26.
SPRUHL7I – April 2014 – Revised December 2019
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Copyright © 2014–2019, Texas Instruments Incorporated
List of Figures
3450
3451
3452
3453
3455
3457
3458
3459
3460
3461
3462
3463
3464
3466
3467
3468
3469
3470
3471
3474
3476
3478
3479
3481
3482
3483
3484
3486
3486
3488
3497
3498
3499
3501
3502
3503
3507
3515
3518
3520
3521
3522
3523
3524
3525
63
www.ti.com
25-27. DCAN_TXRQ_X Register .............................................................................................. 3526
25-28. DCAN_TXRQ12 Register .............................................................................................. 3527
25-29. DCAN_TXRQ34 Register .............................................................................................. 3528
25-30. DCAN_TXRQ56 Register .............................................................................................. 3529
25-31. DCAN_TXRQ78 Register .............................................................................................. 3530
25-32. DCAN_NWDAT_X Register............................................................................................ 3531
25-33. DCAN_NWDAT12 Register ............................................................................................ 3532
25-34. DCAN_NWDAT34 Register ............................................................................................ 3533
25-35. DCAN_NWDAT56 Register ............................................................................................ 3534
25-36. DCAN_NWDAT78 Register ............................................................................................ 3535
3536
25-38.
3537
25-39.
25-40.
25-41.
25-42.
25-43.
25-44.
25-45.
25-46.
25-47.
25-48.
25-49.
25-50.
25-51.
25-52.
25-53.
25-54.
25-55.
25-56.
25-57.
25-58.
25-59.
25-60.
25-61.
25-62.
25-63.
25-64.
25-65.
25-66.
25-67.
25-68.
25-69.
25-70.
25-71.
25-72.
25-73.
25-74.
26-1.
64
...........................................................................................
DCAN_INTPND12 Register ............................................................................................
DCAN_INTPND34 Register ............................................................................................
DCAN_INTPND56 Register ............................................................................................
DCAN_INTPND78 Register ............................................................................................
DCAN_MSGVAL_X Register ..........................................................................................
DCAN_MSGVAL12 Register...........................................................................................
DCAN_MSGVAL34 Register...........................................................................................
DCAN_MSGVAL56 Register...........................................................................................
DCAN_MSGVAL78 Register...........................................................................................
DCAN_INTMUX12 Register ...........................................................................................
DCAN_INTMUX34 Register ...........................................................................................
DCAN_INTMUX56 Register ...........................................................................................
DCAN_INTMUX78 Register ...........................................................................................
DCAN_IF1CMD Register ...............................................................................................
DCAN_IF1MSK Register ...............................................................................................
DCAN_IF1ARB Register ...............................................................................................
DCAN_IF1MCTL Register..............................................................................................
DCAN_IF1DATA Register ..............................................................................................
DCAN_IF1DATB Register ..............................................................................................
DCAN_IF2CMD Register ...............................................................................................
DCAN_IF2MSK Register ...............................................................................................
DCAN_IF2ARB Register ...............................................................................................
DCAN_IF2MCTL Register..............................................................................................
DCAN_IF2DATA Register ..............................................................................................
DCAN_IF2DATB Register ..............................................................................................
DCAN_IF3OBS Register ...............................................................................................
DCAN_IF3MSK Register ...............................................................................................
DCAN_IF3ARB Register ...............................................................................................
DCAN_IF3MCTL Register..............................................................................................
DCAN_IF3DATA Register ..............................................................................................
DCAN_IF3DATB Register ..............................................................................................
DCAN_IF3UPD12 Register ............................................................................................
DCAN_IF3UPD34 Register ............................................................................................
DCAN_IF3UPD56 Register ............................................................................................
DCAN_IF3UPD78 Register ............................................................................................
DCAN_TIOC Register ..................................................................................................
DCAN_RIOC Register ..................................................................................................
SPI Master Application .................................................................................................
25-37. DCAN_INTPND_X Register
List of Figures
3538
3539
3540
3541
3542
3543
3544
3545
3546
3547
3548
3549
3550
3553
3554
3555
3557
3558
3559
3562
3563
3564
3566
3567
3568
3570
3571
3572
3574
3575
3576
3577
3578
3579
3580
3582
3586
SPRUHL7I – April 2014 – Revised December 2019
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26-2.
SPI Slave Application ................................................................................................... 3586
26-3.
SPI Full-Duplex Transmission ......................................................................................... 3590
26-4.
SPI Half-Duplex Transmission (Receive-only Slave) ............................................................... 3591
26-5.
SPI Half-Duplex Transmission (Transmit-Only Slave).............................................................. 3591
26-6.
Phase and Polarity Combinations ..................................................................................... 3593
26-7.
Full Duplex Single Transfer Format with PHA = 0 .................................................................. 3594
26-8.
Full Duplex Single Transfer Format With PHA = 1
26-9.
Continuous Transfers With SPIEN Maintained Active (Single-Data-Pin Interface Mode) ..................... 3600
.................................................................
3595
26-10. Continuous Transfers With SPIEN Maintained Active (Dual-Data-Pin Interface Mode) ....................... 3600
26-11. Extended SPI Transfer With Start Bit PHA = 1 ...................................................................... 3602
26-12. Chip-Select SPIEN Timing Controls .................................................................................. 3603
26-13. Transmit/Receive Mode With No FIFO Used ........................................................................ 3606
26-14. Transmit/Receive Mode With Only Receive FIFO Enabled
.......................................................
3606
26-15. Transmit/Receive Mode With Only Transmit FIFO Used .......................................................... 3607
26-16. Transmit/Receive Mode With Both FIFO Direction Used .......................................................... 3607
26-17. Transmit-Only Mode With FIFO Used ................................................................................ 3608
26-18. Receive-Only Mode With FIFO Used
................................................................................
3608
26-19. Buffer Almost Full Level (AFL)......................................................................................... 3609
26-20. Buffer Almost Empty Level (AEL) ..................................................................................... 3610
26-21. Master Single Channel Initial Delay................................................................................... 3611
26-22. 3-Pin Mode System Overview ......................................................................................... 3612
26-23. Example of SPI Slave with One Master and Multiple Slave Devices on Channel 0............................ 3614
26-24. SPI Half-Duplex Transmission (Receive-Only Slave)
..............................................................
3616
26-25. SPI Half-Duplex Transmission (Transmit-Only Slave).............................................................. 3617
26-26. MCSPI_HL_REV Register
.............................................................................................
3625
26-27. MCSPI_HL_HWINFO Register ........................................................................................ 3626
26-28. MCSPI_HL_SYSCONFIG Register ................................................................................... 3627
26-29. MCSPI_REVISION Register ........................................................................................... 3628
26-30. MCSPI_SYSCONFIG Register ........................................................................................ 3629
26-31. MCSPI_SYSSTS Register ............................................................................................. 3631
26-32. MCSPI_IRQSTS Register .............................................................................................. 3632
...............................................................................................
........................................................................................
MCSPI_SYST Register .................................................................................................
MCSPI_MODULCTRL Register .......................................................................................
MCSPI_CH0CONF Register ...........................................................................................
MCSPI_CH0STAT Register............................................................................................
MCSPI_CH0CTRL Register ...........................................................................................
MCSPI_TX0 Register ...................................................................................................
MCSPI_RX0 Register ...................................................................................................
MCSPI_CH1CONF Register ...........................................................................................
MCSPI_CH1STAT Register............................................................................................
MCSPI_CH1CTRL Register ...........................................................................................
MCSPI_TX1 Register ...................................................................................................
MCSPI_RX1 Register ...................................................................................................
MCSPI_CH2CONF Register ...........................................................................................
MCSPI_CH2STAT Register............................................................................................
MCSPI_CH2CTRL Register ...........................................................................................
MCSPI_TX2 Register ...................................................................................................
26-33. MCSPI_IRQEN Register
3635
26-34. MCSPI_WAKEUPEN Register
3637
26-35.
3638
26-36.
26-37.
26-38.
26-39.
26-40.
26-41.
26-42.
26-43.
26-44.
26-45.
26-46.
26-47.
26-48.
26-49.
26-50.
SPRUHL7I – April 2014 – Revised December 2019
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Copyright © 2014–2019, Texas Instruments Incorporated
List of Figures
3640
3642
3646
3647
3648
3649
3650
3654
3655
3656
3657
3658
3662
3663
3664
65
www.ti.com
26-51. MCSPI_RX2 Register ................................................................................................... 3665
26-52. MCSPI_CH3CONF Register ........................................................................................... 3666
26-53. MCSPI_CH3STAT Register............................................................................................ 3670
3671
26-55.
3672
26-56.
26-57.
26-58.
26-59.
27-1.
27-2.
27-3.
27-4.
27-5.
27-6.
27-7.
27-8.
27-9.
27-10.
27-11.
27-12.
27-13.
27-14.
27-15.
27-16.
27-17.
27-18.
27-19.
27-20.
27-21.
28-1.
28-2.
28-3.
28-4.
28-5.
28-6.
28-7.
28-8.
28-9.
28-10.
28-11.
28-12.
28-13.
28-14.
28-15.
28-16.
28-17.
28-18.
28-19.
66
...........................................................................................
MCSPI_TX3 Register ...................................................................................................
MCSPI_RX3 Register ...................................................................................................
MCSPI_XFERLEVEL Register ........................................................................................
MCSPI_DAFTX Register ...............................................................................................
MCSPI_DAFRX Register ...............................................................................................
QSPI Integration .........................................................................................................
QSPI Block Diagram ....................................................................................................
SPI_CLKGEN Block ....................................................................................................
Logical Representation of the QSPI Interrupt Generation Scheme...............................................
QSPI_PID Register .....................................................................................................
QSPI_SYSCONFIG Register ..........................................................................................
QSPI_INTR_STS_RAW_SET Register ..............................................................................
QSPI_INTR_STS_EN_CLR Register .................................................................................
QSPI_INTR_EN_SET_REG Register ................................................................................
QSPI_INTR_EN_CLR_REG Register ................................................................................
QSPI_INTC_EOI_REG Register ......................................................................................
QSPI_CLOCK_CNTRL_REG Register ...............................................................................
QSPI_DC_REG Register ...............................................................................................
QSPI_CMD_REG Register ............................................................................................
QSPI_STS_REG Register .............................................................................................
QSPI_DATA_REG Register ...........................................................................................
QSPI_SETUP_REG_0 to QSPI_SETUP_REG_3 Register .......................................................
QSPI_SWITCH_REG Register ........................................................................................
QSPI_DATA_REG_1 Register ........................................................................................
QSPI_DATA_REG_2 Register ........................................................................................
QSPI_DATA_REG_3 Register ........................................................................................
GPIO0 Module Integration .............................................................................................
GPIO[1–5] Module Integration .........................................................................................
Interrupt Request Generation ..........................................................................................
Wake-Up Request Generation.........................................................................................
Write @ GPIO_CLRDATAOUT Register Example .................................................................
Write @ GPIO_SETIRQENx Register Example.....................................................................
General-Purpose Interface Used as a Keyboard Interface ........................................................
GPIO_REVISION Register .............................................................................................
GPIO_SYSCONFIG Register ..........................................................................................
GPIO_EOI Register .....................................................................................................
GPIO_IRQSTS_RAW_0 Register .....................................................................................
GPIO_IRQSTS_RAW_1 Register .....................................................................................
GPIO_IRQSTS_0 Register .............................................................................................
GPIO_IRQSTS_1 Register .............................................................................................
GPIO_IRQSTS_SET_0 Register ......................................................................................
GPIO_IRQSTS_SET_1 Register ......................................................................................
GPIO_IRQSTS_CLR_0 Register ......................................................................................
GPIO_IRQSTS_CLR_1 Register ......................................................................................
GPIO_IRQWAKEN_0 Register ........................................................................................
26-54. MCSPI_CH3CTRL Register
List of Figures
3673
3674
3675
3676
3679
3681
3684
3686
3689
3690
3691
3692
3693
3694
3695
3696
3697
3700
3702
3703
3704
3705
3706
3707
3708
3711
3712
3717
3718
3721
3722
3723
3725
3726
3727
3728
3729
3730
3731
3732
3733
3734
3735
3736
SPRUHL7I – April 2014 – Revised December 2019
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28-20. GPIO_IRQWAKEN_1 Register ........................................................................................ 3737
28-21. GPIO_SYSSTS Register ............................................................................................... 3738
28-22. GPIO_CTRL Register ................................................................................................... 3739
28-23. GPIO_OE Register ...................................................................................................... 3740
28-24. GPIO_DATAIN Register ................................................................................................ 3741
28-25. GPIO_DATAOUT Register ............................................................................................. 3742
28-26. GPIO_LEVELDETECT0 Register ..................................................................................... 3743
28-27. GPIO_LEVELDETECT1 Register ..................................................................................... 3744
28-28. GPIO_RISINGDETECT Register...................................................................................... 3745
28-29. GPIO_FALLINGDETECT Register .................................................................................... 3746
........................................................................................
GPIO_DEBOUNCINGTIME Register .................................................................................
GPIO_CLRDATAOUT Register .......................................................................................
GPIO_SETDATAOUT Register........................................................................................
SGX530 Integration .....................................................................................................
SGX Block Diagram .....................................................................................................
PRU-ICSS Block Diagram .............................................................................................
PRU-ICSS Integration ..................................................................................................
PRU Block Diagram .....................................................................................................
PRU Module Interface ..................................................................................................
Event Interface Mapping (R31) .......................................................................................
PRU R31 (GPI) Direct Input Mode Block Diagram .................................................................
PRU R31 (GPI) 16-Bit Parallel Capture Mode Block Diagram ....................................................
PRU R31 (GPI) 28-Bit Shift In Mode .................................................................................
PRU R30 (GPO) Direct Output Mode Block Diagram ..............................................................
PRU R30 (GPO) Shift Out Mode Block Diagram ...................................................................
Sigma Delta Block Diagram ............................................................................................
Sigma Delta Hardware Integrators Block Diagram (snoop = 0) ...................................................
Sigma Delta Hardware Integrators Block Diagram (snoop = 1) ...................................................
Peripheral I/F Block Diagram ..........................................................................................
TX Mode Start Condition ...............................................................................................
ENDAT<m>_CLK Stop High on Last RX Frame ....................................................................
ENDAT<m>_CLK Stop Low on Last RX Frame ....................................................................
ENDAT<m>_CLK Run Continuously .................................................................................
ENDAT<m>_CLK Stop High on Last TX Bit .........................................................................
Integration of the PRU and MPY/MAC ...............................................................................
Multiply-Only Mode Functional Diagram .............................................................................
Multiply and Accumulate Mode Functional Diagram ................................................................
Integration of PRU and Scratch Pad..................................................................................
Interrupt Controller Block Diagram ....................................................................................
Flow of System Events to Host ........................................................................................
Industrial Ethernet Peripheral Block Diagram .......................................................................
Sync Signal Generation Mode .........................................................................................
Examples of the Dependent Mode of SYNC1 .......................................................................
IEP DIGIO Data In ......................................................................................................
IEP DIGIO Data Out ....................................................................................................
UART Block Diagram ...................................................................................................
UART Clock Generation Diagram .....................................................................................
Relationships Between Data Bit, BCLK, and UART Input Clock ..................................................
28-30. GPIO_DEBOUNCEN Register
28-31.
28-32.
28-33.
29-1.
29-2.
30-1.
30-2.
30-3.
30-4.
30-5.
30-6.
30-7.
30-8.
30-9.
30-10.
30-11.
30-12.
30-13.
30-14.
30-15.
30-16.
30-17.
30-18.
30-19.
30-20.
30-21.
30-22.
30-23.
30-24.
30-25.
30-26.
30-27.
30-28.
30-29.
30-30.
30-31.
30-32.
30-33.
SPRUHL7I – April 2014 – Revised December 2019
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Copyright © 2014–2019, Texas Instruments Incorporated
List of Figures
3747
3748
3749
3750
3755
3757
3761
3764
3772
3774
3775
3777
3778
3779
3781
3782
3785
3787
3787
3792
3797
3798
3799
3800
3801
3804
3805
3806
3809
3813
3818
3822
3825
3826
3829
3830
3832
3833
3834
67
www.ti.com
30-34. UART Protocol Formats ................................................................................................ 3836
30-35. UART Interface Using Autoflow Diagram ............................................................................ 3839
3840
30-37. Autoflow Functional Timing Waveforms for UARTn_CTS
3840
30-38.
3842
30-39.
30-40.
30-41.
30-42.
30-43.
30-44.
30-45.
30-46.
30-47.
30-48.
30-49.
30-50.
30-51.
30-52.
30-53.
30-54.
30-55.
30-56.
30-57.
30-58.
30-59.
30-60.
30-61.
30-62.
30-63.
30-64.
30-65.
30-66.
30-67.
30-68.
30-69.
30-70.
30-71.
30-72.
30-73.
30-74.
30-75.
30-76.
30-77.
30-78.
30-79.
30-80.
30-81.
30-82.
68
........................................................
........................................................
UART Interrupt Request Enable Paths ...............................................................................
MII_RT Block Diagram..................................................................................................
Auto-forward .............................................................................................................
Auto-forward with PRU Snoop .........................................................................................
8- or 16-bit Processing with On-the-Fly Modifications ..............................................................
32-byte Double Buffer or Ping-Pong Processing ...................................................................
Data Nibble Structure ...................................................................................................
PRU R30, R31 Operations .............................................................................................
Reading and Writing FIFO Data .......................................................................................
RX Data Latch ...........................................................................................................
Start of Frame Detection ...............................................................................................
CRC Error Detection ....................................................................................................
RX Error Detection ......................................................................................................
Error Detection Window with Running Counter .....................................................................
RX L1 to PRU Interface ................................................................................................
MII RX Data to PRU R31 (R) and RX FIFO .........................................................................
RX L2 to PRU Interface ................................................................................................
Data and Status Register Dependency ..............................................................................
PRU to TX L1 Interface .................................................................................................
PRU to TX MII Interface ................................................................................................
TX Mask Mode...........................................................................................................
RX L1 to TX L1 Interface ...............................................................................................
MII Receive Multiplexer .................................................................................................
MII Transmit Multiplexer ................................................................................................
Scratch Pad Mode ......................................................................................................
PRU_ICSS_CTRL Register ............................................................................................
PRU_ICSS_CTRL_STS Register .....................................................................................
PRU_ICSS_CTRL_WAKEUP_EN Register .........................................................................
PRU_ICSS_CTRL_CYCLE Register .................................................................................
PRU_ICSS_CTRL_STALL Register ..................................................................................
PRU_ICSS_CTRL_CTBIR0 Register .................................................................................
PRU_ICSS_CTRL_CTBIR1 Register .................................................................................
PRU_ICSS_CTRL_CTPPR0 Register ................................................................................
PRU_ICSS_CTRL_CTPPR1 Register ................................................................................
PRU_ICSS_DBG_GPREG0 Register ................................................................................
PRU_ICSS_DBG_GPREG1 Register ................................................................................
PRU_ICSS_DBG_GPREG2 Register ................................................................................
PRU_ICSS_DBG_GPREG3 Register ................................................................................
PRU_ICSS_DBG_GPREG4 Register ................................................................................
PRU_ICSS_DBG_GPREG5 Register ................................................................................
PRU_ICSS_DBG_GPREG6 Register ................................................................................
PRU_ICSS_DBG_GPREG7 Register ................................................................................
PRU_ICSS_DBG_GPREG8 Register ................................................................................
PRU_ICSS_DBG_GPREG9 Register ................................................................................
PRU_ICSS_DBG_GPREG10 Register ...............................................................................
30-36. Autoflow Functional Timing Waveforms for UARTn_RTS
List of Figures
3846
3846
3847
3847
3847
3848
3848
3849
3850
3851
3851
3851
3852
3852
3853
3856
3856
3859
3859
3860
3860
3863
3863
3863
3867
3869
3870
3871
3872
3873
3874
3875
3876
3879
3880
3881
3882
3883
3884
3885
3886
3887
3888
3889
SPRUHL7I – April 2014 – Revised December 2019
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30-83. PRU_ICSS_DBG_GPREG11 Register ............................................................................... 3890
30-84. PRU_ICSS_DBG_GPREG12 Register ............................................................................... 3891
30-85. PRU_ICSS_DBG_GPREG13 Register ............................................................................... 3892
30-86. PRU_ICSS_DBG_GPREG14 Register ............................................................................... 3893
30-87. PRU_ICSS_DBG_GPREG15 Register ............................................................................... 3894
30-88. PRU_ICSS_DBG_GPREG16 Register ............................................................................... 3895
30-89. PRU_ICSS_DBG_GPREG17 Register ............................................................................... 3896
30-90. PRU_ICSS_DBG_GPREG18 Register ............................................................................... 3897
30-91. PRU_ICSS_DBG_GPREG19 Register ............................................................................... 3898
30-92. PRU_ICSS_DBG_GPREG20 Register ............................................................................... 3899
30-93. PRU_ICSS_DBG_GPREG21 Register ............................................................................... 3900
30-94. PRU_ICSS_DBG_GPREG22 Register ............................................................................... 3901
30-95. PRU_ICSS_DBG_GPREG23 Register ............................................................................... 3902
30-96. PRU_ICSS_DBG_GPREG24 Register ............................................................................... 3903
30-97. PRU_ICSS_DBG_GPREG25 Register ............................................................................... 3904
30-98. PRU_ICSS_DBG_GPREG26 Register ............................................................................... 3905
30-99. PRU_ICSS_DBG_GPREG27 Register ............................................................................... 3906
.............................................................................
.............................................................................
PRU_ICSS_DBG_GPREG30 Register .............................................................................
PRU_ICSS_DBG_GPREG31 Register .............................................................................
PRU_ICSS_DBG_CT_REG0 Register ..............................................................................
PRU_ICSS_DBG_CT_REG1 Register ..............................................................................
PRU_ICSS_DBG_CT_REG2 Register ..............................................................................
PRU_ICSS_DBG_CT_REG3 Register ..............................................................................
PRU_ICSS_DBG_CT_REG4 Register ..............................................................................
PRU_ICSS_DBG_CT_REG5 Register ..............................................................................
PRU_ICSS_DBG_CT_REG6 Register ..............................................................................
PRU_ICSS_DBG_CT_REG7 Register ..............................................................................
PRU_ICSS_DBG_CT_REG8 Register ..............................................................................
PRU_ICSS_DBG_CT_REG9 Register ..............................................................................
PRU_ICSS_DBG_CT_REG10 Register ............................................................................
PRU_ICSS_DBG_CT_REG11 Register ............................................................................
PRU_ICSS_DBG_CT_REG12 Register ............................................................................
PRU_ICSS_DBG_CT_REG13 Register ............................................................................
PRU_ICSS_DBG_CT_REG14 Register ............................................................................
PRU_ICSS_DBG_CT_REG15 Register ............................................................................
PRU_ICSS_DBG_CT_REG16 Register ............................................................................
PRU_ICSS_DBG_CT_REG17 Register ............................................................................
PRU_ICSS_DBG_CT_REG18 Register ............................................................................
PRU_ICSS_DBG_CT_REG19 Register ............................................................................
PRU_ICSS_DBG_CT_REG20 Register ............................................................................
PRU_ICSS_DBG_CT_REG21 Register ............................................................................
PRU_ICSS_DBG_CT_REG22 Register ............................................................................
PRU_ICSS_DBG_CT_REG23 Register ............................................................................
PRU_ICSS_DBG_CT_REG24 Register ............................................................................
PRU_ICSS_DBG_CT_REG25 Register ............................................................................
PRU_ICSS_DBG_CT_REG26 Register ............................................................................
PRU_ICSS_DBG_CT_REG27 Register ............................................................................
30-100. PRU_ICSS_DBG_GPREG28 Register
3907
30-101. PRU_ICSS_DBG_GPREG29 Register
3908
30-102.
3909
30-103.
30-104.
30-105.
30-106.
30-107.
30-108.
30-109.
30-110.
30-111.
30-112.
30-113.
30-114.
30-115.
30-116.
30-117.
30-118.
30-119.
30-120.
30-121.
30-122.
30-123.
30-124.
30-125.
30-126.
30-127.
30-128.
30-129.
30-130.
30-131.
SPRUHL7I – April 2014 – Revised December 2019
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List of Figures
3910
3911
3912
3913
3914
3915
3916
3917
3918
3919
3920
3921
3922
3923
3924
3925
3926
3927
3928
3929
3930
3931
3932
3933
3934
3935
3936
3937
3938
69
www.ti.com
30-132. PRU_ICSS_DBG_CT_REG28 Register ............................................................................ 3939
30-133. PRU_ICSS_DBG_CT_REG29 Register ............................................................................ 3940
30-134. PRU_ICSS_DBG_CT_REG30 Register ............................................................................ 3941
30-135. PRU_ICSS_DBG_CT_REG31 Register ............................................................................ 3942
30-136. PRU_ICSS_INTC_REVID Register.................................................................................. 3944
30-137. PRU_ICSS_INTC_CR Register ...................................................................................... 3945
30-138. PRU_ICSS_INTC_GER Register .................................................................................... 3946
30-139. PRU_ICSS_INTC_GNLR Register .................................................................................. 3947
3948
30-141.
3949
30-142.
30-143.
30-144.
30-145.
30-146.
30-147.
30-148.
30-149.
30-150.
30-151.
30-152.
30-153.
30-154.
30-155.
30-156.
30-157.
30-158.
30-159.
30-160.
30-161.
30-162.
30-163.
30-164.
30-165.
30-166.
30-167.
30-168.
30-169.
30-170.
30-171.
30-172.
30-173.
30-174.
30-175.
30-176.
30-177.
30-178.
30-179.
30-180.
70
...................................................................................
PRU_ICSS_INTC_SICR Register ...................................................................................
PRU_ICSS_INTC_EISR Register ...................................................................................
PRU_ICSS_INTC_EICR Register ...................................................................................
PRU_ICSS_INTC_HIEISR Register .................................................................................
PRU_ICSS_INTC_HIDISR Register .................................................................................
PRU_ICSS_INTC_GPIR Register ...................................................................................
PRU_ICSS_INTC_SRSR0 Register .................................................................................
PRU_ICSS_INTC_SRSR1 Register .................................................................................
PRU_ICSS_INTC_SECR0 Register .................................................................................
PRU_ICSS_INTC_SECR1 Register .................................................................................
PRU_ICSS_INTC_ESR0 Register ...................................................................................
PRU_ICSS_INTC_ERS1 Register ...................................................................................
PRU_ICSS_INTC_ECR0 Register...................................................................................
PRU_ICSS_INTC_ECR1 Register...................................................................................
PRU_ICSS_INTC_CMR0 Register ..................................................................................
PRU_ICSS_INTC_CMR1 Register ..................................................................................
PRU_ICSS_INTC_CMR2 Register ..................................................................................
PRU_ICSS_INTC_CMR3 Register ..................................................................................
PRU_ICSS_INTC_CMR4 Register ..................................................................................
PRU_ICSS_INTC_CMR5 Register ..................................................................................
PRU_ICSS_INTC_CMR6 Register ..................................................................................
PRU_ICSS_INTC_CMR7 Register ..................................................................................
PRU_ICSS_INTC_CMR8 Register ..................................................................................
PRU_ICSS_INTC_CMR9 Register ..................................................................................
PRU_ICSS_INTC_CMR10 Register .................................................................................
PRU_ICSS_INTC_CMR11 Register .................................................................................
PRU_ICSS_INTC_CMR12 Register .................................................................................
PRU_ICSS_INTC_CMR13 Register .................................................................................
PRU_ICSS_INTC_CMR14 Register .................................................................................
PRU_ICSS_INTC_CMR15 Register .................................................................................
PRU_ICSS_INTC_HMR0 Register ..................................................................................
PRU_ICSS_INTC_HMR1 Register ..................................................................................
PRU_ICSS_INTC_HMR2 Register ..................................................................................
PRU_ICSS_INTC_HIPIR0 Register .................................................................................
PRU_ICSS_INTC_HIPIR1 Register .................................................................................
PRU_ICSS_INTC_HIPIR2 Register .................................................................................
PRU_ICSS_INTC_HIPIR3 Register .................................................................................
PRU_ICSS_INTC_HIPIR4 Register .................................................................................
PRU_ICSS_INTC_HIPIR5 Register .................................................................................
PRU_ICSS_INTC_HIPIR6 Register .................................................................................
30-140. PRU_ICSS_INTC_SISR Register
List of Figures
3950
3951
3952
3953
3954
3955
3956
3957
3958
3959
3960
3961
3962
3963
3964
3965
3966
3967
3968
3969
3970
3971
3972
3973
3974
3975
3976
3977
3978
3979
3980
3981
3982
3983
3984
3985
3986
3987
3988
SPRUHL7I – April 2014 – Revised December 2019
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30-181. PRU_ICSS_INTC_HIPIR7 Register ................................................................................. 3989
30-182. PRU_ICSS_INTC_HIPIR8 Register ................................................................................. 3990
30-183. PRU_ICSS_INTC_HIPIR9 Register ................................................................................. 3991
30-184. PRU_ICSS_INTC_SIPR0 Register .................................................................................. 3992
30-185. PRU_ICSS_INTC_SIPR1 Register .................................................................................. 3993
30-186. PRU_ICSS_INTC_SITR0 Register .................................................................................. 3994
30-187. PRU_ICSS_INTC_SITR1 Register .................................................................................. 3995
30-188. PRU_ICSS_INTC_HINLR0 Register ................................................................................ 3996
30-189. PRU_ICSS_INTC_HINLR1 Register ................................................................................ 3997
30-190. PRU_ICSS_INTC_HINLR2 Register ................................................................................ 3998
30-191. PRU_ICSS_INTC_HINLR3 Register ................................................................................ 3999
30-192. PRU_ICSS_INTC_HINLR4 Register ................................................................................ 4000
30-193. PRU_ICSS_INTC_HINLR5 Register ................................................................................ 4001
30-194. PRU_ICSS_INTC_HINLR6 Register ................................................................................ 4002
30-195. PRU_ICSS_INTC_HINLR7 Register ................................................................................ 4003
30-196. PRU_ICSS_INTC_HINLR8 Register ................................................................................ 4004
30-197. PRU_ICSS_INTC_HINLR9 Register ................................................................................ 4005
30-198. PRU_ICSS_INTC_HIER Register ................................................................................... 4006
30-199. PRU_ICSS_IEP_TMR_GLB_CFG Register ........................................................................ 4008
30-200. PRU_ICSS_IEP_TMR_GLB_STS Register ........................................................................ 4009
30-201. PRU_ICSS_IEP_TMR_COMPEN Register......................................................................... 4010
30-202. PRU_ICSS_IEP_TMR_CNT Register ............................................................................... 4011
30-203. PRU_ICSS_IEP_TMR_CAP_CFG Register ........................................................................ 4012
30-204. PRU_ICSS_IEP_TMR_CAP_STS Register ........................................................................ 4014
...........................................................................
...........................................................................
PRU_ICSS_IEP_TMR_CAPR2 Register ...........................................................................
PRU_ICSS_IEP_TMR_CAPR3 Register ...........................................................................
PRU_ICSS_IEP_TMR_CAPR4 Register ...........................................................................
PRU_ICSS_IEP_TMR_CAPR5 Register ...........................................................................
PRU_ICSS_IEP_TMR_CAPR6 Register ...........................................................................
PRU_ICSS_IEP_TMR_CAPF6 Register ............................................................................
PRU_ICSS_IEP_TMR_CAPR7 Register ...........................................................................
PRU_ICSS_IEP_TMR_CAPF7 Register ............................................................................
PRU_ICSS_IEP_TMR_CMP_CFG Register .......................................................................
PRU_ICSS_IEP_TMR_CMP_STS Register ........................................................................
PRU_ICSS_IEP_TMR_CMP0 Register .............................................................................
PRU_ICSS_IEP_TMR_CMP1 Register .............................................................................
PRU_ICSS_IEP_TMR_CMP2 Register .............................................................................
PRU_ICSS_IEP_TMR_CMP3 Register .............................................................................
PRU_ICSS_IEP_TMR_CMP4 Register .............................................................................
PRU_ICSS_IEP_TMR_CMP5 Register .............................................................................
PRU_ICSS_IEP_TMR_CMP6 Register .............................................................................
PRU_ICSS_IEP_TMR_CMP7 Register .............................................................................
PRU_ICSS_IEP_TMR_RXIPG0 Register ..........................................................................
PRU_ICSS_IEP_TMR_RXIPG1 Register ..........................................................................
PRU_ICSS_IEP_TMR_CMP8 Register .............................................................................
PRU_ICSS_IEP_TMR_CMP9 Register .............................................................................
PRU_ICSS_IEP_TMR_CMP10 Register ...........................................................................
30-205. PRU_ICSS_IEP_TMR_CAPR0 Register
4015
30-206. PRU_ICSS_IEP_TMR_CAPR1 Register
4016
30-207.
4017
30-208.
30-209.
30-210.
30-211.
30-212.
30-213.
30-214.
30-215.
30-216.
30-217.
30-218.
30-219.
30-220.
30-221.
30-222.
30-223.
30-224.
30-225.
30-226.
30-227.
30-228.
30-229.
SPRUHL7I – April 2014 – Revised December 2019
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Copyright © 2014–2019, Texas Instruments Incorporated
List of Figures
4018
4019
4020
4021
4022
4023
4024
4025
4026
4027
4028
4029
4030
4031
4032
4033
4034
4035
4036
4037
4038
4039
71
www.ti.com
4040
30-231.
4041
30-232.
30-233.
30-234.
30-235.
30-236.
30-237.
30-238.
30-239.
30-240.
30-241.
30-242.
30-243.
30-244.
30-245.
30-246.
30-247.
30-248.
30-249.
30-250.
30-251.
30-252.
30-253.
30-254.
30-255.
30-256.
30-257.
30-258.
30-259.
30-260.
30-261.
30-262.
30-263.
30-264.
30-265.
30-266.
30-267.
30-268.
30-269.
30-270.
30-271.
30-272.
30-273.
30-274.
30-275.
30-276.
30-277.
30-278.
72
...........................................................................
PRU_ICSS_IEP_TMR_CMP12 Register ...........................................................................
PRU_ICSS_IEP_TMR_CMP13 Register ...........................................................................
PRU_ICSS_IEP_TMR_CMP14 Register ...........................................................................
PRU_ICSS_IEP_TMR_CMP15 Register ...........................................................................
PRU_ICSS_IEP_TMR_CNT_RST Register ........................................................................
PRU_ICSS_IEP_TMR_PWM Register ..............................................................................
PRU_ICSS_IEP_SYNC_CTRL Register ............................................................................
PRU_ICSS_IEP_SYNC_FIRST_STAT Register...................................................................
PRU_ICSS_IEP_SYNC0_STAT Register ..........................................................................
PRU_ICSS_IEP_SYNC1_STAT Register ..........................................................................
PRU_ICSS_IEP_SYNC_PWIDTH Register ........................................................................
PRU_ICSS_IEP_SYNC0_PERIOD Register .......................................................................
PRU_ICSS_IEP_SYNC1_DELAY Register ........................................................................
PRU_ICSS_IEP_SYNC_START Register ..........................................................................
PRU_ICSS_IEP_WD_PREDIV Register ............................................................................
PRU_ICSS_IEP_PDI_WD_TIM Register ...........................................................................
PRU_ICSS_IEP_PD_WD_TIM Register ............................................................................
PRU_ICSS_IEP_WD_STS Register ................................................................................
PRU_ICSS_IEP_WD_EXP_CNT Register .........................................................................
PRU_ICSS_IEP_WD_CTRL Register ...............................................................................
PRU_ICSS_IEP_DIGIO_CTRL Register............................................................................
PRU_ICSS_IEP_DIGIO_STATUS Register ........................................................................
PRU_ICSS_IEP_DIGIO_DATA_IN Register .......................................................................
PRU_ICSS_IEP_DIGIO_DATA_IN_RAW Register ...............................................................
PRU_ICSS_IEP_DIGIO_DATA_OUT Register ....................................................................
PRU_ICSS_IEP_DIGIO_DATA_OUT_EN Register ...............................................................
PRU_ICSS_IEP_DIGIO_EXP Register .............................................................................
Receiver Buffer Register (RBR)......................................................................................
Transmitter Holding Register (THR) .................................................................................
Interrupt Enable Register (IER) ......................................................................................
Interrupt Identification Register (IIR) ................................................................................
FIFO Control Register (FCR) .........................................................................................
Line Control Register (LCR) ..........................................................................................
Modem Control Register (MCR) .....................................................................................
Line Status Register (LSR) ...........................................................................................
Modem Status Register (MSR) ......................................................................................
Scratch Pad Register (SCR) .........................................................................................
Divisor LSB Latch (DLL) ..............................................................................................
Divisor MSB Latch (DLH) .............................................................................................
Revision Identification Register 1 (REVID1)........................................................................
Revision Identification Register 2 (REVID2)........................................................................
Power and Emulation Management Register (PWREMU_MGMT)..............................................
Mode Definition Register (MDR) .....................................................................................
RXCFG0 Register ......................................................................................................
RXCFG1 Register ......................................................................................................
TXCFG0 Register ......................................................................................................
TXCFG1 Register ......................................................................................................
TXCRC0 Register ......................................................................................................
30-230. PRU_ICSS_IEP_TMR_CMP11 Register
List of Figures
4042
4043
4044
4045
4046
4047
4048
4049
4050
4051
4052
4053
4054
4055
4056
4057
4058
4059
4060
4061
4062
4063
4064
4065
4066
4067
4069
4070
4071
4072
4074
4075
4077
4078
4081
4082
4083
4083
4084
4084
4085
4086
4088
4090
4092
4094
4096
SPRUHL7I – April 2014 – Revised December 2019
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Copyright © 2014–2019, Texas Instruments Incorporated
www.ti.com
30-279. TXCRC1 Register ...................................................................................................... 4097
30-280. TXIPG0 Register ....................................................................................................... 4098
30-281. TXIPG1 Register ....................................................................................................... 4099
.........................................................................................................
30-283. PRS1 Register .........................................................................................................
30-284. RXFRMS0 Register ....................................................................................................
30-285. RXFRMS1 Register ....................................................................................................
30-286. RXPCNT0 Register ....................................................................................................
30-287. RXPCNT1 Register ....................................................................................................
30-288. RXERR0 Register ......................................................................................................
30-289. RXERR1 Register ......................................................................................................
30-290. RXFLV0 Register ......................................................................................................
30-291. RXFLV1 Register ......................................................................................................
30-292. TXFLV0 Register .......................................................................................................
30-293. TXFLV1 Register .......................................................................................................
30-294. PRU_ICSS_CFG_REVID Register ..................................................................................
30-295. PRU_ICSS_CFG_SYSCFG Register ...............................................................................
30-296. PRU_ICSS_CFG_GPCFG0 Register ...............................................................................
30-297. PRU_ICSS_CFG_GPCFG1 Register ...............................................................................
30-298. PRU_ICSS_CFG_CGR Register ....................................................................................
30-299. PRU_ICSS_CFG_ISRP Register ....................................................................................
30-300. PRU_ICSS_CFG_ISP Register ......................................................................................
30-301. PRU_ICSS_CFG_IESP Register ....................................................................................
30-302. PRU_ICSS_CFG_IECP Register ....................................................................................
30-303. PRU_ICSS_CFG_PMAO Register ..................................................................................
30-304. PRU_ICSS_CFG_MII_RT Register..................................................................................
30-305. PRU_ICSS_CFG_IEPCLK Register .................................................................................
30-306. PRU_ICSS_CFG_SPP Register .....................................................................................
30-307. PRU_ICSS_CFG_PIN_MX Register ................................................................................
30-308. PRU_ICSS_CFG_SD_P0_CLK_i Register .........................................................................
30-309. PRU_ICSS_CFG_SD_P0_SS_i Register ...........................................................................
30-310. PRU_ICSS_CFG_SD_P1_CLK_i Register .........................................................................
30-311. PRU_ICSS_CFG_SD_P1_SS_i Register ...........................................................................
30-312. PRU_ICSS_CFG_ED_P0_RXCFG Register .......................................................................
30-313. PRU_ICSS_CFG_ED_P0_TXCFG Register .......................................................................
30-314. PRU_ICSS_CFG_ED_P0_CFG0_i Register .......................................................................
30-315. PRU_ICSS_CFG_ED_P0_CFG1_i Register .......................................................................
30-316. PRU_ICSS_CFG_ED_P1_RXCFG Register .......................................................................
30-317. PRU_ICSS_CFG_ED_P1_TXCFG Register .......................................................................
30-318. PRU_ICSS_CFG_ED_P1_CFG0_i Register .......................................................................
30-319. PRU_ICSS_CFG_ED_P1_CFG1_i Register .......................................................................
31-1. Functional Block Diagram Debug View ..............................................................................
31-2. MPU Subsystem Cross Trigger Connections ........................................................................
31-3. SoC Processor Trace Flow ............................................................................................
31-4. SoC L3 System Instrumentation Topology ...........................................................................
31-5. DEBUGSS_DRM_SUSPEND_CTRL0 Register ....................................................................
31-6. DEBUGSS_DRM_SUSPEND_CTRL1 Register ....................................................................
31-7. DEBUGSS_DRM_SUSPEND_CTRL2 Register ....................................................................
31-8. DEBUGSS_DRM_SUSPEND_CTRL3 Register ....................................................................
30-282. PRS0 Register
SPRUHL7I – April 2014 – Revised December 2019
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Copyright © 2014–2019, Texas Instruments Incorporated
List of Figures
4100
4101
4102
4103
4104
4105
4106
4107
4108
4109
4110
4111
4113
4114
4115
4117
4119
4121
4122
4123
4124
4125
4126
4127
4128
4129
4130
4131
4132
4133
4134
4135
4136
4138
4139
4140
4141
4143
4146
4154
4157
4159
4172
4173
4174
4175
73
www.ti.com
31-9.
31-10.
31-11.
31-12.
31-13.
31-14.
31-15.
31-16.
31-17.
31-18.
31-19.
31-20.
31-21.
31-22.
31-23.
31-24.
31-25.
31-26.
31-27.
74
....................................................................
DEBUGSS_DRM_SUSPEND_CTRL5 Register ....................................................................
DEBUGSS_DRM_SUSPEND_CTRL6 Register ....................................................................
DEBUGSS_DRM_SUSPEND_CTRL7 Register ....................................................................
DEBUGSS_DRM_SUSPEND_CTRL8 Register ....................................................................
DEBUGSS_DRM_SUSPEND_CTRL10 Register ...................................................................
DEBUGSS_DRM_SUSPEND_CTRL11 Register ...................................................................
DEBUGSS_DRM_SUSPEND_CTRL12 Register ...................................................................
DEBUGSS_DRM_SUSPEND_CTRL13 Register ...................................................................
DEBUGSS_DRM_SUSPEND_CTRL14 Register ...................................................................
DEBUGSS_DRM_SUSPEND_CTRL15 Register ...................................................................
DEBUGSS_DRM_SUSPEND_CTRL16 Register ...................................................................
DEBUGSS_DRM_SUSPEND_CTRL17 Register ...................................................................
DEBUGSS_DRM_SUSPEND_CTRL18 Register ...................................................................
DEBUGSS_DRM_SUSPEND_CTRL19 Register ...................................................................
DEBUGSS_DRM_SUSPEND_CTRL24 Register ...................................................................
DEBUGSS_DRM_SUSPEND_CTRL27 Register ...................................................................
DEBUGSS_DRM_SUSPEND_CTRL28 Register ...................................................................
DEBUGSS_DRM_SUSPEND_CTRL29 Register ...................................................................
DEBUGSS_DRM_SUSPEND_CTRL4 Register
List of Figures
4176
4177
4178
4179
4180
4181
4182
4183
4184
4185
4186
4187
4188
4189
4190
4191
4192
4193
4194
SPRUHL7I – April 2014 – Revised December 2019
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Copyright © 2014–2019, Texas Instruments Incorporated
www.ti.com
List of Tables
1-1.
Device Identification Registers .......................................................................................... 139
2-1.
L3 Memory Map ........................................................................................................... 141
2-2.
L4_WKUP Memory Map ................................................................................................. 143
2-3.
L4_PER Peripheral Memory Map....................................................................................... 144
2-4.
L4 Fast Peripheral Memory Map
3-1.
3-2.
3-3.
3-4.
3-5.
3-6.
3-7.
3-8.
3-9.
4-1.
4-2.
5-1.
5-2.
5-3.
5-4.
5-5.
5-6.
5-7.
5-8.
5-9.
5-10.
5-11.
5-12.
5-13.
5-14.
5-15.
5-16.
5-17.
5-18.
5-19.
5-20.
5-21.
5-22.
5-23.
5-24.
5-25.
5-26.
5-27.
5-28.
5-29.
5-30.
5-31.
.......................................................................................
Summary of Configuration Registers in WkUpGen Unit .............................................................
WFI/WFE Control Register Field Descriptions ........................................................................
WkupGenEnb Registers Field Descriptions ...........................................................................
WATCHDOG REGISTERS ..............................................................................................
GLOBAL TIMER REGISTERS ..........................................................................................
PL310 REGISTERS ......................................................................................................
DISTRIBUTOR REGISTERS............................................................................................
INTC REGISTERS........................................................................................................
SCU REGISTERS ........................................................................................................
L3 Master — Slave Connectivity ........................................................................................
MConnID Assignment ....................................................................................................
Public ROM Exception Vectors .........................................................................................
Dead Loops ................................................................................................................
Boot Error Counters ......................................................................................................
RAM Exception Vectors ..................................................................................................
RAM Exception Handlers Location .....................................................................................
Tracing Data ...............................................................................................................
Crystal Frequencies Supported .........................................................................................
ROM Code Default Clock Settings .....................................................................................
Booting Parameters Structure ...........................................................................................
SYSBOOT Configuration Pins ..........................................................................................
NOR Timings Parameters ...............................................................................................
Pins Used for NOR Boot Common Signals ...........................................................................
Pins Used for NOR Boot Wait Pin Selection ..........................................................................
Pins Used for non-Mux NOR Boot .....................................................................................
Pins Used for Mux NOR Boot ..........................................................................................
SYSBOOT Signals for NOR Boot ......................................................................................
Parameters for NAND Timings ..........................................................................................
ONFI Parameters Page Description ....................................................................................
Supported NAND Devices ...............................................................................................
4th NAND ID Data Byte ..................................................................................................
Pins Used for NAND I2C Boot for I2C EEPROM Access ...........................................................
NAND Geometry Information on I2C EEPROM ......................................................................
Pins Used for NAND Boot ...............................................................................................
Pins Used for NAND Boot Wait Pin Selection ........................................................................
SYSBOOT Signals for NAND Boot .....................................................................................
Master Boot Record Structure ..........................................................................................
Partition Entry .............................................................................................................
Partition Types ............................................................................................................
FAT Boot Sector ..........................................................................................................
FAT Directory Entry ......................................................................................................
FAT Entry Description ....................................................................................................
SPRUHL7I – April 2014 – Revised December 2019
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List of Tables
150
157
158
160
161
161
162
164
165
165
171
172
178
179
180
181
181
181
184
184
186
187
200
200
200
200
202
202
204
206
206
207
208
208
212
213
213
217
218
218
220
223
224
75
www.ti.com
5-32.
Pins Used for MMC0 Boot ............................................................................................... 224
5-33.
Pins Used for MMC1 Boot ............................................................................................... 224
5-34.
Pins Used for SPI Boot
5-35.
Pins Used for QSPI Boot ................................................................................................ 226
5-36.
SYSBOOT Signals for QSPI Boot ...................................................................................... 228
5-37.
Pins Used for USB_MS Boot ............................................................................................ 229
5-38.
SYSBOOT Signals for USB_MS Boot
5-39.
Blocks and Sectors Searched on non-XIP Memories ................................................................ 229
5-40.
Pins Used for EMAC Boot in MII Mode ................................................................................ 233
5-41.
Pins Used for EMAC Boot in RGMII Mode ............................................................................ 233
5-42.
Pins Used for EMAC Boot in RMII Mode .............................................................................. 234
5-43.
Ethernet PHY Mode Selection .......................................................................................... 234
5-44.
Ethernet Clock Selection ................................................................................................. 234
5-45.
Pins Used for UART Boot
5-46.
5-47.
5-48.
5-49.
5-50.
5-51.
5-52.
5-53.
5-54.
5-55.
5-56.
5-57.
5-58.
5-59.
5-60.
5-61.
5-62.
5-63.
5-64.
5-65.
6-1.
6-2.
6-3.
6-4.
6-5.
6-6.
6-7.
6-8.
6-9.
6-10.
6-11.
6-12.
6-13.
6-14.
6-15.
76
..................................................................................................
.................................................................................
...............................................................................................
Customized Descriptor Parameters ....................................................................................
Pins Used for USB_CL Boot ............................................................................................
SYSBOOT Signals for USB_CL Boot ..................................................................................
SYSBOOT Signals for Low Latency NOR Boot ......................................................................
GP Device Image Format ................................................................................................
The TOC Item Fields .....................................................................................................
Magic Values for MMC RAW Mode ....................................................................................
Filenames in TOC for GP Device .......................................................................................
L2 Cache Set Debug Register ..........................................................................................
L2 Cache Clean and Invalidate Range of Physical Address ........................................................
L2 Cache Set Control Register .........................................................................................
L2 Cache Set Auxiliary Control Register ..............................................................................
L2 Cache Set Latency Control Register ...............................................................................
L2 Cache Set Pre-fetch Control Register ..............................................................................
L2 Cache Set Address Filtering Register ..............................................................................
L2 Cache Clean Set Way ................................................................................................
L1 Cache Set Pre-fetch Enable .........................................................................................
SCTLR Round-Robin Enable............................................................................................
CP15 Set ACTLR Register ..............................................................................................
Tracing Vectors ...........................................................................................................
Master Module Standby-Mode Settings ...............................................................................
Master Module Standby Status ........................................................................................
Module Idle Mode Settings ..............................................................................................
Idle States for a Slave Module ..........................................................................................
Slave Module Mode Settings in PRCM ................................................................................
Module Clock Enabling Condition ......................................................................................
Clock Domain Functional Clock States ................................................................................
Clock Domain States .....................................................................................................
Clock Transition Mode Settings .........................................................................................
States of a Memory Area in a Power Domain ........................................................................
States of a Logic Area in a Power Domain ............................................................................
Power Domain Control and Status Registers .........................................................................
Typical Power Modes ....................................................................................................
USB Wakeup Use Cases Supported in System Sleep States ......................................................
CMD_STAT Field .........................................................................................................
List of Tables
225
229
235
237
238
238
239
241
241
241
241
242
242
242
242
243
243
243
243
243
244
244
245
251
252
252
253
253
254
255
256
256
257
257
257
259
263
266
SPRUHL7I – April 2014 – Revised December 2019
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Copyright © 2014–2019, Texas Instruments Incorporated
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6-16.
CMD_ID Field ............................................................................................................. 266
6-17.
Output Clocks in Locked Condition ..................................................................................... 273
6-18.
Output Clocks Before Lock and During Relock Modes .............................................................. 273
6-19.
Output Clocks in Locked Condition ..................................................................................... 275
6-20.
Output Clocks Before Lock and During Relock Modes .............................................................. 275
6-21.
PLL and Clock Frequences.............................................................................................. 280
6-22.
Core PLL Typical Frequencies (MHz) .................................................................................. 281
6-23.
Bus Interface Clocks
6-24.
Per PLL Typical Frequencies (MHz) ................................................................................... 283
6-25.
Latency and Power for PLL Bypass Modes ........................................................................... 288
6-26.
Effects of Temperature Drift on Relock ................................................................................ 288
6-27.
32-kHz Clock Summary .................................................................................................. 290
6-28.
Reset Sources............................................................................................................. 300
6-29.
Core Logic Voltage and Power Domains .............................................................................. 302
6-30.
Power Domain State Table .............................................................................................. 302
6-31.
Power Domain of Various Modules
6-32.
6-33.
6-34.
6-35.
6-36.
6-37.
6-38.
6-39.
6-40.
6-41.
6-42.
6-43.
6-44.
6-45.
6-46.
6-47.
6-48.
6-49.
6-50.
6-51.
6-52.
6-53.
6-54.
6-55.
6-56.
6-57.
6-58.
6-59.
6-60.
6-61.
6-62.
6-63.
6-64.
.....................................................................................................
....................................................................................
PRCM_PRM_CEFUSE REGISTERS ..................................................................................
PRCM_PM_CEFUSE_PWRSTCTRL Register Field Descriptions .................................................
PRCM_PM_CEFUSE_PWRSTST Register Field Descriptions ....................................................
PRCM_RM_CEFUSE_CONTEXT Register Field Descriptions .....................................................
PRCM_PRM_DEVICE REGISTERS ...................................................................................
PRCM_PRM_RSTCTRL Register Field Descriptions ................................................................
PRCM_PRM_RSTST Register Field Descriptions ...................................................................
PRCM_PRM_RSTTIME Register Field Descriptions ................................................................
PRCM_PRM_SRAM_COUNT Register Field Descriptions .........................................................
PRCM_PRM_LDO_SRAM_CORE_SETUP Register Field Descriptions..........................................
PRCM_PRM_LDO_SRAM_CORE_CTRL Register Field Descriptions ...........................................
PRCM_PRM_LDO_SRAM_MPU_SETUP Register Field Descriptions ...........................................
PRCM_PRM_LDO_SRAM_MPU_CTRL Register Field Descriptions .............................................
PRCM_PRM_IO_COUNT Register Field Descriptions ..............................................................
PRCM_PRM_IO_PMCTRL Register Field Descriptions .............................................................
PRCM_PRM_VC_VAL_BYPASS Register Field Descriptions......................................................
PRCM_PRM_EMIF_CTRL Register Field Descriptions .............................................................
PRCM_PRM_GFX REGISTERS .......................................................................................
PRCM_PRM_PM_GFX_PWRSTCTRL Register Field Descriptions ...............................................
PRCM_PRM_PM_GFX_PWRSTST Register Field Descriptions ..................................................
PRCM_PRM_RM_GFX_RSTCTRL Register Field Descriptions ...................................................
PRCM_PRM_RM_GFX_RSTST Register Field Descriptions.......................................................
PRCM_PRM_RM_GFX_CONTEXT Register Field Descriptions...................................................
PRM_MPU Registers.....................................................................................................
PRCM_PM_MPU_PWRSTCTRL Register Field Descriptions ......................................................
PRCM_PM_MPU_PWRSTST Register Field Descriptions .........................................................
PRCM_RM_MPU_RSTST Register Field Descriptions ..............................................................
PRCM_RM_MPU_CONTEXT Register Field Descriptions..........................................................
PRCM_PRM_PER REGISTERS .......................................................................................
PRCM_PM_PER_PWRSTCTRL Register Field Descriptions ......................................................
PRCM_PM_PER_PWRSTST Register Field Descriptions ..........................................................
PRCM_RM_PER_RSTCTRL Register Field Descriptions ..........................................................
PRCM_RM_PER_RSTST Register Field Descriptions ..............................................................
SPRUHL7I – April 2014 – Revised December 2019
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Copyright © 2014–2019, Texas Instruments Incorporated
List of Tables
282
303
307
308
309
310
310
312
313
314
315
316
318
319
321
322
323
325
326
326
327
328
329
330
331
331
332
334
336
337
338
340
342
344
345
77
www.ti.com
6-65.
PRCM_RM_PER_L3_CONTEXT Register Field Descriptions...................................................... 346
6-66.
PRCM_RM_PER_L3_INSTR_CONTEXT Register Field Descriptions ............................................ 347
6-67.
PRCM_RM_PER_OCMCRAM_CONTEXT Register Field Descriptions .......................................... 348
6-68.
PRCM_RM_PER_VPFE0_CONTEXT Register Field Descriptions ................................................ 349
6-69.
PRCM_RM_PER_VPFE1_CONTEXT Register Field Descriptions ................................................ 350
6-70.
PRCM_RM_PER_TPCC_CONTEXT Register Field Descriptions ................................................. 351
6-71.
PRCM_RM_PER_TPTC0_CONTEXT Register Field Descriptions ................................................ 352
6-72.
PRCM_RM_PER_TPTC1_CONTEXT Register Field Descriptions ................................................ 353
6-73.
PRCM_RM_PER_TPTC2_CONTEXT Register Field Descriptions ................................................ 354
6-74.
PRCM_RM_PER_DLL_AGING_CONTEXT Register Field Descriptions
6-75.
PRCM_RM_PER_L4HS_CONTEXT Register Field Descriptions .................................................. 356
6-76.
PRCM_RM_PER_GPMC_CONTEXT Register Field Descriptions
6-77.
PRCM_RM_PER_ADC1_CONTEXT Register Field Descriptions ................................................. 358
6-78.
PRCM_RM_PER_MCASP0_CONTEXT Register Field Descriptions
6-79.
6-80.
6-81.
6-82.
6-83.
6-84.
6-85.
6-86.
6-87.
6-88.
6-89.
6-90.
6-91.
6-92.
6-93.
6-94.
6-95.
6-96.
6-97.
6-98.
6-99.
6-100.
6-101.
6-102.
6-103.
6-104.
6-105.
6-106.
6-107.
6-108.
6-109.
6-110.
6-111.
6-112.
6-113.
78
.........................................
................................................
.............................................
PRCM_RM_PER_MCASP1_CONTEXT Register Field Descriptions .............................................
PRCM_RM_PER_MMC2_CONTEXT Register Field Descriptions.................................................
PRCM_RM_PER_QSPI_CONTEXT Register Field Descriptions ..................................................
PRCM_RM_PER_USB_OTG_SS0_CONTEXT Register Field Descriptions .....................................
PRCM_RM_PER_USB_OTG_SS1_CONTEXT Register Field Descriptions .....................................
PRCM_RM_PER_PRU_ICSS_CONTEXT Register Field Descriptions ...........................................
PRCM_RM_PER_L4LS_CONTEXT Register Field Descriptions ..................................................
PRCM_RM_PER_DCAN0_CONTEXT Register Field Descriptions ...............................................
PRCM_RM_PER_DCAN1_CONTEXT Register Field Descriptions ...............................................
PRCM_RM_PER_PWMSS0_CONTEXT Register Field Descriptions .............................................
PRCM_RM_PER_PWMSS1_CONTEXT Register Field Descriptions .............................................
PRCM_RM_PER_PWMSS2_CONTEXT Register Field Descriptions .............................................
PRCM_RM_PER_PWMSS3_CONTEXT Register Field Descriptions .............................................
PRCM_RM_PER_PWMSS4_CONTEXT Register Field Descriptions .............................................
PRCM_RM_PER_PWMSS5_CONTEXT Register Field Descriptions .............................................
PRCM_RM_PER_ELM_CONTEXT Register Field Descriptions ...................................................
PRCM_RM_PER_GPIO1_CONTEXT Register Field Descriptions ................................................
PRCM_RM_PER_GPIO2_CONTEXT Register Field Descriptions ................................................
PRCM_RM_PER_GPIO3_CONTEXT Register Field Descriptions ................................................
PRCM_RM_PER_GPIO4_CONTEXT Register Field Descriptions ................................................
PRCM_RM_PER_GPIO5_CONTEXT Register Field Descriptions ................................................
PRCM_RM_PER_HDQ1W_CONTEXT Register Field Descriptions ..............................................
PRCM_RM_PER_I2C1_CONTEXT Register Field Descriptions ...................................................
PRCM_RM_PER_I2C2_CONTEXT Register Field Descriptions ...................................................
PRCM_RM_PER_MAILBOX0_CONTEXT Register Field Descriptions ...........................................
PRCM_RM_PER_MMC0_CONTEXT Register Field Descriptions.................................................
PRCM_RM_PER_MMC1_CONTEXT Register Field Descriptions.................................................
PRCM_RM_PER_SPI0_CONTEXT Register Field Descriptions ...................................................
PRCM_RM_PER_SPI1_CONTEXT Register Field Descriptions ...................................................
PRCM_RM_PER_SPI2_CONTEXT Register Field Descriptions ...................................................
PRCM_RM_PER_SPI3_CONTEXT Register Field Descriptions ...................................................
PRCM_RM_PER_SPI4_CONTEXT Register Field Descriptions ...................................................
PRCM_RM_PER_SPINLOCK_CONTEXT Register Field Descriptions ...........................................
PRCM_RM_PER_TIMER2_CONTEXT Register Field Descriptions ...............................................
PRCM_RM_PER_TIMER3_CONTEXT Register Field Descriptions ...............................................
List of Tables
355
357
359
360
361
362
363
364
365
366
367
368
369
370
371
372
373
374
375
376
377
378
379
380
381
382
383
384
385
386
387
388
389
390
391
392
393
394
SPRUHL7I – April 2014 – Revised December 2019
Submit Documentation Feedback
Copyright © 2014–2019, Texas Instruments Incorporated
www.ti.com
6-114. PRCM_RM_PER_TIMER4_CONTEXT Register Field Descriptions ............................................... 395
6-115. PRCM_RM_PER_TIMER5_CONTEXT Register Field Descriptions ............................................... 396
6-116. PRCM_RM_PER_TIMER6_CONTEXT Register Field Descriptions ............................................... 397
6-117. PRCM_RM_PER_TIMER7_CONTEXT Register Field Descriptions ............................................... 398
6-118. PRCM_RM_PER_TIMER8_CONTEXT Register Field Descriptions ............................................... 399
6-119. PRCM_RM_PER_TIMER9_CONTEXT Register Field Descriptions ............................................... 400
6-120. PRCM_RM_PER_TIMER10_CONTEXT Register Field Descriptions ............................................. 401
6-121. PRCM_RM_PER_TIMER11_CONTEXT Register Field Descriptions ............................................. 402
6-122. PRCM_RM_PER_UART1_CONTEXT Register Field Descriptions ................................................ 403
6-123. PRCM_RM_PER_UART2_CONTEXT Register Field Descriptions ................................................ 404
6-124. PRCM_RM_PER_UART3_CONTEXT Register Field Descriptions ................................................ 405
6-125. PRCM_RM_PER_UART4_CONTEXT Register Field Descriptions ................................................ 406
6-126. PRCM_RM_PER_UART5_CONTEXT Register Field Descriptions ................................................ 407
6-127. PRCM_RM_PER_USBPHYOCP2SCP0_CONTEXT Register Field Descriptions ............................... 408
6-128. PRCM_RM_PER_USBPHYOCP2SCP1_CONTEXT Register Field Descriptions ............................... 409
6-129. PRCM_RM_PER_EMIF_CONTEXT Register Field Descriptions .................................................. 410
6-130. PRCM_RM_PER_DLL_CONTEXT Register Field Descriptions.................................................... 411
6-131. PRCM_RM_PER_DSS_CONTEXT Register Field Descriptions ................................................... 412
6-132. PRCM_RM_PER_CPGMAC0_CONTEXT Register Field Descriptions ........................................... 413
6-133. PRCM_RM_PER_OCPWP_CONTEXT Register Field Descriptions .............................................. 414
.......................................................................................
PRCM_RM_RTC_CONTEXT Register Field Descriptions ..........................................................
PRM_WKUP Registers ..................................................................................................
PRCM_RM_WKUP_RSTCTRL Register Field Descriptions ........................................................
PRCM_RM_WKUP_RSTST Register Field Descriptions............................................................
PRCM_RM_WKUP_DBGSS_CONTEXT Register Field Descriptions.............................................
PRCM_RM_WKUP_ADC0_CONTEXT Register Field Descriptions ...............................................
PRCM_RM_WKUP_L4WKUP_CONTEXT Register Field Descriptions ...........................................
PRCM_RM_WKUP_PROC_CONTEXT Register Field Descriptions ..............................................
PRCM_RM_WKUP_SYNCTIMER_CONTEXT Register Field Descriptions ......................................
PRCM_RM_WKUP_TIMER0_CONTEXT Register Field Descriptions ............................................
PRCM_RM_WKUP_TIMER1_CONTEXT Register Field Descriptions ............................................
PRCM_RM_WKUP_WDT1_CONTEXT Register Field Descriptions ..............................................
PRCM_RM_WKUP_I2C0_CONTEXT Register Field Descriptions ................................................
PRCM_RM_WKUP_UART0_CONTEXT Register Field Descriptions .............................................
PRCM_RM_WKUP_GPIO0_CONTEXT Register Field Descriptions ..............................................
PRCM_PRM_IRQ Registers ............................................................................................
PRCM_REVISION Register Field Descriptions .......................................................................
PRCM_PRM_IRQSTS_MPU Register Field Descriptions ...........................................................
PRCM_PRM_IRQEN_MPU Register Field Descriptions ............................................................
PRCM_PRM_IRQSTS_WKUP_PROC Register Field Descriptions ...............................................
PRCM_PRM_IRQEN_WKUP_PROC Register Field Descriptions .................................................
PRCM_CM_CEFUSE REGISTERS ....................................................................................
PRCM_CM_CEFUSE_CLKSTCTRL Register Field Descriptions ..................................................
PRCM_CM_CEFUSE_CLKCTRL Register Field Descriptions .....................................................
PRCM_CM_DEVICE REGISTERS .....................................................................................
PRCM_CM_CLKOUT1_CTRL Register Field Descriptions .........................................................
PRCM_CM_DLL_CTRL Register Field Descriptions ................................................................
PRCM_CM_CLKOUT2_CTRL Register Field Descriptions .........................................................
6-134. PRCM_PRM_RTC REGISTERS
414
6-135.
415
6-136.
6-137.
6-138.
6-139.
6-140.
6-141.
6-142.
6-143.
6-144.
6-145.
6-146.
6-147.
6-148.
6-149.
6-150.
6-151.
6-152.
6-153.
6-154.
6-155.
6-156.
6-157.
6-158.
6-159.
6-160.
6-161.
6-162.
SPRUHL7I – April 2014 – Revised December 2019
Submit Documentation Feedback
Copyright © 2014–2019, Texas Instruments Incorporated
List of Tables
415
417
418
419
420
421
422
423
424
425
426
427
428
429
429
430
431
433
435
437
439
440
441
442
443
445
446
79
www.ti.com
6-163. CM_DPLL Registers ...................................................................................................... 447
6-164. PRCM_CM_DPLL_DPLL_CLKSEL_TIMER1_CLK Register Field Descriptions ................................. 449
6-165. PRCM_CM_DPLL_CLKSEL_TIMER2_CLK Register Field Descriptions ......................................... 450
6-166. PRCM_CM_DPLL_CLKSEL_TIMER3_CLK Register Field Descriptions ......................................... 451
6-167. PRCM_CM_DPLL_CLKSEL_TIMER4_CLK Register Field Descriptions ......................................... 452
6-168. PRCM_CM_DPLL_CLKSEL_TIMER5_CLK Register Field Descriptions ......................................... 453
6-169. PRCM_CM_DPLL_CLKSEL_TIMER6_CLK Register Field Descriptions ......................................... 454
6-170. PRCM_CM_DPLL_CLKSEL_TIMER7_CLK Register Field Descriptions ......................................... 455
6-171. PRCM_CM_DPLL_CLKSEL_TIMER8_CLK Register Field Descriptions ......................................... 456
6-172. PRCM_CM_DPLL_CLKSEL_TIMER9_CLK Register Field Descriptions ......................................... 457
6-173. PRCM_CM_DPLL_CLKSEL_TIMER10_CLK Register Field Descriptions ........................................ 458
6-174. PRCM_CM_DPLL_CLKSEL_TIMER11_CLK Register Field Descriptions ........................................ 459
6-175. PRCM_CM_DPLL_CLKSEL_WDT1_CLK Register Field Descriptions
...........................................
460
6-176. PRCM_CM_DPLL_CLKSEL_SYNCTIMER_CLK Register Field Descriptions ................................... 461
6-177. PRCM_CM_DPLL_CLKSEL_MAC_CLK Register Field Descriptions ............................................. 462
6-178. PRCM_CM_DPLL_CLKSEL_CPTS_RFT_CLK Register Field Descriptions ..................................... 463
6-179. PRCM_CM_DPLL_CLKSEL_GFX_FCLK Register Field Descriptions ............................................ 464
6-180. PRCM_CM_DPLL_CLKSEL_GPIO0_DBCLK Register Field Descriptions ....................................... 465
6-181. PRCM_CM_CLKSEL_PRU_ICSS_OCP_CLK Register Field Descriptions....................................... 466
6-182. PRCM_CM_CLKSEL_ADC1_CLK Register Field Descriptions .................................................... 467
6-183. PRCM_CM_DPLL_CLKSEL_DLL_AGING_CLK Register Field Descriptions .................................... 468
6-184. PRCM_CM_DPLL_CLKSEL_USBPHY32KHZ_GCLK Register Field Descriptions.............................. 469
6-185. PRCM_CM_GFX REGISTERS ......................................................................................... 469
6-186. PRCM_CM_GFX_L3_CLKSTCTRL Register Field Descriptions ................................................... 470
6-187. PRCM_CM_GFX_CLKCTRL Register Field Descriptions ........................................................... 471
6-188. PRCM_CM_MPU REGISTERS ......................................................................................... 472
6-189. PRCM_CM_MPU_CLKSTCTRL Register Field Descriptions ....................................................... 473
6-190. PRCM_CM_MPU_CLKCTRL Register Field Descriptions .......................................................... 474
6-191. CM_PER Registers ....................................................................................................... 475
6-192. PRCM_CM_PER_L3_CLKSTCTRL Register Field Descriptions ................................................... 477
6-193. PRCM_CM_PER_L3_CLKCTRL Register Field Descriptions ...................................................... 478
6-194. PRCM_CM_PER_L3_INSTR_CLKCTRL Register Field Descriptions............................................. 479
6-195. PRCM_CM_PER_OCMCRAM_CLKCTRL Register Field Descriptions ........................................... 480
6-196. PRCM_CM_PER_VPFE0_CLKCTRL Register Field Descriptions................................................. 481
6-197. PRCM_CM_PER_VPFE1_CLKCTRL Register Field Descriptions................................................. 482
6-198. PRCM_CM_PER_TPCC_CLKCTRL Register Field Descriptions .................................................. 483
6-199. PRCM_CM_PER_TPTC0_CLKCTRL Register Field Descriptions................................................. 484
6-200. PRCM_CM_PER_TPTC1_CLKCTRL Register Field Descriptions................................................. 485
6-201. PRCM_CM_PER_TPTC2_CLKCTRL Register Field Descriptions................................................. 486
6-202. PRCM_CM_PER_DLL_AGING_CLKCTRL Register Field Descriptions .......................................... 487
..................................................
PRCM_CM_PER_L3S_CLKSTCTRL Register Field Descriptions .................................................
PRCM_CM_PER_GPMC_CLKCTRL Register Field Descriptions .................................................
PRCM_CM_PER_ADC1_CLKCTRL Register Field Descriptions ..................................................
PRCM_CM_PER_MCASP0_CLKCTRL Register Field Descriptions ..............................................
PRCM_CM_PER_MCASP1_CLKCTRL Register Field Descriptions ..............................................
PRCM_CM_PER_MMC2_CLKCTRL Register Field Descriptions .................................................
PRCM_CM_PER_QSPI_CLKCTRL Register Field Descriptions ...................................................
PRCM_CM_PER_USB_OTG_SS0_CLKCTRL Register Field Descriptions ......................................
6-203. PRCM_CM_PER_L4HS_CLKCTRL Register Field Descriptions
6-204.
6-205.
6-206.
6-207.
6-208.
6-209.
6-210.
6-211.
80
List of Tables
488
489
491
492
493
494
495
496
497
SPRUHL7I – April 2014 – Revised December 2019
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www.ti.com
6-212. PRCM_CM_PER_USB_OTG_SS1_CLKCTRL Register Field Descriptions ...................................... 498
6-213. PRCM_CM_PER_PRU_ICSS_CLKSTCTRL Register Field Descriptions ........................................ 499
6-214. PRCM_CM_PER_PRU_ICSS_CLKCTRL Register Field Descriptions ............................................ 500
...............................................
PRCM_CM_PER_L4LS_CLKCTRL Register Field Descriptions ...................................................
PRCM_CM_PER_DCAN0_CLKCTRL Register Field Descriptions ................................................
PRCM_CM_PER_DCAN1_CLKCTRL Register Field Descriptions ................................................
PRCM_CM_PER_PWMSS0_CLKCTRL Register Field Descriptions .............................................
PRCM_CM_PER_PWMSS1_CLKCTRL Register Field Descriptions .............................................
PRCM_CM_PER_PWMSS2_CLKCTRL Register Field Descriptions .............................................
PRCM_CM_PER_PWMSS3_CLKCTRL Register Field Descriptions .............................................
PRCM_CM_PER_PWMSS4_CLKCTRL Register Field Descriptions .............................................
PRCM_CM_PER_PWMSS5_CLKCTRL Register Field Descriptions .............................................
PRCM_CM_PER_ELM_CLKCTRL Register Field Descriptions....................................................
PRCM_CM_PER_GPIO1_CLKCTRL Register Field Descriptions .................................................
PRCM_CM_PER_GPIO2_CLKCTRL Register Field Descriptions .................................................
PRCM_CM_PER_GPIO3_CLKCTRL Register Field Descriptions .................................................
PRCM_CM_PER_GPIO4_CLKCTRL Register Field Descriptions .................................................
PRCM_CM_PER_GPIO5_CLKCTRL Register Field Descriptions .................................................
PRCM_CM_PER_HDQ1W_CLKCTRL Register Field Descriptions ...............................................
PRCM_CM_PER_I2C1_CLKCTRL Register Field Descriptions ...................................................
PRCM_CM_PER_I2C2_CLKCTRL Register Field Descriptions ...................................................
PRCM_CM_PER_MAILBOX0_CLKCTRL Register Field Descriptions ............................................
PRCM_CM_PER_MMC0_CLKCTRL Register Field Descriptions .................................................
PRCM_CM_PER_MMC1_CLKCTRL Register Field Descriptions .................................................
PRCM_CM_PER_SPI0_CLKCTRL Register Field Descriptions ...................................................
PRCM_CM_PER_SPI1_CLKCTRL Register Field Descriptions ...................................................
PRCM_CM_PER_SPI2_CLKCTRL Register Field Descriptions ...................................................
PRCM_CM_PER_SPI3_CLKCTRL Register Field Descriptions ...................................................
PRCM_CM_PER_SPI4_CLKCTRL Register Field Descriptions ...................................................
PRCM_CM_PER_SPINLOCK_CLKCTRL Register Field Descriptions ...........................................
PRCM_CM_PER_TIMER2_CLKCTRL Register Field Descriptions ...............................................
PRCM_CM_PER_TIMER3_CLKCTRL Register Field Descriptions ...............................................
PRCM_CM_PER_TIMER4_CLKCTRL Register Field Descriptions ...............................................
PRCM_CM_PER_TIMER5_CLKCTRL Register Field Descriptions ...............................................
PRCM_CM_PER_TIMER6_CLKCTRL Register Field Descriptions ...............................................
PRCM_CM_PER_TIMER7_CLKCTRL Register Field Descriptions ...............................................
PRCM_CM_PER_TIMER8_CLKCTRL Register Field Descriptions ...............................................
PRCM_CM_PER_TIMER9_CLKCTRL Register Field Descriptions ...............................................
PRCM_CM_PER_TIMER10_CLKCTRL Register Field Descriptions ..............................................
PRCM_CM_PER_TIMER11_CLKCTRL Register Field Descriptions ..............................................
PRCM_CM_PER_UART1_CLKCTRL Register Field Descriptions ................................................
PRCM_CM_PER_UART2_CLKCTRL Register Field Descriptions ................................................
PRCM_CM_PER_UART3_CLKCTRL Register Field Descriptions ................................................
PRCM_CM_PER_UART4_CLKCTRL Register Field Descriptions ................................................
PRCM_CM_PER_UART5_CLKCTRL Register Field Descriptions ................................................
PRCM_CM_PER_USBPHYOCP2SCP0_CLKCTRL Register Field Descriptions ................................
PRCM_CM_PER_USBPHYOCP2SCP1_CLKCTRL Register Field Descriptions ................................
PRCM_CM_PER_EMIF_CLKSTCTRL Register Field Descriptions ...............................................
6-215. PRCM_CM_PER_L4LS_CLKSTCTRL Register Field Descriptions
6-216.
6-217.
6-218.
6-219.
6-220.
6-221.
6-222.
6-223.
6-224.
6-225.
6-226.
6-227.
6-228.
6-229.
6-230.
6-231.
6-232.
6-233.
6-234.
6-235.
6-236.
6-237.
6-238.
6-239.
6-240.
6-241.
6-242.
6-243.
6-244.
6-245.
6-246.
6-247.
6-248.
6-249.
6-250.
6-251.
6-252.
6-253.
6-254.
6-255.
6-256.
6-257.
6-258.
6-259.
6-260.
SPRUHL7I – April 2014 – Revised December 2019
Submit Documentation Feedback
Copyright © 2014–2019, Texas Instruments Incorporated
List of Tables
501
504
505
506
507
508
509
510
511
512
513
514
515
516
517
518
519
520
521
522
523
524
525
526
527
528
529
530
531
532
533
534
535
536
537
538
539
540
541
542
543
544
545
546
547
548
81
www.ti.com
6-261. PRCM_CM_PER_EMIF_CLKCTRL Register Field Descriptions ................................................... 549
6-262. PRCM_CM_PER_DLL_CLKCTRL Register Field Descriptions .................................................... 550
6-263. PRCM_CM_PER_LCDC_CLKSTCTRL Register Field Descriptions .............................................. 551
6-264. PRCM_CM_PER_DSS_CLKSTCTRL Register Field Descriptions ................................................ 552
6-265. PRCM_CM_PER_DSS_CLKCTRL Register Field Descriptions.................................................... 553
6-266. PRCM_CM_PER_CPSW_CLKSTCTRL Register Field Descriptions.............................................. 554
6-267. PRCM_CM_PER_CPGMAC0_CLKCTRL Register Field Descriptions ............................................ 556
6-268. PRCM_CM_PER_OCPWP_L3_CLKSTCTRL Register Field Descriptions ....................................... 557
6-269. PRCM_CM_PER_OCPWP_CLKCTRL Register Field Descriptions ............................................... 558
6-270. PRCM_CM_RTC REGISTERS ......................................................................................... 558
6-271. PRCM_CM_RTC_CLKSTCTRL Register Field Descriptions ....................................................... 559
6-272. PRCM_CM_RTC_CLKCTRL Register Field Descriptions ........................................................... 560
6-273. CM_WKUP Registers .................................................................................................... 560
..................................................
PRCM_CM_WKUP_DBGSS_CLKCTRL Register Field Descriptions .............................................
PRCM_CM_L3S_TSC_CLKSTCTRL Register Field Descriptions .................................................
PRCM_CM_L3S_ADC0_CLKSTCTRL Register Field Descriptions ...............................................
PRCM_CM_WKUP_ADC_TSC_CLKCTRL Register Field Descriptions ..........................................
PRCM_CM_WKUP_ADC0_CLKCTRL Register Field Descriptions ...............................................
PRCM_CM_L4_WKUP_AON_CLKSTCTRL Register Field Descriptions .........................................
PRCM_CM_WKUP_L4WKUP_CLKCTRL Register Field Descriptions ...........................................
PRCM_CM_WKUP_M3_CLKCTRL Register Field Descriptions ...................................................
PRCM_CM_WKUP_PROC_CLKCTRL Register Field Descriptions ...............................................
PRCM_CM_WKUP_SYNCTIMER_CLKCTRL Register Field Descriptions .......................................
PRCM_CM_WKUP_CLKDIV32K_CLKCTRL Register Field Descriptions ........................................
PRCM_CM_WKUP_USBPHY0_CLKCTRL Register Field Descriptions ..........................................
PRCM_CM_WKUP_USBPHY1_CLKCTRL Register Field Descriptions ..........................................
PRCM_CM_WKUP_CLKSTCTRL Register Field Descriptions .....................................................
PRCM_CM_WKUP_TIMER0_CLKCTRL Register Field Descriptions .............................................
PRCM_CM_WKUP_TIMER1_CLKCTRL Register Field Descriptions .............................................
PRCM_CM_WKUP_WDT0_CLKCTRL Register Field Descriptions ...............................................
PRCM_CM_WKUP_WDT1_CLKCTRL Register Field Descriptions ...............................................
PRCM_CM_WKUP_I2C0_CLKCTRL Register Field Descriptions .................................................
PRCM_CM_WKUP_UART0_CLKCTRL Register Field Descriptions ..............................................
PRCM_CM_WKUP_CTRL_CLKCTRL Register Field Descriptions................................................
PRCM_CM_WKUP_GPIO0_CLKCTRL Register Field Descriptions ..............................................
PRCM_CM_CLKMODE_DPLL_CORE Register Field Descriptions ...............................................
PRCM_CM_IDLEST_DPLL_CORE Register Field Descriptions ...................................................
PRCM_CM_CLKSEL_DPLL_CORE Register Field Descriptions ..................................................
PRCM_CM_DIV_M4_DPLL_CORE Register Field Descriptions ...................................................
PRCM_CM_DIV_M5_DPLL_CORE Register Field Descriptions ...................................................
PRCM_CM_DIV_M6_DPLL_CORE Register Field Descriptions ...................................................
PRCM_CM_SSC_DELTAMSTEP_DPLL_CORE Register Field Descriptions ...................................
PRCM_CM_SSC_MODFREQDIV_DPLL_CORE Register Field Descriptions ...................................
PRCM_CM_CLKMODE_DPLL_MPU Register Field Descriptions .................................................
PRCM_CM_IDLEST_DPLL_MPU Register Field Descriptions .....................................................
PRCM_CM_CLKSEL_DPLL_MPU Register Field Descriptions ....................................................
PRCM_CM_DIV_M2_DPLL_MPU Register Field Descriptions ....................................................
PRCM_CM_SSC_DELTAMSTEP_DPLL_MPU Register Field Descriptions .....................................
6-274. PRCM_CM_L3_AON_CLKSTCTRL Register Field Descriptions
6-275.
6-276.
6-277.
6-278.
6-279.
6-280.
6-281.
6-282.
6-283.
6-284.
6-285.
6-286.
6-287.
6-288.
6-289.
6-290.
6-291.
6-292.
6-293.
6-294.
6-295.
6-296.
6-297.
6-298.
6-299.
6-300.
6-301.
6-302.
6-303.
6-304.
6-305.
6-306.
6-307.
6-308.
6-309.
82
List of Tables
563
564
566
567
568
569
570
571
572
573
574
575
576
577
578
580
581
582
583
584
585
586
587
588
590
591
592
593
594
595
596
597
599
600
601
602
SPRUHL7I – April 2014 – Revised December 2019
Submit Documentation Feedback
Copyright © 2014–2019, Texas Instruments Incorporated
www.ti.com
6-310. PRCM_CM_SSC_MODFREQDIV_DPLL_MPU Register Field Descriptions ..................................... 603
6-311. PRCM_CM_CLKMODE_DPLL_DDR Register Field Descriptions ................................................. 604
6-312. PRCM_CM_IDLEST_DPLL_DDR Register Field Descriptions ..................................................... 606
6-313. PRCM_CM_CLKSEL_DPLL_DDR Register Field Descriptions .................................................... 607
6-314. PRCM_CM_DIV_M2_DPLL_DDR Register Field Descriptions ..................................................... 608
6-315. PRCM_CM_DIV_M4_DPLL_DDR Register Field Descriptions ..................................................... 609
6-316. PRCM_CM_SSC_DELTAMSTEP_DPLL_DDR Register Field Descriptions
.....................................
610
6-317. PRCM_CM_SSC_MODFREQDIV_DPLL_DDR Register Field Descriptions ..................................... 611
6-318. PRCM_CM_CLKMODE_DPLL_PER Register Field Descriptions ................................................. 612
6-319. PRCM_CM_IDLEST_DPLL_PER Register Field Descriptions ..................................................... 613
6-320. PRCM_CM_CLKSEL_DPLL_PER Register Field Descriptions .................................................... 614
6-321. PRCM_CM_DIV_M2_DPLL_PER Register Field Descriptions ..................................................... 615
6-322. PRCM_CM_CLKSEL2_DPLL_PER Register Field Descriptions ................................................... 616
6-323. PRCM_CM_SSC_DELTAMSTEP_DPLL_PER Register Field Descriptions ...................................... 617
6-324. PRCM_CM_SSC_MODFREQDIV_DPLL_PER Register Field Descriptions
.....................................
618
6-325. PRCM_CM_CLKDCOLDO_DPLL_PER Register Field Descriptions .............................................. 619
6-326. PRCM_CM_CLKMODE_DPLL_DISP Register Field Descriptions................................................. 620
6-327. PRCM_CM_IDLEST_DPLL_DISP Register Field Descriptions
....................................................
622
6-328. PRCM_CM_CLKSEL_DPLL_DISP Register Field Descriptions.................................................... 623
6-329. PRCM_CM_DIV_M2_DPLL_DISP Register Field Descriptions .................................................... 624
6-330. PRCM_CM_SSC_DELTAMSTEP_DPLL_DISP Register Field Descriptions ..................................... 625
6-331. PRCM_CM_SSC_MODFREQDIV_DPLL_DISP Register Field Descriptions ..................................... 626
6-332. PRCM_CM_CLKMODE_DPLL_EXTDEV Register Field Descriptions ............................................ 627
6-333. PRCM_CM_IDLEST_DPLL_EXTDEV Register Field Descriptions ................................................ 628
6-334. PRCM_CM_CLKSEL_DPLL_EXTDEV Register Field Descriptions ............................................... 629
6-335. PRCM_CM_DIV_M2_DPLL_EXTDEV Register Field Descriptions ................................................ 630
6-336. PRCM_CM_CLKSEL2_DPLL_EXTDEV Register Field Descriptions.............................................. 631
6-337. PRCM_CM_SSC_DELTAMSTEP_DPLL_EXTDEV Register Field Descriptions
................................
632
6-338. PRCM_CM_SSC_MODFREQDIV_DPLL_EXTDEV Register Field Descriptions ................................ 633
...........................................
...........................................
Pad Control Register Field Descriptions ...............................................................................
Mode Selection ............................................................................................................
Pull Selection ..............................................................................................................
Interconnect Priority Values .............................................................................................
Available Sources for Timer[5–7] and eCAP[0–2] Events ...........................................................
Selection Mux Values ....................................................................................................
Selection Mux Values ....................................................................................................
DDR Slew Rate Control Settings .......................................................................................
DDR Impedance Control Settings ......................................................................................
Address Control Mapping for LPDDR2/DDR3 ........................................................................
CONTROL_MODULE Registers ........................................................................................
CTRL_REVISION Register Field Descriptions ........................................................................
CTRL_HWINFO Register Field Descriptions ..........................................................................
CTRL_SYSCONFIG Register Field Descriptions .....................................................................
CTRL_STS Register Field Descriptions ...............................................................................
CTRL_MPU_L2 Register Field Descriptions ..........................................................................
CTRL_CORE_SLDO Register Field Descriptions ....................................................................
CTRL_MPU_SLDO Register Field Descriptions ......................................................................
6-339. PRCM_CM_SHADOW_FREQ_CONFIG1 Register Field Descriptions
634
6-340. PRCM_CM_SHADOW_FREQ_CONFIG2 Register Field Descriptions
636
7-1.
7-2.
7-3.
7-4.
7-5.
7-6.
7-7.
7-8.
7-9.
7-10.
7-11.
7-12.
7-13.
7-14.
7-15.
7-16.
7-17.
7-18.
SPRUHL7I – April 2014 – Revised December 2019
Submit Documentation Feedback
Copyright © 2014–2019, Texas Instruments Incorporated
List of Tables
638
639
640
641
645
646
647
648
648
648
649
656
657
658
659
661
662
663
83
www.ti.com
7-19.
CTRL_CLK32KDIVRATIO Register Field Descriptions .............................................................. 664
7-20.
CTRL_BANDGAP Register Field Descriptions
7-21.
CTRL_BANDGAP_TRIM Register Field Descriptions ............................................................... 666
7-22.
CTRL_PLL_CLKINPULOW Register Field Descriptions
7-23.
7-24.
7-25.
7-26.
7-27.
7-28.
7-29.
7-30.
7-31.
7-32.
7-33.
7-34.
7-35.
7-36.
7-37.
7-38.
7-39.
7-40.
7-41.
7-42.
7-43.
7-44.
7-45.
7-46.
7-47.
7-48.
7-49.
7-50.
7-51.
7-52.
7-53.
7-54.
7-55.
7-56.
7-57.
7-58.
7-59.
7-60.
7-61.
7-62.
7-63.
7-64.
7-65.
7-66.
7-67.
84
.......................................................................
............................................................
CTRL_MOSC Register Field Descriptions ............................................................................
CTRL_DEEPSLEEP Register Field Descriptions.....................................................................
CTRL_DPLL_PWR_SW_STS Register Field Descriptions .........................................................
CTRL_DISPLAY_PLL_SEL Register Field Descriptions ............................................................
CTRL_DEVICE_ID Register Field Descriptions ......................................................................
CTRL_DEV_FEATURE Register Field Descriptions .................................................................
CTRL_INIT_PRIORITY_0 Register Field Descriptions ..............................................................
CTRL_INIT_PRIORITY_1 Register Field Descriptions ..............................................................
CTRL_DEV_ATTR Register Field Descriptions ......................................................................
CTRL_TPTC_CFG Register Field Descriptions ......................................................................
CTRL_USB_CTRL0 Register Field Descriptions .....................................................................
CTRL_USB_STS0 Register Field Descriptions .......................................................................
CTRL_USB_CTRL1 Register Field Descriptions .....................................................................
CTRL_USB_STS1 Register Field Descriptions .......................................................................
CTRL_MAC_ID0_LO Register Field Descriptions ....................................................................
CTRL_MAC_ID0_HI Register Field Descriptions .....................................................................
CTRL_MAC_ID1_LO Register Field Descriptions ....................................................................
CTRL_MAC_ID1_HI Register Field Descriptions .....................................................................
CTRL_DCAN_RAMINIT Register Field Descriptions ................................................................
CTRL_USB_CTRL2 Register Field Descriptions .....................................................................
CTRL_GMII_SEL Register Field Descriptions ........................................................................
CTRL_MPUSS Register Field Descriptions ...........................................................................
CTRL_TIMER_CASCADE Register Field Descriptions ..............................................................
CTRL_PWMSS Register Field Descriptions ..........................................................................
CTRL_MREQPRIO_0 Register Field Descriptions ...................................................................
CTRL_MREQPRIO_1 Register Field Descriptions ...................................................................
CTRL_VDD_MPU_OPP_050 Register Field Descriptions ..........................................................
CTRL_VDD_MPU_OPP_100 Register Field Descriptions ..........................................................
CTRL_VDD_MPU_OPP_120 Register Field Descriptions ..........................................................
CTRL_VDD_MPU_OPP_TURBO Register Field Descriptions .....................................................
CTRL_VDD_MPU_OPP_NITRO Register Field Descriptions ......................................................
CTRL_VDD_CORE_OPP_050 Register Field Descriptions ........................................................
CTRL_VDD_CORE_OPP_100 Register Field Descriptions ........................................................
CTRL_USB_VID_PID Register Field Descriptions ...................................................................
CTRL_CONF_GPMC_AD0 Register Field Descriptions.............................................................
CTRL_CONF_GPMC_AD1 Register Field Descriptions.............................................................
CTRL_CONF_GPMC_AD2 Register Field Descriptions.............................................................
CTRL_CONF_GPMC_AD3 Register Field Descriptions.............................................................
CTRL_CONF_GPMC_AD4 Register Field Descriptions.............................................................
CTRL_CONF_GPMC_AD5 Register Field Descriptions.............................................................
CTRL_CONF_GPMC_AD6 Register Field Descriptions.............................................................
CTRL_CONF_GPMC_AD7 Register Field Descriptions.............................................................
CTRL_CONF_GPMC_AD8 Register Field Descriptions.............................................................
CTRL_CONF_GPMC_AD9 Register Field Descriptions.............................................................
CTRL_CONF_GPMC_AD10 Register Field Descriptions ...........................................................
List of Tables
665
667
668
669
670
671
672
673
674
675
676
677
678
680
681
683
684
685
686
687
688
689
691
692
693
694
695
696
697
698
699
700
701
702
703
704
705
707
709
711
713
715
717
719
721
723
725
SPRUHL7I – April 2014 – Revised December 2019
Submit Documentation Feedback
Copyright © 2014–2019, Texas Instruments Incorporated
www.ti.com
7-68.
CTRL_CONF_GPMC_AD11 Register Field Descriptions ........................................................... 727
7-69.
CTRL_CONF_GPMC_AD12 Register Field Descriptions ........................................................... 729
7-70.
CTRL_CONF_GPMC_AD13 Register Field Descriptions ........................................................... 731
7-71.
CTRL_CONF_GPMC_AD14 Register Field Descriptions ........................................................... 733
7-72.
CTRL_CONF_GPMC_AD15 Register Field Descriptions ........................................................... 735
7-73.
CTRL_CONF_GPMC_A0 Register Field Descriptions............................................................... 737
7-74.
CTRL_CONF_GPMC_A1 Register Field Descriptions............................................................... 739
7-75.
CTRL_CONF_GPMC_A2 Register Field Descriptions............................................................... 741
7-76.
CTRL_CONF_GPMC_A3 Register Field Descriptions............................................................... 743
7-77.
CTRL_CONF_GPMC_A4 Register Field Descriptions............................................................... 745
7-78.
CTRL_CONF_GPMC_A5 Register Field Descriptions............................................................... 747
7-79.
CTRL_CONF_GPMC_A6 Register Field Descriptions............................................................... 749
7-80.
CTRL_CONF_GPMC_A7 Register Field Descriptions............................................................... 751
7-81.
CTRL_CONF_GPMC_A8 Register Field Descriptions............................................................... 753
7-82.
CTRL_CONF_GPMC_A9 Register Field Descriptions............................................................... 755
7-83.
CTRL_CONF_GPMC_A10 Register Field Descriptions ............................................................. 757
7-84.
CTRL_CONF_GPMC_A11 Register Field Descriptions ............................................................. 759
7-85.
CTRL_CONF_GPMC_WAIT0 Register Field Descriptions.......................................................... 761
7-86.
CTRL_CONF_GPMC_WPN Register Field Descriptions............................................................ 763
7-87.
CTRL_CONF_GPMC_BE1N Register Field Descriptions ........................................................... 765
7-88.
CTRL_CONF_GPMC_CSN0 Register Field Descriptions ........................................................... 767
7-89.
CTRL_CONF_GPMC_CSN1 Register Field Descriptions ........................................................... 769
7-90.
CTRL_CONF_GPMC_CSN2 Register Field Descriptions ........................................................... 771
7-91.
CTRL_CONF_GPMC_CSN3 Register Field Descriptions ........................................................... 773
7-92.
CTRL_CONF_GPMC_CLK Register Field Descriptions............................................................. 775
7-93.
CTRL_CONF_GPMC_ADVN_ALE Register Field Descriptions .................................................... 777
7-94.
CTRL_CONF_GPMC_OEN_REN Register Field Descriptions ..................................................... 779
7-95.
CTRL_CONF_GPMC_WEN Register Field Descriptions............................................................ 781
7-96.
CTRL_CONF_GPMC_BE0N_CLE Register Field Descriptions .................................................... 783
7-97.
CTRL_CONF_DSS_DATA0 Register Field Descriptions ............................................................ 785
7-98.
CTRL_CONF_DSS_DATA1 Register Field Descriptions ............................................................ 787
7-99.
CTRL_CONF_DSS_DATA2 Register Field Descriptions ............................................................ 789
7-100. CTRL_CONF_DSS_DATA3 Register Field Descriptions ............................................................ 791
7-101. CTRL_CONF_DSS_DATA4 Register Field Descriptions ............................................................ 793
7-102. CTRL_CONF_DSS_DATA5 Register Field Descriptions ............................................................ 795
7-103. CTRL_CONF_DSS_DATA6 Register Field Descriptions ............................................................ 797
7-104. CTRL_CONF_DSS_DATA7 Register Field Descriptions ............................................................ 799
7-105. CTRL_CONF_DSS_DATA8 Register Field Descriptions ............................................................ 801
7-106. CTRL_CONF_DSS_DATA9 Register Field Descriptions ............................................................ 803
7-107. CTRL_CONF_DSS_DATA10 Register Field Descriptions .......................................................... 805
7-108. CTRL_CONF_DSS_DATA11 Register Field Descriptions .......................................................... 807
7-109. CTRL_CONF_DSS_DATA12 Register Field Descriptions .......................................................... 809
7-110. CTRL_CONF_DSS_DATA13 Register Field Descriptions .......................................................... 811
7-111. CTRL_CONF_DSS_DATA14 Register Field Descriptions .......................................................... 813
7-112. CTRL_CONF_DSS_DATA15 Register Field Descriptions .......................................................... 815
7-113. CTRL_CONF_DSS_VSYNC Register Field Descriptions ........................................................... 817
7-114. CTRL_CONF_DSS_HSYNC Register Field Descriptions ........................................................... 819
7-115. CTRL_CONF_DSS_PCLK Register Field Descriptions ............................................................. 821
7-116. CTRL_CONF_DSS_AC_BIAS_EN Register Field Descriptions .................................................... 823
SPRUHL7I – April 2014 – Revised December 2019
Submit Documentation Feedback
Copyright © 2014–2019, Texas Instruments Incorporated
List of Tables
85
www.ti.com
7-117. CTRL_CONF_MMC0_DAT3 Register Field Descriptions ........................................................... 825
7-118. CTRL_CONF_MMC0_DAT2 Register Field Descriptions ........................................................... 827
7-119. CTRL_CONF_MMC0_DAT1 Register Field Descriptions ........................................................... 829
7-120. CTRL_CONF_MMC0_DAT0 Register Field Descriptions ........................................................... 831
7-121. CTRL_CONF_MMC0_CLK Register Field Descriptions ............................................................. 833
7-122. CTRL_CONF_MMC0_CMD Register Field Descriptions ............................................................ 835
7-123. CTRL_CONF_MII1_COL Register Field Descriptions ............................................................... 837
7-124. CTRL_CONF_MII1_CRS Register Field Descriptions ............................................................... 839
7-125. CTRL_CONF_MII1_RXERR Register Field Descriptions ........................................................... 841
7-126. CTRL_CONF_MII1_TXEN Register Field Descriptions
.............................................................
843
7-127. CTRL_CONF_MII1_RXDV Register Field Descriptions ............................................................. 845
7-128. CTRL_CONF_MII1_TXD3 Register Field Descriptions .............................................................. 847
7-129. CTRL_CONF_MII1_TXD2 Register Field Descriptions .............................................................. 849
7-130. CTRL_CONF_MII1_TXD1 Register Field Descriptions .............................................................. 851
7-131. CTRL_CONF_MII1_TXD0 Register Field Descriptions .............................................................. 853
7-132. CTRL_CONF_MII1_TXCLK Register Field Descriptions ............................................................ 855
7-133. CTRL_CONF_MII1_RXCLK Register Field Descriptions ............................................................ 857
859
7-135. CTRL_CONF_MII1_RXD2 Register Field Descriptions
861
7-136.
863
7-137.
7-138.
7-139.
7-140.
7-141.
7-142.
7-143.
7-144.
7-145.
7-146.
7-147.
7-148.
7-149.
7-150.
7-151.
7-152.
7-153.
7-154.
7-155.
7-156.
7-157.
7-158.
7-159.
7-160.
7-161.
7-162.
7-163.
7-164.
7-165.
86
.............................................................
.............................................................
CTRL_CONF_MII1_RXD1 Register Field Descriptions .............................................................
CTRL_CONF_MII1_RXD0 Register Field Descriptions .............................................................
CTRL_CONF_RMII1_REFCLK Register Field Descriptions ........................................................
CTRL_CONF_MDIO_DATA Register Field Descriptions ............................................................
CTRL_CONF_MDIO_CLK Register Field Descriptions ..............................................................
CTRL_CONF_SPI0_SCLK Register Field Descriptions .............................................................
CTRL_CONF_SPI0_D0 Register Field Descriptions .................................................................
CTRL_CONF_SPI0_D1 Register Field Descriptions .................................................................
CTRL_CONF_SPI0_CS0 Register Field Descriptions ...............................................................
CTRL_CONF_SPI0_CS1 Register Field Descriptions ...............................................................
CTRL_CONF_ECAP0_IN_PWM0_OUT Register Field Descriptions..............................................
CTRL_CONF_UART0_CTSN Register Field Descriptions ..........................................................
CTRL_CONF_UART0_RTSN Register Field Descriptions ..........................................................
CTRL_CONF_UART0_RXD Register Field Descriptions ...........................................................
CTRL_CONF_UART0_TXD Register Field Descriptions ............................................................
CTRL_CONF_UART1_CTSN Register Field Descriptions ..........................................................
CTRL_CONF_UART1_RTSN Register Field Descriptions ..........................................................
CTRL_CONF_UART1_RXD Register Field Descriptions ...........................................................
CTRL_CONF_UART1_TXD Register Field Descriptions ............................................................
CTRL_CONF_I2C0_SDA Register Field Descriptions ...............................................................
CTRL_CONF_I2C0_SCL Register Field Descriptions ...............................................................
CTRL_CONF_MCASP0_ACLKX Register Field Descriptions ......................................................
CTRL_CONF_MCASP0_FSX Register Field Descriptions..........................................................
CTRL_CONF_MCASP0_AXR0 Register Field Descriptions ........................................................
CTRL_CONF_MCASP0_AHCLKR Register Field Descriptions ....................................................
CTRL_CONF_MCASP0_ACLKR Register Field Descriptions ......................................................
CTRL_CONF_MCASP0_FSR Register Field Descriptions .........................................................
CTRL_CONF_MCASP0_AXR1 Register Field Descriptions ........................................................
CTRL_CONF_MCASP0_AHCLKX Register Field Descriptions ....................................................
CTRL_CONF_CAM0_HD Register Field Descriptions...............................................................
7-134. CTRL_CONF_MII1_RXD3 Register Field Descriptions
List of Tables
865
867
869
871
873
875
877
879
881
882
883
885
887
889
891
893
895
897
899
900
901
903
905
907
909
911
913
915
917
SPRUHL7I – April 2014 – Revised December 2019
Submit Documentation Feedback
Copyright © 2014–2019, Texas Instruments Incorporated
www.ti.com
7-166. CTRL_CONF_CAM0_VD Register Field Descriptions ............................................................... 919
7-167. CTRL_CONF_CAM0_FIELD Register Field Descriptions ........................................................... 921
7-168. CTRL_CONF_CAM0_WEN Register Field Descriptions ............................................................ 923
........................................................... 925
CTRL_CONF_CAM0_DATA8 Register Field Descriptions .......................................................... 927
CTRL_CONF_CAM0_DATA9 Register Field Descriptions .......................................................... 929
CTRL_CONF_CAM1_DATA9 Register Field Descriptions .......................................................... 931
CTRL_CONF_CAM1_DATA8 Register Field Descriptions .......................................................... 933
CTRL_CONF_CAM1_HD Register Field Descriptions............................................................... 935
CTRL_CONF_CAM1_VD Register Field Descriptions ............................................................... 937
CTRL_CONF_CAM1_PCLK Register Field Descriptions ........................................................... 939
CTRL_CONF_CAM1_FIELD Register Field Descriptions ........................................................... 941
CTRL_CONF_CAM1_WEN Register Field Descriptions ............................................................ 943
CTRL_CONF_CAM1_DATA0 Register Field Descriptions .......................................................... 945
CTRL_CONF_CAM1_DATA1 Register Field Descriptions .......................................................... 947
CTRL_CONF_CAM1_DATA2 Register Field Descriptions .......................................................... 949
CTRL_CONF_CAM1_DATA3 Register Field Descriptions .......................................................... 951
CTRL_CONF_CAM1_DATA4 Register Field Descriptions .......................................................... 953
CTRL_CONF_CAM1_DATA5 Register Field Descriptions .......................................................... 955
CTRL_CONF_CAM1_DATA6 Register Field Descriptions .......................................................... 957
CTRL_CONF_CAM1_DATA7 Register Field Descriptions .......................................................... 959
CTRL_CONF_CAM0_DATA0 Register Field Descriptions .......................................................... 961
CTRL_CONF_CAM0_DATA1 Register Field Descriptions .......................................................... 963
CTRL_CONF_CAM0_DATA2 Register Field Descriptions .......................................................... 965
CTRL_CONF_CAM0_DATA3 Register Field Descriptions .......................................................... 967
CTRL_CONF_CAM0_DATA4 Register Field Descriptions .......................................................... 969
CTRL_CONF_CAM0_DATA5 Register Field Descriptions .......................................................... 971
CTRL_CONF_CAM0_DATA6 Register Field Descriptions .......................................................... 973
CTRL_CONF_CAM0_DATA7 Register Field Descriptions .......................................................... 975
CTRL_CONF_UART3_RXD Register Field Descriptions ........................................................... 977
CTRL_CONF_UART3_TXD Register Field Descriptions ............................................................ 979
CTRL_CONF_UART3_CTSN Register Field Descriptions .......................................................... 981
CTRL_CONF_UART3_RTSN Register Field Descriptions .......................................................... 983
CTRL_CONF_GPIO5_8 Register Field Descriptions ................................................................ 985
CTRL_CONF_GPIO5_9 Register Field Descriptions ................................................................ 987
CTRL_CONF_GPIO5_10 Register Field Descriptions ............................................................... 989
CTRL_CONF_GPIO5_11 Register Field Descriptions ............................................................... 991
CTRL_CONF_GPIO5_12 Register Field Descriptions ............................................................... 993
CTRL_CONF_GPIO5_13 Register Field Descriptions ............................................................... 995
CTRL_CONF_SPI4_SCLK Register Field Descriptions ............................................................. 997
CTRL_CONF_SPI4_D0 Register Field Descriptions ................................................................. 999
CTRL_CONF_SPI4_D1 Register Field Descriptions ............................................................... 1001
CTRL_CONF_SPI4_CS0 Register Field Descriptions ............................................................. 1003
CTRL_CONF_SPI2_SCLK Register Field Descriptions............................................................ 1005
CTRL_CONF_SPI2_D0 Register Field Descriptions ............................................................... 1007
CTRL_CONF_SPI2_D1 Register Field Descriptions ............................................................... 1009
CTRL_CONF_SPI2_CS0 Register Field Descriptions ............................................................. 1011
CTRL_CONF_XDMA_EVT_INTR0 Register Field Descriptions .................................................. 1013
CTRL_CONF_XDMA_EVT_INTR1 Register Field Descriptions .................................................. 1014
7-169. CTRL_CONF_CAM0_PCLK Register Field Descriptions
7-170.
7-171.
7-172.
7-173.
7-174.
7-175.
7-176.
7-177.
7-178.
7-179.
7-180.
7-181.
7-182.
7-183.
7-184.
7-185.
7-186.
7-187.
7-188.
7-189.
7-190.
7-191.
7-192.
7-193.
7-194.
7-195.
7-196.
7-197.
7-198.
7-199.
7-200.
7-201.
7-202.
7-203.
7-204.
7-205.
7-206.
7-207.
7-208.
7-209.
7-210.
7-211.
7-212.
7-213.
7-214.
SPRUHL7I – April 2014 – Revised December 2019
Submit Documentation Feedback
Copyright © 2014–2019, Texas Instruments Incorporated
List of Tables
87
www.ti.com
7-215. CTRL_CONF_CLKREQ Register Field Descriptions ............................................................... 1015
7-216. CTRL_CONF_NRESETIN_OUT Register Field Descriptions ..................................................... 1016
7-217. CTRL_CONF_NNMI Register Field Descriptions ................................................................... 1017
7-218. CTRL_CONF_TMS Register Field Descriptions .................................................................... 1018
7-219. CTRL_CONF_TDI Register Field Descriptions...................................................................... 1019
7-220. CTRL_CONF_TDO Register Field Descriptions .................................................................... 1020
7-221. CTRL_CONF_TCK Register Field Descriptions..................................................................... 1021
7-222. CTRL_CONF_NTRST Register Field Descriptions ................................................................. 1022
1023
7-224.
1024
7-225.
7-226.
7-227.
7-228.
7-229.
7-230.
7-231.
7-232.
7-233.
7-234.
7-235.
7-236.
7-237.
7-238.
7-239.
7-240.
7-241.
7-242.
7-243.
7-244.
7-245.
7-246.
7-247.
7-248.
7-249.
7-250.
7-251.
7-252.
7-253.
7-254.
7-255.
7-256.
7-257.
7-258.
7-259.
7-260.
7-261.
7-262.
7-263.
88
..................................................................
CTRL_CONF_EMU1 Register Field Descriptions ..................................................................
CTRL_CONF_OSC1_IN Register Field Descriptions ..............................................................
CTRL_CONF_OSC1_OUT Register Field Descriptions ...........................................................
CTRL_CONF_RTC_PORZ Register Field Descriptions ...........................................................
CTRL_CONF_EXT_WAKEUP0 Register Field Descriptions ......................................................
CTRL_CONF_PMIC_POWER_EN0 Register Field Descriptions .................................................
CTRL_CONF_USB0_DRVVBUS Register Field Descriptions ....................................................
CTRL_CONF_USB1_DRVVBUS Register Field Descriptions ....................................................
CTRL_CQDETECT_STS Register Field Descriptions .............................................................
CTRL_DDR_IO Register Field Descriptions .........................................................................
CTRL_CQDETECT_STS2 Register Field Descriptions ............................................................
CTRL_VTP Register Field Descriptions ..............................................................................
CTRL_VREF Register Field Descriptions ............................................................................
CTRL_TPCC_EVT_MUX_0_3 Register Field Descriptions .......................................................
CTRL_TPCC_EVT_MUX_4_7 Register Field Descriptions .......................................................
CTRL_TPCC_EVT_MUX_8_11 Register Field Descriptions ......................................................
CTRL_TPCC_EVT_MUX_12_15 Register Field Descriptions ....................................................
CTRL_TPCC_EVT_MUX_16_19 Register Field Descriptions ....................................................
CTRL_TPCC_EVT_MUX_20_23 Register Field Descriptions ....................................................
CTRL_TPCC_EVT_MUX_24_27 Register Field Descriptions ....................................................
CTRL_TPCC_EVT_MUX_28_31 Register Field Descriptions ....................................................
CTRL_TPCC_EVT_MUX_32_35 Register Field Descriptions ....................................................
CTRL_TPCC_EVT_MUX_36_39 Register Field Descriptions ....................................................
CTRL_TPCC_EVT_MUX_40_43 Register Field Descriptions ....................................................
CTRL_TPCC_EVT_MUX_44_47 Register Field Descriptions ....................................................
CTRL_TPCC_EVT_MUX_48_51 Register Field Descriptions ....................................................
CTRL_TPCC_EVT_MUX_52_55 Register Field Descriptions ....................................................
CTRL_TPCC_EVT_MUX_56_59 Register Field Descriptions ....................................................
CTRL_TPCC_EVT_MUX_60_63 Register Field Descriptions ....................................................
CTRL_TIMER_EVT_CAPT Register Field Descriptions ...........................................................
CTRL_ECAP_EVT_CAPT Register Field Descriptions ............................................................
CTRL_ADC0_EVT_CAPT Register Field Descriptions ............................................................
CTRL_ADC1_EVT_CAPT Register Field Descriptions ............................................................
CTRL_RESET_ISO Register Field Descriptions ....................................................................
CTRL_DPLL_PWR_SW Register Field Descriptions ...............................................................
CTRL_DDR_CKE Register Field Descriptions ......................................................................
CTRL_VSLDO Register Field Descriptions ..........................................................................
CTRL_WAKEPROC_TXEV_EOI Register Field Descriptions .....................................................
CTRL_IPC_MSG_REG0 Register Field Descriptions ..............................................................
CTRL_IPC_MSG_REG1 Register Field Descriptions ..............................................................
7-223. CTRL_CONF_EMU0 Register Field Descriptions
List of Tables
1025
1026
1027
1028
1029
1030
1032
1034
1036
1037
1038
1039
1040
1041
1042
1043
1044
1045
1046
1047
1048
1049
1050
1051
1052
1053
1054
1055
1056
1057
1058
1059
1060
1061
1063
1064
1065
1066
1067
SPRUHL7I – April 2014 – Revised December 2019
Submit Documentation Feedback
Copyright © 2014–2019, Texas Instruments Incorporated
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7-264. CTRL_IPC_MSG_REG2 Register Field Descriptions .............................................................. 1068
7-265. CTRL_IPC_MSG_REG3 Register Field Descriptions .............................................................. 1069
7-266. CTRL_IPC_MSG_REG4 Register Field Descriptions .............................................................. 1070
7-267. CTRL_IPC_MSG_REG5 Register Field Descriptions .............................................................. 1071
7-268. CTRL_IPC_MSG_REG6 Register Field Descriptions .............................................................. 1072
7-269. CTRL_IPC_MSG_REG7 Register Field Descriptions .............................................................. 1073
7-270. CTRL_IPC_MSG_REG8 Register Field Descriptions .............................................................. 1074
7-271. CTRL_IPC_MSG_REG9 Register Field Descriptions .............................................................. 1075
7-272. CTRL_IPC_MSG_REG10 Register Field Descriptions............................................................. 1076
7-273. CTRL_IPC_MSG_REG11 Register Field Descriptions............................................................. 1077
7-274. CTRL_IPC_MSG_REG12 Register Field Descriptions............................................................. 1078
7-275. CTRL_IPC_MSG_REG13 Register Field Descriptions............................................................. 1079
7-276. CTRL_IPC_MSG_REG14 Register Field Descriptions............................................................. 1080
7-277. CTRL_IPC_INTR Register Field Descriptions ....................................................................... 1081
7-278. CTRL_DPLL_PWR_SW_CTRL2 Register Field Descriptions ..................................................... 1082
......................................................
CTRL_RESET_MISC Register Field Descriptions ..................................................................
CTRL_DDR_ADDRCTRL_IOCTRL Register Field Descriptions ..................................................
CTRL_DDR_ADDRCTRL_WD0_IOCTRL Register Field Descriptions ..........................................
CTRL_DDR_ADDRCTRL_WD1_IOCTRL Register Field Descriptions ..........................................
CTRL_DDR_DATA0_IOCTRL Register Field Descriptions ........................................................
CTRL_DDR_DATA1_IOCTRL Register Field Descriptions ........................................................
CTRL_DDR_DATA2_IOCTRL Register Field Descriptions ........................................................
CTRL_DDR_DATA3_IOCTRL Register Field Descriptions ........................................................
CTRL_EMIF_SDRAM_CONFIG_EXT Register Field Descriptions ...............................................
CTRL_EMIF_SDRAM_STS_EXT Register Field Descriptions ....................................................
CTRL_DISPPLL_CLKCTRL Register Field Descriptions ..........................................................
CTRL_DISPPLL_TEN Register Field Descriptions .................................................................
CTRL_DISPPLL_TENIV Register Field Descriptions...............................................................
CTRL_DISPPLL_M2NDIV Register Field Descriptions ............................................................
CTRL_DISPPLL_MN2DIV Register Field Descriptions ............................................................
CTRL_DISPPLL_FRACDIV Register Field Descriptions ...........................................................
CTRL_DISPPLL_BWCTRL Register Field Descriptions ...........................................................
CTRL_DISPPLL_FRACCTRL Register Field Descriptions ........................................................
CTRL_DISPPLL_STS Register Field Descriptions .................................................................
CTRL_DISPPLL_M3DIV Register Field Descriptions ..............................................................
CTRL_DISPPLL_RAMPCTRL Register Field Descriptions ........................................................
ARM Cortex-A9 Interrupts ..............................................................................................
Timer and eCAP Event Capture .......................................................................................
Unsupported GPMC Features .........................................................................................
GPMC Connectivity Attributes .........................................................................................
GPMC Clock Signals ...................................................................................................
GPMC Signal List .......................................................................................................
GPMC Pin Multiplexing Options .......................................................................................
GPMC Clocks ............................................................................................................
GPMC_CONFIG1_i Configuration ....................................................................................
GPMC Local Power Management Features .........................................................................
GPMC Interrupt Events .................................................................................................
Idle Cycle Insertion Configuration .....................................................................................
7-279. CTRL_DPLL_PWR_SW_STS2 Register Field Descriptions
1083
7-280.
1084
7-281.
7-282.
7-283.
7-284.
7-285.
7-286.
7-287.
7-288.
7-289.
7-290.
7-291.
7-292.
7-293.
7-294.
7-295.
7-296.
7-297.
7-298.
7-299.
7-300.
8-1.
8-2.
9-1.
9-2.
9-3.
9-4.
9-5.
9-6.
9-7.
9-8.
9-9.
9-10.
SPRUHL7I – April 2014 – Revised December 2019
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Copyright © 2014–2019, Texas Instruments Incorporated
List of Tables
1085
1086
1087
1088
1090
1092
1094
1096
1098
1099
1101
1102
1103
1104
1105
1106
1107
1108
1109
1110
1112
1116
1121
1122
1122
1123
1124
1129
1129
1129
1130
1141
89
www.ti.com
9-11.
Chip-Select Configuration for NAND Interfacing .................................................................... 1170
9-12.
ECC Enable Settings ................................................................................................... 1179
9-13.
Flattened BCH Codeword Mapping (512 Bytes + 104 Bits) ....................................................... 1184
9-14.
Aligned Message Byte Mapping in 8-bit NAND ..................................................................... 1184
9-15.
Aligned Message Byte Mapping in 16-bit NAND .................................................................... 1185
9-16.
Aligned Nibble Mapping of Message in 8-bit NAND ................................................................ 1185
9-17.
Misaligned Nibble Mapping of Message in 8-bit NAND ............................................................ 1185
9-18.
Aligned Nibble Mapping of Message in 16-bit NAND
9-19.
Misaligned Nibble Mapping of Message in 16-bit NAND (1 Unused Nibble) .................................... 1186
9-20.
Misaligned Nibble Mapping of Message in 16-bit NAND (2 Unused Nibble) .................................... 1186
9-21.
Misaligned Nibble Mapping of Message in 16-bit NAND (3 Unused Nibble) .................................... 1186
9-22.
Prefetch Mode Configuration .......................................................................................... 1197
9-23.
Write-Posting Mode Configuration .................................................................................... 1199
9-24.
GPMC Configuration in NOR Mode................................................................................... 1205
9-25.
GPMC Configuration in NAND Mode ................................................................................. 1205
9-26.
Reset GPMC ............................................................................................................. 1205
9-27.
NOR Memory Type
9-28.
NOR Chip-Select Configuration ....................................................................................... 1206
9-29.
NOR Timings Configuration ............................................................................................ 1206
9-30.
WAIT Pin Configuration
9-31.
Enable Chip-Select ...................................................................................................... 1207
9-32.
NAND Memory Type .................................................................................................... 1207
9-33.
NAND Chip-Select Configuration...................................................................................... 1207
9-34.
Asynchronous Read and Write Operations .......................................................................... 1207
9-35.
ECC Engine .............................................................................................................. 1207
9-36.
Prefetch and Write-Posting Engine ................................................................................... 1209
9-37.
WAIT Pin Configuration
9-38.
Enable Chip-Select ...................................................................................................... 1209
9-39.
Mode Parameters Check List Table .................................................................................. 1210
9-40.
Access Type Parameters Check List Table
9-41.
Timing Parameters ...................................................................................................... 1212
9-42.
GPMC Signals ........................................................................................................... 1214
9-43.
Useful Timing Parameters on the Memory Side .................................................................... 1216
9-44.
Calculating GPMC Timing Parameters ............................................................................... 1217
9-45.
AC Characteristics for Asynchronous Read Access ................................................................ 1218
9-46.
GPMC Timing Parameters for Asynchronous Read Access
9-47.
9-48.
9-49.
9-50.
9-51.
9-52.
9-53.
9-54.
9-55.
9-56.
9-57.
9-58.
9-59.
90
..............................................................
.....................................................................................................
................................................................................................
................................................................................................
.........................................................................
......................................................
AC Characteristics for Asynchronous Single Write (Memory Side)...............................................
GPMC Timing Parameters for Asynchronous Single Write ........................................................
NAND Interface Bus Operations Summary ..........................................................................
NOR Interface Bus Operations Summary ............................................................................
GPMC Registers ........................................................................................................
GPMC_REVISION Register Field Descriptions .....................................................................
GPMC_SYSCONFIG Register Field Descriptions ..................................................................
GPMC_SYSSTATUS Register Field Descriptions ..................................................................
GPMC_IRQSTATUS Register Field Descriptions...................................................................
GPMC_IRQENABLE Register Field Descriptions...................................................................
GPMC_TIMEOUT_CONTROL Register Field Descriptions .......................................................
GPMC_ERR_ADDRESS Register Field Descriptions ..............................................................
GPMC_ERR_TYPE Register Field Descriptions ....................................................................
List of Tables
1185
1206
1206
1209
1210
1219
1220
1221
1222
1222
1225
1228
1229
1230
1231
1232
1233
1234
1235
SPRUHL7I – April 2014 – Revised December 2019
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Copyright © 2014–2019, Texas Instruments Incorporated
www.ti.com
9-60.
GPMC_CONFIG Register Field Descriptions........................................................................ 1236
9-61.
GPMC_STATUS Register Field Descriptions
9-62.
GPMC_CONFIG1_i Register Field Descriptions .................................................................... 1238
9-63.
GPMC_CONFIG2_i Register Field Descriptions .................................................................... 1241
9-64.
GPMC_CONFIG3_i Register Field Descriptions .................................................................... 1242
9-65.
GPMC_CONFIG4_i Register Field Descriptions .................................................................... 1244
9-66.
GPMC_CONFIG5_i Register Field Descriptions .................................................................... 1246
9-67.
GPMC_CONFIG6_i Register Field Descriptions .................................................................... 1247
9-68.
GPMC_CONFIG7_i Register Field Descriptions .................................................................... 1249
9-69.
GPMC_NAND_COMMAND_i Register Field Descriptions......................................................... 1250
9-70.
GPMC_NAND_ADDRESS_i Register Field Descriptions .......................................................... 1251
9-71.
GPMC_NAND_DATA_i Register Field Descriptions................................................................ 1252
9-72.
GPMC_PREFETCH_CONFIG1 Register Field Descriptions ...................................................... 1253
9-73.
GPMC_PREFETCH_CONFIG2 Register Field Descriptions ...................................................... 1255
9-74.
GPMC_PREFETCH_CONTROL Register Field Descriptions ..................................................... 1256
9-75.
GPMC_PREFETCH_STATUS Register Field Descriptions ....................................................... 1257
9-76.
GPMC_ECC_CONFIG Register Field Descriptions ................................................................ 1258
9-77.
GPMC_ECC_CONTROL Register Field Descriptions .............................................................. 1259
9-78.
GPMC_ECC_SIZE_CONFIG Register Field Descriptions ......................................................... 1260
9-79.
GPMC_ECC1_RESULT Register Field Descriptions ............................................................... 1262
9-80.
GPMC_ECC2_RESULT Register Field Descriptions ............................................................... 1264
9-81.
GPMC_ECC3_RESULT Register Field Descriptions ............................................................... 1266
9-82.
GPMC_ECC4_RESULT Register Field Descriptions ............................................................... 1268
9-83.
GPMC_ECC5_RESULT Register Field Descriptions ............................................................... 1270
9-84.
GPMC_ECC6_RESULT Register Field Descriptions ............................................................... 1272
9-85.
GPMC_ECC7_RESULT Register Field Descriptions ............................................................... 1274
9-86.
GPMC_ECC8_RESULT Register Field Descriptions ............................................................... 1276
9-87.
GPMC_ECC9_RESULT Register Field Descriptions ............................................................... 1278
9-88.
GPMC_BCH_RESULT0_0 Register Field Descriptions ............................................................ 1280
9-89.
GPMC_BCH_RESULT1_0 Register Field Descriptions ............................................................ 1281
9-90.
GPMC_BCH_RESULT2_0 Register Field Descriptions ............................................................ 1282
9-91.
GPMC_BCH_RESULT3_0 Register Field Descriptions ............................................................ 1283
9-92.
GPMC_BCH_RESULT0_1 Register Field Descriptions ............................................................ 1284
9-93.
GPMC_BCH_RESULT1_1 Register Field Descriptions ............................................................ 1285
9-94.
GPMC_BCH_RESULT2_1 Register Field Descriptions ............................................................ 1286
9-95.
GPMC_BCH_RESULT3_1 Register Field Descriptions ............................................................ 1287
9-96.
GPMC_BCH_RESULT0_2 Register Field Descriptions ............................................................ 1288
9-97.
GPMC_BCH_RESULT1_2 Register Field Descriptions ............................................................ 1289
9-98.
GPMC_BCH_RESULT2_2 Register Field Descriptions ............................................................ 1290
9-99.
GPMC_BCH_RESULT3_2 Register Field Descriptions ............................................................ 1291
.......................................................................
1237
9-100. GPMC_BCH_RESULT0_3 Register Field Descriptions ............................................................ 1292
9-101. GPMC_BCH_RESULT1_3 Register Field Descriptions ............................................................ 1293
9-102. GPMC_BCH_RESULT2_3 Register Field Descriptions ............................................................ 1294
9-103. GPMC_BCH_RESULT3_3 Register Field Descriptions ............................................................ 1295
9-104. GPMC_BCH_RESULT0_4 Register Field Descriptions ............................................................ 1296
9-105. GPMC_BCH_RESULT1_4 Register Field Descriptions ............................................................ 1297
9-106. GPMC_BCH_RESULT2_4 Register Field Descriptions ............................................................ 1298
9-107. GPMC_BCH_RESULT3_4 Register Field Descriptions ............................................................ 1299
9-108. GPMC_BCH_RESULT0_5 Register Field Descriptions ............................................................ 1300
SPRUHL7I – April 2014 – Revised December 2019
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Copyright © 2014–2019, Texas Instruments Incorporated
List of Tables
91
www.ti.com
9-109. GPMC_BCH_RESULT1_5 Register Field Descriptions ............................................................ 1301
9-110. GPMC_BCH_RESULT2_5 Register Field Descriptions ............................................................ 1302
9-111. GPMC_BCH_RESULT3_5 Register Field Descriptions ............................................................ 1303
9-112. GPMC_BCH_RESULT0_6 Register Field Descriptions ............................................................ 1304
9-113. GPMC_BCH_RESULT1_6 Register Field Descriptions ............................................................ 1305
9-114. GPMC_BCH_RESULT2_6 Register Field Descriptions ............................................................ 1306
9-115. GPMC_BCH_RESULT3_6 Register Field Descriptions ............................................................ 1307
9-116. GPMC_BCH_SWDATA Register Field Descriptions ............................................................... 1308
9-117. GPMC_BCH_RESULT4_0 Register Field Descriptions ............................................................ 1309
9-118. GPMC_BCH_RESULT5_0 Register Field Descriptions ............................................................ 1310
9-119. GPMC_BCH_RESULT6_0 Register Field Descriptions ............................................................ 1311
9-120. GPMC_BCH_RESULT4_1 Register Field Descriptions ............................................................ 1312
9-121. GPMC_BCH_RESULT5_1 Register Field Descriptions ............................................................ 1313
9-122. GPMC_BCH_RESULT6_1 Register Field Descriptions ............................................................ 1314
9-123. GPMC_BCH_RESULT4_2 Register Field Descriptions ............................................................ 1315
9-124. GPMC_BCH_RESULT5_2 Register Field Descriptions ............................................................ 1316
9-125. GPMC_BCH_RESULT6_2 Register Field Descriptions ............................................................ 1317
9-126. GPMC_BCH_RESULT4_3 Register Field Descriptions ............................................................ 1318
9-127. GPMC_BCH_RESULT5_3 Register Field Descriptions ............................................................ 1319
9-128. GPMC_BCH_RESULT6_3 Register Field Descriptions ............................................................ 1320
9-129. GPMC_BCH_RESULT4_4 Register Field Descriptions ............................................................ 1321
9-130. GPMC_BCH_RESULT5_4 Register Field Descriptions ............................................................ 1322
9-131. GPMC_BCH_RESULT6_4 Register Field Descriptions ............................................................ 1323
9-132. GPMC_BCH_RESULT4_5 Register Field Descriptions ............................................................ 1324
9-133. GPMC_BCH_RESULT5_5 Register Field Descriptions ............................................................ 1325
9-134. GPMC_BCH_RESULT6_5 Register Field Descriptions ............................................................ 1326
9-135. GPMC_BCH_RESULT4_6 Register Field Descriptions ............................................................ 1327
9-136. GPMC_BCH_RESULT5_6 Register Field Descriptions ............................................................ 1328
9-137. GPMC_BCH_RESULT6_6 Register Field Descriptions ............................................................ 1329
9-138. GPMC_BCH_RESULT0_7 Register Field Descriptions ............................................................ 1330
9-139. GPMC_BCH_RESULT1_7 Register Field Descriptions ............................................................ 1331
9-140. GPMC_BCH_RESULT2_7 Register Field Descriptions ............................................................ 1332
9-141. GPMC_BCH_RESULT3_7 Register Field Descriptions ............................................................ 1333
9-142. GPMC_BCH_RESULT4_7 Register Field Descriptions ............................................................ 1334
9-143. GPMC_BCH_RESULT5_7 Register Field Descriptions ............................................................ 1335
9-144. GPMC_BCH_RESULT6_7 Register Field Descriptions ............................................................ 1336
9-145. EMIF Connectivity Attributes ........................................................................................... 1340
9-146. EMIF Clock Signals ..................................................................................................... 1340
9-147. EMIF Pin List ............................................................................................................. 1341
9-148. FIFO Allocation .......................................................................................................... 1343
9-149. Load Value For The MR2 Register During DDR3 SDRAM Initialization ......................................... 1350
9-150. Load Value For The MR1 Register During DDR3 SDRAM Initialization ......................................... 1350
9-151. Load Value For The MR0 Register During DDR3 SDRAM Initialization ......................................... 1351
9-152. 64-Byte Linear Read Starting at Address 0x0 (All DDR) ........................................................... 1353
1353
9-154. 64-Byte Linear Read Starting at Address 0x8 (LPDDR2-S4)
1353
9-155.
1353
9-156.
9-157.
92
.....................................................
.....................................................
64-Byte Linear Read Starting at Address 0x10 (All DDR) .........................................................
64-Byte Linear Read Starting at Address 0x18 (All DDR) .........................................................
Turnaround Time ........................................................................................................
9-153. 64-Byte Linear Read Starting at Address 0x8 (LPDDR2-S2)
List of Tables
1353
1354
SPRUHL7I – April 2014 – Revised December 2019
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9-158. IBANK, RSIZE and PAGESIZE Fields Information ................................................................. 1354
9-159. OCP Address to LPDDR2/DDR3 Address Mapping for REG_IBANK_POS=0 and REG_EBANK_POS=0
1355
9-160. OCP Address to LPDDR2/DDR3 Address Mapping for REG_IBANK_POS=1 and REG_EBANK_POS=0
1356
9-161. OCP Address to LPDDR2/DDR3 Address Mapping for REG_IBANK_POS=2 and REG_EBANK_POS=0
1356
9-162. OCP Address to LPDDR2/DDR3 Address Mapping for REG_IBANK_POS=3 and REG_EBANK_POS=0
1356
9-163. OCP Address to LPDDR2/DDR3 Address Mapping for REG_IBANK_POS=0 and REG_EBANK_POS=1
1357
9-164. OCP Address to LPDDR2/DDR3 Address Mapping for REG_IBANK_POS=1 and REG_EBANK_POS =
1 ........................................................................................................................... 1357
9-165. OCP Address to LPDDR2/DDR3 Address Mapping for REG_IBANK_POS=2 and REG_EBANK_POS =
1 ........................................................................................................................... 1358
9-166. OCP Address to LPDDR2/DDR3 Address Mapping for REG_IBANK_POS=3 and REG_EBANK_POS=1
1358
9-167. Performance Counter Filter Configuration ........................................................................... 1361
9-168. EMIF Registers .......................................................................................................... 1362
9-169. EMIF4D_MOD_ID_REV Register Field Descriptions ............................................................... 1367
9-170. EMIF4D_STS Register Field Descriptions ........................................................................... 1368
..........................................................
EMIF4D_SDRAM_CONFIG_2 Register Field Descriptions .......................................................
EMIF4D_SDRAM_REFRESH_CTRL Register Field Descriptions................................................
EMIF4D_SDRAM_REFRESH_CTRL_SHADOW Register Field Descriptions ..................................
EMIF4D_SDRAM_TIMING_1 Register Field Descriptions.........................................................
EMIF4D_SDRAM_TIMING_1_SHADOW Register Field Descriptions ...........................................
EMIF4D_SDRAM_TIMING_2 Register Field Descriptions.........................................................
EMIF4D_SDRAM_TIMING_2_SHADOW Register Field Descriptions ...........................................
EMIF4D_SDRAM_TIMING_3 Register Field Descriptions.........................................................
EMIF4D_SDRAM_TIMING_3_SHADOW Register Field Descriptions ...........................................
EMIF4D_LPDDR2_NVM_TIMING Register Field Descriptions ...................................................
EMIF4D_LPDDR2_NVM_TIMING_SHADOW Register Field Descriptions .....................................
EMIF4D_POWER_MANAGEMENT_CTRL Register Field Descriptions .........................................
EMIF4D_POWER_MANAGEMENT_CTRL_SHADOW Register Field Descriptions ...........................
EMIF4D_LPDDR2_MODE_REG_DATA Register Field Descriptions ............................................
EMIF4D_LPDDR2_MODE_REG_CONFIG Register Field Descriptions .........................................
EMIF4D_OCP_CONFIG Register Field Descriptions ..............................................................
EMIF4D_OCP_CONFIG_VALUE_1 Register Field Descriptions .................................................
EMIF4D_OCP_CONFIG_VALUE_2 Register Field Descriptions .................................................
EMIF4D_IODFT_TEST_LOGIC_GLOBAL_CTRL Register Field Descriptions .................................
EMIF4D_IODFT_TEST_LOGIC_CTRL_MISR_RESULT Register Field Descriptions .........................
EMIF4D_IODFT_TEST_LOGIC_ADDR_MISR_RESULT Register Field Descriptions ........................
EMIF4D_IODFT_TEST_LOGIC_DATA_MISR_RESULT_1 Register Field Descriptions ......................
EMIF4D_IODFT_TEST_LOGIC_DATA_MISR_RESULT_2 Register Field Descriptions ......................
EMIF4D_IODFT_TEST_LOGIC_DATA_MISR_RESULT_3 Register Field Descriptions ......................
EMIF4D_PERFORMANCE_CTR_1 Register Field Descriptions .................................................
EMIF4D_PERFORMANCE_CTR_2 Register Field Descriptions .................................................
EMIF4D_PERFORMANCE_CTR_CONFIG Register Field Descriptions ........................................
EMIF4D_PERFORMANCE_CTR_MASTER_REGION_SELECT Register Field Descriptions ...............
EMIF4D_PERFORMANCE_CTR_TIME Register Field Descriptions ............................................
EMIF4D_MISC_REG Register Field Descriptions ..................................................................
EMIF4D_DLL_CALIB_CTRL Register Field Descriptions .........................................................
EMIF4D_DLL_CALIB_CTRL_SHADOW Register Field Descriptions ............................................
EMIF4D_END_OF_INTR Register Field Descriptions .............................................................
9-171. EMIF4D_SDRAM_CONFIG Register Field Descriptions
1369
9-172.
1371
9-173.
9-174.
9-175.
9-176.
9-177.
9-178.
9-179.
9-180.
9-181.
9-182.
9-183.
9-184.
9-185.
9-186.
9-187.
9-188.
9-189.
9-190.
9-191.
9-192.
9-193.
9-194.
9-195.
9-196.
9-197.
9-198.
9-199.
9-200.
9-201.
9-202.
9-203.
9-204.
SPRUHL7I – April 2014 – Revised December 2019
Submit Documentation Feedback
Copyright © 2014–2019, Texas Instruments Incorporated
List of Tables
1372
1373
1374
1375
1376
1377
1378
1379
1380
1381
1382
1384
1385
1386
1387
1388
1389
1390
1392
1393
1394
1395
1396
1397
1398
1399
1400
1401
1402
1403
1404
1405
93
www.ti.com
1406
9-206.
1407
9-207.
9-208.
9-209.
9-210.
9-211.
9-212.
9-213.
9-214.
9-215.
9-216.
9-217.
9-218.
9-219.
9-220.
9-221.
9-222.
9-223.
9-224.
9-225.
9-226.
9-227.
9-228.
9-229.
9-230.
9-231.
9-232.
9-233.
9-234.
9-235.
9-236.
9-237.
9-238.
9-239.
9-240.
9-241.
9-242.
9-243.
9-244.
9-245.
9-246.
9-247.
9-248.
9-249.
9-250.
9-251.
9-252.
9-253.
94
.......................................
EMIF4D_LOW_LAT_OCP_INTR_RAW_STS Register Field Descriptions ......................................
EMIF4D_SYSTEM_OCP_INTR_STS Register Field Descriptions ...............................................
EMIF4D_LOW_LAT_OCP_INTR_STS Register Field Descriptions ..............................................
EMIF4D_SYSTEM_OCP_INTR_EN_SET Register Field Descriptions ..........................................
EMIF4D_LOW_LAT_OCP_INTR_EN_SET Register Field Descriptions ........................................
EMIF4D_SYSTEM_OCP_INTR_EN_CLR Register Field Descriptions ..........................................
EMIF4D_LOW_LAT_OCP_INTR_EN_CLR Register Field Descriptions ........................................
EMIF4D_SDRAM_OUTPUT_IMPEDANCE_CALIBRATION_CONFIG Register Field Descriptions .........
EMIF4D_TEMPERATURE_ALERT_CONFIG Register Field Descriptions ......................................
EMIF4D_OCP_ERROR_LOG Register Field Descriptions ........................................................
EMIF4D_READ_WRITE_LEVELING_RAMP_WINDOW Register Field Descriptions .........................
EMIF4D_READ_WRITE_LEVELING_RAMP_CTRL Register Field Descriptions ..............................
EMIF4D_READ_WRITE_LEVELING_CTRL Register Field Descriptions .......................................
EMIF4D_DDR_PHY_CTRL_1 Register Field Descriptions ........................................................
EMIF4D_DDR_PHY_CTRL_1_SHADOW Register Field Descriptions ..........................................
EMIF4D_PRIORITY_TO_CLASS_OF_SERVICE_MAPPING Register Field Descriptions ...................
EMIF4D_CONNECTION_ID_TO_CLASS_OF_SERVICE_1_MAPPING Register Field Descriptions .......
EMIF4D_CONNECTION_ID_TO_CLASS_OF_SERVICE_2_MAPPING Register Field Descriptions .......
EMIF4D_ECC_CTRL_REG Register Field Descriptions ...........................................................
EMIF4D_ECC_ADDR_RANGE_1 Register Field Descriptions ...................................................
EMIF4D_ECC_ADDR_RANGE_2 Register Field Descriptions ...................................................
EMIF4D_READ_WRITE_EXECUTION_THR Register Field Descriptions ......................................
EMIF4D_COS_CONFIG Register Field Descriptions ..............................................................
EMIF4D_1B_ECC_ERR_CNT Register Field Descriptions .......................................................
EMIF4D_1B_ECC_ERR_THRSH Register Field Descriptions ....................................................
EMIF4D_1B_ECC_ERR_DIST_1 Register Field Descriptions ....................................................
EMIF4D_1B_ECC_ERR_ADDR_LOG Register Field Descriptions ..............................................
EMIF4D_2B_ECC_ERR_ADDR_LOG Register Field Descriptions ..............................................
EMIF4D_PHY_STS_1 Register Field Descriptions .................................................................
EMIF4D_PHY_STS_2 Register Field Descriptions .................................................................
EMIF4D_PHY_STS_3 Register Field Descriptions .................................................................
EMIF4D_PHY_STS_4 Register Field Descriptions .................................................................
EMIF4D_PHY_STS_5 Register Field Descriptions .................................................................
EMIF4D_PHY_STS_6 Register Field Descriptions .................................................................
EMIF4D_PHY_STS_7 Register Field Descriptions .................................................................
EMIF4D_PHY_STS_8 Register Field Descriptions .................................................................
EMIF4D_PHY_STS_9 Register Field Descriptions .................................................................
EMIF4D_PHY_STS_10 Register Field Descriptions ...............................................................
EMIF4D_PHY_STS_11 Register Field Descriptions ...............................................................
EMIF4D_PHY_STS_12 Register Field Descriptions ...............................................................
EMIF4D_PHY_STS_13 Register Field Descriptions ...............................................................
EMIF4D_PHY_STS_14 Register Field Descriptions ...............................................................
EMIF4D_PHY_STS_15 Register Field Descriptions ...............................................................
EMIF4D_PHY_STS_16 Register Field Descriptions ...............................................................
EMIF4D_PHY_STS_17 Register Field Descriptions ...............................................................
EMIF4D_PHY_STS_18 Register Field Descriptions ...............................................................
EMIF4D_PHY_STS_19 Register Field Descriptions ...............................................................
EMIF4D_PHY_STS_20 Register Field Descriptions ...............................................................
9-205. EMIF4D_SYSTEM_OCP_INTR_RAW_STS Register Field Descriptions
List of Tables
1408
1409
1410
1411
1412
1413
1414
1415
1416
1417
1418
1419
1420
1422
1424
1425
1426
1427
1428
1429
1430
1431
1432
1433
1434
1435
1436
1437
1438
1439
1440
1441
1442
1443
1444
1445
1446
1447
1448
1449
1450
1451
1452
1453
1454
1455
1456
SPRUHL7I – April 2014 – Revised December 2019
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Copyright © 2014–2019, Texas Instruments Incorporated
www.ti.com
...............................................................
EMIF4D_PHY_STS_22 Register Field Descriptions ...............................................................
EMIF4D_PHY_STS_23 Register Field Descriptions ...............................................................
EMIF4D_PHY_STS_24 Register Field Descriptions ...............................................................
EMIF4D_PHY_STS_25 Register Field Descriptions ...............................................................
EMIF4D_PHY_STS_26 Register Field Descriptions ...............................................................
EMIF4D_PHY_STS_27 Register Field Descriptions ...............................................................
EMIF4D_PHY_STS_28 Register Field Descriptions ...............................................................
EMIF4D_EXT_PHY_CTRL_1 Register Field Descriptions ........................................................
EMIF4D_EXT_PHY_CTRL_1_SHADOW Register Field Descriptions ...........................................
EMIF4D_EXT_PHY_CTRL_2 Register Field Descriptions ........................................................
EMIF4D_EXT_PHY_CTRL_2_SHADOW Register Field Descriptions ...........................................
EMIF4D_EXT_PHY_CTRL_3 Register Field Descriptions ........................................................
EMIF4D_EXT_PHY_CTRL_3_SHADOW Register Field Descriptions ...........................................
EMIF4D_EXT_PHY_CTRL_4 Register Field Descriptions ........................................................
EMIF4D_EXT_PHY_CTRL_4_SHADOW Register Field Descriptions ...........................................
EMIF4D_EXT_PHY_CTRL_5 Register Field Descriptions ........................................................
EMIF4D_EXT_PHY_CTRL_5_SHADOW Register Field Descriptions ...........................................
EMIF4D_EXT_PHY_CTRL_6 Register Field Descriptions ........................................................
EMIF4D_EXT_PHY_CTRL_6_SHADOW Register Field Descriptions ...........................................
EMIF4D_EXT_PHY_CTRL_7 Register Field Descriptions ........................................................
EMIF4D_EXT_PHY_CTRL_7_SHADOW Register Field Descriptions ...........................................
EMIF4D_EXT_PHY_CTRL_8 Register Field Descriptions ........................................................
EMIF4D_EXT_PHY_CTRL_8_SHADOW Register Field Descriptions ...........................................
EMIF4D_EXT_PHY_CTRL_9 Register Field Descriptions ........................................................
EMIF4D_EXT_PHY_CTRL_9_SHADOW Register Field Descriptions ...........................................
EMIF4D_EXT_PHY_CTRL_10 Register Field Descriptions .......................................................
EMIF4D_EXT_PHY_CTRL_10_SHADOW Register Field Descriptions .........................................
EMIF4D_EXT_PHY_CTRL_11 Register Field Descriptions .......................................................
EMIF4D_EXT_PHY_CTRL_11_SHADOW Register Field Descriptions .........................................
EMIF4D_EXT_PHY_CTRL_12 Register Field Descriptions .......................................................
EMIF4D_EXT_PHY_CTRL_12_SHADOW Register Field Descriptions .........................................
EMIF4D_EXT_PHY_CTRL_13 Register Field Descriptions .......................................................
EMIF4D_EXT_PHY_CTRL_13_SHADOW Register Field Descriptions .........................................
EMIF4D_EXT_PHY_CTRL_14 Register Field Descriptions .......................................................
EMIF4D_EXT_PHY_CTRL_14_SHADOW Register Field Descriptions .........................................
EMIF4D_EXT_PHY_CTRL_15 Register Field Descriptions .......................................................
EMIF4D_EXT_PHY_CTRL_15_SHADOW Register Field Descriptions .........................................
EMIF4D_EXT_PHY_CTRL_16 Register Field Descriptions .......................................................
EMIF4D_EXT_PHY_CTRL_16_SHADOW Register Field Descriptions .........................................
EMIF4D_EXT_PHY_CTRL_17 Register Field Descriptions .......................................................
EMIF4D_EXT_PHY_CTRL_17_SHADOW Register Field Descriptions .........................................
EMIF4D_EXT_PHY_CTRL_18 Register Field Descriptions .......................................................
EMIF4D_EXT_PHY_CTRL_18_SHADOW Register Field Descriptions .........................................
EMIF4D_EXT_PHY_CTRL_19 Register Field Descriptions .......................................................
EMIF4D_EXT_PHY_CTRL_19_SHADOW Register Field Descriptions .........................................
EMIF4D_EXT_PHY_CTRL_20 Register Field Descriptions .......................................................
EMIF4D_EXT_PHY_CTRL_20_SHADOW Register Field Descriptions .........................................
EMIF4D_EXT_PHY_CTRL_21 Register Field Descriptions .......................................................
9-254. EMIF4D_PHY_STS_21 Register Field Descriptions
1457
9-255.
1458
9-256.
9-257.
9-258.
9-259.
9-260.
9-261.
9-262.
9-263.
9-264.
9-265.
9-266.
9-267.
9-268.
9-269.
9-270.
9-271.
9-272.
9-273.
9-274.
9-275.
9-276.
9-277.
9-278.
9-279.
9-280.
9-281.
9-282.
9-283.
9-284.
9-285.
9-286.
9-287.
9-288.
9-289.
9-290.
9-291.
9-292.
9-293.
9-294.
9-295.
9-296.
9-297.
9-298.
9-299.
9-300.
9-301.
9-302.
SPRUHL7I – April 2014 – Revised December 2019
Submit Documentation Feedback
Copyright © 2014–2019, Texas Instruments Incorporated
List of Tables
1459
1460
1461
1462
1463
1464
1465
1466
1467
1468
1469
1470
1471
1472
1473
1474
1475
1476
1477
1478
1479
1480
1481
1482
1483
1484
1485
1486
1487
1488
1489
1490
1491
1492
1493
1494
1495
1496
1497
1498
1499
1500
1501
1502
1503
1504
1505
95
www.ti.com
9-303. EMIF4D_EXT_PHY_CTRL_21_SHADOW Register Field Descriptions ......................................... 1506
9-304. EMIF4D_EXT_PHY_CTRL_22 Register Field Descriptions ....................................................... 1507
9-305. EMIF4D_EXT_PHY_CTRL_22_SHADOW Register Field Descriptions ......................................... 1508
9-306. EMIF4D_EXT_PHY_CTRL_23 Register Field Descriptions ....................................................... 1509
9-307. EMIF4D_EXT_PHY_CTRL_23_SHADOW Register Field Descriptions ......................................... 1510
9-308. EMIF4D_EXT_PHY_CTRL_24 Register Field Descriptions ....................................................... 1511
9-309. EMIF4D_EXT_PHY_CTRL_24_SHADOW Register Field Descriptions ......................................... 1512
9-310. EMIF4D_EXT_PHY_CTRL_25 Register Field Descriptions ....................................................... 1513
9-311. EMIF4D_EXT_PHY_CTRL_25_SHADOW Register Field Descriptions ......................................... 1514
9-312. EMIF4D_EXT_PHY_CTRL_26 Register Field Descriptions ....................................................... 1515
9-313. EMIF4D_EXT_PHY_CTRL_26_SHADOW Register Field Descriptions ......................................... 1516
9-314. EMIF4D_EXT_PHY_CTRL_27 Register Field Descriptions ....................................................... 1517
9-315. EMIF4D_EXT_PHY_CTRL_27_SHADOW Register Field Descriptions ......................................... 1518
9-316. EMIF4D_EXT_PHY_CTRL_28 Register Field Descriptions ....................................................... 1519
9-317. EMIF4D_EXT_PHY_CTRL_28_SHADOW Register Field Descriptions ......................................... 1520
9-318. EMIF4D_EXT_PHY_CTRL_29 Register Field Descriptions ....................................................... 1521
9-319. EMIF4D_EXT_PHY_CTRL_29_SHADOW Register Field Descriptions ......................................... 1522
9-320. EMIF4D_EXT_PHY_CTRL_30 Register Field Descriptions ....................................................... 1523
9-321. EMIF4D_EXT_PHY_CTRL_30_SHADOW Register Field Descriptions ......................................... 1524
9-322. EMIF4D_EXT_PHY_CTRL_31 Register Field Descriptions ....................................................... 1525
9-323. EMIF4D_EXT_PHY_CTRL_31_SHADOW Register Field Descriptions ......................................... 1526
9-324. EMIF4D_EXT_PHY_CTRL_32 Register Field Descriptions ....................................................... 1527
9-325. EMIF4D_EXT_PHY_CTRL_32_SHADOW Register Field Descriptions ......................................... 1528
9-326. EMIF4D_EXT_PHY_CTRL_33 Register Field Descriptions ....................................................... 1529
9-327. EMIF4D_EXT_PHY_CTRL_33_SHADOW Register Field Descriptions ......................................... 1530
9-328. EMIF4D_EXT_PHY_CTRL_34 Register Field Descriptions ....................................................... 1531
9-329. EMIF4D_EXT_PHY_CTRL_34_SHADOW Register Field Descriptions ......................................... 1532
9-330. EMIF4D_EXT_PHY_CTRL_35 Register Field Descriptions ....................................................... 1533
9-331. EMIF4D_EXT_PHY_CTRL_35_SHADOW Register Field Descriptions ......................................... 1534
9-332. EMIF4D_EXT_PHY_CTRL_36 Register Field Descriptions ....................................................... 1535
9-333. EMIF4D_EXT_PHY_CTRL_36_SHADOW Register Field Descriptions ......................................... 1536
9-334. ELM Connectivity Attributes............................................................................................ 1538
9-335. ELM Clock Signals ...................................................................................................... 1538
9-336. Local Power Management Features .................................................................................. 1539
9-337. Events..................................................................................................................... 1539
9-338. ELM_LOCATION_STS_i Value Decoding Table .................................................................... 1541
9-339. ELM Processing Initialization .......................................................................................... 1542
9-340. ELM Processing Completion for Continuous Mode ................................................................. 1542
9-341. ELM Processing Completion for Page Mode ........................................................................ 1543
9-342. Use Case: Continuous Mode .......................................................................................... 1543
9-343. 16-bit NAND Sector Buffer Address Map ............................................................................ 1545
9-344. Use Case: Page Mode
.................................................................................................
1545
9-345. ELM Registers ........................................................................................................... 1547
9-346. ELM_REVISION Register Field Descriptions ........................................................................ 1552
9-347. ELM_SYSCONFIG Register Field Descriptions ..................................................................... 1553
9-348. ELM_SYSSTS Register Field Descriptions .......................................................................... 1554
9-349. ELM_IRQSTS Register Field Descriptions........................................................................... 1555
9-350. ELM_IRQEN Register Field Descriptions ............................................................................ 1556
9-351. ELM_LOCATION_CONFIG Register Field Descriptions ........................................................... 1557
96
List of Tables
SPRUHL7I – April 2014 – Revised December 2019
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Copyright © 2014–2019, Texas Instruments Incorporated
www.ti.com
9-352. ELM_PAGE_CTRL Register Field Descriptions..................................................................... 1558
9-353. ELM_SYNDROME_FRAGMENT_0_0 Register Field Descriptions .............................................. 1559
9-354. ELM_SYNDROME_FRAGMENT_1_0 Register Field Descriptions .............................................. 1560
9-355. ELM_SYNDROME_FRAGMENT_2_0 Register Field Descriptions .............................................. 1561
9-356. ELM_SYNDROME_FRAGMENT_3_0 Register Field Descriptions .............................................. 1562
9-357. ELM_SYNDROME_FRAGMENT_4_0 Register Field Descriptions .............................................. 1563
9-358. ELM_SYNDROME_FRAGMENT_5_0 Register Field Descriptions .............................................. 1564
9-359. ELM_SYNDROME_FRAGMENT_6_0 Register Field Descriptions .............................................. 1565
9-360. ELM_LOCATION_STS_0 Register Field Descriptions ............................................................. 1566
9-361. ELM_ERROR_LOCATION_0_0 Register Field Descriptions...................................................... 1567
9-362. ELM_ERROR_LOCATION_1_0 Register Field Descriptions...................................................... 1568
9-363. ELM_ERROR_LOCATION_2_0 Register Field Descriptions...................................................... 1569
9-364. ELM_ERROR_LOCATION_3_0 Register Field Descriptions...................................................... 1570
9-365. ELM_ERROR_LOCATION_4_0 Register Field Descriptions...................................................... 1571
9-366. ELM_ERROR_LOCATION_5_0 Register Field Descriptions...................................................... 1572
9-367. ELM_ERROR_LOCATION_6_0 Register Field Descriptions...................................................... 1573
9-368. ELM_ERROR_LOCATION_7_0 Register Field Descriptions...................................................... 1574
9-369. ELM_ERROR_LOCATION_8_0 Register Field Descriptions...................................................... 1575
9-370. ELM_ERROR_LOCATION_9_0 Register Field Descriptions...................................................... 1576
9-371. ELM_ERROR_LOCATION_10_0 Register Field Descriptions .................................................... 1577
9-372. ELM_ERROR_LOCATION_11_0 Register Field Descriptions .................................................... 1578
9-373. ELM_ERROR_LOCATION_12_0 Register Field Descriptions .................................................... 1579
9-374. ELM_ERROR_LOCATION_13_0 Register Field Descriptions .................................................... 1580
9-375. ELM_ERROR_LOCATION_14_0 Register Field Descriptions .................................................... 1581
9-376. ELM_ERROR_LOCATION_15_0 Register Field Descriptions .................................................... 1582
10-1.
TPCC Connectivity Attributes .......................................................................................... 1587
10-2.
TPCC Clock Signals .................................................................................................... 1587
10-3.
TPTC Connectivity Attributes .......................................................................................... 1588
10-4.
TPTC Clock Signals..................................................................................................... 1588
10-5.
EDMA3 Parameter RAM Contents .................................................................................... 1596
10-6.
EDMA3 Channel Parameter Description ............................................................................. 1598
10-7.
Channel Options Parameters (OPT) Field Descriptions
10-8.
Dummy and Null Transfer Request ................................................................................... 1603
10-9.
Parameter Updates in EDMA3CC (for Non-Null, Non-Dummy PaRAM Set) .................................... 1604
...........................................................
1599
10-10. Expected Number of Transfers for Non-Null Transfer .............................................................. 1610
10-11. EDMA Shadow Regions ................................................................................................ 1613
10-12. Shadow Region Registers
.............................................................................................
1614
10-13. Chain Event Triggers ................................................................................................... 1616
10-14. EDMA3 Transfer Completion Interrupts .............................................................................. 1617
10-15. EDMA3 Error Interrupts
................................................................................................
1617
10-16. Transfer Complete Code (TCC) to EDMA3CC Interrupt Mapping ................................................ 1617
10-17. Number of Interrupts .................................................................................................... 1618
10-18. Allowed Accesses ....................................................................................................... 1623
10-19. MPPA Registers to Region Assignment .............................................................................. 1623
10-20. Example Access Denied
...............................................................................................
1624
10-21. Example Access Allowed............................................................................................... 1625
10-22. Read/Write Command Optimization Rules........................................................................... 1629
10-23. EDMA3 Transfer Controller Configurations .......................................................................... 1631
10-24. Direct Mapped ........................................................................................................... 1651
SPRUHL7I – April 2014 – Revised December 2019
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Copyright © 2014–2019, Texas Instruments Incorporated
List of Tables
97
www.ti.com
10-25. Crossbar Mapped ....................................................................................................... 1652
10-26. EDMA3CC Registers
...................................................................................................
1654
10-27. PID Register Field Descriptions ....................................................................................... 1656
10-28. CCCFG Register Field Descriptions .................................................................................. 1657
10-29. SYSCONFIG Register Field Descriptions ............................................................................ 1659
10-30. DCHMAP_0 to DCHMAP_63 Register Field Descriptions ......................................................... 1660
10-31. QCHMAP_0 to QCHMAP_7 Register Field Descriptions .......................................................... 1661
10-32. DMAQNUM_0 to DMAQNUM_7 Register Field Descriptions ..................................................... 1662
10-33. QDMAQNUM Register Field Descriptions ........................................................................... 1667
10-34. QUEPRI Register Field Descriptions ................................................................................. 1670
10-35. EMR Register Field Descriptions ...................................................................................... 1671
10-36. EMRH Register Field Descriptions .................................................................................... 1672
10-37. EMCR Register Field Descriptions .................................................................................... 1673
10-38. EMCRH Register Field Descriptions .................................................................................. 1674
10-39. QEMR Register Field Descriptions.................................................................................... 1675
10-40. QEMCR Register Field Descriptions.................................................................................. 1676
10-41. CCERR Register Field Descriptions .................................................................................. 1677
10-42. CCERRCLR Register Field Descriptions ............................................................................. 1678
10-43. EEVAL Register Field Descriptions ................................................................................... 1679
10-44. DRAE0 Register Field Descriptions ................................................................................... 1680
10-45. DRAEH0 Register Field Descriptions ................................................................................. 1681
10-46. DRAE1 Register Field Descriptions ................................................................................... 1682
10-47. DRAEH1 Register Field Descriptions ................................................................................. 1683
10-48. DRAE2 Register Field Descriptions ................................................................................... 1684
10-49. DRAEH2 Register Field Descriptions ................................................................................. 1685
10-50. DRAE3 Register Field Descriptions ................................................................................... 1686
10-51. DRAEH3 Register Field Descriptions ................................................................................. 1687
1688
10-53. Q0E_0 to Q0E_15 Register Field Descriptions
1689
10-54.
1690
10-55.
10-56.
10-57.
10-58.
10-59.
10-60.
10-61.
10-62.
10-63.
10-64.
10-65.
10-66.
10-67.
10-68.
10-69.
10-70.
10-71.
10-72.
10-73.
98
..................................................................
.....................................................................
Q1E_0 to Q1E_15 Register Field Descriptions .....................................................................
Q2E_0 to Q2E_15 Register Field Descriptions .....................................................................
QSTAT_0 to QSTAT_2 Register Field Descriptions ................................................................
QWMTHRA Register Field Descriptions .............................................................................
CCSTAT Register Field Descriptions .................................................................................
MPFAR Register Field Descriptions ..................................................................................
MPFSR Register Field Descriptions ..................................................................................
MPFCR Register Field Descriptions ..................................................................................
MPPAG Register Field Descriptions ..................................................................................
MPPA_0 to MPPA_3 Register Field Descriptions ..................................................................
ER Register Field Descriptions ........................................................................................
ERH Register Field Descriptions ......................................................................................
ECR Register Field Descriptions ......................................................................................
ECRH Register Field Descriptions ....................................................................................
ESR Register Field Descriptions ......................................................................................
ESRH Register Field Descriptions ....................................................................................
CER Register Field Descriptions ......................................................................................
CERH Register Field Descriptions ....................................................................................
EER Register Field Descriptions ......................................................................................
EERH Register Field Descriptions ....................................................................................
10-52. QRAE_0 to QRAE_3 Register Field Descriptions
List of Tables
1691
1692
1693
1694
1696
1697
1698
1699
1701
1703
1704
1705
1706
1707
1708
1709
1710
1711
1712
SPRUHL7I – April 2014 – Revised December 2019
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Copyright © 2014–2019, Texas Instruments Incorporated
www.ti.com
10-74. EECR Register Field Descriptions .................................................................................... 1713
10-75. EECRH Register Field Descriptions .................................................................................. 1714
10-76. EESR Register Field Descriptions .................................................................................... 1715
..................................................................................
10-78. SER Register Field Descriptions ......................................................................................
10-79. SERH Register Field Descriptions ....................................................................................
10-80. SECR Register Field Descriptions ....................................................................................
10-81. SECRH Register Field Descriptions ..................................................................................
10-82. IER Register Field Descriptions .......................................................................................
10-83. IERH Register Field Descriptions .....................................................................................
10-84. IECR Register Field Descriptions .....................................................................................
10-85. IECRH Register Field Descriptions ...................................................................................
10-86. IESR Register Field Descriptions .....................................................................................
10-87. IESRH Register Field Descriptions ...................................................................................
10-88. IPR Register Field Descriptions .......................................................................................
10-89. IPRH Register Field Descriptions .....................................................................................
10-90. ICR Register Field Descriptions .......................................................................................
10-91. ICRH Register Field Descriptions .....................................................................................
10-92. IEVAL Register Field Descriptions ....................................................................................
10-93. QER Register Field Descriptions ......................................................................................
10-94. QEER Register Field Descriptions ....................................................................................
10-95. QEECR Register Field Descriptions ..................................................................................
10-96. QEESR Register Field Descriptions ..................................................................................
10-97. QSER Register Field Descriptions ....................................................................................
10-98. QSECR Register Field Descriptions ..................................................................................
10-99. EDMA3TC Registers ....................................................................................................
10-100. PID Register Field Descriptions ......................................................................................
10-101. TCCFG Register Field Descriptions .................................................................................
10-102. SYSCONFIG Register Field Descriptions ..........................................................................
10-103. TCSTAT Register Field Descriptions ................................................................................
10-104. ERRSTAT Register Field Descriptions ..............................................................................
10-105. ERREN Register Field Descriptions .................................................................................
10-106. ERRCLR Register Field Descriptions ...............................................................................
10-107. ERRDET Register Field Descriptions ...............................................................................
10-108. ERRCMD Register Field Descriptions ..............................................................................
10-109. RDRATE Register Field Descriptions ...............................................................................
10-110. SAOPT Register Field Descriptions .................................................................................
10-111. SASRC Register Field Descriptions .................................................................................
10-112. SACNT Register Field Descriptions .................................................................................
10-113. SADST Register Field Descriptions .................................................................................
10-114. SABIDX Register Field Descriptions ................................................................................
10-115. SAMPPRXY Register Field Descriptions ...........................................................................
10-116. SACNTRLD Register Field Descriptions ............................................................................
10-117. SASRCBREF Register Field Descriptions ..........................................................................
10-118. SADSTBREF Register Field Descriptions ..........................................................................
10-119. DFCNTRLD Register Field Descriptions ............................................................................
10-120. DFSRCBREF Register Field Descriptions ..........................................................................
10-121. DFDSTBREF Register Field Descriptions ..........................................................................
10-122. DFOPT0 Register Field Descriptions................................................................................
10-77. EESRH Register Field Descriptions
SPRUHL7I – April 2014 – Revised December 2019
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Copyright © 2014–2019, Texas Instruments Incorporated
List of Tables
1716
1717
1718
1719
1720
1721
1722
1723
1724
1725
1726
1727
1728
1729
1730
1731
1732
1733
1734
1735
1736
1737
1737
1739
1740
1741
1742
1744
1745
1746
1747
1748
1749
1750
1752
1753
1754
1755
1756
1757
1758
1759
1760
1761
1762
1763
99
www.ti.com
...............................................................................
10-124. DFCNT0 Register Field Descriptions................................................................................
10-125. DFDST0 Register Field Descriptions ................................................................................
10-126. DFBIDX0 Register Field Descriptions ...............................................................................
10-127. DFMPPRXY0 Register Field Descriptions ..........................................................................
10-128. DFOPT1 Register Field Descriptions................................................................................
10-129. DFSRC1 Register Field Descriptions ...............................................................................
10-130. DFCNT1 Register Field Descriptions................................................................................
10-131. DFDST1 Register Field Descriptions ................................................................................
10-132. DFBIDX1 Register Field Descriptions ...............................................................................
10-133. DFMPPRXY1 Register Field Descriptions ..........................................................................
10-134. DFOPT2 Register Field Descriptions................................................................................
10-135. DFSRC2 Register Field Descriptions ...............................................................................
10-136. DFCNT2 Register Field Descriptions................................................................................
10-137. DFDST2 Register Field Descriptions ................................................................................
10-138. DFBIDX2 Register Field Descriptions ...............................................................................
10-139. DFMPPRXY2 Register Field Descriptions ..........................................................................
10-140. DFOPT3 Register Field Descriptions................................................................................
10-141. DFSRC3 Register Field Descriptions ...............................................................................
10-142. DFCNT3 Register Field Descriptions................................................................................
10-143. DFDST3 Register Field Descriptions ................................................................................
10-144. DFBIDX3 Register Field Descriptions ...............................................................................
10-145. DFMPPRXY3 Register Field Descriptions ..........................................................................
10-146. Debug List ..............................................................................................................
11-1. TSC_ADC (ADC0) Connectivity Attributes ...........................................................................
11-2. TSC_ADC (ADC0) Clock Signals .....................................................................................
11-3. TSC_ADC (ADC0) Pin List .............................................................................................
11-4. ADC0 Registers .........................................................................................................
11-5. ADC0_REVISION Register Field Descriptions ......................................................................
11-6. ADC0_SYSCONFIG Register Field Descriptions ...................................................................
11-7. ADC0_IRQSTS_RAW Register Field Descriptions .................................................................
11-8. ADC0_IRQSTS Register Field Descriptions .........................................................................
11-9. ADC0_IRQEN_SET Register Field Descriptions ....................................................................
11-10. ADC0_IRQEN_CLR Register Field Descriptions ...................................................................
11-11. ADC0_IRQWAKEUP Register Field Descriptions ..................................................................
11-12. ADC0_DMAEN_SET Register Field Descriptions ..................................................................
11-13. ADC0_DMAEN_CLR Register Field Descriptions ..................................................................
11-14. ADC0_CTRL Register Field Descriptions ............................................................................
11-15. ADC0_ADCSTAT Register Field Descriptions ......................................................................
11-16. ADC0_ADCRANGE Register Field Descriptions ....................................................................
11-17. ADC0_ADC_CLKDIV Register Field Descriptions ..................................................................
11-18. ADC0_ADC_MISC Register Field Descriptions .....................................................................
11-19. ADC0_STEPEN Register Field Descriptions ........................................................................
11-20. ADC0_IDLECONFIG Register Field Descriptions ..................................................................
11-21. ADC0_TS_CHARGE_STEPCONFIG Register Field Descriptions ...............................................
11-22. ADC0_TS_CHARGE_DELAY Register Field Descriptions ........................................................
11-23. ADC0_STEPCONFIG_0 Register Field Descriptions ..............................................................
11-24. ADC0_STEPDELAY_0 Register Field Descriptions ................................................................
11-25. ADC0_FIFOCOUNT_0 Register Field Descriptions ................................................................
10-123. DFSRC0 Register Field Descriptions
100
List of Tables
1765
1766
1767
1768
1769
1770
1772
1773
1774
1775
1776
1777
1779
1780
1781
1782
1783
1784
1786
1787
1788
1789
1790
1791
1797
1798
1798
1806
1808
1809
1810
1812
1814
1816
1818
1819
1820
1821
1823
1824
1825
1826
1827
1828
1830
1832
1833
1835
1836
SPRUHL7I – April 2014 – Revised December 2019
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11-26. ADC0_FIFOTHR_0 Register Field Descriptions .................................................................... 1837
11-27. ADC0_DMAREQ_0 Register Field Descriptions .................................................................... 1838
11-28. ADC0_FIFO0DATA Register Field Descriptions .................................................................... 1839
11-29. ADC0_FIFO1DATA Register Field Descriptions .................................................................... 1840
12-1.
MagneticCard Reader Connectivity Attributes ....................................................................... 1844
12-2.
MagneticCard Reader Clock Signals ................................................................................. 1845
12-3.
MagneticCard Reader Pin List ......................................................................................... 1845
12-4.
ADC1 AFE Signal List (see )
12-5.
ADC1_FIFO0DATA Register Field Descriptions .................................................................... 1857
12-6.
ADC1 Registers
12-7.
ADC1_REVISION Register Field Descriptions ...................................................................... 1860
12-8.
ADC1_SYSCONFIG Register Field Descriptions ................................................................... 1861
12-9.
ADC1_IRQSTS_RAW Register Field Descriptions ................................................................. 1862
..........................................................................................
.........................................................................................................
1854
1858
12-10. ADC1_IRQSTS Register Field Descriptions ......................................................................... 1863
12-11. ADC1_IRQEN_SET Register Field Descriptions .................................................................... 1864
...................................................................
ADC1_DMAEN_SET Register Field Descriptions ..................................................................
ADC1_DMAEN_CLR Register Field Descriptions ..................................................................
ADC1_CTRL Register Field Descriptions ............................................................................
ADC1_ADCSTAT Register Field Descriptions ......................................................................
ADC1_ADCRANGE Register Field Descriptions ....................................................................
ADC1_CLKDIV Register Field Descriptions .........................................................................
ADC1_STEPEN Register Field Descriptions ........................................................................
ADC1_IDLECONFIG Register Field Descriptions ..................................................................
ADC1_SWIPE_COMPARE_REG1_2 Register Field Descriptions ...............................................
ADC1_SWIPE_COMPARE_REG3_4 Register Field Descriptions ...............................................
ADC1_STEPCONFIG1 Register Field Descriptions ................................................................
ADC1_STEPDELAY1 Register Field Descriptions..................................................................
ADC1_STEPCONFIG2 Register Field Descriptions ................................................................
ADC1_STEPDELAY2 Register Field Descriptions..................................................................
ADC1_STEPCONFIG3 Register Field Descriptions ................................................................
ADC1_STEPDELAY3 Register Field Descriptions..................................................................
ADC1_STEPCONFIG4 Register Field Descriptions ................................................................
ADC1_STEPDELAY4 Register Field Descriptions..................................................................
ADC1_STEPCONFIG5 Register Field Descriptions ................................................................
ADC1_STEPDELAY5 Register Field Descriptions..................................................................
ADC1_STEPCONFIG6 Register Field Descriptions ................................................................
ADC1_STEPDELAY6 Register Field Descriptions..................................................................
ADC1_STEPCONFIG7 Register Field Descriptions ................................................................
ADC1_STEPDELAY7 Register Field Descriptions..................................................................
ADC1_STEPCONFIG8 Register Field Descriptions ................................................................
ADC1_STEPDELAY8 Register Field Descriptions..................................................................
ADC1_STEPCONFIG9 Register Field Descriptions ................................................................
ADC1_STEPDELAY9 Register Field Descriptions..................................................................
ADC1_STEPCONFIG10 Register Field Descriptions ..............................................................
ADC1_STEPDELAY10 Register Field Descriptions ................................................................
ADC1_STEPCONFIG11 Register Field Descriptions ..............................................................
ADC1_STEPDELAY11 Register Field Descriptions ................................................................
ADC1_STEPCONFIG12 Register Field Descriptions ..............................................................
12-12. ADC1_IRQEN_CLR Register Field Descriptions
1865
12-13.
1866
12-14.
12-15.
12-16.
12-17.
12-18.
12-19.
12-20.
12-21.
12-22.
12-23.
12-24.
12-25.
12-26.
12-27.
12-28.
12-29.
12-30.
12-31.
12-32.
12-33.
12-34.
12-35.
12-36.
12-37.
12-38.
12-39.
12-40.
12-41.
12-42.
12-43.
12-44.
12-45.
SPRUHL7I – April 2014 – Revised December 2019
Submit Documentation Feedback
Copyright © 2014–2019, Texas Instruments Incorporated
List of Tables
1867
1868
1869
1870
1871
1872
1873
1874
1875
1876
1878
1879
1881
1882
1884
1885
1887
1888
1890
1891
1893
1894
1896
1897
1899
1900
1902
1903
1905
1906
1908
1909
101
www.ti.com
12-46. ADC1_STEPDELAY12 Register Field Descriptions ................................................................ 1911
12-47. ADC1_STEPCONFIG13 Register Field Descriptions
..............................................................
1912
12-48. ADC1_STEPDELAY13 Register Field Descriptions ................................................................ 1914
1915
12-50.
1917
12-51.
12-52.
12-53.
12-54.
12-55.
12-56.
12-57.
12-58.
12-59.
12-60.
12-61.
12-62.
13-1.
13-2.
13-3.
13-4.
13-5.
13-6.
13-7.
13-8.
13-9.
13-10.
13-11.
13-12.
13-13.
13-14.
13-15.
13-16.
13-17.
13-18.
13-19.
13-20.
13-21.
13-22.
13-23.
13-24.
13-25.
13-26.
13-27.
13-28.
13-29.
13-30.
13-31.
13-32.
102
..............................................................
ADC1_STEPDELAY14 Register Field Descriptions ................................................................
ADC1_STEPCONFIG15 Register Field Descriptions ..............................................................
ADC1_STEPDELAY15 Register Field Descriptions ................................................................
ADC1_STEPCONFIG16 Register Field Descriptions ..............................................................
ADC1_STEPDELAY16 Register Field Descriptions ................................................................
ADC1_FIFO0COUNT Register Field Descriptions ..................................................................
ADC1_FIFO0THR Register Field Descriptions ......................................................................
ADC1_DMA0REQ Register Field Descriptions......................................................................
ADC1_FIFO1COUNT Register Field Descriptions ..................................................................
ADC1_FIFO1THR Register Field Descriptions ......................................................................
ADC1_DMA1REQ Register Field Descriptions......................................................................
ADC1_FIFO0DATA Register Field Descriptions ....................................................................
ADC1_FIFO1DATA Register Field Descriptions ....................................................................
Unsupported Display Subsystem Features ..........................................................................
DSS Connectivity Attributes............................................................................................
DSS Clock Signals ......................................................................................................
DSS Pin List..............................................................................................................
LCD Interface Signals and Configurations ...........................................................................
I/O Pad Mode Selection ................................................................................................
LCD Interface Signals (RFBI Mode) ..................................................................................
LCD Interface Signals (Bypass Mode) ...............................................................................
Number of Displayed Pixels per Pixel Clock Cycle Based on Display Type ....................................
Programmable Timing Fields in RFBI Mode .........................................................................
Programmable Fields in Bypass Mode ...............................................................................
Functional Clock Frequency Requirement in RGB16 YUV4:2:2—Active Matrix Display ......................
Functional Clock Frequency Requirement in RGB24—Active Matrix Display...................................
Alpha Blending 4-Bit Values ...........................................................................................
8-Bit Interface Configuration/24-Bit Mode ............................................................................
Maximum Width Allowed ...............................................................................................
16-Bit Interface Configuration/24-Bit Mode ..........................................................................
Read/Write Function Description ......................................................................................
Minimum Cycle Time for CSx/WE Always Asserted ................................................................
Display Subsystem Interrupts..........................................................................................
Shadow Registers .......................................................................................................
Vertical/Horizontal Accumulator Phase ...............................................................................
Color Space Conversion Register Values ...........................................................................
Programming Rules .....................................................................................................
Pixel Clock Frequency Limitations - RGB16 and YUV4:2:2 Active Matrix Display .............................
Pixel Clock Frequency Limitations - RGB16 and YUV4:2:2 Passive Matrix Display - Mono4 ................
Pixel Clock Frequency Limitations - RGB16 and YUV4:2:2 Passive Matrix Display - Mono8 ................
Pixel Clock Frequency Limitations - RGB16 and YUV4:2:2 Passive Matrix Display - Color ..................
RFBI Behavior ...........................................................................................................
RFBI Timings Configuration............................................................................................
Vertical FIR Coefficients Corresponding Table (3-Tap Configuration) ...........................................
Vertical FIR Coefficients Corresponding Table (5-Tap Configuration) ...........................................
12-49. ADC1_STEPCONFIG14 Register Field Descriptions
List of Tables
1918
1920
1921
1923
1924
1925
1926
1927
1928
1929
1930
1931
1934
1935
1936
1936
1939
1941
1942
1944
1945
1950
1951
1969
1969
1975
1979
1980
1982
1983
1983
1984
1987
1997
1998
1999
2001
2001
2001
2001
2009
2013
2022
2023
SPRUHL7I – April 2014 – Revised December 2019
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Copyright © 2014–2019, Texas Instruments Incorporated
www.ti.com
13-33. Horizontal FIR Coefficients Corresponding Table (5-Tap Configuration) ........................................ 2023
13-34. Vertical/Horizontal Accumulator Phase ............................................................................... 2025
13-35. Up-Sampling Vertical Filter Coefficients (Three Taps) ............................................................. 2026
13-36. Up-Sampling Vertical Filter Coefficients (Five Taps) ............................................................... 2026
13-37. Up-Sampling Horizontal Filter Coefficients (Five Taps) ............................................................ 2026
13-38. Down-Sampling Vertical Filter Coefficients (Three Taps) .......................................................... 2027
13-39. Down-Sampling Vertical Filter Coefficients (Five Taps) ............................................................ 2028
13-40. Down-Sampling Horizontal Filter Coefficients (Five Taps)......................................................... 2028
13-41. DSS_DISPC Registers ................................................................................................. 2033
13-42. DISPC_REVISION Register Field Descriptions ..................................................................... 2037
13-43. DISPC_SYSCFG Register Field Descriptions ....................................................................... 2038
13-44. DISPC_SYSSTS Register Field Descriptions ....................................................................... 2040
13-45. DISPC_IRQSTS Register Field Descriptions ........................................................................ 2041
13-46. DISPC_IRQEN Register Field Descriptions ......................................................................... 2044
13-47. DISPC_CTRL Register Field Descriptions ........................................................................... 2046
13-48. DISPC_CFG Register Field Descriptions ............................................................................ 2049
13-49. DISPC_DEFAULT_COLOR_0 Register Field Descriptions
.......................................................
2052
13-50. DISPC_TRANS_COLOR_0 Register Field Descriptions ........................................................... 2053
13-51. DISPC_LINE_STS Register Field Descriptions ..................................................................... 2054
13-52. DISPC_LINE_NUMBER Register Field Descriptions ............................................................... 2055
13-53. DISPC_TIMING_H Register Field Descriptions ..................................................................... 2056
13-54. DISPC_TIMING_V Register Field Descriptions ..................................................................... 2057
13-55. DISPC_POL_FREQ Register Field Descriptions
...................................................................
2058
13-56. DISPC_DIVISOR Register Field Descriptions ....................................................................... 2060
13-57. DISPC_GLOBAL_ALPHA Register Field Descriptions ............................................................. 2061
13-58. DISPC_SIZE_DIG Register Field Descriptions...................................................................... 2062
13-59. DISPC_SIZE_LCD Register Field Descriptions ..................................................................... 2063
13-60. DISPC_GFX_BA_0 Register Field Descriptions .................................................................... 2064
13-61. DISPC_GFX_POSITION Register Field Descriptions .............................................................. 2065
13-62. DISPC_GFX_SIZE Register Field Descriptions ..................................................................... 2066
13-63. DISPC_GFX_ATTRS Register Field Descriptions .................................................................. 2067
13-64. DISPC_GFX_FIFO_THR Register Field Descriptions .............................................................. 2069
13-65. DISPC_GFX_FIFO_SIZE_STS Register Field Descriptions
......................................................
2070
13-66. DISPC_GFX_ROW_INC Register Field Descriptions .............................................................. 2071
13-67. DISPC_GFX_PIXEL_INC Register Field Descriptions ............................................................. 2072
13-68. DISPC_GFX_WINDOW_SKIP Register Field Descriptions ....................................................... 2073
13-69. DISPC_GFX_TBL_BA Register Field Descriptions ................................................................. 2074
13-70. DISPC_VID1_BA_0 to DISPC_VID1_BA_1 Register Field Descriptions ........................................ 2075
.............................................................
DISPC_VID1_SIZE Register Field Descriptions ....................................................................
DISPC_VID1_ATTRS Register Field Descriptions..................................................................
DISPC_VID1_FIFO_THR Register Field Descriptions .............................................................
DISPC_VID1_FIFO_SIZE_STS Register Field Descriptions ......................................................
DISPC_VID1_ROW_INC Register Field Descriptions ..............................................................
DISPC_VID1_PIXEL_INC Register Field Descriptions.............................................................
DISPC_VID1_FIR Register Field Descriptions ......................................................................
DISPC_VID1_PICTURE_SIZE Register Field Descriptions .......................................................
DISPC_VID1_ACCU_0 to DISPC_VID1_ACCU_1 Register Field Descriptions ................................
DISPC_VID1_FIR_COEF_H_0 Register Field Descriptions.......................................................
13-71. DISPC_VID1_POSITION Register Field Descriptions
13-72.
13-73.
13-74.
13-75.
13-76.
13-77.
13-78.
13-79.
13-80.
13-81.
SPRUHL7I – April 2014 – Revised December 2019
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Copyright © 2014–2019, Texas Instruments Incorporated
List of Tables
2076
2077
2078
2081
2082
2083
2084
2085
2086
2087
2088
103
www.ti.com
13-82. DISPC_VID1_FIR_COEF_HV_0 Register Field Descriptions ..................................................... 2089
13-83. DISPC_VID1_CONV_COEF0 Register Field Descriptions ........................................................ 2090
13-84. DISPC_VID1_CONV_COEF1 Register Field Descriptions ........................................................ 2091
13-85. DISPC_VID1_CONV_COEF2 Register Field Descriptions ........................................................ 2092
13-86. DISPC_VID1_CONV_COEF3 Register Field Descriptions ........................................................ 2093
13-87. DISPC_VID1_CONV_COEF4 Register Field Descriptions ........................................................ 2094
13-88. DISPC_VID2_BA_0 to DISPC_VID2_BA_1 Register Field Descriptions ........................................ 2095
.............................................................
....................................................................
13-91. DISPC_VID2_ATTRS Register Field Descriptions..................................................................
13-92. DISPC_VID2_FIFO_THR Register Field Descriptions .............................................................
13-93. DISPC_VID2_FIFO_SIZE_STS Register Field Descriptions ......................................................
13-94. DISPC_VID2_ROW_INC Register Field Descriptions ..............................................................
13-95. DISPC_VID2_PIXEL_INC Register Field Descriptions.............................................................
13-96. DISPC_VID2_FIR Register Field Descriptions ......................................................................
13-97. DISPC_VID2_PICTURE_SIZE Register Field Descriptions .......................................................
13-98. DISPC_VID2_ACCU_0 to DISPC_VID2_ACCU_1 Register Field Descriptions ................................
13-99. DISPC_VID2_FIR_COEF_H_0 Register Field Descriptions.......................................................
13-100. DISPC_VID2_FIR_COEF_HV_0 Register Field Descriptions ...................................................
13-101. DISPC_VID2_CONV_COEF0 Register Field Descriptions .......................................................
13-102. DISPC_VID2_CONV_COEF1 Register Field Descriptions .......................................................
13-103. DISPC_VID2_CONV_COEF2 Register Field Descriptions .......................................................
13-104. DISPC_VID2_CONV_COEF3 Register Field Descriptions .......................................................
13-105. DISPC_VID2_CONV_COEF4 Register Field Descriptions .......................................................
13-106. DISPC_DATA_CYCLE_0 Register Field Descriptions ............................................................
13-107. DISPC_VID1_FIR_COEF_V_0 to DISPC_VID1_FIR_COEF_V_7 Register Field Descriptions .............
13-108. DISPC_VID2_FIR_COEF_V_0 to DISPC_VID2_FIR_COEF_V_7 Register Field Descriptions .............
13-109. DISPC_CPR_COEF_R Register Field Descriptions ..............................................................
13-110. DISPC_CPR_COEF_G Register Field Descriptions ..............................................................
13-111. DISPC_CPR_COEF_B Register Field Descriptions ..............................................................
13-112. DISPC_GFX_PRELOAD Register Field Descriptions.............................................................
13-113. DISPC_VID1_PRELOAD Register Field Descriptions ............................................................
13-114. DISPC_VID2_PRELOAD Register Field Descriptions ............................................................
13-115. DSS_TOP Registers ...................................................................................................
13-116. DSS_REVISIONNUMBER Register Field Descriptions ...........................................................
13-117. DSS_SYSCONFIG Register Field Descriptions ...................................................................
13-118. DSS_SYSSTS Register Field Descriptions.........................................................................
13-119. DSS_IRQSTS Register Field Descriptions .........................................................................
13-120. DSS_CTRL Register Field Descriptions ............................................................................
13-121. DSS_CLK_STS Register Field Descriptions .......................................................................
13-122. DSS_RFBI REGISTERS ..............................................................................................
13-123. RFBI_REVISION Register Field Descriptions ......................................................................
13-124. RFBI_SYSCONFIG Register Field Descriptions ...................................................................
13-125. RFBI_SYSSTS Register Field Descriptions ........................................................................
13-126. RFBI_CTRL Register Field Descriptions............................................................................
13-127. RFBI_PIXEL_CNT Register Field Descriptions ....................................................................
13-128. RFBI_LINE_NUMBER Register Field Descriptions ...............................................................
13-129. RFBI_CMD Register Field Descriptions ............................................................................
13-130. RFBI_PARAM Register Field Descriptions .........................................................................
104
13-89. DISPC_VID2_POSITION Register Field Descriptions
2096
13-90. DISPC_VID2_SIZE Register Field Descriptions
2097
List of Tables
2098
2101
2102
2103
2104
2105
2106
2107
2108
2109
2110
2111
2112
2113
2114
2115
2116
2117
2118
2119
2120
2121
2122
2123
2123
2124
2125
2126
2127
2128
2129
2130
2131
2132
2133
2134
2136
2137
2138
2139
SPRUHL7I – April 2014 – Revised December 2019
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Copyright © 2014–2019, Texas Instruments Incorporated
www.ti.com
...........................................................................
13-132. RFBI_READ Register Field Descriptions ...........................................................................
13-133. RFBI_STS Register Field Descriptions .............................................................................
13-134. RFBI_CONFIG_0 Register Field Descriptions .....................................................................
13-135. RFBI_ONOFF_TIME_0 Register Field Descriptions ..............................................................
13-136. RFBI_CYCLE_TIME_0 Register Field Descriptions ...............................................................
13-137. RFBI_DATA_CYCLE1_0 Register Field Descriptions ............................................................
13-138. RFBI_DATA_CYCLE2_0 Register Field Descriptions ............................................................
13-139. RFBI_DATA_CYCLE3_0 Register Field Descriptions ............................................................
13-140. RFBI_VSYNC_WIDTH Register Field Descriptions ...............................................................
13-141. RFBI_HSYNC_WIDTH Register Field Descriptions ...............................................................
14-1. Unsupported VPFE Features ..........................................................................................
14-2. VPFE Connectivity Attributes ..........................................................................................
14-3. VPFE Clock Signals.....................................................................................................
14-4. VPFE Pin List ............................................................................................................
14-5. Summary of VPFE Signal Pins and Common Input Devices ......................................................
14-6. CCD Interface Signals ..................................................................................................
14-7. ITU-R BT.656 Interface Signals .......................................................................................
14-8. Video Timing Reference Codes for SAV and EAV .................................................................
14-9. F, V, H Signal Descriptions ............................................................................................
14-10. F, H, V Protection (error correction) Bits .............................................................................
14-11. CCD Interface Signals ..................................................................................................
14-12. Example for Decimation Pattern.......................................................................................
14-13. A-Law Table – Part 1 ...................................................................................................
14-14. A-Law Table – Part 2 ...................................................................................................
14-15. Storage Format in external memory for Raw Data Mode ..........................................................
14-16. Storage Format in external memory for BT.656/YCbCr Modes ...................................................
14-17. Basic Configuration of VPFE Registers ..............................................................................
14-18. Conditional Configuration of VPFE Registers .......................................................................
14-19. VPFE Registers..........................................................................................................
14-20. VPFE_REVISION Register Field Descriptions ......................................................................
14-21. VPFE_PCR Register Field Descriptions .............................................................................
14-22. VPFE_SYNMODE Register Field Descriptions .....................................................................
14-23. VPFE_HD_VD_WID Register Field Descriptions ...................................................................
14-24. VPFE_PIX_LINES Register Field Descriptions .....................................................................
14-25. VPFE_HORZ_INFO Register Field Descriptions ...................................................................
14-26. VPFE_VERT_START Register Field Descriptions..................................................................
14-27. VPFE_VERT_LINES Register Field Descriptions...................................................................
14-28. VPFE_CULLING Register Field Descriptions .......................................................................
14-29. VPFE_HSIZE_OFF Register Field Descriptions ....................................................................
14-30. VPFE_SDOFST Register Field Descriptions ........................................................................
14-31. VPFE_SDR_ADDR Register Field Descriptions ....................................................................
14-32. VPFE_CLAMP Register Field Descriptions ..........................................................................
14-33. VPFE_DCSUB Register Field Descriptions ..........................................................................
14-34. VPFE_COLPTN Register Field Descriptions ........................................................................
14-35. VPFE_BLKCMP Register Field Descriptions ........................................................................
14-36. VPFE_VDINT Register Field Descriptions ...........................................................................
14-37. VPFE_ALAW Register Field Descriptions ...........................................................................
14-38. VPFE_REC656IF Register Field Descriptions ......................................................................
13-131. RFBI_DATA Register Field Descriptions
SPRUHL7I – April 2014 – Revised December 2019
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Copyright © 2014–2019, Texas Instruments Incorporated
List of Tables
2140
2141
2142
2143
2145
2146
2147
2148
2149
2150
2151
2153
2154
2155
2155
2156
2157
2159
2160
2160
2160
2161
2166
2167
2168
2173
2176
2177
2178
2180
2182
2183
2184
2186
2187
2188
2189
2190
2191
2192
2193
2195
2196
2198
2199
2201
2202
2203
2204
105
www.ti.com
14-39. VPFE_CCDCFG Register Field Descriptions........................................................................ 2205
14-40. VPFE_DMA_CNTL Register Field Descriptions..................................................................... 2207
14-41. VPFE_SYSCONFIG Register Field Descriptions ................................................................... 2208
14-42. VPFE_CONFIG Register Field Descriptions......................................................................... 2210
14-43. VPFE_IRQ_EOI Register Field Descriptions ........................................................................ 2211
14-44. VPFE_IRQ_STS_RAW Register Field Descriptions ................................................................ 2212
14-45. VPFE_IRQ_STS Register Field Descriptions........................................................................ 2213
14-46. VPFE_IRQ_EN_SET Register Field Descriptions .................................................................. 2214
14-47. VPFE_IRQ_EN_CLR Register Field Descriptions .................................................................. 2215
15-1.
Unsupported CPGMAC Features ..................................................................................... 2218
15-2.
Ethernet Switch Connectivity Attributes .............................................................................. 2220
15-3.
Ethernet Switch Clock Signals ......................................................................................... 2221
15-4.
Ethernet Switch Pin List ................................................................................................ 2222
15-5.
GMII Interface Signal Descriptions in MII (100/10Mbps) Mode ................................................... 2225
15-6.
RMII Interface Signal Descriptions .................................................................................... 2226
15-7.
RGMII Interface Signal Descriptions .................................................................................. 2227
15-8.
VLAN Header Encapsulation Word Field Descriptions ............................................................. 2247
15-9.
Learned Address Control Bits
.........................................................................................
2248
15-10. Free (Unused) Address Table Entry Bit Values ..................................................................... 2248
15-11. Multicast Address Table Entry Bit Values ............................................................................ 2249
15-12. VLAN/Multicast Address Table Entry Bit Values .................................................................... 2249
15-13. Unicast Address Table Entry Bit Values
.............................................................................
2250
15-14. OUI Unicast Address Table Entry Bit Values ........................................................................ 2251
.............................................................................
VLAN Table Entry .......................................................................................................
Operations of Emulation Control Input and Register Bits ..........................................................
Rx Statistics Summary..................................................................................................
Tx Statistics Summary ..................................................................................................
Values of messageType field ..........................................................................................
MDIO Read Frame Format.............................................................................................
MDIO Write Frame Format .............................................................................................
CPSW_ALE Registers ..................................................................................................
CPSW_ALE_IDVER Register Field Descriptions ...................................................................
CPSW_ALE_CTRL Register Field Descriptions ....................................................................
CPSW_ALE_PRESCALE Register Field Descriptions .............................................................
CPSW_ALE_UNKNOWN_VLAN Register Field Descriptions .....................................................
CPSW_ALE_TBLCTL Register Field Descriptions .................................................................
CPSW_ALE_TBLW2 Register Field Descriptions ..................................................................
CPSW_ALE_TBLW1 Register Field Descriptions ..................................................................
CPSW_ALE_TBLW0 Register Field Descriptions ..................................................................
CPSW_ALE_PORTCTL_0 to CPSW_ALE_PORTCTL_5 Register Field Descriptions ........................
CPSW_CPDMA Registers .............................................................................................
CPSW_TX_IDVER Register Field Descriptions .....................................................................
CPSW_TX_CTRL Register Field Descriptions ......................................................................
CPSW_TX_TEARDOWN Register Field Descriptions .............................................................
CPSW_RX_IDVER Register Field Descriptions.....................................................................
CPSW_RX_CTRL Register Field Descriptions ......................................................................
CPSW_RX_TEARDOWN Register Field Descriptions .............................................................
CPSW_CPDMA_SOFT_RESET Register Field Descriptions .....................................................
15-15. Unicast Address Table Entry Bit Values
15-16.
15-17.
15-18.
15-19.
15-20.
15-21.
15-22.
15-23.
15-24.
15-25.
15-26.
15-27.
15-28.
15-29.
15-30.
15-31.
15-32.
15-33.
15-34.
15-35.
15-36.
15-37.
15-38.
15-39.
15-40.
106
List of Tables
2252
2253
2263
2272
2274
2284
2285
2285
2293
2294
2295
2297
2298
2299
2300
2301
2302
2303
2304
2306
2307
2308
2309
2310
2311
2312
SPRUHL7I – April 2014 – Revised December 2019
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15-41. CPSW_DMACTRL Register Field Descriptions ..................................................................... 2313
15-42. CPSW_DMASTS Register Field Descriptions ....................................................................... 2315
15-43. CPSW_RX_BUFFER_OFFSET Register Field Descriptions ...................................................... 2317
15-44. CPSW_EMCTRL Register Field Descriptions ....................................................................... 2318
..............................................................
..............................................................
CPSW_TX_PRI2_RATE Register Field Descriptions ..............................................................
CPSW_TX_PRI3_RATE Register Field Descriptions ..............................................................
CPSW_TX_PRI4_RATE Register Field Descriptions ..............................................................
CPSW_TX_PRI5_RATE Register Field Descriptions ..............................................................
CPSW_TX_PRI6_RATE Register Field Descriptions ..............................................................
CPSW_TX_PRI7_RATE Register Field Descriptions ..............................................................
CPSW_TX_INTSTAT_RAW Register Field Descriptions ..........................................................
CPSW_TX_INTSTAT_MASKED Register Field Descriptions .....................................................
CPSW_TX_INTMASK_SET Register Field Descriptions ..........................................................
CPSW_TX_INTMASK_CLR Register Field Descriptions ..........................................................
CPSW_CPDMA_IN_VECTOR Register Field Descriptions .......................................................
CPSW_CPDMA_EOI_VECTOR Register Field Descriptions .....................................................
CPSW_RX_INTSTAT_RAW Register Field Descriptions ..........................................................
CPSW_RX_INTSTAT_MASKED Register Field Descriptions .....................................................
CPSW_RX_INTMASK_SET Register Field Descriptions ..........................................................
CPSW_RX_INTMASK_CLR Register Field Descriptions ..........................................................
CPSW_DMA_INTSTAT_RAW Register Field Descriptions .......................................................
CPSW_DMA_INTSTAT_MASKED Register Field Descriptions ..................................................
CPSW_DMA_INTMASK_SET Register Field Descriptions ........................................................
CPSW_DMA_INTMASK_CLR Register Field Descriptions ........................................................
CPSW_RX0_PENDTHRESH Register Field Descriptions .........................................................
CPSW_RX1_PENDTHRESH Register Field Descriptions .........................................................
CPSW_RX2_PENDTHRESH Register Field Descriptions .........................................................
CPSW_RX3_PENDTHRESH Register Field Descriptions .........................................................
CPSW_RX4_PENDTHRESH Register Field Descriptions .........................................................
CPSW_RX5_PENDTHRESH Register Field Descriptions .........................................................
CPSW_RX6_PENDTHRESH Register Field Descriptions .........................................................
CPSW_RX7_PENDTHRESH Register Field Descriptions .........................................................
CPSW_RX0_FREEBUFFER Register Field Descriptions .........................................................
CPSW_RX1_FREEBUFFER Register Field Descriptions .........................................................
CPSW_RX2_FREEBUFFER Register Field Descriptions .........................................................
CPSW_RX3_FREEBUFFER Register Field Descriptions .........................................................
CPSW_RX4_FREEBUFFER Register Field Descriptions .........................................................
CPSW_RX5_FREEBUFFER Register Field Descriptions .........................................................
CPSW_RX6_FREEBUFFER Register Field Descriptions .........................................................
CPSW_RX7_FREEBUFFER Register Field Descriptions .........................................................
CPSW_CPTS Registers ................................................................................................
CPSW_CPTS_IDVER Register Field Descriptions .................................................................
CPSW_CPTS_CTRL Register Field Descriptions ..................................................................
CPSW_RFTCLK_SEL Register Field Descriptions .................................................................
CPSW_CPTS_PUSH Register Field Descriptions ..................................................................
CPSW_CPTS_LOAD_VAL Register Field Descriptions ...........................................................
CPSW_CPTS_LOAD_EN Register Field Descriptions .............................................................
15-45. CPSW_TX_PRI0_RATE Register Field Descriptions
2319
15-46. CPSW_TX_PRI1_RATE Register Field Descriptions
2320
15-47.
2321
15-48.
15-49.
15-50.
15-51.
15-52.
15-53.
15-54.
15-55.
15-56.
15-57.
15-58.
15-59.
15-60.
15-61.
15-62.
15-63.
15-64.
15-65.
15-66.
15-67.
15-68.
15-69.
15-70.
15-71.
15-72.
15-73.
15-74.
15-75.
15-76.
15-77.
15-78.
15-79.
15-80.
15-81.
15-82.
15-83.
15-84.
15-85.
15-86.
15-87.
15-88.
15-89.
SPRUHL7I – April 2014 – Revised December 2019
Submit Documentation Feedback
Copyright © 2014–2019, Texas Instruments Incorporated
List of Tables
2322
2323
2324
2325
2326
2327
2328
2329
2330
2331
2332
2333
2334
2335
2336
2337
2338
2339
2340
2341
2342
2343
2344
2345
2346
2347
2348
2349
2350
2351
2352
2353
2354
2355
2356
2356
2357
2358
2359
2360
2361
2362
107
www.ti.com
15-90. CPSW_CPTS_COMP_VAL Register Field Descriptions ........................................................... 2363
15-91. CPSW_CPTS_COMP_LENGTH Register Field Descriptions ..................................................... 2364
15-92. CPSW_CPTS_INTSTAT_RAW Register Field Descriptions ...................................................... 2365
15-93. CPSW_CPTS_INTSTAT_MASKED Register Field Descriptions ................................................. 2366
15-94. CPSW_CPTS_INT_EN Register Field Descriptions ................................................................ 2367
15-95. CPSW_CPTS_EVT_POP Register Field Descriptions ............................................................. 2368
15-96. CPSW_CPTS_EVT_LOW Register Field Descriptions
............................................................
2369
15-97. CPSW_CPTS_EVT_MID Register Field Descriptions .............................................................. 2370
15-98. CPSW_CPTS_EVT_HIGH Register Field Descriptions ............................................................ 2371
15-99. CPSW_STATS REGISTERS .......................................................................................... 2372
15-100. CPDMA_STATERAM REGISTERS ................................................................................. 2373
15-101. CPSW_STATERAM_TX0_HDP Register Field Descriptions .................................................... 2375
15-102. CPSW_STATERAM_TX1_HDP Register Field Descriptions .................................................... 2376
15-103. CPSW_STATERAM_TX2_HDP Register Field Descriptions .................................................... 2377
15-104. CPSW_STATERAM_TX3_HDP Register Field Descriptions .................................................... 2378
15-105. CPSW_STATERAM_TX4_HDP Register Field Descriptions .................................................... 2379
15-106. CPSW_STATERAM_TX5_HDP Register Field Descriptions .................................................... 2380
15-107. CPSW_STATERAM_TX6_HDP Register Field Descriptions .................................................... 2381
15-108. CPSW_STATERAM_TX7_HDP Register Field Descriptions .................................................... 2382
15-109. CPSW_STATERAM_RX0_HDP Register Field Descriptions .................................................... 2383
15-110. CPSW_STATERAM_RX1_HDP Register Field Descriptions .................................................... 2384
15-111. CPSW_STATERAM_RX2_HDP Register Field Descriptions .................................................... 2385
15-112. CPSW_STATERAM_RX3_HDP Register Field Descriptions .................................................... 2386
15-113. CPSW_STATERAM_RX4_HDP Register Field Descriptions .................................................... 2387
15-114. CPSW_STATERAM_RX5_HDP Register Field Descriptions .................................................... 2388
15-115. CPSW_STATERAM_RX6_HDP Register Field Descriptions .................................................... 2389
15-116. CPSW_STATERAM_RX7_HDP Register Field Descriptions .................................................... 2390
15-117. CPSW_STATERAM_TX0_CP Register Field Descriptions ...................................................... 2391
15-118. CPSW_STATERAM_TX1_CP Register Field Descriptions ...................................................... 2392
15-119. CPSW_STATERAM_TX2_CP Register Field Descriptions ...................................................... 2393
15-120. CPSW_STATERAM_TX3_CP Register Field Descriptions ...................................................... 2394
15-121. CPSW_STATERAM_TX4_CP Register Field Descriptions ...................................................... 2395
15-122. CPSW_STATERAM_TX5_CP Register Field Descriptions ...................................................... 2396
15-123. CPSW_STATERAM_TX6_CP Register Field Descriptions ...................................................... 2397
15-124. CPSW_STATERAM_TX7_CP Register Field Descriptions ...................................................... 2398
15-125. CPSW_STATERAM_RX0_CP Register Field Descriptions ...................................................... 2399
15-126. CPSW_STATERAM_RX1_CP Register Field Descriptions ...................................................... 2400
15-127. CPSW_STATERAM_RX2_CP Register Field Descriptions ...................................................... 2401
15-128. CPSW_STATERAM_RX3_CP Register Field Descriptions ...................................................... 2402
15-129. CPSW_STATERAM_RX4_CP Register Field Descriptions ...................................................... 2403
15-130. CPSW_STATERAM_RX5_CP Register Field Descriptions ...................................................... 2404
15-131. CPSW_STATERAM_RX6_CP Register Field Descriptions ...................................................... 2405
15-132. CPSW_STATERAM_RX7_CP Register Field Descriptions ...................................................... 2406
15-133. CPSW_PORT Registers .............................................................................................. 2406
15-134. CPSW_PORT_P0_CTRL Register Field Descriptions ............................................................ 2409
15-135. CPSW_PORT_P0_MAX_BLKS Register Field Descriptions ..................................................... 2410
15-136. CPSW_PORT_P0_BLK_CNT Register Field Descriptions ....................................................... 2411
15-137. CPSW_PORT_P0_TX_IN_CTL Register Field Descriptions ..................................................... 2412
15-138. CPSW_PORT_P0_VLAN Register Field Descriptions ............................................................ 2413
108
List of Tables
SPRUHL7I – April 2014 – Revised December 2019
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www.ti.com
15-139. CPSW_PORT_P0_TX_PRI_MAP Register Field Descriptions .................................................. 2414
15-140. CPSW_PORT_P0_CPDMA_TX_PRI_MAP Register Field Descriptions ....................................... 2415
15-141. CPSW_PORT_P0_CPDMA_RX_CH_MAP Register Field Descriptions ....................................... 2416
15-142. CPSW_PORT_P0_RX_DSCP_PRI_MAP0 Register Field Descriptions ....................................... 2417
15-143. CPSW_PORT_P0_RX_DSCP_PRI_MAP1 Register Field Descriptions ....................................... 2418
15-144. CPSW_PORT_P0_RX_DSCP_PRI_MAP2 Register Field Descriptions ....................................... 2419
15-145. CPSW_PORT_P0_RX_DSCP_PRI_MAP3 Register Field Descriptions ....................................... 2420
15-146. CPSW_PORT_P0_RX_DSCP_PRI_MAP4 Register Field Descriptions ....................................... 2421
15-147. CPSW_PORT_P0_RX_DSCP_PRI_MAP5 Register Field Descriptions ....................................... 2422
15-148. CPSW_PORT_P0_RX_DSCP_PRI_MAP6 Register Field Descriptions ....................................... 2423
15-149. CPSW_PORT_P0_RX_DSCP_PRI_MAP7 Register Field Descriptions ....................................... 2424
15-150. CPSW_PORT_P1_CTRL Register Field Descriptions ............................................................ 2425
15-151. CPSW_PORT_P1_TS_CTL2 Register Field Descriptions ....................................................... 2427
15-152. CPSW_PORT_P1_MAX_BLKS Register Field Descriptions ..................................................... 2428
15-153. CPSW_PORT_P1_BLK_CNT Register Field Descriptions ....................................................... 2429
15-154. CPSW_PORT_P1_TX_IN_CTL Register Field Descriptions ..................................................... 2430
15-155. CPSW_PORT_P1_VLAN Register Field Descriptions ............................................................ 2431
15-156. CPSW_PORT_P1_TX_PRI_MAP Register Field Descriptions .................................................. 2432
.............................................
CPSW_PORT_P1_SA_LO Register Field Descriptions ..........................................................
CPSW_PORT_P1_SA_HI Register Field Descriptions ...........................................................
CPSW_PORT_P1_SEND_PERCENT Register Field Descriptions .............................................
CPSW_PORT_P1_RX_DSCP_PRI_MAP0 Register Field Descriptions .......................................
CPSW_PORT_P1_RX_DSCP_PRI_MAP1 Register Field Descriptions .......................................
CPSW_PORT_P1_RX_DSCP_PRI_MAP2 Register Field Descriptions .......................................
CPSW_PORT_P1_RX_DSCP_PRI_MAP3 Register Field Descriptions .......................................
CPSW_PORT_P1_RX_DSCP_PRI_MAP4 Register Field Descriptions .......................................
CPSW_PORT_P1_RX_DSCP_PRI_MAP5 Register Field Descriptions .......................................
CPSW_PORT_P1_RX_DSCP_PRI_MAP6 Register Field Descriptions .......................................
CPSW_PORT_P1_RX_DSCP_PRI_MAP7 Register Field Descriptions .......................................
CPSW_PORT_P2_CTRL Register Field Descriptions ............................................................
CPSW_PORT_P2_TS_CTL2 Register Field Descriptions .......................................................
CPSW_PORT_P2_MAX_BLKS Register Field Descriptions .....................................................
CPSW_PORT_P2_BLK_CNT Register Field Descriptions .......................................................
CPSW_PORT_P2_TX_IN_CTL Register Field Descriptions .....................................................
CPSW_PORT_P2_VLAN Register Field Descriptions ............................................................
CPSW_PORT_P2_TX_PRI_MAP Register Field Descriptions ..................................................
CPSW_PORT_P2_TS_SEQ_MTYPE Register Field Descriptions .............................................
CPSW_PORT_P2_SA_LO Register Field Descriptions ..........................................................
CPSW_PORT_P2_SA_HI Register Field Descriptions ...........................................................
CPSW_PORT_P2_SEND_PERCENT Register Field Descriptions .............................................
CPSW_PORT_P2_RX_DSCP_PRI_MAP0 Register Field Descriptions .......................................
CPSW_PORT_P2_RX_DSCP_PRI_MAP1 Register Field Descriptions .......................................
CPSW_PORT_P2_RX_DSCP_PRI_MAP2 Register Field Descriptions .......................................
CPSW_PORT_P2_RX_DSCP_PRI_MAP3 Register Field Descriptions .......................................
CPSW_PORT_P2_RX_DSCP_PRI_MAP4 Register Field Descriptions .......................................
CPSW_PORT_P2_RX_DSCP_PRI_MAP5 Register Field Descriptions .......................................
CPSW_PORT_P2_RX_DSCP_PRI_MAP6 Register Field Descriptions .......................................
CPSW_PORT_P2_RX_DSCP_PRI_MAP7 Register Field Descriptions .......................................
15-157. CPSW_PORT_P1_TS_SEQ_MTYPE Register Field Descriptions
2433
15-158.
2434
15-159.
15-160.
15-161.
15-162.
15-163.
15-164.
15-165.
15-166.
15-167.
15-168.
15-169.
15-170.
15-171.
15-172.
15-173.
15-174.
15-175.
15-176.
15-177.
15-178.
15-179.
15-180.
15-181.
15-182.
15-183.
15-184.
15-185.
15-186.
15-187.
SPRUHL7I – April 2014 – Revised December 2019
Submit Documentation Feedback
Copyright © 2014–2019, Texas Instruments Incorporated
List of Tables
2435
2436
2437
2438
2439
2440
2441
2442
2443
2444
2445
2447
2448
2449
2450
2451
2452
2453
2454
2455
2456
2457
2458
2459
2460
2461
2462
2463
2464
109
www.ti.com
15-188. CPSW_SL Registers .................................................................................................. 2465
15-189. CPSW_SL_IDVER Register Field Descriptions.................................................................... 2466
15-190. CPSW_SL_MACCTRL Register Field Descriptions ............................................................... 2467
15-191. CPSW_SL_MACSTS Register Field Descriptions ................................................................. 2470
15-192. CPSW_SL_SOFT_RESET Register Field Descriptions .......................................................... 2471
...........................................................
CPSW_SL_BOFFTEST Register Field Descriptions ..............................................................
CPSW_SL_RX_PAUSE Register Field Descriptions .............................................................
CPSW_SL_TX_PAUSE Register Field Descriptions ..............................................................
CPSW_SL_EMCTRL Register Field Descriptions .................................................................
CPSW_SL_RX_PRI_MAP Register Field Descriptions ...........................................................
CPSW_SL_TX_GAP Register Field Descriptions .................................................................
CPSW_SS Registers ..................................................................................................
CPSW_SS_ID_VER Register Field Descriptions ..................................................................
CPSW_SS_CTRL Register Field Descriptions ....................................................................
CPSW_SS_SOFT_RESET Register Field Descriptions ..........................................................
CPSW_SS_STAT_PORT_EN Register Field Descriptions ......................................................
CPSW_SS_PTYPE Register Field Descriptions ...................................................................
CPSW_SS_SOFT_IDLE Register Field Descriptions .............................................................
CPSW_SS_THRU_RATE Register Field Descriptions ...........................................................
CPSW_SS_GAP_THRESH Register Field Descriptions .........................................................
CPSW_SS_TX_START_WDS Register Field Descriptions ......................................................
CPSW_SS_FLOW_CTRL Register Field Descriptions ...........................................................
CPSW_SS_VLAN_LTYPE Register Field Descriptions ..........................................................
CPSW_SS_TS_LTYPE Register Field Descriptions ..............................................................
CPSW_SS_DLR_LTYPE Register Field Descriptions ............................................................
CPSW_SS_STS Register Field Descriptions ......................................................................
CPSW_WR Registers .................................................................................................
CPSW_WR_IDVER Register Field Descriptions ..................................................................
CPSW_WR_SOFT_RESET Register Field Descriptions .........................................................
CPSW_WR_CTRL Register Field Descriptions ....................................................................
CPSW_WR_INT_CTRL Register Field Descriptions ..............................................................
CPSW_WR_C0_RX_THRESH_EN Register Field Descriptions ................................................
CPSW_WR_C0_RX_EN Register Field Descriptions .............................................................
CPSW_WR_C0_TX_EN Register Field Descriptions .............................................................
CPSW_WR_C0_MISC_EN Register Field Descriptions ..........................................................
CPSW_WR_C1_RX_THRESH_EN Register Field Descriptions ................................................
CPSW_WR_C1_RX_EN Register Field Descriptions .............................................................
CPSW_WR_C1_TX_EN Register Field Descriptions .............................................................
CPSW_WR_C1_MISC_EN Register Field Descriptions ..........................................................
CPSW_WR_C2_RX_THRESH_EN Register Field Descriptions ................................................
CPSW_WR_C2_RX_EN Register Field Descriptions .............................................................
CPSW_WR_C2_TX_EN Register Field Descriptions .............................................................
CPSW_WR_C2_MISC_EN Register Field Descriptions ..........................................................
CPSW_WR_C0_RX_THRESH_STAT Register Field Descriptions .............................................
CPSW_WR_C0_RX_STAT Register Field Descriptions..........................................................
CPSW_WR_C0_TX_STAT Register Field Descriptions ..........................................................
CPSW_WR_C0_MISC_STAT Register Field Descriptions.......................................................
CPSW_WR_C1_RX_THRESH_STAT Register Field Descriptions .............................................
15-193. CPSW_SL_RX_MAXLEN Register Field Descriptions
15-194.
15-195.
15-196.
15-197.
15-198.
15-199.
15-200.
15-201.
15-202.
15-203.
15-204.
15-205.
15-206.
15-207.
15-208.
15-209.
15-210.
15-211.
15-212.
15-213.
15-214.
15-215.
15-216.
15-217.
15-218.
15-219.
15-220.
15-221.
15-222.
15-223.
15-224.
15-225.
15-226.
15-227.
15-228.
15-229.
15-230.
15-231.
15-232.
15-233.
15-234.
15-235.
15-236.
110
List of Tables
2472
2473
2474
2475
2476
2477
2478
2478
2479
2480
2481
2482
2483
2484
2485
2486
2487
2488
2489
2490
2491
2492
2492
2494
2495
2496
2497
2498
2499
2500
2501
2502
2503
2504
2505
2506
2507
2508
2509
2510
2511
2512
2513
2514
SPRUHL7I – April 2014 – Revised December 2019
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Copyright © 2014–2019, Texas Instruments Incorporated
www.ti.com
15-237. CPSW_WR_C1_RX_STAT Register Field Descriptions.......................................................... 2515
15-238. CPSW_WR_C1_TX_STAT Register Field Descriptions .......................................................... 2516
15-239. CPSW_WR_C1_MISC_STAT Register Field Descriptions....................................................... 2517
15-240. CPSW_WR_C2_RX_THRESH_STAT Register Field Descriptions ............................................. 2518
15-241. CPSW_WR_C2_RX_STAT Register Field Descriptions.......................................................... 2519
15-242. CPSW_WR_C2_TX_STAT Register Field Descriptions .......................................................... 2520
15-243. CPSW_WR_C2_MISC_STAT Register Field Descriptions....................................................... 2521
15-244. CPSW_WR_C0_RX_IMAX Register Field Descriptions .......................................................... 2522
15-245. CPSW_WR_C0_TX_IMAX Register Field Descriptions .......................................................... 2523
15-246. CPSW_WR_C1_RX_IMAX Register Field Descriptions .......................................................... 2524
15-247. CPSW_WR_C1_TX_IMAX Register Field Descriptions .......................................................... 2525
15-248. CPSW_WR_C2_RX_IMAX Register Field Descriptions .......................................................... 2526
15-249. CPSW_WR_C2_TX_IMAX Register Field Descriptions .......................................................... 2527
15-250. CPSW_WR_RGMII_CTL Register Field Descriptions ............................................................ 2528
15-251. MDIO REGISTERS .................................................................................................... 2529
15-252. MDIO_VER Register Field Descriptions ............................................................................ 2530
15-253. MDIO_CTRL Register Field Descriptions ........................................................................... 2531
15-254. MDIO_ALIVE Register Field Descriptions .......................................................................... 2533
15-255. MDIO_LINK Register Field Descriptions ............................................................................ 2534
15-256. MDIO_LINKINTRAW Register Field Descriptions ................................................................. 2535
15-257. MDIO_LINKINTMASKED Register Field Descriptions ............................................................ 2536
15-258. MDIO_USERINTRAW Register Field Descriptions................................................................ 2537
15-259. MDIO_USERINTMASKED Register Field Descriptions
..........................................................
2538
15-260. MDIO_USERINTMASKSET Register Field Descriptions ......................................................... 2539
15-261. MDIO_USERINTMASKCLR Register Field Descriptions ......................................................... 2540
15-262. MDIO_USERACCESS0 Register Field Descriptions .............................................................. 2541
15-263. MDIO_USERPHYSEL0 Register Field Descriptions .............................................................. 2542
15-264. MDIO_USERACCESS1 Register Field Descriptions .............................................................. 2543
15-265. MDIO_USERPHYSEL1 Register Field Descriptions .............................................................. 2544
.........................................................................
16-1.
USB2SS Clock Sources and Clock Control
16-2.
USB Signal Pins Description........................................................................................... 2548
16-3.
USB Control, Configuration, and Monitor Signal Pins .............................................................. 2549
16-4.
Typical Use Cases In Terms of Connections ........................................................................ 2549
17-1.
Unsupported MMCSD Features ....................................................................................... 2553
17-2.
MMCSD Connectivity Attributes ....................................................................................... 2555
17-3.
MMCSD Clock Signals
17-4.
17-5.
17-6.
17-7.
17-8.
17-9.
17-10.
17-11.
17-12.
17-13.
17-14.
17-15.
17-16.
.................................................................................................
MMCSD Pin List .........................................................................................................
DAT Line Direction for Data Transfer Modes ........................................................................
ADPDATDIROQ and ADPDATDIRLS Signal States ...............................................................
MMC/SD/SDIO Controller Pins and Descriptions ...................................................................
Response Type Summary .............................................................................................
Local Power Management Features ..................................................................................
Clock Activity Settings ..................................................................................................
Events.....................................................................................................................
Memory Size, BLEN, and Buffer Relationship .......................................................................
MMC, SD, SDIO Responses in the SD_RSPxx Registers.........................................................
CC and TC Values Upon Error Detected ............................................................................
MMC/SD/SDIO Controller Transfer Stop Command Summary ...................................................
MMC/SD/SDIO Hardware Status Features ..........................................................................
SPRUHL7I – April 2014 – Revised December 2019
Submit Documentation Feedback
Copyright © 2014–2019, Texas Instruments Incorporated
List of Tables
2548
2556
2556
2556
2557
2559
2562
2567
2567
2568
2575
2576
2577
2584
2590
111
www.ti.com
2591
17-18.
2592
17-19.
17-20.
17-21.
17-22.
17-23.
17-24.
17-25.
17-26.
17-27.
17-28.
17-29.
17-30.
17-31.
17-32.
17-33.
17-34.
17-35.
17-36.
17-37.
17-38.
17-39.
17-40.
17-41.
17-42.
17-43.
17-44.
17-45.
17-46.
17-47.
17-48.
18-1.
18-2.
18-3.
18-4.
18-5.
18-6.
18-7.
18-8.
18-9.
18-10.
18-11.
18-12.
18-13.
18-14.
18-15.
18-16.
18-17.
112
.................................................................................
MMC/SD/SDIO Controller Wake-Up Configuration .................................................................
MMCSD Registers ......................................................................................................
SD_SYSCONFIG Register Field Descriptions ......................................................................
SD_SYSSTATUS Register Field Descriptions ......................................................................
SD_CSRE Register Field Descriptions ...............................................................................
SD_SYSTEST Register Field Descriptions ..........................................................................
SD_CON Register Field Descriptions ................................................................................
SD_PWCNT Register Field Descriptions ............................................................................
SD_SDMASA Register Field Descriptions ...........................................................................
SD_BLK Register Field Descriptions .................................................................................
SD_ARG Register Field Descriptions.................................................................................
SD_CMD Register Field Descriptions ................................................................................
SD_RSP10 Register Field Descriptions ..............................................................................
SD_RSP32 Register Field Descriptions ..............................................................................
SD_RSP54 Register Field Descriptions ..............................................................................
SD_RSP76 Register Field Descriptions ..............................................................................
SD_DATA Register Field Descriptions ...............................................................................
SD_PSTATE Register Field Descriptions ............................................................................
SD_HCTL Register Field Descriptions ...............................................................................
SD_SYSCTL Register Field Descriptions ............................................................................
SD_STAT Register Field Descriptions ...............................................................................
SD_IE Register Field Descriptions ....................................................................................
SD_ISE Register Field Descriptions ..................................................................................
SD_AC12 Register Field Descriptions ................................................................................
SD_CAPA Register Field Descriptions ...............................................................................
SD_CUR_CAPA Register Field Descriptions ........................................................................
SD_FE Register Field Descriptions ...................................................................................
SD_ADMAES Register Field Descriptions ...........................................................................
SD_ADMASAL Register Field Descriptions .........................................................................
SD_ADMASAH Register Field Descriptions .........................................................................
SD_REV Register Field Descriptions .................................................................................
Mailbox Connectivity Attributes ........................................................................................
Mailbox Clock Signals ..................................................................................................
Mailbox Implementation ................................................................................................
Local Power Management Features ..................................................................................
Interrupt Events ..........................................................................................................
Global Initialization of Surrounding Modules for System Mailbox .................................................
Mailbox Global Initialization ............................................................................................
Sending a Message (Polling Method) ................................................................................
Sending a Message (Interrupt Method) ..............................................................................
Receiving a Message (Polling Method) ..............................................................................
Receiving a Message (Interrupt Method) ............................................................................
Events Servicing in Sending Mode ...................................................................................
Events Servicing in Receiving Mode .................................................................................
MAILBOX REGISTERS ................................................................................................
MLB_REVISION Register Field Descriptions ........................................................................
MLB_SYSCONFIG Register Field Descriptions .....................................................................
MLB_MESSAGE_0 Register Field Descriptions ....................................................................
17-17. Global Init for Surrounding Modules
List of Tables
2596
2597
2599
2600
2601
2605
2609
2610
2611
2612
2613
2615
2616
2617
2618
2619
2620
2623
2626
2628
2633
2636
2639
2641
2643
2644
2646
2647
2648
2649
2652
2653
2654
2655
2656
2658
2659
2659
2659
2660
2660
2660
2660
2661
2662
2663
2664
SPRUHL7I – April 2014 – Revised December 2019
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Copyright © 2014–2019, Texas Instruments Incorporated
www.ti.com
18-18. MLB_MESSAGE_1 Register Field Descriptions .................................................................... 2665
18-19. MLB_MESSAGE_2 Register Field Descriptions .................................................................... 2666
18-20. MLB_MESSAGE_3 Register Field Descriptions .................................................................... 2667
18-21. MLB_MESSAGE_4 Register Field Descriptions .................................................................... 2668
18-22. MLB_MESSAGE_5 Register Field Descriptions .................................................................... 2669
18-23. MLB_MESSAGE_6 Register Field Descriptions .................................................................... 2670
18-24. MLB_MESSAGE_7 Register Field Descriptions .................................................................... 2671
18-25. MLB_FIFOSTS_0 Register Field Descriptions ...................................................................... 2672
18-26. MLB_FIFOSTS_1 Register Field Descriptions ...................................................................... 2673
18-27. MLB_FIFOSTS_2 Register Field Descriptions ...................................................................... 2674
18-28. MLB_FIFOSTS_3 Register Field Descriptions ...................................................................... 2675
18-29. MLB_FIFOSTS_4 Register Field Descriptions ...................................................................... 2676
18-30. MLB_FIFOSTS_5 Register Field Descriptions ...................................................................... 2677
18-31. MLB_FIFOSTS_6 Register Field Descriptions ...................................................................... 2678
18-32. MLB_FIFOSTS_7 Register Field Descriptions ...................................................................... 2679
18-33. MLB_MSGSTS_0 Register Field Descriptions ...................................................................... 2680
18-34. MLB_MSGSTS_1 Register Field Descriptions ...................................................................... 2681
18-35. MLB_MSGSTS_2 Register Field Descriptions ...................................................................... 2682
18-36. MLB_MSGSTS_3 Register Field Descriptions ...................................................................... 2683
18-37. MLB_MSGSTS_4 Register Field Descriptions ...................................................................... 2684
18-38. MLB_MSGSTS_5 Register Field Descriptions ...................................................................... 2685
18-39. MLB_MSGSTS_6 Register Field Descriptions ...................................................................... 2686
18-40. MLB_MSGSTS_7 Register Field Descriptions ...................................................................... 2687
18-41. MLB_IRQSTS_RAW_0 Register Field Descriptions ................................................................ 2688
18-42. MLB_IRQSTS_CLR_0 Register Field Descriptions ................................................................. 2690
18-43. MLB_IRQEN_SET_0 Register Field Descriptions .................................................................. 2692
18-44. MLB_IRQEN_CLR_0 Register Field Descriptions .................................................................. 2694
18-45. MLB_IRQSTS_RAW_1 Register Field Descriptions ................................................................ 2696
18-46. MLB_IRQSTS_CLR_1 Register Field Descriptions ................................................................. 2698
18-47. MLB_IRQEN_SET_1 Register Field Descriptions .................................................................. 2700
18-48. MLB_IRQEN_CLR_1 Register Field Descriptions .................................................................. 2702
18-49. MLB_IRQSTS_RAW_2 Register Field Descriptions ................................................................ 2704
18-50. MLB_IRQSTS_CLR_2 Register Field Descriptions ................................................................. 2706
18-51. MLB_IRQEN_SET_2 Register Field Descriptions .................................................................. 2708
18-52. MLB_IRQEN_CLR_2 Register Field Descriptions .................................................................. 2710
18-53. MLB_IRQSTS_RAW_3 Register Field Descriptions ................................................................ 2712
18-54. MLB_IRQSTS_CLR_3 Register Field Descriptions ................................................................. 2714
18-55. MLB_IRQEN_SET_3 Register Field Descriptions .................................................................. 2716
18-56. MLB_IRQEN_CLR_3 Register Field Descriptions .................................................................. 2718
18-57. SPINLOCK REGISTERS ............................................................................................... 2720
18-58. SPINLOCK_REV Register Field Descriptions ....................................................................... 2721
18-59. SPINLOCK_SYSCONFIG Register Field Descriptions............................................................. 2722
18-60. SPINLOCK_SYSTS Register Field Descriptions .................................................................... 2723
18-61. SPINLOCK_REG_0 Register Field Descriptions .................................................................... 2724
18-62. SPINLOCK_REG_1 Register Field Descriptions .................................................................... 2725
18-63. SPINLOCK_REG_2 Register Field Descriptions .................................................................... 2726
18-64. SPINLOCK_REG_3 Register Field Descriptions .................................................................... 2727
18-65. SPINLOCK_REG_4 Register Field Descriptions .................................................................... 2728
18-66. SPINLOCK_REG_5 Register Field Descriptions .................................................................... 2729
SPRUHL7I – April 2014 – Revised December 2019
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Copyright © 2014–2019, Texas Instruments Incorporated
List of Tables
113
www.ti.com
18-67. SPINLOCK_REG_6 Register Field Descriptions .................................................................... 2730
18-68. SPINLOCK_REG_7 Register Field Descriptions .................................................................... 2731
18-69. SPINLOCK_REG_8 Register Field Descriptions .................................................................... 2732
18-70. SPINLOCK_REG_9 Register Field Descriptions .................................................................... 2733
18-71. SPINLOCK_REG_10 Register Field Descriptions .................................................................. 2734
18-72. SPINLOCK_REG_11 Register Field Descriptions .................................................................. 2735
18-73. SPINLOCK_REG_12 Register Field Descriptions .................................................................. 2736
18-74. SPINLOCK_REG_13 Register Field Descriptions .................................................................. 2737
18-75. SPINLOCK_REG_14 Register Field Descriptions .................................................................. 2738
18-76. SPINLOCK_REG_15 Register Field Descriptions .................................................................. 2739
18-77. SPINLOCK_REG_16 Register Field Descriptions .................................................................. 2740
18-78. SPINLOCK_REG_17 Register Field Descriptions .................................................................. 2741
18-79. SPINLOCK_REG_18 Register Field Descriptions .................................................................. 2742
18-80. SPINLOCK_REG_19 Register Field Descriptions .................................................................. 2743
18-81. SPINLOCK_REG_20 Register Field Descriptions .................................................................. 2744
18-82. SPINLOCK_REG_21 Register Field Descriptions .................................................................. 2745
18-83. SPINLOCK_REG_22 Register Field Descriptions .................................................................. 2746
18-84. SPINLOCK_REG_23 Register Field Descriptions .................................................................. 2747
18-85. SPINLOCK_REG_24 Register Field Descriptions .................................................................. 2748
18-86. SPINLOCK_REG_25 Register Field Descriptions .................................................................. 2749
18-87. SPINLOCK_REG_26 Register Field Descriptions .................................................................. 2750
18-88. SPINLOCK_REG_27 Register Field Descriptions .................................................................. 2751
18-89. SPINLOCK_REG_28 Register Field Descriptions .................................................................. 2752
18-90. SPINLOCK_REG_29 Register Field Descriptions .................................................................. 2753
18-91. SPINLOCK_REG_30 Register Field Descriptions .................................................................. 2754
18-92. SPINLOCK_REG_31 Register Field Descriptions .................................................................. 2755
19-1.
Timer Resolution and Maximum Range .............................................................................. 2758
19-2.
Timer[0] Connectivity Attributes ....................................................................................... 2761
19-3.
Timer[2–11] Connectivity Attributes ................................................................................... 2762
19-4.
Timer[0, 2-7] Clock Signals ............................................................................................ 2763
19-5.
Timer[8-11] Clock Signals .............................................................................................. 2763
19-6.
Timer Pin List ............................................................................................................ 2763
19-7.
Prescaler Functionality
19-8.
Prescaler Clock Ratios Value .......................................................................................... 2769
19-9.
Value and Corresponding Interrupt Period ........................................................................... 2769
.................................................................................................
2766
19-10. OCP Error Reporting .................................................................................................... 2770
19-11. DMTIMER Registers .................................................................................................... 2775
19-12. DMTIMER_TIDR Register Field Descriptions ....................................................................... 2777
19-13. DMTIMER_TIOCP_CFG Register Field Descriptions .............................................................. 2778
19-14. DMTIMER_IRQ_EOI Register Field Descriptions................................................................... 2779
19-15. DMTIMER_IRQSTS_RAW Register Field Descriptions ............................................................ 2780
19-16. DMTIMER_IRQSTS Register Field Descriptions
...................................................................
2781
19-17. DMTIMER_IRQEN_SET Register Field Descriptions .............................................................. 2782
19-18. DMTIMER_IRQEN_CLR Register Field Descriptions .............................................................. 2783
19-19. DMTIMER_IRQWAKEEN Register Field Descriptions ............................................................. 2784
2785
19-21.
2787
19-22.
19-23.
114
......................................................................
DMTIMER_TCRR Register Field Descriptions ......................................................................
DMTIMER_TLDR Register Field Descriptions ......................................................................
DMTIMER_TTGR Register Field Descriptions ......................................................................
19-20. DMTIMER_TCLR Register Field Descriptions
List of Tables
2788
2789
SPRUHL7I – April 2014 – Revised December 2019
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Copyright © 2014–2019, Texas Instruments Incorporated
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19-24. DMTIMER_TWPS Register Field Descriptions ...................................................................... 2790
19-25. DMTIMER_TMAR Register Field Descriptions ...................................................................... 2791
19-26. DMTIMER_TCAR1 Register Field Descriptions ..................................................................... 2792
.....................................................................
DMTIMER_TCAR2 Register Field Descriptions .....................................................................
Timer1 Connectivity Attributes .........................................................................................
Timer Clock Signals .....................................................................................................
Timer Pin List ............................................................................................................
Value Loaded in TCRR to Generate 1ms Tick ......................................................................
Prescaler/Timer Reload Values Versus Contexts ...................................................................
SmartIdle - Clock Activity Field Configuration .......................................................................
Prescaler Clock Ratios Value ..........................................................................................
Value and Corresponding Interrupt Period ...........................................................................
DMTIMER_1MS Registers .............................................................................................
DMTIMER_1MS_TIDR Register Field Descriptions ................................................................
DMTIMER_1MS_TIOCP_CFG Register Field Descriptions .......................................................
DMTIMER_1MS_TISTAT Register Field Descriptions .............................................................
DMTIMER_1MS_TISR Register Field Descriptions ................................................................
DMTIMER_1MS_TIER Register Field Descriptions ................................................................
DMTIMER_1MS_TWER Register Field Descriptions...............................................................
DMTIMER_1MS_TCLR Register Field Descriptions ...............................................................
DMTIMER_1MS_TCRR Register Field Descriptions ...............................................................
DMTIMER_1MS_TLDR Register Field Descriptions ...............................................................
DMTIMER_1MS_TTGR Register Field Descriptions ...............................................................
DMTIMER_1MS_TWPS Register Field Descriptions ...............................................................
DMTIMER_1MS_TMAR Register Field Descriptions ...............................................................
DMTIMER_1MS_TCAR1 Register Field Descriptions ..............................................................
DMTIMER_1MS_TSICR Register Field Descriptions ..............................................................
DMTIMER_1MS_TCAR2 Register Field Descriptions ..............................................................
DMTIMER_1MS_TPIR Register Field Descriptions ................................................................
DMTIMER_1MS_TNIR Register Field Descriptions ................................................................
DMTIMER_1MS_TCVR Register Field Descriptions ...............................................................
DMTIMER_1MS_TOCR Register Field Descriptions ...............................................................
DMTIMER_1MS_TOWR Register Field Descriptions ..............................................................
Unsupported timer_32k Features .....................................................................................
timer_32k Connectivity Attributes .....................................................................................
SyncTimer32K Clock Signals ..........................................................................................
SyncTimer32K Pin List .................................................................................................
SYNCTIMER Registers .................................................................................................
SYNCTIMER32K_SYNCNT_REV Register Field Descriptions ...................................................
SYNCTIMER32K_SYSCONFIG Register Field Descriptions......................................................
SYNCTIMER32K_CR Register Field Descriptions..................................................................
RTC Module Connectivity Attributes ..................................................................................
RTC Clock Signals ......................................................................................................
RTC Pin List..............................................................................................................
RTC Signals..............................................................................................................
Interrupt Trigger Events ................................................................................................
RTC Register Names and Values .....................................................................................
pmic_power_en Description ...........................................................................................
19-27. DMTIMER_TSICR Register Field Descriptions
2793
19-28.
2794
19-29.
19-30.
19-31.
19-32.
19-33.
19-34.
19-35.
19-36.
19-37.
19-38.
19-39.
19-40.
19-41.
19-42.
19-43.
19-44.
19-45.
19-46.
19-47.
19-48.
19-49.
19-50.
19-51.
19-52.
19-53.
19-54.
19-55.
19-56.
19-57.
19-58.
19-59.
19-60.
19-61.
19-62.
19-63.
19-64.
19-65.
19-66.
19-67.
19-68.
19-69.
19-70.
19-71.
19-72.
SPRUHL7I – April 2014 – Revised December 2019
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Copyright © 2014–2019, Texas Instruments Incorporated
List of Tables
2797
2798
2798
2800
2803
2805
2806
2807
2807
2809
2810
2811
2812
2813
2814
2815
2817
2818
2819
2820
2822
2823
2824
2825
2826
2827
2828
2829
2830
2831
2832
2832
2833
2835
2836
2837
2838
2840
2841
2841
2843
2843
2846
2849
115
www.ti.com
19-73. RTC Registers ........................................................................................................... 2850
19-74. RTCSS_SECONDS_REG Register Field Descriptions ............................................................ 2852
19-75. RTCSS_MINUTES_REG Register Field Descriptions
.............................................................
2853
19-76. RTCSS_HOURS_REG Register Field Descriptions ................................................................ 2854
19-77. RTCSS_DAYS_REG Register Field Descriptions .................................................................. 2855
19-78. RTCSS_MONTHS_REG Register Field Descriptions .............................................................. 2856
19-79. RTCSS_YEARS_REG Register Field Descriptions
................................................................
2857
19-80. RTCSS_WEEKS_REG Register Field Descriptions ................................................................ 2858
.................................................
19-82. RTCSS_ALARM_MINUTES_REG Register Field Descriptions ...................................................
19-83. RTCSS_ALARM_HOURS_REG Register Field Descriptions .....................................................
19-84. RTCSS_ALARM_DAYS_REG Register Field Descriptions .......................................................
19-85. RTCSS_ALARM_MONTHS_REG Register Field Descriptions ...................................................
19-86. RTCSS_ALARM_YEARS_REG Register Field Descriptions ......................................................
19-87. RTCSS_CTRL_REG Register Field Descriptions...................................................................
19-88. RTCSS_STS_REG Register Field Descriptions ....................................................................
19-89. RTCSS_INTRS_REG Register Field Descriptions..................................................................
19-90. RTCSS_COMP_LSB_REG Register Field Descriptions ...........................................................
19-91. RTCSS_COMP_MSB_REG Register Field Descriptions ..........................................................
19-92. RTCSS_OSC_REG Register Field Descriptions ....................................................................
19-93. RTCSS_SCRATCH0_REG Register Field Descriptions ...........................................................
19-94. RTCSS_SCRATCH1_REG Register Field Descriptions ...........................................................
19-95. RTCSS_SCRATCH2_REG Register Field Descriptions ...........................................................
19-96. RTCSS_KICK0R Register Field Descriptions .......................................................................
19-97. RTCSS_KICK1R Register Field Descriptions .......................................................................
19-98. RTCSS_REVISION Register Field Descriptions ....................................................................
19-99. RTCSS_SYSCONFIG Register Field Descriptions .................................................................
19-100. RTCSS_IRQWAKEEN Register Field Descriptions ...............................................................
19-101. RTCSS_ALARM2_SECONDS_REG Register Field Descriptions ...............................................
19-102. RTCSS_ALARM2_MINUTES_REG Register Field Descriptions ................................................
19-103. RTCSS_ALARM2_HOURS_REG Register Field Descriptions ..................................................
19-104. RTCSS_ALARM2_DAYS_REG Register Field Descriptions .....................................................
19-105. RTCSS_ALARM2_MONTHS_REG Register Field Descriptions ................................................
19-106. RTCSS_ALARM2_YEARS_REG Register Field Descriptions ...................................................
19-107. RTCSS_PMIC Register Field Descriptions .........................................................................
19-108. RTCSS_DEBOUNCE Register Field Descriptions ................................................................
19-109. Public WD Timer Module Connectivity Attributes ..................................................................
19-110. Public WD Timer Clock Signals ......................................................................................
19-111. Watchdog Timer Events ..............................................................................................
19-112. Count and Prescaler Default Reset Values ........................................................................
19-113. Prescaler Clock Ratio Values ........................................................................................
19-114. Reset Period Examples ...............................................................................................
19-115. Default Watchdog Timer Reset Periods ............................................................................
19-116. Global Initialization of Surrounding Modules .......................................................................
19-117. Watchdog Timer Module Global Initialization ......................................................................
19-118. Watchdog Timer Basic Configuration ...............................................................................
19-119. Disable the Watchdog Timer .........................................................................................
19-120. Enable the Watchdog Timer ..........................................................................................
19-121. WDT Registers .........................................................................................................
19-81. RTCSS_ALARM_SECONDS_REG Register Field Descriptions
116
List of Tables
2859
2860
2861
2862
2863
2864
2865
2867
2868
2869
2870
2871
2872
2873
2874
2875
2876
2877
2878
2879
2880
2881
2882
2883
2884
2885
2886
2887
2889
2890
2891
2892
2893
2893
2894
2897
2897
2897
2898
2898
2898
SPRUHL7I – April 2014 – Revised December 2019
Submit Documentation Feedback
Copyright © 2014–2019, Texas Instruments Incorporated
www.ti.com
...........................................................................
19-123. WDT_WDSC Register Field Descriptions ..........................................................................
19-124. WDT_WDST Register Field Descriptions ...........................................................................
19-125. WDT_WISR Register Field Descriptions............................................................................
19-126. WDT_WIER Register Field Descriptions............................................................................
19-127. WDT_WCLR Register Field Descriptions ...........................................................................
19-128. WDT_WCRR Register Field Descriptions ..........................................................................
19-129. WDT_WLDR Register Field Descriptions ...........................................................................
19-130. WDT_WTGR Register Field Descriptions ..........................................................................
19-131. WDT_WWPS Register Field Descriptions ..........................................................................
19-132. WDT_WDLY Register Field Descriptions ...........................................................................
19-133. WDT_WSPR Register Field Descriptions ..........................................................................
19-134. WDT_WIRQSTATRAW Register Field Descriptions ..............................................................
19-135. WDT_WIRQSTAT Register Field Descriptions ....................................................................
19-136. WDT_WIRQENSET Register Field Descriptions ..................................................................
19-137. WDT_WIRQENCLR Register Field Descriptions ..................................................................
20-1. Unsupported Features ..................................................................................................
20-2. PWMSS Connectivity Attributes .......................................................................................
20-3. PWMSS Clock Signals .................................................................................................
20-4. PWMSS Pin List .........................................................................................................
20-5. PWMSS Registers ......................................................................................................
20-6. IDVER Register Field Descriptions ...................................................................................
20-7. SYSCONFIG Register Field Descriptions ............................................................................
20-8. CLKCONFIG Register Field Descriptions ............................................................................
20-9. CLKSTATUS Register Field Descriptions ............................................................................
20-10. Submodule Configuration Parameters................................................................................
20-11. Time-Base Submodule Registers .....................................................................................
20-12. Key Time-Base Signals .................................................................................................
20-13. Counter-Compare Submodule Registers ............................................................................
20-14. Counter-Compare Submodule Key Signals ..........................................................................
20-15. Action-Qualifier Submodule Registers ................................................................................
20-16. Action-Qualifier Submodule Possible Input Events .................................................................
20-17. Action-Qualifier Event Priority for Up-Down-Count Mode ..........................................................
20-18. Action-Qualifier Event Priority for Up-Count Mode..................................................................
20-19. Action-Qualifier Event Priority for Down-Count Mode ..............................................................
20-20. Behavior if CMPA/CMPB is Greater than the Period ...............................................................
20-21. EPWMx Initialization for ...............................................................................................
20-22. EPWMx Run Time Changes for ......................................................................................
20-23. EPWMx Initialization for ...............................................................................................
20-24. EPWMx Run Time Changes for ......................................................................................
20-25. EPWMx Initialization for ...............................................................................................
20-26. EPWMx Run Time Changes for ......................................................................................
20-27. EPWMx Initialization for ...............................................................................................
20-28. EPWMx Run Time Changes for ......................................................................................
20-29. EPWMx Initialization for ...............................................................................................
20-30. EPWMx Run Time Changes for ......................................................................................
20-31. EPWMx Initialization for ...............................................................................................
20-32. EPWMx Run Time Changes for ......................................................................................
20-33. Dead-Band Generator Submodule Registers........................................................................
19-122. WDT_WIDR Register Field Descriptions
SPRUHL7I – April 2014 – Revised December 2019
Submit Documentation Feedback
Copyright © 2014–2019, Texas Instruments Incorporated
List of Tables
2899
2900
2901
2902
2903
2904
2905
2906
2907
2908
2909
2910
2911
2912
2913
2914
2917
2920
2920
2920
2921
2922
2923
2924
2925
2930
2935
2936
2944
2944
2948
2949
2951
2951
2951
2952
2955
2955
2957
2957
2959
2959
2961
2961
2963
2963
2965
2965
2966
117
www.ti.com
2968
20-35.
2970
20-36.
20-37.
20-38.
20-39.
20-40.
20-41.
20-42.
20-43.
20-44.
20-45.
20-46.
20-47.
20-48.
20-49.
20-50.
20-51.
20-52.
20-53.
20-54.
20-55.
20-56.
20-57.
20-58.
20-59.
20-60.
20-61.
20-62.
20-63.
20-64.
20-65.
20-66.
20-67.
20-68.
20-69.
20-70.
20-71.
20-72.
20-73.
20-74.
20-75.
20-76.
20-77.
20-78.
20-79.
20-80.
20-81.
20-82.
118
.............................................................................
PWM-Chopper Submodule Registers ................................................................................
Trip-Zone Submodule Registers ......................................................................................
Possible Actions On a Trip Event .....................................................................................
Event-Trigger Submodule Registers .................................................................................
Resolution for PWM and HRPWM ....................................................................................
HRPWM Submodule Registers ........................................................................................
Relationship Between MEP Steps, PWM Frequency and Resolution ............................................
CMPA vs Duty (left), and [CMPA:CMPAHR] vs Duty (right).......................................................
EPWM1 Initialization for ...............................................................................................
EPWM2 Initialization for ...............................................................................................
EPWM3 Initialization for ...............................................................................................
EPWM1 Initialization for ...............................................................................................
EPWM2 Initialization for ...............................................................................................
EPWM1 Initialization for ...............................................................................................
EPWM2 Initialization for ...............................................................................................
EPWM1 Initialization for ...............................................................................................
EPWM2 Initialization for ...............................................................................................
EPWM3 Initialization for ...............................................................................................
EPWM1 Initialization for ...............................................................................................
EPWM2 Initialization for ...............................................................................................
EPWM3 Initialization for ...............................................................................................
EPWM1 Initialization for ...............................................................................................
EPWM2 Initialization for ...............................................................................................
PWMSS_EPWM Registers ............................................................................................
TBCTL Register Field Descriptions ...................................................................................
TBSTS Register Field Descriptions ...................................................................................
TBPHSHR Register Field Descriptions ...............................................................................
TBPHS Register Field Descriptions ...................................................................................
TBCNT Register Field Descriptions ...................................................................................
TBPRD Register Field Descriptions ..................................................................................
CMPCTL Register Field Descriptions.................................................................................
CMPAHR Register Field Descriptions ................................................................................
CMPA Register Field Descriptions ....................................................................................
CMPB Register Field Descriptions ....................................................................................
AQCTLA Register Field Descriptions .................................................................................
AQCTLB Register Field Descriptions .................................................................................
AQSFRC Register Field Descriptions ................................................................................
AQCSFRC Register Field Descriptions ..............................................................................
DBCTL Register Field Descriptions ...................................................................................
DBRED Register Field Descriptions ..................................................................................
DBFED Register Field Descriptions ..................................................................................
TZSEL Register Field Descriptions ...................................................................................
TZCTL Register Field Descriptions ...................................................................................
TZEINT Register Field Descriptions ..................................................................................
TZFLG Register Field Descriptions ...................................................................................
TZCLR Register Field Descriptions ...................................................................................
TZFRC Register Field Descriptions ...................................................................................
ETSEL Register Field Descriptions ...................................................................................
20-34. Classical Dead-Band Operating Modes
List of Tables
2975
2976
2978
2983
2984
2985
2986
2994
2994
2994
2997
2997
3000
3000
3003
3003
3004
3009
3009
3010
3013
3013
3014
3015
3017
3018
3019
3020
3021
3022
3024
3025
3026
3027
3029
3031
3032
3033
3035
3036
3037
3038
3039
3040
3041
3042
3043
SPRUHL7I – April 2014 – Revised December 2019
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Copyright © 2014–2019, Texas Instruments Incorporated
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20-83. ETPS Register Field Descriptions..................................................................................... 3044
20-84. ETFLG Register Field Descriptions ................................................................................... 3045
20-85. ETCLR Register Field Descriptions ................................................................................... 3046
20-86. ETFRC Register Field Descriptions ................................................................................... 3047
20-87. PCCTL Register Field Descriptions ................................................................................... 3048
20-88. HRCTL Register Field Descriptions ................................................................................... 3049
20-89. ECAP Initialization for CAP Mode Absolute Time, Rising Edge Trigger ......................................... 3062
20-90. ECAP Initialization for CAP Mode Absolute Time, Rising and Falling Edge Trigger ........................... 3064
20-91. ECAP Initialization for CAP Mode Delta Time, Rising Edge Trigger ............................................. 3066
20-92. ECAP Initialization for CAP Mode Delta Time, Rising and Falling Edge Triggers .............................. 3068
20-93. ECAP Initialization for APWM Mode .................................................................................. 3070
20-94. ECAP1 Initialization for Multichannel PWM Generation with Synchronization .................................. 3072
20-95. ECAP2 Initialization for Multichannel PWM Generation with Synchronization .................................. 3072
20-96. ECAP3 Initialization for Multichannel PWM Generation with Synchronization .................................. 3072
20-97. ECAP4 Initialization for Multichannel PWM Generation with Synchronization .................................. 3072
20-98. ECAP1 Initialization for Multichannel PWM Generation with Phase Control .................................... 3075
20-99. ECAP2 Initialization for Multichannel PWM Generation with Phase Control .................................... 3075
20-100. ECAP3 Initialization for Multichannel PWM Generation with Phase Control ................................... 3075
20-101. PWMSS_ECAP Registers ............................................................................................ 3076
20-102. TSCTR Register Field Descriptions ................................................................................. 3077
20-103. CTRPHS Register Field Descriptions ............................................................................... 3078
20-104. CAP1 Register Field Descriptions ................................................................................... 3079
20-105. CAP2 Register Field Descriptions ................................................................................... 3080
20-106. CAP3 Register Field Descriptions ................................................................................... 3081
20-107. CAP4 Register Field Descriptions ................................................................................... 3082
20-108. ECCTL1 Register Field Descriptions ................................................................................ 3083
20-109. ECCTL2 Register Field Descriptions ................................................................................ 3085
20-110. ECEINT Register Field Descriptions
................................................................................
3087
20-111. ECFLG Register Field Descriptions ................................................................................. 3088
20-112. ECCLR Register Field Descriptions ................................................................................. 3089
20-113. ECFRC Register Field Descriptions ................................................................................. 3090
20-114. REVID Register Field Descriptions .................................................................................. 3091
20-115. Quadrature Decoder Truth Table
...................................................................................
3098
20-116. PWMSS_EQEP REGISTERS ........................................................................................ 3113
20-117. QPOSCNT Register Field Descriptions ............................................................................. 3114
.............................................................................
QPOSMAX Register Field Descriptions.............................................................................
QPOSCMP Register Field Descriptions ............................................................................
QPOSILAT Register Field Descriptions .............................................................................
QPOSSLAT Register Field Descriptions ............................................................................
QPOSLAT Register Field Descriptions .............................................................................
QUTMR Register Field Descriptions ................................................................................
QUPRD Register Field Descriptions ................................................................................
QWDTMR Register Field Descriptions ..............................................................................
QWDPRD Register Field Descriptions ..............................................................................
QDECCTL Register Field Descriptions .............................................................................
QEPCTL Register Field Descriptions ...............................................................................
QCAPCTL Register Field Descriptions .............................................................................
QPOSCTL Register Field Descriptions .............................................................................
20-118. QPOSINIT Register Field Descriptions
3115
20-119.
3116
20-120.
20-121.
20-122.
20-123.
20-124.
20-125.
20-126.
20-127.
20-128.
20-129.
20-130.
20-131.
SPRUHL7I – April 2014 – Revised December 2019
Submit Documentation Feedback
Copyright © 2014–2019, Texas Instruments Incorporated
List of Tables
3117
3118
3119
3120
3121
3122
3123
3124
3125
3126
3128
3129
119
www.ti.com
20-132. QEINT Register Field Descriptions .................................................................................. 3130
20-133. QFLG Register Field Descriptions ................................................................................... 3131
20-134. QCLR Register Field Descriptions ................................................................................... 3132
20-135. QFRC Register Field Descriptions................................................................................... 3133
20-136. QEPSTS Register Field Descriptions ............................................................................... 3134
................................................................................
20-138. QCPRD Register Field Descriptions ................................................................................
20-139. QCTMRLAT Register Field Descriptions ...........................................................................
20-140. QCPRDLAT Register Field Descriptions............................................................................
20-141. REVID Register Field Descriptions ..................................................................................
21-1. Unsupported UART Features ..........................................................................................
21-2. UART0 Connectivity Attributes ........................................................................................
21-3. UART1–5 Connectivity Attributes .....................................................................................
21-4. UART0 Clock Signals ...................................................................................................
21-5. UART1–5 Clock Signals ................................................................................................
21-6. UART Mode Baud and Error Rates ...................................................................................
21-7. IrDA Mode Baud and Error Rates .....................................................................................
21-8. UART Pin List ............................................................................................................
21-9. UART Muxing Control ..................................................................................................
21-10. Local Power-Management Features ..................................................................................
21-11. UART Mode Interrupts ..................................................................................................
21-12. IrDA Mode Interrupts ....................................................................................................
21-13. CIR Mode Interrupts ....................................................................................................
21-14. TX FIFO Trigger Level Setting Summary ............................................................................
21-15. RX FIFO Trigger Level Setting Summary ............................................................................
21-16. UART/IrDA/CIR Register Access Mode Programming (Using UART_LCR) ....................................
21-17. Subconfiguration Mode A Summary ..................................................................................
21-18. Subconfiguration Mode B Summary ..................................................................................
21-19. Suboperational Mode Summary .......................................................................................
21-20. UART/IrDA/CIR Register Access Mode Overview ..................................................................
21-21. UART Mode Selection ..................................................................................................
21-22. UART Mode Register Overview ......................................................................................
21-23. IrDA Mode Register Overview ........................................................................................
21-24. CIR Mode Register Overview .........................................................................................
21-25. UART Baud Rate Settings (48-MHz Clock) ..........................................................................
21-26. UART Parity Bit Encoding ..............................................................................................
21-27. UART_EFR[3:0] Software Flow Control Options ....................................................................
21-28. IrDA Baud Rate Settings ...............................................................................................
21-29. UART Registers .........................................................................................................
21-30. UART_THR Register Field Descriptions .............................................................................
21-31. UART_RHR Register Field Descriptions .............................................................................
21-32. UART_DLL Register Field Descriptions ..............................................................................
21-33. UART_IER_IRDA Register Field Descriptions ......................................................................
21-34. UART_IER_CIR Register Field Descriptions ........................................................................
21-35. UART_IER Register Field Descriptions ..............................................................................
21-36. UART_DLH Register Field Descriptions .............................................................................
21-37. UART_EFR Register Field Descriptions .............................................................................
21-38. UART_IIR Register Field Descriptions ...............................................................................
21-39. UART_IIR_CIR Register Field Descriptions .........................................................................
20-137. QCTMR Register Field Descriptions
120
List of Tables
3135
3136
3137
3138
3139
3142
3143
3144
3144
3144
3145
3145
3146
3146
3150
3150
3151
3152
3154
3154
3161
3162
3162
3162
3162
3163
3164
3165
3166
3169
3169
3170
3180
3199
3201
3202
3203
3204
3205
3206
3207
3208
3210
3211
SPRUHL7I – April 2014 – Revised December 2019
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Copyright © 2014–2019, Texas Instruments Incorporated
www.ti.com
21-40. UART_FCR Register Field Descriptions ............................................................................. 3212
21-41. UART_LCR Register Field Descriptions
.............................................................................
3213
21-42. UART_MCR Register Field Descriptions ............................................................................. 3214
21-43. UART_XON1_ADDR1 Register Field Descriptions ................................................................. 3215
21-44. UART_XON2_ADDR2 Register Field Descriptions ................................................................. 3216
.......................................................................
UART_LSR_IRDA Register Field Descriptions......................................................................
UART_LSR Register Field Descriptions..............................................................................
UART_TCR Register Field Descriptions .............................................................................
UART_MSR Register Field Descriptions .............................................................................
UART_XOFF1 Register Field Descriptions ..........................................................................
UART_SPR Register Field Descriptions .............................................................................
UART_TLR Register Field Descriptions ..............................................................................
UART_XOFF2 Register Field Descriptions ..........................................................................
UART_MDR1 Register Field Descriptions ...........................................................................
UART_MDR2 Register Field Descriptions ...........................................................................
UART_TXFLL Register Field Descriptions ...........................................................................
UART_SFLSR Register Field Descriptions ..........................................................................
UART_RESUME Register Field Descriptions .......................................................................
UART_TXFLH Register Field Descriptions ..........................................................................
UART_RXFLL Register Field Descriptions ..........................................................................
UART_SFREGL Register Field Descriptions ........................................................................
UART_SFREGH Register Field Descriptions........................................................................
UART_RXFLH Register Field Descriptions ..........................................................................
UART_BLR Register Field Descriptions..............................................................................
UART_UASR Register Field Descriptions ...........................................................................
UART_ACREG Register Field Descriptions .........................................................................
UART_SCR Register Field Descriptions .............................................................................
UART_SSR Register Field Descriptions .............................................................................
UART_EBLR Register Field Descriptions ............................................................................
UART_MVR Register Field Descriptions .............................................................................
UART_SYSC Register Field Descriptions ...........................................................................
UART_SYSS Register Field Descriptions............................................................................
UART_WER Register Field Descriptions ............................................................................
UART_CFPS Register Field Descriptions............................................................................
UART_RXFIFO_LVL Register Field Descriptions...................................................................
UART_TXFIFO_LVL Register Field Descriptions ...................................................................
UART_IER2 Register Field Descriptions .............................................................................
UART_ISR2 Register Field Descriptions .............................................................................
UART_FREQ_SEL Register Field Descriptions .....................................................................
UART_MDR3 Register Field Descriptions ...........................................................................
UART_TX_DMA_THR Register Field Descriptions .................................................................
Unsupported I2C Features .............................................................................................
I2C0 Connectivity Attributes ...........................................................................................
I2C(1–2) Connectivity Attributes.......................................................................................
I2C Clock Signals .......................................................................................................
I2C Pin List ...............................................................................................................
Signal Pads ..............................................................................................................
Reset State of I2C Signals .............................................................................................
21-45. UART_LSR_CIR Register Field Descriptions
3217
21-46.
3218
21-47.
21-48.
21-49.
21-50.
21-51.
21-52.
21-53.
21-54.
21-55.
21-56.
21-57.
21-58.
21-59.
21-60.
21-61.
21-62.
21-63.
21-64.
21-65.
21-66.
21-67.
21-68.
21-69.
21-70.
21-71.
21-72.
21-73.
21-74.
21-75.
21-76.
21-77.
21-78.
21-79.
21-80.
21-81.
22-1.
22-2.
22-3.
22-4.
22-5.
22-6.
22-7.
SPRUHL7I – April 2014 – Revised December 2019
Submit Documentation Feedback
Copyright © 2014–2019, Texas Instruments Incorporated
List of Tables
3219
3221
3222
3223
3224
3225
3226
3227
3228
3229
3230
3231
3232
3233
3234
3235
3236
3237
3238
3239
3240
3241
3242
3243
3244
3245
3246
3247
3248
3249
3250
3251
3252
3253
3254
3256
3257
3258
3258
3258
3260
3260
121
www.ti.com
22-8.
22-9.
22-10.
22-11.
22-12.
22-13.
22-14.
22-15.
22-16.
22-17.
22-18.
22-19.
22-20.
22-21.
22-22.
22-23.
22-24.
22-25.
22-26.
22-27.
22-28.
22-29.
22-30.
22-31.
22-32.
22-33.
22-34.
22-35.
22-36.
22-37.
22-38.
22-39.
23-1.
23-2.
23-3.
23-4.
23-5.
23-6.
23-7.
23-8.
23-9.
23-10.
23-11.
23-12.
23-13.
23-14.
23-15.
23-16.
24-1.
122
............................................................................................................
I2C_REVNB_LO Register Field Descriptions........................................................................
I2C_REVNB_HI Register Field Descriptions ........................................................................
I2C_SYSC Register Field Descriptions...............................................................................
I2C_IRQSTS_RAW Register Field Descriptions ....................................................................
I2C_IRQSTS Register Field Descriptions ............................................................................
I2C_IRQEN_SET Register Field Descriptions .......................................................................
I2C_IRQEN_CLR Register Field Descriptions ......................................................................
I2C_WE Register Field Descriptions..................................................................................
I2C_DMARXEN_SET Register Field Descriptions ..................................................................
I2C_DMATXEN_SET Register Field Descriptions ..................................................................
I2C_DMARXEN_CLR Register Field Descriptions..................................................................
I2C_DMATXEN_CLR Register Field Descriptions ..................................................................
I2C_DMARXWAKE_EN Register Field Descriptions ...............................................................
I2C_DMATXWAKE_EN Register Field Descriptions ...............................................................
I2C_SYSS Register Field Descriptions ...............................................................................
I2C_BUF Register Field Descriptions.................................................................................
I2C_CNT Register Field Descriptions ................................................................................
I2C_DATA Register Field Descriptions ...............................................................................
I2C_CON Register Field Descriptions ................................................................................
I2C_OA Register Field Descriptions ..................................................................................
I2C_SA Register Field Descriptions ..................................................................................
I2C_PSC Register Field Descriptions ................................................................................
I2C_SCLL Register Field Descriptions ...............................................................................
I2C_SCLH Register Field Descriptions ...............................................................................
I2C_SYSTEST Register Field Descriptions ..........................................................................
I2C_BUFSTAT Register Field Descriptions ..........................................................................
I2C_OA1 Register Field Descriptions.................................................................................
I2C_OA2 Register Field Descriptions.................................................................................
I2C_OA3 Register Field Descriptions.................................................................................
I2C_ACTOA Register Field Descriptions .............................................................................
I2C_SBLOCK Register Field Descriptions ...........................................................................
HDQ1W Connectivity Attributes .......................................................................................
HDQ1W Clock Signals..................................................................................................
HDQ1W Pin List .........................................................................................................
I/O Description ...........................................................................................................
HDQ/1-Wire Command Byte ...........................................................................................
Registers Print for HDQ/1-Wire Configuration .......................................................................
Registers Print for HDQ/1-Wire Software Reset ....................................................................
Registers Print for HDQ/1-Wire Interrupts Enable ..................................................................
HDQ1W REGISTERS ..................................................................................................
HDQ1W_REVISION Register Field Descriptions ...................................................................
HDQ1W_TX_DATA Register Field Descriptions ....................................................................
HDQ1W_RX_DATA Register Field Descriptions ....................................................................
HDQ1W_CTRL_STS Register Field Descriptions ..................................................................
HDQ1W_INT_STS Register Field Descriptions .....................................................................
HDQ1W_SYSCONFIG Register Field Descriptions ................................................................
HDQ1W_SYSSTS Register Field Descriptions .....................................................................
Unsupported McASP Features ........................................................................................
I2C Registers
List of Tables
3272
3274
3275
3276
3278
3284
3286
3288
3290
3293
3294
3295
3296
3297
3299
3301
3302
3304
3305
3306
3309
3310
3311
3312
3313
3314
3318
3319
3320
3321
3322
3323
3327
3327
3328
3329
3331
3343
3343
3344
3344
3345
3346
3347
3348
3349
3350
3351
3354
SPRUHL7I – April 2014 – Revised December 2019
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Copyright © 2014–2019, Texas Instruments Incorporated
www.ti.com
24-2.
McASP Connectivity Attributes ........................................................................................ 3355
24-3.
McASP Clock Signals................................................................................................... 3356
24-4.
McASP Pin List .......................................................................................................... 3356
24-5.
Biphase-Mark Encoder ................................................................................................. 3363
24-6.
Preamble Codes ......................................................................................................... 3364
24-7.
McASP Interface Signals ............................................................................................... 3371
24-8.
Channel Status and User Data for Each DIT Block
24-9.
Transmit Bitstream Data Alignment ................................................................................... 3389
................................................................
3378
24-10. Receive Bitstream Data Alignment.................................................................................... 3391
24-11. MCASP REGISTERS ................................................................................................... 3410
24-12. MCASP_REV Register Field Descriptions ........................................................................... 3412
24-13. MCASP_PWRIDLESYSCONFIG Register Field Descriptions .................................................... 3413
24-14. MCASP_PFUNC Register Field Descriptions ....................................................................... 3414
24-15. MCASP_PDIR Register Field Descriptions .......................................................................... 3415
24-16. MCASP_PDOUT Register Field Descriptions ....................................................................... 3417
24-17. MCASP_PDIN Register Field Descriptions .......................................................................... 3419
24-18. MCASP_PDCLR Register Field Descriptions
.......................................................................
3420
24-19. MCASP_GBLCTL Register Field Descriptions ...................................................................... 3422
24-20. MCASP_AMUTE Register Field Descriptions ....................................................................... 3424
24-21. MCASP_DLBCTL Register Field Descriptions ...................................................................... 3426
24-22. MCASP_DITCTL Register Field Descriptions ....................................................................... 3427
24-23. MCASP_RGBLCTL Register Field Descriptions .................................................................... 3428
24-24. MCASP_RMASK Register Field Descriptions ....................................................................... 3430
24-25. MCASP_RFMT Register Field Descriptions ......................................................................... 3431
24-26. MCASP_AFSRCTL Register Field Descriptions .................................................................... 3433
..................................................................
MCASP_AHCLKRCTL Register Field Descriptions ................................................................
MCASP_RTDM Register Field Descriptions .........................................................................
MCASP_RINTCTL Register Field Descriptions .....................................................................
MCASP_RSTAT Register Field Descriptions ........................................................................
MCASP_RSLOT Register Field Descriptions........................................................................
MCASP_RCLKCHK Register Field Descriptions ....................................................................
MCASP_REVTCTL Register Field Descriptions ....................................................................
MCASP_XGBLCTL Register Field Descriptions ....................................................................
MCASP_XMASK Register Field Descriptions .......................................................................
MCASP_XFMT Register Field Descriptions .........................................................................
MCASP_AFSXCTL Register Field Descriptions ....................................................................
MCASP_ACLKXCTL Register Field Descriptions...................................................................
MCASP_AHCLKXCTL Register Field Descriptions .................................................................
MCASP_XTDM Register Field Descriptions .........................................................................
MCASP_XINTCTL Register Field Descriptions .....................................................................
MCASP_XSTAT Register Field Descriptions ........................................................................
MCASP_XSLOT Register Field Descriptions ........................................................................
MCASP_XCLKCHK Register Field Descriptions ....................................................................
MCASP_XEVTCTL Register Field Descriptions ....................................................................
MCASP_DITCSRA0 to MCASP_DITCSRA5 Register Field Descriptions .......................................
MCASP_DITCSRB0 to MCASP_DITCSRB5 Register Field Descriptions .......................................
MCASP_DITUDRA0 to MCASP_DITUDRA5 Register Field Descriptions.......................................
MCASP_DITUDRB0 to MCASP_DITUDRB5 Register Field Descriptions.......................................
24-27. MCASP_ACLKRCTL Register Field Descriptions
3434
24-28.
3435
24-29.
24-30.
24-31.
24-32.
24-33.
24-34.
24-35.
24-36.
24-37.
24-38.
24-39.
24-40.
24-41.
24-42.
24-43.
24-44.
24-45.
24-46.
24-47.
24-48.
24-49.
24-50.
SPRUHL7I – April 2014 – Revised December 2019
Submit Documentation Feedback
Copyright © 2014–2019, Texas Instruments Incorporated
List of Tables
3436
3437
3439
3441
3442
3443
3444
3446
3447
3449
3450
3451
3452
3453
3455
3457
3458
3459
3460
3461
3462
3463
123
www.ti.com
24-51. MCASP_SRCTL0 to MCASP_SRCTL5 Register Field Descriptions ............................................. 3464
24-52. MCASP_XBUF0 to MCASP_XBUF5 Register Field Descriptions ................................................ 3466
24-53. MCASP_RBUF0 to MCASP_RBUF5 Register Field Descriptions ................................................ 3467
24-54. MCASP_WFIFOCTL Register Field Descriptions ................................................................... 3468
24-55. MCASP_WFIFOSTS Register Field Descriptions................................................................... 3469
24-56. MCASP_RFIFOCTL Register Field Descriptions ................................................................... 3470
24-57. MCASP_RFIFOSTS Register Field Descriptions ................................................................... 3471
DCAN Connectivity Attributes
25-2.
DCAN Clock Signals .................................................................................................... 3475
25-3.
DCAN Pin List
3475
25-4.
Initialization of a Transmit Object
3491
25-5.
25-6.
25-7.
25-8.
25-9.
25-10.
25-11.
25-12.
25-13.
25-14.
25-15.
25-16.
25-17.
25-18.
25-19.
25-20.
25-21.
25-22.
25-23.
25-24.
25-25.
25-26.
25-27.
25-28.
25-29.
25-30.
25-31.
25-32.
25-33.
25-34.
25-35.
25-36.
25-37.
25-38.
25-39.
25-40.
25-41.
25-42.
124
.........................................................................................
25-1.
...........................................................................................................
.....................................................................................
Initialization of a single Receive Object for Data Frames ..........................................................
Initialization of a Single Receive Object for Remote Frames ......................................................
Parameters of the CAN Bit Time ......................................................................................
Structure of a Message Object ........................................................................................
Field Descriptions .......................................................................................................
Message RAM addressing in Debug/Suspend and RDA Mode...................................................
Message RAM Representation in Debug/Suspend Mode .........................................................
Message RAM Representation in RAM Direct Access Mode .....................................................
DCAN Registers .........................................................................................................
DCAN_CTL Register Field Descriptions .............................................................................
DCAN_ES Register Field Descriptions ...............................................................................
DCAN_ERRC Register Field Descriptions ...........................................................................
DCAN_BTR Register Field Descriptions .............................................................................
DCAN_INT Register Field Descriptions ..............................................................................
DCAN_TEST Register Field Descriptions............................................................................
DCAN_PERR Register Field Descriptions ...........................................................................
DCAN_ABOTR Register Field Descriptions .........................................................................
DCAN_TXRQ_X Register Field Descriptions ........................................................................
DCAN_TXRQ12 Register Field Descriptions ........................................................................
DCAN_TXRQ34 Register Field Descriptions ........................................................................
DCAN_TXRQ56 Register Field Descriptions ........................................................................
DCAN_TXRQ78 Register Field Descriptions ........................................................................
DCAN_NWDAT_X Register Field Descriptions .....................................................................
DCAN_NWDAT12 Register Field Descriptions......................................................................
DCAN_NWDAT34 Register Field Descriptions......................................................................
DCAN_NWDAT56 Register Field Descriptions......................................................................
DCAN_NWDAT78 Register Field Descriptions......................................................................
DCAN_INTPND_X Register Field Descriptions .....................................................................
DCAN_INTPND12 Register Field Descriptions .....................................................................
DCAN_INTPND34 Register Field Descriptions .....................................................................
DCAN_INTPND56 Register Field Descriptions .....................................................................
DCAN_INTPND78 Register Field Descriptions .....................................................................
DCAN_MSGVAL_X Register Field Descriptions ....................................................................
DCAN_MSGVAL12 Register Field Descriptions ....................................................................
DCAN_MSGVAL34 Register Field Descriptions ....................................................................
DCAN_MSGVAL56 Register Field Descriptions ....................................................................
DCAN_MSGVAL78 Register Field Descriptions ....................................................................
DCAN_INTMUX12 Register Field Descriptions .....................................................................
List of Tables
3474
3491
3492
3499
3509
3509
3511
3512
3512
3513
3515
3518
3520
3521
3522
3523
3524
3525
3526
3527
3528
3529
3530
3531
3532
3533
3534
3535
3536
3537
3538
3539
3540
3541
3542
3543
3544
3545
3546
SPRUHL7I – April 2014 – Revised December 2019
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Copyright © 2014–2019, Texas Instruments Incorporated
www.ti.com
25-43. DCAN_INTMUX34 Register Field Descriptions ..................................................................... 3547
25-44. DCAN_INTMUX56 Register Field Descriptions ..................................................................... 3548
25-45. DCAN_INTMUX78 Register Field Descriptions ..................................................................... 3549
........................................................................
DCAN_IF1MSK Register Field Descriptions .........................................................................
DCAN_IF1ARB Register Field Descriptions .........................................................................
DCAN_IF1MCTL Register Field Descriptions .......................................................................
DCAN_IF1DATA Register Field Descriptions .......................................................................
DCAN_IF1DATB Register Field Descriptions .......................................................................
DCAN_IF2CMD Register Field Descriptions ........................................................................
DCAN_IF2MSK Register Field Descriptions .........................................................................
DCAN_IF2ARB Register Field Descriptions .........................................................................
DCAN_IF2MCTL Register Field Descriptions .......................................................................
DCAN_IF2DATA Register Field Descriptions .......................................................................
DCAN_IF2DATB Register Field Descriptions .......................................................................
DCAN_IF3OBS Register Field Descriptions .........................................................................
DCAN_IF3MSK Register Field Descriptions .........................................................................
DCAN_IF3ARB Register Field Descriptions .........................................................................
DCAN_IF3MCTL Register Field Descriptions .......................................................................
DCAN_IF3DATA Register Field Descriptions .......................................................................
DCAN_IF3DATB Register Field Descriptions .......................................................................
DCAN_IF3UPD12 Register Field Descriptions ......................................................................
DCAN_IF3UPD34 Register Field Descriptions ......................................................................
DCAN_IF3UPD56 Register Field Descriptions ......................................................................
DCAN_IF3UPD78 Register Field Descriptions ......................................................................
DCAN_TIOC Register Field Descriptions ............................................................................
DCAN_RIOC Register Field Descriptions ............................................................................
Unsupported McSPI Features .........................................................................................
McSPI Connectivity Attributes .........................................................................................
McSPI Clock Signals ....................................................................................................
McSPI Pin List ...........................................................................................................
Phase and Polarity Combinations ....................................................................................
Chip Select ↔ Clock Edge Delay Depending on Configuration ..................................................
CLKSPIO High/Low Time Computation .............................................................................
Clock Granularity Examples ...........................................................................................
FIFO Writes, Word Length Relationship .............................................................................
MCSPI Registers ........................................................................................................
MCSPI_HL_REV Register Field Descriptions .......................................................................
MCSPI_HL_HWINFO Register Field Descriptions ..................................................................
MCSPI_HL_SYSCONFIG Register Field Descriptions .............................................................
MCSPI_REVISION Register Field Descriptions .....................................................................
MCSPI_SYSCONFIG Register Field Descriptions ..................................................................
MCSPI_SYSSTS Register Field Descriptions .......................................................................
MCSPI_IRQSTS Register Field Descriptions........................................................................
MCSPI_IRQEN Register Field Descriptions .........................................................................
MCSPI_WAKEUPEN Register Field Descriptions ..................................................................
MCSPI_SYST Register Field Descriptions...........................................................................
MCSPI_MODULCTRL Register Field Descriptions .................................................................
MCSPI_CH0CONF Register Field Descriptions.....................................................................
25-46. DCAN_IF1CMD Register Field Descriptions
3550
25-47.
3553
25-48.
25-49.
25-50.
25-51.
25-52.
25-53.
25-54.
25-55.
25-56.
25-57.
25-58.
25-59.
25-60.
25-61.
25-62.
25-63.
25-64.
25-65.
25-66.
25-67.
25-68.
25-69.
26-1.
26-2.
26-3.
26-4.
26-5.
26-6.
26-7.
26-8.
26-9.
26-10.
26-11.
26-12.
26-13.
26-14.
26-15.
26-16.
26-17.
26-18.
26-19.
26-20.
26-21.
26-22.
SPRUHL7I – April 2014 – Revised December 2019
Submit Documentation Feedback
Copyright © 2014–2019, Texas Instruments Incorporated
List of Tables
3554
3555
3557
3558
3559
3562
3563
3564
3566
3567
3568
3570
3571
3572
3574
3575
3576
3577
3578
3579
3580
3582
3585
3587
3587
3587
3593
3603
3604
3604
3605
3623
3625
3626
3627
3628
3629
3631
3632
3635
3637
3638
3640
3642
125
www.ti.com
26-23. MCSPI_CH0STAT Register Field Descriptions ..................................................................... 3646
26-24. MCSPI_CH0CTRL Register Field Descriptions ..................................................................... 3647
26-25. MCSPI_TX0 Register Field Descriptions ............................................................................. 3648
3649
26-27.
3650
26-28.
26-29.
26-30.
26-31.
26-32.
26-33.
26-34.
26-35.
26-36.
26-37.
26-38.
26-39.
26-40.
26-41.
26-42.
26-43.
26-44.
27-1.
27-2.
27-3.
27-4.
27-5.
27-6.
27-7.
27-8.
27-9.
27-10.
27-11.
27-12.
27-13.
27-14.
27-15.
27-16.
27-17.
27-18.
27-19.
27-20.
27-21.
27-22.
27-23.
27-24.
28-1.
28-2.
28-3.
126
............................................................................
MCSPI_CH1CONF Register Field Descriptions.....................................................................
MCSPI_CH1STAT Register Field Descriptions .....................................................................
MCSPI_CH1CTRL Register Field Descriptions .....................................................................
MCSPI_TX1 Register Field Descriptions .............................................................................
MCSPI_RX1 Register Field Descriptions ............................................................................
MCSPI_CH2CONF Register Field Descriptions.....................................................................
MCSPI_CH2STAT Register Field Descriptions .....................................................................
MCSPI_CH2CTRL Register Field Descriptions .....................................................................
MCSPI_TX2 Register Field Descriptions .............................................................................
MCSPI_RX2 Register Field Descriptions ............................................................................
MCSPI_CH3CONF Register Field Descriptions.....................................................................
MCSPI_CH3STAT Register Field Descriptions .....................................................................
MCSPI_CH3CTRL Register Field Descriptions .....................................................................
MCSPI_TX3 Register Field Descriptions .............................................................................
MCSPI_RX3 Register Field Descriptions ............................................................................
MCSPI_XFERLEVEL Register Field Descriptions ..................................................................
MCSPI_DAFTX Register Field Descriptions .........................................................................
MCSPI_DAFRX Register Field Descriptions ........................................................................
Unsupported QSPI Features ...........................................................................................
QSPI Connectivity Attributes ...........................................................................................
QSPI Clock Signals .....................................................................................................
QSPI Pin List .............................................................................................................
SPI Clock Modes Definition ............................................................................................
QSPI Events .............................................................................................................
QSPI Registers ..........................................................................................................
QSPI_PID Register Field Descriptions ...............................................................................
QSPI_SYSCONFIG Register Field Descriptions ....................................................................
QSPI_INTR_STS_RAW_SET Register Field Descriptions ........................................................
QSPI_INTR_STS_EN_CLR Register Field Descriptions ..........................................................
QSPI_INTR_EN_SET_REG Register Field Descriptions ..........................................................
QSPI_INTR_EN_CLR_REG Register Field Descriptions ..........................................................
QSPI_INTC_EOI_REG Register Field Descriptions ................................................................
QSPI_CLOCK_CNTRL_REG Register Field Descriptions.........................................................
QSPI_DC_REG Register Field Descriptions ........................................................................
QSPI_CMD_REG Register Field Descriptions ......................................................................
QSPI_STS_REG Register Field Descriptions .......................................................................
QSPI_DATA_REG Register Field Descriptions .....................................................................
QSPI_SETUP_REG_0 to QSPI_SETUP_REG_3 Register Field Descriptions .................................
QSPI_SWITCH_REG Register Field Descriptions ..................................................................
QSPI_DATA_REG_1 Register Field Descriptions ..................................................................
QSPI_DATA_REG_2 Register Field Descriptions ..................................................................
QSPI_DATA_REG_3 Register Field Descriptions ..................................................................
GPIO0 Connectivity Attributes .........................................................................................
GPIO[1:5] Connectivity Attributes .....................................................................................
GPIO Clock Signals .....................................................................................................
26-26. MCSPI_RX0 Register Field Descriptions
List of Tables
3654
3655
3656
3657
3658
3662
3663
3664
3665
3666
3670
3671
3672
3673
3674
3675
3676
3678
3679
3679
3680
3685
3687
3688
3689
3690
3691
3692
3693
3694
3695
3696
3697
3700
3702
3703
3704
3705
3706
3707
3708
3712
3713
3713
SPRUHL7I – April 2014 – Revised December 2019
Submit Documentation Feedback
Copyright © 2014–2019, Texas Instruments Incorporated
www.ti.com
28-4.
GPIO Pin List ............................................................................................................ 3714
28-5.
GPIO REGISTERS ...................................................................................................... 3724
28-6.
GPIO_REVISION Register Field Descriptions
3725
28-7.
GPIO_SYSCONFIG Register Field Descriptions
3726
28-8.
28-9.
28-10.
28-11.
28-12.
28-13.
28-14.
28-15.
28-16.
28-17.
28-18.
28-19.
28-20.
28-21.
28-22.
28-23.
28-24.
28-25.
28-26.
28-27.
28-28.
28-29.
28-30.
28-31.
29-1.
29-2.
30-1.
30-2.
30-3.
30-4.
30-5.
30-6.
30-7.
30-8.
30-9.
30-10.
30-11.
30-12.
30-13.
30-14.
30-15.
30-16.
30-17.
30-18.
30-19.
......................................................................
...................................................................
GPIO_EOI Register Field Descriptions ...............................................................................
GPIO_IRQSTS_RAW_0 Register Field Descriptions...............................................................
GPIO_IRQSTS_RAW_1 Register Field Descriptions...............................................................
GPIO_IRQSTS_0 Register Field Descriptions ......................................................................
GPIO_IRQSTS_1 Register Field Descriptions ......................................................................
GPIO_IRQSTS_SET_0 Register Field Descriptions................................................................
GPIO_IRQSTS_SET_1 Register Field Descriptions................................................................
GPIO_IRQSTS_CLR_0 Register Field Descriptions ...............................................................
GPIO_IRQSTS_CLR_1 Register Field Descriptions ...............................................................
GPIO_IRQWAKEN_0 Register Field Descriptions ..................................................................
GPIO_IRQWAKEN_1 Register Field Descriptions ..................................................................
GPIO_SYSSTS Register Field Descriptions .........................................................................
GPIO_CTRL Register Field Descriptions ............................................................................
GPIO_OE Register Field Descriptions ...............................................................................
GPIO_DATAIN Register Field Descriptions .........................................................................
GPIO_DATAOUT Register Field Descriptions ......................................................................
GPIO_LEVELDETECT0 Register Field Descriptions ...............................................................
GPIO_LEVELDETECT1 Register Field Descriptions ...............................................................
GPIO_RISINGDETECT Register Field Descriptions ...............................................................
GPIO_FALLINGDETECT Register Field Descriptions .............................................................
GPIO_DEBOUNCEN Register Field Descriptions ..................................................................
GPIO_DEBOUNCINGTIME Register Field Descriptions ...........................................................
GPIO_CLRDATAOUT Register Field Descriptions .................................................................
GPIO_SETDATAOUT Register Field Descriptions .................................................................
SGX530 Connectivity Attributes .......................................................................................
SGX530 Clock Signals .................................................................................................
PRU-ICSS Connectivity Attributes ....................................................................................
PRU-ICSS Clock Signals ...............................................................................................
PRU-ICSS Pin List ......................................................................................................
Local Instruction Memory Map ........................................................................................
Local Data Memory Map ...............................................................................................
Global Memory Map ....................................................................................................
PRU0/1 Constant Table ................................................................................................
Real-Time Status Interface Mapping (R31) Field Descriptions....................................................
Event Interface Mapping (R31) Field Descriptions..................................................................
PRU R31 (GPI) Modes .................................................................................................
PRU GPI Signals and Configurations ................................................................................
Effective Clock Values ..................................................................................................
PRU R30 (GPO) Output Mode ........................................................................................
GPO Mode Descriptions................................................................................................
Effective Clock Values ..................................................................................................
PRU GPI Signals and Configurations for Sigma Delta .............................................................
External Clock Sources .................................................................................................
PRU R31: SD Output Interface Delta Sigma PRU registers: R31Sigma Delta PRU Registers: R31 ........
PRU R30: SD Input Interface Delta Sigma PRU registers: R30Sigma Delta PRU Registers: R30 ..........
SPRUHL7I – April 2014 – Revised December 2019
Submit Documentation Feedback
Copyright © 2014–2019, Texas Instruments Incorporated
List of Tables
3727
3728
3729
3730
3731
3732
3733
3734
3735
3736
3737
3738
3739
3740
3741
3742
3743
3744
3745
3746
3747
3748
3749
3750
3755
3755
3765
3765
3766
3768
3768
3769
3773
3774
3775
3776
3776
3778
3779
3780
3781
3783
3786
3786
3786
127
www.ti.com
30-20. Data_out[23:0] Configuration Options ................................................................................ 3788
30-21. PRU GPI/GPO Signals and Configurations for Peripheral I/F ..................................................... 3789
30-22. Peripheral I/F: RX ....................................................................................................... 3793
30-23. Peripheral I/F: TX........................................................................................................ 3794
30-24. Clock Rate Examples for 192-MHz uart_clk Clock Source ........................................................ 3797
3804
30-26.
3805
30-27.
30-28.
30-29.
30-30.
30-31.
30-32.
30-33.
30-34.
30-35.
30-36.
30-37.
30-38.
30-39.
30-40.
30-41.
30-42.
30-43.
30-44.
30-45.
30-46.
30-47.
30-48.
30-49.
30-50.
30-51.
30-52.
30-53.
30-54.
30-55.
30-56.
30-57.
30-58.
30-59.
30-60.
30-61.
30-62.
30-63.
30-64.
30-65.
30-66.
30-67.
30-68.
128
......................................................................................................
MAC_CTRL_STATUS Register (R25) Field Descriptions .........................................................
CRC Register to PRU Port Mapping ..................................................................................
Scratch Pad XFR ID ....................................................................................................
Scratch Pad XFR Collision and Stall Conditions ....................................................................
PRU-ICSS0 System Events............................................................................................
PRU-ICSS1 System Events............................................................................................
Industrial Ethernet Timer Mode Mapping ............................................................................
Baud Rate Examples for 192-MHZ UART Input Clock and 16× Over-sampling Mode ........................
Baud Rate Examples for 192-MHZ UART Input Clock and 13× Over-sampling Mode ........................
UART Signal Descriptions .............................................................................................
Character Time for Word Lengths ....................................................................................
UART Interrupt Requests Descriptions ...............................................................................
Data Path Configuration Comparison.................................................................................
Frame Structure .........................................................................................................
TX CRC Programming Models ........................................................................................
PRU R31: Receive Interface Data and Status (Read Mode) ......................................................
RX L2 Status .............................................................................................................
RX L2 XFR ID ...........................................................................................................
PRU R30: Transmit Interface ..........................................................................................
PRU R31: Command Interface (Write Mode)........................................................................
RX Nibble and Byte Order .............................................................................................
TX Nibble and Byte Order ..............................................................................................
Preamble Configuration Options ......................................................................................
Interrupt Events in MII_RT .............................................................................................
PRU_ICSS_PRU_CTRL REGISTERS ...............................................................................
PRU_ICSS_CTRL Register Field Descriptions......................................................................
PRU_ICSS_CTRL_STS Register Field Descriptions ...............................................................
PRU_ICSS_CTRL_WAKEUP_EN Register Field Descriptions ...................................................
PRU_ICSS_CTRL_CYCLE Register Field Descriptions ...........................................................
PRU_ICSS_CTRL_STALL Register Field Descriptions ............................................................
PRU_ICSS_CTRL_CTBIR0 Register Field Descriptions ..........................................................
PRU_ICSS_CTRL_CTBIR1 Register Field Descriptions ..........................................................
PRU_ICSS_CTRL_CTPPR0 Register Field Descriptions .........................................................
PRU_ICSS_CTRL_CTPPR1 Register Field Descriptions .........................................................
PRU_ICSS_PRU_DEBUG Registers .................................................................................
PRU_ICSS_DBG_GPREG0 Register Field Descriptions ..........................................................
PRU_ICSS_DBG_GPREG1 Register Field Descriptions ..........................................................
PRU_ICSS_DBG_GPREG2 Register Field Descriptions ..........................................................
PRU_ICSS_DBG_GPREG3 Register Field Descriptions ..........................................................
PRU_ICSS_DBG_GPREG4 Register Field Descriptions ..........................................................
PRU_ICSS_DBG_GPREG5 Register Field Descriptions ..........................................................
PRU_ICSS_DBG_GPREG6 Register Field Descriptions ..........................................................
PRU_ICSS_DBG_GPREG7 Register Field Descriptions ..........................................................
30-25. MPY/MAC XFR ID
List of Tables
3807
3810
3810
3813
3816
3824
3834
3834
3835
3838
3842
3846
3848
3849
3854
3856
3857
3859
3860
3861
3862
3862
3864
3866
3867
3869
3870
3871
3872
3873
3874
3875
3876
3877
3879
3880
3881
3882
3883
3884
3885
3886
SPRUHL7I – April 2014 – Revised December 2019
Submit Documentation Feedback
Copyright © 2014–2019, Texas Instruments Incorporated
www.ti.com
30-69. PRU_ICSS_DBG_GPREG8 Register Field Descriptions .......................................................... 3887
30-70. PRU_ICSS_DBG_GPREG9 Register Field Descriptions .......................................................... 3888
30-71. PRU_ICSS_DBG_GPREG10 Register Field Descriptions......................................................... 3889
30-72. PRU_ICSS_DBG_GPREG11 Register Field Descriptions......................................................... 3890
30-73. PRU_ICSS_DBG_GPREG12 Register Field Descriptions......................................................... 3891
30-74. PRU_ICSS_DBG_GPREG13 Register Field Descriptions......................................................... 3892
30-75. PRU_ICSS_DBG_GPREG14 Register Field Descriptions......................................................... 3893
30-76. PRU_ICSS_DBG_GPREG15 Register Field Descriptions......................................................... 3894
30-77. PRU_ICSS_DBG_GPREG16 Register Field Descriptions......................................................... 3895
30-78. PRU_ICSS_DBG_GPREG17 Register Field Descriptions......................................................... 3896
30-79. PRU_ICSS_DBG_GPREG18 Register Field Descriptions......................................................... 3897
30-80. PRU_ICSS_DBG_GPREG19 Register Field Descriptions......................................................... 3898
30-81. PRU_ICSS_DBG_GPREG20 Register Field Descriptions......................................................... 3899
30-82. PRU_ICSS_DBG_GPREG21 Register Field Descriptions......................................................... 3900
30-83. PRU_ICSS_DBG_GPREG22 Register Field Descriptions......................................................... 3901
30-84. PRU_ICSS_DBG_GPREG23 Register Field Descriptions......................................................... 3902
30-85. PRU_ICSS_DBG_GPREG24 Register Field Descriptions......................................................... 3903
30-86. PRU_ICSS_DBG_GPREG25 Register Field Descriptions......................................................... 3904
30-87. PRU_ICSS_DBG_GPREG26 Register Field Descriptions......................................................... 3905
30-88. PRU_ICSS_DBG_GPREG27 Register Field Descriptions......................................................... 3906
30-89. PRU_ICSS_DBG_GPREG28 Register Field Descriptions......................................................... 3907
30-90. PRU_ICSS_DBG_GPREG29 Register Field Descriptions......................................................... 3908
30-91. PRU_ICSS_DBG_GPREG30 Register Field Descriptions......................................................... 3909
30-92. PRU_ICSS_DBG_GPREG31 Register Field Descriptions......................................................... 3910
30-93. PRU_ICSS_DBG_CT_REG0 Register Field Descriptions ......................................................... 3911
30-94. PRU_ICSS_DBG_CT_REG1 Register Field Descriptions ......................................................... 3912
30-95. PRU_ICSS_DBG_CT_REG2 Register Field Descriptions ......................................................... 3913
30-96. PRU_ICSS_DBG_CT_REG3 Register Field Descriptions ......................................................... 3914
30-97. PRU_ICSS_DBG_CT_REG4 Register Field Descriptions ......................................................... 3915
30-98. PRU_ICSS_DBG_CT_REG5 Register Field Descriptions ......................................................... 3916
30-99. PRU_ICSS_DBG_CT_REG6 Register Field Descriptions ......................................................... 3917
.......................................................
.......................................................
PRU_ICSS_DBG_CT_REG9 Register Field Descriptions .......................................................
PRU_ICSS_DBG_CT_REG10 Register Field Descriptions ......................................................
PRU_ICSS_DBG_CT_REG11 Register Field Descriptions ......................................................
PRU_ICSS_DBG_CT_REG12 Register Field Descriptions ......................................................
PRU_ICSS_DBG_CT_REG13 Register Field Descriptions ......................................................
PRU_ICSS_DBG_CT_REG14 Register Field Descriptions ......................................................
PRU_ICSS_DBG_CT_REG15 Register Field Descriptions ......................................................
PRU_ICSS_DBG_CT_REG16 Register Field Descriptions ......................................................
PRU_ICSS_DBG_CT_REG17 Register Field Descriptions ......................................................
PRU_ICSS_DBG_CT_REG18 Register Field Descriptions ......................................................
PRU_ICSS_DBG_CT_REG19 Register Field Descriptions ......................................................
PRU_ICSS_DBG_CT_REG20 Register Field Descriptions ......................................................
PRU_ICSS_DBG_CT_REG21 Register Field Descriptions ......................................................
PRU_ICSS_DBG_CT_REG22 Register Field Descriptions ......................................................
PRU_ICSS_DBG_CT_REG23 Register Field Descriptions ......................................................
PRU_ICSS_DBG_CT_REG24 Register Field Descriptions ......................................................
30-100. PRU_ICSS_DBG_CT_REG7 Register Field Descriptions
3918
30-101. PRU_ICSS_DBG_CT_REG8 Register Field Descriptions
3919
30-102.
3920
30-103.
30-104.
30-105.
30-106.
30-107.
30-108.
30-109.
30-110.
30-111.
30-112.
30-113.
30-114.
30-115.
30-116.
30-117.
SPRUHL7I – April 2014 – Revised December 2019
Submit Documentation Feedback
Copyright © 2014–2019, Texas Instruments Incorporated
List of Tables
3921
3922
3923
3924
3925
3926
3927
3928
3929
3930
3931
3932
3933
3934
3935
129
www.ti.com
30-118. PRU_ICSS_DBG_CT_REG25 Register Field Descriptions ...................................................... 3936
30-119. PRU_ICSS_DBG_CT_REG26 Register Field Descriptions ...................................................... 3937
30-120. PRU_ICSS_DBG_CT_REG27 Register Field Descriptions ...................................................... 3938
30-121. PRU_ICSS_DBG_CT_REG28 Register Field Descriptions ...................................................... 3939
30-122. PRU_ICSS_DBG_CT_REG29 Register Field Descriptions ...................................................... 3940
30-123. PRU_ICSS_DBG_CT_REG30 Register Field Descriptions ...................................................... 3941
30-124. PRU_ICSS_DBG_CT_REG31 Register Field Descriptions ...................................................... 3942
30-125. PRU_ICSS_INTC Registers .......................................................................................... 3942
30-126. PRU_ICSS_INTC_REVID Register Field Descriptions ........................................................... 3944
30-127. PRU_ICSS_INTC_CR Register Field Descriptions................................................................ 3945
30-128. PRU_ICSS_INTC_GER Register Field Descriptions .............................................................. 3946
30-129. PRU_ICSS_INTC_GNLR Register Field Descriptions ............................................................ 3947
30-130. PRU_ICSS_INTC_SISR Register Field Descriptions ............................................................. 3948
30-131. PRU_ICSS_INTC_SICR Register Field Descriptions ............................................................. 3949
30-132. PRU_ICSS_INTC_EISR Register Field Descriptions ............................................................. 3950
30-133. PRU_ICSS_INTC_EICR Register Field Descriptions ............................................................. 3951
30-134. PRU_ICSS_INTC_HIEISR Register Field Descriptions
..........................................................
3952
30-135. PRU_ICSS_INTC_HIDISR Register Field Descriptions .......................................................... 3953
30-136. PRU_ICSS_INTC_GPIR Register Field Descriptions ............................................................. 3954
3955
30-138. PRU_ICSS_INTC_SRSR1 Register Field Descriptions
3956
30-139.
3957
30-140.
30-141.
30-142.
30-143.
30-144.
30-145.
30-146.
30-147.
30-148.
30-149.
30-150.
30-151.
30-152.
30-153.
30-154.
30-155.
30-156.
30-157.
30-158.
30-159.
30-160.
30-161.
30-162.
30-163.
30-164.
30-165.
30-166.
130
..........................................................
..........................................................
PRU_ICSS_INTC_SECR0 Register Field Descriptions ..........................................................
PRU_ICSS_INTC_SECR1 Register Field Descriptions ..........................................................
PRU_ICSS_INTC_ESR0 Register Field Descriptions ............................................................
PRU_ICSS_INTC_ERS1 Register Field Descriptions ............................................................
PRU_ICSS_INTC_ECR0 Register Field Descriptions ............................................................
PRU_ICSS_INTC_ECR1 Register Field Descriptions ............................................................
PRU_ICSS_INTC_CMR0 Register Field Descriptions ............................................................
PRU_ICSS_INTC_CMR1 Register Field Descriptions ............................................................
PRU_ICSS_INTC_CMR2 Register Field Descriptions ............................................................
PRU_ICSS_INTC_CMR3 Register Field Descriptions ............................................................
PRU_ICSS_INTC_CMR4 Register Field Descriptions ............................................................
PRU_ICSS_INTC_CMR5 Register Field Descriptions ............................................................
PRU_ICSS_INTC_CMR6 Register Field Descriptions ............................................................
PRU_ICSS_INTC_CMR7 Register Field Descriptions ............................................................
PRU_ICSS_INTC_CMR8 Register Field Descriptions ............................................................
PRU_ICSS_INTC_CMR9 Register Field Descriptions ............................................................
PRU_ICSS_INTC_CMR10 Register Field Descriptions ..........................................................
PRU_ICSS_INTC_CMR11 Register Field Descriptions ..........................................................
PRU_ICSS_INTC_CMR12 Register Field Descriptions ..........................................................
PRU_ICSS_INTC_CMR13 Register Field Descriptions ..........................................................
PRU_ICSS_INTC_CMR14 Register Field Descriptions ..........................................................
PRU_ICSS_INTC_CMR15 Register Field Descriptions ..........................................................
PRU_ICSS_INTC_HMR0 Register Field Descriptions ............................................................
PRU_ICSS_INTC_HMR1 Register Field Descriptions ............................................................
PRU_ICSS_INTC_HMR2 Register Field Descriptions ............................................................
PRU_ICSS_INTC_HIPIR0 Register Field Descriptions ...........................................................
PRU_ICSS_INTC_HIPIR1 Register Field Descriptions ...........................................................
PRU_ICSS_INTC_HIPIR2 Register Field Descriptions ...........................................................
30-137. PRU_ICSS_INTC_SRSR0 Register Field Descriptions
List of Tables
3958
3959
3960
3961
3962
3963
3964
3965
3966
3967
3968
3969
3970
3971
3972
3973
3974
3975
3976
3977
3978
3979
3980
3981
3982
3983
3984
SPRUHL7I – April 2014 – Revised December 2019
Submit Documentation Feedback
Copyright © 2014–2019, Texas Instruments Incorporated
www.ti.com
30-167. PRU_ICSS_INTC_HIPIR3 Register Field Descriptions ........................................................... 3985
30-168. PRU_ICSS_INTC_HIPIR4 Register Field Descriptions ........................................................... 3986
30-169. PRU_ICSS_INTC_HIPIR5 Register Field Descriptions ........................................................... 3987
30-170. PRU_ICSS_INTC_HIPIR6 Register Field Descriptions ........................................................... 3988
30-171. PRU_ICSS_INTC_HIPIR7 Register Field Descriptions ........................................................... 3989
30-172. PRU_ICSS_INTC_HIPIR8 Register Field Descriptions ........................................................... 3990
30-173. PRU_ICSS_INTC_HIPIR9 Register Field Descriptions ........................................................... 3991
30-174. PRU_ICSS_INTC_SIPR0 Register Field Descriptions ............................................................ 3992
30-175. PRU_ICSS_INTC_SIPR1 Register Field Descriptions ............................................................ 3993
30-176. PRU_ICSS_INTC_SITR0 Register Field Descriptions ............................................................ 3994
30-177. PRU_ICSS_INTC_SITR1 Register Field Descriptions ............................................................ 3995
30-178. PRU_ICSS_INTC_HINLR0 Register Field Descriptions .......................................................... 3996
30-179. PRU_ICSS_INTC_HINLR1 Register Field Descriptions .......................................................... 3997
30-180. PRU_ICSS_INTC_HINLR2 Register Field Descriptions .......................................................... 3998
30-181. PRU_ICSS_INTC_HINLR3 Register Field Descriptions .......................................................... 3999
30-182. PRU_ICSS_INTC_HINLR4 Register Field Descriptions .......................................................... 4000
30-183. PRU_ICSS_INTC_HINLR5 Register Field Descriptions .......................................................... 4001
30-184. PRU_ICSS_INTC_HINLR6 Register Field Descriptions .......................................................... 4002
30-185. PRU_ICSS_INTC_HINLR7 Register Field Descriptions .......................................................... 4003
30-186. PRU_ICSS_INTC_HINLR8 Register Field Descriptions .......................................................... 4004
30-187. PRU_ICSS_INTC_HINLR9 Register Field Descriptions .......................................................... 4005
30-188. PRU_ICSS_INTC_HIER Register Field Descriptions ............................................................. 4006
30-189. PRU_ICSS_IEP Registers ............................................................................................ 4006
.................................................
PRU_ICSS_IEP_TMR_GLB_STS Register Field Descriptions ..................................................
PRU_ICSS_IEP_TMR_COMPEN Register Field Descriptions ..................................................
PRU_ICSS_IEP_TMR_CNT Register Field Descriptions ........................................................
PRU_ICSS_IEP_TMR_CAP_CFG Register Field Descriptions .................................................
PRU_ICSS_IEP_TMR_CAP_STS Register Field Descriptions ..................................................
PRU_ICSS_IEP_TMR_CAPR0 Register Field Descriptions .....................................................
PRU_ICSS_IEP_TMR_CAPR1 Register Field Descriptions .....................................................
PRU_ICSS_IEP_TMR_CAPR2 Register Field Descriptions .....................................................
PRU_ICSS_IEP_TMR_CAPR3 Register Field Descriptions .....................................................
PRU_ICSS_IEP_TMR_CAPR4 Register Field Descriptions .....................................................
PRU_ICSS_IEP_TMR_CAPR5 Register Field Descriptions .....................................................
PRU_ICSS_IEP_TMR_CAPR6 Register Field Descriptions .....................................................
PRU_ICSS_IEP_TMR_CAPF6 Register Field Descriptions .....................................................
PRU_ICSS_IEP_TMR_CAPR7 Register Field Descriptions .....................................................
PRU_ICSS_IEP_TMR_CAPF7 Register Field Descriptions .....................................................
PRU_ICSS_IEP_TMR_CMP_CFG Register Field Descriptions .................................................
PRU_ICSS_IEP_TMR_CMP_STS Register Field Descriptions .................................................
PRU_ICSS_IEP_TMR_CMP0 Register Field Descriptions.......................................................
PRU_ICSS_IEP_TMR_CMP1 Register Field Descriptions.......................................................
PRU_ICSS_IEP_TMR_CMP2 Register Field Descriptions.......................................................
PRU_ICSS_IEP_TMR_CMP3 Register Field Descriptions.......................................................
PRU_ICSS_IEP_TMR_CMP4 Register Field Descriptions.......................................................
PRU_ICSS_IEP_TMR_CMP5 Register Field Descriptions.......................................................
PRU_ICSS_IEP_TMR_CMP6 Register Field Descriptions.......................................................
PRU_ICSS_IEP_TMR_CMP7 Register Field Descriptions.......................................................
30-190. PRU_ICSS_IEP_TMR_GLB_CFG Register Field Descriptions
4008
30-191.
4009
30-192.
30-193.
30-194.
30-195.
30-196.
30-197.
30-198.
30-199.
30-200.
30-201.
30-202.
30-203.
30-204.
30-205.
30-206.
30-207.
30-208.
30-209.
30-210.
30-211.
30-212.
30-213.
30-214.
30-215.
SPRUHL7I – April 2014 – Revised December 2019
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List of Tables
4010
4011
4012
4014
4015
4016
4017
4018
4019
4020
4021
4022
4023
4024
4025
4026
4027
4028
4029
4030
4031
4032
4033
4034
131
www.ti.com
30-216. PRU_ICSS_IEP_TMR_RXIPG0 Register Field Descriptions .................................................... 4035
30-217. PRU_ICSS_IEP_TMR_RXIPG1 Register Field Descriptions .................................................... 4036
30-218. PRU_ICSS_IEP_TMR_CMP8 Register Field Descriptions....................................................... 4037
30-219. PRU_ICSS_IEP_TMR_CMP9 Register Field Descriptions....................................................... 4038
30-220. PRU_ICSS_IEP_TMR_CMP10 Register Field Descriptions ..................................................... 4039
30-221. PRU_ICSS_IEP_TMR_CMP11 Register Field Descriptions ..................................................... 4040
30-222. PRU_ICSS_IEP_TMR_CMP12 Register Field Descriptions ..................................................... 4041
30-223. PRU_ICSS_IEP_TMR_CMP13 Register Field Descriptions ..................................................... 4042
30-224. PRU_ICSS_IEP_TMR_CMP14 Register Field Descriptions ..................................................... 4043
30-225. PRU_ICSS_IEP_TMR_CMP15 Register Field Descriptions ..................................................... 4044
30-226. PRU_ICSS_IEP_TMR_CNT_RST Register Field Descriptions .................................................. 4045
.......................................................
.....................................................
PRU_ICSS_IEP_SYNC_FIRST_STAT Register Field Descriptions ............................................
PRU_ICSS_IEP_SYNC0_STAT Register Field Descriptions ....................................................
PRU_ICSS_IEP_SYNC1_STAT Register Field Descriptions ....................................................
PRU_ICSS_IEP_SYNC_PWIDTH Register Field Descriptions ..................................................
PRU_ICSS_IEP_SYNC0_PERIOD Register Field Descriptions.................................................
PRU_ICSS_IEP_SYNC1_DELAY Register Field Descriptions ..................................................
PRU_ICSS_IEP_SYNC_START Register Field Descriptions....................................................
PRU_ICSS_IEP_WD_PREDIV Register Field Descriptions .....................................................
PRU_ICSS_IEP_PDI_WD_TIM Register Field Descriptions .....................................................
PRU_ICSS_IEP_PD_WD_TIM Register Field Descriptions .....................................................
PRU_ICSS_IEP_WD_STS Register Field Descriptions ..........................................................
PRU_ICSS_IEP_WD_EXP_CNT Register Field Descriptions ...................................................
PRU_ICSS_IEP_WD_CTRL Register Field Descriptions ........................................................
PRU_ICSS_IEP_DIGIO_CTRL Register Field Descriptions .....................................................
PRU_ICSS_IEP_DIGIO_STATUS Register Field Descriptions ..................................................
PRU_ICSS_IEP_DIGIO_DATA_IN Register Field Descriptions .................................................
PRU_ICSS_IEP_DIGIO_DATA_IN_RAW Register Field Descriptions .........................................
PRU_ICSS_IEP_DIGIO_DATA_OUT Register Field Descriptions ..............................................
PRU_ICSS_IEP_DIGIO_DATA_OUT_EN Register Field Descriptions .........................................
PRU_ICSS_IEP_DIGIO_EXP Register Field Descriptions .......................................................
PRU_ICSS_UART Registers .........................................................................................
Receiver Buffer Register (RBR) Field Descriptions ...............................................................
Transmitter Holding Register (THR) Field Descriptions ..........................................................
Interrupt Enable Register (IER) Field Descriptions ................................................................
Interrupt Identification Register (IIR) Field Descriptions ..........................................................
Interrupt Identification and Interrupt Clearing Information ........................................................
FIFO Control Register (FCR) Field Descriptions ..................................................................
Line Control Register (LCR) Field Descriptions ....................................................................
Relationship Between ST, EPS, and PEN Bits in LCR ...........................................................
Number of STOP Bits Generated ....................................................................................
Modem Control Register (MCR) Field Descriptions ...............................................................
Line Status Register (LSR) Field Descriptions .....................................................................
Modem Status Register (MSR) Field Descriptions ................................................................
Scratch Pad Register (MSR) Field Descriptions ...................................................................
Divisor LSB Latch (DLL) Field Descriptions ........................................................................
Divisor MSB Latch (DLH) Field Descriptions .......................................................................
30-227. PRU_ICSS_IEP_TMR_PWM Register Field Descriptions
4047
30-229.
4048
30-230.
30-231.
30-232.
30-233.
30-234.
30-235.
30-236.
30-237.
30-238.
30-239.
30-240.
30-241.
30-242.
30-243.
30-244.
30-245.
30-246.
30-247.
30-248.
30-249.
30-250.
30-251.
30-252.
30-253.
30-254.
30-255.
30-256.
30-257.
30-258.
30-259.
30-260.
30-261.
30-262.
30-263.
30-264.
132
4046
30-228. PRU_ICSS_IEP_SYNC_CTRL Register Field Descriptions
List of Tables
4049
4050
4051
4052
4053
4054
4055
4056
4057
4058
4059
4060
4061
4062
4063
4064
4065
4066
4067
4068
4069
4070
4071
4072
4073
4074
4075
4076
4076
4077
4078
4081
4082
4083
4083
SPRUHL7I – April 2014 – Revised December 2019
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30-265. Revision Identification Register 1 (REVID1) Field Descriptions ................................................. 4084
30-266. Revision Identification Register 2 (REVID2) Field Descriptions ................................................. 4084
30-267. Power and Emulation Management Register (PWREMU_MGMT) Field Descriptions ....................... 4085
30-268. Mode Definition Register (MDR) Field Descriptions ............................................................... 4086
30-269. PRU_ICSS_MII_RT Registers
.......................................................................................
4086
30-270. RXCFG0 Register Field Descriptions ............................................................................... 4088
30-271. RXCFG1 Register Field Descriptions ............................................................................... 4090
30-272. TXCFG0 Register Field Descriptions................................................................................ 4092
30-273. TXCFG1 Register Field Descriptions................................................................................ 4094
...............................................................................
...............................................................................
TXIPG0 Register Field Descriptions .................................................................................
TXIPG1 Register Field Descriptions .................................................................................
PRS0 Register Field Descriptions ...................................................................................
PRS1 Register Field Descriptions ...................................................................................
RXFRMS0 Register Field Descriptions .............................................................................
RXFRMS1 Register Field Descriptions .............................................................................
RXPCNT0 Register Field Descriptions ..............................................................................
RXPCNT1 Register Field Descriptions ..............................................................................
RXERR0 Register Field Descriptions ...............................................................................
RXERR1 Register Field Descriptions ...............................................................................
RXFLV0 Register Field Descriptions ................................................................................
RXFLV1 Register Field Descriptions ................................................................................
TXFLV0 Register Field Descriptions ................................................................................
TXFLV1 Register Field Descriptions ................................................................................
PRU_ICSS_CFG Registers ..........................................................................................
PRU_ICSS_CFG_REVID Register Field Descriptions ............................................................
PRU_ICSS_CFG_SYSCFG Register Field Descriptions .........................................................
PRU_ICSS_CFG_GPCFG0 Register Field Descriptions .........................................................
PRU_ICSS_CFG_GPCFG1 Register Field Descriptions .........................................................
PRU_ICSS_CFG_CGR Register Field Descriptions ..............................................................
PRU_ICSS_CFG_ISRP Register Field Descriptions ..............................................................
PRU_ICSS_CFG_ISP Register Field Descriptions ................................................................
PRU_ICSS_CFG_IESP Register Field Descriptions ..............................................................
PRU_ICSS_CFG_IECP Register Field Descriptions ..............................................................
PRU_ICSS_CFG_PMAO Register Field Descriptions ............................................................
PRU_ICSS_CFG_MII_RT Register Field Descriptions ...........................................................
PRU_ICSS_CFG_IEPCLK Register Field Descriptions ..........................................................
PRU_ICSS_CFG_SPP Register Field Descriptions ...............................................................
PRU_ICSS_CFG_PIN_MX Register Field Descriptions ..........................................................
PRU_ICSS_CFG_SD_P0_CLK_i Register Field Descriptions ...................................................
PRU_ICSS_CFG_SD_P0_SS_i Register Field Descriptions ....................................................
PRU_ICSS_CFG_SD_P1_CLK_i Register Field Descriptions ...................................................
PRU_ICSS_CFG_SD_P1_SS_i Register Field Descriptions ....................................................
PRU_ICSS_CFG_ED_P0_RXCFG Register Field Descriptions.................................................
PRU_ICSS_CFG_ED_P0_TXCFG Register Field Descriptions .................................................
PRU_ICSS_CFG_ED_P0_CFG0_i Register Field Descriptions .................................................
PRU_ICSS_CFG_ED_P0_CFG1_i Register Field Descriptions .................................................
PRU_ICSS_CFG_ED_P1_RXCFG Register Field Descriptions.................................................
30-274. TXCRC0 Register Field Descriptions
4096
30-275. TXCRC1 Register Field Descriptions
4097
30-276.
4098
30-277.
30-278.
30-279.
30-280.
30-281.
30-282.
30-283.
30-284.
30-285.
30-286.
30-287.
30-288.
30-289.
30-290.
30-291.
30-292.
30-293.
30-294.
30-295.
30-296.
30-297.
30-298.
30-299.
30-300.
30-301.
30-302.
30-303.
30-304.
30-305.
30-306.
30-307.
30-308.
30-309.
30-310.
30-311.
30-312.
30-313.
SPRUHL7I – April 2014 – Revised December 2019
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Copyright © 2014–2019, Texas Instruments Incorporated
List of Tables
4099
4100
4101
4102
4103
4104
4105
4106
4107
4108
4109
4110
4111
4111
4113
4114
4115
4117
4119
4121
4122
4123
4124
4125
4126
4127
4128
4129
4130
4131
4132
4133
4134
4135
4136
4138
4139
133
www.ti.com
30-314. PRU_ICSS_CFG_ED_P1_TXCFG Register Field Descriptions ................................................. 4140
30-315. PRU_ICSS_CFG_ED_P1_CFG0_i Register Field Descriptions ................................................. 4141
30-316. PRU_ICSS_CFG_ED_P1_CFG1_i Register Field Descriptions ................................................. 4143
31-1.
IEEE 1149.1 Signals .................................................................................................... 4147
31-2.
JTAG ID Code ........................................................................................................... 4148
31-3.
Trace Port Signals
31-4.
31-5.
31-6.
31-7.
31-8.
31-9.
31-10.
31-11.
31-12.
31-13.
31-14.
31-15.
31-16.
31-17.
31-18.
31-19.
31-20.
31-21.
31-22.
31-23.
31-24.
31-25.
31-26.
31-27.
31-28.
31-29.
31-30.
31-31.
31-32.
31-33.
31-34.
31-35.
31-36.
31-37.
31-38.
31-39.
31-40.
31-41.
31-42.
31-43.
31-44.
31-45.
31-46.
134
......................................................................................................
ICEPick Boot Modes upon POR ......................................................................................
ICEPick Secondary Debug TAP Mapping ...........................................................................
ICEPick Debug Core Mapping .........................................................................................
Cross-Triggering .........................................................................................................
Debug Subsystem Suspend Output Lines ...........................................................................
TPIU and CS-ETB Trace Funnel Assignment .......................................................................
STM Message Software Masters .....................................................................................
L3 Interconnect Functional Probe Mapping ..........................................................................
L3 Master ID Mapping (Debug View) .................................................................................
Performance Monitoring Events Detection ...........................................................................
Performance Filtering Options .........................................................................................
Statistics Collector Master Address Mapping ........................................................................
Statistics Collector Slave Address Mapping .........................................................................
Performance Filtering Options .........................................................................................
Statistics Collector Counters ...........................................................................................
Statistics Collector 0 Probes ...........................................................................................
Statistics Collector 1 Probes ...........................................................................................
Statistics Collector 2 Probes ...........................................................................................
Statistics Collector 3 Probes ...........................................................................................
Master-ID for Hardware Masters ......................................................................................
Trace Port Configuration ...............................................................................................
Concurrent Debug and Trace ..........................................................................................
Debug Modules Memory Mapping ....................................................................................
Debug Modules Memory Mapping (APB-AP View) .................................................................
DRM Registers ..........................................................................................................
DEBUGSS_DRM_SUSPEND_CTRL0 Register Field Descriptions ..............................................
DEBUGSS_DRM_SUSPEND_CTRL1 Register Field Descriptions ..............................................
DEBUGSS_DRM_SUSPEND_CTRL2 Register Field Descriptions ..............................................
DEBUGSS_DRM_SUSPEND_CTRL3 Register Field Descriptions ..............................................
DEBUGSS_DRM_SUSPEND_CTRL4 Register Field Descriptions ..............................................
DEBUGSS_DRM_SUSPEND_CTRL5 Register Field Descriptions ..............................................
DEBUGSS_DRM_SUSPEND_CTRL6 Register Field Descriptions ..............................................
DEBUGSS_DRM_SUSPEND_CTRL7 Register Field Descriptions ..............................................
DEBUGSS_DRM_SUSPEND_CTRL8 Register Field Descriptions ..............................................
DEBUGSS_DRM_SUSPEND_CTRL10 Register Field Descriptions .............................................
DEBUGSS_DRM_SUSPEND_CTRL11 Register Field Descriptions .............................................
DEBUGSS_DRM_SUSPEND_CTRL12 Register Field Descriptions .............................................
DEBUGSS_DRM_SUSPEND_CTRL13 Register Field Descriptions .............................................
DEBUGSS_DRM_SUSPEND_CTRL14 Register Field Descriptions .............................................
DEBUGSS_DRM_SUSPEND_CTRL15 Register Field Descriptions .............................................
DEBUGSS_DRM_SUSPEND_CTRL16 Register Field Descriptions .............................................
DEBUGSS_DRM_SUSPEND_CTRL17 Register Field Descriptions .............................................
DEBUGSS_DRM_SUSPEND_CTRL18 Register Field Descriptions .............................................
List of Tables
4148
4150
4151
4151
4153
4155
4156
4161
4162
4163
4164
4164
4164
4165
4166
4166
4166
4167
4167
4167
4168
4168
4169
4170
4170
4170
4172
4173
4174
4175
4176
4177
4178
4179
4180
4181
4182
4183
4184
4185
4186
4187
4188
4189
SPRUHL7I – April 2014 – Revised December 2019
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31-47. DEBUGSS_DRM_SUSPEND_CTRL19 Register Field Descriptions ............................................. 4190
31-48. DEBUGSS_DRM_SUSPEND_CTRL24 Register Field Descriptions ............................................. 4191
31-49. DEBUGSS_DRM_SUSPEND_CTRL27 Register Field Descriptions ............................................. 4192
31-50. DEBUGSS_DRM_SUSPEND_CTRL28 Register Field Descriptions ............................................. 4193
31-51. DEBUGSS_DRM_SUSPEND_CTRL29 Register Field Descriptions ............................................. 4194
SPRUHL7I – April 2014 – Revised December 2019
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List of Tables
135
Preface
SPRUHL7I – April 2014 – Revised December 2019
Read This First
About This Manual
Related Documentation From Texas Instruments
For a complete listing of related documentation and development-support tools, visit www.ti.com.
Terms and Abbreviations
Terms and abbreviations will be added to a future version of this document.
For example: Woco - Woco is a read / write type access defined as "Write - One - Change - Only, and a
bit
with this access type can be modified, but only once for a POR cycle".
(1) (2) (3) (4) (5) (6)
(1)
(2)
(3)
(4)
(5)
(6)
136
Cortex is a trademark of ARM Limited.
ARM is a registered trademark of ARM Limited.
1-Wire is a registered trademark of Dallas Semiconductor Corporation.
USSE is a trademark of Imagination Technologies Ltd..
POWERVR is a registered trademark of Imagination Technologies Ltd..
is a trademark of ~Samsung Electronics Co., Ltd..
Read This First
SPRUHL7I – April 2014 – Revised December 2019
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Revision History
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Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from January 15, 2018 to December 30, 2019 (from H Revision (January 2018) to I Revision) .................. Page
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Updated Note 3 for L3 Memory Map table. ......................................................................................... 142
Updated DISTRIBUTOR REGISTERS table. ....................................................................................... 164
Updated SYSBOOT11 Column in SYSBOOT Configuration Pins table with new NAND mode information. .............. 187
Updated Reading NAND Geometry from I2C EEPROM section. ................................................................ 208
Added SYSBOOT[11] information to SYSBOOT Signals for NAND Boot table. ............................................... 213
Updated Initialization and Detection section. ....................................................................................... 226
Updated Note. .......................................................................................................................... 275
Updated EMIF Functional Clock from 100 MHz to 200 MHz. ................................................................... 1340
Updated READ_LAT bit description in the EMIF4D_DDR_PHY_CTRL_1 Register. ........................................ 1421
Added External DMA Pin Functionality section. .................................................................................. 1589
Updated ETYPE bit description in the Q0E_0 to Q0E_15 Register. ........................................................... 1689
Updated ETYPE bit description in the Q1E_0 to Q1E_15 Register. ........................................................... 1690
Updated ETYPE bit description in the Q2E_0 to Q2E_15 Register. ........................................................... 1691
Added Note. ........................................................................................................................... 1803
Updated DIFF_CNTRL bit description for ADC0_IDLECONFIG Register. .................................................... 1828
Updated SEL_INM_SWM bit description for ADC0_IDLECONFIG Register.................................................. 1829
Updated DIFF_CNTRL bit description for ADC0_TS_CHARGE_STEPCONFIG Register. ................................. 1830
Updated SEL_INM_SWM bit description for ADC0_TS_CHARGE_STEPCONFIG Register............................... 1831
Changed INTREF to Reserved in SEL_RFP_SWC bit description of ADC0_TS_CHARGE_STEPCONFIG Register. . 1831
Updated DIFF_CNTRL bit description for ADC0_STEPCONFIG_0 Register. ................................................ 1833
Updated SEL_INM_SWC bit description for ADC0_STEPCONFIG_0 Register. ............................................. 1834
Changed INTREF to Reserved in SEL_RFP_SWC bit description of ADC0_STEPCONFIG_0 Register. ................ 1834
Updated DIFF_CNTRL bit description for ADC1_IDLECONFIG Register. .................................................... 1873
Updated SEL_INM_SWM_3_0 bit description for ADC1_IDLECONFIG Register............................................ 1873
Updated DIFF_CNTRL bit description in ADC1_STEPCONFIG1 Register. .................................................. 1876
Updated SEL_INM_SWM_3_0 bit description in ADC1_STEPCONFIG1 Register. ......................................... 1876
Updated DIFF_CNTRL bit description in ADC1_STEPCONFIG2 Register. ................................................. 1879
Updated SEL_INM_SWM_3_0 bit description in ADC1_STEPCONFIG2 Register. ......................................... 1879
Updated DIFF_CNTRL bit description in ADC1_STEPCONFIG3 Register. ................................................. 1882
Updated SEL_INM_SWM_3_0 bit description in ADC1_STEPCONFIG3 Register. ........................................ 1882
Updated DIFF_CNTRL bit description in ADC1_STEPCONFIG4 Register. ................................................. 1885
Updated SEL_INM_SWM_3_0 bit description in ADC1_STEPCONFIG4 Register. ........................................ 1885
Updated DIFF_CNTRL bit description in ADC1_STEPCONFIG5 Register. ................................................. 1888
Updated SEL_INM_SWM_3_0 bit description in ADC1_STEPCONFIG5 Register. ........................................ 1888
Updated DIFF_CNTRL bit description in ADC1_STEPCONFIG6 Register. ................................................. 1891
Updated SEL_INM_SWM_3_0 bit description in ADC1_STEPCONFIG6 Register. ........................................ 1891
Updated DIFF_CNTRL bit description in ADC1_STEPCONFIG7 Register. ................................................. 1894
Updated SEL_INM_SWM_3_0 bit description in ADC1_STEPCONFIG7 Register. ........................................ 1894
Updated DIFF_CNTRL bit description in ADC1_STEPCONFIG8 Register. ................................................. 1897
Updated SEL_INM_SWM_3_0 bit description in ADC1_STEPCONFIG8 Register. ........................................ 1897
Updated DIFF_CNTRL bit description in ADC1_STEPCONFIG9 Register. ................................................. 1900
Updated SEL_INM_SWM_3_0 bit description in ADC1_STEPCONFIG9 Register. ........................................ 1900
Updated DIFF_CNTRL bit description in ADC1_STEPCONFIG10 Register. ................................................ 1903
Updated SEL_INM_SWM_3_0 bit description in ADC1_STEPCONFIG10 Register. ....................................... 1903
Updated DIFF_CNTRL bit description in ADC1_STEPCONFIG11 Register. ................................................ 1906
Updated SEL_INM_SWM_3_0 bit description in ADC1_STEPCONFIG11 Register. ....................................... 1906
Updated DIFF_CNTRL bit description in ADC1_STEPCONFIG12 Register. ................................................ 1909
Updated SEL_INM_SWM_3_0 bit description in ADC1_STEPCONFIG12 Register. ....................................... 1909
SPRUHL7I – April 2014 – Revised December 2019
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Revision History
137
Revision History
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Updated DIFF_CNTRL bit description in ADC1_STEPCONFIG13 Register. ................................................
Updated SEL_INM_SWM_3_0 bit description in ADC1_STEPCONFIG13 Register. .......................................
Updated DIFF_CNTRL bit description in ADC1_STEPCONFIG14 Register. ................................................
Updated SEL_INM_SWM_3_0 bit description in ADC1_STEPCONFIG14 Register. .......................................
Updated DIFF_CNTRL bit description in ADC1_STEPCONFIG15 Register. ................................................
Updated SEL_INM_SWM_3_0 bit description in ADC1_STEPCONFIG15 Register. .......................................
Updated DIFF_CNTRL bit description in ADC1_STEPCONFIG16 Register. ................................................
Updated SEL_INM_SWM_3_0 bit description in ADC1_STEPCONFIG16 Register. .......................................
Updated Display Subsystem Reset section. ......................................................................................
Updated LCD_EN_POL and LCD_EN_SIGNAL bit descriptions in the DISPC_CTRL Register. ..........................
Updated PCD bit description in the DISPC_DIVISOR Register. ...............................................................
Updated GFX_BURST_SIZE bit description in the DISPC_GFX_ATTRS Register..........................................
Updated Example for Decimation Pattern table...................................................................................
Changed CLKADPI Max Frequency from 48 MHz to 96 MHz in MMCSD Clock Signals table. ...........................
Updated INIT bit description of the SD_CON Register. .........................................................................
Changed Reset value for HSPCLKDIV bit in TBCTL Register from 0h to 1h. ................................................
Updated Unsupported UART Features table. .....................................................................................
Updated FIFO DMA Mode Operation section. ....................................................................................
Updated DMA Transfers (DMA Mode 1, 2, or 3) section. .......................................................................
Updated UART_SCR Register description. ......................................................................................
Updated UART_SSR Register description. .......................................................................................
Updated TRX bit description of the I2C_CON Register. .........................................................................
Updated SINGLE bit description in the MCSPI_MODULCTRL Register. .....................................................
Updated Unsupported QSPI Features table. ......................................................................................
Updated QSPI Pin List table. ........................................................................................................
Updated SPI Control State-Machine section. .....................................................................................
Updated SPI Clock Modes Definition table. .......................................................................................
Updated CKPH3 bit field description in the QSPI_DC_REG Register. .......................................................
Updated WLEN bit in QSPI_CMD_REG Register. ...............................................................................
Updated R31 bit description in Peripheral I/F: RX table. ........................................................................
Updated RX - Auto Arm or Non-Auto Arm section. ..............................................................................
Updated Note in MII_RT Introduction. .............................................................................................
Updated ICEPick Secondary Debug TAP Mapping table........................................................................
Added Trace Datapath section. .....................................................................................................
Added TPIU, CS-TF (CS-ETB), and CD-TF (TPIU) to Debug Modules Memory Mapping table. ..........................
Revision History
1912
1912
1915
1915
1918
1918
1921
1921
1986
2046
2060
2068
2166
2556
2608
3016
3142
3156
3157
3240
3241
3307
3641
3678
3680
3685
3685
3697
3700
3793
3803
3845
4151
4156
4170
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Chapter 1
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Introduction
1.1
AM437x Family
1.1.1 Device Features
This architecture is configured with different sets of features in different devices. This technical reference
manual details all of the features available in current and future AM437x devices. Some features may not
be available or supported in your particular device. The features supported across different AM437x
devices are detailed in your device-specific data manual.
1.1.2 Device Identification
Several registers help identify the type and available features of the device. The DEV_FEATURE register
in the control module is summarized in the Device Comparison section of your device-specific data
manual, and Table 1-1 summarizes the Device_ID registers.
Table 1-1. Device Identification Registers
Bit
Field
Value
Description
31-28
DEVREV
Device revision
0001b - Silicon Revision 1.1
0010b - Silicon Revision 1.2
See device errata for detailed information on functionality in each device revision.
Reset value is revision-dependent.
27-12
PARTNUM
Device part number (unique JTAG)
0xB98C
11-1
MFGR
Manufacturer's ID
0x017
0
ID_LSB
Reserved - always 1.
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Memory Map
This sections describes the memory map for the device.
Topic
2.1
140
...........................................................................................................................
Page
ARM Cortex-A9 Memory Map ............................................................................. 141
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2.1
ARM Cortex-A9 Memory Map
2.1.1 L3 Memory Map
Table 2-1. L3 Memory Map
Block Name
Start_address (hex)
End_address (hex)
Size
Description
GPMC
0x0000_0000
0x1FFF_FFFF
512MB
8-/16-bit External Memory (Ex/R/W) [1][2]
Reserved
0x2000_0000
0x2FFF_FFFF
256MB
QSPI
0x3000_0000
0x33FF_FFFF
64MB
Reserved
0x3400_0000
0x3FFF_FFFF
192MB
Reserved
0x4000_0000
0x4002_FFFF
192KB
MPU_ROM_PUBLIC
0x4003_0000
0x4003_FFFF
64KB
Reserved
0x4004_0000
0x400F_FFFF
768KB
Reserved
0x4010_0000
0x401F_FFFF
1MB
QSPI CS0 Maddrspace 1 space
32-bit Ex/R [2] – Public Boot ROM
Reserved
0x4020_0000
0x402E_FFFF
960KB
MPU_RAM
0x402F_0000
0x402F_FFFF
64KB
32-bit Ex/R/W[2] – SRAM [3]
OCMCRAM
0x4030_0000
0x4033_FFFF
256KB
32-bit Ex/R/W [2] – L3 OCMC SRAM
Reserved
0x4034_0000
0x403F_FFFF
768KB
Reserved
0x4040_0000
0x4041_FFFF
128KB
Reserved
0x4042_0000
0x404F_FFFF
896KB
MPU_L2_CACHE
0x4050_0000
0x4053_FFFF
256KB
Reserved
0x4054_0000
0x405F_FFFF
768KB
Reserved
0x4060_0000
0x407F_FFFF
2MB
Reserved
0x4080_0000
0x4083_FFFF
256KB
Reserved
0x4084_0000
0x40DF_FFFF
5888KB
Reserved
0x40E0_0000
0x40E0_7FFF
32KB
Reserved
0x40E0_8000
0x40EF_FFFF
992KB
Reserved
0x40F0_0000
0x40F0_7FFF
32KB
Reserved
0x40F0_8000
0x40FF_FFFF
992KB
Reserved
0x4100_0000
0x41FF_FFFF
16MB
Reserved
0x4200_0000
0x43FF_FFFF
32MB
L3F_CFG
0x4400_0000
0x443F_FFFF
4MB
Reserved
0x4440_0000
0x447F_FFFF
4MB
L3S_CFG
0x4480_0000
0x44BF_FFFF
4MB
L3Slow configuration registers
L4_WKUP
0x44C0_0000
0x44FF_FFFF
4MB
L4 Wakeup Peripheral (see L4_WKUP table)
Reserved
0x4500_0000
0x45FF_FFFF
16MB
MCASP0_DATA
0x4600_0000
0x463F_FFFF
4MB
McASP0 Data Registers
MCASP1_DATA
0x4640_0000
0x467F_FFFF
4MB
McASP1 Data Registers
Reserved
0x4680_0000
0x46BF_FFFF
4MB
Reserved
0x46C0_0000
0x46FF_FFFF
4MB
Reserved
0x4700_0000
0x473F_FFFF
4MB
Reserved
0x4740_0000
0x477F_FFFF
4MB
Reserved
0x4780_0000
0x4780_FFFF
64KB
MMCSD2
0x4781_0000
0x4781_FFFF
64KB
Reserved
0x4782_0000
0x478F_FFFF
896KB
QSPI
0x4790_0000
0x479F_FFFF
1MB
Reserved
0x47A0_0000
0x47BF_FFFF
2MB
Reserved
0x47C0_0000
0x47FF_FFFF
4MB
L4_PER
0x4800_0000
0x48FF_FFFF
16MB
MPU L2 Cache
L3Fast configuration registers
MMCSD2
QSPI MMR Maddrspace 0 space
L4 Peripheral (see L4_PER table)
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Table 2-1. L3 Memory Map (continued)
Block Name
Start_address (hex)
End_address (hex)
Size
Description
EDMA3CC
0x4900_0000
0x490F_FFFF
1MB
EDMA3 Channel Controller (TPCC) Registers
Reserved
0x4910_0000
0x497F_FFFF
7MB
EDMA3TC0
0x4980_0000
0x498F_FFFF
1MB
EDMA3 Transfer Controller 0 (TPTC0)
Registers
EDMA3TC1
0x4990_0000
0x499F_FFFF
1MB
EDMA3 Transfer Controller 1 (TPTC1)
Registers
EDMA3TC2
0x49A0_0000
0x49AF_FFFF
1MB
EDMA3 Transfer Controller 2 (TPTC2)
Registers
Reserved
0x49B0_0000
0x49BF_FFFF
1MB
Reserved
0x49C0_0000
0x49FF_FFFF
4MB
L4_FAST
0x4A00_0000
0x4AFF_FFFF
16MB
L4 Fast Peripheral (see L4_FAST table)
DEBUGSS
0x4B00_0000
0x4BFF_FFFF
16MB
Debug Subsystem region
EMIF0 Configuration registers
EMIF
0x4C00_0000
0x4CFF_FFFF
16MB
Reserved
0x4D00_0000
0x4DFF_FFFF
16MB
Reserved
0x4E00_0000
0x4FFF_FFFF
32MB
GPMC
0x5000_0000
0x50FF_FFFF
16MB
Reserved
0x5100_0000
0x51FF_FFFF
16MB
Reserved
0x5200_0000
0x52FF_FFFF
16MB
Reserved
0x5300_0000
0x530F_FFFF
1MB
Reserved
0x5310_0000
0x531F_FFFF
1MB
Reserved
0x5320_0000
0x533F_FFFF
2MB
Reserved
0x5340_0000
0x534F_FFFF
1MB
Reserved
0x5350_0000
0x535F_FFFF
1MB
Reserved
0x5360_0000
0x536F_FFFF
1MB
Reserved
0x5370_0000
0x537F_FFFF
1MB
GPMC Configuration registers
Reserved
0x5380_0000
0x543F_FFFF
12MB
PRU_ICSS1
0x5440_0000
0x547F_FFFF
4MB
PRU-ICSS1 Instruction/Data/Control Space [4]
ADC1
0x5480_0000
0x54BF_FFFF
4MB
ADC1 DMA Port
ADC0 DMA Port
ADC0
0x54C0_0000
0x54FF_FFFF
4MB
Reserved
0x5500_0000
0x55FF_FFFF
16MB
GFX
0x5600_0000
0x56FF_FFFF
16MB
Reserved
0x5700_0000
0x57FF_FFFF
16MB
Reserved
0x5800_0000
0x58FF_FFFF
16MB
Reserved
0x5900_0000
0x59FF_FFFF
16MB
Reserved
0x5A00_0000
0x5AFF_FFFF
16MB
Reserved
0x5B00_0000
0x5BFF_FFFF
16MB
Reserved
0x5C00_0000
0x5DFF_FFFF
32MB
Reserved
0x5E00_0000
0x5FFF_FFFF
32MB
Reserved
0x6000_0000
0x7FFF_FFFF
512MB
EMIF
0x8000_0000
0xFFFF_FFFF
2048MB
0x1_0000_0000
0x1_FFFF_FFFF
4096MB
Reserved
SGX530 Slave Port
8-/16-/32-bit External Memory (Ex/R/W) [2]
(1) The first 1MB of address space 0x0-0xFFFFF is inaccessible externally.
(2) Ex/R/W – Execute/Read/Write.
(3) Address 0x402F_0000-0x402F_03FF is not available on general purpose (GP) devices for PG1.1. Address 0x402F_00000x402F_3FFF is not available on general purpose (GP) devices for PG1.2 and beyond.
(4) For PRU-ICSS0/1, the PRU can access the other PRU-ICSS memory space through internal expansion ports. The PRU can
access the neighbor PRU-ICSS memory starting at 256KB/0x0004_0000 range. The address seen by the 2nd PRU-ICSS will
get translated by hardware logic in PRU-ICSS, 0x0004_0000 will get subtracted.
142
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2.1.2 L4_WKUP Memory Map
Table 2-2. L4_WKUP Memory Map
Region Name
Start_address (hex)
End_address (hex)
Size
Reserved
0x0000_0000
0x44BF_FFFF
1100MB
Description
L4_WKUP
0x44C0_0000
0x44C0_07FF
2KB
Address/Protection (AP)
L4_WKUP
0x44C0_0800
0x44C0_0FFF
2KB
Link Agent (LA)
L4_WKUP_REG
0x44C0_1000
0x44C0_13FF
1KB
Initiator Port (IP0)
L4_WKUP_REG
0x44C0_1400
0x44C0_17FF
1KB
Initiator Port (IP1)
Reserved
0x44C0_1800
0x44C0_1FFF
2KB
Reserved
0x44C0_2000
0x44CF_FFFF
1016KB
Reserved
0x44D0_0000
0x44D0_3FFF
16KB
Reserved
0x44D0_4000
0x44D0_4FFF
4KB
Reserved
0x44D0_5000
0x44D7_FFFF
492KB
Reserved
0x44D8_0000
0x44D8_1FFF
8KB
Reserved
0x44D8_2000
0x44D8_2FFF
4KB
Reserved
0x44D8_3000
0x44DE_FFFF
436KB
PRCM
0x44DF_0000
0x44DF_FFFF
64KB
Module
PRM_IRQ
0x44DF_0000
0x44DF_02FF
Power Reset Module IRQ Registers
PRM_MPU
0x44DF_0300
0x44DF_03FF
Power Reset Module MPU Registers
PRM_GFX
0x44DF_0400
0x44DF_0523
Power Reset Module Graphics Controller
Registers
PRM_RTC
0x44DF_0524
0x44DF_0623
Power Reset Module RTC Registers
Reserved
0x44DF_0624
0x44DF_06FF
PRM_CEFUSE
0x44DF_0700
0x44DF_07FF
Power Reset Module Efuse Registers
PRM_PER
0x44DF_0800
0x44DF_1FFF
Power Reset Module Peripheral Registers
PRM_WKUP
0x44DF_2000
0x44DF_27FF
Power Reset Module Wakeup Registers
CM_WKUP
0x44DF_2800
0x44DF_3FFF
Clock Module Wakeup Registers
PRM_DEVICE
0x44DF_4000
0x44DF_40FF
Power Reset Module Device Registers
CM_DEVICE
0x44DF_4100
0x44DF_41FF
Clock Module Device Registers
CM_DPLL
0x44DF_4200
0x44DF_82FF
Clock Module PLL Registers
CM_MPU
0x44DF_8300
0x44DF_83FF
Clock Module MPU Registers
CM_GFX
0x44DF_8400
0x44DF_84FF
Clock Module Graphics Controller Registers
CM_RTC
0x44DF_8500
0x44DF_85FF
Clock Module RTC Registers
Reserved
0x44DF_8600
0x44DF_86FF
CM_CEFUSE
0x44DF_8700
0x44DF_87FF
CM_PER
0x44DF_8800
0x44DF_FFFF
Reserved
0x44E0_0000
0x44E0_0FFF
4KB
Reserved
0x44E0_1000
0x44E0_2FFF
8KB
Reserved
0x44E0_3000
0x44E0_3FFF
4KB
Reserved
0x44E0_4000
0x44E0_4FFF
4KB
DMTIMER0
0x44E0_5000
0x44E0_5FFF
4KB
Reserved
0x44E0_6000
0x44E0_6FFF
4KB
GPIO0
0x44E0_7000
0x44E0_7FFF
4KB
Reserved
0x44E0_8000
0x44E0_8FFF
4KB
Clock Module Efuse Registers
Clock Module Peripheral Registers
UART0
0x44E0_9000
0x44E0_9FFF
4KB
Reserved
0x44E0_A000
0x44E0_AFFF
4KB
I2C0
0x44E0_B000
0x44E0_BFFF
4KB
Reserved
0x44E0_C000
0x44E0_CFFF
4KB
ADC0
0x44E0_D000
0x44E0_DFFF
4KB
DMTimer0 Registers
GPIO0 Registers
UART0 Registers
I2C0 Registers
ADC0 Registers
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Table 2-2. L4_WKUP Memory Map (continued)
Region Name
Start_address (hex)
End_address (hex)
Size
Reserved
0x44E0_E000
0x44E0_EFFF
4KB
Reserved
0x44E0_F000
0x44E0_FFFF
4KB
CONTROL_MODULE 0x44E1_0000
0x44E1_FFFF
64KB
Reserved
0x44E2_0000
0x44E2_FFFF
64KB
Reserved
0x44E3_0000
0x44E3_0FFF
4KB
DMTIMER1_1MS
0x44E3_1000
0x44E3_1FFF
4KB
Reserved
0x44E3_2000
0x44E3_2FFF
4KB
Reserved
0x44E3_3000
0x44E3_3FFF
4KB
Reserved
0x44E3_4000
0x44E3_4FFF
4KB
WDT1
0x44E3_5000
0x44E3_5FFF
4KB
Reserved
0x44E3_6000
0x44E3_6FFF
4KB
Reserved
0x44E3_7000
0x44E3_7FFF
4KB
Reserved
0x44E3_8000
0x44E3_8FFF
4KB
Reserved
0x44E3_9000
0x44E3_9FFF
4KB
Reserved
0x44E3_A000
0x44E3_AFFF
4KB
Reserved
0x44E3_B000
0x44E3_DFFF
12KB
RTCSS
0x44E3_E000
0x44E3_EFFF
4KB
Reserved
0x44E3_F000
0x44E3_FFFF
4KB
DEBUGSS
0x44E4_0000
0x44E7_FFFF
256KB
Reserved
0x44E8_0000
0x44E8_0FFF
4KB
Reserved
0x44E8_1000
0x44E8_1FFF
4KB
Reserved
0x44E8_2000
0x44E8_3FFF
8KB
Reserved
0x44E8_4000
0x44E8_4FFF
4KB
Reserved
0x44E8_5000
0x44E8_5FFF
4KB
SYNCTIMER
0x44E8_6000
0x44E8_6FFF
4KB
Reserved
0x44E8_7000
0x44E8_7FFF
4KB
Reserved
0x44E8_8000
0x44E8_FFFF
32KB
Reserved
0x44E9_0000
0x44E9_0FFF
4KB
Reserved
0x44E9_1000
0x44E9_1FFF
4KB
Reserved
0x44E9_2000
0x44E9_2FFF
4KB
Reserved
0x44E9_3000
0x44E9_FFFF
52KB
Reserved
0x44F0_0000
0x44FF_FFFF
1MB
Reserved
0x4500_0000
0xFFFF_FFFF
2992MB
Description
Control Module Registers
DMTimer1_1ms (accurate 1ms timer)
Registers
Watchdog Timer1 Registers
RTC Registers
Debug Registers
SyncTimer Registers
2.1.3 L4_PER Peripheral Memory Map
Table 2-3. L4_PER Peripheral Memory Map
Device Name
Start_address (hex)
End_address (hex)
Size
Description
L4_PER
0x4800_0000
0x4800_07FF
2KB
Address/Protection (AP)
L4_PER
0x4800_0800
0x4800_0FFF
2KB
Link Agent (LA)
L4_PER_REG
0x4800_1000
0x4800_13FF
1KB
Initiator Port (IP0)
L4_PER_REG
0x4800_1400
0x4800_17FF
1KB
Initiator Port (IP1)
L4_PER_REG
0x4800_1800
0x4800_1BFF
1KB
Initiator Port (IP2)
L4_PER_REG
0x4800_1C00
0x4800_1FFF
1KB
Initiator Port (IP3)
Reserved
0x4800_2000
0x4800_3FFF
8KB
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Table 2-3. L4_PER Peripheral Memory Map (continued)
Device Name
Start_address (hex)
End_address (hex)
Size
Reserved
0x4800_4000
0x4800_7FFF
16KB
Reserved
0x4800_8000
0x4800_8FFF
4KB
Reserved
0x4800_9000
0x4800_9FFF
4KB
Reserved
0x4800_A000
0x4800_FFFF
24KB
Reserved
0x4801_0000
0x4801_0FFF
4KB
Reserved
0x4801_1000
0x4801_1FFF
4KB
Reserved
0x4801_2000
0x4801_FFFF
56KB
Reserved
0x4802_0000
0x4802_0FFF
4KB
Reserved
0x4802_1000
0x4802_1FFF
4KB
UART1
0x4802_2000
0x4802_2FFF
4KB
Reserved
0x4802_3000
0x4802_3FFF
4KB
UART2
0x4802_4000
0x4802_4FFF
4KB
Reserved
0x4802_5000
0x4802_5FFF
4KB
Reserved
0x4802_6000
0x4802_7FFF
8KB
Reserved
0x4802_8000
0x4802_8FFF
4KB
Reserved
0x4802_9000
0x4802_9FFF
4KB
I2C1
0x4802_A000
0x4802_AFFF
4KB
Reserved
0x4802_B000
0x4802_BFFF
4KB
Reserved
0x4802_C000
0x4802_CFFF
4KB
Reserved
0x4802_D000
0x4802_DFFF
4KB
Reserved
0x4802_E000
0x4802_EFFF
4KB
Reserved
0x4802_F000
0x4802_FFFF
4KB
MCSPI0
0x4803_0000
0x4803_0FFF
4KB
Reserved
0x4803_1000
0x4803_1FFF
4KB
Reserved
0x4803_2000
0x4803_2FFF
4KB
Reserved
0x4803_3000
0x4803_3FFF
4KB
Reserved
0x4803_4000
0x4803_4FFF
4KB
Reserved
0x4803_5000
0x4803_5FFF
4KB
Reserved
0x4803_6000
0x4803_6FFF
4KB
Reserved
0x4803_7000
0x4803_7FFF
4KB
MCASP0_CFG
0x4803_8000
0x4803_9FFF
8KB
Reserved
0x4803_A000
0x4803_AFFF
4KB
Reserved
0x4803_B000
0x4803_BFFF
4KB
MCASP1_CFG
0x4803_C000
0x4803_DFFF
8KB
Reserved
0x4803_E000
0x4803_EFFF
4KB
Reserved
0x4803_F000
0x4803_FFFF
4KB
DMTIMER2
0x4804_0000
0x4804_0FFF
4KB
Reserved
0x4804_1000
0x4804_1FFF
4KB
DMTIMER3
0x4804_2000
0x4804_2FFF
4KB
Reserved
0x4804_3000
0x4804_3FFF
4KB
DMTIMER4
0x4804_4000
0x4804_4FFF
4KB
Reserved
0x4804_5000
0x4804_5FFF
4KB
DMTIMER5
0x4804_6000
0x4804_6FFF
4KB
Reserved
0x4804_7000
0x4804_7FFF
4KB
DMTIMER6
0x4804_8000
0x4804_8FFF
4KB
Reserved
0x4804_9000
0x4804_9FFF
4KB
DMTIMER7
0x4804_A000
0x4804_AFFF
4KB
Description
UART1 Registers
UART2 Registers
I2C1 Registers
McSPI0 Registers
McASP0 CFG Registers
McASP1 CFG Registers
DMTimer2 Registers
DMTimer3 Registers
DMTimer4 Registers
DMTimer5 Registers
DMTimer6 Registers
DMTimer7 Registers
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Table 2-3. L4_PER Peripheral Memory Map (continued)
Device Name
Start_address (hex)
End_address (hex)
Size
Reserved
0x4804_B000
0x4804_BFFF
4KB
GPIO1
0x4804_C000
0x4804_CFFF
4KB
Reserved
0x4804_D000
0x4804_DFFF
4KB
Reserved
0x4804_E000
0x4804_FFFF
8KB
Reserved
0x4805_0000
0x4805_1FFF
8KB
Reserved
0x4805_2000
0x4805_2FFF
4KB
Reserved
0x4805_3000
0x4805_FFFF
52KB
MMCSD0
0x4806_0000
0x4806_0FFF
4KB
Reserved
0x4806_1000
0x4806_1FFF
4KB
Reserved
0x4806_2000
0x4807_FFFF
120KB
ELM
0x4808_0000
0x4808_FFFF
64KB
Reserved
0x4809_0000
0x4809_0FFF
4KB
Reserved
0x4809_1000
0x4809_FFFF
60KB
Reserved
0x480A_0000
0x480A_FFFF
64KB
Reserved
0x480B_0000
0x480B_0FFF
4KB
Reserved
0x480B_1000
0x480B_FFFF
60KB
Reserved
0x480C_0000
0x480C_0FFF
4KB
Reserved
0x480C_1000
0x480C_1FFF
4KB
Reserved
0x480C_2000
0x480C_2FFF
4KB
Reserved
0x480C_3000
0x480C_3FFF
4KB
Reserved
0x480C_4000
0x480C_7FFF
16KB
MAILBOX0
0x480C_8000
0x480C_8FFF
4KB
Reserved
0x480C_9000
0x480C_9FFF
4KB
SPINLOCK
0x480C_A000
0x480C_AFFF
4KB
Reserved
0x480C_B000
0x480C_BFFF
4KB
Reserved
0x480C_C000
0x480C_CFFF
4KB
Reserved
0x480C_D000
0x480C_DFFF
4KB
Reserved
0x480C_E000
0x480F_FFFF
200KB
Reserved
0x4810_0000
0x4811_FFFF
128KB
Reserved
0x4812_0000
0x4812_0FFF
4KB
Reserved
0x4812_1000
0x4812_1FFF
4KB
Reserved
0x4812_2000
0x4812_2FFF
4KB
Reserved
0x4812_3000
0x4812_3FFF
4KB
Reserved
0x4812_4000
0x4813_FFFF
112KB
Reserved
0x4814_0000
0x4815_FFFF
128KB
Reserved
0x4816_0000
0x4816_0FFF
4KB
Reserved
0x4816_1000
0x4817_FFFF
124KB
Reserved
0x4818_0000
0x4818_2FFF
12KB
Reserved
0x4818_3000
0x4818_3FFF
4KB
Reserved
0x4818_4000
0x4818_7FFF
16KB
Reserved
0x4818_8000
0x4818_8FFF
4KB
Reserved
0x4818_9000
0x4818_9FFF
4KB
Reserved
0x4818_A000
0x4818_AFFF
4KB
Reserved
0x4818_B000
0x4818_BFFF
4KB
OCP_WP_NOC
0x4818_C000
0x4818_CFFF
4KB
Reserved
0x4818_D000
0x4818_DFFF
4KB
Reserved
0x4818_E000
0x4818_EFFF
4KB
146 Memory Map
Description
GPIO1 Registers
MMCSD0 Registers
ELM Registers
Mailbox Registers
Spinlock Registers
OCP Watchpoint Registers
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Table 2-3. L4_PER Peripheral Memory Map (continued)
Device Name
Start_address (hex)
End_address (hex)
Size
Reserved
0x4818_F000
0x4818_FFFF
4KB
Reserved
0x4819_0000
0x4819_0FFF
4KB
Reserved
0x4819_1000
0x4819_1FFF
4KB
Reserved
0x4819_2000
0x4819_2FFF
4KB
Reserved
0x4819_3000
0x4819_3FFF
4KB
Reserved
0x4819_4000
0x4819_BFFF
32KB
I2C2
0x4819_C000
0x4819_CFFF
4KB
Reserved
0x4819_D000
0x4819_DFFF
4KB
Reserved
0x4819_E000
0x4819_EFFF
4KB
Reserved
0x4819_F000
0x4819_FFFF
4KB
MCSPI1
0x481A_0000
0x481A_0FFF
4KB
Reserved
0x481A_1000
0x481A_1FFF
4KB
MCSPI2
0x481A_2000
0x481A_2FFF
4KB
Reserved
0x481A_3000
0x481A_3FFF
4KB
MCSPI3
0x481A_4000
0x481A_4FFF
4KB
Reserved
0x481A_5000
0x481A_5FFF
4KB
UART3
0x481A_6000
0x481A_6FFF
4KB
Reserved
0x481A_7000
0x481A_7FFF
4KB
UART4
0x481A_8000
0x481A_8FFF
4KB
Reserved
0x481A_9000
0x481A_9FFF
4KB
UART5
0x481A_A000
0x481A_AFFF
4KB
Reserved
0x481A_B000
0x481A_BFFF
4KB
GPIO2
0x481A_C000
0x481A_CFFF
4KB
Reserved
0x481A_D000
0x481A_DFFF
4KB
GPIO3
0x481A_E000
0x481A_EFFF
4KB
Reserved
0x481A_F000
0x481A_FFFF
4KB
Reserved
0x481B_0000
0x481B_FFFF
64KB
Reserved
0x481C_0000
0x481C_0FFF
4KB
DMTIMER8
0x481C_1000
0x481C_1FFF
4KB
Reserved
0x481C_2000
0x481C_2FFF
4KB
Reserved
0x481C_3000
0x481C_9FFF
28KB
Reserved
0x481C_A000
0x481C_AFFF
4KB
Reserved
0x481C_B000
0x481C_BFFF
4KB
DCAN0
0x481C_C000
0x481C_DFFF
8KB
Reserved
0x481C_E000
0x481C_FFFF
8KB
DCAN1
0x481D_0000
0x481D_1FFF
8KB
Reserved
0x481D_2000
0x481D_3FFF
8KB
Reserved
0x481D_4000
0x481D_4FFF
4KB
Reserved
0x481D_5000
0x481D_5FFF
4KB
Reserved
0x481D_6000
0x481D_6FFF
4KB
Reserved
0x481D_7000
0x481D_7FFF
4KB
MMCSD1
0x481D_8000
0x481D_8FFF
4KB
Reserved
0x481D_9000
0x481D_9FFF
4KB
Reserved
0x481D_A000
0x481F_FFFF
152KB
Reserved
0x4820_0000
0x4820_0FFF
4KB
Reserved
0x4820_1000
0x4823_FFFF
252KB
MPU_SCU
0x4824_0000
0x4824_00FF
256B
Description
I2C2 Registers
McSPI1 Registers
McSPI2 Registers
McSPI3 Registers
UART3 Registers
UART4 Registers
UART5 Registers
GPIO2 Registers
GPIO3 Registers
DMTimer8 Registers
DCAN0 Registers
DCAN1 Registers
MMCSD1 Registers
MPU SCU Registers
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Table 2-3. L4_PER Peripheral Memory Map (continued)
Device Name
Start_address (hex)
End_address (hex)
Size
Description
MPU_INTC
0x4824_0100
0x4824_01FF
256B
MPU Interrupt Controller Interfaces
MPU_GBL_TIMER
0x4824_0200
0x4824_02FF
256B
MPU Global Timer
Reserved
0x4824_0300
0x4824_05FF
768B
MPU_PRV_TIMERS
0x4824_0600
0x4824_06FF
256B
Reserved
0x4824_0700
0x4824_0FFF
2304B
MPU_INT_DIST
0x4824_1000
0x4824_1FFF
4KB
MPU Interrupt Distributor
MPU_PL310
0x4824_2000
0x4824_2FFF
4KB
MPU PL310 Programming Registers
Reserved
0x4824_3000
0x4824_3FFF
4KB
Reserved
0x4824_4000
0x4827_FFFF
240KB
Reserved
0x4828_0000
0x4828_0FFF
4KB
MPU_WAKEUP_GEN 0x4828_1000
0x4828_1FFF
4KB
Reserved
0x4828_2000
0x4828_FFFF
56KB
Reserved
0x4829_0000
0x4829_FFFF
64KB
MPU_AXI2OCP
0x482A_0000
0x482A_FFFF
64KB
Reserved
0x482B_0000
0x482F_FFFF
320KB
MPU Private Timers and Watchdog
MPU Wakeup Generator
MPU AXI2OCP Registers
PWMSS0
0x4830_0000
0x4830_00FF
256B
PWMSS0 Configuration Registers
PWMSS0_ECAP
0x4830_0100
0x4830_017F
128B
PWMSS eCAP0 Registers
PWMSS0_EQEP
0x4830_0180
0x4830_01FF
128B
PWMSS eQEP0 Registers
PWMSS0_EPWM
0x4830_0200
0x4830_025F
96B
PWMSS ePWM0 Registers
Reserved
0x4830_0260
0x4830_0FFF
3488B
Reserved
0x4830_1000
0x4830_1FFF
4KB
PWMSS1
0x4830_2000
0x4830_20FF
256B
PWMSS1 Configuration Registers
PWMSS1_ECAP
0x4830_2100
0x4830_217F
128B
PWMSS eCAP1 Registers
PWMSS1_EQEP
0x4830_2180
0x4830_21FF
128B
PWMSS eQEP1 Registers
PWMSS1_EPWM
0x4830_2200
0x4830_225F
96B
PWMSS ePWM1 Registers
Reserved
0x4830_2260
0x4830_2FFF
3488B
Reserved
0x4830_3000
0x4830_3FFF
4KB
PWMSS2
0x4830_4000
0x4830_40FF
256B
PWMSS2 Configuration Registers
PWMSS2_ECAP
0x4830_4100
0x4830_417F
128B
PWMSS eCAP2 Registers
PWMSS2_EQEP
0x4830_4180
0x4830_41FF
128B
PWMSS eQEP2 Registers
PWMSS2_EPWM
0x4830_4200
0x4830_425F
96B
PWMSS ePWM2 Registers
Reserved
0x4830_4260
0x4830_4FFF
3488B
Reserved
0x4830_5000
0x4830_5FFF
4KB
PWMSS3
0x4830_6000
0x4830_60FF
256B
Reserved
0x4830_6100
0x4830_61FF
256B
PWMSS3_EPWM
0x4830_6200
0x4830_625F
96B
Reserved
0x4830_6260
0x4830_6FFF
3488B
Reserved
0x4830_7000
0x4830_7FFF
4KB
PWMSS4
0x4830_8000
0x4830_80FF
256B
Reserved
0x4830_8100
0x4830_81FF
256B
PWMSS4_EPWM
0x4830_8200
0x4830_825F
96B
Reserved
0x4830_8260
0x4830_8FFF
3488B
Reserved
0x4830_9000
0x4830_9FFF
4KB
PWMSS5
0x4830_A000
0x4830_A0FF
256B
Reserved
0x4830_A100
0x4830_A1FF
256B
PWMSS5_EPWM
0x4830_A200
0x4830_A25F
96B
Reserved
0x4830_A260
0x4830_AFFF
3488B
148 Memory Map
PWMSS3 Configuration Registers
PWMSS ePWM3 Registers
PWMSS4 Configuration Registers
PWMSS ePWM4 Registers
PWMSS5 Configuration Registers
PWMSS ePWM5 Registers
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Table 2-3. L4_PER Peripheral Memory Map (continued)
Device Name
Start_address (hex)
End_address (hex)
Size
Reserved
0x4830_B000
0x4830_BFFF
4KB
Reserved
0x4830_C000
0x4830_DFFF
8KB
Reserved
0x4830_E000
0x4830_EFFF
4KB
Reserved
0x4830_F000
0x4830_FFFF
4KB
Reserved
0x4831_0000
0x4831_1FFF
8KB
Reserved
0x4831_2000
0x4831_2FFF
4KB
Reserved
0x4831_3000
0x4831_3FFF
4KB
Reserved
0x4831_4000
0x4831_4FFF
4KB
Reserved
0x4831_5000
0x4831_7FFF
12KB
Reserved
0x4831_8000
0x4831_BFFF
16KB
Reserved
0x4831_C000
0x4831_CFFF
4KB
Reserved
0x4831_D000
0x4831_FFFF
12KB
GPIO4
0x4832_0000
0x4832_0FFF
4KB
Reserved
0x4832_1000
0x4832_1FFF
4KB
GPIO5
0x4832_2000
0x4832_2FFF
4KB
Reserved
0x4832_3000
0x4832_3FFF
4KB
Reserved
0x4832_4000
0x4832_5FFF
8KB
VPFE0
0x4832_6000
0x4832_6FFF
4KB
Reserved
0x4832_7000
0x4832_7FFF
4KB
VPFE1
0x4832_8000
0x4832_8FFF
4KB
Reserved
0x4832_9000
0x4832_9FFF
4KB
Description
GPIO4 Registers
GPIO5 Registers
VPFE0 (Camera) Registers
VPFE1 (Camera) Registers
DSS_TOP
0x4832_A000
0x4832_A3FF
1KB
Display Subsystem Top Registers
DSS_DISPC
0x4832_A400
0x4832_A7FF
1KB
Display Controller Registers
DSS_RFBI
0x4832_A800
0x4832_ABFF
1KB
RFBI Registers
Reserved
0x4832_AC00
0x4832_AFFF
1KB
Reserved
0x4832_B000
0x4832_BFFF
4KB
Reserved
0x4832_C000
0x4832_CFFF
4KB
Reserved
0x4832_D000
0x4833_CFFF
64KB
DMTIMER9
0x4833_D000
0x4833_DFFF
4KB
Reserved
0x4833_E000
0x4833_EFFF
4KB
DMTIMER10
0x4833_F000
0x4833_FFFF
4KB
Reserved
0x4834_0000
0x4834_0FFF
4KB
DMTIMER11
0x4834_1000
0x4834_1FFF
4KB
Reserved
0x4834_2000
0x4834_2FFF
4KB
Reserved
0x4834_3000
0x4834_3FFF
4KB
Reserved
0x4834_4000
0x4834_4FFF
4KB
MCSPI4
0x4834_5000
0x4834_5FFF
4KB
Reserved
0x4834_6000
0x4834_6FFF
4KB
HDQ1W
0x4834_7000
0x4834_7FFF
4KB
Reserved
0x4834_8000
0x4834_8FFF
4KB
Reserved
0x4834_9000
0x4834_AFFF
8KB
Reserved
0x4834_B000
0x4834_BFFF
4KB
ADC1
0x4834_C000
0x4834_DFFF
8KB
Reserved
0x4834_E000
0x4834_EFFF
4KB
Reserved
0x4834_F000
0x4837_FFFF
196KB
USB0_CONTROL
0x4838_0000
0x4839_FFFF
128KB
Reserved
0x483A_0000
0x483A_0FFF
4KB
DMTimer9 Registers
DMTimer10 Registers
DMTimer11 Registers
McSPI4 Registers
HDQ1W Registers
ADC1 Registers
USB0 Controller Registers
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Table 2-3. L4_PER Peripheral Memory Map (continued)
Device Name
Start_address (hex)
End_address (hex)
Size
Reserved
0x483A_1000
0x483A_7FFF
28KB
USB0_PHY
0x483A_8000
0x483A_FFFF
32KB
Reserved
0x483B_0000
0x483B_0FFF
4KB
Reserved
0x483B_1000
0x483B_FFFF
60KB
USB1_CONTROL
0x483C_0000
0x483D_FFFF
128KB
Reserved
0x483E_0000
0x483E_0FFF
4KB
Reserved
0x483E_1000
0x483E_7FFF
28KB
USB1_PHY
0x483E_8000
0x483E_FFFF
32KB
Reserved
0x483F_0000
0x483F_0FFF
4KB
Reserved
0x483F_1000
0x483F_1FFF
4KB
Reserved
0x483F_2000
0x483F_3FFF
8KB
Reserved
0x483F_4000
0x483F_4FFF
4KB
Reserved
0x483F_5000
0x483F_FFFF
44KB
Reserved
0x4840_0000
0x48FF_FFFF
12MB
Description
USB0 PHY Registers
USB1 Controller Registers
USB1 PHY Registers
2.1.4 L4 Fast Peripheral Memory Map
Table 2-4. L4 Fast Peripheral Memory Map
Device Name
Start_address (hex)
End_address (hex)
Size
Description
L4_FAST
0x4A00_0000
0x4A00_07FF
2KB
Address/Protection(AP)
L4_FAST
0x4A00_0800
0x4A00_0FFF
2KB
Link Agent(LA)
L4_FAST_REG
0x4A00_1000
0x4A00_13FF
1KB
Initiator Port(IPO)
Reserved
0x4A00_1400
0x4A00_17FF
1KB
Reserved
0x4A00_1800
0x4A00_1FFF
2KB
Reserved
0x4A00_2000
0x4A07_FFFF
504KB
Reserved
0x4A08_0000
0x4A09_FFFF
128KB
Reserved
0x4A0A_0000
0x4A0A_0FFF
4KB
Reserved
0x4A0A_1000
0x4A0F_FFFF
380KB
32KB
CPSW
0x4A10_0000
0x4A10_7FFF
CPSW_PORT
0x4A10_0100
0x4A10_07FF
Registers
Ethernet Switch Port Control
CPSW_CPDMA
0x4A10_0800
0x4A10_08FF
CPPI DMA Controller Module
CPSW_STATS
0x4A10_0900
0x4A10_09FF
Ethernet Statistics
CPSW_STATERAM
0x4A10_0A00
0x4A10_0BFF
CPPI DMA State RAM
CPSW_CPTS
0x4A10_0C00
0x4A10_0CFF
Ethernet Time Sync Module
CPSW_ALE
0x4A10_0D00
0x4A10_0D7F
Ethernet Address Lookup Engine
CPSW_SL1
0x4A10_0D80
0x4A10_0DBF
Ethernet Sliver for Port 1
CPSW_SL2
0x4A10_0DC0
0x4A10_0DFF
Ethernet Sliver for Port 2
Reserved
0x4A10_0E00
0x4A10_0FFF
CPSW_MDIO
0x4A10_1000
0x4A10_10FF
Reserved
0x4A10_1100
0x4A10_11FF
Ethernet MDIO Controller
CPSW_WR
0x4A10_1200
0x4A10_1FFF
Ethernet Subsystem Wrapper for RMII/RGMII
CPSW_CPPI_RAM
0x4A10_2000
0x4A10_3FFF
Communications Port Programming Interface
Reserved
0x4A10_8000
0x4A10_8FFF
4KB
Reserved
0x4A10_9000
0x4A13_FFFF
220KB
Reserved
0x4A14_0000
0x4A14_FFFF
64KB
Reserved
0x4A15_0000
0x4A15_0FFF
4KB
150 Memory Map
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Table 2-4. L4 Fast Peripheral Memory Map (continued)
Device Name
Start_address (hex)
End_address (hex)
Size
Reserved
0x4A15_1000
0x4A17_FFFF
188KB
Reserved
0x4A18_0000
0x4A19_FFFF
128KB
Reserved
0x4A1A_0000
0x4A1A_0FFF
4KB
Reserved
0x4A1A_1000
0x4A1A_1FFF
4KB
Reserved
0x4A1A_2000
0x4A1A_3FFF
8KB
Reserved
0x4A1A_4000
0x4A1A_4FFF
4KB
Reserved
0x4A1A_5000
0x4A1A_5FFF
4KB
Reserved
0x4A1A_6000
0x4A1A_6FFF
4KB
Reserved
0x4A1A_7000
0x4A1A_7FFF
4KB
Reserved
0x4A1A_8000
0x4A1A_9FFF
8KB
Reserved
0x4A1A_A000
0x4A1A_AFFF
4KB
Reserved
0x4A1A_B000
0x4A1A_BFFF
4KB
Reserved
0x4A1A_C000
0x4A1A_CFFF
4KB
Reserved
0x4A1A_D000
0x4A1A_DFFF
4KB
Reserved
0x4A1A_E000
0x4A1A_FFFF
8KB
Reserved
0x4A1B_0000
0x4A1B_0FFF
4KB
Reserved
0x4A1B_1000
0x4A1B_1FFF
4KB
Reserved
0x4A1B_2000
0x4A1B_2FFF
4KB
Reserved
0x4A1B_3000
0x4A1B_3FFF
4KB
Reserved
0x4A1B_4000
0x4A1B_4FFF
4KB
Reserved
0x4A1B_5000
0x4A1B_5FFF
4KB
Reserved
0x4A1B_6000
0x4A1B_6FFF
4KB
Reserved
0x4A1B_7000
0x4A1F_FFFF
292KB
Reserved
0x4A20_0000
0x4A27_FFFF
512KB
Reserved
0x4A28_0000
0x4A28_0FFF
4KB
Reserved
0x4A28_1000
0x4A2F_FFFF
508KB
Reserved
0x4A30_0000
0x4A37_FFFF
512KB
Reserved
0x4A38_0000
0x4A38_0FFF
4KB
Reserved
0x4A38_1000
0x4A3F_FFFF
508KB
Reserved
0x4A40_0000
0x4A40_1FFF
8KB
Reserved
0x4A40_2000
0x4A40_2FFF
4KB
Reserved
0x4A40_3000
0x4AFF_FFFF
12276KB
Description
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Memory Map
151
Chapter 3
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ARM MPU Subsystem
This chapter describes the MPU Subsystem for the device.
Topic
3.1
3.2
3.3
152
...........................................................................................................................
Page
Introduction ..................................................................................................... 153
Integration ....................................................................................................... 156
Functional Description ...................................................................................... 161
ARM MPU Subsystem
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Introduction
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3.1
Introduction
The microprocessor unit (MPU) subsystem of the device handles transactions between the ARM core
(ARM Cortex-A9 Processor) and the L3 interconnect.
The Cortex-A9 is an ARMv7 compatible, 2-issue, in-order execution pipeline with integrated L1 and L2
caches with a NEON Single Instruction, Multiple Data (SIMD) Media Processing Unit.
The MPU subsystem includes CoreSight compliant logic to allow the debug subsystem access to the
Cortex-A8 debug and emulation resources, including the Embedded Trace Macrocell.
The MPU subsystem includes 256KB of L2 cache. The L2 cache is controlled by a PL310. The CPU is
configured to have 32KB of instruction cache and 32KB of data cache. The CPU includes a NEON and
vector floating point (VFP) (FPU) coprocessors.
Figure 3-1 shows the MPU subsystem top-level block diagram and the power domain partitions.
Figure 3-1. MPU Subsystem Block Diagram
VFP/NEON
L1 I
32KB
System
Interrupts
(224 Interrupts)
WakeUp
Gen
L1 D
32KB
GIC
Cortex-A9MP
PTM Interface
CPU
Timer
SCU
WDT
L2
256KB
PL310
MPU
Subsystem
Sec / Public
ROM
192 / 48KB
AXI2OCP
Bridge
OCM RAM
64KB
Memory
Adaptor
Bridge
MPU PLL
Slave 0
CLK_M_OSC
Frm Master OSC
64
From L3
Master 1
Master 0
64
128
To L3
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3.1.1 Features
This section outlines the key features of the MPU subsection:
• ARM Microprocessor
– Cortex-A9 revision R2P10.
– Symmetric Multi-Processor Architecture (Single CPU Configuration).
– Superscalar, dynamic multi-issue technology with an efficient 8-stage pipeline.
– Continuous fetch and decoding of two instructions per clock cycle.
– Out-of-order (OoO) instruction dispatch and completion.
– Integrated Cortex-A9 NEON Processing Engine (NPE) to enhance the capabilities of the FPU to
include the ARM NEON Advanced SIMD support for accelerated media and signal processing
computation.
– VFPv3-D16 hardware to support single- and double-precision add, subtract, multiply, divide,
multiply and accumulate and square root operations.
– 32KB (L1) instruction and 32KB (L1) data cache with 32B line size and four-way set associative.
– Memory Management Unit (MMU) with a two-level translation lookaside buffer (TLB) organization.
• First level is a 32-entry, fully-associative micro-TLB implemented on each of the instruction and
data sides.
• Second level is a unified, two-way associative, 128-entry main TLB with support for a hardware
TLB table walk.
– Snoop Control Unit (SCU) ensures memory coherency in the system between CPU and other
masters sharing cached data.
– Integrated Timer and Watchdog Timer.
– Integrated symmetric multiprocessing (SMP)-capable generic interrupt controller with 224 shared
peripheral interrupts (SPI).
– Two 64-bit AXI master ports to interface to the L2 controller.
• Supports multiple outstanding transactions
• Supports out-of-order data return
• L2 Cache Controller (PL310)
– 256KB L2 Cache.
– 16-way set associative.
– 32B line size.
– PL310 address filtering function used to split accesses between MA and AXI2OCP
– Two slave ports
– Two master ports.
– Lockdown format C (way locking) for instruction and data.
– Includes four 256-bit line fill buffers (LFB) shared by the master ports.
– Each slave port includes two 256-bit line read buffers (LRB).
– Includes four 256-bit store buffers with merge capability.
– Support for 64-byte line fills issued to L3.
– Support for using the 256KB L2 cache as SRAM. SRAM interface is memory mapped to chip level
L3.
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•
•
•
Debug and Emulation
– CPU debug requirements handled through chip-level debug subsystem.
– Cross trigger interface (CTI) connects to a cross trigger matrix (CTM).
– Includes a trigger interface to convert the TI trigger format to the ARM CTI format.
– Program trace macrocell (PTM) to perform real-time instruction flow tracing based on program flow
trace (PFT) architecture.
– Generates trace only at certain points (waypoints) in program execution to reduce the amount of
trace data generated.
– Implemented in the emulation power domain (WKUP voltage domain).
– A debug bridge connects the external debug OCP port to all the internal APB targets.
AXI2OCP Bridge
– Supports OCP 2.2.
– Connected to PL310 slave port M1.
– Single request, multiple data protocol on port.
– Multiple targets, including two OCP ports (64-bit and 32-bit).
Memory Adaptor
– Connected to PL310 slave port M0.
– Standard OCP 2.3 interface to chip-level L3 interconnect.
– Full-speed interface to the PL310.
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Integration
3.2.1 Clocking, Reset and Power Management
3.2.1.1
Power Management
All power domains are controlled by the global PRCM. The power management supports for debug and
emulation are also controlled by the global PRCM.
3.2.1.2
Clocking Management
The MPU PLL generates the MPU clock for the MPU subsystem, as shown in Figure 3-2.
Figure 3-2. MPU Subsystem Clocking Scheme
MPU Subsystem
/1
PRCM
3.2.1.3
/2
MPU
PLL
CLK_M_OSC
Cortex-A9
NEON + VFP
MPU_CLK
GIC
/1
SCU
/1
PL310
/2
AXI2OCP
Timer/
WDT
WakeUpGen
The WakeUpGen unit is responsible for generating a wakeup event from the incoming interrupts and
enable bits. The WakeUpGen is implemented in the MPU always-on power domain.
3.2.1.3.1 WkUpGen Configuration Registers
The WkUpGen unit has configuration registers which can be accessed via an OCP interface. Table 3-1
summarizes the configuration registers in the WkUpGen unit.
The reserved bits in the WkUpGen configuration registers have the following properties: A) return a 0 on
read and B) no effect on write.
IRQ8 is disabled by default and cannot be used for wake up. All other interrupts are enabled after reset.
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Table 3-1. Summary of Configuration Registers in WkUpGen Unit
RW (1)
Address Offset
Reset
P/S R, SW
0x000
0x0000_0000
CPU0 WakeUp Enable for Interrupts 32
to 63
P/S RW
0x010
0xFFFF_FEFF
WkUpGenEnb_0B
CPU0 WakeUp Enable for Interrupts 64
to 95
P/S RW
0x014
0xFFFF_FFFF
WkUpGenEnb_0C
CPU0 WakeUp Enable for Interrupts 96
to 127
P/S RW
0x018
0xFFFF_FFFF
WkUpGenEnb_0D
CPU0 WakeUp Enable for Interrupts
128 to 159
P/S RW
0x01C
0xFFFF_FFFF
WkUpGenEnb_0E
CPU0 WakeUp Enable for Interrupts
160 to 191
P/S RW
0x020
0xFFFF_FFFF
WkUpGenEnb_0F
CPU0 WakeUp Enable for Interrupts
192 to 223
P/S RW
0x024
0xFFFF_FFFF
WkUpGenEnb_10
CPU0 WakeUp Enable for Interrupts
224 to 255
P/S RW
0x028
0xFFFF_FFFF
AuxCoreBoot0
Registers used by OS to boot of Aux
Core
0x800
0x0000_0000
Reserved
Reserved
PTMsyncreq_mask
[31:8] used by syncreq generation logic.
[7:0] are read-only and read as 0x0
PTMsyncreq_en
[0] used by syncreq generation logic.
[31:1] are read-only and read as 0x0
TimestampCycleLo
TimestampCycleHi
Register
Description
Wkg_control_0
WakeUpGen Control and Status
Register
WkUpGenEnb_0A
(1)
P/S RW
R
0x804
0x0000_0000
0xC00
0x0000_0000
P/S RW
0xC04
0x0000_0000
[31:0] of the 48 bit free running counter.
Reset by PIMPUAONRSTN
P/S R
0xC08
0x0000_0000
[47:32] of the 48 bit free running counter
read as [15:0]. [31:16] are read as 0x0.
Reset by PIMPUAONRSTN
P/S R
0xC0C
0x0000_0000
P/S RW
P/S = Public/secure (privilege or user mode)
R = Read-only
3.2.1.3.1.1 WFI/WFE Control_0 and WFI/WFE Control_1
Figure 3-3 shows the format of the WFI/WFE Control Register. Table 3-2 describes the WFI/WFE Control
Register.
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Figure 3-3. WFI/WFE Control Register
31
30
29
28
27
26
25
24
19
18
17
16
RESERVED
R-0h
23
22
21
20
RESERVED
R-0h
15
14
DOMAINRESE
T
13
12
MPUWARMRE MPUCOLDRES WDTRESETRE
SET
ET
Q
11
10
9
8
RESERVED
EVENTOSTAT
US
STANDBYWFE
STATUS
STANDBYWFI
STATUS
3
2
R-0h
7
6
5
1
0
RESERVED
4
WDTRESET_E
NB
RESERVED
R-0h
R-0h
R-0h
Table 3-2. WFI/WFE Control Register Field Descriptions
Bit
Field
Type
Reset
RESERVED
R
0h
15
DOMAINRESET
RO
0h
Set when the PIDOMAINRSTONLY is asserted (read only).
14
MPUWARMRESET
RWc
0h
Set when the PIMPU_RSTN signal is asserted. Cleared by a write.
13
MPUCOLDRESET
RWc
0h
Set when the PIMPU_PWRON_RSTN signal is asserted. Cleared by
a write.
12
WDTRESETREQ
0h
Set when the WD timer reset request signal from the SCU is
asserted.
11
RESERVED
R
0h
10
EVENTOSTATUS
RWc
0h
Set when a rising edge of EVENTO from CPU is detected. Given
only for visibility/debug purpose.
9
STANDBYWFESTATUS
RWc
0h
Set when a rising edge of StandbyWFE from CPU is detected. Given
only for visibility/debug purpose.
8
STANDBYWFISTATUS
RWc
0h
Set when a rising edge of StandbyWFI from CPU is detected. Given
only for visibility/debug purpose.
31-16
7-2
RESERVED
R
0h
1
WDTRESET_ENB
RW
0h
0
RESERVED
R
0h
Description
Enable Watch Dog Timer Reset assertion. When set to 1’b1, it will
enable POMPU_RESETREQ (mapped to PO_SPARE_B_0) to be
asserted when the Watch Dog timer (in the SCU) of the
corresponding CPU expires.
In the RW column, RWc means a register bit is readable and gets cleared by a write (any input data).
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3.2.1.3.2 WkupGenEnb Registers
Figure 3-4 shows the format of the WkUpGenEnb registers. Table 3-3 describes the WkUpGenEnb
registers.
Each register is 32-bit wide. The LSB is the enable bit for the lowest interrupt line in that group. For
example, bit 0 of WakeUGenEnb_0B is the enable bit for interrupt number 32. The enable bits are reset to
0 and can be set to 1 (by OCP configuration access) to enable the interrupt to wake up the CPU.
Figure 3-4. WkupGenEnb Registers
31
30
29
28
27
26
25
24
WkUpGenEnb[
n+31]
WkUpGenEnb[
n+30]
WkUpGenEnb[
n+29]
WkUpGenEnb[
n+28]
WkUpGenEnb[
n+27]
WkUpGenEnb[
n+26]
WkUpGenEnb[
n+25]
WkUpGenEnb[
n+24]
RW-1h
RW-1h
RW-1h
RW-1h
RW-1h
RW-1h
RW-1h
RW-1h
23
22
21
20
19
18
17
16
WkUpGenEnb[
n+23]
WkUpGenEnb[
n+22]
WkUpGenEnb[
n+21]
WkUpGenEnb[
n+20]
WkUpGenEnb[
n+19]
WkUpGenEnb[
n+18]
WkUpGenEnb[
n+17]
WkUpGenEnb[
n+16]
RW-1h
RW-1h
RW-1h
RW-1h
RW-1h
RW-1h
RW-1h
RW-1h
15
14
13
12
11
10
9
8
WkUpGenEnb[
n+15]
WkUpGenEnb[
n+14]
WkUpGenEnb[
n+13]
WkUpGenEnb[
n+12]
WkUpGenEnb[
n+11]
WkUpGenEnb[
n+10]
WkUpGenEnb[
n+9]
WkUpGenEnb[
n+8]
RW-1h
RW-1h
RW-1h
RW-1h
RW-1h
RW-1h
RW-1h
RW-0h
7
6
5
4
3
2
1
0
WkUpGenEnb[
n+7]
WkUpGenEnb[
n+6]
WkUpGenEnb[
n+5]
WkUpGenEnb[
n+4]
WkUpGenEnb[
n+3]
WkUpGenEnb[
n+2]
WkUpGenEnb[
n+1]
WkUpGenEnb[
n]
RW-1h
RW-1h
RW-1h
RW-1h
RW-1h
RW-1h
RW-1h
RW-1h
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Table 3-3. WkupGenEnb Registers Field Descriptions
160
Bit
Field
Type
Reset
Description
31
WkUpGenEnb[n+31]
RW
1h
WakeUpGen enable for Interrupt line n+31
30
WkUpGenEnb[n+30]
RW
1h
WakeUpGen enable for Interrupt line n+30
29
WkUpGenEnb[n+29]
RW
1h
WakeUpGen enable for Interrupt line n+29
28
WkUpGenEnb[n+28]
RW
1h
WakeUpGen enable for Interrupt line n+28
27
WkUpGenEnb[n+27]
RW
1h
WakeUpGen enable for Interrupt line n+27
26
WkUpGenEnb[n+26]
RW
1h
WakeUpGen enable for Interrupt line n+26
25
WkUpGenEnb[n+25]
RW
1h
WakeUpGen enable for Interrupt line n+25
24
WkUpGenEnb[n+24]
RW
1h
WakeUpGen enable for Interrupt line n+24
23
WkUpGenEnb[n+23]
RW
1h
WakeUpGen enable for Interrupt line n+23
22
WkUpGenEnb[n+22]
RW
1h
WakeUpGen enable for Interrupt line n+22
21
WkUpGenEnb[n+21]
RW
1h
WakeUpGen enable for Interrupt line n+21
20
WkUpGenEnb[n+20]
RW
1h
WakeUpGen enable for Interrupt line n+20
19
WkUpGenEnb[n+19]
RW
1h
WakeUpGen enable for Interrupt line n+19
18
WkUpGenEnb[n+18]
RW
1h
WakeUpGen enable for Interrupt line n+18
17
WkUpGenEnb[n+17]
RW
1h
WakeUpGen enable for Interrupt line n+17
16
WkUpGenEnb[n+16]
RW
1h
WakeUpGen enable for Interrupt line n+16
15
WkUpGenEnb[n+15]
RW
1h
WakeUpGen enable for Interrupt line n+15
14
WkUpGenEnb[n+14]
RW
1h
WakeUpGen enable for Interrupt line n+14
13
WkUpGenEnb[n+13]
RW
1h
WakeUpGen enable for Interrupt line n+13
12
WkUpGenEnb[n+12]
RW
1h
WakeUpGen enable for Interrupt line n+12
11
WkUpGenEnb[n+11]
RW
1h
WakeUpGen enable for Interrupt line n+11
10
WkUpGenEnb[n+10]
RW
1h
WakeUpGen enable for Interrupt line n+10
9
WkUpGenEnb[n+9]
RW
1h
WakeUpGen enable for Interrupt line n+9
8
WkUpGenEnb[n+8]
RW
0h
WakeUpGen enable for Interrupt line n+8
7
WkUpGenEnb[n+7]
RW
1h
WakeUpGen enable for Interrupt line n+7
6
WkUpGenEnb[n+6]
RW
1h
WakeUpGen enable for Interrupt line n+6
5
WkUpGenEnb[n+5]
RW
1h
WakeUpGen enable for Interrupt line n+5
4
WkUpGenEnb[n+4]
RW
1h
WakeUpGen enable for Interrupt line n+4
3
WkUpGenEnb[n+3]
RW
1h
WakeUpGen enable for Interrupt line n+3
2
WkUpGenEnb[n+2]
RW
1h
WakeUpGen enable for Interrupt line n+2
1
WkUpGenEnb[n+1]
RW
1h
WakeUpGen enable for Interrupt line n+1
0
WkUpGenEnb[n]
RW
1h
WakeUpGen enable for Interrupt line n
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3.3
Functional Description
3.3.1 Cortex-A9 MPCore
3.3.1.1
Timer and Watchdog Timer
The Cortex-A9 has its own timer and watchdog timer.
3.3.1.1.1 Power Domain of Timer and Watchdog Timer
The timer and watchdog timer are in the system power and clock domain. When the system is in WFI or
OFF state, the timer will stop running. Software must depend on the timer only when the system power
domain is ON and the DPLL clock is not gated off. If a running timer is required when the system power
domain is off, software must use the system timer at the top-level.
Conversely, since the watchdog timer is in the MPU system power domain, the watchdog timer will
continue to run while the CPU alone is clock-gated (A9 core internal clock gated during WFi and
subsystem (DPLL) clock is running). If the software depends on the watchdog timer to stop when the CPU
is in this mode, the software must disable the watchdog timer before the CPU goes into low-power state.
3.3.1.1.2 Watchdog Registers (Private Timer in ARM Documentation)
For register definitions, see the ARM Cortex-A9 MPCore Technical Reference Manual (available at
infocenter.arm.com/help/index.jsp).
Table 3-4. WATCHDOG REGISTERS
Offset
Register Name
0x00
Private Timer Load
0x04
Private Timer Counter
0x08
Private Timer Control
0x0C
Private Timer Interrupt Status
0x20
Watchdog Load
0x24
Watchdog Counter
0x28
Watchdog Control
0x2C
Watchdog Interrupt Status
0x30
Watchdog Reset Status
0x34
Watchdog Disable
3.3.1.1.3 Global Timer Registers
For register definitions, see the ARM Cortex-A9 MPCore Technical Reference Manual (available at
infocenter.arm.com/help/index.jsp).
Table 3-5. GLOBAL TIMER REGISTERS
Offset
Register Name
0x00, 0x04
Global Timer Counter
0x08
Global Timer Control
0x0C
Global Timer Interrupt Status
0x10, 0x14
Comparator Value
0x18
Auto Increment
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PL310 L2 Cache Controller
For the feature list of the PL310, see Section 3.1.1.
The L2 cache controller on the MPU subsystem is the PL310. The L2 cache controller runs at the full CPU
clock speed and is configured to have two slave ports and two master ports. All four ports are AXI
interfaces with 64-bit data widths. All four ports run at full CPU speed.
The two master ports use load sharing to distribute the transactions. An address filtering mechanism is
implemented but disabled by default. It can be enabled by software, if necessary.
The L2 cache size on the MPU subsystem is 256KB. The cache is configured as 16-way set associative,
with a 32B line size. The L2 cache controller performs critical word first refilling with a pseudo-random
cache replacement policy.
Parity checking is disabled on the L2 cache and parity bits are not implemented.
By default, the PL310 transforms all “shared” non-cacheable accesses to cacheable no-allocate for reads,
or write-through no write-allocate for writes. This is the desired behavior for the MPU subsystem because
the share bit must be set for coherent memory. The share attribute override feature (bit 22 of Auxiliary
Control Register) must be disabled (that is, left in default state) in the PL310.
Cache lockdown by line and cache lockdown by master are implemented.
The PL310 includes logic to support cache event monitoring. All events that are monitored are routed to
the HWDBG port.
The PL310 may be configured to generate interrupts on error conditions or event counter overflow and
increment. The PL310 interrupt is routed to interrupt #0. When an interrupt occurs, software may look at
register 2 (interrupt register) to determine the source of the interrupt.
3.3.1.2.1 PL310 Registers
For register definitions, see the CoreLink Level 2 Cache Controller L2C-310 Technical Reference Manual
Revision: r3p2 (available at infocenter.arm.com/help/index.jsp).
Table 3-6. PL310 REGISTERS
Offset
Register Name
0x000 - 0x0FC
Cache ID and Cache Type
0x100 - 0x1FC
Control
0x200 - 0x2FC
Interrupts and Counter Control
0x300 - 0x6FC
Reserved
0x700 - 0x7FC
Cache Maintenance Operations
0x800 - 0x8FC
Reserved
0x900 - 0x9FC
Cache Lockdown
0xA00 - 0xBFC
Reserved
0xC00 - 0xCFC
Address Filtering
0xD00 - 0xEFC
Reserved
0xF00 - 0xFFC
Debug, Prefetch, and Power
3.3.1.2.2 L2 as SRAM
The MPU subsystem supports usage of the 256KB L2 cache as general-purpose SRAM. The L2 cache
comes up as disabled after reset. Software must ensure that the L2 cache is not enabled in this use case.
Part usage of L2 as cache and part as SRAM is not supported.
L2 SRAM is memory mapped as a slave port on the chip-level interconnect. The MPU subsystem
supports an OCMC64 module that converts the OCP accesses into SRAM accesses. The SRAM signals
are muxed with the signals from PL310.
The input port PIUSEL2SRAM signal controls whether the PL310 path is used or the OCMC path. See the
CTRL_MPU_L2 register.
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The OCMC module is in the MPU voltage and power domain and is asynchronous to the chip-level L3
clock domain. The OCMC module can be clocked by MPU_CLK/2, MPU_CLK/3, MPU_CLK/4, or
MPU_CLK/6. The input pin PIL2SRAMCLKDIV[1:0] determines the divide ratio.
00 - MPU_CLK/2
01 - MPU_CLK/3
10 - MPU_CLK/4
11 - MPU_CLK/6
NOTE: Always ensure that the OCMC (L2) is clocked at a frequency lower or equal to the chip-level
L3 clock frequency by using the appropriate divide ratios. The ASYNC bridge on the OCMC
path does not support response flow control, and if the above restriction is not posed, it could
lead to a hang scenario because the OCMC can give responses faster than the rate at which
the L3 can accept them.
In addition, changing the divide ratio (PIL2SRAMCLKDIV) or changing the L2 from cache to
SRAM (PIUSEL2SRAM) dynamically is not permitted.
3.3.1.2.3 Power and Clock Gating Concerns
The MPU power domain must be ON while using the L2 as SRAM because the OCMC controller resides
in the MPU power domain.
The MPU PLL cannot be clock-gated when OCMC is used for mapping L2 as SRAM because the OCMC
controller receives the clock from the MPU PLL (see Figure 3-5). The MPU PLL supplies a clock to all of
the MPU subsystem components, including the CPU. To achieve lower power in this use case, you must
use CPU-level clock gating (inside the Cortex-A9).
For more details on CPU-level clock gating, see Section 3.2, Integration.
Figure 3-5. L2 Usage as SRAM
PL 310
OCMC_64
256 K L2 Cache
T2 ASYNC
PIUSEL 2SRAM
I2 ASYNC
TA_OCMC
L3 Interconnect
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Generalized Interrupt Controller (GIC)
For details about the GIC, see the ARM Cortex-A9 MPCore Technical Reference Manual (available at
infocenter.arm.com/help/index.jsp). The Cortex-A9 GIC shares the same programmer's model as the GICPL390.
3.3.1.3.1 Interrupts
The first 32 interrupts are mapped internally in the ARM MPU subsystem. For details on the available
interrupts, see the ARM Cortex-A9 MPCore Technical Reference Manual (available at
infocenter.arm.com/help/index.jsp).
There are also an additional 224 shared peripheral interrupts (SPI) which are external to the ARM MPU
subsystem. For SPI interrupt definitions, see Chapter 8, Interrupts.
3.3.1.3.2 Distributor Registers
For register definitions, see the ARM Cortex-A9 MPCore Technical Reference Manual (available at
infocenter.arm.com/help/index.jsp).
Table 3-7. DISTRIBUTOR REGISTERS
164
Offset
Register Name
0x000
Distributor Control
0x004
Interrupt Controller Type
0x008
SCU CPU Power Status
0x00C - 0x7C
Reserved
0x080 - 0x09C
Interrupt Security
0x100 - 0x11C
Interrupt Set-Enable
0x180 - 0x19C
Interrupt Clear-Enable
0x200 - 0x27C
Interrupt Set-Pending
0x280 - 0x29C
Interrupt Clear-Pending
0x300 - 0x31C
Active Bit
0x380 - 0x3FC
Reserved
0x400 - 0x4FC
Interrupt Priority Registers
0xBFC
Reserved
0xC00 - 0xC3C
Interrupt Configuration
0xD00
PPI Status
0xD04 - 0xD1C
SPI Status
0xD80 - 0xEFC
Reserved
0xF00
Software Generated Interrupt
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3.3.1.3.3 Interrupt Controller (INTC) Interface Registers
For register definitions, see the ARM Cortex-A9 MPCore Technical Reference Manual (available at
infocenter.arm.com/help/index.jsp).
Table 3-8. INTC REGISTERS
3.3.1.4
Offset
Register Name
0x000
CPU Interface Control
0x004
Interrupt Priority Mask
0x008
Binary Point Register
0x00C
Interrupt Acknowledge
0x010
End of Interrupt
0x014
Running Priority
0x018
Highest Pending Interrupt
0x01C
Aliased Non-Secure Binary Point
0x0FC
CPU Interface Implementer ID
Snoop Control Unit (SCU)
The SCU connects the Cortex-A9 processor to the memory system through the AXI interfaces.
The SCU functions is to initiate L2 AXI memory accesses.
NOTE: The Cortex SCU does not support hardware management of coherency of the instruction
cache.
3.3.1.4.1 SCU Registers
For register definitions, see the ARM Cortex-A9 MPCore Technical Reference Manual (available at
infocenter.arm.com/help/index.jsp).
Table 3-9. SCU REGISTERS
3.3.1.5
Offset
Register Name
0x00
SCU Control
0x04
SCU Configuration
0x08
SCU CPU Power Status
0x0C
SCU Invalidate All Registers in Secure State
0x40
Filtering Start Address
0x44
Filtering End Address
0x50
SCU Access Control (SAC)
0x54
SCU Non-secure Access Control
AXI2OCP Interface
The AXI2OCP bridge is used to connect the AXI bus on the ARM A9 to the OCP native L3 interconnect
(64-bit widths) and interrupt controller. The AXI2OCP bridge converts between AXI and OCP protocols
and maintains a mapping of AXI tags to the OCP Tag ID.
3.3.1.6
Memory Adaptor
The memory adaptor bridge is used to connect the AXI bus on the ARM A9 to the OCP native L3
interconnect (128-bit width). The memory adaptor contains logic to minimize cache miss latency.
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Configuration Options
This section provides the configurable design options for the Cortex-A9.
166
Feature
Selected Option
Cortex-A9 processors
One
Instruction Cache Size
32KB
Data Cache Size
32KB
TLB size
128-entry
VFP / NEON
Included
Jazelle DBX extension
Included
Program Trace Macrocell (PTM)
Included
Power off and Dormant Wrappers
Included
Support for Parity Error Detection
Not Included
Accelerator Coherency Port
Included
Shared Peripheral Interrupts
224
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Interconnects
This chapter describes the interconnects of the device.
Topic
4.1
...........................................................................................................................
Page
Introduction ..................................................................................................... 168
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Introduction
4.1
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Introduction
The system interconnect is based on a 2-level hierarchical architecture (L3, L4) driven by system
performance. The L4 interconnect is based on a fully native OCP infrastructure, directly complying with the
OCPIP2.2 reference standard.
4.1.1 Terminology
The following is a brief explanation of some terms used in this document:
Initiator: Module able to initiate read and write requests to the chip interconnect (typically: processors,
DMA, etc.).
Target: Unlike an initiator, a target module cannot generate read/write requests to the chip interconnect,
but it can respond to these requests. However, it may generate interrupts or a DMA request to the system
(typically: peripherals, memory controllers). Note: A module can have several separate ports; therefore, a
module can be an initiator and a target.
Agent: Each connection of one module to one interconnect is done using an agent, which is an adaptation
(sometimes configurable) between the module and the interconnect. A target module is connected by a
target agent (TA), and an initiator module is connected by an initiator agent (IA).
Interconnect: The decoding, routing, and arbitration logic that enable the connection between multiple
initiator modules and multiple target modules connected on it.
Register Target (RT): Special TA used to access the interconnect internal configuration registers.
Data-flow Signal: Any signal that is part of a clearly identified transfer or data flow (typically: command,
address, byte enables, etc.). Signal behavior is defined by the protocol semantics.
Sideband Signal: Any signal whose behavior is not associated to a precise transaction or data flow.
Command Slot: A command slot is a subset of the command list. It is the memory buffer for a single
command. A total of 32 command slots exist.
Out-of-band Error: Any signal whose behavior is associated to a device error-reporting scheme, as
opposed to in-band errors. Note: Interrupt requests and DMA requests are not routed by the interconnect
in the device.
ConnID: Any transaction in the system interconnect is tagged by an in-band qualifier ConnID, which
uniquely identifies the initiator at a given interconnect point. A ConnID is transmitted in band with the
request and is used for error-logging mechanism.
4.1.2 L3 Interconnect
The L3 high-performance interconnect is based on a Network-On-Chip (NoC) interconnect infrastructure.
The NoC uses an internal packet-based protocol for forward (read command, write command with data
payload) and backward (read response with data payload, write response) transactions. All exposed
interfaces of this NoC interconnect, both for Targets and Initiators; comply with the OCPIP2.2 reference
standard.
4.1.2.1
L3 Topology
The L3 topology is driven by performance requirements, bus types, and clocking structure. The main L3
paths are shown in Figure 4-1. Arrows indicate the master/slave relationship not data flow. L3 is
partitioned into two separate clock domains: L3F corresponds to L3 Fast clock domain and L3S
corresponds to L3 Slow clock domain.
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Figure 4-1. L3 Topology
VPFE
0
MPUSS
(Cortex-A9)
SGX530
2 Port
GEMAC
Switch
1
TPTC
3 Channels
DSS
R0 W0 R1 W1 R2 W2
128
32
128
64
32
128 128 128 128 128 128
USB
PRU-ICSS0/1
PRU0 PRU1
32
32
32
Debug
Acc
Port
0
1
64
32
IEEE
1500
L3F
128
32
0
32
1
32
32
2
TPTC CFG
EMIF
64
64
OCMC
RAM
TPCC
64
FR
L4_WKUP
SGX530
MPUSS
L2 RAM
32
OCP-WP
32
64
L3S
32
32
32
32
32
32
L4_FAST
32
32
32
32
32
McASP0
ADC0
32
32
GPMC
32
32
MMCSD
32
L4_PER
ADC1
McASP1
QSPI
L4_WKUP
DebugSS
PRU_ICSS0/1
4.1.2.2
L3 Port Mapping
Each initiator and target core is connected to the L3 interconnect through a Network Interface Unit (NIU).
The NIUs act as entry and exit points to the L3 Network-on-Chip (NoC) – converting between the IP’s
OCP protocol and the NoC’s internal protocol, and also include various programming registers. All ports
are single threaded with tags used to enable pipelined transactions. The interconnect includes:
Initiator Ports:
• L3F
– Cortex A9 MPUSS 128-bit initiator port0 and 64-bit initiator port1
– SGX530 128-bit initiator port
– 3 EDMA3TC (TPTC) 128-bit read initiator ports
– 3 EDMA3TC (TPTC) 128-bit write initiator ports
– 2 PRU-ICSS0/1 32-bit initiator ports
– 2 port Gigabit Ethernet Switch (CPGSW) 32-bit initiator port
– Debug Subsystem 32-bit initiator port
– VPFE0 32-bit initiator port
– VPFE1 32-bit initiator port
– DSS 32-bit initiator port
• L3S
– 2 USB 64-bit initiator ports
– P1500 32-bit initiator port
Target Ports:
• L3F
– EMIF 128-bit target port
– 3 EDMA3TC (TPTC) CFG 32-bit target ports
– EDMA3CC (TPCC) CFG 32-bit target port
– OCMC RAM0 64-bit target port
– DebugSS 32-bit target port
– SGX530 64-bit target port
– L4_FAST 32-bit target port
– PRU-ICSS0/1 32-bit target port
– MPUSS L2 RAM
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Introduction
•
4.1.2.3
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L3S
– 4 L4_PER peripheral 32-bit target ports
– GPMC 32-bit target port
– McASP0 32-bit target port
– McASP1 32-bit target port
– QSPI 32-bit target port
– ADC0 32-bit target port
– MMCSD 32-bit target port
– L4_WKUP wakeup 32-bit target port
– ADC1 FIFO 32-bit target port
Interconnect Connections
The L3 connections between bus masters and slave ports are shown in Table 4-1. The L3 interconnect
will return an address-hole error if any initiator attempts to access a target to which it has no connection.
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Table 4-1. L3 Master — Slave Connectivity
TPTC0 RD
X
X
X
X
X
TPTC0 WR
X
X
X
X
X
TPTC1 RD
X
X
X
X
TPTC1 WR
X
X
X
TPTC2 RD
X
X
TPTC2 WR
X
X
PRU-ICSS (PRU0)
X
X
X
PRU-ICSS (PRU1)
X
X
X
GEMAC
X
X
X
SGX530
X
X
USB0
X
X
X
USB1
X
X
X
EMU (DAP)
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
IEEE1500
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
DSS
X
X
X
X
VPFE0
X
X
X
X
VPFE1
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
L4_PER Port3
X
L4_PER Port2
X
L4_PER Port1
X
PRU-ICSS1
X
QSPI
X
ADC1 FIFO / DMA
X
NOC Regs
X
DebugSS
L4_PER Port0
X
L4_WKUP
L4_Fast
X
MMCSD2 / DMA FIFO
SGX530
X
ADC0 FIFO / DMA
TPCC
X
GPMC
TPTC0–2 CFG
X
MPUSS M2 (64-bit)
Masters
McASP0-1
MPUSS L2 RAM
MPUSS M1 (128-bit)
EMIF
OCMC-RAM
Slaves
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
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ConnID Assignment
Each L3 initiator includes a unique 6-bit master connection identifier (MConnID) that is used to indentify
the source of a transfer request.
Table 4-2. MConnID Assignment
Initiator
6-bit MConnID (Debug)
Instrumentation
Comment
MPUSS M1 (128-bit)
0x00
0
Connects only to EMIF
MPUSS M2 (64-bit)
0x01
SW
DAP
0x04
SW
P1500
0x05
SW
PRU-ICSS0/1 (PRU0)
0x0C
SW
PRU-ICSS0/1 (PRU1)
0x0D
SW
Wakeup Processor
0x14
SW
TPTC0 Read
0x18
0
TPTC0 Write
0x19
SW
TPTC1 Read
0x1A
0
TPTC1 Write
0x1B
0
TPTC2 Read
0x1C
0
TPTC2 Write
0x1D
0
SGX530
0x20
0
OCP WP Traffic Probe
0x21 (1)
HW
Direct connect to DebugSS
OCP WP DMA Profiling
0x22 (1)
HW
Direct connect to DebugSS
(1)
HW
Direct connect to DebugSS
OCP-WP Event Trace
0x23
DSS
0x25
0
VPFE0
0x2C
0
VPFE1
0x2D
0
GEMAC
0x30
0
USB0_RD
0x34
0
USB0_WR
0x35
0
USB1_RD
0x36
0
USB1_WR
0x37
0
Stat Collector 0
0x3C
HW
Stat Collector 1
0x3D
HW
Stat Collector 2
0x3E
HW
Stat Collector 3
0x3F
HW
(1)
One WR port for data logging
These MConnIDs are generated within the OCP-WP module based on the H0, H1, and H2 configuration parameters.
NOTE:
172
Connects only to L4_WKUP
Interconnects
Instrumentation refers to debug type. SW instrumentation means that the master can write
data to be logged to the STM (similar to a printf()). HW indicates debug data captured
automatically by hardware. A '0' entry indicates no debug capability.
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4.1.3 L4 Interconnect
The L4 interconnect is a non-blocking peripheral interconnect that provides low latency access to a large
number of low bandwidth, physically dispersed target cores. Each L4 can handle incoming traffic from up
to four initiators and can distribute those communication requests to and collect related responses from up
to 63 targets.
This device provides three interfaces with L3 interconnect for High Speed Peripheral, Standard Peripheral,
and Wakeup Peripherals. Figure 4-2 shows the L4 bus architecture and memory-mapped peripherals.
Figure 4-2. L4 Topology
L3
Wakeup Processor
32
32
32
32
L4_PER
DCAN0
DCAN1
DMTIMER2
DMTIMER3
DMTIMER4
DMTIMER5
DMTIMER6
DMTIMER7
DMTIMER8
DMTIMER9
DMTIMER10
DMTIMER11
eCAP/eQEP/ePWM0
eCAP/eQEP/ePWM1
eCAP/eQEP/ePWM2
eCAP/eQEP/ePWM3
eCAP/eQEP/ePWM4
eCAP/eQEP/ePWM5
eFuse Ctl
ELM
GPIO1
GPIO2
GPIO3
GPIO4
GPIO5
I2C1
I2C2
IEEE1500
32
L4_FAST
DSS
HDQ1W
USB_OTG0
USB_OTG1
USB_PHY0
USB_PHY1
Mailbox0
McASP0 CFG
McASP1 CFG
MMCSD0
MMCSD1
OCP Watchpoint
SPI0
SPI1
SPI2
SPI3
SPI4
Spinlock
UART1
UART2
UART3
UART4
UART5
VPFE0
VPFE1
ADC1
GEMAC
32
32
L4_WKUP
Control Module
DMTIMER0
DMTIMER1_1MS
GPIO0
I2C0
UART0
WDT1
PRCM
SYNCTIMER32K
RTC
ADC0
DebugSS
HWMaster1
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Initialization
This chapter describes the initialization of the device.
Topic
...........................................................................................................................
5.1
5.2
174
Initialization
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Functional Description ...................................................................................... 175
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5.1
Introduction
This section describes the booting functionality of the device, referred hereafter as ROM Code. The
booting functionality covers the following features:
• Memory Booting: booting the device by executing firmware stored on permanent memories like flashmemory or memory cards. This process usually occurs after a cold or warm reset of the device.
• Peripheral Booting: booting the device by downloading the executable code over a communication
interface such as UART, USB, or Ethernet. This process is can also be used to flash a device.
The device always starts in secure mode. The Secure ROM Code handles early initialization. The Secure
ROM code switches the device into public mode. Hence the Public ROM Code provides run-time services
for cache maintenance.
5.2
Functional Description
5.2.1 Architecture
Figure 5-1 shows the architecture of the Public ROM Code. It is split into three main layers with a topdown approach: high-level, drivers, and hardware abstraction layer (HAL). One layer communicates with a
lower level layer through a unified interface.
• The high-level layer implements the main tasks of the Public ROM Code: watchdog and clocks
configuration and main booting routine.
• The driver layer implements the logical and communication protocols for any booting device in
accordance with the interface specification.
• The HAL implements the lowest level code for interacting with the hardware infrastructure IPs. End
booting devices attach to device IO pads.
Figure 5-1. Public ROM Code Architecture
HLOS
Public ROM Code
(High Level)
MAIN
CLOCKS
RNDIS
BOOTING
SEC_ENTRY
FAT
XMODEM
SWCFG
SYSTEM
DFT
BOOTP
TFTP
Public ROM Code drivers
USB_MS
EMAC
UART
USB_CL
SPI
NOR
NAND
MMCSD
QSPI
Public ROM Code HAL
USB_CL
QSPI
USB_MS
DMTIMER1MS
MMCSD
GPMC
ELM
WDTIMER
CKGEN
I2C
SPI
CONTROL
PRM
CM
UART
NOR
HW
MMC / SD cards
NAND flash
SPI flash
NOR flash
QSPI flash
USB
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5.2.2 Functionality
Figure 5-2 shows the high-level flow for the Public ROM Code booting procedure. The Public ROM Code
starts after the secure startup. The ROM Code then performs platform configuration and initialization as
part of the public start-up procedure.
The booting device list is based on the SYSBOOT pins. A booting device can be a memory booting device
(soldered flash memory or temporarily booting device like memory card) or a peripheral interface
connected to a host.
The main loop of the booting procedure searches the booting device list for an image from the currently
selected booting device. This loop exits if a valid booting image is found and successfully executed or if
the watchdog expires.
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Figure 5-2. Public ROM Code Boot Procedure
From power-on reset
Secure startup
(secure mode)
Public startup
Set up the booting
device list
Last device?
No
Take next device from list
Yes
Take first device from list
Yes
Memory device?
Copy the ISW from
memory booting device
No
Download the ISW from the
peripheral booting device
Yes
No
More sectors
available to search
for redundant
image?
No
Search for
redundant image
Image found?
Success?
No
Yes
Yes
HS device?
No
Image copy to
secure SRAM
(secure mode)
Image authentication
(secure mode)
No
Authentication
succeeds?
(secure mode)
Yes
Image execution
5.2.3 Memory Map
5.2.3.1
Public ROM Memory Map
Figure 5-3 shows the on-chip ROM memory map. The top holds the Public ROM Code. The Public ROM
Code mapping includes:
• Exception vectors
• CRC
• Dead loops collection
• Code and const data sections
• ROM Version
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Figure 5-3. ROM Memory Map
0x3FFFC for PG1.2
(0x3BFFC in PG1.1)
ROM Version
Public ROM
64KB
0x3FFFC for PG1.2
(0x3BFFC in PG1.1)
0x30000
Code
0x30100
Secure ROM
176KB
Dead loops
0x30080
Public ROM CRC
0x30020
ROM Exc. Vectors
0x00000
5.2.3.1.1 Public ROM Exception Vectors
Table 5-1 lists the Public ROM exception vectors. These vectors handle the standard exceptions that
occur during the code execution. For example, if there is an issue accessing the memory region, it will
generate a data abort exception when trying to read or write into that memory. The reset exception is
redirected to the Public ROM Code startup. Other exceptions are redirected to their RAM handlers by
loading appropriate addresses into the PC register.
Table 5-1. Public ROM Exception Vectors
Address
Exception
Content
30000h
Reset
Branch to the Public ROM Code startup
30004h
Undefined
PC = 40338E04h
30008h
SWI
PC = 40338E08h
3000Ch
Pre-fetch abort
PC = 40338E0Ch
30010h
Data abort
PC = 40338E10h
30014h
Unused
PC = 40338E14h
30018h
IRQ
PC = 40338E18h
3001Ch
FIQ
PC = 40338E1Ch
5.2.3.1.2 Public ROM Code CRC
The Public ROM Code CRC is calculated as 32-bit CRC code (CRC-32-IEEE 802.3) for the address range
30000h – 3FFFCh for PG1.2 (0x3BFFC for PG1.1). The 4-byte CRC code is stored at location 30020h.
5.2.3.1.3 Dead Loops
Table 5-2 lists the built-in dead loops used for different purposes. All dead loops are branch instructions
coded in ARM mode. The fixed location of these dead loops facilitates debugging and testing. The first
seven dead loops are linked to default ROM exception handlers mentioned in Table 5-1 using RAM
exception vectors mentioned in Table 5-4 and Table 5-5.
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Table 5-2. Dead Loops
Address
Purpose
30080h
Undefined exception default handler
30084h
SWI exception default handler
30088h
Pre-fetch abort exception default handler
3008Ch
Data abort exception default handler
30090h
Unused exception default handler
30094h
IRQ exception default handler
30098h
FIQ exception default handler
3009Ch
Validation tests PASS
300A0h
Validation tests FAIL
300A4h
Reserved
300A8h
Image not executed or returned.
300Ach
Reserved
300B0h
Reserved
300B4h
Reserved
300B8h
Reserved
300BCh
Reserved
5.2.3.1.4 Code
This space is used to hold code and constant data.
5.2.3.1.5 Public ROM Code Version
The ROM Code version includes two decimal numbers: major and minor. The version identifies the ROM
Code release version in a given IC. The ROM Code version is a 32-bit hexadecimal value located at
address 3FFFCh for PG1.2 (0x3BFFC for PG1.1). The minor Version is represented by the 1st byte and
the major version is represented by the 2nd byte.
5.2.3.2
Public L3 RAM Memory Map
The Public ROM Code makes use of the on chip RAM module connected to the L3 interconnect (referred
hereafter as L3 RAM). Its usage is shown in Figure 5-4. The Public L3 RAM memory map ranges from
address 402F0000h to 4033FFFFh.
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Figure 5-4. Public L3 RAM Memory Map
0x4033FFFF
Static Variables
Tracing Data
0x40338E40
0x40338E20
Public RAM
0x40338E00
0x40337E00
0x40337C00
Exc. Handlers Location
RAM Exc. Vectors
8KB Public Stack
(1)
Boot Error Counter
Reserved
0x40337DE0
Reserved on HS
(1)
(1)
(1)
(1)
Downloaded Image
0x402F0000
0x40300000 (HS)
Reserved
(not accessible)
0x402F4000(GP) for PG1.2
(0x402F0400(GP) for PG1.1)
0x402F0000
(1)
Reserved for ROM use.
5.2.3.2.1 Downloaded Image (ISW)
This area is used by the Public ROM Code to store the downloaded Initial SW. The downloaded image
can be up to 271KB on GP Device. It resides from 0x402F4000 (0x402F0400 for PG1.1) to 0x40337C00
in GP device.
Note: If ROM boots using USB_MS boot mode, then the image can reside only from 0x40300000. This
limits the maximum image size while using USB_MS boot mode to 220KB.
5.2.3.2.2 Boot Error Counters
Boot error counter registers contain the number of attempts a particular boot mode has failed after a cold
reset. Each boot mode error counter is 32 bits wide The device numbers 1, 2, 3, 4 mentioned are the
sequential number in which boot modes are tried with a particular set of sysboot pin configuration. The
SYSBOOT pin configuration is given in Table 5-10.
Table 5-3. Boot Error Counters
Address
Boot Mode
40337DE0h
Device No. 1
40337DE4h
Device No. 2
40337DE8h
Device No. 3
40337DECh
Device No. 4
5.2.3.2.3 Public Stack
Space reserved for stack.
5.2.3.2.4 RAM Exception Vectors and Exception Handlers Location
The RAM exception vectors enable a simple means to redirect exceptions to custom handlers. Table 5-4
shows content of the RAM space reserved for RAM vectors. The first seven addresses are ARM
instructions which load the value located in the subsequent seven addresses into the PC register. These
instructions execute when an exception occurs since they are called from the ROM exception vectors.
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Table 5-4. RAM Exception Vectors
Address
Exception
Content
40338E00h
Reserved
Reserved
40338E04h
Undefined
PC = [40338E24h]
40338E08h
SWI
PC = [40338E28h]
40338E0Ch
Pre-fetch abort
PC = [40338E2Ch]
40338E10h
Data abort
PC = [40338E30h]
40338E14h
Unused
PC = [40338E34h]
40338E18h
IRQ
PC = [40338E38h]
40338E1Ch
FIQ
PC = [40338E3Ch]
As Table 5-5 shows, Undefined, SWI, Unused and FIQ exceptions are redirected to a hardcoded dead
loop. Pre-fetch abort, data abort, and IRQ exception are redirected to pre-defined ROM handlers. User
code can redirect any exception to a custom handler by writing its address to the appropriate location from
4033D024h to 4033D03Ch or by overriding the branch (load into PC) instruction between addresses from
4033D004h to 4033D01Ch.
Table 5-5. RAM Exception Handlers Location
Address
Exception
Content
40338E20h
Reserved
30090h
40338E24h
Undefined
30080h
40338E28h
SWI
30084h
40338E2Ch
Pre-fetch abort
Address of default pre-fetch abort
handler (1)
40338E30h
Data abort
Address of default data abort handler (1)
40338E34h
Unused
30090h
40338E38h
IRQ
Address of default IRQ handler
40338E3Ch
FIQ
30098h
(1)
For more details, see Section 5.2.3.1.1, Public ROM Exception Vectors.
5.2.3.2.5 Tracing Data
This area contains trace vectors reflecting the execution path of the public boot. Section 5.2.12, Tracing,
describes the different trace vectors and lists all the possible trace codes.
Table 5-6. Tracing Data
Address
Size (bytes)
Description
40338E40h
4
Current tracing vector, word 1
40338E44h
4
Current tracing vector, word 2
40338E48h
4
Current tracing vector, word 3
40338E4Ch
4
Current tracing vector, word 4
40338E50h
4
Current tracing vector, word 5
40338E54h
4
Reserved
40338E58h
4
Reserved
40338E5Ch
4
Reserved
40338E60h
4
Reserved
40338E64h
4
Reserved
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5.2.3.2.6 Static Variables
This area contains the ROM Code static variables used during boot time.
5.2.3.3
Public ROM Exception Handling
When an exception occurs, ROM Code branches to the corresponding ROM Exception Handler. The ROM
exception handler changes the PC value to the RAM Exception Vectors (ROM specific). The instruction at
RAM Exception Vectors (ROM specific) contains an instruction to change the PC to the value written at
Exception Handlers Location (User Modifiable). In this location, the default value is the location of
deadloops. The user can overwrite these values to point to their specific Exception Handlers.
For example, if Undefined Instruction Abort, the flow is:
30004h → 40338E04h (Load PC with value at 40338E24h) → 30080h {Deadloop}
Figure 5-5. The ROM Exception Handling Flow
ROM Exception
Handler
RAM Exception
Handler
(A)
Exception Handler
Location
(User Modifiable)
(B)
Deadloop
(Default in ROM
A
Instruction to load the PC with the value at the exception handler location.
B
User code can update values here to point to their specific exception handler.
5.2.3.3.1 Specific Cases of Abort Handlers
The default handlers for pre-fetch and data abort perform reads from CP15 debug registers to retrieve the
reason of the abort
5.2.3.3.1.1 Prefetch Abort
If pre-fetch abort: the IFAR register is read from CP15 and stored in R0. The IFSR register is read and
stored in the R1 register. Then the ROM Code jumps to the pre-fetch abort dead loop (30088h).
5.2.3.3.1.2 Data Abort
If data abort: the DFAR register is read from CP15 and stored in R0. The DFSR register is read and
stored in the R1 register. Then the ROM Code jumps to the data abort dead loop (3008Ch).
5.2.4 Start-up and Configuration
5.2.4.1
ROM Code Startup
The Public ROM Code is physically located at the address 30000h that is immediately next to the Secure
ROM Code.
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Figure 5-6. ROM Code Startup Sequence
System start-up
CPU Secure Boot
Initilization
(secure mode)
Jump to public
Public initialization
__main()
(stack setup)
main()
MPU Public Watchdog
Timer Setup
(Timeout = 3 minutes)
DPLLs and clocks
configurations
Booting
(Memory/Peripheral)
As Figure 5-6 shows, the CPU jumps to the Public ROM Code reset vector once it has completed the
secure boot initialization.
Once in public mode, the CPU:
1. Performs the public-side initialization and stack setup (compiler auto generated C- initialization or
“scatter loading”)
2. Configures the public watchdog timer (set to three minutes)
3. Performs system clocks configuration
4. Jumps to the booting routine
5.2.4.2
CPU State at Public Startup
The CPU L1 instruction cache and branch prediction mechanisms are not activated as part of the
public boot process. The public vector base address is configured to the reset vector of Public ROM Code
(30000h). MMU is left switched off during the public boot (hence L1 data cache off).
5.2.4.3
Clocking Configuration
Support for the following frequencies are based on SYSBOOT[15:14].
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Table 5-7. Crystal Frequencies Supported
SYSBOOT[15:14]
Crystal Frequency
00b
19.2 MHz
01b
24 MHz
10b
25 MHz
11b
26 MHz
The ROM Code configures the clocks and DPLLs which are necessary for ROM Code execution:
• CORE ADPLLS is locked at 2 GHz and divided further to provide 100 MHz clocks for L3 functional
clock and 100 MHz for Ethernet Module. The CORE ADPLLS is not reconfigured on warm reset if
Ethernet isolation is enabled.
• MPU ADPLLS is locked to provide 300 MHz for the Cortex-A9.
• PER ADPLLJ is locked to provide 960 MHz and 192 MHz for peripheral blocks.
Table 5-8 summarizes the ROM Code default settings for clocks. This default configuration enables all the
ROM Code functions with minimized needs on power during boot.
Table 5-8. ROM Code Default Clock Settings
Clock
Frequency (MHz)
Source (Source Frequency)
L3_FCLK
100
CORE_CLKOUTM4 (100 MHz)
SPI_CLK
48
PER_CLKOUTM2 (192 MHz)
MMC_CLK
96
PER_CLKOUTM2 (192 MHz)
UART_CLK
48
PER_CLKOUTM2 (192 MHz)
I2C_CLK
48
PER_CLKOUTM2 (192 MHz)
MPU_CLK
300
MPU_PLL (300 MHz)
USB_PHY_CLK
960
PER_CLKDCOLDO (960 MHz)
QSPI_CLK
12
PER_CLKOUTM2 (192 MHz)
MHZ_250_CLK (Ethernet)
100
CORE_CLKOUTM5 (100 MHz)
MHZ_50_CLK (Ethernet)
50
CORE_CLKOUTM5 (100 MHz)
MHZ_5_CLK (Ethernet)
5
CORE_CLKOUTM5 (100 MHz)
The DPLLs and PRCM clock dividers are configured with the ROM Code default values after cold or warm
reset in order to give the same working conditions to the Public ROM Code sequence.
5.2.5 Booting
5.2.5.1
Overview
Figure 5-7 shows the booting procedure. First a booting device list is created. The list consists of all
devices which will be searched for a booting image. The list is filled in based on the SYSBOOT pins.
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Figure 5-7. ROM Code Booting Procedure
Booting
Set the booting device list based on
the SW Booting Configuration or
SYSBOOT pins
Process next device
Process device
Device is of peripheral type
Device is of memory type
Success
Success
Memory
Booting
Peripheral
Booting
Jump to Initial Software
-Fail
-Timeout
Fail
Get next device in the list
No
Yes
Last device in the list?
No more devices in the list
Once the booting device list is set up, the booting routine examines the devices enumerated in the list
sequentially and executes either the memory booting or peripheral booting procedure depending on the
booting device type.
• The memory booting procedure executes when the booting device type is one of NOR, NAND, MMC,
SPI-EEPROM, QSPI-EEPROM or USB Pen drive (Mass Storage Class).
The memory booting procedure reads data from a memory type device. If a valid booting image is
found and successfully read from the external memory device:
– When ROM transfers control to the ISW, it passes a parameter to a Boot Parameter Structure in
R0. The Boot Parameter Structure can be used to determine the boot device, reset reason, etc.
The fields of this structure are described in Table 5-9.
• The peripheral booting executes when the booting device type is Ethernet, USB Client Mode or UART.
The peripheral booting procedure downloads data from a host (commonly a PC) to the device by
Ethernet, USB Client Mode, or UART links. The ROM Code uses a host-slave logical protocol for
synchronization. Upon successful UART, USB Client Mode or Ethernet connection the host sends the
image binary contents. The peripheral booting procedure is described in Section 5.2.7, Peripheral
Booting.
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Table 5-9. Booting Parameters Structure
Offset
Field
Size (bytes)
00h
Reserved
4
Reserved
04h
Device Descriptor Address
4
Pointer to the memory device descriptor that has
been used during the memory booting process
(used internally for ROM testing).
1
Code of device used for booting:
00h – void, no device
01h – NOR
02h – NOR (wait monitoring on)
03h – NOR2
04h – NOR2 (wait monitoring on)
05h – NAND
06h – NAND with I2C
07h – MMC/SD port 0
08h – MMC/SD port 1
0Ah – SPI
0Bh - QSPI
0Ch - SPI2
0Dh - USB_MS
41h – UART0
45h – USB_CL
47h – CPGMAC0
08h
Current Booting Device
Description
09h
Reset Reason
1
Current reset reason bit mask (bit=1-event
present):
[0] – Power-on reset
[1] – Global software reset
[2] – Security violation reset
[4] – Watchdog1 reset
[5] – External warm reset
[9] – IcePick reset
Other bits – Reserved
0Ah
Reserved
10
Reserved
5.2.5.1.1 Device List
The ROM Code creates the device list based on information gathered from the SYSBOOT configuration
pins sensed in the control module. The pins are used to index the device table from which the list of
devices is extracted
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5.2.5.2
SYSBOOT Configuration Pins
Table 5-10. SYSBOOT Configuration Pins
SYS
BOOT
[18] (1) (2)
ALL boot
modes:
CLKOUT2
output
CTRL_
STS[26]
SYS
BOOT
[17]
ALL
boot
modes:
CLKOUT
1 output
enabled
or
disabled
on
XDMA_E
VENT_IN
TR0
SYS
BOOT
[16] (3)
USB_MS
and
USB_CL:
DP/DM
swapping
SYS
BOOT
[15:14]
SYS
BOOT
[13:12]
SYS
BOOT
[11]
ALL
boot
modes:
Crystal
Frequenc
y
(MHz)
ALL
boot
modes:
Set to
00b for
normal
operation
Fast
NOR or
NOR:
Muxed or
nonmuxed
device
NAND:
must be
0
(4)
CTRL_
STS
[21:20]
SYS
BOOT
[9]
CTRL_
STS[19]
Fast
NOR or
NOR:
WAIT
enable
CTRL_
STS[17]
SYS
BOOT
[8]
SYS
BOOT
[7]
SYS
BOOT
[6]
SYS
BOOT
[5]
Fast
NOR:
Must be
1 NAND
or
NAND_I2
C or
NOR:
Wait mux
option
QSPI
Width
Selection
or NOR
Pinmux
NOR
Pinmux
or QSPI
Pinmux
or
NAND/
NAND_I
2C ECC
EMAC:
PHY
interface
Type
CTRL_
STS[25]
CTRL_
STS[24]
CTRL_
STS
[23:22]
CTRL_
STS[16]
don't care
0b =
CLKOUT
1
disabled
1b =
CLKOUT
1
enabled
USB_MS
or
USB_CL:
0b = USB
DP/DM not
swapped
1b = USB
DP/DM
swapped
00b =
19.2
01b = 24
10b = 25
11b = 26
00b
0b
don't
care
NAND:
0b =
Wait mux
option 0
1b =
Wait mux
option 1
don't care
0b =
CLKOUT
1
disabled
1b =
CLKOUT
1
enabled
USB_MS
or
USB_CL:
0b = USB
DP/DM not
swapped
1b = USB
DP/DM
swapped
00b =
19.2
01b = 24
10b = 25
11b = 26
00b
don't
care
don't
care
don't
care
CTRL_
STS[7:6]
SYS
BOOT
[4:0]
Boot Sequence
CTRL_
STS[5]
CTRL_
STS
[4:0]
1
(1)
(2)
(3)
(4)
NAND:
0b =
ECC
done by
ROM
1b =
ECC
done by
NAND
don't care
2
3
4
don't
care
00000b
NAND
USB_MS
(USB1)
MMC0
USB_CL
(USB0)
don't
care
00001b
MMC0
MMC1
USB_MS
(USB1)
USB_CL
(USB0)
SYSBOOT[18] can be used to supply a clock for external ethernet PHY devices. If SYSBOOT[5]=0, EXTDEV_PLL will be configured to 25MHz, if SYSBOOT[5]=1, EXTDEV_PLL will be
configured to 50MHz.
The functionality provided by SYSBOOT[18] is only available in PG1.2 silicon.
The functionality provided by SYSBOOT[16] is only available in PG1.2 silicon
All other values reserved.
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Table 5-10. SYSBOOT Configuration Pins (continued)
SYS
BOOT
[18] (1) (2)
SYS
BOOT
[17]
SYS
BOOT
[16] (3)
SYS
BOOT
[15:14]
SYS
BOOT
[13:12]
SYS
BOOT
[11]
SYS
BOOT
[9]
SYS
BOOT
[8]
don't care
0b =
CLKOUT
1
disabled
1b =
CLKOUT
1
enabled
USB_MS
or
USB_CL:
0b = USB
DP/DM not
swapped
1b = USB
DP/DM
swapped
00b =
19.2
01b = 24
10b = 25
11b = 26
00b
don't
care
don't
care
don't
care
don't care
0b =
CLKOUT
1
disabled
1b =
CLKOUT
1
enabled
USB_MS
or
USB_CL:
0b = USB
DP/DM not
swapped
1b = USB
DP/DM
swapped
00b =
19.2
01b = 24
10b = 25
11b = 26
00b
0b
don't
care
NAND_I2
C: 0b =
Wait mux
option 0
1b =
Wait mux
option 1
don't care
0b =
CLKOUT
1
disabled
1b =
CLKOUT
1
enabled
USB_MS
or
USB_CL:
0b = USB
DP/DM not
swapped
1b = USB
DP/DM
swapped
00b =
19.2
01b = 24
10b = 25
11b = 26
00b
don't
care
don't
care
don't
care
0b = Do not
route
EXTDEV_PL
L to
CLKOUT2
1b = Route
EXTDEV_PL
L to
CLKOUT2
0b =
CLKOUT
1
disabled
1b =
CLKOUT
1
enabled
USB_MS
or
USB_CL:
0b = USB
DP/DM not
swapped
1b = USB
DP/DM
swapped
00b =
19.2
01b = 24
10b = 25
11b = 26
00b
0b =
nonmuxed
device
1b =
muxed
device
NOR:
0=
WAIT
signal
not
monitore
d during
boot
1=
WAIT
signal
monitore
d during
boot
NOR:
0b =
Wait mux
option 0
1b =
Wait mux
option 1
SYS
BOOT
[7]
SYS
BOOT
[6]
don't care
SYS
BOOT
[5]
SYS
BOOT
[4:0]
don't
care
00010b
SPI
USB_MS
(USB1)
MMC0
USB_CL
(USB0)
NAND_I2 don't
C: 0b =
care
ECC
done by
ROM
1b =
ECC
done by
NAND
00011b
NAND_I2C USB_MS
(USB1)
MMC0
USB_CL
(USB0)
don't care
don't
care
00100b
MMC1
MMC0
USB_MS
(USB1)
USB_CL
(USB0)
NOR:
00b = pinmux option
0
01b = pinmux option
1
10b = pinmux option
2
11b = reserved
EMAC:
0b = MII
1b =
RMII
00101b
NOR
USB_MS
(USB1)
EMAC1
USB_CL
(USB0)
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Table 5-10. SYSBOOT Configuration Pins (continued)
SYS
BOOT
[18] (1) (2)
SYS
BOOT
[17]
SYS
BOOT
[16] (3)
SYS
BOOT
[15:14]
SYS
BOOT
[13:12]
SYS
BOOT
[11]
SYS
BOOT
[9]
SYS
BOOT
[8]
don't care
0b =
don't care
CLKOUT
1
disabled
1b =
CLKOUT
1
enabled
00b =
19.2
01b = 24
10b = 25
11b = 26
00b
0b
don't
care
NAND:
0b =
Wait mux
option 0
1b =
Wait mux
option 1
don't care
0b =
CLKOUT
1
disabled
1b =
CLKOUT
1
enabled
USB_MS
or
USB_CL:
0b = USB
DP/DM not
swapped
1b = USB
DP/DM
swapped
00b =
19.2
01b = 24
10b = 25
11b = 26
00b
0b =
nonmuxed
device
1b =
muxed
device
NOR:
0=
WAIT
signal
not
monitore
d during
boot
1=
WAIT
signal
monitore
d during
boot
don't care
0b =
CLKOUT
1
disabled
1b =
CLKOUT
1
enabled
USB_MS
or
USB_CL:
0b = USB
DP/DM not
swapped
1b = USB
DP/DM
swapped
00b =
19.2
01b = 24
10b = 25
11b = 26
00b
don't
care
don't care
0b =
don't care
CLKOUT
1
disabled
1b =
CLKOUT
1
enabled
00b =
19.2
01b = 24
10b = 25
11b = 26
00b
don't
care
SYS
BOOT
[7]
SYS
BOOT
[6]
NAND:
0b =
ECC
done by
ROM
1b =
ECC
done by
NAND
SYS
BOOT
[5]
SYS
BOOT
[4:0]
don't
care
00110b
NAND
NOR:
0b =
Wait mux
option 0
1b =
Wait mux
option 1
NOR:
don't
00b = pinmux option care
0
01b = pinmux option
1
10b = pinmux option
2
11b = reserved
00111b
NOR
USB_MS
(USB1)
UART0
don't
care
don't
care
QSPI:
0b =
quad
read
1b =
single
read
don't
care
01000b
QSPI
USB_MS
(USB1)
MMC0
don't
care
don't
care
don't care
don't
care
01001b
SPI
QSPI:
0b =
pinmux
option 0
1b =
pinmux
option 1
USB_CL
(USB0)
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Table 5-10. SYSBOOT Configuration Pins (continued)
SYS
BOOT
[18] (1) (2)
SYS
BOOT
[17]
SYS
BOOT
[16] (3)
SYS
BOOT
[15:14]
SYS
BOOT
[13:12]
SYS
BOOT
[11]
SYS
BOOT
[9]
SYS
BOOT
[8]
don't care
0b =
don't care
CLKOUT
1
disabled
1b =
CLKOUT
1
enabled
00b =
19.2
01b = 24
10b = 25
11b = 26
00b
don't
care
don't
care
don't
care
don't care
0b =
don't care
CLKOUT
1
disabled
1b =
CLKOUT
1
enabled
00b =
19.2
01b = 24
10b = 25
11b = 26
00b
0b
don't
care
NAND_I2
C: 0b =
Wait mux
option 0
1b =
Wait mux
option 1
don't care
0b =
don't care
CLKOUT
1
disabled
1b =
CLKOUT
1
enabled
00b =
19.2
01b = 24
10b = 25
11b = 26
00b
don't
care
don't
care
don't
care
don't care
0b =
don't care
CLKOUT
1
disabled
1b =
CLKOUT
1
enabled
00b =
19.2
01b = 24
10b = 25
11b = 26
00b
don't
care
don't
care
don't
care
0b = Do not
route
EXTDEV_PL
L to
CLKOUT2
1b = Route
EXTDEV_PL
L to
CLKOUT2
0b =
CLKOUT
1
disabled
1b =
CLKOUT
1
enabled
00b =
19.2
01b = 24
10b = 25
11b = 26
00b
0b
don't
care
NAND_I2
C: 0b =
Wait mux
option 0
1b =
Wait mux
option 1
USB_MS
or
USB_CL:
0b = USB
DP/DM not
swapped
1b = USB
DP/DM
swapped
SYS
BOOT
[7]
QSPI:
0b =
quad
read
1b =
single
read
SYS
BOOT
[6]
QSPI:
0b =
pinmux
option 0
1b =
pinmux
option 1
SYS
BOOT
[5]
SYS
BOOT
[4:0]
don’t
care
01010b
QSPI
NAND_I2 don't
C: 0b =
care
ECC
done by
ROM
1b =
ECC
done by
NAND
01011b
NAND_I2C
don't care
don't
care
01100b
MMC0
don't care
don't
care
01101b
MMC1
EMAC:
0b = MII
1b =
RMII
01110b
NAND_I2C USB_MS
(USB1)
NAND_I2
C: 0b =
ECC
done by
ROM
1b =
ECC
done by
NAND
190 Initialization
EMAC1
UART0
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Table 5-10. SYSBOOT Configuration Pins (continued)
SYS
BOOT
[18] (1) (2)
SYS
BOOT
[17]
SYS
BOOT
[16] (3)
SYS
BOOT
[15:14]
SYS
BOOT
[13:12]
SYS
BOOT
[11]
SYS
BOOT
[9]
SYS
BOOT
[8]
don't care
0b =
don't care
CLKOUT
1
disabled
1b =
CLKOUT
1
enabled
00b =
19.2
01b = 24
10b = 25
11b = 26
00b
0b =
nonmuxed
device
1b =
muxed
device
fast_NO
R:
0=
WAIT
signal
not
monitore
d during
boot
1=
WAIT
signal
monitore
d during
boot
fast
NOR:
must be
1
don't care
0b =
CLKOUT
1
disabled
1b =
CLKOUT
1
enabled
USB_MS
or
USB_CL:
0b = USB
DP/DM not
swapped
1b = USB
DP/DM
swapped
00b =
19.2
01b = 24
10b = 25
11b = 26
00b
0b
don't
care
NAND:
0b =
Wait mux
option 0
1b =
Wait mux
option 1
don't care
0b =
CLKOUT
1
disabled
1b =
CLKOUT
1
enabled
USB_MS
or
USB_CL:
0b = USB
DP/DM not
swapped
1b = USB
DP/DM
swapped
00b =
19.2
01b = 24
10b = 25
11b = 26
00b
don't
care
don't
care
don't
care
don't care
0b =
CLKOUT
1
disabled
1b =
CLKOUT
1
enabled
USB_MS
or
USB_CL:
0b = USB
DP/DM not
swapped
1b = USB
DP/DM
swapped
00b =
19.2
01b = 24
10b = 25
11b = 26
00b
don't
care
don't
care
don't
care
SYS
BOOT
[7]
don't care
SYS
BOOT
[6]
SYS
BOOT
[5]
SYS
BOOT
[4:0]
don't
care
01111b
FAST_NO
R
NAND_I2 don't
C: 0b =
care
ECC
done by
ROM
1b =
ECC
done by
NAND
10000b
MMC0
USB_MS
(USB1)
USB_CL
(USB0)
NAND
don't care
don't
care
10001b
MMC1
USB_MS
(USB1)
USB_CL
(USB0)
MMC0
don't care
don't
care
10010b
MMC0
USB_MS
(USB1)
USB_CL
(USB0)
SPI
Initialization 191
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Table 5-10. SYSBOOT Configuration Pins (continued)
SYS
BOOT
[18] (1) (2)
SYS
BOOT
[17]
SYS
BOOT
[16] (3)
SYS
BOOT
[15:14]
SYS
BOOT
[13:12]
SYS
BOOT
[11]
SYS
BOOT
[9]
SYS
BOOT
[8]
SYS
BOOT
[7]
don't care
0b =
CLKOUT
1
disabled
1b =
CLKOUT
1
enabled
USB_MS
or
USB_CL:
0b = USB
DP/DM not
swapped
1b = USB
DP/DM
swapped
00b =
19.2
01b = 24
10b = 25
11b = 26
00b
0b
don't
care
NAND_I2
C: 0b =
Wait mux
option 0
1b =
Wait mux
option 1
don't care
0b =
CLKOUT
1
disabled
1b =
CLKOUT
1
enabled
USB_MS
or
USB_CL:
0b = USB
DP/DM not
swapped
1b = USB
DP/DM
swapped
00b =
19.2
01b = 24
10b = 25
11b = 26
00b
don't
care
don't
care
don't
care
don't care
don't care
0b =
CLKOUT
1
disabled
1b =
CLKOUT
1
enabled
USB_MS
or
USB_CL:
0b = USB
DP/DM not
swapped
1b = USB
DP/DM
swapped
00b =
19.2
01b = 24
10b = 25
11b = 26
00b
0b =
nonmuxed
device
1b =
muxed
device
NOR:
0b =
WAIT
signal
not
monitore
d during
boot
1b =
WAIT
signal
monitore
d during
boot
NOR:
0b = wait
mux
option 0
1b = wait
mux
option 1
0b = Do not
route
EXTDEV_PL
L to
CLKOUT2
1b = Route
EXTDEV_PL
L to
CLKOUT2
0b =
don't care
CLKOUT
1
disabled
1b =
CLKOUT
1
enabled
00b =
19.2
01b = 24
10b = 25
11b = 26
00b
0b
don't
care
NAND or
NAND_I2
C: 0b =
Wait mux
option 0
1b =
Wait mux
option 1
SYS
BOOT
[6]
SYS
BOOT
[5]
SYS
BOOT
[4:0]
NAND_I2 don't
C: 0b =
care
ECC
done by
ROM
1b =
ECC
done by
NAND
10011b
MMC0
USB_MS
(USB1)
USB_CL
(USB0)
NAND_I2C
don't
care
10100b
MMC0
USB_MS
(USB1)
USB_CL
(USB0)
MMC1
NOR:
don't
00b = pinmux option care
0
01b = pinmux option
1
10b = pinmux option
2
11b = reserved
10101b
USB_MS
(USB1)
USB_CL
(USB0)
UART0
NOR
10110b
EMAC1
NAND_I2C NAND
NAND or
NAND_I2
C: 0b =
ECC
done by
ROM
1b =
ECC
done by
NAND
EMAC:
0b = MII
1b =
RMII
192 Initialization
MMC0
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Table 5-10. SYSBOOT Configuration Pins (continued)
SYS
BOOT
[18] (1) (2)
SYS
BOOT
[17]
SYS
BOOT
[16] (3)
SYS
BOOT
[15:14]
SYS
BOOT
[13:12]
SYS
BOOT
[11]
SYS
BOOT
[9]
SYS
BOOT
[8]
SYS
BOOT
[7]
SYS
BOOT
[6]
SYS
BOOT
[5]
SYS
BOOT
[4:0]
0b = Do not
route
EXTDEV_PL
L to
CLKOUT2
1b = Route
EXTDEV_PL
L to
CLKOUT2
0b =
don't care
CLKOUT
1
disabled
1b =
CLKOUT
1
enabled
00b =
19.2
01b = 24
10b = 25
11b = 26
00b
don't
care
don't
care
don't
care
QSPI:
0b =
quad
read
1b =
single
read
QSPI:
0b =
pinmux
option 0
1b =
pinmux
option 1
EMAC:
0b = MII
1b =
RMII
10111b
EMAC1
SPI
QSPI
MMC1
don't care
0b =
CLKOUT
1
disabled
1b =
CLKOUT
1
enabled
00b =
19.2
01b = 24
10b = 25
11b = 26
00b
don't
care
don't
care
don't
care
QSPI:
0b =
quad
read
1b =
single
read
QSPI:
0b =
pinmux
option 0
1b =
pinmux
option 1
don't
care
11000b
MMC0
USB_MS
(USB1)
USB_CL
(USB0)
QSPI
don't care
0b =
don't care
CLKOUT
1
disabled
1b =
CLKOUT
1
enabled
00b =
19.2
01b = 24
10b = 25
11b = 26
00b
0b
don't
care
NAND or
NAND_I2
C: 0b =
Wait mux
option 0
1b =
Wait mux
option 1
NAND or don't
NAND_I2 care
C: 0b =
ECC
done by
ROM
1b =
ECC
done by
NAND
11001b
UART0
NAND_I2C NAND
MMC0
don't care
0b =
don't care
CLKOUT
1
disabled
1b =
CLKOUT
1
enabled
00b =
19.2
01b = 24
10b = 25
11b = 26
00b
don't
care
don't
care
don't
care
QSPI:
0b =
pinmux
option 0
1b =
pinmux
option 1
11010b
UART0
SPI
MMC1
USB_MS
or
USB_CL:
0b = USB
DP/DM not
swapped
1b = USB
DP/DM
swapped
QSPI:
0b =
quad
read
1b =
single
read
don't
care
QSPI
Initialization 193
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Table 5-10. SYSBOOT Configuration Pins (continued)
SYS
BOOT
[18] (1) (2)
SYS
BOOT
[17]
SYS
BOOT
[16] (3)
SYS
BOOT
[15:14]
SYS
BOOT
[13:12]
SYS
BOOT
[11]
SYS
BOOT
[9]
SYS
BOOT
[8]
SYS
BOOT
[7]
SYS
BOOT
[6]
SYS
BOOT
[5]
SYS
BOOT
[4:0]
0b = Do not
route
EXTDEV_PL
L to
CLKOUT2
1b = Route
EXTDEV_PL
L to
CLKOUT2
0b =
don't care
CLKOUT
1
disabled
1b =
CLKOUT
1
enabled
00b =
19.2
01b = 24
10b = 25
11b = 26
00b
0b =
nonmuxed
device
1b =
muxed
device
NOR:
0=
WAIT
signal
not
monitore
d during
boot
1=
WAIT
signal
monitore
d during
boot
NOR:
0b =
Wait mux
option 0
1b =
Wait mux
option 1
NOR:
00b = pinmux option
0
01b = pinmux option
1
10b = pinmux option
2
11b = reserved
EMAC:
0b = MII
1b =
RMII
11011b
EMAC1
0b = Do not
route
EXTDEV_PL
L to
CLKOUT2
1b = Route
EXTDEV_PL
L to
CLKOUT2
0b =
don't care
CLKOUT
1
disabled
1b =
CLKOUT
1
enabled
00b =
19.2
01b = 24
10b = 25
11b = 26
00b
don't
care
don't
care
don't
care
don't care
EMAC:
0b = MII
1b =
RMII
11100b
EMAC1
don't care
0b =
CLKOUT
1
disabled
1b =
CLKOUT
1
enabled
USB_MS
or
USB_CL:
0b = USB
DP/DM not
swapped
1b = USB
DP/DM
swapped
00b =
19.2
01b = 24
10b = 25
11b = 26
00b
don't
care
don't
care
don't
care
don't care
don't
care
11101b
USB_CL
(USB0)
don't care
0b =
CLKOUT
1
disabled
1b =
CLKOUT
1
enabled
USB_MS
or
USB_CL:
0b = USB
DP/DM not
swapped
1b = USB
DP/DM
swapped
00b =
19.2
01b = 24
10b = 25
11b = 26
00b
0b
don't
care
NAND_I2
C: 0b =
Wait mux
option 0
1b =
Wait mux
option 1
NAND_I2 don't
C: 0b =
care
ECC
done by
ROM
1b =
ECC
done by
NAND_I2
C
11110b
USB_MS
(USB1)
194 Initialization
UART0
NOR
NAND_I2C
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Table 5-10. SYSBOOT Configuration Pins (continued)
SYS
BOOT
[18] (1) (2)
don't care
SYS
BOOT
[17]
SYS
BOOT
[16] (3)
0b =
don't care
CLKOUT
1
disabled
1b =
CLKOUT
1
enabled
SYS
BOOT
[15:14]
00b =
19.2
01b = 24
10b = 25
11b = 26
SYS
BOOT
[13:12]
00b
SYS
BOOT
[11]
0b =
nonmuxed
device
1b =
muxed
device
SYS
BOOT
[9]
fast_NO
R:
0=
WAIT
signal
not
monitore
d during
boot
1=
WAIT
signal
monitore
d during
boot
SYS
BOOT
[8]
fast
NOR:
must be
1
SYS
BOOT
[7]
don't care
SYS
BOOT
[6]
SYS
BOOT
[5]
don’t
care
SYS
BOOT
[4:0]
11111b
FAST_NO
R
Initialization 195
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General notes for SYSBOOT configuration pins:
• SYSBOOT[17] selects the default mux mode of XDMA_EVENT_INTR0. When SYSBOOT[17]=0,
default mux mode of XDMA_EVENT_INTR0 is mode0. When SYSBOOT[17]=1, default mux mode of
XDMA_EVENT_INTR0 is mode3, which enables CLKOUT1 on the terminal.
• DSS_HSYNC terminal is SYSBOOT[17] input. DSS_VSYNC terminal is SYSBOOT[16].
DSS_DATA[15:0] terminals are respectively SYSBOOT[15:0] inputs. All are latched on the rising edge
of PWRONTSTn. DSS_AC_BIAS_EN terminal is SYSBOOT[18].
• Note that even though some bits may be a don't care for ROM code, all SYSBOOT values are latched
into the CTRL_STS register and may be used by software after ROM execution has completed.
• SYSBOOT[10] should always be set to 0 for normal operation. SYSBOOT[10] = 1 is reserved.
The ROM Code uses the row pointed by the SYSBOOT pins value. The device list is filled in with the 1st
to 4th devices.
Table 5-10 is the decoding table for SYSBOOT pin configuration. The following shortcuts are used in the
table:
• MMC1: MMC or SD card (MMC port 1)
• MMC0: MMC or SD card (MMC port 0)
• NAND_I2C: NAND flash memory / read geometry from EEPROM on I2C0
• NOR: NOR device with or without wait monitoring (7)
• UART: UART interface (UART port 0)
• EMAC: Ethernet interface (EMAC port 1)
• SPI: SPI EEPROM (SPI 0, CS0)
• USB_CL: USB Client Mode (USB0 interface)
• USB_MS: USB Mass Storage Class (USB1 interface)
• QSPI: Quad SPI interface (QSPI, CS0)
NOTE: For any SYSBOOT value that is selected, please be aware of the pin muxing implications.
For example, if the boot mode selected is EMAC, NAND, SPI, NANDI2C, the SOC will drive
EMAC, GPMC, SPI and I2C pins, in that order, depending on which boot device finally
succeeds. For specific details of the pins driven by each device, see the description of the
boot device in this document.
To extend the boot flow to boot from devices that are not natively supported by the ROM, or if the user
needs a different booting configuration, use USB_MS boot. For example, if a customer wants to boot from
an unsupported NAND device or UART with different configuration, the system can be configured to boot
from another inexpensive boot media like SPI flash and the code for configuring and booting from the
unsupported NAND device can be loaded into the SPI flash. This is known as a secondary boot.
A “Low Latency NOR boot mechanism” (Section 5.2.8, Low Latency NOR Booting) is provided where
minimal execution is performed from ROM Code for configuring the GPMC interface and then directly
jump to the code contained in the connected NOR flash device.
5.2.6 Memory Booting
5.2.6.1
Overview
The memory booting procedure executes external code located in memory device types.
(7)
196
Wait monitoring is enabled or disabled based on SYSBOOT pins in Table 5-10.
Initialization
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Figure 5-8. Memory Booting
Memory Booting
Device is XIP
type?
No
Yes
HS device?
Copy Image into a target
RAM
Copying failed
No
Yes
Authenticate image
Authentication
successful?
Yes
Execute Initial SW
No
Go to next boot
device in list
Return fail
The following memory booting devices are supported:
• MMC/SD cards
• NOR flash
• NAND flash
• SPI EEPROMs
• Quad SPI EEPROMs
• USB Mass Storage device
Two groups of permanent booting devices are distinguished by the need of code shadowing. The code
shadowing means copying a code from an indirectly addressable device into a location (typically a RAM
area) from where the code can be executed. Devices which are directly addressable are called eXecute In
Place (XIP) devices.
Figure 5-8 shows the memory booting flowchart. The Image execution step is about performing the
shadowing of the image that is copying the image from external mass storage (non-XIP) into internal
RAM. The next sections detail procedures for device initialization and detection in addition to the
description of the sector read routine for each supported device type. A sector is a logical unit of 512
bytes.
The detection of whether an image is present on a selected device differs by device type:
• On a GP Device type, a booting image (bootloader) is considered to be present when the first four
bytes of the sector are not equal to 00000000h or FFFFFFFFh.
During the first read sector call, the first sector is copied to a temporary RAM buffer. Once the image is
found and the destination address is known from the decoding the header, the content of the temporary
buffer is moved to the target RAM location so it is not needed to re-read the first image sector. On a GP
device the GP header is discarded, and only executable code is located in RAM with the first executable
instruction located at the destination address.
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MMC/SD cards (in raw mode), SPI, and NAND devices hold up to four copies of the booting image. The
ROM Code searches for one valid image out of the four, if present, by walking over the first four blocks of
the mass storage space. Other XIP devices (NOR) use only one copy of the booting image.
5.2.6.2
Image Shadowing for non-XIP Memories
The GP device shadowing uses the following approach.
Figure 5-9. Image Shadowing on GP Device
Memory booting
Initialization
and
Device detection
Set first / next valid block
Copying failed
No more sectors to read
Device detection
Initialization failed
No more blocks
Read a sector
Store the loaded sector with
Initial SW in the target buffer
No
Loading Initial SW
Completed?
Return
fail
Yes
Initial SW execution
5.2.6.3
NOR Memory
The ROM Code can boot directly from NOR devices. A NOR flash memory behaves as an eXecute In
Place (XIP) device. NOR flash devices are supported under the following assumptions:
• GPMC is the communication interface.
• Connect up to 1Gb (128MB) memories.
• Only x16 data bus width (x8 not supported).
• Asynchronous protocol.
• Supports address / data multiplexed mode and non-muxed mode.
• GPMC clock is 50 MHz.
• Device connected to CS0 mapped to address 0x08000000h.
• Wait pin signal WAIT0 is monitored or ignored depending on the SYSBOOT pin configuration
mentioned in Table 5-10.
• Flexible muxing options for gpmc address lines for non-muxed and muxed NOR devices based on
SYSBOOT pin configuration mentioned in Table 5-10.
Depending on the SYSBOOT pins, the GPMC is configured to use the WAIT signal connected on the
WAIT pin or not. Wait pin polarity is set to stall accessing memory when the WAIT pin is low. The wait
monitoring is intended to be used with memories which require long time for initialization after reset or
need to pause while reading data.
198
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The boot procedure from a NOR device is:
1. Configure GPMC for NOR device access.
2. Set the image location to 0x08000000h
3. Verify if a bootable image is present at the image location.
4. If the image is not found, return from NOR booting to the main booting loop.
5.2.6.3.1 NOR Initialization and Detection
5.2.6.3.1.1 GPMC Initialization
Figure 5-10 and Table 5-11 describe the GPMC timing settings configured for NOR boot and other
address-data accessible devices.
Figure 5-10. GPMC NOR Timings
twr, trd
tCEoff
tADVoff
tADVon
tCEon
CS0
ADV
trddata
OE
WE
tOEon, tWEon
tWEoff
tOEoff
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Table 5-11. NOR Timings Parameters
Parameter
Description
twr
write cycle period
Value (clock cycles)
17
trd
read cycle period
17
tCEon
CE low time
1
tCEoff
CE high time
16
tADVon
ADV low time
1
tADVoff
ADV high time
2
tOEon
OE low time
3
tWEon
WE low time
3
trddata
data latch time
15
tOEoff
OE high time
16
tWEoff
WE high time
15
5.2.6.3.1.2 Device Detection
There is no specific identification routine executed prior to booting from an NOR device.
5.2.6.3.2 Pins Used
Table 5-12 lists the pins configured by the ROM for NOR boot mode. Not all pins are driven at boot time.
The decision as to which pins need to be driven is based on the type of NOR flash selected.
Table 5-12. Pins Used for NOR Boot Common Signals
Signal Name
Pin Used in NOR
CTRL_CONF Register
Register Setting
cs0
gpmc_cs0
CTRL_CONF_GPMC_CS0
0x00010000
advn_ale
gpmc_advn_ale
CTRL_CONF_GPMC_ADVN_ALE
0x00010000
oen_ren
gpmc_oen_ren
CTRL_CONF_GPMC_OEN_REN
0x00010000
be1n
gpmc_be1n
CTRL_CONF_GPMC_BE1N
0x00010000
be0n_cle
gpmc_be0n_cle
CTRL_CONF_GPMC_BE0N_CLE
0x00010000
wen
gpmc_wen
CTRL_CONF_GPMC_WEN
0x00010000
clk
gpmc_clk
CTRL_CONF_GPMC_CLK
0x00060000
Table 5-13. Pins Used for NOR Boot Wait Pin Selection
Signal
name
Pin used
CTRL_CONF
pinmux option 0 Register
Register
Setting
Pin used
CTRL_CONF
pinmux option 1 Register
Register
Setting
wait
gpmc_wait0
0x00060000
gpmc_csn3
0x00060001
CTRL_CONF_
GPMC_WAIT
CTRL_CONF_
GPMC_CSN3
Table 5-14. Pins Used for non-Mux NOR Boot
Signal Name
Pin Used in
non-Mux-NOR
Pinmux Option
0
CTRL_CONF
Register
Register Setting Pin Used in
non-Mux-NOR
Pinmux Option
1
CTRL_CONF
Register
Register Setting
a0
dss_data0
CTRL_CONF_
DSS_DATA0
0x00000001
gpmc_a0
CTRL_CONF_
GPMC_A0
0x00000000
a1
dss_data1
CTRL_CONF_
DSS_DATA1
0x00000001
gpmc_a1
CTRL_CONF_
GPMC_A1
0x00000000
a2
dss_data2
CTRL_CONF_
DSS_DATA2
0x00000001
gpmc_a2
CTRL_CONF_
GPMC_A2
0x00000000
a3
dss_data3
CTRL_CONF_
DSS_DATA3
0x00000001
gpmc_a3
CTRL_CONF_
GPMC_A3
0x00000000
200 Initialization
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Table 5-14. Pins Used for non-Mux NOR Boot (continued)
Signal Name
Pin Used in
non-Mux-NOR
Pinmux Option
0
CTRL_CONF
Register
Register Setting Pin Used in
non-Mux-NOR
Pinmux Option
1
CTRL_CONF
Register
Register Setting
a4
dss_data4
CTRL_CONF_
DSS_DATA4
0x00000001
gpmc_a4
CTRL_CONF_
GPMC_A4
0x00000000
a5
dss_data5
CTRL_CONF_
DSS_DATA5
0x00000001
gpmc_a5
CTRL_CONF_
GPMC_A5
0x00000000
a6
dss_data6
CTRL_CONF_
DSS_DATA6
0x00000001
gpmc_a6
CTRL_CONF_
GPMC_A6
0x00000000
a7
dss_data7
CTRL_CONF_
DSS_DATA7
0x00000001
gpmc_a7
CTRL_CONF_
GPMC_A7
0x00000000
a8
dss_vsync
CTRL_CONF_
DSS_VSYNC
0x00000001
gpmc_a8
CTRL_CONF_
GPMC_A8
0x00000000
a9
dss_hsync
CTRL_CONF_
DSS_HSYNC
0x00000001
gpmc_a9
CTRL_CONF_
GPMC_A9
0x00000000
a10
dss_pclk
CTRL_CONF_
DSS_PCLK
0x00000001
gpmc_a10
CTRL_CONF_
GPMC_A10
0x00000000
a11
dss_ac_bias_en
CTRL_CONF_
DSS_AC_BIAS_
EN
0x00000001
gpmc_a11
CTRL_CONF_
GPMC_A11
0x00000000
a12
dss_data8
CTRL_CONF_
DSS_DATA8
0x00000001
dss_data8
CTRL_CONF_
DSS_DATA8
0x00000001
a13
dss_data9
CTRL_CONF_
DSS_DATA9
0x00000001
dss_data9
CTRL_CONF_
DSS_DATA9
0x00000001
a14
dss_data10
CTRL_CONF_
DSS_DATA10
0x00000001
dss_data10
CTRL_CONF_
DSS_DATA10
0x00000001
a15
dss_data11
CTRL_CONF_
DSS_DATA11
0x00000001
dss_data11
CTRL_CONF_
DSS_DATA11
0x00000001
a16
dss_data12
CTRL_CONF_
DSS_DATA12
0x00000001
dss_data12
CTRL_CONF_
DSS_DATA12
0x00000001
a17
dss_data13
CTRL_CONF_
DSS_DATA13
0x00000001
dss_data13
CTRL_CONF_
DSS_DATA13
0x00000001
a18
dss_data14
CTRL_CONF_
DSS_DATA14
0x00000001
dss_data14
CTRL_CONF_
DSS_DATA14
0x00000001
a19
dss_data15
CTRL_CONF_
DSS_DATA15
0x00000001
dss_data15
CTRL_CONF_
DSS_DATA15
0x00000001
a20
mmc0_dat3
CTRL_CONF_
MMC0_DAT3
0x08040004
mmc0_dat3
CTRL_CONF_
MMC0_DAT3
0x08040001
a21
mmc0_dat2
CTRL_CONF_
MMC0_DAT2
0x08040004
mmc0_dat2
CTRL_CONF_
MMC0_DAT2
0x08040001
a22
mmc0_dat1
CTRL_CONF_
MMC0_DAT1
0x08040001
mmc0_dat1
CTRL_CONF_
MMC0_DAT1
0x08040001
a23
mmc0_dat0
CTRL_CONF_
MMC0_DAT0
0x08040001
mmc0_dat0
CTRL_CONF_
MMC0_DAT0
0x08040001
a24
mmc0_clk
CTRL_CONF_
MMC0_CLK
0x08040001
mmc0_clk
CTRL_CONF_
MMC0_CLK
0x08040001
a25
mmc0_cmd
CTRL_CONF_
MMC0_CMD
0x08040001
mmc0_cmd
CTRL_CONF_
MMC0_CMD
0x08040001
a26
gpmc_a10
CTRL_CONF_
(pinmux mode 4) GPMC_A10
0x0804004
-
a27
gpmc_a11
CTRL_CONF_
(pinmux mode 4) GPMC_A11
0x0804004
-
d0 - d15
gpmc_ad0 –
gpmc_ad15
0x00060000
gpmc_ad0 gpmc_ad15
CTRL_CONF_
GPMC_AD0 to
CTRL_CONF_
GPMC_AD15
0x00060000
CTRL_CONF_
GPMC_AD0 to
CTRL_CONF_
GPMC_AD15
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Table 5-15. Pins Used for Mux NOR Boot
Signal
Name
Pin Used in
Mux NOR
Pinmux
Option 0
CTRL_CON
F Register
Register
Setting
Pin Used in
Mux NOR
Pinmux
Option 1
CTRL_CON
F Register
Register
Setting
Pin Used in
Mux NOR
Pinmux
Option 2
CTRL_CON
F Register
Register
Setting
d0 – d15 /
a1 – a16
gpmc_ad0 gpmc_ad15
CTRL_CON
F_
GPMC_AD0
to
CTRL_CON
F_
GPMC_AD1
5
0x00060000
gpmc_ad0 gpmc_ad15
CTRL_CON
F_
GPMC_AD0
to
CTRL_CON
F_
GPMC_AD1
5
0x00060000
gpmc_ad0 gpmc_ad15
CTRL_CON
F_
GPMC_AD0
to
CTRL_CON
F_
GPMC_AD1
5
0x00060000
a17
dss_data1
CTRL_CON 0x00000001
F_
DSS_DATA1
gpmc_a1
CTRL_CON
F_
GPMC_A1
0x00000000
dss_vsync
CTRL_CON
F_
DSS_VSYN
C
0x00000002
a18
dss_data2
CTRL_CON 0x00000001
F_
DSS_DATA2
gpmc_a2
CTRL_CON
F_
GPMC_A2
0x00000000
dss_hsync
CTRL_CON
F_
DSS_HSYN
C
0x00000002
a19
dss_data3
CTRL_CON 0x00000001
F_
DSS_DATA3
gpmc_a3
CTRL_CON
F_
GPMC_A3
0x00000000
dss_pclk
CTRL_CON
F_
DSS_PCLK
0x00000002
a20
dss_data4
CTRL_CON 0x00000001
F_
DSS_DATA4
gpmc_a4
CTRL_CON
F_
GPMC_A4
0x00000000
dss_ac_bias
_en
CTRL_CON
F_
DSS_AC_BI
AS_EN
0x00000002
a21
dss_data5
CTRL_CON 0x08040001
F_
DSS_DATA5
gpmc_a5
CTRL_CON
F_
GPMC_A5
0x08040000
gpmc_be0n_ CTRL_CON
cle
F_
GPMC_BE0
N
0x00000002
a22
dss_data6
CTRL_CON 0x08040001
F_
DSS_DATA6
gpmc_a6
CTRL_CON
F_
GPMC_A6
0x08040000
gpmc_a6
CTRL_CON
F_
GPMC_A6
0x08040000
a23
dss_data7
CTRL_CON 0x08040001
F_
DSS_DATA7
gpmc_a7
CTRL_CON
F_
GPMC_A7
0x08040000
gpmc_a7
CTRL_CON
F_
GPMC_A7
0x08040000
a24
dss_vsync
CTRL_CON
F_
DSS_VSYN
C
0x08040001
gpmc_a8
CTRL_CON
F_
GPMC_A8
0x08040000
gpmc_a8
CTRL_CON
F_
GPMC_A8
0x08040000
a25
dss_hsync
CTRL_CON
F_
DSS_HSYN
C
0x08040001
gpmc_a9
CTRL_CON
F_
GPMC_A9
0x08040000
gpmc_a9
CTRL_CON
F_
GPMC_A9
0x08040000
a26
dss_pclk
CTRL_CON
F_
DSS_PCLK
0x08040001
gpmc_a10
CTRL_CON
F_
GPMC_A10
0x08040000
gpmc_a10
CTRL_CON
F_
GPMC_A10
0x08040000
a27
dss_ac_bias
_en
CTRL_CON
F_
DSS_AC_BI
AS_EN
0x08040001
gpmc_a11
CTRL_CON
F_
GPMC_A11
0x08040000
gpmc_a11
CTRL_CON
F_
GPMC_A11
0x08040000
5.2.6.3.2.1 SYSBOOT Signals
Table 5-16 describes the SYSBOOT signals relevant to NOR boot.
Table 5-16. SYSBOOT Signals for NOR Boot
202
SYSBOOT[7:6]
Used for Pinmux option selection in NOR
00b – pinmux option 0 is selected for NOR
01b – pinmux option 1 is selected for NOR
1xb – pinmux option 2 is selected for NOR
SYSBOOT[8]
Decides which pin WAIT needs to be connected to the
NOR flash.
0b – Wait mux option 0
1b – Wait mux option 1
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Table 5-16. SYSBOOT Signals for NOR Boot (continued)
5.2.6.4
SYSBOOT[9]
During NOR Boot this pin will be used to determine if
Wait is enabled.
0b – Ignore WAIT input
1b – Use WAIT input
SYSBOOT[11]
Address Muxing
0b – No Addr/Data Muxing
1b – Addr/Data Muxing
NAND Memory
The NAND flash memory is not XIP and requires shadowing before the code can be executed.
5.2.6.4.1
•
•
•
•
•
•
•
•
•
•
•
•
•
•
Features
GPMC is the communication interface
Device size from 512Mb (64MB)
x8 and x16 bus width
Support for the following page sizes:
– 2048 bytes + 64 spare bytes
– 4096 bytes + 128 or 218 spare bytes
Only supports devices where chip select can be de-asserted during read, program, or erase cycles,
without interrupting the operation
Single Level Cell (SLC) and Multiple Level Cell (MLC) devices
Device Identification based on ONFI or ROM table
ECC correction: 8 bits per sector for most devices (16 bits per sector for devices with large spare area)
Support for disabling ECC correction, so than the in-built ECC correction mechanisms on some
NANDs can be used.
GPMC timings adjusted for NAND access
GPMC clock is 50 MHz
Device connected to CS0
Wait pin signal WAIT0 connected to NAND BUSY output based on SYSBOOT[8] (8)
Four physical blocks are searched for an image. The block size depends on device.
5.2.6.4.2 Initialization and Detection
The initialization routine for NAND devices includes three parts: GPMC initialization, device detection with
parameters determination, and bad block detection.
5.2.6.4.2.1 ONFI Support
The NAND identification starts with ONFI detection.
5.2.6.4.2.2 GPMC Initialization
The GPMC interface is configured to NAND devices. The address bus is released since a NAND device
does not use it. The data bus width is initially set to 8 bits and changed to 16 bits if needed after device
parameters determination. The following scheme is applied since NAND devices require different timings
when compared to regular NOR devices:
(8)
See Table 5-10, SYSBOOT Configuration Pins.
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Figure 5-11. GPMC NAND Timings
twr, trd, tCEoff
tOEon, tWEon
CS0
OE
WE
trddata
tOEoff, tWEoff
Table 5-17. Parameters for NAND Timings
Parameter
Description
twr
write cycle period
Value (clock cycles)
30
trd
read cycle period
30
tCEon
CE low (not marked on the figure)
0
tOEon
CE low to OE low time
7
tWEon
CE low to WE low time
5
trddata
CE low to data latch time
21
tOEoff
CE low to OE high time
24
tWEoff
CE low to WE high time
22
Figure 5-11 and Table 5-17 describe the timings configured for NAND device access.
5.2.6.4.2.3 Device Detection and Parameters
The ROM Code first performs an initial wait for device auto initialization (with a 250 ms timeout) with
polling of the ready information. It then identifies the NAND type connected to the GPMC interface. The
GPMC is initialized using 8-bit asynchronous mode. The NAND device is reset (command FFh) and its
status is polled until ready for operation (with a 200 ms timeout). The ONFI Read ID (command 90h /
address 20h) is sent to the NAND device. If it replies with the ONFI signature (4 bytes), then a Read
parameters page (command ECh) is sent. If the parameters page does not have the ONFI signature, then
the ONFI identification fails.
If the ONFI identification passes, the information shown in Table 5-18 is then extracted: page size, spare
area size, number of pages per block, and the addressing mode. The remaining data bytes from the
parameters page stream are simply ignored. The detection procedure is described in Figure 5-12. Once
the device has been successfully detected, the ROM Code changes GPMC to 16-bit bus width if
necessary.
204
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Figure 5-12. NAND Device Detection
NAND detection
Wait for device initialization
(max timeout 250ms)
Device ready
No
Yes
Issue Reset command
(max timeout 200ms)
Device ready
No
Yes
Issue Read ID (ONFI) command
Yes
Device replied (ONFI)?
No
Issue Reset command
Issue Read parameters page
command
Device ready
No
Yes
Issue Read ID (standard) command
Extract NAND parameters
from device parameters page
Device ID
in the table?
No
Yes
Extract NAND parameters from table
Update page size, block size, ECC
correction for devices > 1 Gb
Read Invalid Blocks
Information
Success
Failed
NOTE: Timeouts are based on ONFI timing requirements and NAND reset timing specifications.
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Table 5-18. ONFI Parameters Page Description
Offset
Description
6
Features supported
Size (bytes)
2
80
Number of data bytes per page
4
84
Number of spare bytes per page
2
92
Number of pages per block
4
101
Number of address cycles
1
If the ONFI Read ID command fails (it will fail with any device not supporting ONFI) then the device is
reset again with polling for device to be ready (with a 200 ms timeout). Then, the standard Read ID
(command 90h / address 00h) is sent. If the Device ID (2nd byte of the ID byte stream) is recognized as a
supported device, then the device parameters are extracted from an internal ROM Code table. The list of
supported devices is in Table 5-19.
Table 5-19. Supported NAND Devices
Capacity
512 Mb
1 Gb
2 Gb
4 Gb
8 Gb
206 Initialization
Device ID
Bus Width
F0
x8
C0
x16
A0
x8
B0
x16
F2
x8
C2
x16
A2
x8
B2
x16
F1
x8
C1
x16
A1
x8
B1
x16
DA
x8
CA
x16
AA
x8
BA
x16
83
x8
93
x16
DC
x8
CC
x16
AC
x8
BC
x16
84
x8
94
x16
D3
x8
C3
x16
A3
x8
B3
x16
85
x8
95
x16
Page Size
2048
2048
2048
2048
2048/4096
2048
2048/4096
2048
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Table 5-19. Supported NAND Devices (continued)
Capacity
16 Gb
32 Gb
64 Gb
Device ID
Bus Width
D5
x8
C5
x16
A5
x8
B5
x16
86
x8
96
x16
D7
x8
C7
x16
A7
x8
B7
x16
87
x8
97
x16
DE
x8
CE
x16
AE
x8
BE
x16
Page Size
2048/4096
2048
2048/4096
2048
2048/4096
When the parameters are retrieved from the ROM table: page size and block size are updated based on
4th byte of NAND ID data. Due to inconsistency among manufacturers, only devices of at least 2Gb
(included) have these parameters updated. Therefore, the ROM Code supports 4kB page devices but only
if their size, according to the table, is at least 2Gb. Devices smaller than 2Gb have the block size
parameter fixed to 128kB. Table 5-20 shows the 4th ID Data byte encoding used in ROM Code.
Table 5-20. 4th NAND ID Data Byte
Item
Description
I/O #
1
0
Page Size
1kB
0
0
2kB
0
1
4kB
1
0
8kB
1
1
7
Cell type
Block Size
6
5
4
3
2
2 levels
0
0
4 levels
0
1
8 levels
1
0
16 levels
1
1
64kB
0
0
128kB
0
1
256kB
1
0
512kB
1
1
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5.2.6.4.2.4 Reading NAND Geometry from I2C EEPROM
ROM supports a special boot mode called NANDI2C to support NAND devices whose geometry cannot be
detected by the ROM automatically using methods described in the previous section (Figure 5-12). If this
boot mode is selected, the ROM code reads NAND geometry from an I2C EEPROM. If the read is
successful, ROM code moves to the next steps of NAND boot beginning with reading bad blocks
information.
If the I2C EEPROM read fails, the ROM will fall back to querying the NAND for the geometry information,
as described above.
Note: The NAND bus width configuration mentioned in the I2C EEPROM overrides the BUSWIDTH
configuration selected by SYSBOOT pins.
Table 5-21 lists the device pins configured by the ROM for NANDI2C boot mode, in addition to the NAND
boot pins described in the previous sections.
Table 5-21. Pins Used for NAND I2C Boot for I2C EEPROM Access
Signal Name
Pin Used
CTRL_CONF Register
Register Setting
I2C SCL
i2c0_scl
CTRL_CONF_I2C0_SCL
0x000e0000
I2C SDA
i2c0_sda
CTRL_CONF_I2C0_SDA
0x000e0000
ROM accesses the I2C EEPROM at I2C slave address 0x50 and reads 7 bytes starting from address
offset 0x80. The ROM sends a 2-byte address to perform a selective read from the I2C EEPROM, thus
the ROM can only support devices that are minimum of 32Kb in size. The format of this NAND geometry
information follows:
Table 5-22. NAND Geometry Information on I2C EEPROM
Byte address
Information
Upper Nibble
Lower Nibble
0x80
Magic Number – 0x10
0x81
Magic Number – 0xb3
0x82
Magic Number – 0x57
0x83
Magic Number – 0xa6
0x84
NAND column address (word/byte offset within
a page) size in bytes, Example: 2
NAND row address (page offset) size in bytes.
Example: 3
0x85
Page size (2N) exponent “N”. Example (for
page size of 2048): 11
Pages per block (2N) exponent “N”
Example (for number of blocks 64): 6
0x86
NAND bus width
0 → 8-bit, 1 → 16-bit
ECC Type
0 → No ECC, 1 → BCH8, 2 → BCH16
5.2.6.4.2.5 ECC Correction
The default ECC correction applied is BCH 8 bits per sector using the GPMC and ELM hardware.
For device ID codes D3h, C3h, D5h, C5h, D7h, C7h, DEh, CEh when manufacturer code (first ID byte) is
98h the Cell type information is checked in the 4th byte of ID data. If it is equal to 10b then the ECC
correction applied is BCH 16 bits per sector.
In addition, ECC computation done by the ROM can be turned off completely by using SYSBOOT[6] . This
is particularly useful when interfacing with NAND devices that have built in ECC engines.
5.2.6.4.2.6 Bad Block Verification
Invalid blocks are blocks with invalid bits whose reliability cannot be guaranteed by the manufacturer.
Invalid bits are identified in the factory or during the programming and reported in the initial invalid block
information located in the spare area on the 1st and 2nd page of each block. Since the ROM Code is
looking for an image in the first four blocks, it must detect block validity status of these blocks. Blocks
which are detected as invalid are not accessed later on.
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The valid block status is coded in the spare areas of the first two pages of a block:
• 8-bit device: first byte equals FFh in 1st and 2nd pages
• 16-bit device: first word equals FFFFh in 1st and 2nd pages
Figure 5-13 shows the invalid block detection routine. The routine reads spare areas and checks validity
data pattern.
Figure 5-13. NAND Invalid Blocks Detection
Read Invalid Blocks
Information
Invalid Block
Information
¹
0xFF (or 0xFFFF for
16-bit devices)
Yes
Set Invalid Block Flag
No
For first 4 blocks
Read 1st and 2nd page spare
sectors
Clear Invalid Block Flag
5.2.6.4.3 NAND Read Sector Procedure
The ROM Code reads data from NAND devices in 512-byte sectors. The read function fails in two cases:
• The accessed sector is within a block marked as invalid
• The accessed sector contains an error which cannot be corrected with ECC
Figure 5-14 shows the read sector routine for NAND devices. The ROM Code uses a normal read
(command 00h 30h) to read NAND page data.
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Figure 5-14. NAND Read Sector Procedure
Read Sector
Yes
Is this block
invalid
No
Read 512 bytes sector
GPMC ECC
?
NAND ECC
Yes
No
Failed
Correct Error
Success
Success
Failed
Page data can contain errors due to memory alteration. The ROM Code uses an ECC correction algorithm
to detect and possibly correct those errors. The ECC algorithm used is BCH with capability for correcting
8b or 16b errors per sector. Selecting between BCH8 and BCH16 ECC scheme is shown in Figure 5-15.
The BCH data is automatically calculated by the GPMC on reading each 512-byte sector. The computed
ECC is compared against ECC stored in the spare area for the corresponding page. Depending on the
page size, the amount of ECC data bytes stored in the corresponding spare area is different.
Figure 5-16 and Figure 5-17 show the mapping of ECC data inside the spare area for respectively 2KBpage and 4KB-page devices. If both ECC data are equal then the Read Sector function returns the read
512-byte sector without error. Otherwise the ROM Code tries to correct errors in the corresponding sector
(this procedure is assisted by the ELM hardware) and returns the data if successful. If errors are
uncorrectable, the function returns with FAIL.
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Figure 5-15. NAND ECC Scheme Selection Procedure
Read spare bytes
per page
Read page size
Sectors per page
= Pagesize/512
Yes
No
Spare bytes >=
sectors * 26
(1)
?
BCH16
(1)
BCH8
26 is the number of ECC bytes needed for the 512-byte sector in the BCH16 scheme.
Figure 5-16. ECC Data Mapping for 2KB Page and 8b BCH Encoding
byte x8
0
word x16
MSB
LSB
0
1
2
ECC-A[0]
ECC-A[1]
ECC-A[0]
1
3
ECC-A[1]
ECC-A[3]
ECC-A[2]
2
4
ECC-A[2]
...
...
...
0x00
ECC-A[12]
7
ECC-A[12]
ECC-B[1]
ECC-B[0]
8
15
0x00
...
...
16
ECC-B[0]
0x00
ECC-B[12]
14
...
ECC-C[1]
ECC-C[0]
15
28
ECC-B[12]
...
...
29
0x00
0x00
ECC-C[12]
21
30
ECC-C[0]
ECC-D[1]
ECC-D[0]
22
...
...
...
42
ECC-C[12]
0x00
ECC-D[12]
43
0x00
44
ECC-D[0]
14
28
...
56
ECC-D[12]
57
0x00
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Figure 5-17. ECC Data Mapping for 4KB Page and 16b BCH Encoding
byte x8
word x16
0
MSB
1
LSB
0
ECC-A[0]
2
1
...
ECC-A[1]
ECC-A[0]
...
...
27
ECC-A[25]
13
ECC-A[25]
ECC-A[24]
28
ECC-B[0]
14
ECC-B[1]
ECC-B[0]
...
...
...
53
ECC-B[25]
26
ECC-B[25]
ECC-B[24]
54
ECC-C[0]
27
ECC-C[1]
ECC-C[0]
...
...
39
ECC-C[25]
ECC-C[24]
92
ECC-H[1]
ECC-H[0]
...
...
...
79
ECC-C[25]
80
ECC-D[0]
...
105 ECC-D[25]
ECC-E[0]
106
...
104 ECC-H[25]
ECC-H[24]
131 ECC-E[25]
ECC-F[0]
132
...
157 ECC-F[25]
ECC-G[0]
158
...
183 ECC-G[25]
ECC-H[0]
184
...
209 ECC-H[25]
5.2.6.4.4 Pins Used
Table 5-23 lists the device pins configured by the ROM for NAND boot mode. Not all the pins are driven at
boot time.
Table 5-23. Pins Used for NAND Boot
212
Signal Name
Pin Used
CTRL_CONF Register
Register Setting
cs0
gpmc_cs0
CTRL_CONF_GPMC_CS0
0x00010000
advn_ale
gpmc_advn_ale
CTRL_CONF_GPMC_ADVN_ALE
0x00010000
oen_ren
gpmc_oen_ren
CTRL_CONF_GPMC_OEN_REN
0x00010000
be0n_cle
gpmc_be0n_cle
CTRL_CONF_GPMC_BE0N_CLE
0x00010000
Wen
gpmc_wen
CTRL_CONF_GPMC_WEN
0x00010000
Clk
gpmc_clk
CTRL_CONF_GPMC_CLK
0x00060000
ad0 - ad15
gpmc_ad0 - gpmc_ad15
CTRL_CONF_GPMC_AD0 to
CTRL_CONF_GPMC_AD15
0x00060000
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Table 5-24. Pins Used for NAND Boot Wait Pin Selection
Signal name
Pin Used
CTRL_CONF
Pinmux Option 0 Register
Register
Setting
Pin Used
CTRL_CONF
Pinmux Option 1 Register
Register
Setting
wait
gpmc_wait0
0x00060000
gpmc_csn3
0x00600001
CTRL_CONF_
GPMC_WAIT0
CTRL_CONF_
GPMC_CSN3
5.2.6.4.4.1 SYSBOOT Signals
Table 5-25 lists the SYSBOOT signals for NAND boot.
Table 5-25. SYSBOOT Signals for NAND Boot
5.2.6.5
SYSBOOT[6]
Used by Boot ROM to determine if NAND ECC is handled by ROM or NAND device. Please
note that when ROM is booting from external NAND, WAIT monitoring will be forced by ROM
code. SYSBOOT setting is not required to enable/disable Wait monitoring.
0 – ECC done by ROM
1 – ECC done by NAND Device
SYSBOOT[8]
Decides which pin READY/BUSY needs to be connected to when NAND is selected.
0 – Wait mux option 0
1 – Wait mux option 1
SYSBOOT[11]
Must be 0
MMC/SD Cards
5.2.6.5.1 Overview
The ROM Code supports booting from MMC/SD cards in the following conditions:
• MMC/SD Cards compliant to [6], [9] of low and high capacities.
• MMC/SD cards connected to MMC interface #0 and #1.
• Support for 3.3 V or 1.8 V I/O voltages.
• Initial 1-bit MMC Mode and optional 4-bit mode, if MMC/SD card supports it.
• Clock Frequency: identification mode: 240 KHz; data transfer mode up to 12 MHz.
• Only one card connected to the bus.
• Raw mode, image data read directly from sectors in the user area.
• File system mode (FAT16/32 supported with or without Master Boot Record), image data is read from
a booting file.
5.2.6.5.2 System Interconnection
An MMC/SD card or eMMC/eSD/managed NAND memory device can connect to MMC0 or MMC1
interface.
Note:
• The ROM Code does not handle the card detection feature on card cage.
• MMC0 and MMC1 support sector mode without querying the card.
5.2.6.5.3 Booting Procedure
Figure 5-18 shows the high level flowchart of the eMMC, eSD, and MMC/SD booting procedure.
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Figure 5-18. MMC/SD Booting
MMC/ SD Booting
Initialize the MMC / SD driver
Detect card
or embedded
memory
Not detected
Detected
Configure the card address
(RCA)
No
Booting file
found?
No
“Raw mode”
detected?
Yes
Get the booting file
Failed
Get raw data
Success
5.2.6.5.4 Initialization and Detection
The ROM Code attempts to initialize the memory device or card connected on MMC interface. If neither
memory device nor card is detected then the ROM Code carries on to the next booting device. The
standard identification process and Relative Card Address (RCA) assignment are used. However, the
ROM Code assumes that only one memory or card is present on the bus. This first sequence uses the
CMD signal which is common to SD and MMC devices.
MMC and SD standards detail this phase as initialization phase. Both standards differ in the first
commands involved: CMD1 and ACMD41. The ROM Code uses this difference in command set to
discriminate between MMC and SD devices: CMD1 is supported only by the MMC standard, whereas
ACMD41 is only supported by SD standard.
The ROM Code first sends a CMD1 to the device and gets a response only if an MMC device is
connected. If no response is received, then ACMD41 (ACMD41 is made out of CMD55 and ACMD41) is
sent and a response is expected from an SD device. If no response is received, then it is assumed that no
device is connected and the ROM Code exits the MMC/SD Booting procedure with FAIL. Figure 5-19
shows the detection procedure.
At first the ROM queries the card with CMD1, ARG = 0, to get the OCR from the card. Bit 30 of the
response received from the card is set to 1 by the ROM, and this modified value is used as the argument
for subsequent CMD1. This is done to indicate to the card that the ROM supports sector addressing. This
mode might not be compatible with older (older than v4.4) versions of cards.
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Figure 5-19. MMC/SD Detection Procedure
MMC / SD detection
Send CMD1 command
No response received
Timeout
waiting for
answer?
Response received
Send CMD55
Send ACMD41
Timeout
waiting for
answer?
Yes
No
MMC device
SD device
No device detected
The contents of an MMC/SD card or an eMMC/eSD device can be formatted as raw binary or within a
FAT file system. The ROM Code reads out raw sectors from image or the booting file within the file
system and boots from it.
5.2.6.5.5 MMC/SD Read Sector Procedure in Raw Mode
In
•
•
•
•
raw mode the booting image can be located at one of the four consecutive locations in the main area:
offset 0x0
0x40000 (256KB)
0x80000 (512KB)
0xC0000 (768KB)
A booting image must not exceed 256KB in size. However, it is possible to flash a device with an image
greater than 256KB starting at one of the four locations and the ROM Code will not check the image size.
The only drawback is that the image will cross the subsequent image boundary.
The raw mode is detected by reading sectors #0 and #1024. The content of these sectors is then verified
for presence of a TOC structure as described in 10. In the case of a GP Device, a Configuration Header
(CH) must be located in the first sector followed by a GP header (9). The CH might be void (only containing
a CHSETTINGS item for which the valid field is zero).
(9)
See Section 5.2.9, Image Format.
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5.2.6.5.6 MMC/SD Read Sector Procedure in FAT Mode
MMC/SD cards or eMMC/eSD devices hold a FAT file system which ROM Code reads and processes.
The image used by the booting procedure is taken from a specific booting file named “MLO”. This file must
be in the root directory on an active primary partition of type FAT16 or FAT32. Please refer to [8] and [10]
for a more detailed description of MMC/SD file system support.
An MMC/SD card or eMMC/eSD device can be configured either as floppy-like or hard-drive-like.
• When acting as floppy-like, the content is a single file system without any Master Boot Record (MBR)
holding a partition table.
• When acting as hard-drive-like, an MBR is present in the first sector. This MBR holds a table of
partitions, one of which must be FAT16/32, primary and active.
According to [8], the card or eMMC/eSD device should always hold an MBR except for ones using floppylike file system (please refer to the CSD internal Register fields FILE_FORMAT_GRP and FILE_FORMAT
in [6]). However, depending on the used operating system the MMC/SD card or device will be formatted
either with partitions (using an MBR) or without. The ROM Code supports both types, described in the
following section.
The ROM Code retrieves a map of the booting file from the FAT table. The booting file map is a collection
of all FAT table entries related to the booting file (a FAT entry points to a cluster holding part of the file).
The booting procedure uses this map to access any 512 byte sector within the booting file without
involving ROM Code FAT module.
The sector read procedure utilizes standard MMC/SD raw data read function. The sector address is
generated based on the booting memory file map collected during the initialization. Hence the ROM Code
can address sectors freely within the booting file space.
5.2.6.5.7 FAT File System
The following sections describe functions used by the ROM Code but do not fully describe the Master
Boot Record and the FAT file system:
• Recognize if a sector is the 1st sector of an MBR
• Recognize if a sector is the 1st sector of a FAT16/32
• Find the 1st cluster of the booting file
• Buffer the booting file FAT entries.
If true, an active FAT 16/32 partition is searched in all 4 MBR partition entries, based on the type field. If
the MBR entries are not valid, or if no useable partition is found, then the ROM Code returns to the
booting procedure with FAIL. The extended partitions are not checked. The booting file must reside in a
primary partition.
If a partition is found, then its first sector is read and used further on. If no MBR is present (if a floppy-like
system), the first sector of the device is read and used further on.
The read sector is checked to be a valid FAT16 or FAT32 partition. If this fails, and another partition type
is used (that is, Linux FS or any other), or if the partition is not valid, the ROM Code returns with FAIL.
Otherwise, the root directory entries are searched for a file named depending on the booting device. The
Long File Names (LFN) format is not used and only file names in 8.3 format are searched for. If no valid
file is found, the ROM Code returns with FAIL.
Once the file is found, the ROM Code reads the File Allocation Table (FAT) and buffers the single-linked
chain of clusters in a FAT Buffer which the booting procedure uses to access the file directly sector by
sector. For FAT16 and FAT32 (valid if a specific flag has been set in the FAT32 Boot Sector), multiples
copies of the FAT exist (ROM Code supports only two copies). When buffering FAT entries, the two FATs
are compared. If they do not match, only entries from the last FAT are used. The FAT Buffer holds sector
numbers and not cluster numbers. The ROM Code converts each cluster entry to one or several sector
entries, if applicable.
Figure 5-20 shows the whole process.
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Figure 5-20. SD/MMC Booting, Get Booting File
Get Booting File
Failed
Read 1st sector
Is there an
active primary
FAT 12/16/32
partition?
Yes
Is there an
MBR?
No
No
Yes
Read partition 1st sector
Is this a
FAT12/16/32
partition?
Failed
No
Yes
Failed
Find booting file
in the root directory
Passed
Failed
Buffers FAT entries in FAT
Buffer
Passed
Failed
Success
5.2.6.5.7.1 Master Boot Record (MBR)
The Master Boot Record is the 1st sector of a memory device. It is made out of some executable code
and 4 partition entries. The aim of such a structure is to divide the hard disk in partitions mostly used to
boot different systems (Microsoft Windows®, Linux, or others). Table 5-26 and Table 5-27 describe the
structure. Table 5-28 describes the valid partition types searched by the ROM Code.
Table 5-26. Master Boot Record Structure
Offset
Length (bytes)
Entry Description
0000h
446
Optional Code
01BEh
16
Partition Table Entry
(see Table 5-27)
01CEh
16
Partition Table Entry
(see Table 5-27)
01DEh
16
Partition Table Entry
(see Table 5-27)
01EEh
16
Partition Table Entry
(see Table 5-27)
01FEh
2
Signature
AA55h
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Table 5-27. Partition Entry
Offset
Length (bytes)
Entry Description
Value
0000h
1
Partition State
00h: Inactive
80h: Active
0001h
1
Partition Start Head
Hs
0002h
2
Partition Start Cylinder and Sector
Cs[7:0]-Cs[9:8]-Ss[5:0]
0004h
1
Partition Type
See Table 5-28 for partial partition types
0005h
1
Partition End Head
He
0006h
2
Partition End Cylinder and Sector
Ce[7:0]-Ce[9:8]-Se[5:0]
0008h
4
First sector position relative to the
beginning of media
LBAs=Cs.H.S+ Hs.S+ Ss-1
000Ch
4
Number of sectors in partition
LBAe=Ce.H.S+ He.S+ Se-1
Nbs= LBAe-LBAs+1
Table 5-28. Partition Types
Partition Type
Description
04h, 06h, 0Eh
FAT16
0Bh, 0Ch, 0Fh
FAT32
Figure 5-21 shows whether the ROM Code detects a sector is the 1st sector of an MBR.
The ROM Code first checks if the signature is present. Each partition entry is checked:
• If the type is 00h then all fields in the entry must be 00h.
• The partition is checked to be within physical boundaries, that is, the partition is located inside and its
size fits the total physical sectors.
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Figure 5-21. MBR Detection Procedure
MBR detection
No
0xAA55 Signature
at offset 0x01FE ?
Yes
Are all fields
0x00 ?
No
No
No
Is partition
within
physical
boundaries?
Yes
For all 4 entries
Yes
Partition type
is 0x00 ?
Yes
Failed
Success
Once identified, the ROM Code gets the partition using the procedure shown in Figure 5-22. The partition
type is checked to be FAT16 or FAT32. Its state must be 00h or 80h. If than one active partition exists, the
test fails. The ROM Code returns FAIL if no active primary FAT16/32 is found.
Figure 5-22. MBR, Get Partition
MBR get partition
Partition type
is
FAT12/16/32
No
No
Is it active
Yes
Yes
For all 4 entries
Yes
An active
partition has
already been
found
No
No
An active
partition was
found
Yes
Failed
Success
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5.2.6.5.7.2 FAT16/32 Boot Sector
The FAT file system includes:
• Boot sector which holds the BIOS Parameter Block (BPB)
• File Allocation Table (FAT) which describes the use of each cluster of the partition
• Data area which holds the files, directories and root directory (for FAT16, the root directory has a
specific fixed location).
Table 5-29 describes the boot sector. For more details, refer to [12]. Note: In the following description, all
the fields whose names start with BPB_ are part of the BPB. All the fields whose names start with BS_ are
part of the Boot Sector. They are not part of the BPB (not mandatory) and they are not used by the ROM
Code.
Table 5-29. FAT Boot Sector
Offset
Length (bytes)
Name
Description
0000h
3
BS_jmpBoot
Jump Instruction to Boot Code (not used)
0003h
8
BS_OEMName
Name of the System which created the partition
000Bh
2
BPB_BytsPerSec
Bytes per sector (usually 512)
000Dh
1
BPB_SecPerClus
Number of sectors per allocation unit
000Eh
2
BPB_RsvdSecCnt
Number of reserved sectors for the Boot Sector. For
FAT16 is 1, for FAT32, usually 32
0010h
1
BPB_NumFATs
Number of copies of FAT, usually 2
0011h
2
BPB_RootEntCnt
For FAT16, number of 32-byte entries in the Root
Directory (multiple of BPB_BytsPerSec/32). For
FAT32 this value is 0.
0013h
2
BPB_TotSec16
Total Count of sectors on the volume. If the size is
bigger than 10000h or for FAT32, this field is 0 and
BPB_TotSec32 holds the value
0015h
1
BPB_Media
Media Type, usually F8h: fixed, non-removable
0016h
2
BPB_FATSz16
For FAT16, size in sectors of one FAT. For FAT32,
holds 0
0018h
2
BPB_SecPerTrk
Number of sectors per track, 63 for SD/MMC
001Ah
2
BPB_NumHeads
Number of heads, 255 for SD/MMC
001Ch
4
BPB_HiddSec
Number of sectors preceding the partition
0020h
4
BPB_TotSec32
Total Count of sectors on the volume. If the size is
smaller than 10000h (for FAT16), this field is 0 and
BPB_TotSec16 is valid
0024h
1
BS_DrvNum
Drive Number
0025h
1
BS_Reserved1
00h
0026h
1
BS_BootSig
Extended Boot Signature 29h. Indicates that the
following three fields are present
0027h
4
BS_VolID
Volume Serial Number
002Bh
11
BS_VolLab
Volume Label
0036h
8
BS_FilSysType
File system Type: “FAT16”, “FAT32”. Note: This
field is not mandatory (BS_) and cannot identify the
partition type.
FAT16
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Table 5-29. FAT Boot Sector (continued)
Offset
Name
Description
0024h
Length (bytes)
4
BPB_FATSz32
Size in sectors of one FAT. Field BPB_FATSz16
must be 0
0028h
2
BPB_ExtFlags
FAT Flags:
[7]: 0=FAT is mirrored; 1=Only one FAT is used
[3:0]: Number of used FAT if no mirroring used
002Ah
2
BPB_FSVer
File system Version Number
002Ch
4
BPB_RootClus
First Cluster number of the Root Directory
0030h
2
BPB_FSInfo
Sector number of FSINFO Structure in the
reserved-area, usually 1
0032h
2
BPB_BkBootSec
If non-zero, indicates the sector number in the
reserved-area of a copy of the Boot Sector
0034h
12
BPB_Reserved
Reserved, set to 00h
0040h
1
BS_DrvNum
Drive Number
0041h
1
BS_Reserved1
00h
0042h
1
BS_BootSig
Extended Boot Signature 29h. Indicates that the
following 3 fields are present
0043h
4
BS_VolID
Volume Serial Number
0047h
11
BS_VolLab
Volume Label
0052h
8
BS_FilSysType
File system Type: “FAT16”, “FAT32”. Note: This
field is not mandatory (BS_) and cannot identify the
partition type.
2
BPB_Signature
AA55h
FAT32
01FEh
To check whether a sector holds a valid FAT16/32 partition, only fields starting with BPB can be checked
because they are mandatory. The fields starting from offset 0024h to 01FDh cannot be used for the check
because they differ when using FAT16 or FAT32. Figure 5-23 describes the procedure.
1. The ROM Code checks if the BPB_Signature is equal to AA55h.
2. The ROM Code checks some fields which must have some values: BPB_BytsPerSec,
BPB_SecPerClus, BPB_RsvdSecCnt, BPB_NumFATs, BPB_RootEntCnt
3. If the geometry of the device is known (valid CHS for device size < 4GB) then it is compared against
BPB_SecPerTrk and BPB_NumHeads fields
4. If an MBR was found before, the partition size is also checked:
BPB_TotSec16 = MBR_Partition_Size
or
BPB_TotSec32 = MBR_Partition_Size
5. The field BPB_ToSec16 is used if the total number of sectors is below 65518 (in this case
BPB_TotSec32 = 0). Otherwise, BPB_TotSec32 is used (BPB_TotSec16=0).
6. The partition sector offset is also checked: BPB_HiddSec = MBR_Partition_Offset (if this value is not 0
as some operating systems do not update this field correctly).
7. The last step is to decide the type of FAT file system. The ROM Code computes the number of
clusters in the Data Area part of the partition:
Nbclusters < 4085 Þ FAT12
4085 £ Nbclusters < 65525 Þ FAT16
65525 £ Nbclusters Þ FAT32
(1)
where Nbclusters is given by the size of the data area:
BPB_RootEntCnt*32
BPB_BytesPerSec
DataSec = BPB_TotSec - (BPB_ResvdSecCnt + (BPB_NumFATs.BPB_FATSz) + RootDirSectors)
RootDirSectors =
Nbclusters =
DataSec
BPB_SecPerClus
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Figure 5-23. FAT Detection Procedure
Is there a FAT?
Yes
0xAA55
at offset 0x01FE
No
BPB_BytsPerSec
=
512
BPB_SecPerClus
=
1, 2, 4, 8, 16,
32, 64 or 128
Yes
No
No
BPB_RsvdSecCnt
>
0
Yes
No
BPB_NumFATs
=
2
BPB_RootEntCnt
multiple of
BPB_BytsPerSec/
32
or 0
Yes
No
Yes
Was there
an MBR?
BPB_TotSec16 or
BPB_TotSec32
=
MBR_Partition_Size
Yes
Yes
No
Yes
No
No
Compute data area size to
determine FAT type
Failed
Success:
FAT12,
FAT16 or
FAT32
5.2.6.5.7.3 FAT16/32 Root Directory
Next, the ROM Code finds the booting file named “MLO” inside the root directory of the FAT16/32 file
system. The file is not searched in any other location.
For a FAT16 file system, the root directory has a fixed location which is cluster 0. For a FAT32 file system,
its cluster location is given by BPB_RootClus. The general formulae to find the sector number (relative to
device sector 0, not partition sector 0) of a cluster is given by:
Clustersector = BPB_HiddSec + BPB_RsvdSecCnt + BPB_NumFATs × BPB_FATSz + Cluster × BPB_SecPerClus
(3)
Note: the BPB_HiddSec field can contain 0 even if the FAT file system is located somewhere other than
on sector 0 (floppy-like). The ROM Code actually uses the partition offset taken from the MBR instead of
this field, which can be wrong. If no MBR is found (floppy-like), the value 0 is used.
Each entry in the root directory is 32 bytes long and holds information about the file such as filename, date
of creation, rights, and cluster location. Table 5-30 describes more.
The ROM Code checks each entry in the root directory until either the booting file is found or the entry is
empty (first byte is 00h), or when the end of the root directory is reached. Entries with an
ATTR_LONG_NAME attribute (LFN) and with first byte at E5h (erased file) are ignored. When found, the
first cluster offset of the file is read from the DIR_FstClusHi and DIR_FstClusLo fields.
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There is a slight difference between FAT16 and FAT32 when handling the Root Directory. On FAT16, this
directory has a fixed location and length fixed by BPB_RootEntCnt which is the total number of 32-byte
entries. Handling this directory is therefore straightforward. On FAT32, the root directory is like a standard
file. The File Allocation Table (FAT) must retrieve each sector of the directory.
Table 5-30. FAT Directory Entry
Offset
Length
(bytes)
Name
Description
0000h
11
DIR_Name
Short Name (8+3)
000Bh
1
DIR_Attr
File Attributes:
ATTR_READ_ONLY
01h
ATTR_HIDDEN
02h
ATTR_SYSTEM
04h
ATTR_VOLUME_ID
08h
ATTR_DIRECTORY
10h
ATTR_ARCHIVE
20h
ATTR_LONG_NAME
ATTR_READ_ONLY |
ATTR_HIDDEN |
ATTR_SYSTEM |
ATTR_VOLUME_ID
000Ch
1
DIR_NTRes
Reserved, set to 00h
000Dh
1
DIR_CrtTimeTenth
Millisecond stamp at file creation
000Eh
2
DIR_CrtTime
Time file was created
0010h
2
DIR_CrtDate
Date file was created
0012h
2
DIR_LstAccDate
Last Access date
0014h
2
DIR_FstClusHi
High word of this entry’s first cluster number
0016h
2
DIR_WrtTime
Time of last write
0018h
2
DIR_WrtDate
Date of last write
001Ah
2
DIR_FstClusLo
Low word of this entry’s first cluster number
001Ch
4
DIR_FileSize
File size in bytes
5.2.6.5.7.4 FAT16/32 File Allocation Table
The ROM Code must read the FAT to retrieve sectors either for the booting file or for the root directory (if
the file system is FAT32). There can be multiple copies of the FAT inside the file system (ROM Code
supports only 2) located after the boot sector:
FATnsector = BPB_HiddSec + BPB_RsvdSecCnt + BPB_FATSz × n
(4)
Its size is given by BPB_FATSz16 or BPB_FATSz32. The ROM Code checks each copy of the FAT if
identical. If the values are different, the ROM Code uses the value from the last FAT copy. With the
FAT32 file system, the copy system can be disabled according to a flag located in BPB_ExtFlags[7]. If this
flag is set, then FAT BPB_ExtFlags[3:0] is used and the ROM Code verifies no other copies of FAT.
The FAT is a simple array of values each referring to a cluster located in the data area. One entry of the
array is 16- or 32-bit depending on the file system.
The value inside an entry defines whether the cluster is being used and if another cluster must be taken
into account. This creates a single-linked chain of clusters defining the file. The meaning of an entry is
described in Table 5-31.
Note: For compatibility reasons, clusters 0 and 1 are not used for files and those entries must contain
FFF8h and FFFFh (for FAT16) and ?FFFFFF8h and ?FFFFFFFh (for FAT32).
SPRUHL7I – April 2014 – Revised December 2019
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Initialization 223
Functional Description
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Table 5-31. FAT Entry Description
FAT16
FAT32
Description
0000h
?0000000h
Free Cluster
0001h
?0000001h
Reserved Cluster
0002h-FFEFh
00000002h-?FFFFFEFh
Used Cluster; value points to next cluster
FFF0h-FFF6h
?FFFFFF0h-?FFFFFF6h
Reserved values
FFF7h
?FFFFFF7h
Bad Cluster
FFF8h-FFFFh
?FFFFFF8h-?FFFFFFFh
Last Cluster in File
Note: FAT32 uses only bits [27:0]. The upper 4 bits are usually 0 and should be left untouched. When
accessing the root directory for FAT32, the ROM Code starts from the root directory cluster entry and
follows the linked chain to retrieve the clusters.
When the booting file is found, the ROM Code buffers each FAT entry corresponding to the file in a sector
way. This means each cluster is translated to one or several sectors depending on the number of sectors
in a cluster (BPB_SecPerClus). This buffer is used later by the booting procedure to access the file.
5.2.6.5.8 Pins Used
Table 5-32 and Table 5-33 list the device pins configured by the ROM for MMC boot mode. Not all pins
are driven at boot time.
Table 5-32. Pins Used for MMC0 Boot
Signal name
Pin used
CTRL_CONF Register
Register Setting
clk
mmc0_clk
CTRL_CONF_MMC0_CLK
0x08050000
cmd
mmc0_cmd
CTRL_CONF_MMC0_CMD
0x08060000
dat0
mmc0_dat0
CTRL_CONF_MMC0_DAT0
0x08060000
dat1
mmc0_dat1
CTRL_CONF_MMC0_DAT1
0x08060000
dat2
mmc0_dat2
CTRL_CONF_MMC0_DAT2
0x08060000
dat3
mmc0_dat3
CTRL_CONF_MMC0_DAT3
0x0806000