Texas Instruments | DRA71x and DRA72x (Rev. D) | User Guides | Texas Instruments DRA71x and DRA72x (Rev. D) User guides

Texas Instruments DRA71x and DRA72x (Rev. D) User guides
DRA72x (SR2.0, SR1.0)
DRA71x (SR2.1, SR2.0)
SoC for Automotive Infotainment
Texas Instruments Jacinto6 Eco and Jacinto6 Entry
Infotainment Families of Products
Technical Reference Manual
Literature Number: SPRUIC2D
January 2017 – Revised April 2019
Contents
Revision History ........................................................................................................................ 359
Preface ..................................................................................................................................... 360
1
Introduction ..................................................................................................................... 367
1.1
1.2
1.3
1.4
1.5
1.6
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Memory Mapping .............................................................................................................. 384
2.1
2.2
2.3
2.4
2.5
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DRA72x, DRA71x Overview.............................................................................................
DRA72x, DRA71x Environment .........................................................................................
DRA72x, DRA71x Description ..........................................................................................
1.3.1 MPU Subsystem .................................................................................................
1.3.2 DSP Subsystem..................................................................................................
1.3.3 PRU-ICSS ........................................................................................................
1.3.4 IPU Subsystems .................................................................................................
1.3.5 IVA-HD Subsystem ..............................................................................................
1.3.6 Display Subsystem ..............................................................................................
1.3.7 Video Processing Subsystem ..................................................................................
1.3.8 Video Capture ....................................................................................................
1.3.9 3D GPU Subsystem ............................................................................................
1.3.10 BB2D Subsystem ...............................................................................................
1.3.11 Camera Interface Subsystem .................................................................................
1.3.12 On-Chip Debug Support .......................................................................................
1.3.13 Power, Reset, and Clock Management ......................................................................
1.3.14 On-Chip Memory ................................................................................................
1.3.15 Memory Management ..........................................................................................
1.3.16 External Memory Interfaces ...................................................................................
1.3.17 System and Connectivity Peripherals ........................................................................
1.3.17.1 System Peripherals........................................................................................
1.3.17.2 Media Connectivity Peripherals ..........................................................................
1.3.17.3 Car Connectivity Peripherals .............................................................................
1.3.17.4 Audio Connectivity Peripherals ..........................................................................
1.3.17.5 Serial Control Peripherals ................................................................................
1.3.17.6 Radio Accelerators ........................................................................................
DRA72x, DRA71x Family ................................................................................................
DRA72x, DRA71x Device Identification ................................................................................
DRA72x, DRA71x Package Characteristics Overview ..............................................................
Introduction ................................................................................................................
L3_MAIN Memory Map ..................................................................................................
2.2.1 L3_INSTR Memory Map ........................................................................................
L4 Memory Map ...........................................................................................................
2.3.1 L4_CFG Memory Map ..........................................................................................
2.3.2 L4_WKUP Memory Map ........................................................................................
2.3.3 L4_PER Memory Map ...........................................................................................
2.3.3.1
L4_PER1 Memory Map ...................................................................................
2.3.3.2
L4_PER2 Memory Map ...................................................................................
2.3.3.3
L4_PER3 Memory Map ...................................................................................
MPU Memory Map ........................................................................................................
IPU Memory Map .........................................................................................................
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2.6
2.7
2.8
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DSP Memory Map ........................................................................................................ 406
PRU-ICSS Memory Map ................................................................................................. 407
TILER View Memory Map ............................................................................................... 408
Power, Reset, and Clock Management................................................................................. 409
3.1
3.2
3.3
3.4
3.5
Device Power Management Introduction ..............................................................................
3.1.1 Device Power-Management Architecture Building Blocks..................................................
3.1.1.1
Clock Management ........................................................................................
3.1.1.1.1 Module Interface and Functional Clocks ...........................................................
3.1.1.1.2 Module-Level Clock Management ..................................................................
3.1.1.1.3 Clock Domain ..........................................................................................
3.1.1.1.4 Clock Domain-Level Clock Management ..........................................................
3.1.1.1.5 Clock Domain HW_AUTO Mode Sequences .....................................................
3.1.1.1.6 Clock Domain Sleep/Wake-up ......................................................................
3.1.1.1.7 Clock Domain Dependency ..........................................................................
3.1.1.2
Power Management .......................................................................................
3.1.1.2.1 Power Domain .........................................................................................
3.1.1.2.2 Module Logic and Memory Context ................................................................
3.1.1.2.3 Power Domain Management ........................................................................
3.1.1.3
Voltage Management .....................................................................................
3.1.1.3.1 Voltage Domain .......................................................................................
3.1.1.3.2 Voltage Domain Management .......................................................................
3.1.1.3.3 AVS Overview .........................................................................................
3.1.2 Power-Management Techniques ..............................................................................
3.1.2.1
Standby Leakage Management .........................................................................
3.1.2.2
Dynamic Voltage and Frequency Scaling ..............................................................
3.1.2.3
Dynamic Power Switching ................................................................................
3.1.2.4
Adaptive Voltage Scaling .................................................................................
3.1.2.5
Adaptive Body Bias .......................................................................................
3.1.2.6
SR3-APG (Automatic Power Gating) ...................................................................
3.1.2.7
Combining Power-Management Techniques ..........................................................
3.1.2.7.1 DPS Versus SLM .....................................................................................
PRCM Subsystem Overview ............................................................................................
3.2.1 Introduction .......................................................................................................
3.2.2 Power-Management Framework Features ...................................................................
PRCM Subsystem Environment ........................................................................................
3.3.1 External Clock Signals ..........................................................................................
3.3.2 External Boot Signals ...........................................................................................
3.3.3 External Reset Signals ..........................................................................................
3.3.4 External Voltage Inputs .........................................................................................
PRCM Subsystem Integration ...........................................................................................
3.4.1 Device Power-Management Layout ...........................................................................
3.4.2 Power-Management Scheme, Reset, and Interrupt Requests.............................................
3.4.2.1
Power Domain .............................................................................................
3.4.2.2
Resets.......................................................................................................
3.4.2.3
PRCM Interrupt Requests ................................................................................
Reset Management Functional Description ...........................................................................
3.5.1 Overview ..........................................................................................................
3.5.1.1
PRCM Reset Management Functional Description ...................................................
3.5.1.1.1 Power-On Reset ......................................................................................
3.5.1.1.2 Warm Reset ...........................................................................................
3.5.1.2
PRM Reset Management Functional Description .....................................................
3.5.2 General Characteristics of Reset Signals ....................................................................
3.5.2.1
Scope .......................................................................................................
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3.5.2.2
Occurrence .................................................................................................
3.5.2.3
Source Type ................................................................................................
3.5.2.4
Retention Type .............................................................................................
3.5.3 Reset Sources....................................................................................................
3.5.3.1
Global Reset Sources .....................................................................................
3.5.3.2
Local Reset Sources ......................................................................................
3.5.4 Reset Logging ....................................................................................................
3.5.5 Reset Domains ...................................................................................................
3.5.6 Reset Sequences ................................................................................................
3.5.6.1
MPU Subsystem Power-On Reset Sequence .........................................................
3.5.6.2
MPU Subsystem Warm Reset Sequence ..............................................................
3.5.6.3
MPU Subsystem Reset Sequence on Sleep and Wake-Up Transitions From RETENTION
State .........................................................................................................
3.5.6.4
IVA Subsystem Power-On Reset Sequence ...........................................................
3.5.6.5
IVA Subsystem Software Warm Reset Sequence ....................................................
3.5.6.6
DSP1 Subsystem Power-On Reset Sequence ........................................................
3.5.6.7
DSP1 Subsystem Software Warm Reset Sequence..................................................
3.5.6.8
IPU1 Subsystem Power-On Reset Sequence .........................................................
3.5.6.9
IPU1 Subsystem Software Warm Reset Sequence...................................................
3.5.6.10 IPU2 Subsystem Power-On Reset Sequence .........................................................
3.5.6.11 IPU2 Subsystem Software Warm Reset Sequence...................................................
3.5.6.12 Global Warm Reset Sequence ..........................................................................
Clock Management Functional Description ...........................................................................
3.6.1 Overview ..........................................................................................................
3.6.2 External Clock Inputs ............................................................................................
3.6.2.1
FUNC_32K_CLK Clock ..................................................................................
3.6.2.2
High-Frequency System Clock Input ....................................................................
3.6.2.3
External Reference Clock Input .........................................................................
3.6.3 Internal Clock Sources and Generators ......................................................................
3.6.3.1
PRM Clock Source ........................................................................................
3.6.3.2
CM Clock Source ..........................................................................................
3.6.3.2.1 CM_CORE_AON Clock Generator .................................................................
3.6.3.2.2 CM_CORE_AON_CLKOUTMUX Overview .......................................................
3.6.3.2.3 CM_CORE_AON_TIMER Overview ...............................................................
3.6.3.2.4 CM_CORE_AON_MCASP Overview ..............................................................
3.6.3.3
Generic DPLL Overview ..................................................................................
3.6.3.3.1 Generic APLL Overview..............................................................................
3.6.3.3.2 DPLLs Output Clocks Parameters ..................................................................
3.6.3.3.3 Enable Control, Status, and Low-Power Operation Mode .......................................
3.6.3.3.4 DPLL Power Modes ..................................................................................
3.6.3.3.5 DPLL Recalibration ...................................................................................
3.6.3.3.6 DPLL Output Power Down ...........................................................................
3.6.3.4
DPLL_PER Description ...................................................................................
3.6.3.4.1 DPLL_PER Overview .................................................................................
3.6.3.4.2 DPLL_PER Synthesized Clock Parameters .......................................................
3.6.3.4.3 DPLL_PER Power Modes ...........................................................................
3.6.3.4.4 DPLL_PER Recalibration ............................................................................
3.6.3.5
DPLL_CORE Description .................................................................................
3.6.3.5.1 DPLL_CORE Overview ..............................................................................
3.6.3.5.2 DPLL_CORE Synthesized Clock Parameters .....................................................
3.6.3.5.3 DPLL_CORE Power Modes .........................................................................
3.6.3.5.4 DPLL_CORE Recalibration ..........................................................................
3.6.3.6
DPLL_ABE Description ...................................................................................
3.6.3.6.1 DPLL_ABE Overview .................................................................................
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3.6.3.6.2 DPLL_ABE Synthesized Clock Parameters .......................................................
3.6.3.6.3 DPLL_ABE Power Modes ...........................................................................
3.6.3.6.4 DPLL_ABE Recalibration ............................................................................
3.6.3.7
DPLL_MPU Description ..................................................................................
3.6.3.7.1 DPLL_MPU Overview ................................................................................
3.6.3.7.2 DPLL_MPU Tactical Clocking Adjustment .........................................................
3.6.3.7.3 DPLL_MPU Synthesized Clock Parameters ......................................................
3.6.3.7.4 DPLL_MPU Power Modes ...........................................................................
3.6.3.7.5 DPLL_MPU Recalibration ............................................................................
3.6.3.8
DPLL_IVA Description ....................................................................................
3.6.3.8.1 DPLL_IVA Overview ..................................................................................
3.6.3.8.2 DPLL_IVA Synthesized Clock Parameters ........................................................
3.6.3.8.3 DPLL_IVA Power Modes.............................................................................
3.6.3.8.4 DPLL_IVA Recalibration .............................................................................
3.6.3.9
DPLL_USB Description ...................................................................................
3.6.3.9.1 DPLL_USB Overview .................................................................................
3.6.3.9.2 DPLL_USB Synthesized Clock Parameters .......................................................
3.6.3.9.3 DPLL_USB Power Modes ...........................................................................
3.6.3.9.4 DPLL_USB Recalibration ............................................................................
3.6.3.10 DPLL_DSP Description ...................................................................................
3.6.3.10.1 DPLL_DSP Overview ................................................................................
3.6.3.10.2 DPLL_DSP Synthesized Clock Parameters .......................................................
3.6.3.10.3 DPLL_DSP Power Modes ...........................................................................
3.6.3.10.4 DPLL_DSP Recalibration ............................................................................
3.6.3.11 DPLL_GMAC Description ................................................................................
3.6.3.11.1 DPLL_GMAC Overview ..............................................................................
3.6.3.11.2 DPLL_GMAC Synthesized Clock Parameters ....................................................
3.6.3.11.3 DPLL_GMAC Power Modes .........................................................................
3.6.3.11.4 DPLL_GMAC Recalibration .........................................................................
3.6.3.12 DPLL_GPU Description...................................................................................
3.6.3.12.1 DPLL_GPU Overview ................................................................................
3.6.3.12.2 DPLL_GPU Synthesized Clock Parameters ......................................................
3.6.3.12.3 DPLL_GPU Power Modes ...........................................................................
3.6.3.12.4 DPLL_GPU Recalibration ............................................................................
3.6.3.13 DPLL_DDR Description...................................................................................
3.6.3.13.1 DPLL_DDR Overview ................................................................................
3.6.3.13.2 DPLL_DDR Synthesized Clock Parameters ......................................................
3.6.3.13.3 DPLL_DDR Power Modes ...........................................................................
3.6.3.13.4 DPLL_DDR Recalibration ............................................................................
3.6.3.14 DPLL_PCIE_REF Description ...........................................................................
3.6.3.14.1 DPLL_PCIE_REF Overview .........................................................................
3.6.3.14.2 DPLL_PCIE_REF Synthesized Clock Parameters ...............................................
3.6.3.14.3 DPLL_PCIE_REF Power Modes ...................................................................
3.6.3.15 APLL_PCIE Description ..................................................................................
3.6.3.15.1 APLL_PCIE Overview ................................................................................
3.6.3.15.2 APLL_PCIE Synthesized Clock Parameters ......................................................
3.6.3.15.3 APLL_PCIE Power Modes...........................................................................
3.6.4 Clock Domains ...................................................................................................
3.6.4.1
CD_WKUPAON Clock Domain ..........................................................................
3.6.4.1.1 CD_WKUPAON Overview ...........................................................................
3.6.4.1.2 CD_WKUPAON Clock Domain Modes.............................................................
3.6.4.1.3 CD_WKUPAON Clock Domain Dependency......................................................
3.6.4.1.4 CD_WKUPAON Clock Domain Module Attributes ................................................
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3.6.4.2
CD_DSP1 Clock Domain .................................................................................
3.6.4.2.1 CD_DSP1 Overview ..................................................................................
3.6.4.2.2 CD_DSP1 Clock Domain Modes ...................................................................
3.6.4.2.3 CD_DSP1 Clock Domain Dependency ............................................................
3.6.4.2.4 CD_DSP1 Clock Domain Module Attributes.......................................................
3.6.4.3
CD_CUSTEFUSE Clock Domain........................................................................
3.6.4.3.1 CD_CUSTEFUSE Overview .........................................................................
3.6.4.3.2 CD_CUSTEFUSE Clock Domain Modes ..........................................................
3.6.4.3.3 CD_CUSTEFUSE Clock Domain Dependency ...................................................
3.6.4.3.4 CD_CUSTEFUSE Clock Domain Module Attributes .............................................
3.6.4.4
CD_MPU Clock Domain ..................................................................................
3.6.4.4.1 CD_MPU Overview ...................................................................................
3.6.4.4.2 CD_MPU Clock Domain Modes.....................................................................
3.6.4.4.3 CD_MPU Clock Domain Dependency .............................................................
3.6.4.4.4 CD_MPU Clock Domain Module Attributes........................................................
3.6.4.5
CD_L4PER1 Clock Domain ..............................................................................
3.6.4.5.1 CD_L4PER1 Overview ...............................................................................
3.6.4.5.2 CD_L4PER1 Clock Domain Modes ................................................................
3.6.4.5.3 CD_L4PER1 Clock Domain Dependency .........................................................
3.6.4.5.4 CD_L4PER1 Clock Domain Module Attributes....................................................
3.6.4.6
CD_L4PER2 Clock Domain ..............................................................................
3.6.4.6.1 CD_L4PER2 Overview ...............................................................................
3.6.4.6.2 CD_L4PER2 Clock Domain Modes ................................................................
3.6.4.6.3 CD_L4PER2 Clock Domain Dependency .........................................................
3.6.4.6.4 CD_L4PER2 Clock Domain Module Attributes....................................................
3.6.4.7
CD_L4PER3 Clock Domain ..............................................................................
3.6.4.7.1 CD_L4PER3 Overview ...............................................................................
3.6.4.7.2 CD_L4PER3 Clock Domain Modes ................................................................
3.6.4.7.3 CD_L4PER3 Clock Domain Dependency .........................................................
3.6.4.7.4 CD_L4PER3 Clock Domain Module Attributes....................................................
3.6.4.8
CD_L4SEC Clock Domain ...............................................................................
3.6.4.8.1 CD_L4SEC Overview ................................................................................
3.6.4.8.2 CD_L4SEC Clock Domain Modes ..................................................................
3.6.4.8.3 CD_L4SEC Clock Domain Dependency ...........................................................
3.6.4.8.4 CD_L4SEC Clock Domain Module Attributes .....................................................
3.6.4.9
CD_L3INIT Clock Domain ................................................................................
3.6.4.9.1 CD_L3INIT Overview .................................................................................
3.6.4.9.2 CD_L3INIT Clock Domain Modes ..................................................................
3.6.4.9.3 CD_L3INIT Clock Domain Dependency ...........................................................
3.6.4.9.4 CD_L3INIT Clock Domain Module Attributes .....................................................
3.6.4.10 CD_IVA Clock Domain....................................................................................
3.6.4.10.1 CD_IVA Overview.....................................................................................
3.6.4.10.2 CD_IVA Clock Domain Modes ......................................................................
3.6.4.10.3 CD_IVA Clock Domain Dependency ...............................................................
3.6.4.10.4 CD_IVA Clock Domain Module Attributes .........................................................
3.6.4.11 CD_GPU Description .....................................................................................
3.6.4.11.1 CD_GPU Overview ...................................................................................
3.6.4.11.2 CD_GPU Clock Domain Modes ....................................................................
3.6.4.11.3 CD_GPU Clock Domain Dependency .............................................................
3.6.4.11.4 CD_GPU Clock Domain Module Attributes........................................................
3.6.4.12 CD_EMU Clock Domain ..................................................................................
3.6.4.12.1 CD_EMU Overview ...................................................................................
3.6.4.12.2 CD_EMU Clock Domain Modes ....................................................................
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3.6.4.12.3 CD_EMU Clock Domain Dependency .............................................................
3.6.4.12.4 CD_EMU Clock Domain Module Attributes .......................................................
3.6.4.13 CD_DSS Clock Domain ..................................................................................
3.6.4.13.1 CD_DSS Overview ...................................................................................
3.6.4.13.2 CD_DSS Clock Domain Modes .....................................................................
3.6.4.13.3 CD_DSS Clock Domain Dependency ..............................................................
3.6.4.13.4 CD_DSS Clock Domain Module Attributes ........................................................
3.6.4.14 CD_L4_CFG Clock Domain ..............................................................................
3.6.4.14.1 CD_L4_CFG Overview ...............................................................................
3.6.4.14.2 CD_L4_CFG Clock Domain Modes ................................................................
3.6.4.14.3 CD_L4_CFG Clock Domain Dependency .........................................................
3.6.4.14.4 CD_L4_CFG Clock Domain Module Attributes ...................................................
3.6.4.15 CD_L3_INSTR Clock Domain ...........................................................................
3.6.4.15.1 CD_L3_INSTR Overview ............................................................................
3.6.4.15.2 CD_L3_INSTR Clock Domain Modes ..............................................................
3.6.4.15.3 CD_L3_INSTR Clock Domain Dependency .......................................................
3.6.4.15.4 CD_L3_INSTR Clock Domain Module Attributes .................................................
3.6.4.16 CD_L3_MAIN1 Clock Domain ...........................................................................
3.6.4.16.1 CD_L3_MAIN1 Overview ............................................................................
3.6.4.16.2 CD_L3_MAIN1 Clock Domain Modes ..............................................................
3.6.4.16.3 CD_L3_MAIN1 Clock Domain Dependency.......................................................
3.6.4.16.4 CD_L3_MAIN1 Clock Domain Module Attributes .................................................
3.6.4.17 CD_EMIF Clock Domain .................................................................................
3.6.4.17.1 CD_EMIF Overview ..................................................................................
3.6.4.17.2 CD_EMIF Clock Domain Modes ....................................................................
3.6.4.17.3 CD_EMIF Clock Domain Dependency .............................................................
3.6.4.17.4 CD_EMIF Clock Domain Module Attributes .......................................................
3.6.4.18 CD_IPU Clock Domain ...................................................................................
3.6.4.18.1 CD_IPU Overview ....................................................................................
3.6.4.18.2 CD_IPU Clock Domain Modes ......................................................................
3.6.4.18.3 CD_IPU Clock Domain Dependency ...............................................................
3.6.4.18.4 CD_IPU Clock Domain Module Attributes .........................................................
3.6.4.19 CD_IPU1 Clock Domain ..................................................................................
3.6.4.19.1 CD_IPU1 Overview ...................................................................................
3.6.4.19.2 CD_IPU1 Clock Domain Modes ....................................................................
3.6.4.19.3 CD_IPU1 Clock Domain Dependency .............................................................
3.6.4.19.4 CD_IPU1 Clock Domain Module Attributes .......................................................
3.6.4.20 CD_IPU2 Clock Domain ..................................................................................
3.6.4.20.1 CD_IPU2 Overview ...................................................................................
3.6.4.20.2 CD_IPU2 Clock Domain Modes ....................................................................
3.6.4.20.3 CD_IPU2 Clock Domain Dependency .............................................................
3.6.4.20.4 CD_IPU2 Clock Domain Module Attributes .......................................................
3.6.4.21 CD_DMA Clock Domain ..................................................................................
3.6.4.21.1 CD_DMA Overview ...................................................................................
3.6.4.21.2 CD_DMA Clock Domain Modes ....................................................................
3.6.4.21.3 CD_DMA Clock Domain Dependency .............................................................
3.6.4.21.4 CD_DMA Clock Domain Module Attributes .......................................................
3.6.4.22 CD_ATL Clock Domain ...................................................................................
3.6.4.22.1 CD_ATL Overview ....................................................................................
3.6.4.22.2 CD_ATL Clock Domain Modes .....................................................................
3.6.4.22.3 CD_ATL Clock Domain Module Attributes ........................................................
3.6.4.23 CD_CAM Clock Domain ..................................................................................
3.6.4.23.1 CD_CAM Overview ...................................................................................
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3.6.4.23.2 CD_CAM Clock Domain Modes ....................................................................
3.6.4.23.3 CD_CAM Clock Domain Dependency .............................................................
3.6.4.23.4 CD_CAM Clock Domain Module Attributes .......................................................
3.6.4.24 CD_GMAC Clock Domain ................................................................................
3.6.4.24.1 CD_GMAC Overview .................................................................................
3.6.4.24.2 CD_GMAC Clock Domain Modes ..................................................................
3.6.4.24.3 CD_GMAC Clock Domain Dependency ...........................................................
3.6.4.24.4 CD_GMAC Clock Domain Module Attributes .....................................................
3.6.4.25 CD_VPE Clock Domain...................................................................................
3.6.4.25.1 CD_VPE Overview ...................................................................................
3.6.4.25.2 CD_VPE Clock Domain Modes .....................................................................
3.6.4.25.3 CD_VPE Clock Domain Dependency ..............................................................
3.6.4.25.4 CD_VPE Clock Domain Module Attributes ........................................................
3.6.4.26 CD_RTC Clock Domain ..................................................................................
3.6.4.26.1 CD_RTC Overview ...................................................................................
3.6.4.26.2 CD_RTC Clock Domain Modes .....................................................................
3.6.4.26.3 CD_RTC Clock Domain Dependency ..............................................................
3.6.4.26.4 CD_RTC Clock Domain Module Attributes ........................................................
3.6.4.27 CD_PCIE Clock Domain ..................................................................................
3.6.4.27.1 CD_PCIE Overview...................................................................................
3.6.4.27.2 CD_PCIE Clock Domain Modes ....................................................................
3.6.4.27.3 CD_PCIE Clock Domain Dependency .............................................................
3.6.4.27.4 CD_PCIE Clock Domain Module Attributes .......................................................
Power Management Functional Description...........................................................................
3.7.1 PD_WKUPAON Description ....................................................................................
3.7.1.1
PD_WKUPAON Power Domain Modes ................................................................
3.7.1.1.1 PD_WKUPAON Logic and Memory Area Power Modes ........................................
3.7.2 PD_DSP1 Description ...........................................................................................
3.7.2.1
PD_DSP1 Power Domain Modes .......................................................................
3.7.2.1.1 PD_DSP1 Logic and Memory Area Power Modes ...............................................
3.7.2.1.2 PD_DSP1 Logic and Memory Area Power Modes Control and Status ........................
3.7.3 PD_CUSTEFUSE Description .................................................................................
3.7.3.1
PD_CUSTEFUSE Power Domain Modes ..............................................................
3.7.3.1.1 PD_CUSTEFUSE Logic and Memory Area Power Modes ......................................
3.7.3.1.2 PD_CUSTEFUSE Logic and Memory Area Power Modes Control and Status ...............
3.7.4 PD_MPU Description ............................................................................................
3.7.4.1
PD_MPU Power Domain Modes ........................................................................
3.7.4.1.1 PD_MPU Logic and Memory Area Power Modes ................................................
3.7.4.1.2 PD_MPU Logic and Memory Area Power Modes Control and Status .........................
3.7.4.1.3 PD_MPU Power State Override.....................................................................
3.7.5 PD_IPU Description .............................................................................................
3.7.5.1
PD_IPU Power Domain Modes ..........................................................................
3.7.5.1.1 PD_IPU Logic and Memory Area Power Modes ..................................................
3.7.5.1.2 PD_IPU Logic and Memory Area Power Modes Control and Status ..........................
3.7.6 PD_L3INIT Description ..........................................................................................
3.7.6.1
PD_L3INIT Power Domain Modes ......................................................................
3.7.6.1.1 PD_L3INIT Logic and Memory Area Power Modes ..............................................
3.7.6.1.2 PD_L3INIT Logic and Memory Area Power Modes Control and Status .......................
3.7.7 PD_L4PER Description .........................................................................................
3.7.8 PD_IVA Description .............................................................................................
3.7.8.1
PD_IVA Power Domain Modes ..........................................................................
3.7.8.1.1 PD_IVA Logic and Memory Area Power Modes ..................................................
3.7.8.1.2 PD_IVA Logic and Memory Area Power Modes Control and Status ...........................
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3.8
3.9
3.10
3.7.9 PD_GPU Description ............................................................................................
3.7.9.1
PD_GPU Power Domain Modes ........................................................................
3.7.9.1.1 PD_GPU Logic and Memory Area Power Modes ................................................
3.7.9.1.2 PD_GPU Logic and Memory Area Power Modes Control and Status .........................
3.7.10 PD_EMU Description ...........................................................................................
3.7.11 PD_DSS Description ...........................................................................................
3.7.11.1 PD_DSS Power Domain Modes .........................................................................
3.7.11.1.1 PD_DSS Logic and Memory Area Power Modes.................................................
3.7.11.1.2 PD_DSS Logic and Memory Area Power Mode Control and Status ...........................
3.7.12 PD_CORE Description .........................................................................................
3.7.12.1 PD_CORE Power Domain Modes ......................................................................
3.7.12.1.1 PD_CORE Logic and Memory Area Power Modes ..............................................
3.7.12.1.2 PD_CORE Logic and Memory Area Power Mode Control and Status ........................
3.7.13 PD_CAM Description ...........................................................................................
3.7.13.1 PD_CAM Power Domain Modes ........................................................................
3.7.13.1.1 PD_CAM Logic and Memory Area Power Modes ................................................
3.7.13.1.2 PD_CAM Logic and Memory Area Power Mode Control and Status ..........................
3.7.14 PD_MPUAON Description .....................................................................................
3.7.14.1 PD_MPUAON Power Domain Modes ..................................................................
3.7.15 PD_MMAON Description ......................................................................................
3.7.15.1 PD_MMAON Power Domain Modes ....................................................................
3.7.16 PD_COREAON Description ...................................................................................
3.7.16.1 PD_COREAON Power Domain Modes .................................................................
3.7.17 PD_VPE Description ...........................................................................................
3.7.17.1 PD_VPE Power Domain Modes .........................................................................
3.7.17.1.1 PD_VPE Logic and Memory Area Power Modes .................................................
3.7.17.1.2 PD_VPE Logic and Memory Area Power Modes Control and Status .........................
3.7.18 PD_RTC Description ...........................................................................................
3.7.18.1 PD_RTC Power Domain Modes .........................................................................
3.7.18.1.1 PD_RTC Logic and Memory Area Power Modes.................................................
Voltage-Management Functional Description .........................................................................
3.8.1 Overview ..........................................................................................................
3.8.2 Voltage-Control Architecture ...................................................................................
3.8.3 Internal LDOs Control ...........................................................................................
3.8.3.1
VDD_MPU_L, VDD_CORE_L, and VDD_IVAHD_L, VDD_GPU_L, VDD_DSPEVE_L Control
3.8.3.1.1 Adaptive Voltage Scaling ............................................................................
3.8.3.2
Memory LDOs..............................................................................................
3.8.3.3
ABB LDOs Control ........................................................................................
3.8.3.4
ABB LDO Programming Sequence .....................................................................
3.8.3.4.1 ABB LDO Enable Sequence.........................................................................
3.8.3.4.2 ABB LDO Disable Sequence (Entering in Bypass Mode) .......................................
3.8.3.5
BANDGAPs Control .......................................................................................
3.8.3.6
Memory LDO Transitions .................................................................................
3.8.3.7
VDD_WKUP_L Transitions ...............................................................................
3.8.4 DVFS ..............................................................................................................
Device Low-Power States ...............................................................................................
3.9.1 Device Wake-Up Source Summary ...........................................................................
3.9.2 Wakeup Upon Global Warm Reset ............................................................................
3.9.3 Global Warm Reset During a Device Wake-Up Sequence ................................................
3.9.4 I/O Management .................................................................................................
3.9.4.1
Isolation / Wakeup Sequence ............................................................................
3.9.4.1.1 Software-Controlled I/O Isolation ...................................................................
PRCM Module Programming Guide ....................................................................................
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3.12
10
3.10.1 DPLLs Low-Level Programming Models ....................................................................
3.10.1.1 Global Initialization ........................................................................................
3.10.1.1.1 Surrounding Module Global Initialization ..........................................................
3.10.1.1.2 DPLL Global Initialization ............................................................................
3.10.1.2 DPLL Output Frequency Change........................................................................
3.10.2 Clock Management Low-Level Programming Models .....................................................
3.10.2.1 Global Initialization ........................................................................................
3.10.2.1.1 Surrounding Module Global Initialization ..........................................................
3.10.2.1.2 Clock Management Global Initialization ...........................................................
3.10.2.2 Clock Domain Sleep Transition and Troubleshooting ................................................
3.10.2.3 Enable/Disable Software-Programmable Static Dependency .......................................
3.10.3 Power Management Low-Level Programming Models ....................................................
3.10.3.1 Global Initialization ........................................................................................
3.10.3.1.1 Surrounding Module Global Initialization ..........................................................
3.10.3.1.2 Power Management Global Initialization...........................................................
3.10.3.2 Forced Memory Area State Change With Power Domain ON.......................................
3.10.3.3 Forced Power Domain Low-Power State Transition ..................................................
PRCM Software Configuration for OPP_PLUS .......................................................................
PRCM Register Manual ..................................................................................................
3.12.1 Not Supported Functionality (Registers and Bits) ..........................................................
3.12.2 PRCM Instance Summary .....................................................................................
3.12.3 CM_CORE_AON__CKGEN Registers.......................................................................
3.12.3.1 CM_CORE_AON__CKGEN Register Summary ......................................................
3.12.3.2 CM_CORE_AON__CKGEN Register Description ....................................................
3.12.4 CM_CORE_AON__DSP1 Registers .........................................................................
3.12.4.1 CM_CORE_AON__DSP1 Register Summary ........................................................
3.12.4.2 CM_CORE_AON__DSP1 Register Description ......................................................
3.12.5 CM_CORE_AON__DSP2 Registers .........................................................................
3.12.5.1 CM_CORE_AON__DSP2 Register Summary ........................................................
3.12.5.2 CM_CORE_AON__DSP2 Register Description ......................................................
3.12.6 CM_CORE_AON__EVE1 Registers .........................................................................
3.12.6.1 CM_CORE_AON__EVE1 Register Summary ........................................................
3.12.6.2 CM_CORE_AON__EVE1 Register Description ......................................................
3.12.7 CM_CORE_AON__EVE2 Registers .........................................................................
3.12.7.1 CM_CORE_AON__EVE2 Register Summary ........................................................
3.12.7.2 CM_CORE_AON__EVE2 Register Description ......................................................
3.12.8 CM_CORE_AON__EVE3 Registers .........................................................................
3.12.8.1 CM_CORE_AON__EVE3 Register Summary ........................................................
3.12.8.2 CM_CORE_AON__EVE3 Register Description ......................................................
3.12.9 CM_CORE_AON__EVE4 Registers .........................................................................
3.12.9.1 CM_CORE_AON__EVE4 Register Summary ........................................................
3.12.9.2 CM_CORE_AON__EVE4 Register Description ......................................................
3.12.10 CM_CORE_AON__INSTR Registers.......................................................................
3.12.10.1 CM_CORE_AON__INSTR Register Summary .....................................................
3.12.10.2 CM_CORE_AON__INSTR Register Description ...................................................
3.12.11 CM_CORE_AON__IPU Registers ..........................................................................
3.12.11.1 CM_CORE_AON__IPU Register Summary .........................................................
3.12.11.2 CM_CORE_AON__IPU Register Description .......................................................
3.12.12 CM_CORE_AON__MPU Registers .........................................................................
3.12.12.1 CM_CORE_AON__MPU Register Summary .......................................................
3.12.12.2 CM_CORE_AON__MPU Register Description .....................................................
3.12.13 CM_CORE_AON__OCP_SOCKET Registers ............................................................
3.12.13.1 CM_CORE_AON__OCP_SOCKET Register Summary ...........................................
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SPRUIC2D – January 2017 – Revised April 2019
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3.12.13.2 CM_CORE_AON__OCP_SOCKET Register Description ......................................... 829
3.12.14 CM_CORE_AON__RESTORE Registers .................................................................. 832
3.12.14.1 CM_CORE_AON__RESTORE Register Summary ................................................ 832
3.12.14.2 CM_CORE_AON__RESTORE Register Description .............................................. 834
3.12.15 CM_CORE_AON__RTC Registers ......................................................................... 841
3.12.15.1 CM_CORE_AON__RTC Register Summary ........................................................ 841
3.12.15.2 CM_CORE_AON__RTC Register Description ...................................................... 842
3.12.16 CM_CORE_AON__VPE Registers ......................................................................... 843
3.12.16.1 CM_CORE_AON__VPE Register Summary ........................................................ 843
3.12.16.2 CM_CORE_AON__VPE Register Description ...................................................... 844
3.12.17 CM_CORE__CAM Registers ................................................................................ 846
3.12.17.1 CM_CORE__CAM Register Summary .............................................................. 846
3.12.17.2 CM_CORE__CAM Register Description ............................................................ 847
3.12.18 CM_CORE__CKGEN Registers ............................................................................ 855
3.12.18.1 CM_CORE__CKGEN Register Summary ........................................................... 855
3.12.18.2 CM_CORE__CKGEN Register Description ......................................................... 856
3.12.19 CM_CORE__COREAON Registers ........................................................................ 880
3.12.19.1 CM_CORE__COREAON Register Summary ....................................................... 880
3.12.19.2 CM_CORE__COREAON Register Description ..................................................... 881
3.12.20 CM_CORE__CORE Registers .............................................................................. 891
3.12.20.1 CM_CORE__CORE Register Summary ............................................................. 891
3.12.20.2 CM_CORE__CORE Register Description ........................................................... 893
3.12.21 CM_CORE__CUSTEFUSE Registers ...................................................................... 951
3.12.21.1 CM_CORE__CUSTEFUSE Register Summary .................................................... 951
3.12.21.2 CM_CORE__CUSTEFUSE Register Description .................................................. 952
3.12.22 CM_CORE__DSS Registers ................................................................................ 954
3.12.22.1 CM_CORE__DSS Register Summary ............................................................... 954
3.12.22.2 CM_CORE__DSS Register Description ............................................................. 954
3.12.23 CM_CORE__GPU Registers ................................................................................ 960
3.12.23.1 CM_CORE__GPU Register Summary ............................................................... 960
3.12.23.2 CM_CORE__GPU Register Description ............................................................. 961
3.12.24 CM_CORE__IVA Registers .................................................................................. 964
3.12.24.1 CM_CORE__IVA Register Summary ................................................................ 964
3.12.24.2 CM_CORE__IVA Register Description .............................................................. 965
3.12.25 CM_CORE__L3INIT Registers .............................................................................. 969
3.12.25.1 CM_CORE__L3INIT Register Summary ............................................................ 969
3.12.25.2 CM_CORE__L3INIT Register Description .......................................................... 970
3.12.26 CM_CORE__L4PER Registers ............................................................................. 996
3.12.26.1 CM_CORE__L4PER Register Summary ............................................................ 996
3.12.26.2 CM_CORE__L4PER Register Description .......................................................... 998
3.12.27 CM_CORE__OCP_SOCKET Registers .................................................................. 1077
3.12.27.1 CM_CORE__OCP_SOCKET Register Summary ................................................ 1077
3.12.27.2 CM_CORE__OCP_SOCKET Register Description ............................................... 1077
3.12.28 CM_CORE__RESTORE Registers ....................................................................... 1079
3.12.28.1 CM_CORE__RESTORE Register Summary ...................................................... 1079
3.12.28.2 CM_CORE__RESTORE Register Description .................................................... 1079
3.12.29 SMARTREFLEX Registers ................................................................................. 1084
3.12.29.1 SMARTREFLEX Register Summary ................................................................ 1084
3.12.29.2 SMARTREFLEX Register Description .............................................................. 1086
3.12.30 CAM_PRM Registers........................................................................................ 1094
3.12.30.1 CAM_PRM Register Summary ....................................................................... 1094
3.12.30.2 CAM_PRM Register Description .................................................................... 1095
3.12.31 CKGEN_PRM Registers .................................................................................... 1104
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3.12.31.1 CKGEN_PRM Register Summary ...................................................................
3.12.31.2 CKGEN_PRM Register Description ................................................................
3.12.32 COREAON_PRM Registers ................................................................................
3.12.32.1 COREAON_PRM Register Summary ...............................................................
3.12.32.2 COREAON_PRM Register Description ............................................................
3.12.33 CORE_PRM Registers ......................................................................................
3.12.33.1 CORE_PRM Register Summary .....................................................................
3.12.33.2 CORE_PRM Register Description ..................................................................
3.12.34 CUSTEFUSE_PRM Registers .............................................................................
3.12.34.1 CUSTEFUSE_PRM Register Summary ............................................................
3.12.34.2 CUSTEFUSE_PRM Register Description ..........................................................
3.12.35 DEVICE_PRM Registers ...................................................................................
3.12.35.1 DEVICE_PRM Register Summary ...................................................................
3.12.35.2 DEVICE_PRM Register Description ................................................................
3.12.36 DSP1_PRM registers .......................................................................................
3.12.36.1 DSP1_PRM Register Summary ......................................................................
3.12.36.2 DSP1_PRM Register Description ...................................................................
3.12.37 DSP2_PRM Registers ......................................................................................
3.12.37.1 DSP2_PRM Register Summary ......................................................................
3.12.37.2 DSP2_PRM Register Description ...................................................................
3.12.38 DSS_PRM Registers ........................................................................................
3.12.38.1 DSS_PRM Register Summary .......................................................................
3.12.38.2 DSS_PRM Register Description ....................................................................
3.12.39 EMU_CM Registers .........................................................................................
3.12.39.1 EMU_CM Register Summary .........................................................................
3.12.39.2 EMU_CM Register Description ......................................................................
3.12.40 EMU_PRM Registers........................................................................................
3.12.40.1 EMU_PRM Register Summary ......................................................................
3.12.40.2 EMU_PRM Register Description ....................................................................
3.12.41 EVE1_PRM Registers .......................................................................................
3.12.41.1 EVE1_PRM Register Summary ......................................................................
3.12.41.2 EVE1_PRM Register Description ...................................................................
3.12.42 EVE2_PRM Registers .......................................................................................
3.12.42.1 EVE2_PRM Register Summary ......................................................................
3.12.42.2 EVE2_PRM Register Description ...................................................................
3.12.43 EVE3_PRM Registers .......................................................................................
3.12.43.1 EVE3_PRM Register Summary ......................................................................
3.12.43.2 EVE3_PRM Register Description ...................................................................
3.12.44 EVE4_PRM Registers .......................................................................................
3.12.44.1 EVE4_PRM Register Summary ......................................................................
3.12.44.2 EVE4_PRM Register Description ...................................................................
3.12.45 GPU_PRM Registers ........................................................................................
3.12.45.1 GPU_PRM Register Summary .......................................................................
3.12.45.2 GPU_PRM Register Description ....................................................................
3.12.46 INSTR_PRM Registers .....................................................................................
3.12.46.1 INSTR_PRM Register Summary .....................................................................
3.12.46.2 INSTR_PRM Register Description ..................................................................
3.12.47 IPU_PRM registers ..........................................................................................
3.12.47.1 IPU_PRM Register Summary ........................................................................
3.12.47.2 IPU_PRM Register Description .....................................................................
3.12.48 IVA_PRM Registers .........................................................................................
3.12.48.1 IVA_PRM Register Summary ........................................................................
3.12.48.2 IVA_PRM Register Description ......................................................................
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3.12.49 L3INIT_PRM Registers .....................................................................................
3.12.49.1 L3INIT_PRM Register Summary .....................................................................
3.12.49.2 L3INIT_PRM Register Description ..................................................................
3.12.50 L4PER_PRM Registers .....................................................................................
3.12.50.1 L4PER_PRM Register Summary ....................................................................
3.12.50.2 L4PER_PRM Register Description .................................................................
3.12.51 MPU_PRM Registers........................................................................................
3.12.51.1 MPU_PRM Register Summary .......................................................................
3.12.51.2 MPU_PRM Register Description ....................................................................
3.12.52 OCP_SOCKET_PRM Registers ...........................................................................
3.12.52.1 OCP_SOCKET_PRM Register Summary ..........................................................
3.12.52.2 OCP_SOCKET_PRM Register Description ........................................................
3.12.53 RTC_PRM Registers ........................................................................................
3.12.53.1 RTC_PRM Register Summary ......................................................................
3.12.53.2 RTC_PRM Register Description ....................................................................
3.12.54 VPE_PRM Registers ........................................................................................
3.12.54.1 VPE_PRM Register Summary .......................................................................
3.12.54.2 VPE_PRM Register Description .....................................................................
3.12.55 WKUPAON_CM Registers .................................................................................
3.12.55.1 WKUPAON_CM Register Summary .................................................................
3.12.55.2 WKUPAON_CM Register Description ..............................................................
3.12.56 WKUPAON_PRM registers .................................................................................
3.12.56.1 WKUPAON_PRM Register Summary ...............................................................
3.12.56.2 WKUPAON_PRM Register Description ............................................................
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4.2
4.3
Cortex-A15 MPU Subsystem Overview ..............................................................................
4.1.1 Introduction ......................................................................................................
4.1.2 Features .........................................................................................................
Cortex-A15 MPU Subsystem Integration .............................................................................
4.2.1 Clock Distribution ...............................................................................................
4.2.2 Reset Distribution ..............................................................................................
Cortex-A15 MPU Subsystem Functional Description ...............................................................
4.3.1 MPU Subsystem Block Diagram .............................................................................
4.3.2 Cortex-A15 MPCore (MPU_CLUSTER) .....................................................................
4.3.2.1
MPU L2 Cache Memory System .......................................................................
4.3.2.1.1 MPU L2 Cache Architecture .......................................................................
4.3.2.1.2 MPU L2 Cache Controller ..........................................................................
4.3.3 MPU_AXI2OCP.................................................................................................
4.3.4 Memory Adapter ................................................................................................
4.3.4.1
MPU_MA Overview ......................................................................................
4.3.4.2
AXI Input Interface ......................................................................................
4.3.4.3
Interleaving................................................................................................
4.3.4.3.1 High-Order Fixed Interleaving Model .............................................................
4.3.4.3.2 Lower 2-GiB Programmable Interleaving Model.................................................
4.3.4.3.3 Local Interconnect and Synchronization Agent (LISA) Section Manager ....................
4.3.4.3.4 MA_LSM Registers ..................................................................................
4.3.4.3.5 Posted and Nonposted Writes .....................................................................
4.3.4.3.6 Errors .................................................................................................
4.3.4.4
Statistics Collector Probe Ports .......................................................................
4.3.4.5
MPU_MA Firewall .......................................................................................
4.3.4.6
MPU_MA Power and Reset Management ...........................................................
4.3.4.7
MPU_MA Watchpoint ....................................................................................
4.3.4.7.1 Watchpoint Types ...................................................................................
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1605
1605
1605
1605
1605
1605
1606
1606
1606
1607
1610
1610
1610
1614
1614
1614
1615
1615
1616
1627
1627
1627
1631
1631
1631
1632
1632
1632
1632
1632
1633
DSP Subsystem .............................................................................................................. 1645
5.1
5.2
5.3
14
4.3.4.7.2 Transaction Filtering Options ......................................................................
4.3.4.7.3 Transaction Match Effects ..........................................................................
4.3.4.7.4 Trigger Generation ..................................................................................
4.3.4.7.5 Programming Options Summary ..................................................................
4.3.5 Realtime Counter (Master Counter) .........................................................................
4.3.5.1
Counter Operation .......................................................................................
4.3.5.2
Frequency Change Procedure .........................................................................
4.3.6 MPU Watchdog Timer .........................................................................................
4.3.7 MPU Subsystem Power Management .......................................................................
4.3.7.1
Power Domains ..........................................................................................
4.3.7.2
Power States of MPU_C0...............................................................................
4.3.7.3
Power States of MPU Subsystem .....................................................................
4.3.7.4
MPU_WUGEN ............................................................................................
4.3.7.5
Power Transition Sequence ............................................................................
4.3.7.6
SR3-APG Technology Fail-Safe Mode ................................................................
4.3.8 MPU Subsystem AMBA Interface Configuration ...........................................................
Cortex-A15 MPU Subsystem Register Manual ......................................................................
4.4.1 Cortex-A15 MPU Subsystem Instance Summary ..........................................................
4.4.2 MPU_CS_STM Registers .....................................................................................
4.4.3 MPU_INTC Registers ..........................................................................................
4.4.4 MPU_PRCM_OCP_SOCKET Registers ....................................................................
4.4.4.1
MPU_PRCM_OCP_SOCKET Register Summary ...................................................
4.4.4.2
MPU_PRCM_OCP_SOCKET Register Description .................................................
4.4.5 MPU_PRCM_DEVICE Registers.............................................................................
4.4.5.1
MPU_PRCM_DEVICE Register Summary ...........................................................
4.4.5.2
MPU_PRCM_DEVICE Register Description .........................................................
4.4.6 MPU_PRCM_PRM_C0 Registers ............................................................................
4.4.6.1
MPU_PRCM_PRM_C0 Register Summary ..........................................................
4.4.6.2
MPU_PRCM_PRM_C0 Register Description ........................................................
4.4.7 MPU_PRCM_CM_C0 Registers .............................................................................
4.4.7.1
MPU_PRCM_CM_C0 Register Summary ...........................................................
4.4.7.2
MPU_PRCM_CM_C0 Register Description .........................................................
4.4.8 MPU_WUGEN Registers ......................................................................................
4.4.8.1
MPU_WUGEN Register Summary ....................................................................
4.4.8.2
MPU_WUGEN Register Description ..................................................................
4.4.9 MPU_WD_TIMER Registers ..................................................................................
4.4.9.1
MPU_WD_TIMER Register Summary ................................................................
4.4.9.2
MPU_WD_TIMER Register Description ..............................................................
4.4.10 MPU_AXI2OCP_MISC Registers ...........................................................................
4.4.10.1 MPU_AXI2OCP_MISC Register Summary ...........................................................
4.4.10.2 MPU_AXI2OCP_MISC Register Description .........................................................
4.4.11 MPU_MA_LSM Registers ....................................................................................
4.4.11.1 MPU_MA_LSM Register Summary ....................................................................
4.4.11.2 MPU_MA_LSM Register Description ..................................................................
4.4.12 MPU_MA_WP Registers .....................................................................................
4.4.12.1 MPU_MA_WP Register Summary ....................................................................
4.4.12.2 MPU_MA_WP Register Description ..................................................................
DSP Subsystem Overview .............................................................................................
5.1.1 DSP Subsystem Key Features ...............................................................................
DSP Subsystem Integration............................................................................................
DSP Subsystem Functional Description..............................................................................
5.3.1 DSP Subsystem Block Diagram ..............................................................................
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5.4
5.3.2 DSP Subsystem Components ................................................................................
5.3.2.1
C66x DSP Subsystem Introduction ....................................................................
5.3.2.2
DSP TMS320C66x CorePac ...........................................................................
5.3.2.2.1 DSP TMS320C66x CorePac CPU ................................................................
5.3.2.2.2 DSP TMS320C66x CorePac Internal Memory Controllers and Memories ..................
5.3.2.2.3 DSP C66x CorePac Internal Peripherals .........................................................
5.3.2.3
DSP Debug and Trace Support ........................................................................
5.3.2.3.1 DSP Advanced Event Triggering (AET) ..........................................................
5.3.2.3.2 DSP Trace Support .................................................................................
5.3.3 DSP System Control Logic ....................................................................................
5.3.3.1
DSP System Clocks .....................................................................................
5.3.3.2
DSP Hardware Resets ..................................................................................
5.3.3.3
DSP Software Resets ...................................................................................
5.3.3.4
DSP Power Management ...............................................................................
5.3.3.4.1 DSP System Powerdown Protocols ...............................................................
5.3.3.4.2 DSP Software and Hardware Power Down Sequence Overview .............................
5.3.3.4.3 DSP IDLE Wakeup ..................................................................................
5.3.3.4.4 DSP SYSTEM IRQWAKEEN registers ...........................................................
5.3.3.4.5 DSP Automatic Power Transition..................................................................
5.3.4 DSP Interrupt Requests .......................................................................................
5.3.4.1
DSP Input Interrupts .....................................................................................
5.3.4.1.1 DSP Non-maskable Interrupt Input................................................................
5.3.4.2
DSP Event and Interrupt Generation Outputs ........................................................
5.3.4.2.1 DSP MDMA and DSP EDMA Mflag Event Outputs ............................................
5.3.4.2.2 DSP Aggregated Error Interrupt Output ..........................................................
5.3.4.2.3 Non-DSP C66x CorePac Generated Peripheral Interrupt Outputs ...........................
5.3.5 DSP DMA Requests ...........................................................................................
5.3.5.1
DSP EDMA Wakeup Interrupt .........................................................................
5.3.6 DSP Intergated Memory Management Units ...............................................................
5.3.6.1
DSP MMUs Overview ...................................................................................
5.3.6.2
Routing MDMA Traffic through DSP MMU0 .........................................................
5.3.6.3
Routing EDMA Traffic thorugh DSP MMU1 .........................................................
5.3.7 DSP Integrated EDMA Subsystem ..........................................................................
5.3.7.1
DSP EDMA Overview ...................................................................................
5.3.7.2
DSP System and Device Level Settings of DSP EDMA ...........................................
5.3.8 DSP L2 interconnect Network ................................................................................
5.3.8.1
DSP Public Firewall Settings ...........................................................................
5.3.8.2
DSP NoC Flag Mux and Error Log Registers ........................................................
5.3.8.3
DSP NoC Arbitration .....................................................................................
5.3.9 DSP Boot Configuration .......................................................................................
5.3.10 DSP Internal and External Memory Views .................................................................
5.3.10.1 C66x CPU View of the Address Space ...............................................................
5.3.10.2 DSP_EDMA View of the Address Space .............................................................
5.3.10.3 L3_MAIN View of the DSP Address Space ..........................................................
DSP Subsystem Register Manual.....................................................................................
5.4.1 DSP Subsystem Instance Summary .........................................................................
5.4.2 DSP_ICFG Registers ..........................................................................................
5.4.2.1
DSP_ICFG Register Summary ........................................................................
5.4.2.2
DSP_ICFG Register Description ......................................................................
5.4.3 DSP_SYSTEM Registers .....................................................................................
5.4.3.1
DSP_SYSTEM Register Summary ...................................................................
5.4.3.2
DSP_SYSTEM Register Description .................................................................
5.4.4 DSP_FW_L2_NOC_CFG Registers .........................................................................
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Contents
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5.4.4.1
5.4.4.2
DSP_FW_L2_NOC_CFG Register Summary ....................................................... 1711
DSP_FW_L2_NOC_CFG Register Description ..................................................... 1714
6
IVA Subsystem ............................................................................................................... 1731
7
Dual Cortex-M4 IPU Subsystem ........................................................................................ 1732
7.1
7.2
7.3
7.4
16
Dual Cortex-M4 IPU Subsystem Overview ..........................................................................
7.1.1 Introduction ......................................................................................................
7.1.2 Features .........................................................................................................
Dual Cortex-M4 IPU Subsystem Integration .........................................................................
7.2.1 Dual Cortex-M4 IPU Subsystem Clock and Reset Distribution ..........................................
7.2.1.1
Clock Distribution ........................................................................................
7.2.1.2
Reset Distribution ........................................................................................
Dual Cortex-M4 IPU Subsystem Functional Description ...........................................................
7.3.1 IPUx Subsystem Block Diagram .............................................................................
7.3.2 Power Management............................................................................................
7.3.2.1
Local Power Management ..............................................................................
7.3.2.2
Power Domains ..........................................................................................
7.3.2.3
Voltage Domain ..........................................................................................
7.3.2.4
Power States and Modes ...............................................................................
7.3.2.5
Wake-Up Generator (IPUx_WUGEN) .................................................................
7.3.2.5.1 IPUx_WUGEN Main Features .....................................................................
7.3.3 IPUx_UNICACHE ..............................................................................................
7.3.4 IPUx_UNICACHE_MMU ......................................................................................
7.3.5 IPUx_UNICACHE_SCTM .....................................................................................
7.3.5.1
Counter Functions .......................................................................................
7.3.5.1.1 Input Events ..........................................................................................
7.3.5.1.2 Counters ..............................................................................................
7.3.5.2
Timer Functions ..........................................................................................
7.3.5.2.1 Periodic Intervals ....................................................................................
7.3.5.2.2 Event Generation ....................................................................................
7.3.6 IPUx_MMU ......................................................................................................
7.3.6.1
IPUx_MMU Behavior on Page-Fault in IPUx Subsystem ...........................................
7.3.7 Interprocessor Communication (IPC) ........................................................................
7.3.7.1
Use of WFE and SEV ...................................................................................
7.3.7.2
Use of Interrupt for IPC..................................................................................
7.3.7.3
Use of the Bit-Band Feature for Semaphore Operations ...........................................
7.3.7.4
Private Memory Space ..................................................................................
7.3.8 IPU Boot Options ...............................................................................................
Dual Cortex-M4 IPU Subsystem Register Manual ..................................................................
7.4.1 IPUx Subsystem Instance Summary ........................................................................
7.4.2 IPUx_UNICACHE_CFG Registers ...........................................................................
7.4.2.1
IPUx_UNICACHE_CFG Register Summary ..........................................................
7.4.2.2
IPUx_UNICACHE_CFG Register Description ........................................................
7.4.3 IPUx_UNICACHE_SCTM Registers .........................................................................
7.4.3.1
IPUx_UNICACHE_SCTM Register Summary ........................................................
7.4.3.2
IPUx_UNICACHE_SCTM Register Description ......................................................
7.4.4 IPUx_UNICACHE_MMU (AMMU) Registers ...............................................................
7.4.4.1
IPUx_UNICACHE_MMU (AMMU) Register Summary ..............................................
7.4.4.2
IPUx_UNICACHE_MMU (AMMU) Register Description ............................................
7.4.5 IPUx_MMU Registers ..........................................................................................
7.4.6 IPUx_Cx_INTC Registers .....................................................................................
7.4.7 IPUx_WUGEN Registers ......................................................................................
7.4.7.1
IPUx_WUGEN Register Summary.....................................................................
7.4.7.2
IPUx_WUGEN Register Description ...................................................................
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7.4.8 IPUx_Cx_RW_TABLE Registers ............................................................................. 1782
7.4.8.1
IPUx_Cx_RW_TABLE Register Summary............................................................ 1782
7.4.8.2
IPUx_Cx_RW_TABLE Register Description .......................................................... 1783
8
Camera Interface Subsystem ............................................................................................ 1784
8.1
8.2
8.3
8.4
8.5
CAMSS Overview .......................................................................................................
8.1.1 CAMSS Block Diagram ........................................................................................
8.1.2 CAMSS Features ...............................................................................................
CAMSS Environment ...................................................................................................
8.2.1 CAMSS Interfaces Signal Descriptions......................................................................
CAMSS Integration ......................................................................................................
8.3.1 CAMSS Main Integration Attributes ..........................................................................
8.3.2 CAL Integration - Video Port ..................................................................................
8.3.3 CAL Integration - PPI Interface ...............................................................................
CAMSS Functional Description ........................................................................................
8.4.1 CAMSS Hardware and Software Reset .....................................................................
8.4.2 CAMSS Clock Configuration ..................................................................................
8.4.3 CAMSS Power Management .................................................................................
8.4.4 CAMSS Interrupt Events ......................................................................................
8.4.5 CSI2 PHY Functional Description ............................................................................
8.4.5.1
CSI2 PHY Overview .....................................................................................
8.4.5.2
CSI2 PHY Configuration ................................................................................
8.4.5.3
CSI2 PHY Link Initialization Sequence................................................................
8.4.5.4
CSI2 PHY Error Signals .................................................................................
8.4.6 CAL Functional Description ...................................................................................
8.4.6.1
CAL Block Diagram ......................................................................................
8.4.6.2
CSI2 Low Level Protocol ................................................................................
8.4.6.2.1 CSI2 Physical Layer.................................................................................
8.4.6.2.2 CSI2 Multi-lane Layer and Lane Merger .........................................................
8.4.6.2.3 CSI2 Protocol Layer .................................................................................
8.4.6.2.4 CSI2 TAG Generation FSM ........................................................................
8.4.6.3
CAL Data Stream Merger ...............................................................................
8.4.6.4
CAL Pixel Extraction .....................................................................................
8.4.6.5
CAL DPCM Decoding and Encoding ..................................................................
8.4.6.6
CAL Stream Interleaving ................................................................................
8.4.6.7
CAL Pixel Packing .......................................................................................
8.4.6.8
CAL Write DMA ..........................................................................................
8.4.6.8.1 CAL Write DMA Overview ..........................................................................
8.4.6.8.2 CAL Write DMA Data Cropping....................................................................
8.4.6.8.3 CAL Write DMA Buffer Management .............................................................
8.4.6.8.4 CAL Write DMA OCP Address Generation ......................................................
8.4.6.8.5 CAL Write DMA OCP Transaction Generation ..................................................
8.4.6.8.6 CAL Write DMA Real Time Traffic ................................................................
8.4.6.9
CAL Video Port ...........................................................................................
8.4.6.9.1 CAL Video Port Overview ..........................................................................
8.4.6.9.2 CAL Video Port Pixel Clock Generation ..........................................................
8.4.6.9.3 CAL Video Port Video Timing Generator .........................................................
8.4.6.10 CAL Registers Shadowing ..............................................................................
CAMSS Register Manual ...............................................................................................
8.5.1 CAMSS Instance Summary ...................................................................................
8.5.2 CAL Registers ..................................................................................................
8.5.2.1
CAL Register Summary ................................................................................
8.5.2.2
CAL Register Description ..............................................................................
8.5.3 CSI2 PHY Registers ...........................................................................................
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8.5.3.1
8.5.3.2
9
Video Input Port .............................................................................................................. 1900
9.1
9.2
9.3
9.4
18
CSI2 PHY Register Summary .......................................................................... 1895
CSI2 PHY Register Description ........................................................................ 1896
VIP Overview ............................................................................................................
VIP Environment ........................................................................................................
VIP Integration ...........................................................................................................
VIP Functional Description ............................................................................................
9.4.1 VIP Block Diagram .............................................................................................
9.4.2 VIP Software Reset ............................................................................................
9.4.3 VIP Power and Clocks Management .......................................................................
9.4.3.1
VIP Clocks ................................................................................................
9.4.3.2
VIP Idle Mode ............................................................................................
9.4.3.3
VIP StandBy Mode.......................................................................................
9.4.4 VIP Slice .........................................................................................................
9.4.4.1
VIP Slice Processing Path Overview ..................................................................
9.4.4.2
VIP Slice Processing Path Multiplexers ...............................................................
9.4.4.2.1 VIP_CSC Multiplexers .............................................................................
9.4.4.2.2 VIP_SC Multiplexer..................................................................................
9.4.4.2.3 Output to VPDMA Multiplexers ....................................................................
9.4.4.3
VIP Slice Processing Path Examples .................................................................
9.4.4.3.1 Input: A=RGB, B=YUV422; Output: A=RGB, B=RGB ..........................................
9.4.4.3.2 Input: A=YUV422 8/16, B=YUV422; Output: A=Scaled YUV420, B=RGB ..................
9.4.4.3.3 Input: A=RGB, B=YUV422; Output: A=RGB, B=Scaled YUV420 .............................
9.4.4.3.4 Input: A=YUV444, B=YUV422; Output: A=YUV422, A=Scaled YUV422, B=YUV422 .....
9.4.4.3.5 Input: A=YUV444; Output: A=Scaled YUV420, A=YUV420 ...................................
9.4.4.3.6 Input: A=YUV444; Output: A=Scaled YUV420, A=YUV444 ...................................
9.4.4.3.7 Input: A=YUV422 8/16; Output: A=Scaled YUV420, A=YUV444 .............................
9.4.4.3.8 Input: A=YUV422 8/16, B=YUV422; Output: A=Scaled YUV420, B=YUV420 ..............
9.4.4.3.9 Input: A=YUV422 8/16, B=YUV422; Output: A=YUV420, B=YUV420 .......................
9.4.5 VIP Parser .......................................................................................................
9.4.5.1
Features ...................................................................................................
9.4.5.2
Repacker ..................................................................................................
9.4.5.3
Analog Video .............................................................................................
9.4.5.4
Digitized Video ...........................................................................................
9.4.5.5
Frame Buffers ............................................................................................
9.4.5.6
Input Data Interface ......................................................................................
9.4.5.6.1 8b Interface Mode ...................................................................................
9.4.5.6.2 16b Interface Mode ..................................................................................
9.4.5.6.3 24b Interface Mode ..................................................................................
9.4.5.6.4 Signal Relationships ................................................................................
9.4.5.6.5 General 5 Pin Interfaces ............................................................................
9.4.5.6.6 Signal Subsets—4 Pin VSYNC, ACTVID, and FID .............................................
9.4.5.6.7 Signal Subsets—4 Pin VSYNC, HSYNC, and FID ..............................................
9.4.5.6.8 Vertical Sync .........................................................................................
9.4.5.6.9 Field ID Determination Using Dedicated Signal .................................................
9.4.5.6.10 Field ID Determination Using VSYNC Skew .....................................................
9.4.5.6.11 Rationale for FID Determination By VSYNC Skew .............................................
9.4.5.6.12 ACTVID Framing ....................................................................................
9.4.5.6.13 Ancillary Data Storage in Descrete Sync Mode .................................................
9.4.5.7
BT.656 Style Embedded Sync .........................................................................
9.4.5.7.1 Data Input ............................................................................................
9.4.5.7.2 Sync Words ..........................................................................................
9.4.5.7.3 Error Correction ......................................................................................
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9.4.5.7.4 Embedded Sync Ancillary Data ....................................................................
9.4.5.7.5 Embedded Sync RGB 24-bit Data ................................................................
9.4.5.8
Source Multiplexing ......................................................................................
9.4.5.8.1 Multiplexing Scenarios ..............................................................................
9.4.5.8.2 2-Way Multiplexing ..................................................................................
9.4.5.8.3 4-Way Multiplexing ..................................................................................
9.4.5.8.4 Line Multiplexing .....................................................................................
9.4.5.8.5 Super Frame Concept in Line Multiplexing ......................................................
9.4.5.8.6 8-bit Data Interface in Line Multiplexing ..........................................................
9.4.5.8.7 16-bit Data Interface in Line Multiplexing.........................................................
9.4.5.8.8 Split Lines in Line Multiplex Mode .................................................................
9.4.5.8.9 Meta Data ............................................................................................
9.4.5.8.10 TI Line Mux Mode, Split Lines, and Channel ID Remapping ..................................
9.4.5.9
Channel ID Extraction for 2x/4x Multiplexed Source ................................................
9.4.5.9.1 Channel ID Extraction Overview...................................................................
9.4.5.9.2 Channel ID Embedded in Protection Bits for 2- and 4-Way Multiplexing ....................
9.4.5.9.3 Channel ID Embedded in Horizontal Blanking Pixel Data for 2- and 4-Way Multiplexing .
9.4.5.10 Embedded Sync Mux Modes and Data Bus Widths ................................................
9.4.5.11 Ancillary and Active Video Cropping ..................................................................
9.4.5.12 Interrupts ..................................................................................................
9.4.5.13 VDET Interrupt ...........................................................................................
9.4.5.14 Source Video Size .......................................................................................
9.4.5.15 Clipping ....................................................................................................
9.4.5.16 Current and Last FID Value ............................................................................
9.4.5.17 Disable Handling .........................................................................................
9.4.5.18 Picture Size Interrupt ....................................................................................
9.4.5.19 Discrete Sync Signals ...................................................................................
9.4.5.19.1 VBLNK and HBLNK .................................................................................
9.4.5.19.2 BLNK and ACTVID (1) ..............................................................................
9.4.5.19.3 VBLNK and ACTVID(2) .............................................................................
9.4.5.19.4 VBLNK and HSYNC ................................................................................
9.4.5.19.5 VSYNC and HBLNK ................................................................................
9.4.5.19.6 VSYNC and ACTIVID(1) ...........................................................................
9.4.5.19.7 VSYNC and ACTIVID(2) ...........................................................................
9.4.5.19.8 VSYNC and HSYNC ................................................................................
9.4.5.19.9 Line and Pixel Capture Examples .................................................................
9.4.5.20 VIP Overflow Detection and Recovery ................................................................
9.4.6 VIP Color Space Converter (CSC) ...........................................................................
9.4.6.1
CSC Features ............................................................................................
9.4.6.2
CSC Functional Description ............................................................................
9.4.6.2.1 HDTV Application ....................................................................................
9.4.6.2.2 SDTV Application ....................................................................................
9.4.6.3
CSC Bypass Mode.......................................................................................
9.4.7 VIP Scaler (SC) .................................................................................................
9.4.7.1
SC Features ..............................................................................................
9.4.7.2
SC Functional Description ..............................................................................
9.4.7.2.1 Trimmer ...............................................................................................
9.4.7.2.2 Peaking ...............................................................................................
9.4.7.2.3 Vertical Scaler........................................................................................
9.4.7.2.4 Horizontal Scaler ....................................................................................
9.4.7.2.5 Basic Configurations ................................................................................
9.4.7.2.6 Coefficient Memory ..................................................................................
9.4.7.3
SC Code ..................................................................................................
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9.4.7.3.1 Generate Coefficient Memory Image .............................................................
9.4.7.3.2 Scaler Configuration Calculation ..................................................................
9.4.7.3.3 Typical Configuration Values.......................................................................
9.4.7.4
SC Coefficient Data Files ...............................................................................
9.4.7.4.1 HS Polyphase Filter Coefficients ..................................................................
9.4.7.4.2 VS Polyphase Filter Coefficients ..................................................................
9.4.7.4.3 VS (Bilinear Filter Coefficients) ....................................................................
9.4.8 VIP Video Port Direct Memory Access (VPDMA) ..........................................................
9.4.8.1
VPDMA Introduction .....................................................................................
9.4.8.2
VPDMA Basic Definitions ...............................................................................
9.4.8.2.1 Client ..................................................................................................
9.4.8.2.2 Channel ...............................................................................................
9.4.8.2.3 List .....................................................................................................
9.4.8.2.4 Data Formats Supported ...........................................................................
9.4.8.3
VPDMA Client Buffering and Functionality ...........................................................
9.4.8.4
VPDMA Channels Assignment .........................................................................
9.4.8.5
VPDMA MFLAG Mechanism ...........................................................................
9.4.8.6
VPDMA Interrupts .......................................................................................
9.4.8.7
VPDMA Descriptors .....................................................................................
9.4.8.7.1 Data Transfer Descriptors ..........................................................................
9.4.8.7.2 Configuration Descriptor ............................................................................
9.4.8.7.3 Control Descriptor ...................................................................................
9.4.8.8
VPDMA Configuration ...................................................................................
9.4.8.8.1 Regular List...........................................................................................
9.4.8.8.2 Video Input Ports ....................................................................................
9.4.8.9
VPDMA Data Formats ...................................................................................
9.4.8.9.1 YUV Data Formats ..................................................................................
9.4.8.9.2 RGB Data Formats ..................................................................................
9.4.8.9.3 Miscellaneous Data Type...........................................................................
VIP Register Manual ....................................................................................................
9.5.1 VIP Instance Summary ........................................................................................
9.5.2 VIP Top Level Registers.......................................................................................
9.5.2.1
VIP Top Level Register Summary ....................................................................
9.5.2.2
VIP Top Level Register Description ..................................................................
9.5.3 VIP Parser Registers ..........................................................................................
9.5.3.1
VIP Parser Register Summary ........................................................................
9.5.3.2
VIP Parser Register Description .......................................................................
9.5.4 VIP CSC Registers .............................................................................................
9.5.4.1
VIP CSC Register Summary ...........................................................................
9.5.4.2
VIP CSC Register Description .........................................................................
9.5.5 VIP SC registers ................................................................................................
9.5.5.1
VIP SC Register Summary .............................................................................
9.5.5.2
VIP SC Register Description ...........................................................................
9.5.6 VIP VPDMA Registers .........................................................................................
9.5.6.1
VIP VPDMA Register Summary .......................................................................
9.5.6.2
VIP VPDMA Register Description .....................................................................
VPE Overview ...........................................................................................................
VPE Integration ..........................................................................................................
VPE Functional Description ............................................................................................
10.3.1 VPE Block Diagram ...........................................................................................
10.3.2 VPE VC1 Range Mapping/Range Reduction ..............................................................
10.3.3 VPE Deinterlacer (DEI) .......................................................................................
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10.3.3.1 Functional Description ...................................................................................
10.3.3.2 Bypass Mode .............................................................................................
10.3.3.2.1 VPDMA Interface ....................................................................................
10.3.3.2.2 MDT ..................................................................................................
10.3.3.2.3 EDI ....................................................................................................
10.3.3.2.4 FMD ..................................................................................................
10.3.3.2.5 MUX ...................................................................................................
10.3.3.2.6 LINE BUFFER .......................................................................................
10.3.4 VPE Scaler (SC) ..............................................................................................
10.3.4.1 SC Features ..............................................................................................
10.3.4.2 SC Functional Description ..............................................................................
10.3.4.2.1 Trimmer ...............................................................................................
10.3.4.2.2 Peaking ...............................................................................................
10.3.4.2.3 Vertical Scaler .......................................................................................
10.3.4.2.4 Horizontal Scaler ....................................................................................
10.3.4.2.5 Basic Configurations ................................................................................
10.3.4.2.6 Coefficient Memory..................................................................................
10.3.4.3 SC Code ..................................................................................................
10.3.4.3.1 Generate Coefficient Memory Image .............................................................
10.3.4.3.2 Scaler Configuration Calculation ..................................................................
10.3.4.3.3 Typical Configuration Values ......................................................................
10.3.4.4 SC Coefficient Data Files ...............................................................................
10.3.4.4.1 HS Polyphase Filter Coefficients ..................................................................
10.3.4.4.2 VS Polyphase Filter Coefficients ..................................................................
10.3.4.4.3 VS (Bilinear Filter Coefficients) ....................................................................
10.3.5 VPE Color Space Converter (CSC) .........................................................................
10.3.5.1 CSC Features ............................................................................................
10.3.5.2 CSC Functional Description ............................................................................
10.3.5.2.1 HDTV Application ...................................................................................
10.3.5.2.2 SDTV Application ....................................................................................
10.3.5.3 CSC Bypass Mode.......................................................................................
10.3.6 VPE Chroma Up-Sampler (CHR_US) ......................................................................
10.3.6.1 Features ...................................................................................................
10.3.6.2 Functional Description ...................................................................................
10.3.6.3 For Interlaced YUV420 Input Data .....................................................................
10.3.6.4 Edge Effects ..............................................................................................
10.3.6.5 Modes of Operation (VPDMA) .........................................................................
10.3.6.6 Coefficient Configuration ................................................................................
10.3.7 VPE Chroma Down-Sampler (CHR_DS)...................................................................
10.3.8 VPE YUV422 to YUV444 Conversion ......................................................................
10.3.9 VPE Video Port Direct Memory Access (VPDMA) ........................................................
10.3.9.1 VPDMA Introduction .....................................................................................
10.3.9.2 VPDMA Basic Definitions ...............................................................................
10.3.9.2.1 Client ..................................................................................................
10.3.9.2.2 Channel ...............................................................................................
10.3.9.2.3 List .....................................................................................................
10.3.9.2.4 Data Formats Supported ...........................................................................
10.3.9.3 VPDMA Client Buffering and Functionality ...........................................................
10.3.9.4 VPDMA Channels Assignment .........................................................................
10.3.9.5 VPDMA Interrupts .......................................................................................
10.3.9.6 VPDMA Descriptors .....................................................................................
10.3.9.6.1 Data Transfer Descriptors ..........................................................................
10.3.9.6.2 Configuration Descriptor ............................................................................
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Display Subsystem.......................................................................................................... 2617
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10.3.9.6.3 Control Descriptor ...................................................................................
10.3.9.7 VPDMA Configuration ...................................................................................
10.3.9.7.1 Regular List ..........................................................................................
10.3.9.7.2 Video Input Ports ....................................................................................
10.3.9.8 VPDMA Data Formats ...................................................................................
10.3.9.8.1 YUV Data Formats ..................................................................................
10.3.9.8.2 RGB Data Formats ..................................................................................
10.3.9.8.3 Miscellaneous Data Type ..........................................................................
10.3.10 VPE Software Reset ........................................................................................
10.3.11 VPE Power and Clocks Management ....................................................................
10.3.11.1 VPE Clocks ..............................................................................................
10.3.11.2 VPE Idle Mode ..........................................................................................
10.3.11.3 VPE StandBy Mode ....................................................................................
VPE Register Manual ...................................................................................................
10.4.1 VPE Instance Summary ......................................................................................
10.4.2 VPE_CSC Registers ..........................................................................................
10.4.2.1 VPE_CSC Register Summary .........................................................................
10.4.2.2 VPE_CSC Register Description .......................................................................
10.4.3 VPE_SC Registers ............................................................................................
10.4.3.1 VPE_SC Register Summary ...........................................................................
10.4.3.2 VPE_SC Register Description .........................................................................
10.4.4 VPE_CHR_US Registers.....................................................................................
10.4.4.1 VPE_CHR_US Register Summary ...................................................................
10.4.4.2 VPE_CHR_US Register Description ..................................................................
10.4.5 VPE_DEI Registers ...........................................................................................
10.4.5.1 VPE_DEI Register Summary ..........................................................................
10.4.5.2 VPE_DEI Register Description ........................................................................
10.4.6 VPE_VPDMA Registers ......................................................................................
10.4.6.1 VPE_VPDMA Register Summary .....................................................................
10.4.6.2 VPE_VPDMA Register Description ...................................................................
10.4.7 VPE_TOP_LEVEL Registers ................................................................................
10.4.7.1 VPE_TOP_LEVEL Register Summary ...............................................................
10.4.7.2 VPE_TOP_LEVEL Register Description .............................................................
Display Subsystem Overview ..........................................................................................
11.1.1 Display Subsystem Environment ............................................................................
11.1.1.1 Display Subsystem LCD Support ......................................................................
11.1.1.1.1 Display Subsystem LCD with Parallel Interfaces................................................
11.1.1.2 Display Subsystem TV Display Support ..............................................................
11.1.1.2.1 Display Subsystem TV With Parallel Interfaces .................................................
11.1.1.2.2 Display Subsystem TV With Serial Interfaces ...................................................
11.1.2 Display Subsystem Integration ..............................................................................
11.1.2.1 Display Subsystem Clocks..............................................................................
11.1.2.2 Display Subsystem Resets .............................................................................
11.1.2.3 Display Subsystem Power Management .............................................................
11.1.2.3.1 Display Subsystem Standby Mode................................................................
11.1.2.3.2 Display Subsystem Wake-Up Mode ..............................................................
11.1.3 Display Subsystem DPLL Controllers Functional Description ...........................................
11.1.3.1 DPLL Controllers Overview .............................................................................
11.1.3.2 OCP2SCP2 Functional Description....................................................................
11.1.3.2.1 OCP2SCP2 Reset...................................................................................
11.1.3.2.2 OCP2SCP2 Power Management .................................................................
11.1.3.2.3 OCP2SCP2 Timing Registers .....................................................................
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11.2
11.1.3.3 DPLL_VIDEO Functional Description .................................................................
11.1.3.3.1 DPLL_VIDEO Controller Architecture ............................................................
11.1.3.3.2 DPLL_VIDEO Operations ..........................................................................
11.1.3.3.3 DPLL_VIDEO Error Handling ......................................................................
11.1.3.3.4 DPLL_VIDEO Software Reset .....................................................................
11.1.3.3.5 DPLL_VIDEO Power Management ...............................................................
11.1.3.3.6 DPLL_VIDEO HSDIVIDER Loading Operation ..................................................
11.1.3.3.7 DPLL_VIDEO Clock Sequence ....................................................................
11.1.3.3.8 DPLL_VIDEO Go Sequence .......................................................................
11.1.3.3.9 DPLL_VIDEO Recommended Values ............................................................
11.1.3.4 DPLL_HDMI Functional Description ...................................................................
11.1.3.4.1 DPLL_HDMI and PLLCTRL_HDMI Overview ..................................................
11.1.3.4.2 DPLL_HDMI and PLLCTRL_HDMI Architecture ................................................
11.1.3.4.3 DPLL_HDMI Operations ............................................................................
11.1.3.4.4 DPLL_HDMI Register Access .....................................................................
11.1.3.4.5 DPLL_HDMI Error Handling .......................................................................
11.1.3.4.6 DPLL_HDMI Software Reset ......................................................................
11.1.3.4.7 DPLL_HDMI Power Management .................................................................
11.1.3.4.8 DPLL_HDMI Lock Sequence ......................................................................
11.1.3.4.9 DPLL_HDMI Go Sequence ........................................................................
11.1.3.4.10 DPLL_HDMI Recommended Values ............................................................
11.1.4 Display Subsystem Programming Guide ...................................................................
11.1.5 Display Subsystem Register Manual .......................................................................
11.1.5.1 Display Subsystem Instance Summary ...............................................................
11.1.5.2 Display Subsystem Registers ..........................................................................
11.1.5.2.1 Display Subsystem Registers Mapping Summary ..............................................
11.1.5.2.2 Display Subsystem Register Description .........................................................
11.1.5.3 OCP2SCP2 registers ....................................................................................
11.1.5.3.1 OCP2SCP2 Register Summary ..................................................................
11.1.5.3.2 OCP2SCP Register Description .................................................................
11.1.5.4 DPLL_VIDEO Registers .................................................................................
11.1.5.4.1 DPLL_VIDEO Register Summary .................................................................
11.1.5.4.2 DPLL_VIDEO Register Description ...............................................................
11.1.5.5 DPLL_HDMI Registers ..................................................................................
11.1.5.5.1 DPLL_HDMI Registers Mapping Summary ......................................................
11.1.5.5.2 DPLL_HDMI Register Description ................................................................
11.1.5.6 HDMI_WP Registers.....................................................................................
11.1.5.6.1 HDMI_WP Registers Mapping Summary ........................................................
11.1.5.6.2 HDMI_WP Register Description ...................................................................
11.1.5.7 DSI Registers .............................................................................................
11.1.5.7.1 DSI Register Summary .............................................................................
11.1.5.7.2 DSI Register Description ...........................................................................
Display Controller .......................................................................................................
11.2.1 DISPC Overview ..............................................................................................
11.2.2 DISPC Environment ..........................................................................................
11.2.2.1 DISPC LCD Output and Data Format for the Parallel Interface ...................................
11.2.2.2 DISPC Transaction Timing Diagrams .................................................................
11.2.2.3 DISPC TV Output and Data Format for the Parallel Interface .....................................
11.2.3 DISPC Integration .............................................................................................
11.2.4 DISPC Functional Description ...............................................................................
11.2.4.1 DISPC Clock Configuration .............................................................................
11.2.4.2 DISPC Software Reset ..................................................................................
11.2.4.3 DISPC Power Management ............................................................................
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11.2.4.3.1 DISPC Idle Mode ....................................................................................
11.2.4.3.2 DISPC StandBy Mode ..............................................................................
11.2.4.3.3 DISPC Wakeup ......................................................................................
11.2.4.4 DISPC Interrupt Requests ..............................................................................
11.2.4.5 DISPC DMA Requests ..................................................................................
11.2.4.6 DISPC DMA Engine .....................................................................................
11.2.4.6.1 DISPC Addressing and Bursts ....................................................................
11.2.4.6.2 DISPC Immediate Base Address Flip Mechanism ..............................................
11.2.4.6.3 DISPC DMA Buffers ................................................................................
11.2.4.6.4 DISPC MFLAG Mechanism and Arbitration .....................................................
11.2.4.6.5 DISPC Predecimation...............................................................................
11.2.4.6.6 DISPC Progressive-to-Interlaced Format Conversion ..........................................
11.2.4.6.7 DISPC Arbitration ...................................................................................
11.2.4.6.8 DISPC DMA Power Modes ........................................................................
11.2.4.7 DISPC Rotation and Mirroring ..........................................................................
11.2.4.8 DISPC Memory Format .................................................................................
11.2.4.9 DISPC Graphics Pipeline ...............................................................................
11.2.4.9.1 DISPC Replication Logic ...........................................................................
11.2.4.9.2 DISPC Antiflicker Filter .............................................................................
11.2.4.10 DISPC Video Pipelines.................................................................................
11.2.4.10.1 DISPC Replication Logic ..........................................................................
11.2.4.10.2 DISPC VC-1 Range Mapping Unit...............................................................
11.2.4.10.3 DISPC CSC Unit YUV to RGB ...................................................................
11.2.4.10.4 DISPC Scaler Unit .................................................................................
11.2.4.11 DISPC Write-Back Pipeline ............................................................................
11.2.4.11.1 DISPC Write-Back CSC Unit RGB to YUV .....................................................
11.2.4.11.2 DISPC Write-Back Scaler Unit ...................................................................
11.2.4.11.3 DISPC Write-Back RGB Truncation Logic......................................................
11.2.4.12 DISPC Hardware Cursor ...............................................................................
11.2.4.13 DISPC LCD Outputs....................................................................................
11.2.4.13.1 DISPC Overlay Manager .........................................................................
11.2.4.13.2 DISPC Gamma Correction Unit ..................................................................
11.2.4.13.3 DISPC Color Phase Rotation Unit ...............................................................
11.2.4.13.4 DISPC Color Space Conversion .................................................................
11.2.4.13.5 DISPC BT.656 and BT.1120 Modes ............................................................
11.2.4.13.6 DISPC Active Matrix ...............................................................................
11.2.4.13.7 DISPC Synchronized Buffer Update ............................................................
11.2.4.13.8 DISPC Timing Generator and Panel Settings ..................................................
11.2.4.14 DISPC TV Output .......................................................................................
11.2.4.14.1 DISPC Overlay Manager .........................................................................
11.2.4.14.2 DISPC Gamma Correction Unit ..................................................................
11.2.4.14.3 DISPC Synchronized Buffer Update ............................................................
11.2.4.14.4 DISPC Timing and TV Format Settings .........................................................
11.2.4.15 DISPC Frame Width Considerations .................................................................
11.2.4.16 DISPC Extended 3D Support .........................................................................
11.2.4.16.1 DISPC Extended 3D Support - Line Alternative Format ......................................
11.2.4.16.2 DISPC Extended 3D Support - Frame Packing Format Format .............................
11.2.4.16.3 DISPC Extended 3D Support - DLP 3D Format ..............................................
11.2.4.17 DISPC Shadow Registers .............................................................................
11.2.5 DISPC Programming Guide .................................................................................
11.2.5.1 DISPC Low-Level Programming Models ..............................................................
11.2.5.1.1 DISPC Global Initialization .........................................................................
11.2.5.1.2 DISPC Operational Modes Configuration ........................................................
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11.3
12
12.2
12.3
12.4
GPU Overview ...........................................................................................................
12.1.1 GPU Features Overview .....................................................................................
12.1.2 Graphics Feature Overview ..................................................................................
GPU Integration .........................................................................................................
GPU Functional Description ...........................................................................................
12.3.1 GPU Block Diagram ..........................................................................................
12.3.2 GPU Clock Configuration ....................................................................................
12.3.3 GPU Software Reset..........................................................................................
12.3.4 GPU Power Management ....................................................................................
12.3.5 GPU Thermal Management ..................................................................................
12.3.6 GPU Interrupt Requests ......................................................................................
GPU Register Manual ..................................................................................................
12.4.1 GPU Instance Summary .....................................................................................
12.4.2 GPU Registers .................................................................................................
12.4.2.1 GPU_WRAPPER Register Summary .................................................................
12.4.2.2 GPU_WRAPPER Register Description ...............................................................
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2D Graphics Accelerator .................................................................................................. 2983
13.1
13.2
13.3
13.4
14
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2795
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3D Graphics Accelerator .................................................................................................. 2959
12.1
13
11.2.6 DISPC Register Manual ......................................................................................
11.2.6.1 DISPC Instance Summary ..............................................................................
11.2.6.2 DISPC Logical Register Mapping ......................................................................
11.2.6.3 DISPC Registers .........................................................................................
11.2.6.3.1 DISPC Register Summary .........................................................................
11.2.6.3.2 DISPC Register Description .......................................................................
High-Definition Multimedia Interface ..................................................................................
11.3.1 HDMI Overview ................................................................................................
11.3.1.1 HDMI Main Features ....................................................................................
11.3.1.2 HDMI Video Formats and Timings .....................................................................
11.3.1.2.1 HDMI CEA-861-D Video Formats and Timings .................................................
11.3.1.2.2 VESA DMT Video Formats and Timings .........................................................
BB2D Overview ..........................................................................................................
13.1.1 BB2D Key Features Overview ...............................................................................
BB2D Integration ........................................................................................................
BB2D Functional Description ..........................................................................................
13.3.1 BB2D Block Diagram .........................................................................................
13.3.2 BB2D Clock Configuration ...................................................................................
13.3.3 BB2D Software Reset ........................................................................................
13.3.4 BB2D Power Management ...................................................................................
BB2D Register Manual .................................................................................................
13.4.1 BB2D Instance Summary ....................................................................................
13.4.2 BB2D Registers ...............................................................................................
13.4.2.1 BB2D Register Summary ...............................................................................
13.4.2.2 BB2D Register Description ............................................................................
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Interconnect ................................................................................................................... 3032
14.1
14.2
Interconnect Overview ..................................................................................................
14.1.1 Terminology ....................................................................................................
14.1.2 Architecture Overview ........................................................................................
L3_MAIN Interconnect ..................................................................................................
14.2.1 L3_MAIN Interconnect Overview ............................................................................
14.2.2 L3_MAIN Interconnect Integration ..........................................................................
14.2.3 L3_MAIN Interconnect Functional Description ............................................................
14.2.3.1 Module Use in L3_MAIN Interconnect ................................................................
14.2.3.2 Module Distribution ......................................................................................
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14.3
26
14.2.3.2.1 L3_MAIN Interconnect Agents .....................................................................
14.2.3.2.2 L3_MAIN Connectivity Matrix ......................................................................
14.2.3.2.3 Master NIU Identification ...........................................................................
14.2.3.3 Bandwidth Regulators ...................................................................................
14.2.3.4 Bandwidth Limiters .......................................................................................
14.2.3.5 Flag Muxing ...............................................................................................
14.2.3.5.1 Flag Mux Time-out ..................................................................................
14.2.3.6 Statistic Collectors Group ...............................................................................
14.2.3.7 L3_MAIN Protection and Firewalls.....................................................................
14.2.3.7.1 L3_MAIN Firewall Reset ............................................................................
14.2.3.7.2 Power Management .................................................................................
14.2.3.7.3 L3_MAIN Firewall Functionality ...................................................................
14.2.3.8 L3_MAIN Interconnect Error Handling ................................................................
14.2.3.8.1 Global Error-Routing Scheme .....................................................................
14.2.3.8.2 Slave NIU Error Logging ...........................................................................
14.2.3.8.3 Flag Mux Error Logging ............................................................................
14.2.3.8.4 Severity Level of Standard and Custom Errors .................................................
14.2.3.8.5 Example for Decoding Standard/Custom Errors Logged in L3_MAIN .......................
14.2.4 L3_MAIN Interconnect Programming Guide ...............................................................
14.2.4.1 L3 _MAIN Interconnect Low-Level Programming Models ..........................................
14.2.4.1.1 Global Initialization ..................................................................................
14.2.4.2 Operational Modes Configuration ......................................................................
14.2.4.2.1 L3_MAIN Interconnect Error Analysis Mode .....................................................
14.2.5 L3_MAIN Interconnect Register Manual ...................................................................
14.2.5.1 L3_MAIN Register Group Summary ...................................................................
14.2.5.1.1 L3_MAIN Firewall Registers Summary and Description .......................................
14.2.5.1.2 L3_MAIN Host Register Summary and Description ............................................
14.2.5.1.3 L3_MAIN TARG Register Summary and Description ..........................................
14.2.5.1.4 L3_MAIN FLAGMUX Registers Summary and Description....................................
14.2.5.1.5 L3_MAIN FLAGMUX CLK1MERGE Registers Summary and Description ..................
14.2.5.1.6 L3_MAIN FLAGMUX TIMEOUT Registers Summary and Description.......................
14.2.5.1.7 L3_MAIN BW Regulator Register Summary and Description .................................
14.2.5.1.8 L3_MAIN Bandwidth Limiter Register Summary and Description ............................
14.2.5.1.9 L3_MAIN STATCOLL Register Summary and Description ....................................
L4 Interconnects .........................................................................................................
14.3.1 L4 Interconnect Overview ....................................................................................
14.3.2 L4 Interconnect Integration ..................................................................................
14.3.3 L4 Interconnect Functional Description ....................................................................
14.3.3.1 Module Distribution ......................................................................................
14.3.3.1.1 L4_PER1 Interconnect Agents ....................................................................
14.3.3.1.2 L4_PER2 Interconnect Agents ....................................................................
14.3.3.1.3 L4_PER3 Interconnect Agents ....................................................................
14.3.3.1.4 L4_CFG Interconnect Agents ......................................................................
14.3.3.1.5 L4_WKUP Interconnect Agents ...................................................................
14.3.3.2 Power Management .....................................................................................
14.3.3.3 L4 Firewalls ...............................................................................................
14.3.3.3.1 Protection Group ....................................................................................
14.3.3.3.2 Segments and Regions .............................................................................
14.3.3.3.3 L4 Firewall Address and Protection Register Settings .........................................
14.3.3.4 L4 Error Detection and Reporting ......................................................................
14.3.3.4.1 IA and TA Error Detection and Logging ..........................................................
14.3.3.4.2 Time-Out..............................................................................................
14.3.3.4.3 Error Reporting ......................................................................................
Contents
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3046
3047
3048
3049
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3052
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3054
3065
3065
3066
3067
3069
3069
3069
3069
3069
3070
3070
3073
3073
3073
3085
3098
3121
3125
3129
3137
3145
3153
3208
3208
3210
3211
3211
3211
3212
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3222
3229
3230
3230
3231
3232
SPRUIC2D – January 2017 – Revised April 2019
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14.3.3.4.4 Error Recovery .......................................................................................
14.3.3.4.5 Firewall Error Logging in the Control Module ....................................................
14.3.4 L4 Interconnect Programming Guide .......................................................................
14.3.4.1 L4 Interconnect Low-level Programming Models ....................................................
14.3.4.1.1 Global Initialization ..................................................................................
14.3.4.1.2 Operational Modes Configuration .................................................................
14.3.5 L4 Interconnects Register Manual ..........................................................................
14.3.5.1 L4 Interconnects Instance Summary ..................................................................
14.3.5.2 L4 Initiator Agent (L4 IA) ................................................................................
14.3.5.2.1 L4 Initiator Agent (L4 IA) Register Summary ....................................................
14.3.5.2.2 L4 Initiator Agent (L4 IA) Register Description ..................................................
14.3.5.3 L4 Target Agent (L4 TA) ................................................................................
14.3.5.3.1 L4 Target Agent (L4 TA) Register Summary ....................................................
14.3.5.3.2 L4 Target Agent (L4 TA) Register Description ..................................................
14.3.5.4 L4 Link Agent (L4 LA) ...................................................................................
14.3.5.4.1 L4 Link Agent (L4 LA) Register Summary .......................................................
14.3.5.4.2 L4 Link Agent (L4 LA) Register Description .....................................................
14.3.5.5 L4 Address Protection (L4 AP) .........................................................................
14.3.5.5.1 L4 Address Protection (L4 AP) Register Summary .............................................
14.3.5.5.2 L4 Address Protection (L4 AP) Register Description ...........................................
15
3233
3234
3235
3235
3235
3235
3239
3239
3242
3242
3244
3252
3252
3270
3274
3274
3275
3282
3282
3284
Memory Subsystem ......................................................................................................... 3300
15.1
15.2
Memory Subsystem Overview .........................................................................................
15.1.1 DMM Overview ................................................................................................
15.1.2 TILER Overview ...............................................................................................
15.1.3 EMIF Overview ................................................................................................
15.1.4 GPMC Overview...............................................................................................
15.1.5 ELM Overview .................................................................................................
15.1.6 OCM Overview ................................................................................................
Dynamic Memory Manager ............................................................................................
15.2.1 DMM Overview ................................................................................................
15.2.2 DMM Integration ...............................................................................................
15.2.2.1 DMM Configuration ......................................................................................
15.2.3 DMM Functional Description .................................................................................
15.2.3.1 DMM Block Diagram .....................................................................................
15.2.3.2 DMM Clock Configuration ...............................................................................
15.2.3.3 DMM Power Management ..............................................................................
15.2.3.4 DMM Interrupt Requests ................................................................................
15.2.3.5 DMM .......................................................................................................
15.2.3.5.1 DMM Concepts ......................................................................................
15.2.3.5.2 DMM Transaction Flows ............................................................................
15.2.3.5.3 DMM Internal Macro-Architecture .................................................................
15.2.3.6 TILER ......................................................................................................
15.2.3.6.1 TILER Concepts .....................................................................................
15.2.3.6.2 TILER Macro-Architecture..........................................................................
15.2.3.6.3 TILER Guidelines for Initiators .....................................................................
15.2.4 DMM Use Cases and Tips ...................................................................................
15.2.4.1 PAT Use Cases ..........................................................................................
15.2.4.1.1 Simple Manual Area Refill..........................................................................
15.2.4.1.2 Single Auto-Configured Area Refill................................................................
15.2.4.1.3 Chained Auto-Configured Area Refill .............................................................
15.2.4.1.4 Synchronized Auto-Configured Area Refill .......................................................
15.2.4.1.5 Cyclic Synchronized Auto-Configured Area Refill ...............................................
15.2.4.2 Addressing Management with LISA ...................................................................
SPRUIC2D – January 2017 – Revised April 2019
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Contents
3301
3301
3302
3302
3303
3304
3304
3306
3306
3306
3308
3309
3309
3310
3310
3311
3313
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3317
3318
3321
3321
3339
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3344
3344
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3344
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15.3
28
15.2.4.2.1 Case 1: Use of One Memory Controller ..........................................................
15.2.5 DMM Basic Programming Model ............................................................................
15.2.5.1 Global Initialization .......................................................................................
15.2.5.2 DMM Module Global Initialization ......................................................................
15.2.5.3 DMM Operational Modes Configuration...............................................................
15.2.5.3.1 Different Operational Modes .......................................................................
15.2.5.3.2 Configuration Settings and LUT Refill ............................................................
15.2.5.3.3 LISA Settings ........................................................................................
15.2.5.3.4 Aliased Tiled View Orientation Settings and LUT Refill ........................................
15.2.5.3.5 Priority Settings ......................................................................................
15.2.5.3.6 Error Handling .......................................................................................
15.2.5.3.7 PAT Programming Model ..........................................................................
15.2.5.4 Addressing an Object in Tiled Mode ..................................................................
15.2.5.4.1 Frame-Buffer Addressing ...........................................................................
15.2.5.4.2 TILER Page Mapping ...............................................................................
15.2.5.5 Addressing an Object in Page Mode ..................................................................
15.2.5.6 Sharing Containers Between Different Modes .......................................................
15.2.6 DMM Register Manual ........................................................................................
15.2.6.1 DMM Instance Summary ................................................................................
15.2.6.2 DMM Registers ...........................................................................................
15.2.6.2.1 DMM Register Summary ...........................................................................
15.2.6.2.2 DMM Register Description .........................................................................
EMIF Controller ..........................................................................................................
15.3.1 EMIF Controller Overview ....................................................................................
15.3.2 EMIF Module Environment ...................................................................................
15.3.3 EMIF Module Integration .....................................................................................
15.3.4 EMIF Functional Description .................................................................................
15.3.4.1 Block Diagram ............................................................................................
15.3.4.1.1 Local Interface .......................................................................................
15.3.4.1.2 FIFO Description ....................................................................................
15.3.4.1.3 MPU Port Restrictions ..............................................................................
15.3.4.1.4 Arbitration of Commands in the Command FIFO ..............................................
15.3.4.2 Clock Management ......................................................................................
15.3.4.2.1 EMIF_FICLK Overview .............................................................................
15.3.4.2.2 EMIF Dependency on MPU Clock Rate ..........................................................
15.3.4.3 Reset ......................................................................................................
15.3.4.4 System Power Management ...........................................................................
15.3.4.4.1 Power-Down Mode ..................................................................................
15.3.4.4.2 Self-Refresh Mode ..................................................................................
15.3.4.5 Interrupt Requests .......................................................................................
15.3.4.6 SDRAM Refresh Scheduling ...........................................................................
15.3.4.7 SDRAM Initialization .....................................................................................
15.3.4.7.1 DDR3/DDR3L SDRAM Initialization ..............................................................
15.3.4.8 DDR3/DDR3L Read-Write Leveling ...................................................................
15.3.4.8.1 Full Leveling ..........................................................................................
15.3.4.8.2 Software Leveling ...................................................................................
15.3.4.9 EMIF Access Cycles .....................................................................................
15.3.4.10 Turnaround Time .......................................................................................
15.3.4.11 PHY DLL Calibration ...................................................................................
15.3.4.12 SDRAM Address Mapping .............................................................................
15.3.4.12.1 Address Mapping for IBANK_POS = 0 and EBANK_POS = 0 ..............................
15.3.4.12.2 Address Mapping for IBANK_POS = 1 and EBANK_POS = 0 ..............................
15.3.4.12.3 Address Mapping for IBANK_POS = 2 and EBANK_POS = 0 ..............................
Contents
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3349
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3355
3356
3356
3356
3356
3357
3395
3395
3395
3400
3403
3403
3403
3404
3405
3405
3407
3407
3407
3407
3408
3408
3408
3409
3410
3410
3411
3412
3413
3413
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3416
3417
3417
SPRUIC2D – January 2017 – Revised April 2019
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15.4
15.3.4.12.4 Address Mapping for IBANK_POS = 3 and EBANK_POS = 0 .............................. 3417
15.3.4.12.5 Address Mapping for IBANK_POS = 0 and EBANK_POS = 1 .............................. 3418
15.3.4.12.6 Address Mapping for IBANK_POS = 1 and EBANK_POS = 1 .............................. 3418
15.3.4.12.7 Address Mapping for IBANK_POS = 2 and EBANK_POS = 1 .............................. 3419
15.3.4.12.8 Address Mapping for IBANK_POS = 3 and EBANK_POS = 1 .............................. 3419
15.3.4.13 DDR3/DDR3L Output Impedance Calibration....................................................... 3420
15.3.4.14 Error Correction And Detection Feature ............................................................. 3421
15.3.4.15 Class of Service ......................................................................................... 3422
15.3.4.16 Performance Counters ................................................................................ 3423
15.3.4.16.1 Performance Counters General Examples ..................................................... 3423
15.3.4.17 Forcing CKE to tri-state ................................................................................ 3424
15.3.5 EMIF Programming Guide ................................................................................... 3426
15.3.5.1 EMIF Low-Level Programming Models ............................................................... 3426
15.3.5.1.1 Global Initialization .................................................................................. 3426
15.3.5.1.2 Operational Modes Configuration ................................................................. 3432
15.3.6 EMIF Register Manual ........................................................................................ 3435
15.3.6.1 EMIF Instance Summary ................................................................................ 3435
15.3.6.2 EMIF Registers ........................................................................................... 3435
15.3.6.2.1 EMIF Register Summary ........................................................................... 3435
15.3.6.2.2 EMIF Register Description ......................................................................... 3439
General-Purpose Memory Controller ................................................................................. 3539
15.4.1 GPMC Overview............................................................................................... 3539
15.4.2 GPMC Environment ........................................................................................... 3539
15.4.2.1 GPMC Modes ............................................................................................ 3539
15.4.2.2 GPMC Signals ............................................................................................ 3542
15.4.3 GPMC Integration ............................................................................................. 3543
15.4.4 GPMC Functional Description ............................................................................... 3547
15.4.4.1 GPMC Block Diagram ................................................................................... 3547
15.4.4.2 GPMC Clock Configuration ............................................................................. 3548
15.4.4.3 GPMC Software Reset .................................................................................. 3549
15.4.4.4 GPMC Power Management ............................................................................ 3549
15.4.4.5 GPMC Interrupt Requests .............................................................................. 3550
15.4.4.6 L3 Interconnect Interface................................................................................ 3550
15.4.4.7 GPMC Address and Data Bus ......................................................................... 3550
15.4.4.7.1 GPMC I/O Configuration Setting .................................................................. 3551
15.4.4.7.2 GPMC CS0 Default Configuration at Device Reset ............................................ 3551
15.4.4.8 Address Decoder and Chip-Select Configuration .................................................... 3553
15.4.4.8.1 Chip-Select Base Address and Region Size .................................................... 3553
15.4.4.8.2 Access Protocol ..................................................................................... 3554
15.4.4.8.3 External Signals ..................................................................................... 3555
15.4.4.8.4 Error Handling ....................................................................................... 3564
15.4.4.9 Timing Setting ............................................................................................ 3564
15.4.4.9.1 Read Cycle Time and Write Cycle Time (RDCYCLETIME / WRCYCLETIME) ............. 3565
15.4.4.9.2 nCS: Chip-Select Signal Control Assertion/Deassertion Time (CSONTIME / CSRDOFFTIME /
CSWROFFTIME / CSEXTRADELAY) ............................................................ 3565
15.4.4.9.3 nADV/ALE: Address Valid/Address Latch Enable Signal Control Assertion/Deassertion Time
(ADVONTIME / ADVRDOFFTIME / ADVWROFFTIME /
ADVEXTRADELAY/ADVAADMUXONTIME/ADVAADMUXRDOFFTIME/ADVAADMUXWROFF
TIME) .................................................................................................. 3565
15.4.4.9.4 nOE/nRE: Output Enable/Read Enable Signal Control Assertion/Deassertion Time
(OEONTIME / OEOFFTIME / OEEXTRADELAY / OEAADMUXONTIME /
OEAADMUXOFFTIME) ............................................................................. 3566
15.4.4.9.5 nWE: Write Enable Signal Control Assertion/Deassertion Time (WEONTIME / WEOFFTIME /
WEEXTRADELAY) .................................................................................. 3567
15.4.4.9.6 GPMC_CLK .......................................................................................... 3567
SPRUIC2D – January 2017 – Revised April 2019
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Contents
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15.5
30
15.4.4.9.7 GPMC_CLK and Control Signals Setup and Hold ..............................................
15.4.4.9.8 Access Time (RDACCESSTIME / WRACCESSTIME) .........................................
15.4.4.9.9 Page Burst Access Time (PAGEBURSTACCESSTIME) ......................................
15.4.4.9.10 Bus Keeping Support ..............................................................................
15.4.4.10 NOR Access Description ..............................................................................
15.4.4.10.1 Asynchronous Access Description ..............................................................
15.4.4.10.2 Synchronous Access Description ................................................................
15.4.4.10.3 Asynchronous and Synchronous Accesses in Nonmultiplexed Mode ......................
15.4.4.10.4 Page and Burst Support ..........................................................................
15.4.4.10.5 System Burst vs External Device Burst Support...............................................
15.4.4.11 pSRAM Access Specificities ..........................................................................
15.4.4.12 NAND Access Description .............................................................................
15.4.4.12.1 NAND Memory Device in Byte or 16-bit Word Stream Mode ................................
15.4.4.12.2 NAND Device-Ready Pin .........................................................................
15.4.4.12.3 ECC Calculator .....................................................................................
15.4.4.12.4 Prefetch and Write-Posting Engine ..............................................................
15.4.5 GPMC Basic Programming Model ..........................................................................
15.4.5.1 GPMC High-Level Programming Model Overview ..................................................
15.4.5.2 GPMC Initialization ......................................................................................
15.4.5.3 GPMC Configuration in NOR Mode ...................................................................
15.4.5.4 GPMC Configuration in NAND Mode ..................................................................
15.4.5.5 Set Memory Access .....................................................................................
15.4.5.6 GPMC Timing Parameters ..............................................................................
15.4.5.6.1 GPMC Timing Parameters Formulas .............................................................
15.4.6 GPMC Use Cases and Tips .................................................................................
15.4.6.1 How to Set GPMC Timing Parameters for Typical Accesses ......................................
15.4.6.1.1 External Memory Attached to the GPMC Module ...............................................
15.4.6.1.2 Typical GPMC Setup ...............................................................................
15.4.6.2 How to Choose a Suitable Memory to Use With the GPMC .......................................
15.4.6.2.1 Supported Memories or Devices ..................................................................
15.4.6.2.2 GPMC Features and Settings .....................................................................
15.4.7 GPMC Register Manual ......................................................................................
15.4.7.1 GPMC Register Summary ..............................................................................
15.4.7.2 GPMC Register Descriptions ...........................................................................
Error Location Module ..................................................................................................
15.5.1 Error Location Module Overview ............................................................................
15.5.2 ELM Integration................................................................................................
15.5.3 ELM Functional Description ..................................................................................
15.5.3.1 ELM Software Reset .....................................................................................
15.5.3.2 ELM Power Management ...............................................................................
15.5.3.3 ELM Interrupt Requests .................................................................................
15.5.3.4 Processing Initialization .................................................................................
15.5.3.5 Processing Sequence ...................................................................................
15.5.3.6 Processing Completion ..................................................................................
15.5.4 ELM Basic Programming Model.............................................................................
15.5.4.1 ELM Low-Level Programming Model ..................................................................
15.5.4.1.1 Processing Initialization.............................................................................
15.5.4.1.2 Read Results.........................................................................................
15.5.4.2 Use Case: ELM Used in Continuous Mode ..........................................................
15.5.4.3 Use Case: ELM Used in Page Mode ..................................................................
15.5.5 ELM Register Manual .........................................................................................
15.5.5.1 ELM Instance Summary.................................................................................
15.5.5.2 ELM Registers ............................................................................................
Contents
3568
3568
3569
3569
3569
3570
3577
3586
3590
3590
3591
3591
3591
3598
3599
3615
3623
3623
3625
3625
3626
3628
3629
3632
3642
3642
3642
3642
3648
3648
3651
3652
3652
3653
3685
3685
3686
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3687
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3688
3689
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3692
3693
3696
3696
3696
SPRUIC2D – January 2017 – Revised April 2019
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15.6
16
15.5.5.2.1 ELM Register Summary ............................................................................
15.5.5.2.2 ELM Register Description ..........................................................................
On-Chip Memory (OCM) Subsystem .................................................................................
15.6.1 OCM Subsystem Overview ..................................................................................
15.6.2 OCM Subsystem Integration .................................................................................
15.6.3 OCM Subsystem Functional Desctiption ...................................................................
15.6.3.1 Block Diagram ............................................................................................
15.6.3.2 Resets .....................................................................................................
15.6.3.3 Clock Management ......................................................................................
15.6.3.4 Interrupt Requests .......................................................................................
15.6.3.5 OCM Subsystem Memory Regions ....................................................................
15.6.3.6 OCM Controller Modes Of Operation .................................................................
15.6.3.7 ECC Associated FIFOs .................................................................................
15.6.3.8 ECC Counters And Corrected Bit Distribution Register .............................................
15.6.3.9 ECC Support..............................................................................................
15.6.3.10 Circular Buffer (CBUF) Support .......................................................................
15.6.3.11 CBUF Mode Error Handling ..........................................................................
15.6.3.11.1 VBUF Address Not Mapped to a CBUF Memory Space .....................................
15.6.3.11.2 VBUF Access Not Starting At The Base Address .............................................
15.6.3.11.3 Illegal Address Change Between Two Same Type Accesses ...............................
15.6.3.11.4 Illegal Frame SIze (Short Frame Detection)....................................................
15.6.3.11.5 CBUF Overflow.....................................................................................
15.6.3.11.6 CBUF Underflow ...................................................................................
15.6.3.12 Status Reporting .......................................................................................
15.6.4 OCM Subsystem Register Manual ..........................................................................
15.6.4.1 OCM Subsystem Instance Summary ..................................................................
15.6.4.2 OCM Subsystem Registers .............................................................................
15.6.4.2.1 OCM Subsystem Register Summary .............................................................
15.6.4.2.2 OCM Subsystem Register Description ...........................................................
3696
3697
3714
3714
3714
3716
3716
3717
3717
3717
3720
3721
3721
3722
3722
3724
3725
3725
3726
3726
3727
3728
3728
3729
3729
3729
3729
3729
3731
DMA Controllers ............................................................................................................. 3764
16.1
System DMA .............................................................................................................
16.1.1 DMA_SYSTEM Module Overview ..........................................................................
16.1.2 DMA_SYSTEM Controller Environment ....................................................................
16.1.3 DMA_SYSTEM Module Integration .........................................................................
16.1.3.1 DMA Requests to the DMA_SYSTEM Controller ....................................................
16.1.3.2 Mapping of DMA Requests to DMA_CROSSBAR Inputs ..........................................
16.1.4 DMA_SYSTEM Functional Description.....................................................................
16.1.4.1 DMA_SYSTEM Controller Power Management .....................................................
16.1.4.2 DMA_SYSTEM Controller Interrupt Requests .......................................................
16.1.4.2.1 Interrupt Generation .................................................................................
16.1.4.3 Logical Channel Transfer Overview ...................................................................
16.1.4.4 FIFO Queue Memory Pool ..............................................................................
16.1.4.5 Addressing Modes .......................................................................................
16.1.4.6 Packed Accesses ........................................................................................
16.1.4.7 Burst Transactions .......................................................................................
16.1.4.8 Endianism Conversion ..................................................................................
16.1.4.9 Transfer Synchronization ...............................................................................
16.1.4.9.1 Software Synchronization ..........................................................................
16.1.4.9.2 Hardware Synchronization .........................................................................
16.1.4.10 Thread Budget Allocation ..............................................................................
16.1.4.11 FIFO Budget Allocation ................................................................................
16.1.4.12 Chained Logical Channel Transfers ..................................................................
16.1.4.13 Reprogramming an Active Channel ..................................................................
SPRUIC2D – January 2017 – Revised April 2019
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Contents
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16.2
32
16.1.4.14 Packet Synchronization ................................................................................
16.1.4.15 Graphics Acceleration Support........................................................................
16.1.4.16 Supervisor Modes ......................................................................................
16.1.4.17 Posted and Nonposted Writes ........................................................................
16.1.4.18 Disabling a Channel During Transfer ................................................................
16.1.4.19 FIFO Draining Mechanism .............................................................................
16.1.4.20 Linked List ...............................................................................................
16.1.4.20.1 Overview ............................................................................................
16.1.4.20.2 Link-List Transfer Profile ..........................................................................
16.1.4.20.3 Descriptors ..........................................................................................
16.1.4.20.4 Linked-List Control and Monitoring ..............................................................
16.1.5 DMA_SYSTEM Basic Programming Model................................................................
16.1.5.1 Setup Configuration......................................................................................
16.1.5.2 Software-Triggered (Nonsynchronized) Transfer ....................................................
16.1.5.3 Hardware-Synchronized Transfer ......................................................................
16.1.5.4 Synchronized Transfer Monitoring Using CDAC .....................................................
16.1.5.5 Concurrent Software and Hardware Synchronization ...............................................
16.1.5.6 Chained Transfer.........................................................................................
16.1.5.7 90-Degree Clockwise Image Rotation .................................................................
16.1.5.8 Graphic Operations ......................................................................................
16.1.5.9 Linked-List Programming Guidelines ..................................................................
16.1.6 DMA_SYSTEM Register Manual ............................................................................
16.1.6.1 DMA_SYSTEM Instance Summary....................................................................
16.1.6.2 DMA_SYSTEM Registers ...............................................................................
16.1.6.2.1 DMA_SYSTEM Register Summary ...............................................................
16.1.6.2.2 DMA_SYSTEM Register Description .............................................................
Enhanced DMA ..........................................................................................................
16.2.1 EDMA Module Overview .....................................................................................
16.2.1.1 EDMA Features ..........................................................................................
16.2.1.2 EDMA Controllers Configuration .......................................................................
16.2.2 EDMA Controller Environment ..............................................................................
16.2.3 EDMA Controller Integration .................................................................................
16.2.3.1 EDMA Requests to the EDMA Controller .............................................................
16.2.4 EDMA Controller Functional Description ...................................................................
16.2.4.1 Block Diagram ............................................................................................
16.2.4.1.1 Third-Party Channel Controller ....................................................................
16.2.4.1.2 Third-Party Transfer Controller ....................................................................
16.2.4.2 Types of EDMA controller Transfers ..................................................................
16.2.4.2.1 A-Synchronized Transfers..........................................................................
16.2.4.2.2 AB-Synchronized Transfers ........................................................................
16.2.4.3 Parameter RAM (PaRAM) ..............................................................................
16.2.4.3.1 PaRAM................................................................................................
16.2.4.3.2 EDMA Channel PaRAM Set Entry Fields ........................................................
16.2.4.3.3 Null PaRAM Set .....................................................................................
16.2.4.3.4 Dummy PaRAM Set.................................................................................
16.2.4.3.5 Dummy Versus Null Transfer Comparison .......................................................
16.2.4.3.6 Parameter Set Updates ............................................................................
16.2.4.3.7 Linking Transfers ....................................................................................
16.2.4.3.8 Constant Addressing Mode Transfers/Alignment Issues.......................................
16.2.4.3.9 Element Size .........................................................................................
16.2.4.4 Initiating a DMA Transfer ...............................................................................
16.2.4.4.1 DMA Channel ........................................................................................
16.2.4.4.2 QDMA Channels ....................................................................................
Contents
3800
3801
3801
3801
3802
3802
3802
3802
3803
3803
3806
3809
3809
3809
3812
3814
3814
3814
3815
3816
3817
3818
3818
3818
3818
3819
3848
3848
3849
3850
3852
3853
3857
3862
3862
3862
3864
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3866
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3868
3871
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3876
3879
3879
3879
3879
3881
SPRUIC2D – January 2017 – Revised April 2019
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16.2.4.4.3 Comparison Between DMA and QDMA Channels ..............................................
16.2.4.5 Completion of a DMA Transfer .........................................................................
16.2.4.5.1 Normal Completion ..................................................................................
16.2.4.5.2 Early Completion ....................................................................................
16.2.4.5.3 Dummy or Null Completion ........................................................................
16.2.4.6 Event, Channel, and PaRAM Mapping ................................................................
16.2.4.6.1 DMA Channel to PaRAM Mapping ................................................................
16.2.4.6.2 QDMA Channel to PaRAM Mapping..............................................................
16.2.4.7 EDMA Channel Controller Regions ....................................................................
16.2.4.7.1 Region Overview ....................................................................................
16.2.4.7.2 Channel Controller Regions........................................................................
16.2.4.7.3 Region Interrupts ....................................................................................
16.2.4.8 Chaining EDMA Channels ..............................................................................
16.2.4.9 EDMA Interrupts .........................................................................................
16.2.4.9.1 Transfer Completion Interrupts ....................................................................
16.2.4.9.2 EDMA Interrupt Servicing ..........................................................................
16.2.4.9.3 Interrupt Evaluation Operations ...................................................................
16.2.4.9.4 Error Interrupts .......................................................................................
16.2.4.10 Memory Protection......................................................................................
16.2.4.10.1 Active Memory Protection ........................................................................
16.2.4.10.2 Proxy Memory Protection .........................................................................
16.2.4.11 Event Queue(s) .........................................................................................
16.2.4.11.1 DMA/QDMA Channel to Event Queue Mapping ...............................................
16.2.4.11.2 Queue RAM Debug Visibility .....................................................................
16.2.4.11.3 Queue Resource Tracking ........................................................................
16.2.4.11.4 Performance Considerations .....................................................................
16.2.4.12 EDMA Transfer Controller (EDMA_TPTC) ..........................................................
16.2.4.12.1 Architecture Details ................................................................................
16.2.4.12.2 Memory Protection .................................................................................
16.2.4.12.3 Error Generation ...................................................................................
16.2.4.12.4 Debug Features ....................................................................................
16.2.4.12.5 EDMA_TPTC Configuration ......................................................................
16.2.4.13 Event Dataflow ..........................................................................................
16.2.4.14 EDMA controller Prioritization .........................................................................
16.2.4.14.1 Channel Priority ....................................................................................
16.2.4.14.2 Trigger Source Priority ............................................................................
16.2.4.14.3 Dequeue Priority ...................................................................................
16.2.4.15 EDMA Power, Reset and Clock Management ......................................................
16.2.4.15.1 Clock and Power Management ..................................................................
16.2.4.15.2 Reset Considerations .............................................................................
16.2.4.16 Emulation Considerations .............................................................................
16.2.5 EDMA Transfer Examples ...................................................................................
16.2.5.1 Block Move Example ....................................................................................
16.2.5.2 Subframe Extraction Example ..........................................................................
16.2.5.3 Data Sorting Example ...................................................................................
16.2.5.4 Peripheral Servicing Example ..........................................................................
16.2.5.4.1 Non-bursting Peripherals ...........................................................................
16.2.5.4.2 Bursting Peripherals ................................................................................
16.2.5.4.3 Continuous Operation ..............................................................................
16.2.5.4.4 Ping-Pong Buffering .................................................................................
16.2.5.4.5 Transfer Chaining Examples .......................................................................
16.2.5.5 Setting Up an EDMA Transfer..........................................................................
16.2.6 EDMA Debug Checklist and Programming Tips ..........................................................
SPRUIC2D – January 2017 – Revised April 2019
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Contents
3881
3882
3883
3883
3883
3883
3884
3884
3885
3885
3887
3887
3887
3888
3889
3892
3893
3894
3896
3896
3899
3901
3901
3902
3902
3902
3903
3903
3904
3904
3905
3905
3906
3906
3907
3908
3908
3908
3908
3909
3909
3910
3910
3912
3913
3915
3915
3917
3919
3922
3926
3929
3931
33
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16.2.6.1 EDMA Debug Checklist .................................................................................
16.2.6.2 EDMA Programming Tips ...............................................................................
16.2.7 EDMA Register Manual ......................................................................................
16.2.7.1 EDMA Instance Summary ..............................................................................
16.2.7.2 EDMA Registers .........................................................................................
16.2.7.2.1 EDMA Register Summary ..........................................................................
16.2.7.2.2 EDMA Register Description ........................................................................
17
Interrupt Controllers ........................................................................................................ 4086
17.1
17.2
17.3
17.4
18
Interrupt Controllers Overview .........................................................................................
Interrupt Controllers Environment .....................................................................................
Interrupt Controllers Integration .......................................................................................
17.3.1 Interrupt Requests to MPU_INTC ...........................................................................
17.3.2 Interrupt Requests to DSP1_INTC ..........................................................................
17.3.3 Interrupt Requests to IPU1_Cx_INTC ......................................................................
17.3.4 Interrupt Requests to IPU2_Cx_INTC ......................................................................
17.3.5 Interrupt Requests to PRUSS1_INTC ......................................................................
17.3.6 Interrupt Requests to PRUSS2_INTC ......................................................................
17.3.7 Mapping of Device Interrupts to IRQ_CROSSBAR Inputs...............................................
Interrupt Controllers Functional Description .........................................................................
4087
4090
4092
4092
4100
4105
4109
4113
4116
4119
4128
Control Module ............................................................................................................... 4129
18.1
18.2
18.3
18.4
34
3931
3932
3933
3933
3933
3933
3945
Control Module Overview ..............................................................................................
Control Module Environment ..........................................................................................
Control Module Integration .............................................................................................
Control Module Functional Description ...............................................................................
18.4.1 Control Module Clock Configuration ........................................................................
18.4.2 Control Module Resets .......................................................................................
18.4.3 Control Module Power Management .......................................................................
18.4.3.1 Power Management Protocols .........................................................................
18.4.4 Hardware Requests ...........................................................................................
18.4.5 Control Module Initialization .................................................................................
18.4.6 Functional Description Of The Various Register Types In CTRL_MODULE_CORE Submodule .
18.4.6.1 Pad Configuration ........................................................................................
18.4.6.1.1 Pad Configuration Registers .......................................................................
18.4.6.1.2 Pull Selection ........................................................................................
18.4.6.1.3 Pad multiplexing .....................................................................................
18.4.6.1.4 IOSETs...............................................................................................
18.4.6.1.5 Virtual IO Timing Modes ............................................................................
18.4.6.1.6 Manual IO Timing Modes ..........................................................................
18.4.6.1.7 Isolation Requirements .............................................................................
18.4.6.1.8 IO Delay Recalibration ..............................................................................
18.4.6.2 Thermal Management Related Registers .............................................................
18.4.6.2.1 Temperature Sensors Control Registers .........................................................
18.4.6.2.2 Registers For The Thermal Alert Comparators ..................................................
18.4.6.2.3 Thermal Shutdown Comparators ..................................................................
18.4.6.2.4 Temperature Timestamp Registers ...............................................................
18.4.6.2.5 Other Thermal Management Related Registers ................................................
18.4.6.2.6 Summary Of The Thermal Management Related Registers...................................
18.4.6.2.7 ADC Values Versus Temperature.................................................................
18.4.6.3 PBIAS Cell And MMC1 I/O Cells Control Registers .................................................
18.4.6.4 IRQ_CROSSBAR Module Functional Description ...................................................
18.4.6.5 DMA_CROSSBAR Module Functional Description ..................................................
18.4.6.6 SDRAM Initiator Priority Registers .....................................................................
18.4.6.7 L3_MAIN Initiator Priority Registers ...................................................................
Contents
4130
4132
4133
4135
4135
4135
4135
4135
4135
4135
4135
4136
4136
4147
4147
4147
4148
4148
4149
4150
4150
4152
4152
4154
4154
4155
4156
4157
4160
4162
4166
4170
4170
SPRUIC2D – January 2017 – Revised April 2019
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18.5
18.6
18.7
19
18.4.6.8 Memory Region Lock Registers ........................................................................
18.4.6.9 NMI Mapping To Respective Cores ...................................................................
18.4.6.10 Software Controls for the DDR3 I/O Cells ...........................................................
18.4.6.11 Reference Voltage for the Device DDR3 Receivers ...............................................
18.4.6.12 AVS Class 0 Associated Registers ...................................................................
18.4.6.13 ABB Associated Registers .............................................................................
18.4.6.14 Registers For Other Miscellaneous Functions ......................................................
18.4.6.14.1 System Boot Status Settings .....................................................................
18.4.6.14.2 Force MPU Write Nonposted Transactions ....................................................
18.4.6.14.3 Firewall Error Status Registers...................................................................
18.4.6.14.4 Settings Related To Different Peripheral Modules ............................................
18.4.7 Functional Description Of The Various Register Types In CTRL_MODULE_WKUP Submodule ..
18.4.7.1 Registers For Basic EMIF configuration ..............................................................
Control Module Register Manual ......................................................................................
18.5.1 Control Module Instance Summary .........................................................................
18.5.2 CTRL_MODULE_CORE registers ..........................................................................
18.5.2.1 CTRL_MODULE_CORE Register Summary ........................................................
18.5.2.2 CTRL_MODULE_CORE Register Description ......................................................
18.5.3 CTRL_MODULE_WKUP Registers .........................................................................
18.5.3.1 CTRL_MODULE_WKUP Register Summary .........................................................
18.5.3.2 CTRL_MODULE_WKUP Register Description .......................................................
IODELAYCONFIG Module Integration ...............................................................................
IODELAYCONFIG Module Register Manual ........................................................................
18.7.1 IODELAYCONFIG Module Instance Summary ...........................................................
18.7.2 IODELAYCONFIG Registers ................................................................................
18.7.2.1 IODELAYCONFIG Register Summary ...............................................................
18.7.2.2 IODELAYCONFIG Register Description .............................................................
4171
4171
4171
4174
4176
4179
4179
4179
4179
4180
4180
4180
4180
4180
4180
4181
4181
4199
4842
4842
4844
4867
4868
4868
4868
4868
4885
Mailbox .......................................................................................................................... 5348
19.1
19.2
19.3
19.4
Mailbox Overview .......................................................................................................
Mailbox Integration ......................................................................................................
19.2.1 System MAILBOX Integration ...............................................................................
19.2.2 IVA Mailbox Integration .......................................................................................
Mailbox Functional Description ........................................................................................
19.3.1 Mailbox Block Diagram .......................................................................................
19.3.2 Mailbox Software Reset ......................................................................................
19.3.3 Mailbox Power Management ................................................................................
19.3.4 Mailbox Interrupt Requests ..................................................................................
19.3.5 Mailbox Assignment ..........................................................................................
19.3.5.1 Description ................................................................................................
19.3.6 Sending and Receiving Messages ..........................................................................
19.3.6.1 Description ................................................................................................
19.3.7 16-Bit Register Access .......................................................................................
19.3.7.1 Description ................................................................................................
19.3.8 Example of Communication ..................................................................................
Mailbox Programming Guide ..........................................................................................
19.4.1 Mailbox Low-level Programming Models ...................................................................
19.4.1.1 Global Initialization .......................................................................................
19.4.1.1.1 Surrounding Modules Global Initialization........................................................
19.4.1.1.2 Mailbox Global Initialization ........................................................................
19.4.1.2 Mailbox Operational Modes Configuration ............................................................
19.4.1.2.1 Mailbox Processing modes ........................................................................
19.4.1.3 Mailbox Events Servicing ...............................................................................
19.4.1.3.1 Events Servicing in Sending Mode ...............................................................
SPRUIC2D – January 2017 – Revised April 2019
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Contents
5349
5350
5350
5353
5355
5356
5356
5356
5357
5357
5357
5358
5358
5358
5358
5360
5361
5361
5361
5361
5361
5362
5362
5363
5363
35
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19.5
20
20.4
20.5
MMU Overview ..........................................................................................................
MMU Integration .........................................................................................................
MMU Functional Description ...........................................................................................
20.3.1 MMU Block Diagram ..........................................................................................
20.3.1.1 MMU Address Translation Process ....................................................................
20.3.1.2 Translation Tables .......................................................................................
20.3.1.2.1 Translation Table Hierarchy........................................................................
20.3.1.2.2 First-Level Translation Table ......................................................................
20.3.1.2.3 Two-Level Translation ..............................................................................
20.3.1.3 Translation Lookaside Buffer ...........................................................................
20.3.1.3.1 TLB Entry Format ...................................................................................
20.3.1.4 No Translation (Bypass) Regions ......................................................................
20.3.2 MMU Software Reset .........................................................................................
20.3.3 MMU Power Management ...................................................................................
20.3.4 MMU Interrupt Requests .....................................................................................
20.3.5 MMU Error Handling ..........................................................................................
MMU Low-level Programming Models ................................................................................
20.4.1 Global Initialization ............................................................................................
20.4.1.1 Surrounding Modules Global Initialization ............................................................
20.4.1.2 MMU Global Initialization................................................................................
20.4.1.2.1 Main Sequence - MMU Global Initialization......................................................
20.4.1.2.2 Subsequence - Configure a TLB entry ...........................................................
20.4.1.3 Operational Modes Configuration ......................................................................
20.4.1.3.1 Main Sequence - Writing TLB Entries Statically.................................................
20.4.1.3.2 Main Sequence - Protecting TLB Entries ........................................................
20.4.1.3.3 Main Sequence - Deleting TLB Entries ...........................................................
20.4.1.3.4 Main Sequence - Read TLB Entries ..............................................................
MMU Register Manual ..................................................................................................
20.5.1 MMU Instance Summary .....................................................................................
20.5.2 MMU Registers ................................................................................................
20.5.2.1 MMU Register Summary ................................................................................
20.5.2.2 MMU Register Description ..............................................................................
5386
5389
5391
5391
5391
5392
5392
5393
5396
5399
5400
5401
5401
5401
5402
5402
5403
5403
5403
5403
5403
5404
5405
5405
5405
5405
5405
5407
5407
5407
5407
5410
Spinlock ......................................................................................................................... 5427
21.1
21.2
21.3
21.4
36
5363
5364
5364
5364
5364
5367
Memory Management Units .............................................................................................. 5385
20.1
20.2
20.3
21
19.4.1.3.2 Events Servicing in Receiving Mode..............................................................
Mailbox Register Manual ...............................................................................................
19.5.1 Mailbox Instance Summary ..................................................................................
19.5.2 Mailbox Registers .............................................................................................
19.5.2.1 Mailbox Register Summary .............................................................................
19.5.2.2 Mailbox Register Description ...........................................................................
Spinlock Overview.......................................................................................................
Spinlock Integration .....................................................................................................
Spinlock Functional Description .......................................................................................
21.3.1 Spinlock Software Reset .....................................................................................
21.3.2 Spinlock Power Management ...............................................................................
21.3.3 About Spinlocks ...............................................................................................
21.3.4 Spinlock Functional Operation...............................................................................
Spinlock Programming Guide..........................................................................................
21.4.1 Spinlock Low-level Programming Models ..................................................................
21.4.1.1 Surrounding Modules Global Initialization ............................................................
21.4.1.2 Basic Spinlock Operations ..............................................................................
21.4.1.2.1 Spinlocks Clearing After a System Bug Recovery ..............................................
21.4.1.2.2 Take and Release Spinlock ........................................................................
Contents
5428
5429
5430
5430
5430
5430
5431
5432
5432
5432
5432
5432
5432
SPRUIC2D – January 2017 – Revised April 2019
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21.5
22
Spinlock Register Manual ..............................................................................................
21.5.1 Spinlock Instance Summary .................................................................................
21.5.2 Spinlock Registers ............................................................................................
21.5.2.1 Spinlock Register Summary ............................................................................
21.5.2.2 Spinlock Register Description ..........................................................................
5435
5435
5435
5435
5435
Timers ........................................................................................................................... 5439
22.1
22.2
22.3
Timers Overview ........................................................................................................
General-Purpose Timers ...............................................................................................
22.2.1 General-Purpose Timers Overview .........................................................................
22.2.1.1 GP Timer Features ......................................................................................
22.2.2 GP Timer Environment .......................................................................................
22.2.2.1 GP Timer External System Interface ..................................................................
22.2.3 GP Timer Integration..........................................................................................
22.2.4 GP Timer Functional Description............................................................................
22.2.4.1 GP Timer Block Diagram ...............................................................................
22.2.4.2 TIMER1, TIMER2 and TIMER10 Power Management ..............................................
22.2.4.2.1 Wake-Up Capability .................................................................................
22.2.4.3 Power Management of Other GP Timers .............................................................
22.2.4.3.1 Wake-Up Capability .................................................................................
22.2.4.4 Software Reset ...........................................................................................
22.2.4.5 GP Timer Interrupts ......................................................................................
22.2.4.6 Timer Mode Functionality ...............................................................................
22.2.4.6.1 1-ms Tick Generation (Only TIMER1, TIMER2 and TIMER10) ...............................
22.2.4.7 Capture Mode Functionality ............................................................................
22.2.4.8 Compare Mode Functionality ...........................................................................
22.2.4.9 Prescaler Functionality ..................................................................................
22.2.4.10 Pulse-Width Modulation ................................................................................
22.2.4.11 Timer Counting Rate ...................................................................................
22.2.4.12 Timer Under Emulation ................................................................................
22.2.4.13 Accessing GP Timer Registers .......................................................................
22.2.4.13.1 Writing to Timer Registers ........................................................................
22.2.4.13.2 Reading From Timer Counter Registers ........................................................
22.2.4.14 Posted Mode Selection ................................................................................
22.2.5 GP Timer Low-Level Programming Models ...............................................................
22.2.5.1 Global Initialization .......................................................................................
22.2.5.1.1 Global Initialization of Surrounding Modules.....................................................
22.2.5.1.2 GP Timer Module Global Initialization ............................................................
22.2.5.2 Operational Mode Configuration .......................................................................
22.2.5.2.1 GP Timer Mode ......................................................................................
22.2.5.2.2 GP Timer Compare Mode ..........................................................................
22.2.5.2.3 GP Timer Capture Mode ...........................................................................
22.2.5.2.4 GP Timer PWM Mode ..............................................................................
22.2.6 GP Timer Register Manual...................................................................................
22.2.6.1 GP Timer Instance Summary...........................................................................
22.2.6.2 GP Timer Registers ......................................................................................
22.2.6.2.1 GP Timer Register Summary ......................................................................
22.2.6.2.2 GP Timer Register Description ....................................................................
22.2.6.2.3 TIMER1, TIMER2, and TIMER10 Register Description ........................................
32-kHz Synchronized Timer (COUNTER_32K) .....................................................................
22.3.1 32-kHz Synchronized Timer Overview .....................................................................
22.3.1.1 32-kHz Synchronized Timer Features .................................................................
22.3.2 32-kHz Synchronized Timer Integration ....................................................................
22.3.3 32-kHz Synchronized Timer Functional Description ......................................................
SPRUIC2D – January 2017 – Revised April 2019
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Copyright © 2017–2019, Texas Instruments Incorporated
Contents
5440
5441
5441
5442
5443
5443
5445
5449
5449
5452
5452
5453
5454
5454
5455
5455
5456
5457
5459
5459
5460
5461
5462
5462
5463
5465
5465
5467
5467
5467
5467
5467
5467
5468
5468
5469
5470
5470
5470
5470
5473
5492
5497
5497
5497
5498
5499
37
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22.4
23
5499
5501
5501
5502
5504
5504
5504
5506
5508
5508
5508
5508
5509
5509
5510
5510
5511
5512
5512
5512
5512
5513
5513
5515
5515
5515
5516
5516
5516
5517
5517
5517
5517
5519
Real-Time Clock (RTC) ..................................................................................................... 5531
23.1
23.2
23.3
23.4
38
22.3.3.1 Reading the 32-kHz Synchronized Timer .............................................................
22.3.4 COUNTER_32K Timer Register Manual ...................................................................
22.3.4.1 COUNTER_32K Timer Register Mapping Summary ................................................
22.3.4.2 COUNTER_32K Timer Register Description .........................................................
Watchdog Timer .........................................................................................................
22.4.1 Watchdog Timer Overview ...................................................................................
22.4.1.1 Watchdog Timer Features ..............................................................................
22.4.2 Watchdog Timer Integration .................................................................................
22.4.3 Watchdog Timer Functional Description ...................................................................
22.4.3.1 Power Management .....................................................................................
22.4.3.1.1 Wake-Up Capability .................................................................................
22.4.3.2 Interrupts ..................................................................................................
22.4.3.3 General Watchdog Timer Operation...................................................................
22.4.3.4 Reset Context ............................................................................................
22.4.3.5 Overflow/Reset Generation .............................................................................
22.4.3.6 Prescaler Value/Timer Reset Frequency .............................................................
22.4.3.7 Triggering a Timer Reload ..............................................................................
22.4.3.8 Start/Stop Sequence for Watchdog Timer (Using the WSPR Register) ..........................
22.4.3.9 Modifying Timer Count/Load Values and Prescaler Setting ........................................
22.4.3.10 Watchdog Counter Register Access Restriction (WCRR) .........................................
22.4.3.11 Watchdog Timer Interrupt Generation ...............................................................
22.4.3.12 Watchdog Timer Under Emulation ...................................................................
22.4.3.13 Accessing Watchdog Timer Registers ...............................................................
22.4.4 Watchdog Timer Low-Level Programming Model.........................................................
22.4.4.1 Global Initialization .......................................................................................
22.4.4.1.1 Surrounding Modules Global Initialization........................................................
22.4.4.1.2 Watchdog Timer Module Global Initialization ....................................................
22.4.4.2 Operational Mode Configuration .......................................................................
22.4.4.2.1 Watchdog Timer Basic Configuration .............................................................
22.4.5 Watchdog Timer Register Manual ..........................................................................
22.4.5.1 Watchdog Timer Instance Summary ..................................................................
22.4.5.2 Watchdog Timer Registers .............................................................................
22.4.5.2.1 Watchdog Timer Register Summary ..............................................................
22.4.5.2.2 Watchdog Timer Register Description ............................................................
RTC Overview ...........................................................................................................
23.1.1 RTC Features ..................................................................................................
RTC Environment .......................................................................................................
23.2.1 RTC External Interface .......................................................................................
RTC Integration ..........................................................................................................
RTC Functional Description ............................................................................................
23.4.1 Clock Source ...................................................................................................
23.4.2 Interrupt Support ..............................................................................................
23.4.2.1 CPU Interrupts............................................................................................
23.4.2.2 Interrupt Description .....................................................................................
23.4.2.2.1 Timer Interrupt (timer_intr) .........................................................................
23.4.2.2.2 Alarm Interrupt (alarm_intr) ........................................................................
23.4.3 RTC Programming/Usage Guide ............................................................................
23.4.3.1 Time/Calendar Data Format ............................................................................
23.4.3.2 Register Access ..........................................................................................
23.4.3.3 Register Spurious Write Protection ....................................................................
23.4.3.4 Reading the Timer/Calendar (TC) Registers .........................................................
23.4.3.4.1 Rounding Seconds ..................................................................................
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SPRUIC2D – January 2017 – Revised April 2019
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23.5
23.6
24
23.4.3.5 Modifying the TC Registers .............................................................................
23.4.3.5.1 General Registers ...................................................................................
23.4.3.6 Crystal Compensation ...................................................................................
23.4.4 Scratch Registers .............................................................................................
23.4.5 Debouncing ....................................................................................................
23.4.6 Power Management ..........................................................................................
23.4.6.1 Device-Level Power Management .....................................................................
23.4.6.2 Subsystem-Level Power Management — PMIC Mode .............................................
RTC Low-Level Programming Guide .................................................................................
23.5.1 Global Initialization ............................................................................................
23.5.1.1 Surrounding Modules Global Initialization ............................................................
23.5.1.2 RTC Module Global Initialization .......................................................................
23.5.1.2.1 Main Sequence – RTC Module Global Initialization ............................................
RTC Register Manual ...................................................................................................
23.6.1 RTC Instance Summary ......................................................................................
23.6.2 RTC_SS Registers ............................................................................................
23.6.2.1 RTC_SS Register Summary ...........................................................................
23.6.2.2 RTC_SS Register Description .........................................................................
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Serial Communication Interfaces ...................................................................................... 5568
24.1
Multimaster High-Speed I2C Controller ...............................................................................
24.1.1 HS I2C Overview...............................................................................................
24.1.2 HS I2C Environment ...........................................................................................
24.1.2.1 HS I2C Typical Application ..............................................................................
24.1.2.1.1 HS I2C Pins for Typical Connections in I2C Mode ..............................................
24.1.2.1.2 HS I2C Interface Typical Connections ............................................................
24.1.2.2 HS I2C Typical Connection Protocol and Data Format ..............................................
24.1.2.2.1 HS I2C Serial Data Format .........................................................................
24.1.2.2.2 HS I2C Data Validity .................................................................................
24.1.2.2.3 HS I2C Start and Stop Conditions .................................................................
24.1.2.2.4 HS I2C Addressing ..................................................................................
24.1.2.2.5 HS I2C Master Transmitter .........................................................................
24.1.2.2.6 HS I2C Master Receiver ............................................................................
24.1.2.2.7 HS I2C Slave Transmitter ...........................................................................
24.1.2.2.8 HS I2C Slave Receiver ..............................................................................
24.1.2.2.9 HS I2C Bus Arbitration ..............................................................................
24.1.2.2.10 HS I2C Clock Generation and Synchronization ................................................
24.1.3 HS I2C Integration .............................................................................................
24.1.4 HS I2C Functional Description ...............................................................................
24.1.4.1 HS I2C Block Diagram ...................................................................................
24.1.4.2 HS I2C Clocks ............................................................................................
24.1.4.2.1 HS I2C Clocking......................................................................................
24.1.4.2.2 HS I2C Automatic Blocking of the I2C Clock Feature ..........................................
24.1.4.3 HS I2C Software Reset ..................................................................................
24.1.4.4 HS I2C Power Management ............................................................................
24.1.4.5 HS I2C Interrupt Requests ..............................................................................
24.1.4.6 HS I2C DMA Requests ..................................................................................
24.1.4.7 HS I2C Programmable Multislave Channel Feature ................................................
24.1.4.8 HS I2C FIFO Management ..............................................................................
24.1.4.8.1 HS I2C FIFO Interrupt Mode .......................................................................
24.1.4.8.2 HS I2C FIFO Polling Mode .........................................................................
24.1.4.8.3 HS I2C FIFO DMA Mode ...........................................................................
24.1.4.8.4 HS I2C Draining Feature ...........................................................................
24.1.4.9 HS I2C Noise Filter .......................................................................................
SPRUIC2D – January 2017 – Revised April 2019
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24.1.4.10 HS I C System Test Mode .............................................................................
24.1.5 HS I2C Programming Guide ..................................................................................
24.1.5.1 HS I2C Low-Level Programming Models ..............................................................
24.1.5.1.1 HS I2C Programming Model .......................................................................
24.1.6 HS I2C Register Manual ......................................................................................
24.1.6.1 HS I2C Instance Summary ..............................................................................
24.1.6.2 HS I2C Registers .........................................................................................
24.1.6.2.1 HS I2C Register Summary..........................................................................
24.1.6.2.2 HS I2C Register Description........................................................................
HDQ/1-Wire ..............................................................................................................
24.2.1 HDQ1W Overview .............................................................................................
24.2.2 HDQ1W Environment .........................................................................................
24.2.2.1 HDQ1W Functional Modes .............................................................................
24.2.2.2 HDQ and 1-Wire (SDQ) Protocols .....................................................................
24.2.2.2.1 HDQ Protocol Initialization (Default) ..............................................................
24.2.2.2.2 1-Wire (SDQ) Protocol Initialization ...............................................................
24.2.2.2.3 Communication Sequence (HDQ and 1-Wire Protocols) ......................................
24.2.3 HDQ1W Integration ...........................................................................................
24.2.4 HDQ1W Functional Description .............................................................................
24.2.4.1 HDQ1W Block Diagram .................................................................................
24.2.4.2 HDQ1W Clocking Configuration .......................................................................
24.2.4.2.1 HDQ1W Clocks ......................................................................................
24.2.4.3 HDQ1W Hardware and Software Reset ..............................................................
24.2.4.4 HDQ1W Power Management ..........................................................................
24.2.4.4.1 Auto-Idle Mode ......................................................................................
24.2.4.4.2 Power-Down Mode ..................................................................................
24.2.4.5 HDQ Interrupt Requests ................................................................................
24.2.4.6 HDQ Mode (Default) .....................................................................................
24.2.4.6.1 HDQ Mode Features ................................................................................
24.2.4.6.2 Description ...........................................................................................
24.2.4.6.3 Single-Bit Mode ......................................................................................
24.2.4.6.4 Interrupt Conditions .................................................................................
24.2.4.7 1-Wire Mode ..............................................................................................
24.2.4.7.1 1-Wire Mode Features ..............................................................................
24.2.4.7.2 Description ...........................................................................................
24.2.4.7.3 1-Wire Single-Bit Mode Operation ................................................................
24.2.4.7.4 Interrupt Conditions .................................................................................
24.2.4.7.5 Status Flags ..........................................................................................
24.2.4.8 BITFSM Delay ............................................................................................
24.2.5 HDQ1W Low-Level Programming Model ..................................................................
24.2.5.1 Global Initialization .......................................................................................
24.2.5.1.1 Surrounding Modules Global Initialization........................................................
24.2.5.1.2 HDQ1W Module Global Initialization ..............................................................
24.2.5.2 HDQ Operational Modes Configuration ...............................................................
24.2.5.2.1 Main Sequence - HDQ Write Operation Mode ..................................................
24.2.5.2.2 Main Sequence - HDQ Read Operation Mode ..................................................
24.2.5.3 1-Wire Operational Modes Configuration .............................................................
24.2.5.3.1 Main Sequence - 1-Wire Write Operation Mode ................................................
24.2.5.3.2 Main Sequence - 1-Wire Read Operation Mode ................................................
24.2.5.3.3 Sub-sequence - Initialize 1-Wire Slave ...........................................................
24.2.6 HDQ1W Register Manual ....................................................................................
24.2.6.1 HDQ1W Instance Summary ............................................................................
24.2.6.2 HDQ1W Registers .......................................................................................
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SPRUIC2D – January 2017 – Revised April 2019
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24.3
24.2.6.2.1 HDQ1W Register Summary........................................................................
24.2.6.2.2 HDQ1W Register Description ......................................................................
UART/IrDA/CIR ..........................................................................................................
24.3.1 UART/IrDA/CIR Overview ....................................................................................
24.3.1.1 UART Features ...........................................................................................
24.3.1.2 IrDA Features .............................................................................................
24.3.1.3 CIR Features .............................................................................................
24.3.2 UART/IrDA/CIR Environment ................................................................................
24.3.2.1 UART Interface ...........................................................................................
24.3.2.1.1 System Using UART Communication With Hardware Handshake ...........................
24.3.2.1.2 UART Interface Description ........................................................................
24.3.2.1.3 UART Protocol and Data Format..................................................................
24.3.2.2 IrDA Functional Interfaces ..............................................................................
24.3.2.2.1 System Using IrDA Communication Protocol ....................................................
24.3.2.2.2 IrDA Interface Description ..........................................................................
24.3.2.2.3 IrDA Protocol and Data Format....................................................................
24.3.2.3 CIR Functional Interfaces ...............................................................................
24.3.2.3.1 System Using CIR Communication Protocol With Remote Control ..........................
24.3.2.3.2 CIR Interface Description...........................................................................
24.3.2.3.3 CIR Protocol and Data Format ....................................................................
24.3.3 UART/IrDA/CIR Integration ..................................................................................
24.3.4 UART/IrDA/CIR Functional Description ....................................................................
24.3.4.1 Block Diagram ............................................................................................
24.3.4.2 Clock Configuration ......................................................................................
24.3.4.3 Software Reset ...........................................................................................
24.3.4.4 Power Management .....................................................................................
24.3.4.4.1 UART Mode Power Management .................................................................
24.3.4.4.2 IrDA Mode Power Management (UART3 Only) .................................................
24.3.4.4.3 CIR Mode Power Management (UART3 Only) ..................................................
24.3.4.4.4 Local Power Management .........................................................................
24.3.4.5 Interrupt Requests .......................................................................................
24.3.4.5.1 UART Mode Interrupt Management ..............................................................
24.3.4.5.2 IrDA Mode Interrupt Management ................................................................
24.3.4.5.3 CIR Mode Interrupt Management .................................................................
24.3.4.6 FIFO Management .......................................................................................
24.3.4.6.1 FIFO Trigger .........................................................................................
24.3.4.6.2 FIFO Interrupt Mode ................................................................................
24.3.4.6.3 FIFO Polled Mode Operation ......................................................................
24.3.4.6.4 FIFO DMA Mode Operation ........................................................................
24.3.4.7 Mode Selection ...........................................................................................
24.3.4.7.1 Register Access Modes ............................................................................
24.3.4.7.2 UART/IrDA (SIR, MIR, FIR)/CIR Mode Selection ...............................................
24.3.4.8 Protocol Formatting ......................................................................................
24.3.4.8.1 UART Mode ..........................................................................................
24.3.4.8.2 IrDA Mode (UART3 Only) ..........................................................................
24.3.4.8.3 CIR Mode (UART3 Only) ...........................................................................
24.3.5 UART/IrDA/CIR Basic Programming Model ...............................................................
24.3.5.1 Global Initialization .......................................................................................
24.3.5.1.1 Surrounding Modules Global Initialization........................................................
24.3.5.1.2 UART/IrDA/CIR Module Global Initialization .....................................................
24.3.5.2 Mode selection ..........................................................................................
24.3.5.3 Submode selection ......................................................................................
24.3.5.4 Load FIFO trigger and DMA mode settings ..........................................................
SPRUIC2D – January 2017 – Revised April 2019
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24.4
42
24.3.5.4.1 DMA mode Settings .................................................................................
24.3.5.4.2 FIFO Trigger Settings ...............................................................................
24.3.5.5 Protocol, Baud rate and interrupt settings ............................................................
24.3.5.5.1 Baud rate settings ...................................................................................
24.3.5.5.2 Interrupt settings .....................................................................................
24.3.5.5.3 Protocol settings .....................................................................................
24.3.5.5.4 UART/IrDA(SIR/MIR/FIR)/CIR .....................................................................
24.3.5.6 Hardware and Software Flow Control Configuration ................................................
24.3.5.6.1 Hardware Flow Control Configuration ............................................................
24.3.5.6.2 Software Flow Control Configuration .............................................................
24.3.5.7 IrDA Programming Model (UART3 Only) .............................................................
24.3.5.7.1 SIR mode ............................................................................................
24.3.5.7.2 MIR mode ...........................................................................................
24.3.5.7.3 FIR mode ............................................................................................
24.3.6 UART/IrDA/CIR Register Manual ...........................................................................
24.3.6.1 UART/IrDA/CIR Instance Summary ...................................................................
24.3.6.2 UART/IrDA/CIR Registers ..............................................................................
24.3.6.2.1 UART/IrDA/CIR Register Summary .............................................................
24.3.6.2.2 UART/IrDA/CIR Register Description .............................................................
Multichannel Serial Peripheral Interface..............................................................................
24.4.1 McSPI Overview ...............................................................................................
24.4.2 McSPI Environment ...........................................................................................
24.4.2.1 Basic McSPI Pins for Master Mode....................................................................
24.4.2.2 Basic McSPI Pins for Slave Mode .....................................................................
24.4.2.3 Multichannel SPI Protocol and Data Format .........................................................
24.4.2.3.1 Transfer Format .....................................................................................
24.4.2.4 SPI in Master Mode ......................................................................................
24.4.2.5 SPI in Slave Mode .......................................................................................
24.4.3 McSPI Integration .............................................................................................
24.4.4 McSPI Functional Description ...............................................................................
24.4.4.1 McSPI Block Diagram ...................................................................................
24.4.4.2 Reset ......................................................................................................
24.4.4.3 Master Mode ..............................................................................................
24.4.4.3.1 Master Mode Features..............................................................................
24.4.4.3.2 Master Transmit-and-Receive Mode (Full Duplex) .............................................
24.4.4.3.3 Master Transmit-Only Mode (Half Duplex) .......................................................
24.4.4.3.4 Master Receive-Only Mode (Half Duplex) .......................................................
24.4.4.3.5 Single-Channel Master Mode ......................................................................
24.4.4.3.6 Start-Bit Mode .......................................................................................
24.4.4.3.7 Chip-Select Timing Control ........................................................................
24.4.4.3.8 Programmable SPI Clock ..........................................................................
24.4.4.4 Slave Mode ...............................................................................................
24.4.4.4.1 Dedicated Resources ...............................................................................
24.4.4.4.2 Slave Transmit-and-Receive Mode ...............................................................
24.4.4.4.3 Slave Transmit-Only Mode .........................................................................
24.4.4.4.4 Slave Receive-Only Mode .........................................................................
24.4.4.5 3-Pin or 4-Pin Mode .....................................................................................
24.4.4.6 FIFO Buffer Management ...............................................................................
24.4.4.6.1 Buffer Almost Full ...................................................................................
24.4.4.6.2 Buffer Almost Empty ................................................................................
24.4.4.6.3 End of Transfer Management......................................................................
24.4.4.7 Interrupts ..................................................................................................
24.4.4.7.1 Interrupt Events in Master Mode ..................................................................
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SPRUIC2D – January 2017 – Revised April 2019
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24.5
24.6
24.4.4.7.2 Interrupt Events in Slave Mode ....................................................................
24.4.4.7.3 Interrupt-Driven Operation .........................................................................
24.4.4.7.4 Polling .................................................................................................
24.4.4.8 DMA Requests ...........................................................................................
24.4.4.9 Power Saving Management ............................................................................
24.4.4.9.1 Normal Mode.........................................................................................
24.4.4.9.2 Idle Mode .............................................................................................
24.4.5 McSPI Programming Guide ..................................................................................
24.4.5.1 Global Initialization .......................................................................................
24.4.5.1.1 Surrounding Modules Global Initialization........................................................
24.4.5.1.2 McSPI Global Initialization .........................................................................
24.4.5.2 Operational Mode Configuration ......................................................................
24.4.5.2.1 McSPI Operational Modes ........................................................................
24.4.5.3 Common Transfer Procedures Without FIFO – Polling Method ...................................
24.4.5.3.1 Receive-Only Procedure – Polling Method ......................................................
24.4.5.3.2 Receive-Only Procedure – Interrupt Method ....................................................
24.4.5.3.3 Transmit-Only Procedure – Polling Method......................................................
24.4.5.3.4 Transmit-and-Receive Procedure – Polling Method ............................................
24.4.6 McSPI Register Manual ......................................................................................
24.4.6.1 McSPI Instance Summary ..............................................................................
24.4.6.2 McSPI Registers .........................................................................................
24.4.6.2.1 McSPI Register Summary ..........................................................................
24.4.6.2.2 McSPI Register Description ........................................................................
Quad Serial Peripheral Interface ......................................................................................
24.5.1 Quad Serial Peripheral Interface Overview ................................................................
24.5.2 QSPI Environment ............................................................................................
24.5.3 QSPI Integration ...............................................................................................
24.5.4 QSPI Functional Description .................................................................................
24.5.4.1 QSPI Block Diagram .....................................................................................
24.5.4.1.1 SFI Register Control ................................................................................
24.5.4.1.2 SFI Translator ........................................................................................
24.5.4.1.3 SPI Control Interface ................................................................................
24.5.4.1.4 SPI Clock Generator ...............................................................................
24.5.4.1.5 SPI Control State-Machine .........................................................................
24.5.4.1.6 SPI Data Shifter .....................................................................................
24.5.4.2 QSPI Clock Configuration ...............................................................................
24.5.4.3 QSPI Interrupt Requests ................................................................................
24.5.4.4 QSPI Memory Regions ..................................................................................
24.5.5 QSPI Register Manual ........................................................................................
24.5.5.1 QSPI Instance Summary ................................................................................
24.5.5.2 QSPI registers ............................................................................................
24.5.5.2.1 QSPI Register Summary ..........................................................................
24.5.5.2.2 QSPI Register Description ........................................................................
Multichannel Audio Serial Port ........................................................................................
24.6.1 McASP Overview ..............................................................................................
24.6.2 McASP Environment ..........................................................................................
24.6.2.1 McASP Signals ..........................................................................................
24.6.2.2 Protocols and Data Formats ............................................................................
24.6.2.2.1 Protocols Supported ................................................................................
24.6.2.2.2 Definition of Terms ..................................................................................
24.6.2.2.3 TDM Format ..........................................................................................
24.6.2.2.4 I2S Format ...........................................................................................
24.6.2.2.5 S/PDIF Coding Format .............................................................................
SPRUIC2D – January 2017 – Revised April 2019
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24.6.3 McASP Integration ............................................................................................
24.6.4 McASP Functional Description ..............................................................................
24.6.4.1 McASP Block Diagram ..................................................................................
24.6.4.2 McASP Clock and Frame-Sync Configurations ......................................................
24.6.4.2.1 McASP Transmit Clock .............................................................................
24.6.4.2.2 McASP Receive Clock ..............................................................................
24.6.4.2.3 Frame-Sync Generator ............................................................................
24.6.4.2.4 Synchronous and Asynchronous Transmit and Receive Operations .........................
24.6.4.3 Serializers .................................................................................................
24.6.4.4 Format Units ..............................................................................................
24.6.4.4.1 Transmit Format Unit ...............................................................................
24.6.4.4.2 Receive Format Unit ................................................................................
24.6.4.5 State-Machines ...........................................................................................
24.6.4.6 TDM Sequencers ........................................................................................
24.6.4.7 McASP Software Reset .................................................................................
24.6.4.8 McASP Power Management ...........................................................................
24.6.4.9 Transfer Modes...........................................................................................
24.6.4.9.1 Burst Transfer Mode ................................................................................
24.6.4.9.2 Time-Division Multiplexed (TDM) Transfer Mode ...............................................
24.6.4.9.3 DIT Transfer Mode ..................................................................................
24.6.4.10 Data Transmission and Reception ...................................................................
24.6.4.10.1 Data Ready Status and Event/Interrupt Generation...........................................
24.6.4.11 McASP Audio FIFO (AFIFO) ..........................................................................
24.6.4.11.1 AFIFO Data Transmission ........................................................................
24.6.4.11.2 AFIFO Data Reception ............................................................................
24.6.4.11.3 Arbitration Between Transmit and Receive DMA Requests..................................
24.6.4.12 McASP Events and Interrupt Requests ..............................................................
24.6.4.12.1 Transmit Data Ready Event and Interrupt ......................................................
24.6.4.12.2 Receive Data Ready Event and Interrupt.......................................................
24.6.4.12.3 Error Interrupt ......................................................................................
24.6.4.12.4 Multiple Interrupts ..................................................................................
24.6.4.13 DMA Requests ..........................................................................................
24.6.4.14 Loopback Modes ........................................................................................
24.6.4.14.1 Loopback Mode Configurations ..................................................................
24.6.4.15 Error Reporting ..........................................................................................
24.6.4.15.1 Buffer Underrun Error -Transmitter ..............................................................
24.6.4.15.2 Buffer Overrun Error-Receiver ...................................................................
24.6.4.15.3 DATA Port Error - Transmitter ...................................................................
24.6.4.15.4 DATA Port Error - Receiver ......................................................................
24.6.4.15.5 Unexpected Frame Sync Error ...................................................................
24.6.4.15.6 Clock Failure Detection ...........................................................................
24.6.5 McASP Low-Level Programming Model ...................................................................
24.6.5.1 Global Initialization .......................................................................................
24.6.5.1.1 Surrounding Modules Global Initialization........................................................
24.6.5.1.2 McASP Global Initialization ........................................................................
24.6.5.2 Operational Modes Configuration ......................................................................
24.6.5.2.1 McASP Transmission Modes ......................................................................
24.6.5.2.2 McASP Reception Modes ..........................................................................
24.6.5.2.3 McASP Event Servicing ............................................................................
24.6.6 McASP Register Manual .....................................................................................
24.6.6.1 McASP Instance Summary .............................................................................
24.6.6.2 McASP Registers ........................................................................................
24.6.6.2.1 MCASP_CFG Register Summary .................................................................
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24.7
24.8
24.6.6.2.2 MCASP_CFG Register Description ...............................................................
24.6.6.2.3 MCASP_AFIFO Register Summary...............................................................
24.6.6.2.4 MCASP_AFIFO Register Description .............................................................
24.6.6.2.5 MCASP_DAT Register Summary .................................................................
24.6.6.2.6 MCASP_DAT Register Description ...............................................................
SuperSpeed USB DRD .................................................................................................
24.7.1 SuperSpeed USB DRD Subsystem Overview ............................................................
24.7.1.1 Main Features ............................................................................................
24.7.2 SuperSpeed USB DRD Subsystem Environment.........................................................
24.7.2.1 SuperSpeed USB DRD Subsystem I/O Interfaces ..................................................
24.7.2.2 SuperSpeed USB Subsystem Application ............................................................
24.7.2.2.1 USB3.0 DRD Application ...........................................................................
24.7.2.2.2 USB2.0 DRD Internal PHY .........................................................................
24.7.2.2.3 USB2.0 DRD External PHY ........................................................................
24.7.2.2.4 Host Mode ............................................................................................
24.7.2.2.5 Device Mode .........................................................................................
24.7.3 SuperSpeed USB Subsystem Integration ..................................................................
SATA Controller .........................................................................................................
24.8.1 SATA Controller Overview ..................................................................................
24.8.1.1 SATA Controller .........................................................................................
24.8.1.1.1 AHCI Mode Overview ...............................................................................
24.8.1.1.2 Native Command Queuing ........................................................................
24.8.1.1.3 SATA Transport Layer Functionalities ...........................................................
24.8.1.1.4 SATA Link Layer Functionalities ..................................................................
24.8.1.2 SATA Controller Features ..............................................................................
24.8.2 SATA Controller Environment ...............................................................................
24.8.3 SATA Controller Integration..................................................................................
24.8.4 SATA Controller Functional Description....................................................................
24.8.4.1 SATA Controller Block Diagram........................................................................
24.8.4.2 SATA Controller Link Layer Protocol and Data Format .............................................
24.8.4.2.1 SATA 8b/10b Parallel Encoding/Decoding .......................................................
24.8.4.2.2 SATA Stream Dword Components................................................................
24.8.4.2.3 Scrambling/Descrambling Processing ............................................................
24.8.4.3 Resets .....................................................................................................
24.8.4.3.1 Hardware Reset .....................................................................................
24.8.4.3.2 Software Initiated Resets ...........................................................................
24.8.4.4 Power Management .....................................................................................
24.8.4.4.1 SATA Specific Power Management ..............................................................
24.8.4.4.2 Master Standby and Slave Idle Management Protocols ......................................
24.8.4.4.3 Clock Gating Synchronization ....................................................................
24.8.4.5 Interrupt Requests .......................................................................................
24.8.4.5.1 Interrupt Generation ................................................................................
24.8.4.5.2 Levels of Interrupt Control..........................................................................
24.8.4.5.3 Interrupt Events Description .......................................................................
24.8.4.5.4 Interrupt Condition Control .........................................................................
24.8.4.5.5 Command Completion Coalescing Interrupts....................................................
24.8.4.6 System Memory FIS Descriptors ......................................................................
24.8.4.6.1 Command List Structure Basics ...................................................................
24.8.4.6.2 Supported Types of Commands...................................................................
24.8.4.6.3 Received FIS Structures ...........................................................................
24.8.4.6.4 FIS Descriptors Summary ..........................................................................
24.8.4.7 Transport Layer FIS-Based Interactions ..............................................................
24.8.4.7.1 Software Processing of the Port Command List ................................................
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24.9
46
24.8.4.7.2 Handling the Received FIS Descriptors ..........................................................
24.8.4.8 DMA Port Configuration ................................................................................
24.8.4.9 Port Multiplier Operation ................................................................................
24.8.4.9.1 Command-Based Switching Mode ................................................................
24.8.4.9.2 Port Multiplier Enumeration ........................................................................
24.8.4.10 Activity LED Generation Functionality................................................................
24.8.4.11 Supported Types of SATA Transfers.................................................................
24.8.4.11.1 Supported Higher Level Protocols ..............................................................
24.8.4.12 SATA Controller AHCI Hardware Register Interface ..............................................
24.8.5 SATA Controller Low Level Programming Model .........................................................
24.8.5.1 Global Initialization .......................................................................................
24.8.5.1.1 Surrounding Modules Global Initialization........................................................
24.8.5.1.2 SATA Controller Global Initialization ..............................................................
24.8.5.1.3 Issue Command - Main Sequence ................................................................
24.8.5.1.4 Receive FIS—Main Sequence.....................................................................
24.8.6 SATA Controller Register Manual ...........................................................................
24.8.6.1 SATA Controller Instance Summary...................................................................
24.8.6.2 DWC_ahsata Registers .................................................................................
24.8.6.2.1 DWC_ahsata Register Summary ................................................................
24.8.6.2.2 DWC_ahsata Register Description ..............................................................
24.8.6.3 SATAMAC_wrapper Registers .........................................................................
24.8.6.3.1 SATAMAC_wrapper Register Summary ........................................................
24.8.6.3.2 SATAMAC_wrapper Register Description ......................................................
PCIe Controller ..........................................................................................................
24.9.1 PCIe Controller Subsystem Overview ......................................................................
24.9.1.1 PCIe Controllers Key Features .........................................................................
24.9.2 PCIe Controller Environment ................................................................................
24.9.3 PCIe Controllers Integration .................................................................................
24.9.4 PCIe SS Controller Functional Description ................................................................
24.9.4.1 PCIe Controller Functional Block Diagram ...........................................................
24.9.4.2 PCIe Traffics ..............................................................................................
24.9.4.3 PCIe Controller Ports on L3_MAIN Interconnect ....................................................
24.9.4.3.1 PCIe Controller Master Port .......................................................................
24.9.4.3.2 PCIe Controller Slave Port ........................................................................
24.9.4.4 PCIe Controller Reset Management...................................................................
24.9.4.4.1 PCIe Reset Types and Stickiness.................................................................
24.9.4.4.2 PCIe Reset Conditions .............................................................................
24.9.4.5 PCIe Controller Power Management ..................................................................
24.9.4.5.1 PCIe Protocol Power Management ..............................................................
24.9.4.5.2 PCIE Controller Clocks Management.............................................................
24.9.4.6 PCIe Controller Interrupt Requests ....................................................................
24.9.4.6.1 PCIe Controller Main Hardware Management...................................................
24.9.4.6.2 PCIe Controller Legacy and MSI Virtual Interrupts Management ............................
24.9.4.6.3 PCIe Controller MSI Hardware Interrupt Events ...............................................
24.9.4.7 PCIe Controller Address Spaces and Address Translation ........................................
24.9.4.8 PCIe Traffic Requesting and Responding ............................................................
24.9.4.8.1 PCIe Memory-type (Mem) Traffic Management ................................................
24.9.4.8.2 PCIe Configuration Type (Cfg) Traffic Management ...........................................
24.9.4.8.3 PCIe I/O-type (IO) traffic management ...........................................................
24.9.4.8.4 PCIe Message-type (Msg) traffic management .................................................
24.9.4.9 PCIe Programming Register Interface ................................................................
24.9.4.9.1 PCIe Register Access ..............................................................................
24.9.4.9.2 Double Mapping of the PCIe Local Control Registers ..........................................
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24.9.4.9.3 Base Address Registers (BAR) Initialization ....................................................
24.9.4.9.4 PCIe Sticky Registers ...............................................................................
24.9.5 PCIe Controller Low Level Programming Model ..........................................................
24.9.5.1 Surrounding Modules Global Initialization ............................................................
24.9.5.2 Main Sequence of PCIe Controllers Initalization .....................................................
24.9.6 PCIe Standard Registers vs PCIe Subsystem Hardware Registers Mapping ........................
24.9.7 PCIe Controller Register Manual ............................................................................
24.9.7.1 PCIe Controller Instance Summary ....................................................................
24.9.7.2 PCIe_SS_EP_CFG_PCIe Registers ..................................................................
24.9.7.2.1 PCIe_SS_EP_CFG_PCIe Register Summary ...................................................
24.9.7.2.2 PCIe_SS_EP_CFG_PCIe Register Description .................................................
24.9.7.3 PCIe_SS_RC_CFG_PCIe Registers ..................................................................
24.9.7.3.1 PCIe_SS_RC_CFG_PCIe Register Summary ..................................................
24.9.7.3.2 PCIe_SS_RC_CFG_PCIe Register Description ................................................
24.9.7.4 PCIe_SS_EP_CFG_DBICS Registers ...............................................................
24.9.7.4.1 PCIe_SS_EP_CFG_DBICS Register Summary ................................................
24.9.7.4.2 PCIe_SS_EP_CFG_DBICS Register Description...............................................
24.9.7.5 PCIe_SS_RC_CFG_DBICS Registers ................................................................
24.9.7.5.1 PCIe_SS_RC_CFG_DBICS Register Summary ...............................................
24.9.7.5.2 PCIe_SS_RC_CFG_DBICS Register Description .............................................
24.9.7.6 PCIe_SS_PL_CONF Registers ........................................................................
24.9.7.6.1 PCIe_SS_PL_CONF Register Summary .......................................................
24.9.7.6.2 PCIe_SS_PL_CONF Register Description .....................................................
24.9.7.7 PCIe_SS_EP_CFG_DBICS2 Registers ..............................................................
24.9.7.7.1 PCIe_SS_EP_CFG_DBICS2 Register Summary ...............................................
24.9.7.7.2 PCIe_SS_EP_CFG_DBICS2 Register Description .............................................
24.9.7.8 PCIe_SS_RC_CFG_DBICS2 Registers ..............................................................
24.9.7.8.1 PCIe_SS_RC_CFG_DBICS2 Register Summary .............................................
24.9.7.8.2 PCIe_SS_RC_CFG_DBICS2 Register Description ...........................................
24.9.7.9 PCIe_SS_TI_CONF Registers .........................................................................
24.9.7.9.1 PCIe_SS_TI_CONF Register Summary ........................................................
24.9.7.9.2 PCIe_SS_TI_CONF Register Description ......................................................
24.10 DCAN .....................................................................................................................
24.10.1 DCAN Overview .............................................................................................
24.10.1.1 Features ..................................................................................................
24.10.2 DCAN Environment ..........................................................................................
24.10.2.1 CAN Network Basics ...................................................................................
24.10.3 DCAN Integration ............................................................................................
24.10.4 DCAN Functional Description ..............................................................................
24.10.4.1 Module Clocking Requirements .......................................................................
24.10.4.2 Interrupt Functionality ..................................................................................
24.10.4.2.1 Message Object Interrupts........................................................................
24.10.4.2.2 Status Change Interrupts .........................................................................
24.10.4.2.3 Error Interrupts .....................................................................................
24.10.4.3 DMA Functionality ......................................................................................
24.10.4.4 Local Power-Down Mode ..............................................................................
24.10.4.4.1 Entering Local Power-Down Mode ..............................................................
24.10.4.4.2 Wakeup From Local Power Down ...............................................................
24.10.4.5 Parity Check Mechanism ..............................................................................
24.10.4.5.1 Behavior on Parity Error ..........................................................................
24.10.4.5.2 Parity Testing .......................................................................................
24.10.4.6 Debug/Suspend Mode .................................................................................
24.10.4.7 Configuration of Message Objects Description .....................................................
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24.10.4.7.1 Configuration of a Transmit Object for Data Frames..........................................
24.10.4.7.2 Configuration of a Transmit Object for Remote Frames ......................................
24.10.4.7.3 Configuration of a Single Receive Object for Data Frames ..................................
24.10.4.7.4 Configuration of a Single Receive Object for Remote Frames ..............................
24.10.4.7.5 Configuration of a FIFO Buffer ...................................................................
24.10.4.8 Message Handling ......................................................................................
24.10.4.8.1 Message Handler Overview ......................................................................
24.10.4.8.2 Receive/Transmit Priority .........................................................................
24.10.4.8.3 Transmission of Messages in Event Driven CAN Communication ..........................
24.10.4.8.4 Updating a Transmit Object ......................................................................
24.10.4.8.5 Changing a Transmit Object......................................................................
24.10.4.8.6 Acceptance Filtering of Received Messages...................................................
24.10.4.8.7 Reception of Data Frames ........................................................................
24.10.4.8.8 Reception of Remote Frames ....................................................................
24.10.4.8.9 Reading Received Messages ....................................................................
24.10.4.8.10 Requesting New Data for a Receive Object ..................................................
24.10.4.8.11 Storing Received Messages in FIFO Buffers .................................................
24.10.4.8.12 Reading From a FIFO Buffer ...................................................................
24.10.4.9 CAN Bit Timing ..........................................................................................
24.10.4.9.1 Bit Time and Bit Rate..............................................................................
24.10.4.9.2 DCAN Bit Timing Registers .......................................................................
24.10.4.10 Message Interface Register Sets ...................................................................
24.10.4.10.1 Message Interface Register Sets 1 and 2.....................................................
24.10.4.10.2 IF3 Register Set ..................................................................................
24.10.4.11 Message RAM .........................................................................................
24.10.4.11.1 Structure of Message Objects ..................................................................
24.10.4.11.2 Addressing Message Objects in RAM .........................................................
24.10.4.11.3 Message RAM Representation in Debug/Suspend Mode ..................................
24.10.4.11.4 Message RAM Representation in Direct Access Mode .....................................
24.10.4.12 CAN Operation ........................................................................................
24.10.4.12.1 CAN Module Initialization........................................................................
24.10.4.12.2 CAN Message Transfer (Normal Operation)..................................................
24.10.4.12.3 Test Modes ........................................................................................
24.10.4.13 GPIO Support ..........................................................................................
24.10.5 DCAN Register Manual .....................................................................................
24.10.5.1 DCAN Instance Summary .............................................................................
24.10.5.2 DCAN Registers ........................................................................................
24.10.5.2.1 DCAN Register Summary ........................................................................
24.10.5.2.2 DCAN Register Description ......................................................................
24.11 Gigabit Ethernet Switch (GMAC_SW)................................................................................
24.11.1 GMAC_SW Overview .......................................................................................
24.11.1.1 Features ..................................................................................................
24.11.2 GMAC_SW Environment ...................................................................................
24.11.2.1 G/MII Interface ..........................................................................................
24.11.2.2 RMII Interface ...........................................................................................
24.11.2.3 RGMII Interface .........................................................................................
24.11.3 GMAC_SW Integration ......................................................................................
24.11.4 GMAC_SW Functional Description ........................................................................
24.11.4.1 Functional Block Diagram .............................................................................
24.11.4.2 GMAC_SW Ports .......................................................................................
24.11.4.2.1 Interface Mode Selection .........................................................................
24.11.4.3 Clocking ..................................................................................................
24.11.4.3.1 Subsystem Clocking ...............................................................................
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24.11.4.3.2 Interface Clocking ..................................................................................
24.11.4.4 Software IDLE ...........................................................................................
24.11.4.5 Interrupt Functionality ..................................................................................
24.11.4.5.1 Receive Packet Completion Pulse Interrupt (RX_PULSE) ...................................
24.11.4.5.2 Transmit Packet Completion Pulse Interrupt (TX_PULSE) ..................................
24.11.4.5.3 Receive Threshold Pulse Interrupt (RX_THRESH_PULSE) .................................
24.11.4.5.4 Miscellaneous Pulse Interrupt (MISC_PULSE) ................................................
24.11.4.5.5 Interrupt Pacing ....................................................................................
24.11.4.6 Reset Isolation ..........................................................................................
24.11.4.6.1 Reset Isolation Functional Description ..........................................................
24.11.4.7 Software Reset ..........................................................................................
24.11.4.8 CPSW_3G ...............................................................................................
24.11.4.8.1 CPDMA RX and TX Interfaces ...................................................................
24.11.4.8.2 Address Lookup Engine (ALE) ...................................................................
24.11.4.8.3 Packet Priority Handling ..........................................................................
24.11.4.8.4 FIFO Memory Control .............................................................................
24.11.4.8.5 FIFO Transmit Queue Control ...................................................................
24.11.4.8.6 Audio Video Bridging ..............................................................................
24.11.4.8.7 Ethernet MAC Sliver (CPGMAC_SL) ...........................................................
24.11.4.8.8 Embedded Memories ..............................................................................
24.11.4.8.9 Flow Control ........................................................................................
24.11.4.8.10 Short Gap .........................................................................................
24.11.4.8.11 Switch Latency ....................................................................................
24.11.4.8.12 Emulation Control ................................................................................
24.11.4.8.13 FIFO Loopback ...................................................................................
24.11.4.8.14 Device Level Ring (DLR) Support ..............................................................
24.11.4.8.15 Energy Efficient Ethernet Support (802.3az) .................................................
24.11.4.8.16 CPSW_3G Network Statistics ..................................................................
24.11.4.9 Static Packet Filter (SPF) ..............................................................................
24.11.4.9.1 SPF Overview ......................................................................................
24.11.4.9.2 SPF Functional Description ......................................................................
24.11.4.9.3 Programming Guide ...............................................................................
24.11.4.10 Common Platform Time Sync (CPTS)..............................................................
24.11.4.10.1 CPTS Architecture ...............................................................................
24.11.4.10.2 CPTS Initialization ................................................................................
24.11.4.10.3 Time Stamp Value ...............................................................................
24.11.4.10.4 Event FIFO ........................................................................................
24.11.4.10.5 Time Sync Events ................................................................................
24.11.4.10.6 CPTS Interrupt Handling ........................................................................
24.11.4.11 CPPI Buffer Descriptors ..............................................................................
24.11.4.11.1 TX Buffer Descriptors ............................................................................
24.11.4.11.2 RX Buffer Descriptors ............................................................................
24.11.4.12 MDIO ....................................................................................................
24.11.4.12.1 MDIO Frame Formats ...........................................................................
24.11.4.12.2 MDIO Functional Description ...................................................................
24.11.5 GMAC_SW Programming Guide ..........................................................................
24.11.5.1 Transmit Operation .....................................................................................
24.11.5.2 Receive Operation ......................................................................................
24.11.5.3 MDIO Software Interface ..............................................................................
24.11.5.3.1 Initializing the MDIO Module .....................................................................
24.11.5.3.2 Writing Data To a PHY Register .................................................................
24.11.5.3.3 Reading Data From a PHY Register ............................................................
24.11.5.4 Initialization and Configuration of CPSW ............................................................
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24.11.6 GMAC_SW Register Manual ...............................................................................
24.11.6.1 GMAC_SW Instance Summary .......................................................................
24.11.6.2 SS Registers ............................................................................................
24.11.6.2.1 SS Register Summary ...........................................................................
24.11.6.2.2 SS Register Description .........................................................................
24.11.6.3 PORT Registers.........................................................................................
24.11.6.3.1 PORT Register Summary .......................................................................
24.11.6.3.2 PORT Register Description .....................................................................
24.11.6.4 CPDMA registers .......................................................................................
24.11.6.4.1 CPDMA Register Summary .....................................................................
24.11.6.4.2 CPDMA Register Description ...................................................................
24.11.6.5 STATS Registers .......................................................................................
24.11.6.5.1 STATS Register Summary .......................................................................
24.11.6.5.2 STATS Register Description .....................................................................
24.11.6.6 STATERAM Registers .................................................................................
24.11.6.6.1 STATERAM Register Summary ................................................................
24.11.6.6.2 STATERAM Register Description ..............................................................
24.11.6.7 CPTS registers ..........................................................................................
24.11.6.7.1 CPTS Register Summary .......................................................................
24.11.6.7.2 CPTS Register Description .....................................................................
24.11.6.8 ALE registers ............................................................................................
24.11.6.8.1 ALE Register Summary .........................................................................
24.11.6.8.2 ALE Register Description .......................................................................
24.11.6.9 SL registers ..............................................................................................
24.11.6.9.1 SL Register Summary ...........................................................................
24.11.6.9.2 SL Register Description .........................................................................
24.11.6.10 MDIO registers.........................................................................................
24.11.6.10.1 MDIO Register Summary ......................................................................
24.11.6.10.2 MDIO Register Description ....................................................................
24.11.6.11 WR registers ...........................................................................................
24.11.6.11.1 WR Register Summary ........................................................................
24.11.6.11.2 WR Register Description .......................................................................
24.11.6.12 SPF Registers .........................................................................................
24.11.6.12.1 SPF Register Summary .........................................................................
24.11.6.12.2 SPF Register Description .......................................................................
24.12 Media Local Bus (MLB) ................................................................................................
24.12.1 MLB Overview ................................................................................................
24.12.2 MLB Environment ............................................................................................
24.12.2.1 MLB IO Cell Controls ...................................................................................
24.12.2.2 Doubling the MLB Clock Line Frequency ............................................................
24.12.3 MLB Integration ..............................................................................................
24.12.4 MLB Functional Description ................................................................................
24.12.4.1 Block Diagram ...........................................................................................
24.12.4.1.1 MediaLB Core Block ...............................................................................
24.12.4.1.2 Routing Fabric Block ..............................................................................
24.12.4.1.3 Data Buffer RAM ...................................................................................
24.12.4.1.4 Channel Table RAM ...............................................................................
24.12.4.1.5 DMA Block .........................................................................................
24.12.4.2 Software and Data Flow for MLBSS .................................................................
24.12.4.2.1 Data Flow For Receive Channels ...............................................................
24.12.4.2.2 Data Flow for Transmit Channels ................................................................
24.12.4.3 MLB Priority On The L3_MAIN Interconnect ........................................................
24.12.5 MLB Programming Guide ...................................................................................
50
Contents
6535
6535
6535
6535
6536
6544
6544
6545
6592
6592
6593
6621
6621
6622
6639
6639
6640
6655
6655
6655
6661
6661
6662
6672
6672
6673
6681
6681
6682
6691
6691
6692
6701
6701
6702
6715
6715
6715
6716
6719
6720
6722
6722
6723
6724
6724
6724
6731
6737
6738
6738
6739
6739
SPRUIC2D – January 2017 – Revised April 2019
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24.12.5.1 Global Initialization......................................................................................
24.12.5.1.1 Surrounding Modules Global Initialization ......................................................
24.12.5.1.2 MLBSS Global Initialization .......................................................................
24.12.5.2 MLBSS Operational Modes Configuration...........................................................
24.12.5.2.1 Channel Servicing .................................................................................
24.12.5.2.2 Channel Table RAM Access .....................................................................
24.12.6 MLB Register Manual .......................................................................................
24.12.6.1 MLB Instance Summary ...............................................................................
24.12.6.2 MLB registers............................................................................................
24.12.6.2.1 MLB Register Summary .........................................................................
24.12.6.2.2 MLB Register Description .......................................................................
25
6739
6739
6739
6744
6744
6746
6747
6747
6747
6747
6748
eMMC/SD/SDIO ............................................................................................................... 6766
25.1
25.2
25.3
25.4
eMMC/SD/SDIO Overview .............................................................................................
25.1.1 eMMC/SD/SDIO Features ...................................................................................
eMMC/SD/SDIO Environment .........................................................................................
25.2.1 eMMC/SD/SDIO Functional Modes .........................................................................
25.2.1.1 eMMC/SD/SDIO Connected to an eMMC, SD, or SDIO Card .....................................
25.2.2 Protocol and Data Format ....................................................................................
25.2.2.1 Protocol....................................................................................................
25.2.2.2 Data Format ..............................................................................................
eMMC/SD/SDIO Integration ...........................................................................................
eMMC/SD/SDIO Functional Description .............................................................................
25.4.1 Block Diagram .................................................................................................
25.4.2 Resets ..........................................................................................................
25.4.2.1 Hardware Reset ..........................................................................................
25.4.2.2 Software Reset ...........................................................................................
25.4.3 Power Management ..........................................................................................
25.4.4 Interrupt Requests ............................................................................................
25.4.4.1 Interrupt-Driven Operation ..............................................................................
25.4.4.2 Polling .....................................................................................................
25.4.4.3 Asynchronous Interrupt..................................................................................
25.4.5 DMA Modes ....................................................................................................
25.4.5.1 Master DMA Operations ................................................................................
25.4.5.1.1 Descriptor Table Description .......................................................................
25.4.5.1.2 Requirements for Descriptors ......................................................................
25.4.5.1.3 Advanced DMA Description ........................................................................
25.4.5.2 Slave DMA Operations ..................................................................................
25.4.5.2.1 DMA Receive Mode .................................................................................
25.4.5.2.2 DMA Transmit Mode ................................................................................
25.4.6 Mode Selection ................................................................................................
25.4.7 Buffer Management ...........................................................................................
25.4.7.1 Data Buffer ................................................................................................
25.4.7.1.1 Memory Size, Block Length, and Buffer-Management Relationship .........................
25.4.7.1.2 Data Buffer Status ...................................................................................
25.4.8 Transfer Process ..............................................................................................
25.4.8.1 Different Types of Commands .........................................................................
25.4.8.2 Different Types of Responses ..........................................................................
25.4.9 Transfer or Command Status and Errors Reporting ......................................................
25.4.9.1 Busy Time-Out for R1b, R5b Response Type .......................................................
25.4.9.2 Busy Time-Out After Write CRC Status ...............................................................
25.4.9.3 Write CRC Status Time-Out ............................................................................
25.4.9.4 Read Data Time-Out ....................................................................................
25.4.9.5 Boot Acknowledge Time-Out ...........................................................................
SPRUIC2D – January 2017 – Revised April 2019
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Copyright © 2017–2019, Texas Instruments Incorporated
Contents
6767
6768
6771
6771
6771
6772
6773
6775
6778
6784
6784
6784
6784
6784
6785
6789
6792
6792
6793
6793
6793
6794
6795
6796
6797
6797
6798
6799
6799
6799
6802
6803
6803
6803
6803
6804
6805
6805
6805
6806
6807
51
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25.5
25.6
26
Shared PHY Component Subsystem
26.1
26.2
52
25.4.10 Auto Command 12 Timings ................................................................................
25.4.10.1 Auto CMD12 Timings During Write Transfer ........................................................
25.4.10.2 Auto CMD12 Timings During Read Transfer ........................................................
25.4.11 Transfer Stop .................................................................................................
25.4.12 Output Signals Generation .................................................................................
25.4.12.1 Generation on Falling Edge of MMC Clock .........................................................
25.4.12.2 Generation on Rising Edge of MMC Clock ..........................................................
25.4.13 Sampling Clock Tuning .....................................................................................
25.4.14 Card Boot Mode Management .............................................................................
25.4.14.1 Boot Mode Using CMD0 ...............................................................................
25.4.14.2 Boot Mode With CMD Line Tied to 0 .................................................................
25.4.15 MMC CE-ATA Command Completion Disable Management ..........................................
25.4.16 Test Registers ................................................................................................
25.4.17 eMMC/SD/SDIO Hardware Status Features .............................................................
eMMC/SD/SDIO Programming Guide ................................................................................
25.5.1 Low-Level Programming Models ............................................................................
25.5.1.1 Global Initialization .......................................................................................
25.5.1.1.1 Surrounding Modules Global Initialization........................................................
25.5.1.1.2 eMMC/SD/SDIO Host Controller Initialization Flow .............................................
25.5.1.2 Operational Modes Configuration ......................................................................
25.5.1.2.1 Basic Operations for eMMC/SD/SDIO Host Controller .........................................
25.5.1.2.2 Bus Voltage Selection ..............................................................................
25.5.1.2.3 Boot Mode Configuration ...........................................................................
25.5.1.2.4 SDR104/HS200 DLL Tuning Procedure..........................................................
eMMC/SD/SDIO Register Manual ....................................................................................
25.6.1 eMMC/SD/SDIO Instance Summary........................................................................
25.6.2 eMMC/SD/SDIO Registers ...................................................................................
25.6.2.1 eMMC/SD/SDIO Register Summary ..................................................................
25.6.2.2 eMMC/SD/SDIO Register Description ................................................................
................................................................................. 6912
SATA PHY Subsystem .................................................................................................
26.1.1 SATA PHY Subsystem Overview ..........................................................................
26.1.2 SATA PHY Subsystem Environment .......................................................................
26.1.2.1 SATA PHY I/O Signals ..................................................................................
26.1.3 SATA PHY Subsystem Integration..........................................................................
26.1.4 SATA PHY Subsystem Functional Description............................................................
26.1.4.1 SATA PLL Controller L4 Interface Adapter Functional Description ...............................
26.1.4.2 SATA PHY Serializer and Deserializer Functional Descriptions ...................................
26.1.4.2.1 SATA PHY Reset....................................................................................
26.1.4.2.2 SATA_PHY Clocking................................................................................
26.1.4.2.3 SATA_PHY Power Management ..................................................................
26.1.4.2.4 SATA_PHY Hardware Requests ..................................................................
26.1.4.3 SATA Clock Generator Subsystem Functional Description ........................................
26.1.4.3.1 SATA DPLL Clock Generator Overview ..........................................................
26.1.4.3.2 SATA DPLL Clock Generator Reset ..............................................................
26.1.4.3.3 SATA DPLL Low-Power Modes ...................................................................
26.1.4.3.4 SATA DPLL Clocks Configuration ................................................................
26.1.4.3.5 SATA DPLL Subsystem Architecture .............................................................
26.1.4.3.6 SATA DPLL Clock Generator Modes and State Transitions ..................................
26.1.4.3.7 SATA PLL Controller Functions ...................................................................
26.1.5 SATA PHY Subsystem Low-Level Programming Model .................................................
USB3_PHY Subsystem.................................................................................................
26.2.1 USB3_PHY Subsystem Overview..........................................................................
Contents
6808
6808
6808
6808
6810
6810
6810
6811
6811
6812
6812
6813
6813
6813
6815
6815
6815
6815
6815
6818
6818
6835
6836
6839
6841
6841
6841
6841
6843
6913
6913
6915
6915
6917
6920
6920
6920
6920
6920
6921
6921
6921
6922
6923
6923
6923
6924
6925
6928
6931
6933
6933
SPRUIC2D – January 2017 – Revised April 2019
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26.3
26.4
26.2.2 USB3_PHY Subsystem Environment ......................................................................
26.2.2.1 USB3_PHY I/O Signals .................................................................................
26.2.3 USB3_PHY Subsystem Integration .........................................................................
26.2.4 USB3_PHY Subsystem Functional Description ...........................................................
26.2.4.1 Super-Speed USB PLL Controller L4 Interface Adapter Functional Description ................
26.2.4.2 USB3_PHY Serializer and Deserializer Functional Descriptions ..................................
26.2.4.2.1 USB3_PHY Module Resets ........................................................................
26.2.4.2.2 USB3_PHY Subsystem Clocking .................................................................
26.2.4.2.3 USB3_PHY Power Management ..................................................................
26.2.4.2.4 USB3_PHY Hardware Requests ..................................................................
26.2.4.3 USB3_PHY Clock Generator Subsystem Functional Description .................................
26.2.4.3.1 USB3_PHY DPLL Clock Generator Overview...................................................
26.2.4.3.2 USB3_PHY DPLL Clock Generator Reset .......................................................
26.2.4.3.3 USB3_PHY DPLL Low-Power Modes ............................................................
26.2.4.3.4 USB3_PHY DPLL Clocks Configuration .........................................................
26.2.4.3.5 USB3_PHY DPLL Subsystem Architecture ......................................................
26.2.4.3.6 USB3_PHY DPLL Clock Generator Modes and State Transitions ...........................
26.2.4.3.7 USB3_PHY PLL Controller Functions ............................................................
26.2.5 USB3_PHY Subsystem Low-Level Programming Model ................................................
USB3 PHY and SATA PHY Register Manual .......................................................................
26.3.1 USB3 PHY and SATA PHY Instance Summary ..........................................................
26.3.2 USB3_PHY_RX Registers ..................................................................................
26.3.2.1 USB3_PHY_RX Register Summary ...................................................................
26.3.2.2 USB3_PHY_RX Register Description ................................................................
26.3.3 USB3_PHY_TX Registers ...................................................................................
26.3.3.1 USB3_PHY_TX Register Summary ...................................................................
26.3.3.2 USB3_PHY_TX Register Description ................................................................
26.3.4 DPLLCTRL Registers .........................................................................................
26.3.4.1 DPLLCTRL Register Summary ........................................................................
26.3.4.2 DPLLCTRL Register Description ......................................................................
PCIe PHY Subsystem ..................................................................................................
26.4.1 PCIe PHY Subsystem Overview ...........................................................................
26.4.1.1 PCIe PHY Subsystem Key Features ..................................................................
26.4.2 PCIe PHY Subsystem Environment ........................................................................
26.4.2.1 PCIe PHY I/O Signals ...................................................................................
26.4.3 PCIe Shared PHY Subsystem Integration .................................................................
26.4.4 PCIe PHY Subsystem Functional Description .............................................................
26.4.4.1 PCIe PHY Subsystem Block Diagram.................................................................
26.4.4.2 OCP2SCP Functional Description .....................................................................
26.4.4.2.1 OCP2SCP Reset ....................................................................................
26.4.4.2.2 OCP2SCP Power Management ...................................................................
26.4.4.2.3 OCP2SCP Timing Registers ......................................................................
26.4.4.3 PCIe PHY Serializer and Deserializer Functional Descriptions ....................................
26.4.4.3.1 PCIe PHY Module Resets..........................................................................
26.4.4.3.2 PCIe PHY Subsystem Clocking ...................................................................
26.4.4.3.3 PCIe PHY Power Management ...................................................................
26.4.4.3.4 PCIe PHY Hardware Requests ....................................................................
26.4.4.4 PCIe PHY Clock Generator Subsystem Functional Description ...................................
26.4.4.4.1 PCIe PHY DPLL Clock Generator ................................................................
26.4.4.4.2 PCIe PHY APLL Clock Generator.................................................................
26.4.4.4.3 ACSPCIE reference clock buffer ..................................................................
26.4.5 PCIePHY Subsystem Low-Level Programming Model ...................................................
26.4.6 PCIe PHY Subsystem Register Manual ....................................................................
SPRUIC2D – January 2017 – Revised April 2019
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Contents
6935
6935
6937
6940
6940
6940
6940
6940
6941
6942
6942
6942
6944
6944
6944
6945
6947
6950
6952
6954
6954
6954
6954
6955
6961
6961
6961
6964
6964
6964
6971
6971
6972
6974
6974
6976
6979
6979
6980
6980
6980
6980
6981
6981
6981
6983
6983
6983
6985
6991
6994
6994
6998
53
www.ti.com
26.4.6.1 PCIe PHY Instance Summary ..........................................................................
26.4.6.1.1 PCIe_PHY_RX Registers ..........................................................................
26.4.6.1.2 PCIe_PHY_TX Registers ...........................................................................
26.4.6.1.3 OCP2SCP Registers ................................................................................
27
General-Purpose Interface................................................................................................ 7010
27.1
27.2
27.3
27.4
27.5
27.6
54
6998
6998
7004
7007
General-Purpose Interface Overview .................................................................................
General-Purpose Interface Environment .............................................................................
27.2.1 General-Purpose Interface as a Keyboard Interface .....................................................
27.2.2 General-Purpose Interface Signals .........................................................................
General-Purpose Interface Integration ...............................................................................
General-Purpose Interface Functional Description .................................................................
27.4.1 General-Purpose Interface Block Diagram ................................................................
27.4.2 General-Purpose Interface Interrupt and Wake-Up Features ...........................................
27.4.2.1 Synchronous Path: Interrupt Request Generation ...................................................
27.4.2.2 Asynchronous Path: Wake-Up Request Generation ................................................
27.4.2.3 Wake-Up Event Conditions During Transition To/From IDLE State ...............................
27.4.2.4 Interrupt (or Wake-Up) Line Release ..................................................................
27.4.3 General-Purpose Interface Clock Configuration ..........................................................
27.4.3.1 Clocking ...................................................................................................
27.4.4 General-Purpose Interface Hardware and Software Reset ..............................................
27.4.5 General-Purpose Interface Power Management ..........................................................
27.4.5.1 Power Domain ............................................................................................
27.4.5.2 Power Management .....................................................................................
27.4.5.2.1 Idle Scheme ..........................................................................................
27.4.5.2.2 Operating Modes ....................................................................................
27.4.5.2.3 System Power Management and Wakeup .......................................................
27.4.5.2.4 Module Power Saving ..............................................................................
27.4.6 General-Purpose Interface Interrupt and Wake-Up Requests ..........................................
27.4.6.1 Interrupt Requests Generation .........................................................................
27.4.6.2 Wake-Up Requests Generation ........................................................................
27.4.7 General-Purpose Interface Channels Description ........................................................
27.4.8 General-Purpose Interface Data Input/Output Capabilities ..............................................
27.4.9 General-Purpose Interface Set-and-Clear Protocol.......................................................
27.4.9.1 Description ................................................................................................
27.4.9.2 Clear Instruction ..........................................................................................
27.4.9.2.1 Clear Register Addresses ..........................................................................
27.4.9.2.2 Clear Instruction Example ..........................................................................
27.4.9.3 Set Instruction ............................................................................................
27.4.9.3.1 Set Register Addresses ............................................................................
27.4.9.3.2 Set Instruction Example ............................................................................
General-Purpose Interface Programming Guide ....................................................................
27.5.1 General-Purpose Interface Low-Level Programming Models ...........................................
27.5.1.1 Global Initialization .......................................................................................
27.5.1.1.1 Surrounding Modules Global Initialization........................................................
27.5.1.1.2 General-Purpose Interface Module Global Initialization ........................................
27.5.1.2 General-Purpose Interface Operational Modes Configuration .....................................
27.5.1.2.1 General-Purpose Interface Read Input Register ................................................
27.5.1.2.2 General-Purpose Interface Set Bit Function .....................................................
27.5.1.2.3 General-Purpose Interface Clear Bit Function...................................................
General-Purpose Interface Register Manual ........................................................................
27.6.1 General-Purpose Interface Instance Summary ...........................................................
27.6.2 General-Purpose Interface Registers .......................................................................
27.6.2.1 General-Purpose Interface Register Summary ......................................................
Contents
7011
7014
7014
7015
7018
7023
7023
7024
7024
7025
7026
7027
7028
7028
7028
7029
7029
7029
7029
7029
7030
7030
7032
7032
7033
7034
7035
7035
7035
7036
7036
7036
7036
7036
7037
7038
7038
7038
7038
7038
7039
7039
7039
7039
7040
7040
7040
7040
SPRUIC2D – January 2017 – Revised April 2019
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Copyright © 2017–2019, Texas Instruments Incorporated
www.ti.com
.................................................... 7044
Keyboard Controller ........................................................................................................ 7062
28.1 Keyboard Controller Overview ......................................................................................... 7063
28.2 Keyboard Controller Environment ..................................................................................... 7065
28.2.1 Keyboard Controller Functions/Modes ..................................................................... 7065
28.2.2 Keyboard Controller Signals ................................................................................. 7066
28.2.3 Protocols and Data Formats ................................................................................. 7066
28.3 Keyboard Controller Integration ....................................................................................... 7068
28.4 Keyboard Controller Functional Description ......................................................................... 7070
28.4.1 Keyboard Controller Block Diagram ........................................................................ 7070
28.4.2 Keyboard Controller Software Reset ....................................................................... 7071
28.4.3 Keyboard Controller Power Management .................................................................. 7071
28.4.4 Keyboard Controller Interrupt Requests.................................................................... 7071
28.4.5 Keyboard Controller Software Mode ........................................................................ 7071
28.4.6 Keyboard Controller Hardware Decoding Modes ......................................................... 7072
28.4.6.1 Functional Modes ........................................................................................ 7072
28.4.6.2 Keyboard Controller Timer .............................................................................. 7072
28.4.6.3 State-Machine Status .................................................................................... 7074
28.4.6.4 Keyboard Controller Interrupt Generation ............................................................ 7074
28.4.6.4.1 Interrupt-Generation Scheme ...................................................................... 7074
28.4.6.4.2 Keyboard Buffer and Missed Events (Overrun Feature) ....................................... 7076
28.4.7 Keyboard Controller Key Coding Registers ................................................................ 7076
28.4.8 Keyboard Controller Register Access ...................................................................... 7077
28.4.8.1 Write Registers Access ................................................................................. 7077
28.4.8.2 Read Registers Access ................................................................................. 7078
28.5 Keyboard Controller Programming Guide ............................................................................ 7079
28.5.1 Keyboard Controller Low-Level Programming Models ................................................... 7079
28.5.1.1 Global Initialization ....................................................................................... 7079
28.5.1.1.1 Surrounding Modules Global Initialization........................................................ 7079
28.5.1.1.2 Keyboard Controller Global Initialization ......................................................... 7079
28.5.1.2 Operational Modes Configuration ...................................................................... 7080
28.5.1.2.1 Keyboard Controller in Hardware Decoding Mode (Default Mode) ........................... 7080
28.5.1.2.2 Keyboard Controller Software Scanning Mode .................................................. 7081
28.5.1.2.3 Using the Timer ...................................................................................... 7081
28.5.1.2.4 State-Machine Status Register .................................................................... 7081
28.5.1.3 Keyboard Controller Events Servicing ................................................................ 7081
28.6 Keyboard Controller Register Manual ................................................................................ 7083
28.6.1 Keyboard Controller Instance Summary ................................................................... 7083
28.6.2 Keyboard Controller Registers .............................................................................. 7083
28.6.2.1 Keyboard Controller Register Summary .............................................................. 7083
28.6.2.2 Keyboard Controller Register Description ........................................................... 7084
Pulse-Width Modulation Subsystem .................................................................................. 7099
29.1 PWM Subsystem Resources .......................................................................................... 7100
29.1.1 PWMSS Overview ............................................................................................ 7100
29.1.1.1 PWMSS Key Features .................................................................................. 7100
29.1.1.2 PWMSS Unsupported Fetaures........................................................................ 7101
29.1.2 PWMSS Environment......................................................................................... 7102
29.1.2.1 PWMSS I/O Interface.................................................................................... 7102
29.1.3 PWMSS Integration ........................................................................................... 7104
29.1.3.1 PWMSS Module Interfaces Implementation .......................................................... 7107
29.1.3.1.1 Device Specific PWMSS Features ................................................................ 7108
29.1.3.1.2 Daisy-Chain Connectivity between PWMSS Modules ......................................... 7108
29.1.3.1.3 eHRPWM Modules Time Base Clock Gating .................................................... 7109
27.6.2.2
28
29
General-Purpose Interface Register Description
SPRUIC2D – January 2017 – Revised April 2019
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Contents
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29.2
56
29.1.4 PWMSS Subsystem Power, Reset and Clock Configuration............................................
29.1.4.1 PWMSS Local Clock Management ....................................................................
29.1.4.2 PWMSS Modules Local Clock Gating .................................................................
29.1.4.3 PWMSS Software Reset ................................................................................
29.1.5 PWMSS_CFG Register Manual .............................................................................
29.1.5.1 PWMSS_CFG Instance Summary .....................................................................
29.1.5.2 PWMSS_CFG Registers ................................................................................
29.1.5.2.1 PWMSS_CFG Register Summary ...............................................................
29.1.5.2.2 PWMSS_CFG Register Description .............................................................
Enhanced PWM (ePWM) Module .....................................................................................
29.2.1 ePWM Overview...............................................................................................
29.2.2 ePWM Functional Description ...............................................................................
29.2.2.1 ePWM Submodule Features ...........................................................................
29.2.2.2 Proper ePWM Interrupt Initialization Procedure .....................................................
29.2.2.3 ePWM Time-Base (TB) Submodule ...................................................................
29.2.2.3.1 Purpose of the ePWM Time-Base Submodule ..................................................
29.2.2.3.2 Controlling and Monitoring the ePWM Time-Base Submodule ...............................
29.2.2.3.3 Calculating PWM Period and Frequency.........................................................
29.2.2.3.4 Phase Locking the Time-Base Clocks of Multiple ePWM Modules ...........................
29.2.2.3.5 ePWM Time-Base Counter Modes and Timing Waveforms ...................................
29.2.2.4 ePWM Counter-Compare (CC) Submodule ..........................................................
29.2.2.4.1 Purpose of the ePWM Counter-Compare Submodule .........................................
29.2.2.4.2 Controlling and Monitoring the ePWM Counter-Compare Submodule .......................
29.2.2.4.3 Operational Highlights for the ePWM Counter-Compare Submodule ........................
29.2.2.4.4 ePWM Count Mode Timing Waveforms .........................................................
29.2.2.5 ePWM Action-Qualifier (AQ) Submodule .............................................................
29.2.2.5.1 Purpose of the ePWM Action-Qualifier Submodule.............................................
29.2.2.5.2 Controlling and Monitoring the ePWM Action-Qualifier Submodule ..........................
29.2.2.5.3 ePWM Action-Qualifier Event Priority.............................................................
29.2.2.5.4 Waveforms for Common ePWM Configurations ................................................
29.2.2.6 ePWM Dead-Band Generator (DB) Submodule .....................................................
29.2.2.6.1 Purpose of the ePWM Dead-Band Submodule .................................................
29.2.2.6.2 Controlling and Monitoring the ePWM Dead-Band Submodule ...............................
29.2.2.6.3 Operational Highlights for the ePWM Dead-Band Generator Submodule ...................
29.2.2.7 PWM-Chopper (PC) Submodule .......................................................................
29.2.2.7.1 Purpose of the PWM-Chopper Submodule ......................................................
29.2.2.7.2 Controlling the PWM-Chopper Submodule ......................................................
29.2.2.7.3 Operational Highlights for the PWM-Chopper Submodule.....................................
29.2.2.7.4 PWM Chopper Waveforms .........................................................................
29.2.2.8 ePWM Trip-Zone (TZ) Submodule.....................................................................
29.2.2.8.1 Purpose of the ePWM Trip-Zone Submodule ...................................................
29.2.2.8.2 Controlling and Monitoring the ePWM Trip-Zone Submodule .................................
29.2.2.8.3 Operational Highlights for the ePWM Trip-Zone Submodule ..................................
29.2.2.8.4 Generating ePWM Trip Event Interrupts .........................................................
29.2.2.9 ePWM Event-Trigger (ET) Submodule ................................................................
29.2.2.9.1 Purpose of the ePWM Event-Trigger Submodule ...............................................
29.2.2.9.2 Controlling and Monitoring the ePWM Event-Trigger Submodule ............................
29.2.2.9.3 Operational Overview of the ePWM Event-Trigger Submodule ...............................
29.2.2.10 High-Resolution PWM (HRPWM) Submodule ......................................................
29.2.2.10.1 Purpose of the High-Resolution PWM Submodule ............................................
29.2.2.10.2 Architecture of the High-Resolution PWM Submodule .......................................
29.2.2.10.3 Controlling and Monitoring the High-Resolution PWM Submodule .........................
29.2.2.10.4 Configuring the High-Resolution PWM Submodule ...........................................
Contents
7110
7110
7110
7111
7111
7111
7111
7111
7112
7116
7116
7120
7120
7123
7123
7124
7125
7126
7129
7129
7134
7135
7135
7137
7137
7140
7140
7140
7143
7144
7158
7158
7158
7159
7162
7162
7162
7163
7164
7166
7166
7167
7167
7168
7170
7170
7170
7171
7175
7176
7177
7177
7178
SPRUIC2D – January 2017 – Revised April 2019
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29.3
29.4
30
29.2.2.10.5 Operational Highlights for the High-Resolution PWM Submodule ..........................
29.2.2.11 eHRPWM Functional Register Groups ..............................................................
29.2.3 PWMSS_EPWM Register Manual ..........................................................................
29.2.3.1 PWMSS_EPWM Instance Summary ..................................................................
29.2.3.2 PWMSS_EPWM Registers .............................................................................
29.2.3.2.1 PWMSS_EPWM Register Summary..............................................................
29.2.3.2.2 PWMSS_EPWM Register Description............................................................
Enhanced Capture (eCAP) Module ...................................................................................
29.3.1 eCAP Overview ................................................................................................
29.3.1.1 Purpose of the eCAP Peripheral ......................................................................
29.3.1.2 eCAP Features ...........................................................................................
29.3.2 eCAP Functional Description ................................................................................
29.3.2.1 Capture and APWM Operating Mode .................................................................
29.3.2.2 eCAP Capture Mode Description ......................................................................
29.3.2.2.1 eCAP Event Prescaler ..............................................................................
29.3.2.2.2 eCAP Edge Polarity Select and Qualifier ........................................................
29.3.2.2.3 eCAP Continuous/One-Shot Control .............................................................
29.3.2.2.4 eCAP 32-Bit Counter and Phase Control ........................................................
29.3.2.2.5 CAP1-CAP4 Registers ..............................................................................
29.3.2.2.6 eCAP Interrupt Control .............................................................................
29.3.2.2.7 eCAP Shadow Load and Lockout Control .......................................................
29.3.2.2.8 eCAP Module APWM Mode Operation ...........................................................
29.3.2.3 Summary of eCAP Functional Registers..............................................................
29.3.3 PWMSS_ECAP Register Manual ..........................................................................
29.3.3.1 PWMSS_ECAP Instance Summary ...................................................................
29.3.3.2 PWMSS_ECAP Registers ..............................................................................
29.3.3.2.1 PWMSS_ECAP Register Summary...............................................................
29.3.3.2.2 PWMSS_ECAP Register Description ...........................................................
Enhanced Quadrature Encoder Pulse (eQEP) Module ............................................................
29.4.1 eQEP Overview ...............................................................................................
29.4.2 eQEP Module Functional Description ......................................................................
29.4.2.1 eQEP Inputs ..............................................................................................
29.4.2.2 eQEP Quadrature Decoder Unit (QDU) ...............................................................
29.4.2.2.1 eQEP Position Counter Input Modes .............................................................
29.4.2.2.2 eQEP Input Polarity Selection .....................................................................
29.4.2.2.3 eQEP Position-Compare Sync Output ...........................................................
29.4.2.3 eQEP Position Counter and Control Unit (PCCU) ...................................................
29.4.2.3.1 eQEP Position Counter Operating Modes .......................................................
29.4.2.3.2 eQEP Position Counter Latch .....................................................................
29.4.2.3.3 eQEP Position Counter Initialization ..............................................................
29.4.2.3.4 eQEP Position-Compare Unit ......................................................................
29.4.2.4 eQEP Edge Capture Unit ...............................................................................
29.4.2.5 eQEP Watchdog .........................................................................................
29.4.2.6 Unit Timer Base ..........................................................................................
29.4.2.7 eQEP Interrupt Structure ................................................................................
29.4.2.8 Summary of PWMSS eQEP Functional Registers ..................................................
29.4.3 PWMSS_EQEP Register Manual ..........................................................................
29.4.3.1 PWMSS_EQEP Instance Summary ...................................................................
29.4.3.2 PWMSS_EQEP Registers ..............................................................................
29.4.3.2.1 PWMSS_EQEP Register Summary ..............................................................
29.4.3.2.2 PWMSS_EQEP Register Description ............................................................
Programmable Real-Time Unit Subsystem and Industrial Communication Subsystem
30.1
7178
7181
7183
7183
7183
7183
7185
7212
7212
7212
7212
7213
7215
7216
7217
7218
7218
7219
7220
7220
7220
7222
7223
7223
7223
7224
7224
7224
7236
7236
7239
7239
7241
7242
7244
7244
7244
7244
7247
7250
7250
7252
7255
7256
7256
7257
7257
7257
7258
7258
7259
........... 7278
PRU-ICSS Overview .................................................................................................... 7279
SPRUIC2D – January 2017 – Revised April 2019
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Contents
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30.2
30.3
30.4
30.5
30.6
58
30.1.1 PRU-ICSS Key Features .....................................................................................
PRU-ICSS Environment ................................................................................................
30.2.1 PRU-ICSS I/O Interface ......................................................................................
PRU-ICSS Integration ..................................................................................................
PRU-ICSS Level Resources Functional Description ...............................................................
30.4.1 PRU-ICSS Reset Management .............................................................................
30.4.2 PRU-ICSS Power and Clock Management ................................................................
30.4.2.1 PRU-ICSS Idle and Standby States ...................................................................
30.4.2.2 Module Clock Configurations at PRU-ICSS Top Level .............................................
30.4.3 Other PRU-ICSS Module Functional Registers at Subsystem Level ...................................
30.4.4 PRU-ICSS Memory Maps ....................................................................................
30.4.4.1 PRU-ICSS Local Memory Map .........................................................................
30.4.4.1.1 PRU-ICSS Local Instruction Memory Map .......................................................
30.4.4.1.2 PRU-ICSS Local Data Memory Map..............................................................
30.4.4.2 PRU-ICSS Global Memory Map .......................................................................
30.4.5 PRUSS_CFG Register Manual ..............................................................................
30.4.5.1 PRUSS_CFG Instance Summary ......................................................................
30.4.5.2 PRUSS_CFG Registers .................................................................................
30.4.5.2.1 PRUSS_CFG Register Summary ...............................................................
30.4.5.2.2 PRUSS_CFG Register Description ..............................................................
PRU-ICSS PRU Cores .................................................................................................
30.5.1 PRU Cores Overview .........................................................................................
30.5.2 PRU Cores Functional Description .........................................................................
30.5.2.1 PRUs Constant Table ...................................................................................
30.5.2.2 PRU Module Interface ...................................................................................
30.5.2.2.1 Real-Time Status Interface Mapping (R31): Interrupt Events Input ..........................
30.5.2.2.2 Event Interface Mapping (R31): PRU System Events ..........................................
30.5.2.2.3 General-Purpose Inputs (R31): Enhanced PRU GP Module ..................................
30.5.3 PRU Multiplier with Optional Accumulation (MPY/MAC) .................................................
30.5.3.1 PRU MACs Overview....................................................................................
30.5.3.1.1 PRU MAC Key Features ...........................................................................
30.5.3.1.2 PRU MAC Operations .............................................................................
30.5.4 CRC16/32 ......................................................................................................
30.5.4.1 Features ...................................................................................................
30.5.4.2 PRU and CRC16/32 Interface ..........................................................................
30.5.4.3 Programming Model .....................................................................................
30.5.5 PRU0 and PRU1 Scratch Pad Memory ...................................................................
30.5.5.1 PRU0/1 Scratch Pad Overview ........................................................................
30.5.5.2 PRU0 /1 Scratch Pad Operations ......................................................................
30.5.5.2.1 Optional XIN/XOUT Shift ...........................................................................
30.5.6 PRUSS_PRU_CTRL Register Manual .....................................................................
30.5.6.1 PRUSS_PRU_CTRL Instance Summary .............................................................
30.5.6.2 PRUSS_PRU_CTRL Registers ........................................................................
30.5.6.2.1 PRUSS_PRU_CTRL Register Summary .......................................................
30.5.6.2.2 PRUSS_PRU_CTRL Register Description .....................................................
30.5.7 PRUSS_PRU_DEBUG Register Manual ...................................................................
30.5.7.1 PRUSS_PRU_DEBUG Instance Summary...........................................................
30.5.7.2 PRUSS_PRU_DEBUG Registers ......................................................................
30.5.7.2.1 PRUSS_PRU_DEBUG Register Summary ......................................................
30.5.7.2.2 PRUSS_PRU_DEBUG Register Description ....................................................
PRU-ICSS Local Interrupt Controller .................................................................................
30.6.1 PRU-ICSS Interrupt Controller Overview ..................................................................
30.6.2 PRU-ICSS Interrupt Controller Functional Description ...................................................
Contents
7280
7282
7282
7293
7297
7297
7297
7298
7299
7299
7300
7300
7300
7300
7301
7303
7303
7303
7303
7305
7328
7328
7329
7329
7330
7331
7331
7333
7360
7360
7360
7360
7362
7363
7363
7364
7364
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7365
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7410
SPRUIC2D – January 2017 – Revised April 2019
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30.7
30.6.2.1 PRU-ICSS Interrupt Controller System Events ......................................................
30.6.2.2 PRU-ICSS Interrupt Controller System Events Flow ................................................
30.6.2.2.1 PRU-ICSS Interrupt Processing ...................................................................
30.6.2.2.2 PRU-ICSS Interrupt Status Checking.............................................................
30.6.2.2.3 PRU-ICSS Interrupt Channel Mapping ...........................................................
30.6.2.2.4 PRU-ICSS Interrupt Nesting .......................................................................
30.6.2.2.5 PRU-ICSS Interrupt Status Clearing ..............................................................
30.6.2.3 PRU-ICSS Interrupt Disabling ..........................................................................
30.6.3 PRU-ICSS Interrupt Controller Basic Programming Model ..............................................
30.6.4 PRU-ICSS Interrupt Requests Mapping....................................................................
30.6.5 PRU-ICSS Interrupt Controller Register Manual ..........................................................
30.6.5.1 PRUSS_INTC Instance Summary .....................................................................
30.6.5.2 PRUSS_INTC Registers ................................................................................
30.6.5.2.1 PRUSS_INTC Register Summary ...............................................................
30.6.5.2.2 PRUSS_INTC Register Description .............................................................
PRU-ICSS UART Module ..............................................................................................
30.7.1 PRU-ICSS UART Module Overview ........................................................................
30.7.1.1 Purpose of the PRU-ICSS integrated UART Peripheral ............................................
30.7.1.2 PRU-ICSS UART Key Features........................................................................
30.7.1.2.1 PRU-ICSS UART Module Industry Standard Compliance Statement ........................
30.7.2 PRU-ICSS UART Environment ..............................................................................
30.7.2.1 PRU-ICSS UART Pin Multiplexing .....................................................................
30.7.2.2 PRU-ICSS UART Signal Descriptions ................................................................
30.7.2.3 PRU-ICSS UART Data Format and Protocol Description ..........................................
30.7.2.3.1 PRU-ICSS UART Transmission Protocol ........................................................
30.7.2.3.2 PRU-ICSS UART Reception Protocol ............................................................
30.7.2.3.3 PRU-ICSS UART Data Format ....................................................................
30.7.2.4 PRU-ICSS UART Clock Generation and Control ....................................................
30.7.3 PRU-ICSS UART Module Functional Description ........................................................
30.7.3.1 PRU-ICSS UART Functional Block Diagram .........................................................
30.7.3.2 PRU-ICSS UART Reset Considerations ..............................................................
30.7.3.2.1 PRU-ICSS UART Software Reset Considerations ..............................................
30.7.3.2.2 PRU-ICSS UART Hardware Reset Considerations .............................................
30.7.3.3 PRU-ICSS UART Power Management ...............................................................
30.7.3.4 PRU-ICSS UART Interrupt Support ...................................................................
30.7.3.4.1 PRU-ICSS UART Interrupt Events and Requests ..............................................
30.7.3.4.2 PRU-ICSS UART Interrupt Multiplexing ..........................................................
30.7.3.5 PRU-ICSS UART DMA Event Support ................................................................
30.7.3.6 PRU-ICSS UART Operations ..........................................................................
30.7.3.6.1 PRU-ICSS UART Transmission ...................................................................
30.7.3.6.2 PRU-ICSS UART Reception .......................................................................
30.7.3.6.3 PRU-ICSS UART FIFO Modes ....................................................................
30.7.3.6.4 PRU-ICSS UART Autoflow Control ...............................................................
30.7.3.6.5 PRU-ICSS UART Loopback Control ..............................................................
30.7.3.7 PRU-ICSS UART Initialization..........................................................................
30.7.3.8 PRU-ICSS UART Exception Processing ..............................................................
30.7.3.8.1 PRU-ICSS UART Divisor Latch Not Programmed ..............................................
30.7.3.8.2 Changing Operating Mode During Busy Serial Communication of PRU-ICSS UART .....
30.7.4 PRUSS_UART Register Manual ............................................................................
30.7.4.1 PRUSS_UART Instance Summary ....................................................................
30.7.4.2 PRUSS_UART Registers ...............................................................................
30.7.4.2.1 PRUSS_UART Register Summary ..............................................................
30.7.4.2.2 PRUSS_UART Register Description ............................................................
SPRUIC2D – January 2017 – Revised April 2019
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Contents
7411
7411
7412
7412
7412
7413
7414
7414
7414
7415
7418
7418
7418
7418
7420
7435
7435
7435
7435
7435
7435
7435
7435
7436
7436
7436
7436
7438
7440
7440
7442
7442
7442
7442
7442
7442
7442
7444
7445
7445
7445
7445
7447
7449
7449
7449
7449
7450
7450
7450
7450
7450
7451
59
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PRU-ICSS eCAP Module ..............................................................................................
30.8.1 PRU-ICSS eCAP Functional Description ..................................................................
30.8.2 PRUSS_ECAP Register Manual ............................................................................
30.8.2.1 PRUSS_ECAP Instance Summary ....................................................................
30.8.2.2 PRUSS_ECAP Registers ...............................................................................
30.8.2.2.1 PRUSS_ECAP Register Summary ..............................................................
30.8.2.2.2 PRUSS_ECAP Register Description ............................................................
30.9 PRU-ICSS MII RT Module .............................................................................................
30.9.1 Introduction .....................................................................................................
30.9.1.1 Features ...................................................................................................
30.9.1.2 Unsupported Features...................................................................................
30.9.1.3 Block Diagram ............................................................................................
30.9.2 Functional Description ........................................................................................
30.9.2.1 Data Path Configuration.................................................................................
30.9.2.1.1 Auto-forward with Optional PRU Snoop ..........................................................
30.9.2.1.2 8- or 16-bit Processing with On-the-Fly Modifications ..........................................
30.9.2.1.3 32-byte Double Buffer or Ping-Pong Processing ...............................................
30.9.2.2 Definition and Terms ....................................................................................
30.9.2.2.1 Data Frame Structure ...............................................................................
30.9.2.2.2 PRU R30 and R31 ..................................................................................
30.9.2.2.3 RX and TX L1 FIFO Data Movement .............................................................
30.9.2.2.4 CRC Computation ...................................................................................
30.9.2.3 RX MII Interface ..........................................................................................
30.9.2.3.1 RX MII Submodule Overview ......................................................................
30.9.2.4 TX MII Interface ..........................................................................................
30.9.2.4.1 TX Data Path Options to TX L1 FIFO ............................................................
30.9.2.5 PRU R31 Command Interface .........................................................................
30.9.2.6 Other Configuration Options ............................................................................
30.9.2.6.1 Nibble and Byte Order ..............................................................................
30.9.2.6.2 Preamble Source ....................................................................................
30.9.2.6.3 PRU and MII Port Multiplexer .....................................................................
30.9.2.6.4 RX L2 Scratch Pad ..................................................................................
30.9.3 PRU-ICSS MII RT Module Register Manual ...............................................................
30.9.3.1 PRUSS_MII_RT Instance Summary ..................................................................
30.9.3.2 PRUSS_MII_RT Registers ..............................................................................
30.9.3.2.1 PRUSS_MII_RT Register Summary ............................................................
30.9.3.2.2 PRUSS_MII_RT Register Description ..........................................................
30.10 PRU-ICSS MII MDIO Module .........................................................................................
30.10.1 PRU-ICSS MII MDIO Overview ............................................................................
30.10.2 PRU-ICSS MII MDIO Functional Description ............................................................
30.10.2.1 MII MDIO Management Interface Frame Formats .................................................
30.10.2.2 PRU-ICSS MII MDIO Interractions ...................................................................
30.10.2.3 PRU-ICSS MII MDIO Interrupts .......................................................................
30.10.3 PRU-ICSS MII MDIO Receive/Transmit Frame Host Software Interface ............................
30.10.4 PRU-ICSS MII MDIO Module Register Manual ..........................................................
30.10.4.1 PRUSS_MII_MDIO Instance Summary ..............................................................
30.10.4.2 PRUSS_MII_MDIO Registers .........................................................................
30.10.4.2.1 PRUSS_MII_MDIO Register Summary .......................................................
30.10.4.2.2 PRUSS_MII_MDIO Register Description .....................................................
30.11 PRU-ICSS Industrial Ethernet Peripheral (IEP) .....................................................................
30.11.1 PRU-ICSS IEP Overview ...................................................................................
30.11.2 PRU-ICSS IEP Functional Description....................................................................
30.11.2.1 PRU-ICSS IEP Clock Generation ....................................................................
30.8
60
Contents
7465
7465
7465
7465
7465
7465
7466
7477
7477
7477
7477
7477
7478
7478
7478
7479
7479
7480
7480
7480
7480
7481
7481
7481
7489
7489
7491
7493
7493
7493
7494
7495
7495
7495
7496
7496
7497
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SPRUIC2D – January 2017 – Revised April 2019
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30.11.2.2 PRU-ICSS Industrial Ethernet Timer .................................................................
30.11.2.2.1 PRU-ICSS Industrial Ethernet Timer Features ................................................
30.11.2.2.2 Industrial Ethernet Mapping ......................................................................
30.11.2.2.3 PRU-ICSS Industrial Ethernet Timer Basic Programming Sequence.......................
30.11.2.3 PRU-ICSS IEP Sync0/Sync1 Signals Generation ..................................................
30.11.2.3.1 PRU-ICSS IEP Sync0/Sync1 Features .........................................................
30.11.2.3.2 PRU-ICSS IEP Sync0/Sync1 Generation Modes .............................................
30.11.2.4 PRU-ICSS Industrial Ethernet WatchDog ...........................................................
30.11.2.4.1 Features .............................................................................................
30.11.2.5 PRU-ICSS Industrial Ethernet Digital IOs ...........................................................
30.11.2.5.1 Features .............................................................................................
30.11.2.5.2 DIGIO Block Diagrams ............................................................................
30.11.2.5.3 Basic Programming Model........................................................................
30.11.3 PRUSS_IEP Register Manual..............................................................................
30.11.3.1 PRUSS_IEP Instance Summary ......................................................................
30.11.3.2 PRUSS_IEP Registers .................................................................................
30.11.3.2.1 PRUSS_IEP Register Summary ...............................................................
30.11.3.2.2 PRUSS_IEP Register Description .............................................................
31
7531
7531
7532
7532
7532
7532
7533
7534
7535
7535
7535
7535
7536
7537
7537
7537
7537
7538
Viterbi-Decoder Coprocessor ........................................................................................... 7566
31.1
31.2
31.3
VCP Overview ...........................................................................................................
31.1.1 VCP Features ..................................................................................................
VCP Integration ..........................................................................................................
VCP Functional Description ............................................................................................
31.3.1 VCP Block Diagram ...........................................................................................
31.3.2 VCP Internal Interfaces .......................................................................................
31.3.2.1 VCP Power Management ...............................................................................
31.3.2.1.1 Idle Mode .............................................................................................
31.3.2.2 VCP Clocks ...............................................................................................
31.3.2.3 VCP Resets ...............................................................................................
31.3.2.4 Interrupt Requests .......................................................................................
31.3.2.5 EDMA Requests .........................................................................................
31.3.3 Functional Overview ..........................................................................................
31.3.3.1 Theoretical Basics of the Convolutional Code. ......................................................
31.3.4 VCP Architecture ..............................................................................................
31.3.4.1 Sliding Windows Processing ...........................................................................
31.3.4.1.1 Tailed Traceback Mode ............................................................................
31.3.4.1.2 Mixed Traceback Mode .............................................................................
31.3.4.1.3 Convergent Traceback Mode ......................................................................
31.3.4.1.4 F, R, and C Limitations .............................................................................
31.3.4.1.5 Yamamoto Parameters .............................................................................
31.3.4.1.6 Input FIFO (Branch Metrics) .......................................................................
31.3.4.1.7 Output FIFO (Decisions) ...........................................................................
31.3.5 VCP Input Data ................................................................................................
31.3.5.1 Branch Metrics Calculations ............................................................................
31.3.6 Soft Input Dynamic Ranges ..................................................................................
31.3.7 VCP Memory Sleep Mode ...................................................................................
31.3.8 Decision Data ..................................................................................................
31.3.9 Endianness .....................................................................................................
31.3.9.1 Branch Metrics ...........................................................................................
31.3.9.1.1 Hard Decisions ......................................................................................
31.3.9.1.2 Soft Decisions .......................................................................................
31.3.10 VCP Output Parameters ....................................................................................
31.3.11 Event Generation ............................................................................................
SPRUIC2D – January 2017 – Revised April 2019
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Contents
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7569
7571
7571
7572
7572
7573
7573
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7573
7574
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31.4
31.5
32
ATL Overview ............................................................................................................ 7614
Initialization .................................................................................................................... 7615
33.1
33.2
33.3
62
7586
7586
7586
7587
7587
7589
7589
7589
7589
7590
7591
7592
7592
7593
7594
7595
7596
7596
7596
7596
7597
7604
Audio Tracking Logic ...................................................................................................... 7613
32.1
33
31.3.11.1 VCPnXEVT Generation ................................................................................
31.3.11.2 VCPnREVT Generation ................................................................................
31.3.12 Operational Modes ..........................................................................................
31.3.12.1 Debugging Features ....................................................................................
31.3.13 Errors and Status ............................................................................................
VCP Modules Programming Guide ...................................................................................
31.4.1 EDMA Resources .............................................................................................
31.4.1.1 VCP1 and VCP2 Dedicated EDMA Resources ......................................................
31.4.1.2 Special VCP EDMA Programming Considerations ..................................................
31.4.1.2.1 Input Configuration Parameters Transfer ........................................................
31.4.1.2.2 Branch Metrics Transfer ............................................................................
31.4.1.2.3 Decisions Transfer ..................................................................................
31.4.1.2.4 Hard-Decisions Mode ...............................................................................
31.4.1.2.5 Soft-Decisions Mode ................................................................................
31.4.1.2.6 Output Parameters Transfer .......................................................................
31.4.2 Input Configuration Words ...................................................................................
VCP Register Manual ...................................................................................................
31.5.1 VCP1 and VCP2 Instance Summary .......................................................................
31.5.2 VCP Registers .................................................................................................
31.5.2.1 VCP Register Summary .................................................................................
31.5.2.2 VCP1 and VCP2 Data Registers Description ........................................................
31.5.2.3 VCP1 and VCP2 Configuration Registers Description ..............................................
Initialization Overview ...................................................................................................
33.1.1 Terminology ....................................................................................................
33.1.2 Initialization Process ..........................................................................................
Preinitialization ...........................................................................................................
33.2.1 Power Requirements .........................................................................................
33.2.2 Boot Device Conditions.......................................................................................
33.2.3 Clock, Reset, and Control ....................................................................................
33.2.3.1 Overview ..................................................................................................
33.2.3.2 Clocking Scheme ........................................................................................
33.2.3.3 Reset Configuration......................................................................................
33.2.3.3.1 ON/OFF Interconnect and Power-On-Reset .....................................................
33.2.3.3.2 Warm Reset ..........................................................................................
33.2.3.3.3 Peripheral Reset by GPIO .........................................................................
33.2.3.3.4 Warm Reset Impact on GPIOs ....................................................................
33.2.3.4 PMIC Control .............................................................................................
33.2.3.5 PMIC Request Signals ..................................................................................
33.2.4 Sysboot Configuration ........................................................................................
33.2.4.1 GPMC Configuration for XIP/NAND ...................................................................
33.2.4.2 System Clock Speed Selection ........................................................................
33.2.4.3 QSPI Redundant SBL Images Offset .................................................................
33.2.4.4 Booting Device Order Selection ........................................................................
33.2.4.5 Boot Peripheral Pin Multiplexing .......................................................................
Device Initialization by ROM Code ....................................................................................
33.3.1 Booting Overview .............................................................................................
33.3.1.1 Booting Types ............................................................................................
33.3.1.2 ROM Code Architecture .................................................................................
33.3.2 Memory Maps..................................................................................................
33.3.2.1 ROM Memory Map.......................................................................................
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SPRUIC2D – January 2017 – Revised April 2019
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33.4
33.3.2.2 RAM Memory Map .......................................................................................
33.3.3 Overall Booting Sequence ...................................................................................
33.3.4 Startup and Configuration ....................................................................................
33.3.4.1 Startup .....................................................................................................
33.3.4.2 Control Module Configuration ..........................................................................
33.3.4.3 PRCM Module Mode Configuration ...................................................................
33.3.4.4 Clocking Configuration ..................................................................................
33.3.4.5 Booting Device List Setup ..............................................................................
33.3.5 Peripheral Booting ............................................................................................
33.3.5.1 Description ................................................................................................
33.3.5.2 Initialization Phase for UART Boot ....................................................................
33.3.5.3 Initialization Phase for USB Boot ......................................................................
33.3.5.3.1 Initialization Procedure .............................................................................
33.3.5.3.2 SATA Peripheral Device Flashing over USB Interface ........................................
33.3.5.3.3 USB Driver Descriptors .............................................................................
33.3.5.3.4 USB Customized Vendor and Product IDs ......................................................
33.3.5.3.5 USB Driver Functionality ...........................................................................
33.3.6 Fast External Booting .........................................................................................
33.3.6.1 Overview ..................................................................................................
33.3.6.2 Fast External Booting Procedure ......................................................................
33.3.7 Memory Booting ...............................................................................................
33.3.7.1 Overview ..................................................................................................
33.3.7.2 Non-XIP Memory .........................................................................................
33.3.7.3 XIP Memory...............................................................................................
33.3.7.3.1 GPMC Initialization ..................................................................................
33.3.7.4 NAND ......................................................................................................
33.3.7.4.1 Initialization and NAND Detection .................................................................
33.3.7.4.2 NAND Read Sector Procedure ....................................................................
33.3.7.5 SPI/QSPI Flash Devices ................................................................................
33.3.7.6 eMMC Memories and SD Cards .......................................................................
33.3.7.6.1 eMMC Memories ....................................................................................
33.3.7.6.2 SD Cards .............................................................................................
33.3.7.6.3 Initialization and Detection .........................................................................
33.3.7.6.4 Read Sector Procedure ............................................................................
33.3.7.6.5 File System Handling ...............................................................................
33.3.7.7 SATA Device Boot Operation ..........................................................................
33.3.7.7.1 SATA Booting Overview ...........................................................................
33.3.7.7.2 SATA Power-Up Initialization Sequence ........................................................
33.3.7.7.3 System Conditions and Limitations for SATA Boot .............................................
33.3.7.7.4 SATA Read Sector Procedure in FAT Mode ....................................................
33.3.8 Image Format ..................................................................................................
33.3.8.1 Overview ..................................................................................................
33.3.8.2 Configuration Header ....................................................................................
33.3.8.2.1 CHSETTINGS Item .................................................................................
33.3.8.2.2 CHFLASH Item ......................................................................................
33.3.8.2.3 CHMMCSD Item .....................................................................................
33.3.8.2.4 CHQSPI Item ........................................................................................
33.3.8.3 GP Header ................................................................................................
33.3.8.4 Image Execution .........................................................................................
33.3.9 Tracing ..........................................................................................................
Services for HLOS Support ............................................................................................
33.4.1 Hypervisor .....................................................................................................
33.4.2 Caches Maintenance ........................................................................................
SPRUIC2D – January 2017 – Revised April 2019
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Contents
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33.4.3
33.4.4
33.4.5
33.4.6
34
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On-Chip Debug Support ................................................................................................... 7697
34.1
34.2
34.3
34.4
34.5
34.6
34.7
64
CP15 Registers ................................................................................................
Wakeup Generator ............................................................................................
Arm Timer ......................................................................................................
MReq Domain .................................................................................................
Introduction ...............................................................................................................
34.1.1 Key Features...................................................................................................
Debug Interfaces ........................................................................................................
34.2.1 IEEE1149.1 ....................................................................................................
34.2.2 Debug (Trace) Port ...........................................................................................
34.2.3 Trace Connector and Board Layout Considerations......................................................
Debugger Connection ..................................................................................................
34.3.1 ICEPick Module ...............................................................................................
34.3.2 ICEPick Boot Modes ..........................................................................................
34.3.2.1 Default Boot Mode .......................................................................................
34.3.2.2 Wait-In-Reset .............................................................................................
34.3.3 Dynamic TAP Insertion .......................................................................................
34.3.3.1 ICEPick Secondary TAPs ...............................................................................
Primary Debug Support ................................................................................................
34.4.1 Processor Native Debug Support ...........................................................................
34.4.1.1 Cortex-A15 Processor ...................................................................................
34.4.1.2 Cortex-M4 Processor ....................................................................................
34.4.1.3 DSP C66x .................................................................................................
34.4.1.4 IVA Arm968 ...............................................................................................
34.4.1.5 PRU ........................................................................................................
34.4.2 Cross-Triggering ...............................................................................................
34.4.2.1 SoC-Level Cross-Triggering ............................................................................
34.4.2.2 Cross-Triggering With External Device ...............................................................
34.4.3 Suspend ........................................................................................................
34.4.3.1 Debug Aware Peripherals and Host Processors .....................................................
Real-Time Debug........................................................................................................
34.5.1 Real-Time Debug Events ....................................................................................
34.5.1.1 Emulation Interrupts .....................................................................................
Power, Reset, and Clock Management Debug Support ...........................................................
34.6.1 Power and Clock Management ..............................................................................
34.6.1.1 Power and Clock Control Override From Debugger.................................................
34.6.1.1.1 Debugger Directives ................................................................................
34.6.1.1.2 Intrusive Debug Model ..............................................................................
34.6.1.2 Debug Across Power Transition .......................................................................
34.6.1.2.1 Nonintrusive Debug Model .........................................................................
34.6.1.2.2 Debug Context Save and Restore ................................................................
34.6.2 Reset Management ...........................................................................................
34.6.2.1 Debugger Directives .....................................................................................
34.6.2.1.1 Assert Reset .........................................................................................
34.6.2.1.2 Block Reset ..........................................................................................
34.6.2.1.3 Wait-In-Reset ........................................................................................
Performance Monitoring ................................................................................................
34.7.1 MPU Subsystem Performance Monitoring .................................................................
34.7.1.1 Performance Monitoring Unit ...........................................................................
34.7.1.2 L2 Cache Controller .....................................................................................
34.7.2 IPU Subsystem Performance Monitoring ..................................................................
34.7.2.1 Subsystem Counter Timer Module ....................................................................
34.7.2.2 Cache Events .............................................................................................
Contents
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SPRUIC2D – January 2017 – Revised April 2019
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34.7.3 DSP Subsystem Performance Monitoring .................................................................
34.7.3.1 Advanced Event Triggering .............................................................................
34.8 MPU Memory Adaptor (MPU_MA) Watchpoint......................................................................
34.9 Processor Trace .........................................................................................................
34.9.1 Cortex-A15 Processor Trace ................................................................................
34.9.2 DSP Processor Trace ........................................................................................
34.9.3 Trace Export ...................................................................................................
34.9.3.1 Trace Exported to External Trace Receiver ..........................................................
34.9.3.2 Trace Captured Into On-Chip Trace Buffer ...........................................................
34.9.3.3 Trace Exported Through USB ..........................................................................
34.10 System Instrumentation ................................................................................................
34.10.1 MIPI STM (CT_STM) ........................................................................................
34.10.2 System Trace Export ........................................................................................
34.10.2.1 CT_STM ATB Export ...................................................................................
34.10.2.2 Trace Streams Interleaving ............................................................................
34.10.3 Software Instrumentation ...................................................................................
34.10.3.1 MPU Software Instrumentation .......................................................................
34.10.3.2 SoC Software Instrumentation ........................................................................
34.10.4 OCP Watchpoint .............................................................................................
34.10.4.1 OCP Target Traffic Monitoring ........................................................................
34.10.4.2 Messages Triggered from System Events...........................................................
34.10.4.3 DMA Transfer Profiling .................................................................................
34.10.5 IVA Pipeline ..................................................................................................
34.10.6 L3 NOC Statistics Collector ................................................................................
34.10.6.1 L3 Target Load Monitoring ............................................................................
34.10.6.2 L3 Master Latency Monitoring.........................................................................
34.10.6.2.1 SC_LAT0 Configuration ...........................................................................
34.10.6.2.2 SC_LAT1 Configuration ...........................................................................
34.10.6.2.3 SC_LAT2 Configuration ...........................................................................
34.10.6.2.4 SC_LAT3 Configuration ...........................................................................
34.10.6.2.5 SC_LAT4 Configuration ...........................................................................
34.10.6.2.6 SC_LAT5 Configuration ...........................................................................
34.10.6.2.7 SC_LAT6 Configuration ...........................................................................
34.10.6.2.8 SC_LAT7 Configuration ...........................................................................
34.10.6.2.9 SC_LAT8 Configuration ...........................................................................
34.10.6.2.10 Statistics Collector Alarm Mode ................................................................
34.10.6.2.11 Statistics Collector Suspend Mode.............................................................
34.10.7 PM Instrumentation ..........................................................................................
34.10.8 CM Instrumentation ..........................................................................................
34.10.9 Master-ID Encoding .........................................................................................
34.10.9.1 Software Masters .......................................................................................
34.10.9.2 Hardware Masters ......................................................................................
34.11 Concurrent Debug Modes .............................................................................................
34.12 DRM Register Manual ..................................................................................................
34.12.1 DRM Instance Summary ....................................................................................
34.12.2 DRM Registers ...............................................................................................
34.12.2.1 DRM Register Summary .............................................................................
34.12.2.2 DRM Register Description ...........................................................................
A
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Glossary ........................................................................................................................ 7789
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Contents
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List of Figures
1-1.
DRA72x, DRA71x Sample Environment Diagram .................................................................... 370
1-2.
DRA72x, DRA71x Block Diagram ...................................................................................... 371
2-1.
Interconnect Overview
3-1.
Clock Tree Tool (CTT) ................................................................................................... 410
3-2.
Functional and Interface Clocks ........................................................................................ 411
3-3.
Generic Clock Domain ................................................................................................... 417
3-4.
Clock Domain State Transitions ........................................................................................ 418
3-5.
Clock Domain/Slave Module Clock-Management Interaction Sequence 1
420
3-6.
Clock Domain/Slave Module Clock-Management Interaction Sequence 2
421
3-7.
3-8.
3-9.
3-10.
3-11.
3-12.
3-13.
3-14.
3-15.
3-16.
3-17.
3-18.
3-19.
3-20.
3-21.
3-22.
3-23.
3-24.
3-25.
3-26.
3-27.
3-28.
3-29.
3-30.
3-31.
3-32.
3-33.
3-34.
3-35.
3-36.
3-37.
3-38.
3-39.
3-40.
3-41.
3-42.
3-43.
3-44.
66
...................................................................................................
.......................................
.......................................
Clock Domain/Slave Module Clock-Management Interaction Sequence 3 .......................................
Sliding Window for Dynamic Dependency.............................................................................
Generic Power Domain ..................................................................................................
Power Domain Transitions...............................................................................................
Generic Voltage Domain .................................................................................................
Generic Logic Voltage Management ...................................................................................
Generic Memory Voltage Management ................................................................................
SmartReflex Static Voltage Adjustment ................................................................................
SmartReflex Voltage Control Functional Overview ...................................................................
Comparison of Energy Consumed With/Without DVFS .............................................................
Comparison of Energy Consumed With/Without DPS ...............................................................
Performance Level and Applied Power-Management Techniques .................................................
PMFW Overview ..........................................................................................................
MPU Power-On Reset Sequence.......................................................................................
MPU Warm Reset Sequence ...........................................................................................
MPU Reset Sequence on Sleep and Wake-Up Transition ..........................................................
IVA Power-On Reset Sequence ........................................................................................
IVA Software Warm Reset Sequence ..................................................................................
DSP1 Subsystem Power-On Reset Sequence .......................................................................
DSP1 Subsystem Software Warm Reset Sequence .................................................................
IPU1 Power-On Reset Sequence.......................................................................................
IPU1 Subsystem Software Warm Reset Sequence ..................................................................
IPU2 Power-On Reset Sequence.......................................................................................
IPU2 Subsystem Software Warm Reset Sequence ..................................................................
Global Warm Reset Sequence ..........................................................................................
PRCM Module Clock Manager Overview ..............................................................................
PRM Clock Manager Overview ........................................................................................
CM_CORE_AON Overview (a) .........................................................................................
CM_CORE_AON Overview (b) .........................................................................................
CM_CORE_AON_CLKOUTMUX Clock Manager Overview (CLKOUTMUX0) ...................................
CM_CORE_AON_CLKOUTMUX Clock Manager Overview (CLKOUTMUX1 and CLKOUTMUX2) ..........
CM_CORE_AON_TIMER1 Clock Manager Overview ...............................................................
CM_CORE_AON_TIMER2 Clock Manager Overview ...............................................................
CM_CORE_AON_TIMER3 Clock Manager Overview ...............................................................
CM_CORE_AON_TIMER4 Clock Manager Overview ...............................................................
CM_CORE_AON_MCASP1 Clock Manager Overview ..............................................................
CM_CORE_AON_MCASP2 Clock Manager Overview ..............................................................
CM_CORE_AON_MCASP3 Clock Manager Overview ..............................................................
List of Figures
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SPRUIC2D – January 2017 – Revised April 2019
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3-45.
Generic DPLL Functional Diagram ..................................................................................... 513
3-46.
DPLL_PER Overview
3-47.
DPLL_CORE Overview .................................................................................................. 520
3-48.
DPLL_ABE Overview..................................................................................................... 522
3-49.
DPLL_MPU Overview .................................................................................................... 524
3-50.
DPLL_IVA Overview ...................................................................................................... 526
3-51.
DPLL_USB Overview
3-52.
DPLL_DSP Overview
3-53.
3-54.
3-55.
3-56.
3-57.
3-58.
3-59.
3-60.
3-61.
3-62.
3-63.
3-64.
3-65.
3-66.
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3-68.
3-69.
3-70.
3-71.
3-72.
3-73.
3-74.
3-75.
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3-87.
3-88.
4-1.
4-2.
4-3.
4-4.
4-5.
....................................................................................................
518
.................................................................................................... 527
.................................................................................................... 528
DPLL_GMAC Overview .................................................................................................. 530
DPLL_GPU Overview .................................................................................................... 532
DPLL_DDR Overview .................................................................................................... 533
DPLL_PCIE_REF Overview ............................................................................................. 535
APLL_PCIE Overview .................................................................................................... 536
CD_WKUPAON Overview ............................................................................................... 537
CD_DSP1 Overview ...................................................................................................... 542
CD_CUSTEFUSE Overview ............................................................................................ 545
CD_MPU Overview ....................................................................................................... 547
CD_L4PER1 Overview ................................................................................................... 550
CD_L4PER2 Overview ................................................................................................... 570
CD_L4PER3 Overview ................................................................................................... 581
CD_L4SEC Overview .................................................................................................... 584
CD_L3INIT Overview ..................................................................................................... 586
CD_IVA Overview ........................................................................................................ 594
CD_GPU Overview ....................................................................................................... 596
CD_EMU Overview ....................................................................................................... 598
CD_DSS Overview ....................................................................................................... 600
CD_L4_CFG Overview ................................................................................................... 605
CD_L3_INSTR Overview ................................................................................................ 609
CD_L3_MAIN1 Overview ................................................................................................ 611
CD_EMIF Overview ...................................................................................................... 615
CD_IPU Overview ........................................................................................................ 617
CD_IPU1 Overview ....................................................................................................... 621
CD_IPU2 Overview ....................................................................................................... 624
CD_DMA Overview ....................................................................................................... 627
CD_ATL Overview ........................................................................................................ 629
CD_CAM Overview ....................................................................................................... 631
CD_GMAC Overview ..................................................................................................... 634
CD_VPE Overview ....................................................................................................... 636
CD_RTC Overview ....................................................................................................... 639
CD_PCIE Overview....................................................................................................... 641
PRM Voltage Control Architecture ...................................................................................... 670
SmartReflex Integration .................................................................................................. 671
I/O Pads Daisy-Chain Configuration ................................................................................... 678
DPLL Output-Frequency Change ....................................................................................... 682
MPU Subsystem Overview............................................................................................. 1574
MPU Subsystem Integration ........................................................................................... 1578
MPU Subsystem Clocking Scheme ................................................................................... 1579
MPU Subsystem Reset Scheme ...................................................................................... 1580
MPU Subsystem Block Diagram ...................................................................................... 1582
SPRUIC2D – January 2017 – Revised April 2019
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List of Figures
67
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4-6.
MPU_MA Overview ..................................................................................................... 1587
4-7.
EMIF Partitioning Without High-Order Interleaving ................................................................. 1589
4-8.
EMIF Partitioning With High-Order Interleaving ..................................................................... 1589
4-9.
MPU Subsystem Power Domains Overview ......................................................................... 1598
4-10.
MPU_WUGEN Overview ............................................................................................... 1603
5-1.
DSP Subsystem Highlight .............................................................................................. 1647
5-2.
DSP Subsystem Integration............................................................................................ 1651
5-3.
DSP_SYSTEM Block Diagram ........................................................................................ 1665
5-4.
Extended Duration Sleep Software and Hardware Sequence
5-5.
5-6.
5-7.
7-1.
7-2.
7-3.
7-4.
7-5.
7-6.
7-7.
7-8.
7-9.
8-1.
8-2.
8-3.
8-4.
8-5.
8-6.
8-7.
8-8.
8-9.
8-10.
8-11.
8-12.
8-13.
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8-15.
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8-18.
8-19.
8-20.
8-21.
8-22.
8-23.
8-24.
8-25.
8-26.
8-27.
8-28.
68
....................................................
DSP Subsystem Interrupt Management ..............................................................................
ERRINT Diagram ........................................................................................................
DSP DMA Requests ....................................................................................................
IPUx Subsystem Overview .............................................................................................
IPU1 Subsystem Integration ...........................................................................................
IPU2 Subsystem Integration ...........................................................................................
IPUx Subsystem Clocking Scheme ...................................................................................
IPUx Subsystem Reset Scheme ......................................................................................
IPUx Subsystem Block Diagram ......................................................................................
IPUx_WUGEN Overview ...............................................................................................
SCTM Block Diagram ...................................................................................................
Event Communication Connection in IPUx Subsystem ............................................................
CAMSS Overview .......................................................................................................
CAMSS Environment ...................................................................................................
CAMSS Integration ......................................................................................................
CAL Interrupt Events Mapping to Registers .........................................................................
CSI2 PHY Diagram .....................................................................................................
CSI2 Complex I/O Power FSM ........................................................................................
CSI2 PHY RxMode and StopState FSM .............................................................................
CAL Top-Level Diagram ................................................................................................
CAL Data Pipeline TAGs ...............................................................................................
CSI2 Low Level Protocol Engine Block Diagram ...................................................................
CSI2 One Data-Lane Configuration ...................................................................................
CSI2 Two Data-Lane Merger Configuration .........................................................................
CSI2 Three Data-Lane Merger Configuration .......................................................................
CSI2 Four Data-Lane Merger Configuration .........................................................................
CSI2 Protocol Layer With Short and Long Packets.................................................................
CSI2 Short Packet Structure ...........................................................................................
CSI2 Long Packet Structure ...........................................................................................
CSI2 Data Identifier Structure .........................................................................................
CSI2 Virtual Channel ...................................................................................................
CSI2 General Frame Structure (Informative) ........................................................................
CSI2 Digital Interlaced Video Frame (Informative)..................................................................
CSI-2 LL Tag Generation Example - Line Mode ....................................................................
CSI-2 Packing – Example 1............................................................................................
CSI-2 Packing – Example 2............................................................................................
CSI-2 Packing – Example 3............................................................................................
CSI-2 Packing – Example 4............................................................................................
CAL PPI Interleaving - Physical View ................................................................................
CAL Stream Interleaving - Logical View..............................................................................
List of Figures
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Copyright © 2017–2019, Texas Instruments Incorporated
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8-29.
8-30.
8-31.
8-32.
8-33.
8-34.
8-35.
8-36.
9-1.
9-2.
9-3.
9-4.
9-5.
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9-16.
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9-28.
9-29.
9-30.
9-31.
9-32.
9-33.
9-34.
9-35.
9-36.
9-37.
9-38.
9-39.
9-40.
9-41.
............................................................................................
CAL Interleaver - Example of RAW Bayer Data ....................................................................
CAL MIPI RAW10 Data Packing ......................................................................................
CAL Pixel Packing – Data Storage in Memory ......................................................................
CAL Pixel Packing – Data Storage in Memory ......................................................................
Write DMA - Framing ...................................................................................................
CAL Video Port and Timing Generator ...............................................................................
CAL Registers Shadowing Example ..................................................................................
VIP Overview ............................................................................................................
VIP Environment ........................................................................................................
VIP Integration ...........................................................................................................
VIP Block Diagram ......................................................................................................
VIP Slice Processing Path Block Diagram ...........................................................................
Input: A=RGB, B=YUV422; Output: A=RGB, B=RGB ..............................................................
Input: A=YUV422 8/16, B=YUV422; Output: A=Scaled YUV420, B=RGB ......................................
Input: A=RGB, B=YUV422; Output: A=RGB, B=Scaled YUV420.................................................
Input: A=YUV444, B=YUV422; Output: A=YUV422, A=Scaled YUV422, B=YUV422 .........................
Input: A=YUV444; Output: A=Scaled YUV420, A=YUV420 ......................................................
Input: A=YUV444; Output: A=Scaled YUV420, A=YUV444 .......................................................
Input: A=YUV422 8/16; Output: A=Scaled YUV420, A=YUV444 .................................................
Input: A=YUV422 8/16, B=YUV422; Output: A=Scaled YUV420, B=YUV420 ..................................
Input: A=YUV422 8/16, B=YUV422; Output: A=YUV420, B=YUV420 ...........................................
Bytelane Swapping Modes .............................................................................................
RAW16 to RGB565 Mapping ..........................................................................................
RAW12 Swap ............................................................................................................
NTSC Analog Video Waveform for One Horizontal Line ...........................................................
Digitized Video ...........................................................................................................
Code Word Embedded Video Format ................................................................................
Digitized Video with F, V, and H Flags in EAV/SAV ................................................................
Planar Buffer Storage Description ....................................................................................
8-bit Interface Discrete Sync Pixel Multiplexing .....................................................................
16-bit Interface Discrete Sync Pixel Multiplexing ...................................................................
24b Interface RGB Discrete Sync .....................................................................................
Discrete Sync Signals ..................................................................................................
Type 1, First Horizontal Blanking Pixel ...............................................................................
Type 1, First Vertical Ancillary Data Pixel ............................................................................
Type 1, Horizontal Blanking in Video Region ........................................................................
Type 1, First Video Pixel ...............................................................................................
4-Pin Reduced ACTVID Signaling with Vertical Ancillary Data ...................................................
4-Pin Reduced ACTVID Signaling with No Vertical Ancillary Data ...............................................
4-Pin Reduced HSYNC Signaling with Vertical Ancillary Data ....................................................
VSYNC Pre and Post Window.........................................................................................
VSYNC Equivalence When Using Transition Window .............................................................
FID Registering When Using HSYNC ................................................................................
FID Registering When Using ACTVID ................................................................................
Field ID Determination By VSYNC Skew ............................................................................
Example of 525-line FID Determination By VSYNC Skew.........................................................
Horizontal Ancillary Data Packing When HSYNC Used as Sync Signal .........................................
Interlaced Field Vertical Blanking Ancillary Data Storage..........................................................
CAL Interleave FIFO reads
SPRUIC2D – January 2017 – Revised April 2019
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List of Figures
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9-42.
Progressive Frame Vertical Blanking Ancillary Data Storage ..................................................... 1937
9-43.
Embedded Sync Data Entry ........................................................................................... 1937
9-44.
Code Word Format Example Followed by Video Data ............................................................. 1938
9-45.
Embedded Sync Packing............................................................................................... 1940
9-46.
RGB Frame Storage .................................................................................................... 1941
9-47.
2-Way Multiplexing ...................................................................................................... 1942
9-48.
Example of 4-Way Multiplexing........................................................................................ 1942
9-49.
Example of Line Multiplexing .......................................................................................... 1943
9-50.
8-bit Line Mux Interface
9-51.
9-52.
9-53.
9-54.
9-55.
9-56.
9-57.
9-58.
9-59.
9-60.
9-61.
9-62.
9-63.
9-64.
9-65.
9-66.
9-67.
9-68.
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9-75.
9-76.
9-77.
9-78.
9-79.
9-80.
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9-84.
9-85.
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70
................................................................................................
16-bit Line Mux Interface ...............................................................................................
BOP/EOP Definition of a Period .......................................................................................
Channel ID Inserted Into Horizontal Blanking .......................................................................
Vertical Ancillary Data Cropping.......................................................................................
Active Video Cropping ..................................................................................................
Problematic Error Cropping Case .....................................................................................
Endline/Endframe Behavior for Error Cropping Case ..............................................................
Generic External Sync Signals ........................................................................................
vblnk and hblnk ..........................................................................................................
VBLNK and ACTID (1) ..................................................................................................
VBLNK and ACTVID(2) .................................................................................................
VBLNK and HSYNC ....................................................................................................
VSYNC and HBLNK ....................................................................................................
VSYNC and ACTIVID(1) ...............................................................................................
VSYNC and ACTIVID(2) ...............................................................................................
VSYNC and HSYNC ....................................................................................................
Ancillary and Active Video Line Determination ......................................................................
HSYNC Pixel Capture ..................................................................................................
ACTVID Pixel Capture ..................................................................................................
Matrix Format ............................................................................................................
Conversion from RGB to YCbCr ......................................................................................
Conversion from YCbCr to RGB ......................................................................................
Conversion from RGB to YCbCr ......................................................................................
Conversion from YCbCr to RGB ......................................................................................
Conversion from RGB to YCbCr ......................................................................................
Conversion from YCbCr to RGB ......................................................................................
Conversion from RGB to YCbCr ......................................................................................
Conversion from YCbCr to RGB ......................................................................................
High Level Block Diagram..............................................................................................
SC Block Diagram .......................................................................................................
Input Image Trimming ..................................................................................................
Filter Implementation and Parameter Description...................................................................
Peaking Filter at fs/4 ....................................................................................................
Vertical Scaler Block Diagram .........................................................................................
Horizontal Scaler Block Diagram ......................................................................................
Polyphase Filtering Example ..........................................................................................
Non-linear Scaling Example ...........................................................................................
SRAM Layout for 7tap Coefficient ....................................................................................
SRAM Layout for 5tap Coefficient ....................................................................................
VPI Control I/F Coef Data Format (7tap) .............................................................................
List of Figures
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SPRUIC2D – January 2017 – Revised April 2019
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9-91.
VPI Control I/F Coef Data Format (5tap) ............................................................................. 1977
9-92.
VPI Control I/F Coef Data Format (3tap) ............................................................................. 1977
9-93.
VPI Control I/F Memory Map (Write)
9-94.
VPI Control I/F Memory Map (Read) ................................................................................. 1978
9-95.
Inbound Data Transfer Descriptor Format ........................................................................... 2024
9-96.
Outbound Data Transfer Descriptor Format ......................................................................... 2024
9-97.
Y 4:4:4 (Data Type 0) ................................................................................................... 2041
9-98.
Y 4:2:2 (Data Type 1) ................................................................................................... 2042
9-99.
Y 4:2:0 (Data Type 2) ................................................................................................... 2042
.................................................................................
1977
9-100. C 4:4:4 (Data Type 4)................................................................................................... 2043
9-101. C 4:2:2 (Data Type 5)................................................................................................... 2044
9-102. C 4:2:0 (Data Type 6)................................................................................................... 2044
9-103. YC 4:2:2 (Data Type 7) ................................................................................................. 2045
9-104. YC 4:4:4 (Data Type 8) ................................................................................................. 2045
9-105. CY 4:2:2 (Data Type 23h) .............................................................................................. 2046
9-106. RGB16-565 (Data Type 0) ............................................................................................. 2047
9-107. ARGB-1555 (Data Type 1) ............................................................................................. 2047
9-108. ARGB-4444 (Data Type 2) ............................................................................................. 2048
9-109. RGBA-5551 (Data Type 3) ............................................................................................. 2048
9-110. RGBA-4444 (Data Type 4) ............................................................................................. 2049
9-111. ARGB24-6666 (Data Type 5) .......................................................................................... 2049
9-112. RGB24-888 (Data Type 6) ............................................................................................. 2050
9-113. ARGB32-8888 (Data Type 7) .......................................................................................... 2050
9-114. RGBA24-6666 (Data Type 8) .......................................................................................... 2051
9-115. RGBA32-8888 (Data Type 9) .......................................................................................... 2051
10-1.
VPE Integration .......................................................................................................... 2321
10-2.
VPE Block Diagram ..................................................................................................... 2323
10-3.
Block Diagram of Motion-Adaptive Deinterlacer
10-4.
Motion Detection (MDT) Block Diagram .............................................................................. 2325
10-5.
Motion Detection (MDT) MV Calc Data Path ........................................................................ 2326
10-6.
Motion Detection (MDT) Max Filter Data Path
10-7.
10-8.
10-9.
10-10.
10-11.
10-12.
10-13.
10-14.
10-15.
10-16.
10-17.
10-18.
10-19.
10-20.
10-21.
10-22.
10-23.
10-24.
....................................................................
......................................................................
Motion Detection (MDT) Uniform Area Data Path ..................................................................
Motion Detection (MDT) Detect Motion Data Path ..................................................................
Edge Directed Interpolation (EDI) Block Diagram ..................................................................
Edge Directed Interpolation Edge Vector Calculation ..............................................................
Edge Directed Interpolation Luma Interpolation Calculationn .....................................................
Edge Directed Interpolation Chroma Interpolation Calculation ....................................................
Film Mode Detection (FMD) Block Diagram .........................................................................
Film Mode Detection (FMD) Frame/Field Difference Calculation .................................................
Film Mode Detection (FMD) Combing Artifacts Calculation .......................................................
Film Mode Detection (FMD) Combing Artifacts Data Path ........................................................
Output Data Path ........................................................................................................
High Level Block Diagram..............................................................................................
SC Block Diagram .......................................................................................................
Input Image Trimming ..................................................................................................
Filter Implementation and Parameter Description...................................................................
Peaking Filter at fs/4 ....................................................................................................
Vertical Scaler Block Diagram .........................................................................................
Horizontal Scaler Block Diagram ......................................................................................
SPRUIC2D – January 2017 – Revised April 2019
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List of Figures
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2339
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10-28.
10-29.
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..........................................................................................
Non-linear Scaling Example ...........................................................................................
SRAM Layout for 7tap Coefficient ....................................................................................
SRAM Layout for 5tap Coefficient ....................................................................................
VPI Control I/F Coef Data Format (7tap) .............................................................................
VPI Control I/F Coef Data Format (5tap) .............................................................................
VPI Control I/F Coef Data Format (3tap) .............................................................................
VPI Control I/F Memory Map (Write) .................................................................................
VPI Control I/F Memory Map (Read) .................................................................................
Matrix Format ............................................................................................................
Conversion from RGB to YCbCr ......................................................................................
Conversion from YCbCr to RGB ......................................................................................
Conversion from RGB to YCbCr ......................................................................................
Conversion from YCbCr to RGB ......................................................................................
Conversion from RGB to YCbCr ......................................................................................
Conversion from YCbCr to RGB ......................................................................................
Conversion from RGB to YCbCr ......................................................................................
Conversion from YCbCr to RGB ......................................................................................
4:2:0 YCrCb Color Space with Chroma Left-aligned ...............................................................
4:2:0 YCrCb Color Space with Chroma Left-aligned ...............................................................
4:2:0 YCrCb Color Space with Chroma Left-aligned ...............................................................
Anchor Pixels ............................................................................................................
4:2:0 Interlaced Scan ...................................................................................................
Ideal 4:2:2 Chroma Upsampling for Interlaced Scan ...............................................................
Inbound Data Transfer Descriptor Format ...........................................................................
Outbound Data Transfer Descriptor Format .........................................................................
Y 4:4:4 (Data Type 0) ...................................................................................................
Y 4:2:2 (Data Type 1) ...................................................................................................
Y 4:2:0 (Data Type 2) ...................................................................................................
C 4:4:4 (Data Type 4)...................................................................................................
C 4:2:2 (Data Type 5)...................................................................................................
C 4:2:0 (Data Type 6)...................................................................................................
YC 4:2:2 (Data Type 7) .................................................................................................
YC 4:4:4 (Data Type 8) .................................................................................................
CY 4:2:2 (Data Type 23h) ..............................................................................................
RGB16-565 (Data Type 0) .............................................................................................
ARGB-1555 (Data Type 1) .............................................................................................
ARGB-4444 (Data Type 2) .............................................................................................
RGBA-5551 (Data Type 3) .............................................................................................
RGBA-4444 (Data Type 4) .............................................................................................
ARGB24-6666 (Data Type 5) ..........................................................................................
RGB24-888 (Data Type 6) .............................................................................................
ARGB32-8888 (Data Type 7) ..........................................................................................
RGBA24-6666 (Data Type 8) ..........................................................................................
RGBA32-8888 (Data Type 9) ..........................................................................................
RGB16-565 (Data Type 0) .............................................................................................
ARGB-1555 (Data Type 1) .............................................................................................
ARGB-4444 (Data Type 2) .............................................................................................
RGBA-5551 (Data Type 3) .............................................................................................
10-25. Polyphase Filtering Example
List of Figures
2342
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SPRUIC2D – January 2017 – Revised April 2019
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10-74. RGBA-4444 (Data Type 4) ............................................................................................. 2416
10-75. ARGB24-6666 (Data Type 5) .......................................................................................... 2417
10-76. RGB24-888 (Data Type 6) ............................................................................................. 2417
10-77. ARGB32-8888 (Data Type 7) .......................................................................................... 2418
10-78. RGBA24-6666 (Data Type 8) .......................................................................................... 2418
10-79. RGBA32-8888 (Data Type 9) .......................................................................................... 2419
11-1.
Display Subsystem Overview .......................................................................................... 2619
11-2.
Display Subsystem Environment ...................................................................................... 2620
11-3.
Display Subsystem Integration ........................................................................................ 2623
11-4.
Display Subsystem Clock Tree ........................................................................................ 2624
11-5.
Display Subsystem Reset Scheme ................................................................................... 2626
11-6.
Display Subsystem SIdleAck/MStandby Generation ............................................................... 2628
11-7.
Display Subsystem Wake-Up Generation............................................................................ 2629
11-8.
PLL Controller Overview
11-9.
11-10.
11-11.
11-12.
11-13.
11-14.
11-15.
11-16.
11-17.
11-18.
11-19.
11-20.
11-21.
11-22.
11-23.
11-24.
11-25.
11-26.
11-27.
11-28.
11-29.
11-30.
11-31.
11-32.
11-33.
11-34.
11-35.
11-36.
11-37.
11-38.
11-39.
11-40.
11-41.
11-42.
11-43.
...............................................................................................
OCP2SCP2 Overview ..................................................................................................
VIDEO PLL Reference Diagram.......................................................................................
DPLL_VIDEO Functional Block Diagram ............................................................................
VIDEO PLL Power State Diagram ....................................................................................
VIDEO PLL Programming Sequence .................................................................................
VIDEO PLL Go Sequence (Manual Mode) ..........................................................................
VIDEO PLL Go Sequence (Automatic Mode) .......................................................................
DPLL_HDMI and PLLCTRL_HDMI Overview .......................................................................
DPLL_HDMI and PLLCTRL_HDMI Reference Diagram ...........................................................
DPLL_HDMI Functional Block Diagram ..............................................................................
PLLCTRL_HDMI Power State Diagram ..............................................................................
DPLL_HDMI Programming Sequence ................................................................................
DPLL_HDMI GO Sequence (Manual Mode) .........................................................................
DISPC Overview ........................................................................................................
DISPC LCD Support Parallel Interface ...............................................................................
DISPC LCD Pixel Data Color12 Active Matrix.......................................................................
DISPC LCD Pixel Data Color16 Active Matrix.......................................................................
DISPC LCD Pixel Data Color18 Active Matrix.......................................................................
DISPC LCD Pixel Data Color24 Active Matrix.......................................................................
DISPC Active Matrix Timing Diagram of Configuration 1 (Start of Frame) ......................................
DISPC Active Matrix Timing Diagram of Configuration 1 (Between Lines) ......................................
DISPC Active Matrix Timing Diagram of Configuration 1 (Between Frames) ...................................
DISPC Active Matrix Timing Diagram of Configuration 1 (End of Frame) .......................................
DISPC Active Matrix Timing Diagram of Configuration 2 (Start of Frame) ......................................
DISPC Active Matrix Timing Diagram of Configuration 2 (Between Lines) ......................................
DISPC Active Matrix Timing Diagram of Configuration 2 (Between Frames) ...................................
DISPC Active Matrix Timing Diagram of Configuration 2 (End of Frame) .......................................
DISPC Active Matrix Timing Diagram of Configuration 3 (Start of Frame) ......................................
DISPC Active Matrix Timing Diagram of Configuration 3 (Between Lines) ......................................
DISPC Active Matrix Timing Diagram of Configuration 3 (Between Frames) ...................................
DISPC Active Matrix Timing Diagram of Configuration 3 (End of Frame) .......................................
DISPC TV Output Pixel Data ..........................................................................................
DISPC Integration .......................................................................................................
DISPC Architecture Overview .........................................................................................
DISPC Clock Tree Overview...........................................................................................
SPRUIC2D – January 2017 – Revised April 2019
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Copyright © 2017–2019, Texas Instruments Incorporated
List of Figures
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........................................................................................
YUV4:2:2 Predecimation ...............................................................................................
DISPC 90-Degree Rotation With Mirroring ..........................................................................
DISPC Graphics Pipeline...............................................................................................
DISPC Configuration 1: Video Pipeline ..............................................................................
DISPC Configuration 2: Video Pipeline ..............................................................................
DISPC YCbCr to RGB Registers (FULLRANGE = 0), 8-Bit Outputs .............................................
DISPC YCbCr to RGB Registers (FULLRANGE = 1), 8-Bit Outputs .............................................
DISPC YCbCr to RGB Registers (FULLRANGE = 0), 10-Bit Outputs ...........................................
DISPC YCbCr to RGB Registers (FULLRANGE = 1), 10-Bit Outputs ...........................................
DISPC Averaging of the Chrominance Formula ....................................................................
DISPC Averaging of the Chrominance Representation ............................................................
DISPC YUV4:2:2 to RGB30 Using Averaging of the Chrominance ..............................................
DISPC YUV4:2:0 to RGB30 Using Scaler Unit for Resampling Chrominance ..................................
DISPC YUV4:2:2 to RGB30 Using Scaler Unit for Resampling Chrominance ..................................
DISPC Video Upsampling ..............................................................................................
11-44. DISPC DMA Engine Overview
11-45.
11-46.
11-47.
11-48.
11-49.
11-50.
11-51.
11-52.
11-53.
11-54.
11-55.
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2696
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2717
11-60. DISPC Macro-Architecture of the Horizontal Scaling for A, R, G, B, and Y Components (5-tap
Restriction) ............................................................................................................... 2719
11-61. DISPC Macro-Architecture of the Vertical Scaling for A, R, G, B, and Y Components (5 and 3 taps)
......
2719
11-62. DISPC Macro-Architecture of the Horizontal Scaling for Cr and Cb Components (5-tap Restriction) ....... 2719
11-63. DISPC Macro-Architecture of the Vertical Scaling for Cr and Cb Components (5 and 3 taps) ............... 2720
11-64. DISPC Vertical Upsampling and Downsampling Algorithm ........................................................ 2723
11-65. DISPC Horizontal Up/Downsampling Algorithm ..................................................................... 2724
11-66. DISPC Write-Back Pipeline ............................................................................................ 2725
2726
11-68. DISPC RGB to YCbCr (FULLRANGE = 1)
2726
11-69.
2727
11-70.
11-71.
11-72.
11-73.
11-74.
11-75.
11-76.
11-77.
11-78.
11-79.
11-80.
11-81.
11-82.
11-83.
11-84.
11-85.
11-86.
11-87.
11-88.
11-89.
11-90.
11-91.
74
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..........................................................................
DISPC Macro-Architecture of the Vertical Scaling for A, R, G, B, and Y Components ........................
DISPC Macro-Architecture of the Horizontal Scaling for A, R, G, B, and Y Components .....................
DISPC Macro-Architecture of the Vertical Scaling for Cr and Cb Components.................................
DISPC Macro-Architecture of the Horizontal Scaling for Cr and Cb Components .............................
DISPC LCD Output Architecture ......................................................................................
DISPC Priority Rule Architecture ......................................................................................
DISPC Example of Priority Rule: From Lower to Higher VID1, VID2, VID3, GFX ..............................
DISPC Alpha Blending Architecture With Premultiplied Alpha Support ..........................................
DISPC Source Transparency Color Key Example ..................................................................
DISPC Destination Transparency Color Key Example .............................................................
DISPC LCD1 Gamma Correction Architecture ......................................................................
DISPC Data Memory Organization for Gamma Mode in LCD Output ...........................................
DISPC CPR Matrix ......................................................................................................
DISPC CPR Macro-Architecture ......................................................................................
DISPC RGB to YUV Registers (FullRange=0) ......................................................................
DISPC RGB to YUV Registers (FullRange=1) ......................................................................
DISPC Signal Mapping in BT.656 Mode .............................................................................
DISPC Signal Mapping in BT.1120 Mode............................................................................
Bit-assignment for the fourth byte of EAV/SAV codes .............................................................
DISPC 8-Bit Interface Settings ........................................................................................
DISPC 9-Bit Interface Settings ........................................................................................
DISPC 12-Bit Interface Settings .......................................................................................
DISPC 16-Bit Interface Settings .......................................................................................
11-67. DISPC RGB to YCbCr (FULLRANGE = 0)
List of Figures
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SPRUIC2D – January 2017 – Revised April 2019
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Copyright © 2017–2019, Texas Instruments Incorporated
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11-92. DISPC Timing Values (Active Matrix Display) ....................................................................... 2754
11-93. DISPC TV Output Architecture ........................................................................................ 2755
.............................................
.................................................................................
11-96. DISPC Frame Width Control ...........................................................................................
11-97. DISPC Illustration of 3D Interleaving .................................................................................
11-98. DISPC Illustration of a Non-zero Position of 3D Window ..........................................................
11-99. DISPC Illustration of DLP 3D Format .................................................................................
11-100. DISPC GFX Pipeline Processing Configuration ...................................................................
11-101. DISPC Video Pipeline Processing Configuration ..................................................................
11-102. DISPC Scaler Unit Programming Flow..............................................................................
11-103. HDMI Overview ........................................................................................................
12-1. GPU Overview ...........................................................................................................
12-2. GPU Integration .........................................................................................................
12-3. GPU Block Diagram.....................................................................................................
13-1. BB2D Overview ..........................................................................................................
13-2. BB2D Integration ........................................................................................................
13-3. BB2D Block Diagram ...................................................................................................
14-1. Interconnect Overview ..................................................................................................
14-2. L3_MAIN Interconnect Overview ......................................................................................
14-3. Connectivity Matrix ......................................................................................................
14-4. Bandwidth Regulator Pressure Settings..............................................................................
14-5. Flag Mux Structure ......................................................................................................
14-6. L3 Interconnect Region Overlay and Priority Level Overview .....................................................
14-7. L3_MAIN Global Error-Routing Scheme .............................................................................
14-8. Typical Error Analysis Sequence ......................................................................................
14-9. L4 Interconnect Overview ..............................................................................................
14-10. L4 Initiator-Target Connectivity ........................................................................................
14-11. Example of CONNID_BIT_VECTOR L4_AP_PROT_GROUP_MEMBERS_k ..................................
14-12. L4 Segmentation ........................................................................................................
14-13. L4 Error Reporting ......................................................................................................
14-14. Protection Violation Out-of-Band Error Reporting ...................................................................
14-15. Typical Error Analysis Sequence ......................................................................................
15-1. Memory Subsystem Functional Diagram .............................................................................
15-2. DMM and Tiler Overview ...............................................................................................
15-3. DMM Integration .........................................................................................................
15-4. DMM Block Diagram ....................................................................................................
15-5. DMM Sections and Memory Mapping ................................................................................
15-6. PAT Direct Access Translation ........................................................................................
15-7. PAT Indirect Access Translation ......................................................................................
15-8. Physical Address Translation Table ..................................................................................
15-9. PAT Descriptors .........................................................................................................
15-10. TILER Address Space Structure for Tiled Modes ...................................................................
15-11. TILER Object Containers and Views .................................................................................
15-12. TILER Memory Footprint With PAT and Shared Physical Address Translation LUT ..........................
15-13. Object Container Geometry With 4-kiB Pages ......................................................................
15-14. TILER Page Mapping When Using 4-kiB Pages ....................................................................
15-15. Isometric Transforms in the TILER Container .......................................................................
15-16. Tile Geometry ............................................................................................................
11-94. DISPC Data Memory Organization for Gamma Mode in TV Output
2755
11-95. DISPC Example Timing TV Formats
2756
SPRUIC2D – January 2017 – Revised April 2019
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Copyright © 2017–2019, Texas Instruments Incorporated
List of Figures
2758
2759
2760
2761
2772
2774
2776
2956
2960
2962
2964
2984
2986
2988
3035
3038
3045
3047
3050
3058
3066
3070
3209
3216
3218
3222
3233
3234
3236
3301
3306
3307
3310
3313
3315
3316
3317
3319
3322
3325
3325
3326
3326
3327
3328
75
www.ti.com
.........................................................................................................
Page Mode Virtual Addressing ........................................................................................
Tiled Mode Addressing in 0- or 180-Degree Orientation (S = 0)..................................................
Tiled Mode Addressing in 90- or 270-Degree Orientation (S = 1) ................................................
Tiled Mode Ordering of Elements in Natural View ..................................................................
Page Mode Ordering of Elements in Natural View .................................................................
Tiled Mode Ordering of Elements in 0-Degree View With Vertical Mirror .......................................
Page Mode Ordering of Elements in 0-Degree View With Vertical Mirror .......................................
Tiled Mode Ordering of Elements in 0-Degree View With Horizontal Mirror ....................................
Page Mode Ordering of Elements in 0-Degree View With Horizontal Mirror ....................................
Tiled Mode Ordering of Elements in 180-Degree View ............................................................
Page Mode Ordering of Elements in 180-Degree View ............................................................
Tiled Mode Ordering of Elements in 90-Degree View With Vertical Mirror ......................................
Page Mode Ordering of Elements in 90-Degree View With Vertical Mirror......................................
Tiled Mode Ordering of Elements in 270-Degree View ............................................................
Page Mode Ordering of Elements in 270-Degree View ............................................................
Tiled Mode Ordering of Elements in 90-Degree View ..............................................................
Page Mode Ordering of Elements in 90-Degree View .............................................................
Tiled Mode Ordering of Elements in 90-Degree View With Horizontal Mirror ...................................
Page Mode Ordering of Elements in 90-Degree View With Horizontal Mirror ..................................
TILER Port Address Map ...............................................................................................
TILER Aliased View Orientation .......................................................................................
Simple Manual Area Refill Scheme ...................................................................................
Single Auto-Configured Area Refill Scheme .........................................................................
Chained Auto-Configured Area Refill Scheme ......................................................................
Synchronized Auto-Configured Area Refill Scheme ................................................................
Cyclic Synchronized Auto-Configured Area Refill Scheme ........................................................
Example of 8-Bit Frame-Buffer Addressing in any Orientation ....................................................
EMIF Controller Overview ..............................................................................................
EMIF DDR3/DDR3L Configuration Without ECC ...................................................................
EMIF DDR3/DDR3L Configuration With ECC .......................................................................
EMIF Module Integration ...............................................................................................
EMIF Block Diagram ....................................................................................................
FIFO Block Diagram ....................................................................................................
Example for Using the CKE Tri-state Functionality .................................................................
GPMC Overview .........................................................................................................
GPMC to 16-Bit Address/Data-Multiplexed Memory................................................................
GPMC to 16-Bit Nonmultiplexed Memory ............................................................................
GPMC to 8-Bit Nonmultiplexed Memory .............................................................................
GPMC to 8-Bit NAND Device ..........................................................................................
GPMC Integration .......................................................................................................
GPMC Block Diagram ..................................................................................................
Chip-Select Address Mapping and Decoding Mask ................................................................
Wait Behavior During an Asynchronous Single Read Access (GPMCFCLKDivider = 1) ......................
Wait Behavior During a Synchronous Read Burst Access ........................................................
15-17. Subtile Mapping
3329
15-18.
3330
15-19.
15-20.
15-21.
15-22.
15-23.
15-24.
15-25.
15-26.
15-27.
15-28.
15-29.
15-30.
15-31.
15-32.
15-33.
15-34.
15-35.
15-36.
15-37.
15-38.
15-39.
15-40.
15-41.
15-42.
15-43.
15-44.
15-45.
15-46.
15-47.
15-48.
15-49.
15-50.
15-51.
15-52.
15-53.
15-54.
15-55.
15-56.
15-57.
15-58.
15-59.
15-60.
15-61.
3331
3331
3332
3332
3333
3333
3334
3334
3335
3335
3336
3336
3337
3337
3338
3338
3339
3339
3340
3341
3344
3345
3346
3347
3348
3353
3395
3396
3397
3400
3403
3404
3425
3539
3540
3540
3541
3541
3544
3548
3554
3557
3559
15-62. Read-to-Read for an Address-Data Multiplexed Device, on Different Chip-Select, Without Bus
Turnaround (nCS Attached to a Fast Device) ....................................................................... 3561
15-63. Read- to-Read/Write for an Address-Data Multiplexed Device, on Different Chip-Select, With Bus
Turnaround ............................................................................................................... 3561
76
List of Figures
SPRUIC2D – January 2017 – Revised April 2019
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15-64. Read-to-Read/Write for a Address-Data or AAD-Multiplexed Device, on Same Chip-Select, With Bus
Turnaround ............................................................................................................... 3562
15-65. Asynchronous Single Read on an Address/Data-Multiplexed Device ............................................ 3571
15-66. Two Asynchronous Single-Read Accesses on an Address/Data-Multiplexed Device (32-Bit Read Split
Into 2 x 16-Bit Read) .................................................................................................... 3572
15-67. Asynchronous Single-Write on an Address/Data-Multiplexed Device ............................................ 3573
15-68. Asynchronous Single Read on an AAD-Multiplexed Device....................................................... 3575
15-69. Asynchronous Single Write on an AAD-Multiplexed Device ....................................................... 3576
15-70. Synchronous Single Read (GPMCFCLKDIVIDER = 0) ............................................................ 3578
15-71. Synchronous Single Read (GPMCFCLKDIVIDER = 1) ............................................................ 3579
15-72. Synchronous Multiple (Burst) Read (GPMCFCLKDIVIDER = 0).................................................. 3581
15-73. Synchronous Multiple (Burst) Read (GPMCFCLKDIVIDER = 1).................................................. 3582
15-74. Synchronous Single Write on an Address/Data-Multiplexed Device ............................................. 3583
15-75. Synchronous Multiple Write (Burst Write) in Address/Data-Multiplexed Mode .................................. 3584
15-76. Synchronous Multiple Write (Burst Write) in Address/Address/Data-Multiplexed Mode ....................... 3585
15-77. Asynchronous Single Read on an Address/Data-Nonmultiplexed Device ....................................... 3587
15-78. Asynchronous Single Write on an Address/Data-Nonmultiplexed Device ....................................... 3588
15-79. Asynchronous Multiple (Page Mode) Read .......................................................................... 3589
15-80. NAND Command Latch Cycle ......................................................................................... 3594
15-81. NAND Address Latch Cycle
...........................................................................................
3595
15-82. NAND Data Read Cycle ................................................................................................ 3596
15-83. NAND Data Write Cycle ................................................................................................ 3596
......................................................................
15-85. Hamming Code Accumulation Algorithm (2/2) ......................................................................
15-86. ECC Computation for a 256-Byte Data Stream (Read or Write) ..................................................
15-87. ECC Computation for a 512-Byte Data Stream (Read or Write) ..................................................
15-88. 128 Word16 ECC Computation .......................................................................................
15-89. 256 Word16 ECC Computation .......................................................................................
15-90. Manual Mode Sequence and Mapping ...............................................................................
15-91. NAND Page Mapping and ECC: Per-Sector Schemes.............................................................
15-92. NAND Page Mapping and ECC: Pooled Spare Schemes .........................................................
15-93. NAND Page Mapping and ECC: Per-Sector Schemes, With Separate ECC ...................................
15-94. NAND Read Cycle Optimization Timing Description ...............................................................
15-95. Programming Model Top-Level Diagram .............................................................................
15-96. NOR Interfacing Timing Parameters Diagram .......................................................................
15-97. NAND Command Latch Cycle Timing Simplified Example ........................................................
15-98. Synchronous NOR Single Read Simplified Example ...............................................................
15-99. Asynchronous NOR Single Write Simplified Example ..............................................................
15-100. GPMC Connection to an External NOR Flash Memory...........................................................
15-101. Synchronous Burst Read Access (Timing Parameters in Clock Cycles) .......................................
15-102. Asynchronous Single Read Access (Timing Parameters in Clock Cycles) ....................................
15-103. Asynchronous Single Write Access (Timing Parameters in Clock Cycles).....................................
15-104. ELM Overview ..........................................................................................................
15-105. ELM Integration ........................................................................................................
15-106. OCMC_RAM1 Overview ..............................................................................................
15-107. OCMC_RAM1 Integration .............................................................................................
15-108. OCMC Block Diagram .................................................................................................
15-109. VBUF to CBUF Address Mapping ...................................................................................
16-1. DMA_SYSTEM Overview ..............................................................................................
15-84. Hamming Code Accumulation Algorithm (1/2)
SPRUIC2D – January 2017 – Revised April 2019
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List of Figures
3601
3602
3602
3603
3604
3604
3609
3613
3614
3615
3622
3624
3629
3633
3639
3641
3643
3645
3646
3647
3685
3686
3714
3715
3716
3725
3766
77
www.ti.com
16-2.
Example of External DMA Requests Use ............................................................................ 3767
16-3.
Transition-Sensitive DMA Request Scheme ......................................................................... 3768
16-4.
DMA_SYSTEM Controller Integration ................................................................................ 3770
16-5.
DMA_SYSTEM Controller Top-Level Block Diagram
16-6.
16-7.
16-8.
16-9.
16-10.
16-11.
16-12.
16-13.
16-14.
16-15.
16-16.
16-17.
16-18.
16-19.
16-20.
16-21.
16-22.
16-23.
16-24.
16-25.
16-26.
16-27.
16-28.
16-29.
16-30.
16-31.
16-32.
16-33.
16-34.
16-35.
16-36.
16-37.
16-38.
16-39.
16-40.
16-41.
16-42.
16-43.
16-44.
16-45.
16-46.
16-47.
16-48.
16-49.
16-50.
78
..............................................................
Example Showing Double-Index Addressing, Elements, Frames, and Strides .................................
Addressing Mode Example (a) ........................................................................................
Addressing Mode Example (b) ........................................................................................
Addressing Mode Example (c) ........................................................................................
Example of a 90-Degree Clockwise Image Rotation ...............................................................
2-D Graphic Transparent Color Block Diagram .....................................................................
EDMA module Overview ...............................................................................................
Example of External DMA Requests Use ............................................................................
EDMA Controller Integration ...........................................................................................
EDMA Controller Block Diagram ......................................................................................
EDMA Channel Controller Block Diagram ...........................................................................
TPTC Block Diagram ...................................................................................................
Definition of ACNT, BCNT, and CCNT ..............................................................................
A-Synchronized Transfers (ACNT = n, BCNT = 4, CCNT = 3)....................................................
AB-Synchronized Transfers (ACNT = n, BCNT = 4, CCNT = 3) ..................................................
PaRAM Set ...............................................................................................................
Linked Transfer ..........................................................................................................
Link-to-Self Transfer ....................................................................................................
DMA Channel and QDMA Channel to PaRAM Mapping...........................................................
QDMA Channel to PaRAM Mapping .................................................................................
Shadow Region Registers .............................................................................................
Interrupt Diagram ........................................................................................................
Error Interrupt Operation ...............................................................................................
PaRAM Set Content for Proxy Memory Protection Example ......................................................
Channel Options Parameter (OPT) Example ........................................................................
Proxy Memory Protection Example ...................................................................................
EDMA Prioritization .....................................................................................................
Block Move Example ...................................................................................................
Block Move Example PaRAM Configuration.........................................................................
Subframe Extraction Transfer .........................................................................................
Subframe Extraction Example PaRAM Configuration ..............................................................
Data Sorting Example ..................................................................................................
Data Sorting Example PaRAM Configuration .......................................................................
Servicing Incoming McASP Data Example ..........................................................................
Servicing Incoming McASP Data Example PaRAM Configuration ...............................................
Servicing Peripheral Burst Example ..................................................................................
Servicing Peripheral Burst Example PaRAM Configuration .......................................................
Servicing Continuous McASP Data Example ........................................................................
Servicing Continuous McASP Data Example PaRAM Configuration .............................................
Servicing Continuous McASP Data Example Reload PaRAM Configuration ...................................
Ping-Pong Buffering for McASP Data Example ....................................................................
Ping-Pong Buffering for McASP Example PaRAM Configuration.................................................
Ping-Pong Buffering for McASP Example Pong PaRAM Configuration .........................................
Ping-Pong Buffering for McASP Example Ping PaRAM Configuration ..........................................
Intermediate Transfer Completion Chaining Example ..............................................................
List of Figures
3786
3792
3792
3792
3793
3794
3801
3849
3852
3854
3862
3863
3864
3866
3866
3867
3869
3877
3878
3884
3885
3886
3891
3895
3900
3900
3901
3907
3910
3911
3912
3912
3913
3914
3915
3916
3917
3918
3919
3920
3921
3922
3924
3925
3925
3927
SPRUIC2D – January 2017 – Revised April 2019
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16-51. Single Large Block Transfer Example ................................................................................ 3928
16-52. Smaller Packet Data Transfers Example............................................................................. 3928
....................................................................................
17-1.
Interrupt Controllers in the Device
17-2.
Interrupts From External Devices ..................................................................................... 4090
18-1.
Control Module Overview Block Diagram ............................................................................ 4131
18-2.
Control Module Environment
18-3.
18-4.
18-5.
18-6.
18-7.
18-8.
18-9.
18-10.
18-11.
18-12.
18-13.
18-14.
18-15.
19-1.
19-2.
19-3.
19-4.
19-5.
20-1.
20-2.
20-3.
20-4.
20-5.
20-6.
20-7.
20-8.
20-9.
20-10.
20-11.
20-12.
20-13.
20-14.
20-15.
20-16.
20-17.
21-1.
21-2.
21-3.
21-4.
22-1.
22-2.
22-3.
22-4.
..........................................................................................
Control Module Integration .............................................................................................
Pad Configuration Register Bits .......................................................................................
Multiplexing Scheme of the Pads Having Capability for Additional Signal Mapping ...........................
Thermal Management Functional Block Diagram ...................................................................
Behavior Of The Thermal Alert Logic .................................................................................
Behavior Of The Thermal Shutdown Logic ..........................................................................
PBIAS Cell And Its Connections ......................................................................................
IRQ_CROSSBAR Module Functional Diagram .....................................................................
DMA_CROSSBAR Module Functional Diagram ....................................................................
Vref-Generation Cells and Their Controls ............................................................................
AVS Class 0 Procedure ................................................................................................
Combined Firewall Error Interrupt .....................................................................................
IODELAYCONFIG Integration .........................................................................................
MAILBOX1 Integration ..................................................................................................
MAILBOX2..13 Integration .............................................................................................
IVA Mailbox Integration .................................................................................................
Mailbox Block Diagram .................................................................................................
Example of Communication ............................................................................................
System MMU1 Overview ...............................................................................................
System MMU2 Overview ...............................................................................................
System MMU1 Integration .............................................................................................
System MMU2 Integration .............................................................................................
MMU Block Diagram ....................................................................................................
Translation Process .....................................................................................................
Translation Hierarchy ...................................................................................................
First-level Descriptor Address Calculation ...........................................................................
Detailed First-Level Descriptor Address Calculation................................................................
Section Translation Summary .........................................................................................
Supersection Translation Summary...................................................................................
Two-Level Translation ..................................................................................................
Small Page Translation Summary ....................................................................................
Large Page Translation Summary ....................................................................................
TLB Entry Lock Mechanism ............................................................................................
TLB Entry Structure .....................................................................................................
MMU Global Initialization ...............................................................................................
Spinlock Overview.......................................................................................................
Spinlock Integration .....................................................................................................
Lock Register State Diagram ..........................................................................................
Take and Release Spinlock ............................................................................................
Timers Overview ........................................................................................................
GP Timers Overview ....................................................................................................
GP Timers External System Interface ................................................................................
GP Timer Integration ....................................................................................................
SPRUIC2D – January 2017 – Revised April 2019
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Copyright © 2017–2019, Texas Instruments Incorporated
List of Figures
4089
4132
4133
4136
4146
4151
4153
4154
4160
4165
4169
4175
4178
4180
4867
5350
5350
5353
5356
5360
5387
5388
5389
5389
5391
5392
5393
5393
5394
5395
5396
5397
5398
5399
5400
5401
5404
5428
5429
5431
5433
5440
5441
5443
5445
79
www.ti.com
22-5.
Block Diagram of TIMER3 Through TIMER9 and TIMER11 Through TIMER16 ............................... 5450
22-6.
Block Diagram of TIMER1, TIMER2 and TIMER10
22-7.
Wake-Up Request Generation......................................................................................... 5453
22-8.
Wake-Up Request Generation......................................................................................... 5454
22-9.
TCRR Timing Value ..................................................................................................... 5455
................................................................
5451
22-10. Block Diagram of the 1-ms Tick Module ............................................................................. 5456
22-11. Capture Wave Example for TCLR[13] CAPT_MODE = 0.......................................................... 5458
22-12. Capture Wave Example for TCLR[13] CAPT_MODE = 1.......................................................... 5459
5460
22-14.
5461
22-15.
22-16.
22-17.
22-18.
22-19.
22-20.
22-21.
23-1.
23-2.
23-3.
23-4.
23-5.
23-6.
23-7.
24-1.
24-2.
24-3.
24-4.
24-5.
24-6.
24-7.
24-8.
24-9.
24-10.
24-11.
24-12.
24-13.
24-14.
24-15.
24-16.
24-17.
24-18.
24-19.
24-20.
24-21.
24-22.
24-23.
24-24.
24-25.
80
..........................................................
Timing Diagram of PWM With TCLR[7] SCPWM Bit = 1 ..........................................................
32-kHz Synchronized Timer Block Diagram .........................................................................
Reset Resynchronization Timing Diagram ...........................................................................
CONTER_32K Block Diagram .........................................................................................
Watchdog Timer Block Diagram.......................................................................................
Watchdog Timer Integration ...........................................................................................
32-Bit Watchdog Timer Functional Block Diagram .................................................................
Watchdog Timers General Functional View .........................................................................
RTC Block Diagram .....................................................................................................
RTC External Signals ...................................................................................................
RTC Module Integration ................................................................................................
RTC Functional Block Diagram........................................................................................
Kick Register State Machine Diagram ................................................................................
Flow Control for Updating RTC Registers ...........................................................................
Compensation Illustration ..............................................................................................
HS I2C Controllers .......................................................................................................
HS I2C and Typical Connections to I2C Devices ....................................................................
HS I2C Interface Signals ................................................................................................
HS I2C Data Transfer ...................................................................................................
HS I2C Bit Transfer on the I2C Bus ....................................................................................
HS I2C S and P Condition Events .....................................................................................
HS I2C Data Transfer Formats in F/S Mode .........................................................................
HS I2C Data Transfer in HS Mode ....................................................................................
HS I2C Arbitration Between Master Transmitters ...................................................................
HS I2C Clock Generators Synchronization ...........................................................................
HS I2C Integration .......................................................................................................
HS I2C Block Diagram ..................................................................................................
HS I2C Clock Generation ...............................................................................................
HS I2C Receive FIFO Interrupt Request Generation ...............................................................
HS I2C Transmit FIFO Interrupt Request Generation...............................................................
HS I2C Receive FIFO DMA Request Generation ...................................................................
HS I2C Transmit FIFO Request Generation (High Threshold) ....................................................
HS I2C Transmit FIFO Request Generation (Low Threshold) .....................................................
HS I2C Setup Procedure................................................................................................
HS I2C Master Transmitter Mode, Polling Method, in F/S and HS Modes .......................................
HS I2C Master Receiver Mode, Polling Method, in F/S and HS Modes ..........................................
HS I2C Master Transmitter Mode, Interrupt Method, in F/S and HS Modes .....................................
HS I2C Master Receiver Mode, Interrupt Method, in F/S and HS Modes ........................................
HS I2C Master Transmitter Mode, DMA Method in F/S and HS Modes..........................................
HS I2C Master Receiver Mode, DMA Method in F/S and HS Modes.............................................
22-13. Timing Diagram of PWM With TCLR[7] SCPWM Bit = 0
List of Figures
5497
5499
5499
5504
5506
5509
5510
5532
5534
5535
5537
5540
5542
5543
5570
5572
5572
5573
5574
5574
5575
5575
5576
5577
5578
5582
5583
5588
5588
5589
5590
5590
5596
5597
5599
5600
5602
5604
5606
SPRUIC2D – January 2017 – Revised April 2019
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Copyright © 2017–2019, Texas Instruments Incorporated
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24-26. HS I2C Slave Transmitter/Receiver Mode, Polling .................................................................. 5607
24-27. HS I2C Slave Transmitter/Receiver Mode, Interrupt ................................................................ 5608
24-28. HDQ1W Overview ....................................................................................................... 5642
24-29. HDQ1W Typical Application System Overview...................................................................... 5643
24-30. HDQ Break-Pulse Timing Diagram
...................................................................................
5644
24-31. 1-Wire (SDQ) Reset Timing Diagram ................................................................................. 5644
24-32. HDQ1W Transmitted Bit Timing ....................................................................................... 5645
24-33. HDQ/1-Wire Communication Sequence.............................................................................. 5645
24-34. HDQ1W Integration ..................................................................................................... 5646
24-35. HDQ1W Block Diagram ................................................................................................ 5648
........................................................................................
UART Overview .........................................................................................................
UART Mode Bus System Overview...................................................................................
UART Frame Data Format .............................................................................................
IrDA System Overview..................................................................................................
IrDA SIR Frame Format ................................................................................................
IrDA SIR Encoding Mechanism .......................................................................................
IrDA SIR Decoding Mechanism .......................................................................................
SIR FF Mode .............................................................................................................
MIR Transmit Frame Format...........................................................................................
MIR Baud Rate Adjustment Mechanism .............................................................................
SIP ........................................................................................................................
FIR Transmit Frame Format ...........................................................................................
CIR System Overview ..................................................................................................
CIR Pulse Modulation...................................................................................................
CIR Modulation Duty Cycle ............................................................................................
RC-5 Bit Encoding ......................................................................................................
SIRC Bit Encoding ......................................................................................................
RC-5 Standard Packet Format ........................................................................................
SIRC Packet Format ....................................................................................................
SIRC Bit Transmission Example ......................................................................................
UART/IrDA/CIR Integration ............................................................................................
UART/IrDA/CIR Functional Block Diagram ..........................................................................
FIFO Management Registers ..........................................................................................
RX FIFO Interrupt Request Generation ..............................................................................
TX FIFO Interrupt Request Generation ..............................................................................
Receive FIFO DMA Request Generation (32 Characters) .........................................................
Transmit FIFO DMA Request Generation (56 Spaces) ............................................................
Transmit FIFO DMA Request Generation (8 Spaces)..............................................................
Transmit FIFO DMA Request Generation (1 Space) ...............................................................
24-36. Protocol Registers Description
24-37.
24-38.
24-39.
24-40.
24-41.
24-42.
24-43.
24-44.
24-45.
24-46.
24-47.
24-48.
24-49.
24-50.
24-51.
24-52.
24-53.
24-54.
24-55.
24-56.
24-57.
24-58.
24-59.
24-60.
24-61.
24-62.
24-63.
24-64.
24-65.
5649
5663
5665
5667
5667
5669
5670
5670
5671
5672
5673
5673
5673
5675
5676
5676
5677
5678
5678
5678
5679
5680
5685
5690
5692
5693
5695
5696
5697
5697
24-66. Transmit FIFO DMA Request Generation Using Direct TX DMA Threshold Programming. (Threshold = 3;
Spaces = 8) .............................................................................................................. 5698
24-67. DMA Transmission ...................................................................................................... 5698
24-68. DMA Reception .......................................................................................................... 5699
24-69. Baud Rate Generation .................................................................................................. 5705
24-70. Baud Rate Generator ................................................................................................... 5712
24-71. CIR Mode Block Components ......................................................................................... 5716
.............................................................................................
McSPI Interface Signals in Master Mode ............................................................................
24-72. Multichannel SPI Modules
5783
24-73.
5784
SPRUIC2D – January 2017 – Revised April 2019
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List of Figures
81
www.ti.com
24-74. McSPI Interface Signals in Slave Mode .............................................................................. 5785
24-75. Phase and Polarity Combinations ..................................................................................... 5787
24-76. Full-Duplex Transfer Format With PHA = 0 .......................................................................... 5788
24-77. Extended SPI Transfer With a Start-Bit (SBE = 1).................................................................. 5789
24-78. McSPI Master Mode (Full Duplex) .................................................................................... 5789
24-79. McSPI Master Single Mode (Receive Only) ......................................................................... 5790
24-80. McSPI Slave Mode (Full Duplex)...................................................................................... 5790
24-81. McSPI Slave Single Mode (Transmit Only) .......................................................................... 5791
24-82. McSPI Integration ....................................................................................................... 5792
24-83. McSPI Block Diagram
..................................................................................................
5797
24-84. SPI Full-Duplex Transmission (Example) ............................................................................ 5799
..................
....................
24-87. CS (SPIEN) Timing Controls...........................................................................................
24-88. Example of McSPI Slave With One Master and Multiple Slave Devices on Channel 0 .......................
24-89. SPI Half-Duplex Transmission (Transmit-Only Slave)..............................................................
24-90. SPI Half-Duplex Transmission (Receive-Only Slave) ..............................................................
24-91. Buffer Used in Transmit Direction Only ..............................................................................
24-92. Buffer Used in Receive Direction Only ...............................................................................
24-93. Buffer Used for Transmit and Receive Directions...................................................................
24-94. Buffer Almost Full Level (AFL).........................................................................................
24-95. Buffer Almost Empty Level (AEL) .....................................................................................
24-96. FIFO Mode Transmit-and-Receive With Word Count (Master) ...................................................
24-97. FIFO Mode Transmit-and-Receive Without Word Count (Master) ................................................
24-98. FIFO Mode Transmit-Only (Master) ..................................................................................
24-99. FIFO Mode Receive-Only With Word Count (Master) ..............................................................
24-100. FIFO Mode Receive-Only Without Word Count (Master) .........................................................
24-101. QSPI Overview .........................................................................................................
24-102. QSPI Connected to an External Quad-SPI Flash Memory .......................................................
24-103. QSPI Integration .......................................................................................................
24-104. QSPI Block Diagram...................................................................................................
24-105. SPI_CLKGEN Block ...................................................................................................
24-106. SPI Clock Modes.......................................................................................................
24-107. Logical Representation of the QSPI Interrupt Generation Scheme .............................................
24-108. McASP Modules Overview ...........................................................................................
24-109. McASP Environment ..................................................................................................
24-110. Definition of Bit, Word, and Slot ......................................................................................
24-111. Bit Order and Word Alignment Within a Slot Examples ..........................................................
24-112. Definition of Frame and Frame-Sync Width ........................................................................
24-113. TDM Format - 6 channel example ..................................................................................
24-114. I2S Format Overview ..................................................................................................
24-115. Biphase-Mark Code ...................................................................................................
24-116. S/PDIF Subframe Format .............................................................................................
24-117. S/PDIF Frame Format .................................................................................................
24-118. McASP Integration .....................................................................................................
24-119. McASP Module Block Diagram ......................................................................................
24-120. Transmit Clock Generator Block Diagram ..........................................................................
24-121. Receive Clock Generator Block Diagram ...........................................................................
24-122. Frame Sync Generator Block Diagram .............................................................................
82
24-85. Continuous Transfers With SPIEN[x] Maintained Active (Single-Data-Pin Interface Mode)
5801
24-86. Continuous Transfers With SPIEN[x] Maintained Active (Dual-Data-Pin Interface Mode)
5801
List of Figures
5802
5805
5807
5808
5809
5809
5809
5810
5811
5826
5827
5828
5829
5830
5857
5858
5860
5861
5865
5866
5867
5888
5891
5896
5897
5898
5899
5900
5901
5902
5902
5904
5910
5912
5913
5914
SPRUIC2D – January 2017 – Revised April 2019
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Copyright © 2017–2019, Texas Instruments Incorporated
www.ti.com
24-123. Individual Serializer and Connections Within McASP ............................................................. 5916
24-124. Transmit Format Unit .................................................................................................. 5918
24-125. Receive Format Unit ................................................................................................... 5921
24-126. Burst Frame Sync Mode .............................................................................................. 5924
24-127. Transmit DMA Event (AXEVT) Generation in TDM Time Slots .................................................. 5926
24-128. MPU Service Time Upon Transmit DMA Event (AXEVT) ........................................................ 5931
24-129. CPU Service Time Upon Receive Event (AREVT) ................................................................ 5932
24-130. DMA Transmit and Receive Event in an Audio Example – One Event ......................................... 5935
24-131. McASP Audio FIFO (AFIFO) Block Diagram ....................................................................... 5936
24-132. McASP Serializers Operation in Loopback Mode
.................................................................
5941
24-133. Transmit Clock Failure Detection Circuit Block Diagram ......................................................... 5945
24-134. Receive Clock Failure Detection Circuit Block Diagram .......................................................... 5946
................................................................
...................................................
McASP Polling Reception Method ...................................................................................
Subsequence – TDM - Reception Startup Procedure.............................................................
McASP Transmit Interrupt Events Servicing .......................................................................
McASP Receive Interrupt Events Servicing ........................................................................
McASP Transmit Error Handling .....................................................................................
McASP Receive Error Handling......................................................................................
USB1 Highlight .........................................................................................................
USB2 Highlight .........................................................................................................
USB3 Highlight .........................................................................................................
SuperSpeed USB Subsystem Environment ........................................................................
SuperSpeed USB Controller Application: USB3.0 DRD ..........................................................
SuperSpeed USB Controller Application: USB2.0 DRD (Internal PHY) ........................................
SuperSpeed USB Controller Application: USB2.0 DRD (ULPI PHY) ...........................................
SuperSpeed USB Subsystem Integration ..........................................................................
SATA Host Controller Subsystem Overview ......................................................................
SATA Subsystem Environment ......................................................................................
SATA Controller Integration ..........................................................................................
SATA Controller Functional Block Diagram ........................................................................
Simplified Schema of Link Dword Processing .....................................................................
SATA Data Stream Components ....................................................................................
SATA Controller Interrupt Propagation Schema ...................................................................
Command List Descriptor Structures ................................................................................
PCIe Controller Subsystem Overview ..............................................................................
PCIe Controllers Integration ..........................................................................................
PCIe Controller Functional Block Diagram .........................................................................
PCIe D-state (function power state) FSM diagram ................................................................
PCIe Core to PCIe Core Address Mapping and Translation .....................................................
DCAN1 Overview ......................................................................................................
DCAN2 Overview .....................................................................................................
DCAN Typical Application ............................................................................................
DCAN1 Integration .....................................................................................................
DCAN2 Integration ....................................................................................................
DCAN Block Diagram .................................................................................................
Error and Status Change Interrupts .................................................................................
Message Objects Interrupts ..........................................................................................
24-135. McASP DIT- /TDM- Transmission Polling Method
5958
24-136. Subsequence – DIT-/TDM- Transmission Startup Procedure
5960
24-137.
5963
24-138.
24-139.
24-140.
24-141.
24-142.
24-143.
24-144.
24-145.
24-146.
24-147.
24-148.
24-149.
24-150.
24-151.
24-152.
24-153.
24-154.
24-155.
24-156.
24-157.
24-158.
24-159.
24-160.
24-161.
24-162.
24-163.
24-164.
24-165.
24-166.
24-167.
24-168.
24-169.
24-170.
24-171.
SPRUIC2D – January 2017 – Revised April 2019
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Copyright © 2017–2019, Texas Instruments Incorporated
List of Figures
5965
5968
5969
5970
5971
6040
6041
6042
6044
6046
6048
6049
6050
6054
6058
6059
6061
6062
6064
6069
6075
6127
6130
6134
6143
6155
6356
6357
6358
6360
6361
6363
6365
6366
83
www.ti.com
24-172. Local Power-Down Mode Flow Diagram ............................................................................ 6367
24-173. Software Handling of a FIFO Buffer (Interrupt Driven) ............................................................ 6376
24-174. Bit Timing ............................................................................................................... 6377
24-175. The Propagation Time Segment ..................................................................................... 6378
24-176. Synchronization on Late and Early Edges .......................................................................... 6380
24-177. Filtering of Short Dominant Spikes .................................................................................. 6381
24-178. Structure of the CAN Core’s CAN Protocol Controller ............................................................ 6382
24-179. Data Transfer Between IF1/IF2 Registers and Message RAM .................................................. 6385
24-180. CAN Module General Initialization Flow ............................................................................ 6391
24-181. CAN Bit-Timing Configuration ........................................................................................ 6392
24-182. CAN Core in Silent Mode ............................................................................................. 6395
24-183. CAN Core in Loopback Mode ........................................................................................ 6395
24-184. CAN Core in External Loopback Mode
.............................................................................
6396
24-185. CAN Core in Loop Back Combined With Silent Mode ............................................................ 6397
24-186. GMAC_SW Overview
.................................................................................................
6451
24-187. MII Interface Typical Application ..................................................................................... 6454
24-188. RMII Interface Typical Application ................................................................................... 6455
24-189. RGMII Interface Typical Application ................................................................................. 6456
24-190. GMAC_SW Integration ................................................................................................ 6458
24-191. GMAC_SW Top Level Block Diagram .............................................................................. 6461
24-192. CPSW_3G Block Diagram ............................................................................................ 6468
24-193. The Network Static with AVB ......................................................................................... 6480
24-194. AVB Network & PTP Clock Entities
.................................................................................
6481
24-195. IEEE 1722 Packets .................................................................................................... 6482
24-196. Cross Time Stamping and Presentation Timestamps............................................................. 6483
24-197. AV Stream Queuing/Policing ......................................................................................... 6484
24-198. SPF Block Diagram .................................................................................................... 6501
24-199. Packet Octets as Stored in the Packet Buffer...................................................................... 6505
24-200. CPTS Block Diagram .................................................................................................. 6517
24-201. Event FIFO Misalignment Condition ................................................................................. 6519
24-202. HW1/4_TSP_PUSH Connection ..................................................................................... 6520
24-203. Partial Ethernet-II Frames Showing Register Mapping of EtherTypes for a Simple Frame (1), a Single
1Q Tag Added (2), and Two 1Q Tags Added (3) ................................................................... 6521
24-204. TX Queue Head Descriptor ........................................................................................... 6531
24-205. RX Queue Head Descriptor
..........................................................................................
6533
24-206. MLB Overview .......................................................................................................... 6715
24-207. MLB Sub System Environment
......................................................................................
6716
24-208. MLB I/O Cells And Their Controls ................................................................................... 6718
24-209. Circuit for Doubling the MLB Clock Line Frequency
..............................................................
6720
24-210. MLB Sub System Integration ......................................................................................... 6721
24-211. MLBSS Structural Overview .......................................................................................... 6723
24-212. DMA Descriptor Table Endian Options
.............................................................................
6733
24-213. Ping-Pong System Memory Structure ............................................................................... 6733
24-214. Single-Packet Mode Memory Space ................................................................................ 6735
24-215. Multi-Packet Mode System Memory ................................................................................. 6736
6737
25-1.
6768
25-2.
25-3.
84
........................................................................
eMMC/SD/SDIOi Overview (i = 1 to 4) ...............................................................................
eMMC/SD/SDIOi Controller Connected to an eMMC, SD, or SDIO Card (where i = 1 to 4) ..................
Sequential Read Operation (MMC Cards Only) .....................................................................
24-216. MLBSS Software and Data Flow Overview
List of Figures
6771
6773
SPRUIC2D – January 2017 – Revised April 2019
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25-4.
Sequential Write Operation (MMC Cards Only) ..................................................................... 6773
25-5.
Multiple Block Read Operation ........................................................................................ 6774
25-6.
Multiple Block Write Operation With Card Busy Signal ............................................................ 6774
25-7.
Command Token Format ............................................................................................... 6775
25-8.
Response Token Format (R1, R3, R4, R5, R6, R7) ................................................................ 6775
25-9.
Response Token Format (R2) ......................................................................................... 6775
25-10. Data Token Format for 1-Bit Transfers ............................................................................... 6776
25-11. Data Token Format for 4-Bit Transfers ............................................................................... 6776
25-12. Data Token Format for 8-Bit Transfers ............................................................................... 6777
25-13. Integration of MMC1 and MMC2 Controllers – Master and Slave Capable
....................................
6779
25-14. Integration of MMC3 and MMC4 Controllers – Slave Capable Only ............................................. 6780
25-15. eMMC/SD/SDIO Diagram .............................................................................................. 6784
25-16. ADMA Block Diagram Overview....................................................................................... 6794
...........................................................................................
DMA Receive Mode .....................................................................................................
DMA Transmit Mode ....................................................................................................
Buffer Management for a Write ........................................................................................
Buffer Management for a Read .......................................................................................
Busy Time-Out for R1b, R5b Response Type .......................................................................
Busy Time-Out After Write CRC Status ..............................................................................
Write CRC Status Time-Out ...........................................................................................
Read Data Time-Out ....................................................................................................
Boot Acknowledge Time-Out When Using CMD0 ..................................................................
Boot Acknowledge Time-Out When CMD Line Tied to 0 ..........................................................
Auto CMD12 Timings During Write Transfer ........................................................................
Auto CMD12 Timings During Read Transfer ........................................................................
Output Driven on Falling Edge ........................................................................................
Output Driven on Rising Edge .........................................................................................
Boot Mode Using the CMD0 Timing Diagram .......................................................................
Boot Mode With CMD Line Tied to 0 Timing Diagram .............................................................
eMMC/SD/SDIO Controller Software Reset Flow ...................................................................
eMMC/SD/SDIO Controller Bus Configuration ......................................................................
eMMC/SD/SDIO Controller Card Identification and Selection – Part 1 ..........................................
eMMC/SD/SDIO Controller Card Identification and Selection – Part 2 ..........................................
eMMC/SD/SDIO Controller Read/Write Transfer Flow in DMA Slave Mode With interrupt ...................
eMMC/SD/SDIO Controller Read/Write Transfer Flow in DMA Mode With Polling ............................
eMMC/SD/SDIO Controller Read/Write Transfer Flow Without DMA and With Polling ........................
eMMC/SD/SDIO Controller Read/Write in CE-ATA Mode .........................................................
eMMC/SD/SDIO Controller Suspend Flow...........................................................................
eMMC/SD/SDIO Controller Resume Flow ...........................................................................
eMMC/SD/SDIO Controller Command Transfer Flow With Polling ...............................................
eMMC/SD/SDIO Controller Command Transfer Flow With interrupts ............................................
eMMC/SD/SDIO Controller Clock Frequency Change Flow .......................................................
eMMC/SD/SDIO Controller Bus Width Configuration Flow ........................................................
eMMC/SD/SDIO Power Switching Procedure .......................................................................
eMMC/SD/SDIO Controller Boot Using CMD0 ......................................................................
eMMC/SD/SDIO Controller Boot With CMD Line Tied to 0 ........................................................
SDR104/HS200 DLL Tuning Procedure..............................................................................
SATA PHY Subsystem Overview .....................................................................................
25-17. ADMA Finite State-Machine
25-18.
25-19.
25-20.
25-21.
25-22.
25-23.
25-24.
25-25.
25-26.
25-27.
25-28.
25-29.
25-30.
25-31.
25-32.
25-33.
25-34.
25-35.
25-36.
25-37.
25-38.
25-39.
25-40.
25-41.
25-42.
25-43.
25-44.
25-45.
25-46.
25-47.
25-48.
25-49.
25-50.
25-51.
26-1.
SPRUIC2D – January 2017 – Revised April 2019
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Copyright © 2017–2019, Texas Instruments Incorporated
List of Figures
6796
6798
6799
6801
6802
6805
6805
6806
6806
6807
6807
6808
6808
6810
6811
6812
6812
6816
6817
6819
6820
6822
6823
6825
6826
6828
6829
6830
6832
6833
6834
6835
6837
6838
6840
6914
85
www.ti.com
26-2.
SATA PHY I/O Signals ................................................................................................. 6916
26-3.
SATA PHY Subsystem Integration .................................................................................... 6918
26-4.
SATA DPLL Clock Generator Overview .............................................................................. 6922
26-5.
DPLL_SATA Functional Block Diagram .............................................................................. 6925
26-6.
SATA PLL GO Sequence
26-7.
SATA PLL Programming Sequence .................................................................................. 6929
26-8.
USB3_PHY Subsystem Overview
26-9.
USB3_PHY I/O Signals ................................................................................................. 6935
.............................................................................................
....................................................................................
6926
6934
26-10. USB3_PHY Subsystem Integration ................................................................................... 6938
26-11. USB3_PHY DPLL Clock Generator Overview....................................................................... 6943
26-12. DPLL_USB_OTG_SS Functional Block Diagram ................................................................... 6946
26-13. USB3_PHY PLL GO Sequence
......................................................................................
6948
26-14. USB3_PHY PLL Programming Sequence ........................................................................... 6951
...............................................................................
PCIe PHY I/O Signals ..................................................................................................
PCIe PHY Subsystem Integration .....................................................................................
PCIe PHY Subsystem Block Diagram ................................................................................
PCIe PHY Clock Generator Overview ................................................................................
DPLL_PCIE_REF Functional Block Diagram ........................................................................
DPLL_PCIE_REF Programming Sequence .........................................................................
APLL_PCIE Functional Block Diagram ...............................................................................
General-Purpose Interface Overview .................................................................................
General-Purpose Interface Typical Application......................................................................
General-Purpose Interface Used as a Keyboard Interface ........................................................
GPIO1 Signal Connections ............................................................................................
GPIO2 Through GPIO8 Signal Connections ........................................................................
GPIO Integration ........................................................................................................
General-Purpose Interface Block Diagram...........................................................................
Synchronous Path .......................................................................................................
Asynchronous Path .....................................................................................................
Interrupt Request Generation ..........................................................................................
Wake-Up Request Generation.........................................................................................
Wake-Up Event Conditions ............................................................................................
GPIO_CLEARDATAOUT Register Example ........................................................................
Write in GPIO_IRQSTATUS_SET_0 Register Example ...........................................................
Keyboard Controller Overview .........................................................................................
Typical Keyboard Environment ........................................................................................
Multikey Limitation Example ...........................................................................................
Keyboard Controller Integration .......................................................................................
Keyboard Controller Block Diagram ..................................................................................
Functional Modes and Related Interrupt Events ....................................................................
Key Coding Registers...................................................................................................
PWMSS Block Diagram ................................................................................................
PWMSS External Interface I/Os .......................................................................................
PWMSS Integration .....................................................................................................
Synchronization between PWMSS1, PWMSS2 and PWMSS3 ...................................................
Multiple ePWM Modules................................................................................................
Submodules and Signal Connections for an ePWM Module ......................................................
ePWM Submodules and Critical Internal Signal Interconnects ...................................................
26-15. PCIe Controller Subsystem Overview
26-16.
26-17.
26-18.
26-19.
26-20.
26-21.
26-22.
27-1.
27-2.
27-3.
27-4.
27-5.
27-6.
27-7.
27-8.
27-9.
27-10.
27-11.
27-12.
27-13.
27-14.
28-1.
28-2.
28-3.
28-4.
28-5.
28-6.
28-7.
29-1.
29-2.
29-3.
29-4.
29-5.
29-6.
29-7.
86
List of Figures
6972
6975
6977
6979
6984
6987
6990
6993
7012
7014
7015
7016
7017
7018
7023
7023
7024
7025
7026
7027
7036
7037
7063
7065
7067
7068
7070
7075
7076
7100
7103
7105
7109
7117
7118
7119
SPRUIC2D – January 2017 – Revised April 2019
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29-8.
ePWM Time-Base Submodule Block Diagram ...................................................................... 7123
29-9.
ePWM Time-Base Submodule Signals and Registers ............................................................. 7125
...........................................................................
...........................................................
ePWM Time-Base Up-Count Mode Waveforms ....................................................................
ePWM Time-Base Down-Count Mode Waveforms .................................................................
29-10. ePWM Time-Base Frequency and Period
7127
29-11. ePWM Time-Base Counter Synchronization Scheme 1
7128
29-12.
29-13.
7130
7131
29-14. ePWM Time-Base Up-Down-Count Waveforms, EPWM_TBCTL[13] PHSDIR = 0 Count Down on
Synchronization Event .................................................................................................. 7132
29-15. ePWM Time-Base Up-Down Count Waveforms, EPWM_TBCTL[13] PHSDIR = 1 Count Up on
Synchronization Event .................................................................................................. 7133
29-16. ePWM Counter-Compare Submodule ................................................................................ 7134
29-17. ePWM Counter-Compare Submodule Signals and Registers ..................................................... 7135
29-18. ePWM Counter-Compare Event Waveforms in Up-Count Mode ................................................. 7138
29-19. ePWM Counter-Compare Events in Down-Count Mode ........................................................... 7138
29-20. ePWM Counter-Compare Events in Up-Down-Count Mode, EPWM_TBCTL[13] PHSDIR = 0 Count
Down on Synchronization Event ...................................................................................... 7139
29-21. ePWM Counter-Compare Events in Up-Down-Count Mode, EPWM_TBCTL[13] PHSDIR = 1 Count Up
on Synchronization Event ............................................................................................. 7139
29-22. ePWM Action-Qualifier Submodule ................................................................................... 7140
29-23. ePWM Action-Qualifier Submodule Inputs and Outputs ........................................................... 7141
29-24. Possible Action-Qualifier Actions for EPWMxA and EPWMxB Outputs
.........................................
7142
29-25. ePWM Up-Down-Count Mode Symmetrical Waveform ............................................................ 7145
29-26. Up, Single Edge Asymmetric Waveform, With Independent Modulation on EPWMxA and
EPWMxB—Active High ................................................................................................. 7146
29-27. Up, Single Edge Asymmetric Waveform With Independent Modulation on EPWMxA and
EPWMxB—Active Low ................................................................................................. 7148
29-28. Up-Count, Pulse Placement Asymmetric Waveform With Independent Modulation on EPWMxA ........... 7150
29-29. Up-Down-Count, Dual Edge Symmetric Waveform, With Independent Modulation on EPWMxA and
EPWMxB — Active Low ................................................................................................ 7152
29-30. Up-Down-Count, Dual Edge Symmetric Waveform, With Independent Modulation on EPWMxA and
EPWMxB — Complementary .......................................................................................... 7154
29-31. Up-Down-Count, Dual Edge Asymmetric Waveform, With Independent Modulation on EPWMxA—Active
Low ........................................................................................................................ 7156
29-32. Dead-Band Generator Submodule .................................................................................... 7158
29-33. Configuration Options for the ePWM Dead-Band Generator Submodule ....................................... 7159
29-34. Dead-Band Waveforms for Typical Cases (0% < Duty < 100%).................................................. 7161
29-35. PWM-Chopper Submodule
............................................................................................
7162
29-36. PWM-Chopper Submodule Signals and Registers ................................................................. 7163
29-37. Simple PWM-Chopper Submodule Waveforms Showing Chopping Action Only ............................... 7164
29-38. PWM-Chopper Submodule Waveforms Showing the First Pulse and Subsequent Sustaining Pulses ...... 7164
29-39. PWM-Chopper Submodule Waveforms Showing the Pulse Width (Duty Cycle) Control of Sustaining
Pulses ..................................................................................................................... 7165
29-40. ePWM Trip-Zone Submodule .......................................................................................... 7166
.................................................................
ePWM Trip-Zone Submodule Interrupt Logic ........................................................................
ePWM Event-Trigger Submodule .....................................................................................
ePWM Event-Trigger Submodule Inter-Connectivity to Interrupt Controller .....................................
ePWM Event-Trigger Submodule Showing Event Inputs and Prescaled Outputs ..............................
ePWM Event-Trigger Interrupt Generator ............................................................................
HRPWM System Interface .............................................................................................
Resolution Calculations for Conventionally Generated PWM .....................................................
29-41. ePWM Trip-Zone Submodule Mode Control Logic
7169
29-42.
7169
29-43.
29-44.
29-45.
29-46.
29-47.
29-48.
SPRUIC2D – January 2017 – Revised April 2019
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Copyright © 2017–2019, Texas Instruments Incorporated
List of Figures
7170
7171
7172
7174
7175
7176
87
www.ti.com
29-49. Operating Logic Using MEP ........................................................................................... 7177
29-50. Required PWM Waveform for a Requested Duty = 40.5% ........................................................ 7179
7181
29-52. High % Duty Cycle Range Limitation Example when PWM Frequency = 1 MHz
7181
29-53.
29-54.
29-55.
29-56.
29-57.
29-58.
29-59.
29-60.
29-61.
29-62.
29-63.
29-64.
29-65.
29-66.
29-67.
29-68.
29-69.
29-70.
29-71.
29-72.
29-73.
29-74.
29-75.
29-76.
29-77.
29-78.
29-79.
29-80.
29-81.
30-1.
30-2.
30-3.
30-4.
30-5.
30-6.
30-7.
30-8.
30-9.
30-10.
30-11.
30-12.
30-13.
30-14.
30-15.
30-16.
88
..............................
..............................
Multiple eCAP Modules .................................................................................................
Capture and APWM Modes of Operation ............................................................................
Capture Function Diagram .............................................................................................
Event Prescale Control .................................................................................................
Prescale Function Waveforms .........................................................................................
eCAP Continuous/One-shot Block Diagram .........................................................................
eCAP Counter and Synchronization Block Diagram ................................................................
Interrupts in eCAP Module .............................................................................................
PWM Waveform Details Of eCAP APWM Mode Operation .......................................................
Optical Encoder Disk ...................................................................................................
QEP Encoder Output Signal for Forward/Reverse Movement ....................................................
Index Pulse Example ...................................................................................................
Functional Block Diagram of the eQEP Peripheral .................................................................
Functional Block Diagram of Decoder Unit ..........................................................................
Quadrature Decoder State Machine ..................................................................................
Quadrature-clock and Direction Decoding ...........................................................................
Position Counter Reset by Index Pulse for 1000 Line Encoder (QPOSMAX = 3999 or F9Fh) ...............
Position Counter Underflow/Overflow (QPOSMAX = 4) ...........................................................
Software Index Marker for 1000-line Encoder (EQEP_QEPCTL[5:4] IEL = 0b01) .............................
eQEP Strobe Event Latch (EQEP_QEPCTL[6] SEL = 0b1) .......................................................
eQEP Position-compare Unit ..........................................................................................
eQEP Position-compare Event Generation Points ..................................................................
eQEP Position-compare Sync Output Pulse Stretcher .............................................................
eQEP Edge Capture Unit ..............................................................................................
Unit Position Event for Low Speed Measurement (EQEP_QCAPCTL[UPPS] = 0010) ........................
eQEP Edge Capture Unit - Timing Details ...........................................................................
eQEP Watchdog Timer .................................................................................................
eQEP Unit Time Base ..................................................................................................
EQEP Interrupt Generation ............................................................................................
PRU-ICSS Overview ....................................................................................................
PRU-ICSS Internal Wrapper Multiplexing ............................................................................
PRU-ICSS1 External Interface I/Os ...................................................................................
PRU-ICSS2 External Interface I/Os ...................................................................................
PRU-ICSS1 Integration in the Device ................................................................................
PRU-ICSS2 Integration in the Device ................................................................................
PRU Block Diagram .....................................................................................................
PRU Module Interface ..................................................................................................
Event Interface Mapping (R31) ........................................................................................
PRU R31 (EGPI) Direct Input Mode Block Diagram ................................................................
PRU R31 (EGPI) 16-Bit Parallel Capture Mode Block Diagram ..................................................
PRU R31 (EGPI) 28-Bit Shift Mode ...................................................................................
PRU R30 (EGPO) Direct Output Mode Block Diagram ............................................................
PRU R30 (GPO) Shift Out Mode Block Diagram ...................................................................
Sigma Delta Block Diagram ............................................................................................
Sigma Delta Hardware Integrators Block Diagram (snoop = 0) ...................................................
29-51. Low % Duty Cycle Range Limitation Example When PWM Frequency = 1 MHz
List of Figures
7214
7215
7216
7217
7217
7218
7219
7221
7222
7236
7237
7237
7239
7241
7243
7243
7245
7246
7248
7249
7250
7251
7251
7253
7253
7254
7255
7256
7256
7280
7282
7291
7292
7293
7294
7329
7331
7332
7334
7335
7336
7337
7338
7341
7343
SPRUIC2D – January 2017 – Revised April 2019
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30-17. Sigma Delta Hardware Integrators Block Diagram (snoop = 1) ................................................... 7343
30-18. Peripheral I/F Block Diagram .......................................................................................... 7348
30-19. TX Mode Start Condition ............................................................................................... 7353
30-20. ENDAT<m>_CLK Stop High on Last RX Frame .................................................................... 7354
30-21. ENDAT<m>_CLK Stop Low on Last RX Frame
....................................................................
7355
30-22. ENDAT<m>_CLK Run Continuously ................................................................................. 7356
30-23. ENDAT<m>_CLK Stop High on Last TX Bit ......................................................................... 7357
30-24. Integration of the PRU and MPY/MAC ............................................................................... 7360
.....................................................................
MAC Multiply and Accumulate Mode Functional Diagram ........................................................
ScratchPad and PRU Integration .....................................................................................
PRU-ICSS Interrupt Controller Block Diagram ......................................................................
Flow of System Interrupts to Host.....................................................................................
PRU-ICSS UART Protocol Formats ..................................................................................
PRU-ICSS UART Clock Generation Diagram .......................................................................
Relationships Between PRU-ICSS UART Data Bit, BCLK, and Input Clock ....................................
PRU-ICSS UART Block Diagram .....................................................................................
PRU-ICSS UART Interrupt Request Enable Paths .................................................................
UART Interface Using Autoflow Diagram ............................................................................
Autoflow Functional Timing Waveforms for PRUSS_UART0_RTS ..............................................
Autoflow Functional Timing Waveforms for PRUSS_UART0_CTS ..............................................
MII_RT Block Diagram..................................................................................................
Auto-forward .............................................................................................................
Auto-forward with PRU Snoop .........................................................................................
8- or 16-bit Processing with On-the-Fly Modifications ..............................................................
32-byte Double Buffer or Ping-Pong Processing ...................................................................
Data Nibble Structure ...................................................................................................
PRU R30, R31 Operations .............................................................................................
Reading and Writing FIFO Data .......................................................................................
RX Data Latch ...........................................................................................................
Start of Frame Detection ...............................................................................................
CRC Error Detection ....................................................................................................
RX Error Detection ......................................................................................................
Error Detection Window with Running Counter .....................................................................
RX L1 to PRU Interface ................................................................................................
MII RX Data to PRU R31 (R) and RX FIFO .........................................................................
RX L2 to PRU Interface ................................................................................................
Data and Status Register Dependency ..............................................................................
PRU to TX L1 Interface .................................................................................................
PRU to TX MII Interface ................................................................................................
TX Mask Mode (PRUSS_MII_RT_TXCFG0/1 [TX_32_MODE_EN] = 0) ........................................
RX L1 to TX L1 Interface ...............................................................................................
MII Receive Multiplexer .................................................................................................
MII Transmit Multiplexer ................................................................................................
Scratch Pad Mode ......................................................................................................
Device PRU-ICSS MII MDIO Management Interface Overview ..................................................
Functional Block Diagram ..............................................................................................
PRU-ICSS IEP SYNC0 Signal Generation Modes .................................................................
Examples of the Dependent Mode of SYNC1 ......................................................................
30-25. MAC Multiply-only Mode- Functional Diagram
30-26.
30-27.
30-28.
30-29.
30-30.
30-31.
30-32.
30-33.
30-34.
30-35.
30-36.
30-37.
30-38.
30-39.
30-40.
30-41.
30-42.
30-43.
30-44.
30-45.
30-46.
30-47.
30-48.
30-49.
30-50.
30-51.
30-52.
30-53.
30-54.
30-55.
30-56.
30-57.
30-58.
30-59.
30-60.
30-61.
30-62.
30-63.
30-64.
30-65.
SPRUIC2D – January 2017 – Revised April 2019
Submit Documentation Feedback
Copyright © 2017–2019, Texas Instruments Incorporated
List of Figures
7361
7362
7365
7411
7411
7437
7439
7439
7441
7443
7448
7448
7449
7478
7478
7479
7479
7479
7480
7480
7481
7482
7482
7483
7483
7483
7484
7484
7487
7488
7490
7490
7491
7491
7494
7495
7495
7515
7530
7533
7534
89
www.ti.com
......................................................................................................
IEP DIGIO Data Out ....................................................................................................
VCP Highlight ............................................................................................................
VCP1 and VCP2 Integration ...........................................................................................
VCP Block Diagram .....................................................................................................
Convolutional Encoder Example Block Diagram ....................................................................
Trellis Diagram for Convolutional Encoder Example Block Diagram .............................................
Viterbi Processing Unit .................................................................................................
Tailed Traceback Mode ................................................................................................
Mixed Traceback Mode - Example with Five Sliding Windows ...................................................
Convergent Traceback Mode - Example With Five Sliding Windows ............................................
Input FIFO (Branch Metrics) ...........................................................................................
Output FIFO (Decisions Data) .........................................................................................
Data Source - EDMA (BM = 1) ........................................................................................
Data Destination - Kernel for Processing Unit (BM = 1) ...........................................................
Data Source - EDMA (BM = 0) ........................................................................................
Data Destination - Kernel for Processing Unit (BM = 0) ...........................................................
Trellis Stage Ordering of Hard Decisions in 32-Bit Word (OUT_ORDER = 0) ..................................
Trellis Stage Ordering of Hard Decisions in 32-Bit Word (OUT_ORDER = 1) ..................................
EDMA Parameters Structure ..........................................................................................
ATL Module Overview ..................................................................................................
Initialization Process ....................................................................................................
Power Supply Connections Example .................................................................................
Clock, Reset, and Control Environment Overview ..................................................................
ROM Code Architecture ................................................................................................
ROM Memory Map ......................................................................................................
RAM Memory Map ......................................................................................................
Overall Booting Sequence .............................................................................................
ROM Code Start-Up Sequence .......................................................................................
Synchronization Phase for UART .....................................................................................
Synchronization Phase for USB .......................................................................................
Peripheral Booting Procedure .........................................................................................
USB Initialization Procedure ...........................................................................................
SATA Flashing Over USB ..............................................................................................
Fast External Boot Procedure .........................................................................................
Memory Booting Procedure ............................................................................................
Image Shadowing .......................................................................................................
NAND Device Detection ................................................................................................
Bad NAND – Invalid Block Detection .................................................................................
ECC Data Mapping for 2-KiB Page and 8b BCH Encoding .......................................................
ECC Data Mapping for 4-KiB Page and 16b BCH Encoding ......................................................
eMMC Connection ......................................................................................................
MMC/SD Card Connection .............................................................................................
eMMC and SD Booting .................................................................................................
SD/eMMC Detection Procedure (part 1) .............................................................................
SD/eMMC Detection Procedure (part 2) .............................................................................
SD/eMMC Detection Procedure (part 3) .............................................................................
SD/MMC Get Booting File..............................................................................................
MBR Detection Procedure .............................................................................................
30-66. IEP DIGIO Data In
30-67.
31-1.
31-2.
31-3.
31-4.
31-5.
31-6.
31-7.
31-8.
31-9.
31-10.
31-11.
31-12.
31-13.
31-14.
31-15.
31-16.
31-17.
31-18.
32-1.
33-1.
33-2.
33-3.
33-4.
33-5.
33-6.
33-7.
33-8.
33-9.
33-10.
33-11.
33-12.
33-13.
33-14.
33-15.
33-16.
33-17.
33-18.
33-19.
33-20.
33-21.
33-22.
33-23.
33-24.
33-25.
33-26.
33-27.
33-28.
90
List of Figures
7536
7536
7567
7569
7571
7574
7575
7576
7576
7577
7577
7579
7580
7584
7584
7585
7585
7585
7585
7590
7614
7616
7618
7621
7630
7631
7632
7634
7636
7640
7641
7643
7644
7645
7652
7654
7655
7660
7661
7662
7663
7665
7666
7667
7669
7670
7671
7673
7675
SPRUIC2D – January 2017 – Revised April 2019
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www.ti.com
33-29. MBR, Get Partition ...................................................................................................... 7676
33-30. Booting from a Permanently-Attached SSD Device ................................................................ 7679
33-31. SATA Power-on Initialization Sequencing
...........................................................................
7680
33-32. Image Formats........................................................................................................... 7683
33-33. CH Format................................................................................................................ 7684
34-1.
34-2.
.......................................................................................
MPU and DSP Processor Traces Flow ...............................................................................
Register Descriptor Tool (RDT)
SPRUIC2D – January 2017 – Revised April 2019
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Copyright © 2017–2019, Texas Instruments Incorporated
List of Figures
7699
7721
91
www.ti.com
List of Tables
1-1.
Device Identification Register Fields ................................................................................... 380
1-2.
DIE_ID...................................................................................................................... 380
1-3.
DRA72x, DRA71x Part Number Identifier ............................................................................. 381
1-4.
ID_CODE .................................................................................................................. 381
1-5.
DRA72x, DRA71x ID_CODE Values ................................................................................... 381
1-6.
PROD_ID .................................................................................................................. 381
1-7.
DEVICE_TYPE ............................................................................................................ 382
2-1.
L3_MAIN Memory Map
2-2.
L3_INSTR Memory Map ................................................................................................. 390
2-3.
L4_CFG Memory Map
2-4.
2-5.
2-6.
2-7.
2-8.
2-9.
2-10.
2-11.
2-12.
3-1.
3-2.
3-3.
3-4.
3-5.
3-6.
3-7.
3-8.
3-9.
3-10.
3-11.
3-12.
3-13.
3-14.
3-15.
3-16.
3-17.
3-18.
3-19.
3-20.
3-21.
3-22.
3-23.
3-24.
3-25.
3-26.
3-27.
3-28.
92
..................................................................................................
...................................................................................................
L4_WKUP Memory Map .................................................................................................
L4_PER1 Memory Map ..................................................................................................
L4_PER2 Memory Map ..................................................................................................
L4_PER3 Memory Map ..................................................................................................
MPU Memory Map ........................................................................................................
IPU Memory Map .........................................................................................................
DSP Memory Map ........................................................................................................
PRU-ICSS Memory Map .................................................................................................
TILER View Memory Map ...............................................................................................
Master Module Standby Mode Settings................................................................................
Master Module Standby Status .........................................................................................
Master Module Clock Enabling Conditions ............................................................................
Module Idle Mode Settings ..............................................................................................
Slave Module Idle Status ................................................................................................
Slave Module Clock Activity Settings ..................................................................................
Slave Module Mode Settings in PRCM ................................................................................
Slave Module Interface Clock Enabling Conditions ..................................................................
Slave Module Functional Clock Enabling Conditions ................................................................
Clock Domain Functional Clock States ................................................................................
Clock Domain Interface Clock States ..................................................................................
Clock Domain Clock States .............................................................................................
Clock Domain Clock Transition Mode Settings .......................................................................
Clock Domain Wake-Up Conditions ....................................................................................
Clock Domain Sleep Conditions ........................................................................................
Device Domain Dependencies (Table 1) ..............................................................................
Device Domain Dependencies (Table 2) ..............................................................................
States of a Logic Area in a Power Domain ............................................................................
States of a Memory Area in a Power Domain ........................................................................
Power Domain Wake-Up Conditions ...................................................................................
Power Domain Sleep Conditions .......................................................................................
Power Domain Control and Status Registers .........................................................................
External Clock Signals ...................................................................................................
External Boot Signals ....................................................................................................
External Reset Signals ...................................................................................................
Voltage Sources ..........................................................................................................
PMFW Device-Level Layout .............................................................................................
PMFW Module Power Domains ........................................................................................
List of Tables
387
391
395
397
399
401
403
404
406
407
408
413
413
413
414
414
415
415
416
416
418
418
419
419
422
423
425
425
430
431
432
432
433
444
444
445
446
448
452
SPRUIC2D – January 2017 – Revised April 2019
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www.ti.com
3-29.
PMFW Module Reset Signals ........................................................................................... 452
3-30.
PMFW Hardware Requests
3-31.
Global Reset Sources .................................................................................................... 456
3-32.
Local Reset Sources ..................................................................................................... 456
3-33.
Modules, Power Domains, and Reset Domains Association
3-34.
Reset Sources for the Reset Domains ................................................................................. 461
3-35.
Reset Domains Attributes................................................................................................ 476
3-36.
Internal Clock Sources
3-37.
PRM Clock Division and Muxing Control .............................................................................. 493
3-38.
CM_CORE_AON (a) Clock Division and Muxing Control ........................................................... 497
3-39.
CM_CORE_AON (b) Clock Division and Muxing Control ........................................................... 499
3-40.
CM_CORE_AON_CLKOUTMUX Clock Division and Muxing Control ............................................. 504
3-41.
CM_CORE_AON_TIMER Clock Division and Muxing Control
3-42.
CM_CORE_AON_MCASP Clock Division and Muxing Control .................................................... 511
3-43.
CLKOUT_M2, CLKOUTX2_M2, and CLKOUTX2_M3 Frequencies With DPLL State .......................... 514
3-44.
CLKOUTX2_Hmn Frequencies With DPLL State .................................................................... 514
3-45.
DPLL Power Modes ...................................................................................................... 516
3-46.
DPLL Recalibration Control Parameters ............................................................................... 517
3-47.
DPLL Power-Down Control Parameters ............................................................................... 518
3-48.
DPLL_PER Clock Synthesis Parameters .............................................................................. 519
3-49.
DPLL_PER Clock Output Parameters ................................................................................. 519
3-50.
DPLL_PER Modes........................................................................................................ 519
3-51.
DPLL_PER Mode Control Parameters ................................................................................. 519
3-52.
DPLL_PER Recalibration Feature Parameters ....................................................................... 519
3-53.
DPLL_CORE Clock Synthesis Parameters
3-54.
DPLL_CORE Clock Output Parameters ............................................................................... 521
3-55.
DPLL_CORE Modes
3-56.
DPLL_CORE Mode Control Parameters
3-57.
3-58.
3-59.
3-60.
3-61.
3-62.
3-63.
3-64.
3-65.
3-66.
3-67.
3-68.
3-69.
3-70.
3-71.
3-72.
3-73.
3-74.
3-75.
3-76.
3-77.
.............................................................................................
.......................................................
..................................................................................................
.....................................................
...........................................................................
.....................................................................................................
..............................................................................
DPLL_CORE Recalibration Feature Parameters .....................................................................
DPLL_ABE Clock Synthesis Parameters ..............................................................................
DPLL_ABE Clock Output Parameters .................................................................................
DPLL_ABE Modes ........................................................................................................
DPLL_ABE Mode Control Parameters .................................................................................
DPLL_ABE Recalibration Feature Parameters .......................................................................
DPLL_MPU Clock Synthesis Parameters .............................................................................
DPLL_MPU Clock Output Parameters .................................................................................
DPLL_MPU Modes .......................................................................................................
DPLL_MPU Mode Control Parameters ................................................................................
DPLL_MPU Recalibration Feature Parameters .......................................................................
DPLL_IVA Clock Synthesis Parameters ...............................................................................
DPLL_IVA Clock Output Parameters ..................................................................................
DPLL_IVA Modes .........................................................................................................
DPLL_IVA Mode Control Parameters ..................................................................................
DPLL_IVA Recalibration Feature Parameters ........................................................................
DPLL_USB Clock Synthesis Parameters ..............................................................................
DPLL_USB Clock Output Parameters .................................................................................
DPLL_USB Modes........................................................................................................
DPLL_USB Mode Control Parameters .................................................................................
DPLL_USB Recalibration Feature Parameters .......................................................................
SPRUIC2D – January 2017 – Revised April 2019
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Copyright © 2017–2019, Texas Instruments Incorporated
List of Tables
452
457
491
508
520
521
521
522
522
523
523
523
523
524
524
525
525
525
526
526
526
526
527
527
527
528
528
528
93
www.ti.com
3-78.
DPLL_DSP Clock Synthesis Parameters .............................................................................. 529
3-79.
DPLL_DSP Clock Output Parameters ................................................................................. 529
3-80.
DPLL_DSP Modes........................................................................................................ 529
3-81.
DPLL_DSP Mode Control Parameters ................................................................................. 529
3-82.
DPLL_DSP Recalibration Feature Parameters ....................................................................... 529
3-83.
DPLL_GMAC Clock Synthesis Parameters ........................................................................... 530
3-84.
DPLL_GMAC Clock Output Parameters ............................................................................... 530
3-85.
DPLL_GMAC Modes ..................................................................................................... 531
3-86.
DPLL_GMAC Mode Control Parameters .............................................................................. 531
3-87.
DPLL_GMAC Recalibration Feature Parameters..................................................................... 531
3-88.
DPLL_GPU Clock Synthesis Parameters
3-89.
3-90.
3-91.
3-92.
3-93.
3-94.
3-95.
3-96.
3-97.
3-98.
3-99.
3-100.
3-101.
3-102.
3-103.
3-104.
3-105.
3-106.
3-107.
3-108.
3-109.
3-110.
3-111.
3-112.
3-113.
3-114.
3-115.
3-116.
3-117.
3-118.
3-119.
3-120.
3-121.
3-122.
3-123.
3-124.
3-125.
3-126.
94
.............................................................................
DPLL_GPU Clock Output Parameters .................................................................................
DPLL_GPU Modes .......................................................................................................
DPLL_GPU Mode Control Parameters ................................................................................
DPLL_GPU Recalibration Feature Parameters .......................................................................
DPLL_DDR Clock Synthesis Parameters .............................................................................
DPLL_DDR Clock Output Parameters .................................................................................
DPLL_DDR Modes .......................................................................................................
DPLL_DDR Mode Control Parameters ................................................................................
DPLL_DDR Recalibration Feature Parameters .......................................................................
DPLL_PCIE_REF Clock Synthesis Parameters ......................................................................
DPLL_PCIE_REF Clock Output Parameters ..........................................................................
DPLL_PCIE_REF Modes ................................................................................................
DPLL_PCIE_REF Mode Control Parameters .........................................................................
APLL_PCIE Clock Output Parameters .................................................................................
APLL_PCIE Modes .......................................................................................................
APLL_PCIE Mode Control Parameters ................................................................................
CD_WKUPAON Clock Domain Modes ................................................................................
CD_WKUPAON Control and Status Parameters .....................................................................
CD_WKUPAON Wake-Up Dependency Association Parameters..................................................
CD_WKUPAON Modules Clocks Association ........................................................................
CD_WKUPAON Modules Wake-Up Request .........................................................................
CD_WKUPAON Modules Clock-Management Modes and Control ................................................
CD_WKUPAON Modules Slave Clock-Management Modes and Control ........................................
CD_DSP1 Clock Domain Modes .......................................................................................
CD_DSP1 Control and Status Parameters ............................................................................
CD_DSP1 Static Dependency Association Parameters .............................................................
CD_DSP1 Dynamic Dependency Association Parameters .........................................................
CD_DSP1 Modules Clocks Association ...............................................................................
CD_DSP1 Modules Wake-Up Request ................................................................................
CD_DSP1 Modules Clock-Management Modes and Control .......................................................
CD_DSP1 Modules Slave Clock-Management Modes and Control ...............................................
CD_CUSTEFUSE Clock Domain Modes ..............................................................................
CD_CUSTEFUSE Control and Status Parameters...................................................................
CD_CUSTEFUSE Modules Clocks Association ......................................................................
CD_CUSTEFUSE Modules Wake-Up Request .......................................................................
CD_CUSTEFUSE Modules Clock-Management Modes and Control ..............................................
CD_CUSTEFUSE Modules Slave Clock-Management Modes and Control ......................................
CD_MPU Clock Domain Modes ........................................................................................
List of Tables
532
532
532
533
533
534
534
534
534
534
535
535
535
536
536
537
537
538
538
538
540
541
541
541
543
543
543
544
544
544
544
545
545
545
546
546
546
546
547
SPRUIC2D – January 2017 – Revised April 2019
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Copyright © 2017–2019, Texas Instruments Incorporated
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3-127. CD_MPU Control and Status Parameters ............................................................................. 547
3-128. CD_MPU Static Dependency Association Parameters .............................................................. 547
3-129. CD_MPU Dynamic Dependency Association Parameters .......................................................... 548
................................................................................
CD_MPU Modules Wake-Up Request .................................................................................
CD_MPU Modules Clock-Management Modes and Control ........................................................
CD_MPU Modules Slave Clock-Management Modes and Control ................................................
CD_L4PER1 Clock Domain Modes ....................................................................................
CD_L4PER1 Control and Status Parameters .........................................................................
CD_L4PER1 Dynamic Dependency Association Parameters ......................................................
CD_L4PER1 Wake-Up Dependency Association Parameters .....................................................
CD_L4PER1 Modules Clocks Association ............................................................................
CD_L4PER1 Modules Wake-Up Request .............................................................................
CD_L4PER1 Modules Clock-Management Modes and Control ....................................................
CD_L4PER1 Modules Slave Clock-Management Modes and Control ............................................
CD_L4PER2 Clock Domain Modes ....................................................................................
CD_L4PER2 Control and Status Parameters .........................................................................
CD_L4PER2 Dynamic Dependency Association Parameters ......................................................
CD_L4PER2 Wake-Up Dependency Association Parameters .....................................................
CD_L4PER2 Modules Clocks Association ............................................................................
CD_L4PER2 Modules Wake-Up Request .............................................................................
CD_L4PER2 Modules Clock-Management Modes and Control ....................................................
CD_L4PER2 Modules Slave Clock-Management Modes and Control ............................................
CD_L4PER3 Clock Domain Modes ....................................................................................
CD_L4PER3 Control and Status Parameters .........................................................................
CD_L4PER3 Dynamic Dependency Association Parameters ......................................................
CD_L4PER3 Modules Clocks Association ............................................................................
CD_L4PER3 Modules Wake-Up Request .............................................................................
CD_L4PER3 Modules Clock-Management Modes and Control ....................................................
CD_L4PER3 Modules Slave Clock-Management Modes and Control ............................................
CD_L4SEC Clock Domain Modes ......................................................................................
CD_L4SEC Control and Status Parameters ..........................................................................
CD_L4SEC Static Dependency Association Parameters ...........................................................
CD_L4SEC Dynamic Dependency Association Parameters ........................................................
CD_L4SEC Modules Clocks Association ..............................................................................
CD_L4SEC Modules Clock-Management Modes and Control .....................................................
CD_L4SEC Modules Slave Clock-Management Modes and Control ..............................................
CD_L3INIT Clock Domain Modes ......................................................................................
CD_L3INIT Control and Status Parameters ...........................................................................
CD_L3INIT Static Dependency Association Parameters ............................................................
CD_L3INIT Dynamic Dependency Association Parameters ........................................................
CD_L3INIT Wake-Up Dependency Association Parameters .......................................................
CD_L3INIT Modules Clocks Association ..............................................................................
CD_L3INIT Modules Wake-Up Request ...............................................................................
CD_L3INIT Modules Clock-Management Modes and Control ......................................................
CD_L3INIT Modules Slave Clock-Management Modes and Control ..............................................
CD_IVA Clock Domain Modes ..........................................................................................
CD_IVA Control and Status Parameters ..............................................................................
CD_IVA Static Dependency Association Parameters ................................................................
3-130. CD_MPU Modules Clocks Association
549
3-131.
549
3-132.
3-133.
3-134.
3-135.
3-136.
3-137.
3-138.
3-139.
3-140.
3-141.
3-142.
3-143.
3-144.
3-145.
3-146.
3-147.
3-148.
3-149.
3-150.
3-151.
3-152.
3-153.
3-154.
3-155.
3-156.
3-157.
3-158.
3-159.
3-160.
3-161.
3-162.
3-163.
3-164.
3-165.
3-166.
3-167.
3-168.
3-169.
3-170.
3-171.
3-172.
3-173.
3-174.
3-175.
SPRUIC2D – January 2017 – Revised April 2019
Submit Documentation Feedback
Copyright © 2017–2019, Texas Instruments Incorporated
List of Tables
549
549
550
550
551
551
565
566
567
568
571
571
572
572
577
578
579
580
581
581
582
582
583
583
583
584
584
584
585
585
585
586
587
587
588
588
588
591
591
592
593
594
594
594
95
www.ti.com
3-176. CD_IVA Dynamic Dependency Association Parameters ............................................................ 595
3-177. CD_IVA Modules Clocks Association .................................................................................. 595
3-178. CD_IVA Modules Wake-Up Request ................................................................................... 595
3-179. CD_IVA Modules Clock-Management Modes and Control .......................................................... 595
3-180. CD_IVA Modules Slave Clock-Management Modes and Control .................................................. 595
596
3-182.
596
3-183.
3-184.
3-185.
3-186.
3-187.
3-188.
3-189.
3-190.
3-191.
3-192.
3-193.
3-194.
3-195.
3-196.
3-197.
3-198.
3-199.
3-200.
3-201.
3-202.
3-203.
3-204.
3-205.
3-206.
3-207.
3-208.
3-209.
3-210.
3-211.
3-212.
3-213.
3-214.
3-215.
3-216.
3-217.
3-218.
3-219.
3-220.
3-221.
3-222.
3-223.
3-224.
96
........................................................................................
CD_GPU Control and Status Parameters .............................................................................
CD_GPU Static Dependency Association Parameters ..............................................................
CD_GPU Dynamic Dependency Association Parameters ..........................................................
CD_GPU Modules Clocks Association.................................................................................
CD_GPU Modules Wake-Up Request .................................................................................
CD_GPU Modules Clock-Management Modes and Control ........................................................
CD_GPU Modules Slave Clock-Management Modes and Control.................................................
CD_EMU Clock Domain Modes ........................................................................................
CD_EMU Control and Status Parameters .............................................................................
CD_EMU Dynamic Dependency Association Parameters ..........................................................
CD_EMU Modules Clocks Association ................................................................................
CD_EMU Modules Wake-Up Request .................................................................................
CD_DSS Clock Domain Modes .........................................................................................
CD_DSS Control and Status Parameters .............................................................................
CD_DSS Static Dependency Association Parameters ..............................................................
CD_DSS Dynamic Dependency Association Parameters ...........................................................
CD_DSS Wake-Up Dependency Association Parameters ..........................................................
CD_DSS Modules Clocks Association .................................................................................
CD_DSS Modules Wake-Up Request .................................................................................
CD_DSS Modules Clock-Management Modes and Control ........................................................
CD_DSS Modules Slave Clock-Management Modes and Control .................................................
CD_L4_CFG Clock Domain Modes ....................................................................................
CD_L4_CFG Control and Status Parameters .........................................................................
CD_L4_CFG Dynamic Dependency Association Parameters ......................................................
CD_L4_CFG Modules Clocks Association ............................................................................
CD_L4_CFG Modules Wake-Up Request .............................................................................
CD_L4_CFG Modules Clock-Management Modes and Control ....................................................
CD_L4_CFG Modules Slave Clock-Management Modes and Control ............................................
CD_L3_INSTR Clock Domain Modes ..................................................................................
CD_L3_INSTR Control and Status Parameters ......................................................................
CD_L3_INSTR Modules Clocks Association ..........................................................................
CD_L3_INSTR Modules Wake-Up Request ..........................................................................
CD_L3_INSTR Modules Clock-Management Modes and Control .................................................
CD_L3_INSTR Modules Slave Clock-Management Modes and Control ..........................................
CD_L3_MAIN1 Clock Domain Modes..................................................................................
CD_L3_MAIN1 Control and Status Parameters ......................................................................
CD_L3_MAIN1 Dynamic Dependency Association Parameters....................................................
CD_L3_MAIN1 Modules Clocks Association ..........................................................................
CD_L3_MAIN1 Modules Wake-Up Request ..........................................................................
CD_L3_MAIN1 Modules Clock-Management Modes and Control .................................................
CD_L3_MAIN1 Modules Slave Clock-Management Modes and Control ..........................................
CD_EMIF Clock Domain Modes ........................................................................................
CD_EMIF Control and Status Parameters ............................................................................
3-181. CD_GPU Clock Domain Modes
List of Tables
597
597
597
597
597
598
598
598
599
599
599
600
600
601
601
601
603
604
604
604
605
605
605
606
606
607
607
609
609
610
610
610
611
612
612
612
613
613
614
614
615
615
SPRUIC2D – January 2017 – Revised April 2019
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3-225. CD_EMIF Modules Clocks Association ................................................................................ 616
3-226. CD_EMIF Modules Wake-Up Request................................................................................. 616
3-227. CD_EMIF Modules Clock-Management Modes and Control........................................................ 616
3-228. CD_EMIF Modules Slave Clock-Management Modes and Control ................................................ 616
3-229. CD_IPU Clock Domain Modes .......................................................................................... 617
..............................................................................
CD_IPU Static Dependency Association Parameters................................................................
CD_IPU Dynamic Dependency Association Parameters ............................................................
CD_IPU Modules Clocks Association ..................................................................................
CD_IPU Modules Wake-Up Request ..................................................................................
CD_IPU Modules Clock-Management Modes and Control .........................................................
CD_IPU Modules Slave Clock-Management Modes and Control ..................................................
CD_IPU1 Clock Domain Modes ........................................................................................
CD_IPU1 Control and Status Parameters .............................................................................
CD_IPU1 Static Dependency Association Parameters ..............................................................
CD_IPU1 Dynamic Dependency Association Parameters ..........................................................
CD_IPU1 Modules Clocks Association ................................................................................
CD_IPU1 Modules Wake-Up Request .................................................................................
CD_IPU1 Modules Clock-Management Modes and Control ........................................................
CD_IPU1 Modules Slave Clock-Management Modes and Control ................................................
CD_IPU2 Clock Domain Modes ........................................................................................
CD_IPU2 Control and Status Parameters .............................................................................
CD_IPU2 Static Dependency Association Parameters ..............................................................
CD_IPU2 Dynamic Dependency Association Parameters ..........................................................
CD_IPU2 Modules Clocks Association ................................................................................
CD_IPU2 Modules Wake-Up Request .................................................................................
CD_IPU2 Modules Clock-Management Modes and Control ........................................................
CD_IPU2 Modules Slave Clock-Management Modes and Control ................................................
CD_DMA Clock Domain Modes ........................................................................................
CD_DMA Control and Status Parameters .............................................................................
CD_DMA Static Dependency Association Parameters ..............................................................
CD_DMA Dynamic Dependency Association Parameters ..........................................................
CD_DMA Modules Clocks Association ................................................................................
CD_DMA Modules Wake-Up Request .................................................................................
CD_DMA Modules Clock-Management Modes and Control ........................................................
CD_DMA Modules Slave Clock-Management Modes and Control ................................................
CD_ATL Clock Domain Modes .........................................................................................
CD_ATL Control and Status Parameters ..............................................................................
CD_ATL Modules Clocks Association .................................................................................
CD_ATL Modules Wake-Up Request ..................................................................................
CD_ATL Modules Clock-Management Modes and Control .........................................................
CD_ATL Modules Slave Clock-Management Modes and Control .................................................
CD_CAM Clock Domain Modes ........................................................................................
CD_CAM Control and Status Parameters .............................................................................
CD_CAM Static Dependency Association Parameters ..............................................................
CD_CAM Modules Clocks Association ................................................................................
CD_CAM Modules Wake-Up Request .................................................................................
CD_CAM Modules Clock-Management Modes and Control ........................................................
CD_CAM Modules Slave Clock-Management Modes and Control ................................................
3-230. CD_IPU Control and Status Parameters
3-231.
3-232.
3-233.
3-234.
3-235.
3-236.
3-237.
3-238.
3-239.
3-240.
3-241.
3-242.
3-243.
3-244.
3-245.
3-246.
3-247.
3-248.
3-249.
3-250.
3-251.
3-252.
3-253.
3-254.
3-255.
3-256.
3-257.
3-258.
3-259.
3-260.
3-261.
3-262.
3-263.
3-264.
3-265.
3-266.
3-267.
3-268.
3-269.
3-270.
3-271.
3-272.
3-273.
SPRUIC2D – January 2017 – Revised April 2019
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Copyright © 2017–2019, Texas Instruments Incorporated
List of Tables
617
618
619
619
620
620
620
621
621
622
623
623
623
623
623
624
624
624
625
626
626
626
626
627
627
627
628
628
628
629
629
629
630
630
630
630
630
631
631
632
632
633
633
633
97
www.ti.com
3-274. CD_GMAC Clock Domain Modes ...................................................................................... 634
3-275. CD_GMAC Control and Status Parameters ........................................................................... 634
3-276. CD_GMAC Static Dependency Association Parameters ............................................................ 635
3-277. CD_GMAC Dynamic Dependency Association Parameters ........................................................ 635
3-278. CD_GMAC Modules Clocks Association“
.............................................................................
635
3-279. CD_GMAC Modules Wake-Up Request ............................................................................... 635
3-280. CD_GMAC Modules Clock-Management Modes and Control ...................................................... 635
3-281. CD_GMAC Modules Slave Clock-Management Modes and Control .............................................. 636
3-282. CD_VPE Clock Domain Modes ......................................................................................... 637
3-283. CD_VPE Control and Status Parameters
.............................................................................
637
3-284. CD_VPE Static Dependency Association Parameters ............................................................... 637
3-285. CD_VPE Wake-Up Dependency Association Parameters .......................................................... 637
3-286. CD_VPE Modules Clocks Association ................................................................................. 638
3-287. CD_VPE Modules Wake-Up Request.................................................................................. 638
3-288. CD_VPE Modules Clock-Management Modes and Control......................................................... 638
3-289. CD_VPE Modules Slave Clock-Management Modes and Control ................................................. 638
3-290. CD_RTC Clock Domain Modes ......................................................................................... 639
3-291. CD_RTC Control and Status Parameters ............................................................................. 639
3-292. CD_RTC Wake-Up Dependency Association Parameters .......................................................... 639
3-293. CD_RTC Modules Clocks Association ................................................................................. 640
.................................................................................
CD_RTC Modules Clock-Management Modes and Control ........................................................
CD_RTC Modules Slave Clock-Management Modes and Control .................................................
CD_PCIE Clock Domain Modes ........................................................................................
CD_PCIE Control and Status Parameters.............................................................................
CD_PCIE Static Dependency Association Parameters ..............................................................
CD_PCIE Wake-Up Dependency Association Parameters .........................................................
CD_PCIE Modules Clocks Association ................................................................................
CD_PCIE Modules Wake-Up Request .................................................................................
CD_PCIE Modules Clock-Management Modes and Control ........................................................
CD_PCIE Modules Slave Clock-Management Modes and Control ................................................
PD_WKUPAON Modules Power Attributes ...........................................................................
PD_WKUPAON Memory Area Power Modes .........................................................................
PD_DSP1 Modules Power Attributes ..................................................................................
PD_DSP1 Logic Area Power Modes ...................................................................................
PD_DSP1 Memory Area Power Modes................................................................................
PD_DSP1 Power Modes Control Parameters ........................................................................
PD_DSP1 Power Modes Status Parameters .........................................................................
PD_CUSTEFUSE Modules Power Attributes .........................................................................
PD_CUSTEFUSE Logic Area Power Modes..........................................................................
PD_CUSTEFUSE Power Modes Control Parameters ...............................................................
PD_CUSTEFUSE Power Modes Status Parameters ................................................................
PD_MPU Module Power Attributes .....................................................................................
PD_MPU Logic Area Power Modes ....................................................................................
PD_MPU Memory Area Power Modes .................................................................................
PD_MPU Power Modes Control Parameters .........................................................................
PD_MPU Power Mode Status Parameters ............................................................................
MPU Allowed Low-Power Mode ........................................................................................
PD_IPU Module Power Attributes ......................................................................................
3-294. CD_RTC Modules Wake-Up Request
3-295.
3-296.
3-297.
3-298.
3-299.
3-300.
3-301.
3-302.
3-303.
3-304.
3-305.
3-306.
3-307.
3-308.
3-309.
3-310.
3-311.
3-312.
3-313.
3-314.
3-315.
3-316.
3-317.
3-318.
3-319.
3-320.
3-321.
3-322.
98
List of Tables
640
640
641
641
641
642
643
643
644
644
644
645
646
646
647
647
647
647
648
648
648
649
649
649
649
650
650
651
651
SPRUIC2D – January 2017 – Revised April 2019
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Copyright © 2017–2019, Texas Instruments Incorporated
www.ti.com
.....................................................................................
PD_IPU Memory Area Power Modes ..................................................................................
PD_IPU Power Modes Control Parameters ...........................................................................
PD_IPU Power Mode Status Parameters .............................................................................
PD_L3INIT Modules Power Attributes .................................................................................
PD_L3INIT Logic Area Power Modes ..................................................................................
PD_L3INIT Memory Area Power Modes...............................................................................
PD_L3INIT Power Modes Control Parameters .......................................................................
PD_L3INIT Power Modes Status Parameters ........................................................................
PD_IVA Modules Power Attributes .....................................................................................
PD_IVA Logic Area Power Modes......................................................................................
PD_IVA Memory Area Power Modes ..................................................................................
PD_IVA Power Modes Control Parameters ...........................................................................
PD_IVA Power Modes Status Parameters ............................................................................
PD_GPU Modules Power Attributes....................................................................................
PD_GPU Logic Area Power Modes ....................................................................................
PD_GPU Memory Area Power Modes .................................................................................
PD_GPU Power Modes Control Parameters..........................................................................
PD_GPU Power Mode Status Parameters ............................................................................
PD_DSS Modules Power Attributes ....................................................................................
PD_DSS Logic Area Power Modes ....................................................................................
PD_DSS Memory Area Power Modes .................................................................................
PD_DSS Power Modes Control Parameters ..........................................................................
PD_DSS Power Modes Status Parameters ...........................................................................
PD_CORE Modules Power Attributes..................................................................................
PD_CORE Logic Area Power Modes ..................................................................................
PD_CORE Memory Area Power Modes ...............................................................................
PD_CORE Power Modes Control Parameters ........................................................................
PD_CORE Power Mode Status Parameters ..........................................................................
PD_CAM Modules Power Attributes ...................................................................................
PD_CAM Logic Area Power Modes ....................................................................................
PD_CAM Memory Area Power Modes .................................................................................
PD_CAM Power Mode Control Parameters ...........................................................................
PD_CAM Power Modes Status Parameters ..........................................................................
PD_MPUAON Modules Power Attributes..............................................................................
PD_MMAON Module Power Attributes ................................................................................
PD_COREAON Module Power Attributes .............................................................................
PD_VPE Modules Power Attributes ....................................................................................
PD_VPE Logic Area Power Modes ....................................................................................
PD_VPE Memory Area Power Modes .................................................................................
PD_VPE Power Modes Control Parameters ..........................................................................
PD_VPE Power Modes Status Parameters ...........................................................................
PD_RTC Modules Power Attributes ....................................................................................
PD_RTC Logic Area Power Modes ....................................................................................
Wake-Up Sources During Device Low Power Mode .................................................................
Global Initialization of Surrounding Modules ..........................................................................
DPLL Global Initialization ................................................................................................
DPLL Recalibration Parameter Configuration .........................................................................
DPLL Synthesized Clock Parameter Configuration ..................................................................
3-323. PD_IPU Logic Area Power Modes
651
3-324.
652
3-325.
3-326.
3-327.
3-328.
3-329.
3-330.
3-331.
3-332.
3-333.
3-334.
3-335.
3-336.
3-337.
3-338.
3-339.
3-340.
3-341.
3-342.
3-343.
3-344.
3-345.
3-346.
3-347.
3-348.
3-349.
3-350.
3-351.
3-352.
3-353.
3-354.
3-355.
3-356.
3-357.
3-358.
3-359.
3-360.
3-361.
3-362.
3-363.
3-364.
3-365.
3-366.
3-367.
3-368.
3-369.
3-370.
3-371.
SPRUIC2D – January 2017 – Revised April 2019
Submit Documentation Feedback
Copyright © 2017–2019, Texas Instruments Incorporated
List of Tables
652
652
653
653
653
654
654
655
655
655
655
656
656
657
657
657
657
658
658
658
658
659
659
660
660
660
661
661
661
661
662
662
662
663
663
666
666
667
667
667
668
668
676
680
680
680
681
99
www.ti.com
3-372. DPLL Output Clock Parameter Configuration ......................................................................... 681
3-373. Register Call Summary for Sequence – DPLL Output Frequency Change ....................................... 683
3-374. Subprocess Call Summary for Sequence – DPLL Output Frequency Change ................................... 683
3-375. Global Initialization of Surrounding Modules .......................................................................... 683
3-376. Clock Domain Global Initialization ...................................................................................... 683
3-377. Clock Domain Sleep Transition and Troubleshooting ................................................................ 684
3-378. Enable/Disable Software-Programmable Static Dependency....................................................... 684
3-379. Power Domain Global Initialization ..................................................................................... 685
3-380. Forced Memory Area State Change With Power Domain ON ...................................................... 685
3-381. Forced Power Domain Low-Power State Transition ................................................................. 685
3-382. Not Supported Functionality (Registers and Bits) .................................................................... 686
3-383. PRCM L4_CFG Instance Summary .................................................................................... 699
3-384. PRCM L4_WKUP Instance Summary.................................................................................. 699
3-385. CM_CORE_AON__CKGEN Registers Mapping Summary ......................................................... 700
3-386. CM_CLKSEL_CORE ..................................................................................................... 703
.........................................................
CM_CLKSEL_ABE .......................................................................................................
Register Call Summary for Register CM_CLKSEL_ABE ............................................................
CM_DLL_CTRL ...........................................................................................................
Register Call Summary for Register CM_DLL_CTRL ................................................................
CM_CLKMODE_DPLL_CORE ..........................................................................................
Register Call Summary for Register CM_CLKMODE_DPLL_CORE ..............................................
CM_IDLEST_DPLL_CORE..............................................................................................
Register Call Summary for Register CM_IDLEST_DPLL_CORE ..................................................
CM_AUTOIDLE_DPLL_CORE..........................................................................................
Register Call Summary for Register CM_AUTOIDLE_DPLL_CORE ..............................................
CM_CLKSEL_DPLL_CORE .............................................................................................
Register Call Summary for Register CM_CLKSEL_DPLL_CORE .................................................
CM_DIV_M2_DPLL_CORE .............................................................................................
Register Call Summary for Register CM_DIV_M2_DPLL_CORE ..................................................
CM_DIV_M3_DPLL_CORE .............................................................................................
CM_DIV_H11_DPLL_CORE ............................................................................................
CM_DIV_H12_DPLL_CORE ............................................................................................
Register Call Summary for Register CM_DIV_H12_DPLL_CORE .................................................
CM_DIV_H13_DPLL_CORE ............................................................................................
Register Call Summary for Register CM_DIV_H13_DPLL_CORE .................................................
CM_DIV_H14_DPLL_CORE ............................................................................................
Register Call Summary for Register CM_DIV_H14_DPLL_CORE .................................................
CM_SSC_DELTAMSTEP_DPLL_CORE ..............................................................................
CM_SSC_MODFREQDIV_DPLL_CORE ..............................................................................
CM_DIV_H21_DPLL_CORE ............................................................................................
CM_DIV_H22_DPLL_CORE ............................................................................................
Register Call Summary for Register CM_DIV_H22_DPLL_CORE .................................................
CM_DIV_H23_DPLL_CORE ............................................................................................
Register Call Summary for Register CM_DIV_H23_DPLL_CORE .................................................
CM_DIV_H24_DPLL_CORE ............................................................................................
Register Call Summary for Register CM_DIV_H24_DPLL_CORE .................................................
CM_CLKMODE_DPLL_MPU ...........................................................................................
Register Call Summary for Register CM_CLKMODE_DPLL_MPU ................................................
3-387. Register Call Summary for Register CM_CLKSEL_CORE
3-388.
3-389.
3-390.
3-391.
3-392.
3-393.
3-394.
3-395.
3-396.
3-397.
3-398.
3-399.
3-400.
3-401.
3-402.
3-403.
3-404.
3-405.
3-406.
3-407.
3-408.
3-409.
3-410.
3-411.
3-412.
3-413.
3-414.
3-415.
3-416.
3-417.
3-418.
3-419.
3-420.
100
List of Tables
703
703
704
704
704
705
706
707
707
708
708
709
709
710
710
710
711
711
712
712
713
713
713
714
714
714
715
715
716
716
716
717
717
719
SPRUIC2D – January 2017 – Revised April 2019
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...............................................................................................
Register Call Summary for Register CM_IDLEST_DPLL_MPU ....................................................
CM_AUTOIDLE_DPLL_MPU ...........................................................................................
Register Call Summary for Register CM_AUTOIDLE_DPLL_MPU ................................................
CM_CLKSEL_DPLL_MPU ..............................................................................................
Register Call Summary for Register CM_CLKSEL_DPLL_MPU ...................................................
CM_DIV_M2_DPLL_MPU ...............................................................................................
Register Call Summary for Register CM_DIV_M2_DPLL_MPU ....................................................
CM_SSC_DELTAMSTEP_DPLL_MPU ................................................................................
CM_SSC_MODFREQDIV_DPLL_MPU ...............................................................................
CM_BYPCLK_DPLL_MPU ..............................................................................................
Register Call Summary for Register CM_BYPCLK_DPLL_MPU ...................................................
CM_CLKMODE_DPLL_IVA .............................................................................................
Register Call Summary for Register CM_CLKMODE_DPLL_IVA ..................................................
CM_IDLEST_DPLL_IVA .................................................................................................
Register Call Summary for Register CM_IDLEST_DPLL_IVA......................................................
CM_AUTOIDLE_DPLL_IVA .............................................................................................
Register Call Summary for Register CM_AUTOIDLE_DPLL_IVA..................................................
CM_CLKSEL_DPLL_IVA ................................................................................................
Register Call Summary for Register CM_CLKSEL_DPLL_IVA .....................................................
CM_DIV_M2_DPLL_IVA .................................................................................................
Register Call Summary for Register CM_DIV_M2_DPLL_IVA .....................................................
CM_DIV_M3_DPLL_IVA .................................................................................................
CM_SSC_DELTAMSTEP_DPLL_IVA .................................................................................
CM_SSC_MODFREQDIV_DPLL_IVA .................................................................................
CM_BYPCLK_DPLL_IVA ................................................................................................
Register Call Summary for Register CM_BYPCLK_DPLL_IVA ....................................................
CM_CLKMODE_DPLL_ABE ............................................................................................
Register Call Summary for Register CM_CLKMODE_DPLL_ABE .................................................
CM_IDLEST_DPLL_ABE ................................................................................................
Register Call Summary for Register CM_IDLEST_DPLL_ABE.....................................................
CM_AUTOIDLE_DPLL_ABE ............................................................................................
Register Call Summary for Register CM_AUTOIDLE_DPLL_ABE ................................................
CM_CLKSEL_DPLL_ABE ...............................................................................................
Register Call Summary for Register CM_CLKSEL_DPLL_ABE ....................................................
CM_DIV_M2_DPLL_ABE ................................................................................................
Register Call Summary for Register CM_DIV_M2_DPLL_ABE ....................................................
CM_DIV_M3_DPLL_ABE ................................................................................................
Register Call Summary for Register CM_DIV_M3_DPLL_ABE ....................................................
CM_SSC_DELTAMSTEP_DPLL_ABE ................................................................................
CM_SSC_MODFREQDIV_DPLL_ABE ................................................................................
CM_CLKMODE_DPLL_DDR ............................................................................................
Register Call Summary for Register CM_CLKMODE_DPLL_DDR ................................................
CM_IDLEST_DPLL_DDR................................................................................................
Register Call Summary for Register CM_IDLEST_DPLL_DDR ....................................................
CM_AUTOIDLE_DPLL_DDR ...........................................................................................
Register Call Summary for Register CM_AUTOIDLE_DPLL_DDR ................................................
CM_CLKSEL_DPLL_DDR ...............................................................................................
Register Call Summary for Register CM_CLKSEL_DPLL_DDR ...................................................
3-421. CM_IDLEST_DPLL_MPU
719
3-422.
719
3-423.
3-424.
3-425.
3-426.
3-427.
3-428.
3-429.
3-430.
3-431.
3-432.
3-433.
3-434.
3-435.
3-436.
3-437.
3-438.
3-439.
3-440.
3-441.
3-442.
3-443.
3-444.
3-445.
3-446.
3-447.
3-448.
3-449.
3-450.
3-451.
3-452.
3-453.
3-454.
3-455.
3-456.
3-457.
3-458.
3-459.
3-460.
3-461.
3-462.
3-463.
3-464.
3-465.
3-466.
3-467.
3-468.
3-469.
SPRUIC2D – January 2017 – Revised April 2019
Submit Documentation Feedback
Copyright © 2017–2019, Texas Instruments Incorporated
List of Tables
720
720
721
721
721
722
722
723
723
723
724
725
726
726
727
727
728
728
728
729
729
730
730
730
731
731
733
733
734
734
735
735
736
736
736
737
737
737
738
738
740
740
741
741
742
742
743
101
www.ti.com
3-470. CM_DIV_M2_DPLL_DDR ............................................................................................... 743
3-471. Register Call Summary for Register CM_DIV_M2_DPLL_DDR .................................................... 743
3-472. CM_DIV_M3_DPLL_DDR ............................................................................................... 744
3-473. CM_DIV_H11_DPLL_DDR .............................................................................................. 744
3-474. Register Call Summary for Register CM_DIV_H11_DPLL_DDR................................................... 745
3-475. CM_SSC_DELTAMSTEP_DPLL_DDR ................................................................................ 745
3-476. CM_SSC_MODFREQDIV_DPLL_DDR ................................................................................ 745
3-477. CM_CLKMODE_DPLL_DSP ............................................................................................ 746
................................................
CM_IDLEST_DPLL_DSP ................................................................................................
Register Call Summary for Register CM_IDLEST_DPLL_DSP ....................................................
CM_AUTOIDLE_DPLL_DSP ............................................................................................
Register Call Summary for Register CM_AUTOIDLE_DPLL_DSP ................................................
CM_CLKSEL_DPLL_DSP ...............................................................................................
Register Call Summary for Register CM_CLKSEL_DPLL_DSP ...................................................
CM_DIV_M2_DPLL_DSP................................................................................................
Register Call Summary for Register CM_DIV_M2_DPLL_DSP ....................................................
CM_DIV_M3_DPLL_DSP................................................................................................
Register Call Summary for Register CM_DIV_M3_DPLL_DSP ....................................................
CM_SSC_DELTAMSTEP_DPLL_DSP ................................................................................
CM_SSC_MODFREQDIV_DPLL_DSP ................................................................................
CM_BYPCLK_DPLL_DSP ...............................................................................................
Register Call Summary for Register CM_BYPCLK_DPLL_DSP ...................................................
CM_SHADOW_FREQ_CONFIG1 ......................................................................................
Register Call Summary for Register CM_SHADOW_FREQ_CONFIG1 ..........................................
CM_SHADOW_FREQ_CONFIG2 ......................................................................................
Register Call Summary for Register CM_SHADOW_FREQ_CONFIG2 ..........................................
CM_DYN_DEP_PRESCAL ..............................................................................................
Register Call Summary for Register CM_DYN_DEP_PRESCAL ..................................................
CM_RESTORE_ST.......................................................................................................
CM_CLKMODE_DPLL_EVE ............................................................................................
CM_IDLEST_DPLL_EVE ................................................................................................
CM_AUTOIDLE_DPLL_EVE ............................................................................................
CM_CLKSEL_DPLL_EVE ...............................................................................................
CM_DIV_M2_DPLL_EVE ................................................................................................
CM_DIV_M3_DPLL_EVE ................................................................................................
CM_SSC_DELTAMSTEP_DPLL_EVE ................................................................................
CM_SSC_MODFREQDIV_DPLL_EVE ................................................................................
CM_BYPCLK_DPLL_EVE ...............................................................................................
CM_CLKMODE_DPLL_GMAC .........................................................................................
Register Call Summary for Register CM_CLKMODE_DPLL_GMAC ..............................................
CM_IDLEST_DPLL_GMAC .............................................................................................
Register Call Summary for Register CM_IDLEST_DPLL_GMAC ..................................................
CM_AUTOIDLE_DPLL_GMAC .........................................................................................
Register Call Summary for Register CM_AUTOIDLE_DPLL_GMAC ..............................................
CM_CLKSEL_DPLL_GMAC ............................................................................................
Register Call Summary for Register CM_CLKSEL_DPLL_GMAC .................................................
CM_DIV_M2_DPLL_GMAC .............................................................................................
Register Call Summary for Register CM_DIV_M2_DPLL_GMAC..................................................
3-478. Register Call Summary for Register CM_CLKMODE_DPLL_DSP
3-479.
3-480.
3-481.
3-482.
3-483.
3-484.
3-485.
3-486.
3-487.
3-488.
3-489.
3-490.
3-491.
3-492.
3-493.
3-494.
3-495.
3-496.
3-497.
3-498.
3-499.
3-500.
3-501.
3-502.
3-503.
3-504.
3-505.
3-506.
3-507.
3-508.
3-509.
3-510.
3-511.
3-512.
3-513.
3-514.
3-515.
3-516.
3-517.
3-518.
102
List of Tables
747
748
748
749
749
750
750
750
751
751
751
752
752
752
753
753
754
754
755
755
756
756
757
758
759
760
761
761
762
762
762
763
764
765
765
766
766
767
767
768
768
SPRUIC2D – January 2017 – Revised April 2019
Submit Documentation Feedback
Copyright © 2017–2019, Texas Instruments Incorporated
www.ti.com
3-519. CM_DIV_M3_DPLL_GMAC ............................................................................................. 768
3-520. Register Call Summary for Register CM_DIV_M3_DPLL_GMAC.................................................. 769
3-521. CM_DIV_H11_DPLL_GMAC ............................................................................................ 769
3-522. Register Call Summary for Register CM_DIV_H11_DPLL_GMAC ................................................ 769
3-523. CM_DIV_H12_DPLL_GMAC ............................................................................................ 770
3-524. Register Call Summary for Register CM_DIV_H12_DPLL_GMAC ................................................ 770
3-525. CM_DIV_H13_DPLL_GMAC ............................................................................................ 770
3-526. Register Call Summary for Register CM_DIV_H13_DPLL_GMAC ................................................ 771
3-527. CM_DIV_H14_DPLL_GMAC ............................................................................................ 771
3-528. CM_SSC_DELTAMSTEP_DPLL_GMAC .............................................................................. 772
.............................................................................
CM_CLKMODE_DPLL_GPU ............................................................................................
Register Call Summary for Register CM_CLKMODE_DPLL_GPU ................................................
CM_IDLEST_DPLL_GPU................................................................................................
Register Call Summary for Register CM_IDLEST_DPLL_GPU ....................................................
CM_AUTOIDLE_DPLL_GPU ...........................................................................................
Register Call Summary for Register CM_AUTOIDLE_DPLL_GPU ................................................
CM_CLKSEL_DPLL_GPU ...............................................................................................
Register Call Summary for Register CM_CLKSEL_DPLL_GPU ...................................................
CM_DIV_M2_DPLL_GPU ...............................................................................................
Register Call Summary for Register CM_DIV_M2_DPLL_GPU ....................................................
CM_DIV_M3_DPLL_GPU ...............................................................................................
CM_SSC_DELTAMSTEP_DPLL_GPU ................................................................................
CM_SSC_MODFREQDIV_DPLL_GPU ................................................................................
CM_CORE_AON__DSP1 Registers Mapping Summary ............................................................
CM_DSP1_CLKSTCTRL ................................................................................................
Register Call Summary for Register CM_DSP1_CLKSTCTRL .....................................................
CM_DSP1_STATICDEP .................................................................................................
Register Call Summary for Register CM_DSP1_STATICDEP .....................................................
CM_DSP1_DYNAMICDEP ..............................................................................................
Register Call Summary for Register CM_DSP1_DYNAMICDEP...................................................
CM_DSP1_DSP1_CLKCTRL ...........................................................................................
Register Call Summary for Register CM_DSP1_DSP1_CLKCTRL ................................................
CM_CORE_AON__DSP2 Registers Mapping Summary ............................................................
CM_DSP2_CLKSTCTRL ................................................................................................
CM_DSP2_STATICDEP .................................................................................................
CM_DSP2_DYNAMICDEP ..............................................................................................
CM_DSP2_DSP2_CLKCTRL ...........................................................................................
CM_CORE_AON__EVE1 Registers Mapping Summary ............................................................
CM_EVE1_CLKSTCTRL ................................................................................................
CM_EVE1_STATICDEP .................................................................................................
CM_EVE1_EVE1_CLKCTRL ...........................................................................................
CM_CORE_AON__EVE2 Registers Mapping Summary ............................................................
CM_EVE2_CLKSTCTRL ................................................................................................
CM_EVE2_STATICDEP .................................................................................................
CM_EVE2_EVE2_CLKCTRL ...........................................................................................
CM_CORE_AON__EVE3 Registers Mapping Summary ............................................................
CM_EVE3_CLKSTCTRL ................................................................................................
CM_EVE3_STATICDEP .................................................................................................
3-529. CM_SSC_MODFREQDIV_DPLL_GMAC
772
3-530.
773
3-531.
3-532.
3-533.
3-534.
3-535.
3-536.
3-537.
3-538.
3-539.
3-540.
3-541.
3-542.
3-543.
3-544.
3-545.
3-546.
3-547.
3-548.
3-549.
3-550.
3-551.
3-552.
3-553.
3-554.
3-555.
3-556.
3-557.
3-558.
3-559.
3-560.
3-561.
3-562.
3-563.
3-564.
3-565.
3-566.
3-567.
SPRUIC2D – January 2017 – Revised April 2019
Submit Documentation Feedback
Copyright © 2017–2019, Texas Instruments Incorporated
List of Tables
774
775
775
776
776
777
777
778
778
778
779
779
780
780
781
781
783
783
784
784
785
785
785
786
788
789
789
790
791
791
792
793
794
795
795
796
797
103
www.ti.com
798
3-569.
798
3-570.
3-571.
3-572.
3-573.
3-574.
3-575.
3-576.
3-577.
3-578.
3-579.
3-580.
3-581.
3-582.
3-583.
3-584.
3-585.
3-586.
3-587.
3-588.
3-589.
3-590.
3-591.
3-592.
3-593.
3-594.
3-595.
3-596.
3-597.
3-598.
3-599.
3-600.
3-601.
3-602.
3-603.
3-604.
3-605.
3-606.
3-607.
3-608.
3-609.
3-610.
3-611.
3-612.
3-613.
3-614.
3-615.
3-616.
104
...........................................................................................
CM_CORE_AON__EVE4 Registers Mapping Summary ............................................................
CM_EVE4_CLKSTCTRL ................................................................................................
CM_EVE4_STATICDEP .................................................................................................
CM_EVE4_EVE4_CLKCTRL ...........................................................................................
CM_CORE_AON__INSTR Registers Mapping Summary ...........................................................
CMI_IDENTICATION .....................................................................................................
Register Call Summary for Register CMI_IDENTICATION .........................................................
CMI_SYS_CONFIG ......................................................................................................
Register Call Summary for Register CMI_SYS_CONFIG ...........................................................
CMI_STATUS .............................................................................................................
Register Call Summary for Register CMI_STATUS ..................................................................
CMI_CONFIGURATION .................................................................................................
Register Call Summary for Register CMI_CONFIGURATION ......................................................
CMI_CLASS_FILTERING ...............................................................................................
Register Call Summary for Register CMI_CLASS_FILTERING ....................................................
CMI_TRIGGERING .......................................................................................................
Register Call Summary for Register CMI_TRIGGERING ...........................................................
CMI_SAMPLING ..........................................................................................................
Register Call Summary for Register CMI_SAMPLING ..............................................................
CM_CORE_AON__IPU Registers Mapping Summary ..............................................................
CM_IPU1_CLKSTCTRL .................................................................................................
Register Call Summary for Register CM_IPU1_CLKSTCTRL ......................................................
CM_IPU1_STATICDEP ..................................................................................................
Register Call Summary for Register CM_IPU1_STATICDEP ......................................................
CM_IPU1_DYNAMICDEP ...............................................................................................
Register Call Summary for Register CM_IPU1_DYNAMICDEP ....................................................
CM_IPU1_IPU1_CLKCTRL .............................................................................................
Register Call Summary for Register CM_IPU1_IPU1_CLKCTRL ..................................................
CM_IPU_CLKSTCTRL ...................................................................................................
Register Call Summary for Register CM_IPU_CLKSTCTRL .......................................................
CM_IPU_MCASP1_CLKCTRL ..........................................................................................
Register Call Summary for Register CM_IPU_MCASP1_CLKCTRL ..............................................
CM_IPU_TIMER5_CLKCTRL ...........................................................................................
Register Call Summary for Register CM_IPU_TIMER5_CLKCTRL ...............................................
CM_IPU_TIMER6_CLKCTRL ...........................................................................................
Register Call Summary for Register CM_IPU_TIMER6_CLKCTRL ...............................................
CM_IPU_TIMER7_CLKCTRL ...........................................................................................
Register Call Summary for Register CM_IPU_TIMER7_CLKCTRL ...............................................
CM_IPU_TIMER8_CLKCTRL ...........................................................................................
Register Call Summary for Register CM_IPU_TIMER8_CLKCTRL ...............................................
CM_IPU_I2C5_CLKCTRL ...............................................................................................
Register Call Summary for Register CM_IPU_I2C5_CLKCTRL ....................................................
CM_IPU_UART6_CLKCTRL ............................................................................................
Register Call Summary for Register CM_IPU_UART6_CLKCTRL ................................................
CM_CORE_AON__MPU Registers Mapping Summary .............................................................
CM_MPU_CLKSTCTRL .................................................................................................
Register Call Summary for Register CM_MPU_CLKSTCTRL ......................................................
CM_MPU_STATICDEP ..................................................................................................
3-568. CM_EVE3_EVE3_CLKCTRL
List of Tables
799
800
800
801
802
802
802
802
803
803
803
803
804
804
805
805
805
805
806
806
807
807
809
810
810
810
811
812
813
814
815
815
816
817
818
818
819
819
820
820
821
821
822
822
823
823
824
SPRUIC2D – January 2017 – Revised April 2019
Submit Documentation Feedback
Copyright © 2017–2019, Texas Instruments Incorporated
www.ti.com
......................................................
CM_MPU_DYNAMICDEP ...............................................................................................
Register Call Summary for Register CM_MPU_DYNAMICDEP ....................................................
CM_MPU_MPU_CLKCTRL .............................................................................................
Register Call Summary for Register CM_MPU_MPU_CLKCTRL ..................................................
CM_MPU_MPU_MPU_DBG_CLKCTRL ..............................................................................
Register Call Summary for Register CM_MPU_MPU_MPU_DBG_CLKCTRL ...................................
CM_CORE_AON__OCP_SOCKET Registers Mapping Summary ................................................
REVISION_CM_CORE_AON ...........................................................................................
Register Call Summary for Register REVISION_CM_CORE_AON................................................
CM_CM_CORE_AON_PROFILING_CLKCTRL ......................................................................
Register Call Summary for Register CM_CM_CORE_AON_PROFILING_CLKCTRL ..........................
CM_CORE_AON_DEBUG_OUT .......................................................................................
Register Call Summary for Register CM_CORE_AON_DEBUG_OUT ............................................
CM_CORE_AON_DEBUG_CFG0 ......................................................................................
Register Call Summary for Register CM_CORE_AON_DEBUG_CFG0 ..........................................
CM_CORE_AON_DEBUG_CFG1 ......................................................................................
Register Call Summary for Register CM_CORE_AON_DEBUG_CFG1 ..........................................
CM_CORE_AON_DEBUG_CFG2 ......................................................................................
Register Call Summary for Register CM_CORE_AON_DEBUG_CFG2 ..........................................
CM_CORE_AON_DEBUG_CFG3 ......................................................................................
Register Call Summary for Register CM_CORE_AON_DEBUG_CFG3 ..........................................
CM_CORE_AON__RESTORE Registers Mapping Summary ......................................................
CM_CLKSEL_CORE_RESTORE ......................................................................................
Register Call Summary for Register CM_CLKSEL_CORE_RESTORE ...........................................
CM_DIV_M2_DPLL_CORE_RESTORE ...............................................................................
Register Call Summary for Register CM_DIV_M2_DPLL_CORE_RESTORE ...................................
CM_DIV_M3_DPLL_CORE_RESTORE ...............................................................................
CM_DIV_H11_DPLL_CORE_RESTORE..............................................................................
CM_DIV_H12_DPLL_CORE_RESTORE..............................................................................
Register Call Summary for Register CM_DIV_H12_DPLL_CORE_RESTORE ..................................
CM_DIV_H13_DPLL_CORE_RESTORE..............................................................................
Register Call Summary for Register CM_DIV_H13_DPLL_CORE_RESTORE ..................................
CM_DIV_H14_DPLL_CORE_RESTORE..............................................................................
Register Call Summary for Register CM_DIV_H14_DPLL_CORE_RESTORE ..................................
CM_DIV_H21_DPLL_CORE_RESTORE..............................................................................
CM_DIV_H22_DPLL_CORE_RESTORE..............................................................................
Register Call Summary for Register CM_DIV_H22_DPLL_CORE_RESTORE ..................................
CM_DIV_H23_DPLL_CORE_RESTORE..............................................................................
Register Call Summary for Register CM_DIV_H23_DPLL_CORE_RESTORE ..................................
CM_DIV_H24_DPLL_CORE_RESTORE..............................................................................
Register Call Summary for Register CM_DIV_H24_DPLL_CORE_RESTORE ..................................
CM_CLKSEL_DPLL_CORE_RESTORE ..............................................................................
Register Call Summary for Register CM_CLKSEL_DPLL_CORE_RESTORE ...................................
CM_SSC_DELTAMSTEP_DPLL_CORE_RESTORE ...............................................................
CM_SSC_MODFREQDIV_DPLL_CORE_RESTORE ...............................................................
CM_CLKMODE_DPLL_CORE_RESTORE ...........................................................................
Register Call Summary for Register CM_CLKMODE_DPLL_CORE_RESTORE ................................
CM_SHADOW_FREQ_CONFIG2_RESTORE .......................................................................
3-617. Register Call Summary for Register CM_MPU_STATICDEP
3-618.
3-619.
3-620.
3-621.
3-622.
3-623.
3-624.
3-625.
3-626.
3-627.
3-628.
3-629.
3-630.
3-631.
3-632.
3-633.
3-634.
3-635.
3-636.
3-637.
3-638.
3-639.
3-640.
3-641.
3-642.
3-643.
3-644.
3-645.
3-646.
3-647.
3-648.
3-649.
3-650.
3-651.
3-652.
3-653.
3-654.
3-655.
3-656.
3-657.
3-658.
3-659.
3-660.
3-661.
3-662.
3-663.
3-664.
3-665.
SPRUIC2D – January 2017 – Revised April 2019
Submit Documentation Feedback
Copyright © 2017–2019, Texas Instruments Incorporated
List of Tables
826
826
826
827
827
828
828
828
829
829
829
830
830
830
831
831
831
831
832
832
832
832
833
834
834
834
834
834
835
835
835
835
835
836
836
836
836
836
837
837
837
837
837
838
838
838
838
839
839
105
www.ti.com
3-666. Register Call Summary for Register CM_SHADOW_FREQ_CONFIG2_RESTORE ............................ 839
3-667. CM_SHADOW_FREQ_CONFIG1_RESTORE
.......................................................................
839
3-668. Register Call Summary for Register CM_SHADOW_FREQ_CONFIG1_RESTORE ............................ 839
3-669. CM_AUTOIDLE_DPLL_CORE_RESTORE ........................................................................... 840
3-670. Register Call Summary for Register CM_AUTOIDLE_DPLL_CORE_RESTORE................................ 840
3-671. CM_MPU_CLKSTCTRL_RESTORE ................................................................................... 840
840
3-673. CM_CM_CORE_AON_PROFILING_CLKCTRL_RESTORE
840
3-674.
841
3-675.
3-676.
3-677.
3-678.
3-679.
3-680.
3-681.
3-682.
3-683.
3-684.
3-685.
3-686.
3-687.
3-688.
3-689.
3-690.
3-691.
3-692.
3-693.
3-694.
3-695.
3-696.
3-697.
3-698.
3-699.
3-700.
3-701.
3-702.
3-703.
3-704.
3-705.
3-706.
3-707.
3-708.
3-709.
3-710.
3-711.
3-712.
3-713.
3-714.
106
.......................................
.......................................................
Register Call Summary for Register CM_CM_CORE_AON_PROFILING_CLKCTRL_RESTORE ............
CM_DYN_DEP_PRESCAL_RESTORE ...............................................................................
Register Call Summary for Register CM_DYN_DEP_PRESCAL_RESTORE ....................................
CM_CORE_AON__RTC Registers Mapping Summary .............................................................
CM_RTC_CLKSTCTRL ..................................................................................................
Register Call Summary for Register CM_RTC_CLKSTCTRL ......................................................
CM_RTC_RTCSS_CLKCTRL ...........................................................................................
Register Call Summary for Register CM_RTC_RTCSS_CLKCTRL ...............................................
CM_CORE_AON__VPE Registers Mapping Summary .............................................................
CM_VPE_CLKSTCTRL ..................................................................................................
Register Call Summary for Register CM_VPE_CLKSTCTRL ......................................................
CM_VPE_VPE_CLKCTRL ..............................................................................................
Register Call Summary for Register CM_VPE_VPE_CLKCTRL ...................................................
CM_VPE_STATICDEP...................................................................................................
Register Call Summary for Register CM_VPE_STATICDEP .......................................................
CM_CORE__CAM Registers Mapping Summary ....................................................................
CM_CAM_CLKSTCTRL .................................................................................................
Register Call Summary for Register CM_CAM_CLKSTCTRL ......................................................
CM_CAM_STATICDEP ..................................................................................................
Register Call Summary for Register CM_CAM_STATICDEP ......................................................
CM_CAM_VIP1_CLKCTRL .............................................................................................
Register Call Summary for Register CM_CAM_VIP1_CLKCTRL ..................................................
CM_CAM_CAL_CLKCTRL ..............................................................................................
Register Call Summary for Register CM_CAM_CAL_CLKCTRL...................................................
CM_CAM_VIP3_CLKCTRL .............................................................................................
CM_CAM_LVDSRX_CLKCTRL ........................................................................................
CM_CAM_CSI1_CLKCTRL .............................................................................................
CM_CAM_CSI2_CLKCTRL .............................................................................................
CM_CORE__CKGEN Registers Mapping Summary ................................................................
CM_CLKSEL_USB_60MHZ .............................................................................................
Register Call Summary for Register CM_CLKSEL_USB_60MHZ .................................................
CM_CLKMODE_DPLL_PER ............................................................................................
Register Call Summary for Register CM_CLKMODE_DPLL_PER ................................................
CM_IDLEST_DPLL_PER ................................................................................................
Register Call Summary for Register CM_IDLEST_DPLL_PER ....................................................
CM_AUTOIDLE_DPLL_PER ............................................................................................
Register Call Summary for Register CM_AUTOIDLE_DPLL_PER ................................................
CM_CLKSEL_DPLL_PER ...............................................................................................
Register Call Summary for Register CM_CLKSEL_DPLL_PER ...................................................
CM_DIV_M2_DPLL_PER................................................................................................
Register Call Summary for Register CM_DIV_M2_DPLL_PER ....................................................
3-672. Register Call Summary for Register CM_MPU_CLKSTCTRL_RESTORE
List of Tables
841
841
841
842
842
843
843
843
844
844
845
845
846
846
846
847
848
848
849
850
850
851
851
852
853
853
854
855
856
856
857
858
859
859
860
860
861
861
861
862
SPRUIC2D – January 2017 – Revised April 2019
Submit Documentation Feedback
Copyright © 2017–2019, Texas Instruments Incorporated
www.ti.com
3-715. CM_DIV_M3_DPLL_PER................................................................................................ 862
3-716. CM_DIV_H11_DPLL_PER
..............................................................................................
863
3-717. Register Call Summary for Register CM_DIV_H11_DPLL_PER ................................................... 863
..............................................................................................
Register Call Summary for Register CM_DIV_H12_DPLL_PER ...................................................
CM_DIV_H13_DPLL_PER ..............................................................................................
Register Call Summary for Register CM_DIV_H13_DPLL_PER ...................................................
CM_DIV_H14_DPLL_PER ..............................................................................................
Register Call Summary for Register CM_DIV_H14_DPLL_PER ...................................................
CM_SSC_DELTAMSTEP_DPLL_PER ................................................................................
CM_SSC_MODFREQDIV_DPLL_PER ................................................................................
CM_CLKMODE_DPLL_USB ............................................................................................
Register Call Summary for Register CM_CLKMODE_DPLL_USB ................................................
CM_IDLEST_DPLL_USB ................................................................................................
Register Call Summary for Register CM_IDLEST_DPLL_USB ....................................................
CM_AUTOIDLE_DPLL_USB ............................................................................................
Register Call Summary for Register CM_AUTOIDLE_DPLL_USB ................................................
CM_CLKSEL_DPLL_USB ...............................................................................................
Register Call Summary for Register CM_CLKSEL_DPLL_USB ...................................................
CM_DIV_M2_DPLL_USB................................................................................................
Register Call Summary for Register CM_DIV_M2_DPLL_USB ....................................................
CM_SSC_DELTAMSTEP_DPLL_USB ................................................................................
CM_SSC_MODFREQDIV_DPLL_USB ................................................................................
CM_CLKDCOLDO_DPLL_USB ........................................................................................
Register Call Summary for Register CM_CLKDCOLDO_DPLL_USB .............................................
CM_CLKMODE_DPLL_PCIE_REF ....................................................................................
Register Call Summary for Register CM_CLKMODE_DPLL_PCIE_REF .........................................
CM_IDLEST_DPLL_PCIE_REF ........................................................................................
Register Call Summary for Register CM_IDLEST_DPLL_PCIE_REF .............................................
CM_AUTOIDLE_DPLL_PCIE_REF ....................................................................................
Register Call Summary for Register CM_AUTOIDLE_DPLL_PCIE_REF .........................................
CM_CLKSEL_DPLL_PCIE_REF .......................................................................................
Register Call Summary for Register CM_CLKSEL_DPLL_PCIE_REF ............................................
CM_DIV_M2_DPLL_PCIE_REF ........................................................................................
Register Call Summary for Register CM_DIV_M2_DPLL_PCIE_REF ............................................
CM_SSC_DELTAMSTEP_DPLL_PCIE_REF .........................................................................
CM_SSC_MODFREQDIV_DPLL_PCIE_REF ........................................................................
CM_CLKMODE_APLL_PCIE ...........................................................................................
Register Call Summary for Register CM_CLKMODE_APLL_PCIE ................................................
CM_IDLEST_APLL_PCIE ...............................................................................................
Register Call Summary for Register CM_IDLEST_APLL_PCIE ....................................................
CM_DIV_M2_APLL_PCIE ...............................................................................................
Register Call Summary for Register CM_DIV_M2_APLL_PCIE ...................................................
CM_CLKVCOLDO_APLL_PCIE ........................................................................................
Register Call Summary for Register CM_CLKVCOLDO_APLL_PCIE.............................................
CM_CORE__COREAON Registers Mapping Summary ............................................................
CM_COREAON_CLKSTCTRL ..........................................................................................
Register Call Summary for Register CM_COREAON_CLKSTCTRL ..............................................
CM_COREAON_SMARTREFLEX_MPU_CLKCTRL ................................................................
3-718. CM_DIV_H12_DPLL_PER
3-719.
3-720.
3-721.
3-722.
3-723.
3-724.
3-725.
3-726.
3-727.
3-728.
3-729.
3-730.
3-731.
3-732.
3-733.
3-734.
3-735.
3-736.
3-737.
3-738.
3-739.
3-740.
3-741.
3-742.
3-743.
3-744.
3-745.
3-746.
3-747.
3-748.
3-749.
3-750.
3-751.
3-752.
3-753.
3-754.
3-755.
3-756.
3-757.
3-758.
3-759.
3-760.
3-761.
3-762.
3-763.
SPRUIC2D – January 2017 – Revised April 2019
Submit Documentation Feedback
Copyright © 2017–2019, Texas Instruments Incorporated
List of Tables
863
864
864
864
865
865
865
866
866
867
867
868
868
869
869
870
870
870
870
871
871
872
872
873
873
873
874
874
874
875
875
876
876
876
877
878
878
878
878
879
879
879
880
881
882
883
107
www.ti.com
..............................................................
CM_COREAON_USB_PHY1_CORE_CLKCTRL ....................................................................
Register Call Summary for Register CM_COREAON_USB_PHY1_CORE_CLKCTRL .........................
CM_COREAON_IO_SRCOMP_CLKCTRL ...........................................................................
CM_COREAON_SMARTREFLEX_GPU_CLKCTRL ................................................................
CM_COREAON_SMARTREFLEX_DSPEVE_CLKCTRL ...........................................................
CM_COREAON_SMARTREFLEX_IVAHD_CLKCTRL ..............................................................
CM_COREAON_USB_PHY2_CORE_CLKCTRL ....................................................................
Register Call Summary for Register CM_COREAON_USB_PHY2_CORE_CLKCTRL .........................
CM_COREAON_USB_PHY3_CORE_CLKCTRL ....................................................................
Register Call Summary for Register CM_COREAON_USB_PHY3_CORE_CLKCTRL .........................
CM_COREAON_CLKOUTMUX1_CLKCTRL .........................................................................
Register Call Summary for Register CM_COREAON_CLKOUTMUX1_CLKCTRL ..............................
CM_COREAON_CLKOUTMUX2_CLKCTRL .........................................................................
Register Call Summary for Register CM_COREAON_CLKOUTMUX2_CLKCTRL ..............................
CM_COREAON_L3INIT_60M_GFCLK_CLKCTRL ..................................................................
Register Call Summary for Register CM_COREAON_L3INIT_60M_GFCLK_CLKCTRL .......................
CM_COREAON_ABE_GICLK_CLKCTRL .............................................................................
Register Call Summary for Register CM_COREAON_ABE_GICLK_CLKCTRL .................................
CM_CORE__CORE Registers Mapping Summary ..................................................................
CM_L3MAIN1_CLKSTCTRL ............................................................................................
Register Call Summary for Register CM_L3MAIN1_CLKSTCTRL .................................................
CM_L3MAIN1_DYNAMICDEP ..........................................................................................
Register Call Summary for Register CM_L3MAIN1_DYNAMICDEP ..............................................
CM_L3MAIN1_L3_MAIN_1_CLKCTRL ................................................................................
Register Call Summary for Register CM_L3MAIN1_L3_MAIN_1_CLKCTRL ....................................
CM_L3MAIN1_GPMC_CLKCTRL ......................................................................................
Register Call Summary for Register CM_L3MAIN1_GPMC_CLKCTRL ..........................................
CM_L3MAIN1_MMU_EDMA_CLKCTRL ..............................................................................
Register Call Summary for Register CM_L3MAIN1_MMU_EDMA_CLKCTRL ...................................
CM_L3MAIN1_MMU_PCIESS_CLKCTRL ............................................................................
Register Call Summary for Register CM_L3MAIN1_MMU_PCIESS_CLKCTRL .................................
CM_L3MAIN1_OCMC_RAM1_CLKCTRL .............................................................................
Register Call Summary for Register CM_L3MAIN1_OCMC_RAM1_CLKCTRL .................................
CM_L3MAIN1_OCMC_RAM2_CLKCTRL .............................................................................
CM_L3MAIN1_OCMC_RAM3_CLKCTRL .............................................................................
CM_L3MAIN1_OCMC_ROM_CLKCTRL ..............................................................................
CM_L3MAIN1_TPCC_CLKCTRL .......................................................................................
Register Call Summary for Register CM_L3MAIN1_TPCC_CLKCTRL ...........................................
CM_L3MAIN1_TPTC1_CLKCTRL .....................................................................................
Register Call Summary for Register CM_L3MAIN1_TPTC1_CLKCTRL ..........................................
CM_L3MAIN1_TPTC2_CLKCTRL .....................................................................................
Register Call Summary for Register CM_L3MAIN1_TPTC2_CLKCTRL ..........................................
CM_L3MAIN1_VCP1_CLKCTRL .......................................................................................
Register Call Summary for Register CM_L3MAIN1_VCP1_CLKCTRL............................................
CM_L3MAIN1_VCP2_CLKCTRL .......................................................................................
Register Call Summary for Register CM_L3MAIN1_VCP2_CLKCTRL............................................
CM_L3MAIN1_SPARE_CME_CLKCTRL .............................................................................
CM_L3MAIN1_SPARE_HDMI_CLKCTRL ............................................................................
3-764. CM_COREAON_SMARTREFLEX_CORE_CLKCTRL
3-765.
3-766.
3-767.
3-768.
3-769.
3-770.
3-771.
3-772.
3-773.
3-774.
3-775.
3-776.
3-777.
3-778.
3-779.
3-780.
3-781.
3-782.
3-783.
3-784.
3-785.
3-786.
3-787.
3-788.
3-789.
3-790.
3-791.
3-792.
3-793.
3-794.
3-795.
3-796.
3-797.
3-798.
3-799.
3-800.
3-801.
3-802.
3-803.
3-804.
3-805.
3-806.
3-807.
3-808.
3-809.
3-810.
3-811.
3-812.
108
List of Tables
883
884
884
885
885
886
887
887
888
888
888
889
889
889
890
890
890
891
891
891
893
894
894
895
896
896
896
897
897
898
898
898
899
899
899
900
901
901
902
902
903
903
904
904
905
905
905
906
906
SPRUIC2D – January 2017 – Revised April 2019
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Copyright © 2017–2019, Texas Instruments Incorporated
www.ti.com
..............................................................................
CM_L3MAIN1_SPARE_IVA2_CLKCTRL..............................................................................
CM_L3MAIN1_SPARE_SATA2_CLKCTRL ...........................................................................
CM_L3MAIN1_SPARE_UNKNOWN4_CLKCTRL ....................................................................
CM_L3MAIN1_SPARE_UNKNOWN5_CLKCTRL ....................................................................
CM_L3MAIN1_SPARE_UNKNOWN6_CLKCTRL ....................................................................
CM_L3MAIN1_SPARE_VIDEOPLL1_CLKCTRL .....................................................................
CM_L3MAIN1_SPARE_VIDEOPLL2_CLKCTRL .....................................................................
CM_L3MAIN1_SPARE_VIDEOPLL3_CLKCTRL .....................................................................
CM_IPU2_CLKSTCTRL .................................................................................................
Register Call Summary for Register CM_IPU2_CLKSTCTRL ......................................................
CM_IPU2_STATICDEP ..................................................................................................
Register Call Summary for Register CM_IPU2_STATICDEP ......................................................
CM_IPU2_DYNAMICDEP ...............................................................................................
Register Call Summary for Register CM_IPU2_DYNAMICDEP ....................................................
CM_IPU2_IPU2_CLKCTRL .............................................................................................
Register Call Summary for Register CM_IPU2_IPU2_CLKCTRL ..................................................
CM_DMA_CLKSTCTRL .................................................................................................
Register Call Summary for Register CM_DMA_CLKSTCTRL ......................................................
CM_DMA_STATICDEP ..................................................................................................
Register Call Summary for Register CM_DMA_STATICDEP ......................................................
CM_DMA_DYNAMICDEP ...............................................................................................
Register Call Summary for Register CM_DMA_DYNAMICDEP ....................................................
CM_DMA_DMA_SYSTEM_CLKCTRL .................................................................................
Register Call Summary for Register CM_DMA_DMA_SYSTEM_CLKCTRL .....................................
CM_EMIF_CLKSTCTRL .................................................................................................
Register Call Summary for Register CM_EMIF_CLKSTCTRL .....................................................
CM_EMIF_DMM_CLKCTRL ............................................................................................
Register Call Summary for Register CM_EMIF_DMM_CLKCTRL .................................................
CM_EMIF_EMIF_OCP_FW_CLKCTRL ...............................................................................
Register Call Summary for Register CM_EMIF_EMIF_OCP_FW_CLKCTRL ....................................
CM_EMIF_EMIF1_CLKCTRL ...........................................................................................
Register Call Summary for Register CM_EMIF_EMIF1_CLKCTRL ...............................................
CM_EMIF_EMIF2_CLKCTRL ...........................................................................................
CM_EMIF_EMIF_DLL_CLKCTRL ......................................................................................
Register Call Summary for Register CM_EMIF_EMIF_DLL_CLKCTRL ..........................................
CM_ATL_ATL_CLKCTRL ...............................................................................................
Register Call Summary for Register CM_ATL_ATL_CLKCTRL ....................................................
CM_ATL_CLKSTCTRL ..................................................................................................
Register Call Summary for Register CM_ATL_CLKSTCTRL .......................................................
CM_L4CFG_CLKSTCTRL ...............................................................................................
Register Call Summary for Register CM_L4CFG_CLKSTCTRL ...................................................
CM_L4CFG_DYNAMICDEP ............................................................................................
Register Call Summary for Register CM_L4CFG_DYNAMICDEP .................................................
CM_L4CFG_L4_CFG_CLKCTRL ......................................................................................
Register Call Summary for Register CM_L4CFG_L4_CFG_CLKCTRL ...........................................
CM_L4CFG_SPINLOCK_CLKCTRL ...................................................................................
Register Call Summary for Register CM_L4CFG_SPINLOCK_CLKCTRL .......................................
CM_L4CFG_MAILBOX1_CLKCTRL ...................................................................................
3-813. CM_L3MAIN1_SPARE_ICM_CLKCTRL
3-814.
3-815.
3-816.
3-817.
3-818.
3-819.
3-820.
3-821.
3-822.
3-823.
3-824.
3-825.
3-826.
3-827.
3-828.
3-829.
3-830.
3-831.
3-832.
3-833.
3-834.
3-835.
3-836.
3-837.
3-838.
3-839.
3-840.
3-841.
3-842.
3-843.
3-844.
3-845.
3-846.
3-847.
3-848.
3-849.
3-850.
3-851.
3-852.
3-853.
3-854.
3-855.
3-856.
3-857.
3-858.
3-859.
3-860.
3-861.
SPRUIC2D – January 2017 – Revised April 2019
Submit Documentation Feedback
Copyright © 2017–2019, Texas Instruments Incorporated
List of Tables
907
908
908
909
910
910
911
912
912
913
914
914
916
916
917
917
917
918
918
919
920
920
921
921
921
922
922
923
923
923
924
924
925
925
926
926
927
927
928
929
929
930
930
931
931
931
932
932
932
109
www.ti.com
3-862. Register Call Summary for Register CM_L4CFG_MAILBOX1_CLKCTRL ........................................ 933
3-863. CM_L4CFG_SAR_ROM_CLKCTRL ................................................................................... 933
3-864. CM_L4CFG_OCP2SCP2_CLKCTRL .................................................................................. 934
3-865. Register Call Summary for Register CM_L4CFG_OCP2SCP2_CLKCTRL ....................................... 934
3-866. CM_L4CFG_MAILBOX2_CLKCTRL ................................................................................... 934
3-867. Register Call Summary for Register CM_L4CFG_MAILBOX2_CLKCTRL ........................................ 935
3-868. CM_L4CFG_MAILBOX3_CLKCTRL ................................................................................... 935
3-869. Register Call Summary for Register CM_L4CFG_MAILBOX3_CLKCTRL ........................................ 936
3-870. CM_L4CFG_MAILBOX4_CLKCTRL ................................................................................... 936
3-871. Register Call Summary for Register CM_L4CFG_MAILBOX4_CLKCTRL ........................................ 936
3-872. CM_L4CFG_MAILBOX5_CLKCTRL ................................................................................... 937
3-873. Register Call Summary for Register CM_L4CFG_MAILBOX5_CLKCTRL ........................................ 937
3-874. CM_L4CFG_MAILBOX6_CLKCTRL ................................................................................... 937
3-875. Register Call Summary for Register CM_L4CFG_MAILBOX6_CLKCTRL ........................................ 938
3-876. CM_L4CFG_MAILBOX7_CLKCTRL ................................................................................... 938
3-877. Register Call Summary for Register CM_L4CFG_MAILBOX7_CLKCTRL ........................................ 939
3-878. CM_L4CFG_MAILBOX8_CLKCTRL ................................................................................... 939
3-879. Register Call Summary for Register CM_L4CFG_MAILBOX8_CLKCTRL ........................................ 939
3-880. CM_L4CFG_MAILBOX9_CLKCTRL ................................................................................... 940
3-881. Register Call Summary for Register CM_L4CFG_MAILBOX9_CLKCTRL ........................................ 940
3-882. CM_L4CFG_MAILBOX10_CLKCTRL.................................................................................. 940
3-883. Register Call Summary for Register CM_L4CFG_MAILBOX10_CLKCTRL ...................................... 941
3-884. CM_L4CFG_MAILBOX11_CLKCTRL.................................................................................. 941
3-885. Register Call Summary for Register CM_L4CFG_MAILBOX11_CLKCTRL ...................................... 942
3-886. CM_L4CFG_MAILBOX12_CLKCTRL.................................................................................. 942
3-887. Register Call Summary for Register CM_L4CFG_MAILBOX12_CLKCTRL ...................................... 942
3-888. CM_L4CFG_MAILBOX13_CLKCTRL.................................................................................. 943
3-889. Register Call Summary for Register CM_L4CFG_MAILBOX13_CLKCTRL ...................................... 943
3-890. CM_L4CFG_SPARE_SMARTREFLEX_RTC_CLKCTRL ........................................................... 943
3-891. CM_L4CFG_SPARE_SMARTREFLEX_SDRAM_CLKCTRL ....................................................... 944
945
3-893.
945
3-894.
3-895.
3-896.
3-897.
3-898.
3-899.
3-900.
3-901.
3-902.
3-903.
3-904.
3-905.
3-906.
3-907.
3-908.
3-909.
3-910.
110
........................................................
CM_L4CFG_IO_DELAY_BLOCK_CLKCTRL .........................................................................
CM_L3INSTR_CLKSTCTRL ............................................................................................
Register Call Summary for Register CM_L3INSTR_CLKSTCTRL .................................................
CM_L3INSTR_L3_MAIN_2_CLKCTRL ................................................................................
Register Call Summary for Register CM_L3INSTR_L3_MAIN_2_CLKCTRL ....................................
CM_L3INSTR_L3_INSTR_CLKCTRL ..................................................................................
Register Call Summary for Register CM_L3INSTR_L3_INSTR_CLKCTRL ......................................
CM_L3INSTR_OCP_WP_NOC_CLKCTRL ...........................................................................
Register Call Summary for Register CM_L3INSTR_OCP_WP_NOC_CLKCTRL................................
CM_L3INSTR_DLL_AGING_CLKCTRL ...............................................................................
Register Call Summary for Register CM_L3INSTR_DLL_AGING_CLKCTRL....................................
CM_L3INSTR_CTRL_MODULE_BANDGAP_CLKCTRL ...........................................................
Register Call Summary for Register CM_L3INSTR_CTRL_MODULE_BANDGAP_CLKCTRL ................
CM_CORE__CUSTEFUSE Registers Mapping Summary ..........................................................
CM_CUSTEFUSE_CLKSTCTRL .......................................................................................
Register Call Summary for Register CM_CUSTEFUSE_CLKSTCTRL............................................
CM_CUSTEFUSE_EFUSE_CTRL_CUST_CLKCTRL...............................................................
Register Call Summary for Register CM_CUSTEFUSE_EFUSE_CTRL_CUST_CLKCTRL ...................
3-892. CM_L4CFG_SPARE_SMARTREFLEX_WKUP_CLKCTRL
List of Tables
946
947
947
948
948
948
949
949
950
950
950
951
951
952
953
953
953
SPRUIC2D – January 2017 – Revised April 2019
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www.ti.com
3-911. CM_CORE__DSS Registers Mapping Summary..................................................................... 954
3-912. CM_DSS_CLKSTCTRL .................................................................................................. 954
......................................................
..................................................................................................
Register Call Summary for Register CM_DSS_STATICDEP .......................................................
CM_DSS_DYNAMICDEP................................................................................................
Register Call Summary for Register CM_DSS_DYNAMICDEP ....................................................
CM_DSS_DSS_CLKCTRL ..............................................................................................
Register Call Summary for Register CM_DSS_DSS_CLKCTRL ...................................................
CM_DSS_BB2D_CLKCTRL .............................................................................................
Register Call Summary for Register CM_DSS_BB2D_CLKCTRL .................................................
CM_DSS_SDVENC_CLKCTRL ........................................................................................
CM_CORE__GPU Registers Mapping Summary ....................................................................
CM_GPU_CLKSTCTRL .................................................................................................
Register Call Summary for Register CM_GPU_CLKSTCTRL ......................................................
CM_GPU_STATICDEP ..................................................................................................
Register Call Summary for Register CM_GPU_STATICDEP .......................................................
CM_GPU_DYNAMICDEP ...............................................................................................
Register Call Summary for Register CM_GPU_DYNAMICDEP ....................................................
CM_GPU_GPU_CLKCTRL..............................................................................................
Register Call Summary for Register CM_GPU_GPU_CLKCTRL ..................................................
CM_CORE__IVA Registers Mapping Summary ......................................................................
CM_IVA_CLKSTCTRL ...................................................................................................
Register Call Summary for Register CM_IVA_CLKSTCTRL........................................................
CM_IVA_STATICDEP....................................................................................................
Register Call Summary for Register CM_IVA_STATICDEP ........................................................
CM_IVA_DYNAMICDEP .................................................................................................
Register Call Summary for Register CM_IVA_DYNAMICDEP .....................................................
CM_IVA_IVA_CLKCTRL.................................................................................................
Register Call Summary for Register CM_IVA_IVA_CLKCTRL .....................................................
CM_IVA_SL2_CLKCTRL ................................................................................................
Register Call Summary for Register CM_IVA_SL2_CLKCTRL .....................................................
CM_CORE__L3INIT Registers Mapping Summary ..................................................................
CM_L3INIT_CLKSTCTRL ...............................................................................................
Register Call Summary for Register CM_L3INIT_CLKSTCTRL ....................................................
CM_L3INIT_STATICDEP ................................................................................................
Register Call Summary for Register CM_L3INIT_STATICDEP ....................................................
CM_L3INIT_DYNAMICDEP .............................................................................................
Register Call Summary for Register CM_L3INIT_DYNAMICDEP..................................................
CM_L3INIT_MMC1_CLKCTRL .........................................................................................
Register Call Summary for Register CM_L3INIT_MMC1_CLKCTRL ..............................................
CM_L3INIT_MMC2_CLKCTRL .........................................................................................
Register Call Summary for Register CM_L3INIT_MMC2_CLKCTRL ..............................................
CM_L3INIT_USB_OTG_SS2_CLKCTRL ..............................................................................
Register Call Summary for Register CM_L3INIT_USB_OTG_SS2_CLKCTRL ..................................
CM_L3INIT_USB_OTG_SS3_CLKCTRL ..............................................................................
Register Call Summary for Register CM_L3INIT_USB_OTG_SS3_CLKCTRL ..................................
CM_L3INIT_USB_OTG_SS4_CLKCTRL ..............................................................................
CM_L3INIT_MLB_SS_CLKCTRL.......................................................................................
3-913. Register Call Summary for Register CM_DSS_CLKSTCTRL
956
3-914. CM_DSS_STATICDEP
956
3-915.
957
3-916.
3-917.
3-918.
3-919.
3-920.
3-921.
3-922.
3-923.
3-924.
3-925.
3-926.
3-927.
3-928.
3-929.
3-930.
3-931.
3-932.
3-933.
3-934.
3-935.
3-936.
3-937.
3-938.
3-939.
3-940.
3-941.
3-942.
3-943.
3-944.
3-945.
3-946.
3-947.
3-948.
3-949.
3-950.
3-951.
3-952.
3-953.
3-954.
3-955.
3-956.
3-957.
3-958.
3-959.
SPRUIC2D – January 2017 – Revised April 2019
Submit Documentation Feedback
Copyright © 2017–2019, Texas Instruments Incorporated
List of Tables
957
957
957
958
959
959
960
960
961
962
962
962
963
963
963
964
964
965
965
966
966
966
967
967
968
968
968
969
970
972
972
973
973
974
974
975
975
976
976
977
977
978
978
979
111
www.ti.com
3-960. Register Call Summary for Register CM_L3INIT_MLB_SS_CLKCTRL ........................................... 980
3-961. CM_L3INIT_IEEE1500_2_OCP_CLKCTRL ........................................................................... 980
3-962. Register Call Summary for Register CM_L3INIT_IEEE1500_2_OCP_CLKCTRL ............................... 981
3-963. CM_L3INIT_SATA_CLKCTRL .......................................................................................... 981
3-964. Register Call Summary for Register CM_L3INIT_SATA_CLKCTRL ............................................... 982
3-965. CM_PCIE_CLKSTCTRL ................................................................................................. 982
3-966. Register Call Summary for Register CM_PCIE_CLKSTCTRL...................................................... 983
3-967. CM_PCIE_STATICDEP .................................................................................................. 983
3-968. Register Call Summary for Register CM_PCIE_STATICDEP ...................................................... 985
3-969. CM_PCIE_PCIESS1_CLKCTRL........................................................................................ 986
3-970. Register Call Summary for Register CM_PCIE_PCIESS1_CLKCTRL ............................................ 987
3-971. CM_PCIE_PCIESS2_CLKCTRL........................................................................................ 987
3-972. Register Call Summary for Register CM_PCIE_PCIESS2_CLKCTRL ............................................ 988
3-973. CM_GMAC_CLKSTCTRL ............................................................................................... 989
3-974. Register Call Summary for Register CM_GMAC_CLKSTCTRL .................................................... 990
3-975. CM_GMAC_STATICDEP ................................................................................................ 990
3-976. Register Call Summary for Register CM_GMAC_STATICDEP
....................................................
991
3-977. CM_GMAC_DYNAMICDEP ............................................................................................. 991
3-978. Register Call Summary for Register CM_GMAC_DYNAMICDEP.................................................. 991
3-979. CM_GMAC_GMAC_CLKCTRL ......................................................................................... 991
3-980. Register Call Summary for Register CM_GMAC_GMAC_CLKCTRL .............................................. 992
3-981. CM_L3INIT_OCP2SCP1_CLKCTRL ................................................................................... 993
3-982. Register Call Summary for Register CM_L3INIT_OCP2SCP1_CLKCTRL ....................................... 993
3-983. CM_L3INIT_OCP2SCP3_CLKCTRL ................................................................................... 994
3-984. Register Call Summary for Register CM_L3INIT_OCP2SCP3_CLKCTRL ....................................... 994
3-985. CM_L3INIT_USB_OTG_SS1_CLKCTRL .............................................................................. 995
3-986. Register Call Summary for Register CM_L3INIT_USB_OTG_SS1_CLKCTRL .................................. 995
3-987. CM_CORE__L4PER Registers Mapping Summary.................................................................. 996
3-988. CM_L4PER_CLKSTCTRL ............................................................................................... 998
3-989. Register Call Summary for Register CM_L4PER_CLKSTCTRL .................................................. 1000
3-990. CM_L4PER_DYNAMICDEP ........................................................................................... 1000
3-991. Register Call Summary for Register CM_L4PER_DYNAMICDEP................................................ 1001
3-992. CM_L4PER2_L4_PER2_CLKCTRL .................................................................................. 1001
3-993. Register Call Summary for Register CM_L4PER2_L4_PER2_CLKCTRL ....................................... 1002
3-994. CM_L4PER3_L4_PER3_CLKCTRL .................................................................................. 1002
3-995. Register Call Summary for Register CM_L4PER3_L4_PER3_CLKCTRL ....................................... 1002
3-996. CM_L4PER2_PRUSS1_CLKCTRL ................................................................................... 1003
3-997. Register Call Summary for Register CM_L4PER2_PRUSS1_CLKCTRL
.......................................
1003
3-998. CM_L4PER2_PRUSS2_CLKCTRL ................................................................................... 1004
1004
3-1000. CM_L4PER_TIMER10_CLKCTRL
1005
3-1001.
1006
3-1002.
3-1003.
3-1004.
3-1005.
3-1006.
3-1007.
3-1008.
112
.......................................
..................................................................................
Register Call Summary for Register CM_L4PER_TIMER10_CLKCTRL .......................................
CM_L4PER_TIMER11_CLKCTRL ..................................................................................
Register Call Summary for Register CM_L4PER_TIMER11_CLKCTRL .......................................
CM_L4PER_TIMER2_CLKCTRL ....................................................................................
Register Call Summary for Register CM_L4PER_TIMER2_CLKCTRL ........................................
CM_L4PER_TIMER3_CLKCTRL ....................................................................................
Register Call Summary for Register CM_L4PER_TIMER3_CLKCTRL ........................................
CM_L4PER_TIMER4_CLKCTRL ....................................................................................
3-999. Register Call Summary for Register CM_L4PER2_PRUSS2_CLKCTRL
List of Tables
1006
1007
1007
1008
1008
1009
1010
SPRUIC2D – January 2017 – Revised April 2019
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........................................
CM_L4PER_TIMER9_CLKCTRL ....................................................................................
Register Call Summary for Register CM_L4PER_TIMER9_CLKCTRL ........................................
CM_L4PER_ELM_CLKCTRL ........................................................................................
Register Call Summary for Register CM_L4PER_ELM_CLKCTRL .............................................
CM_L4PER_GPIO2_CLKCTRL ......................................................................................
Register Call Summary for Register CM_L4PER_GPIO2_CLKCTRL ..........................................
CM_L4PER_GPIO3_CLKCTRL ......................................................................................
Register Call Summary for Register CM_L4PER_GPIO3_CLKCTRL ..........................................
CM_L4PER_GPIO4_CLKCTRL ......................................................................................
Register Call Summary for Register CM_L4PER_GPIO4_CLKCTRL ..........................................
CM_L4PER_GPIO5_CLKCTRL ......................................................................................
Register Call Summary for Register CM_L4PER_GPIO5_CLKCTRL ..........................................
CM_L4PER_GPIO6_CLKCTRL ......................................................................................
Register Call Summary for Register CM_L4PER_GPIO6_CLKCTRL ..........................................
CM_L4PER_HDQ1W_CLKCTRL ....................................................................................
Register Call Summary for Register CM_L4PER_HDQ1W_CLKCTRL ........................................
CM_L4PER2_PWMSS2_CLKCTRL .................................................................................
Register Call Summary for Register CM_L4PER2_PWMSS2_CLKCTRL .....................................
CM_L4PER2_PWMSS3_CLKCTRL .................................................................................
Register Call Summary for Register CM_L4PER2_PWMSS3_CLKCTRL .....................................
CM_L4PER_I2C1_CLKCTRL ........................................................................................
Register Call Summary for Register CM_L4PER_I2C1_CLKCTRL .............................................
CM_L4PER_I2C2_CLKCTRL ........................................................................................
Register Call Summary for Register CM_L4PER_I2C2_CLKCTRL .............................................
CM_L4PER_I2C3_CLKCTRL ........................................................................................
Register Call Summary for Register CM_L4PER_I2C3_CLKCTRL .............................................
CM_L4PER_I2C4_CLKCTRL ........................................................................................
Register Call Summary for Register CM_L4PER_I2C4_CLKCTRL .............................................
CM_L4PER_L4_PER1_CLKCTRL ..................................................................................
Register Call Summary for Register CM_L4PER_L4_PER1_CLKCTRL .......................................
CM_L4PER2_PWMSS1_CLKCTRL .................................................................................
Register Call Summary for Register CM_L4PER2_PWMSS1_CLKCTRL .....................................
CM_L4PER3_TIMER13_CLKCTRL .................................................................................
Register Call Summary for Register CM_L4PER3_TIMER13_CLKCTRL .....................................
CM_L4PER3_TIMER14_CLKCTRL .................................................................................
Register Call Summary for Register CM_L4PER3_TIMER14_CLKCTRL .....................................
CM_L4PER3_TIMER15_CLKCTRL .................................................................................
Register Call Summary for Register CM_L4PER3_TIMER15_CLKCTRL .....................................
CM_L4PER_MCSPI1_CLKCTRL ....................................................................................
Register Call Summary for Register CM_L4PER_MCSPI1_CLKCTRL ........................................
CM_L4PER_MCSPI2_CLKCTRL ....................................................................................
Register Call Summary for Register CM_L4PER_MCSPI2_CLKCTRL ........................................
CM_L4PER_MCSPI3_CLKCTRL ....................................................................................
Register Call Summary for Register CM_L4PER_MCSPI3_CLKCTRL ........................................
CM_L4PER_MCSPI4_CLKCTRL ....................................................................................
Register Call Summary for Register CM_L4PER_MCSPI4_CLKCTRL ........................................
CM_L4PER_GPIO7_CLKCTRL ......................................................................................
Register Call Summary for Register CM_L4PER_GPIO7_CLKCTRL ..........................................
3-1009. Register Call Summary for Register CM_L4PER_TIMER4_CLKCTRL
1011
3-1010.
1011
3-1011.
3-1012.
3-1013.
3-1014.
3-1015.
3-1016.
3-1017.
3-1018.
3-1019.
3-1020.
3-1021.
3-1022.
3-1023.
3-1024.
3-1025.
3-1026.
3-1027.
3-1028.
3-1029.
3-1030.
3-1031.
3-1032.
3-1033.
3-1034.
3-1035.
3-1036.
3-1037.
3-1038.
3-1039.
3-1040.
3-1041.
3-1042.
3-1043.
3-1044.
3-1045.
3-1046.
3-1047.
3-1048.
3-1049.
3-1050.
3-1051.
3-1052.
3-1053.
3-1054.
3-1055.
3-1056.
3-1057.
SPRUIC2D – January 2017 – Revised April 2019
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Copyright © 2017–2019, Texas Instruments Incorporated
List of Tables
1012
1012
1013
1013
1014
1014
1015
1015
1016
1016
1017
1017
1018
1018
1018
1019
1019
1020
1020
1021
1021
1022
1022
1023
1023
1024
1024
1025
1025
1025
1026
1026
1027
1028
1029
1029
1030
1030
1031
1031
1032
1032
1032
1033
1033
1034
1034
113
www.ti.com
3-1058. CM_L4PER_GPIO8_CLKCTRL ...................................................................................... 1035
3-1059. Register Call Summary for Register CM_L4PER_GPIO8_CLKCTRL .......................................... 1035
3-1060. CM_L4PER_MMC3_CLKCTRL ...................................................................................... 1036
1037
3-1062.
1037
3-1063.
3-1064.
3-1065.
3-1066.
3-1067.
3-1068.
3-1069.
3-1070.
3-1071.
3-1072.
3-1073.
3-1074.
3-1075.
3-1076.
3-1077.
3-1078.
3-1079.
3-1080.
3-1081.
3-1082.
3-1083.
3-1084.
3-1085.
3-1086.
3-1087.
3-1088.
3-1089.
3-1090.
3-1091.
3-1092.
3-1093.
3-1094.
3-1095.
3-1096.
3-1097.
3-1098.
3-1099.
3-1100.
3-1101.
3-1102.
3-1103.
3-1104.
3-1105.
3-1106.
114
..........................................
CM_L4PER_MMC4_CLKCTRL ......................................................................................
Register Call Summary for Register CM_L4PER_MMC4_CLKCTRL ..........................................
CM_L4PER3_TIMER16_CLKCTRL .................................................................................
Register Call Summary for Register CM_L4PER3_TIMER16_CLKCTRL .....................................
CM_L4PER2_QSPI_CLKCTRL ......................................................................................
Register Call Summary for Register CM_L4PER2_QSPI_CLKCTRL ..........................................
CM_L4PER_UART1_CLKCTRL .....................................................................................
Register Call Summary for Register CM_L4PER_UART1_CLKCTRL..........................................
CM_L4PER_UART2_CLKCTRL .....................................................................................
Register Call Summary for Register CM_L4PER_UART2_CLKCTRL..........................................
CM_L4PER_UART3_CLKCTRL .....................................................................................
Register Call Summary for Register CM_L4PER_UART3_CLKCTRL..........................................
CM_L4PER_UART4_CLKCTRL .....................................................................................
Register Call Summary for Register CM_L4PER_UART4_CLKCTRL..........................................
CM_L4PER2_MCASP2_CLKCTRL .................................................................................
Register Call Summary for Register CM_L4PER2_MCASP2_CLKCTRL ......................................
CM_L4PER2_MCASP3_CLKCTRL .................................................................................
Register Call Summary for Register CM_L4PER2_MCASP3_CLKCTRL ......................................
CM_L4PER_UART5_CLKCTRL .....................................................................................
Register Call Summary for Register CM_L4PER_UART5_CLKCTRL..........................................
CM_L4PER2_MCASP5_CLKCTRL .................................................................................
Register Call Summary for Register CM_L4PER2_MCASP5_CLKCTRL ......................................
CM_L4SEC_CLKSTCTRL ............................................................................................
Register Call Summary for Register CM_L4SEC_CLKSTCTRL ................................................
CM_L4SEC_STATICDEP.............................................................................................
Register Call Summary for Register CM_L4SEC_STATICDEP .................................................
CM_L4SEC_DYNAMICDEP ..........................................................................................
Register Call Summary for Register CM_L4SEC_DYNAMICDEP ..............................................
CM_L4PER2_MCASP8_CLKCTRL .................................................................................
Register Call Summary for Register CM_L4PER2_MCASP8_CLKCTRL ......................................
CM_L4PER2_MCASP4_CLKCTRL .................................................................................
Register Call Summary for Register CM_L4PER2_MCASP4_CLKCTRL ......................................
CM_L4SEC_AES1_CLKCTRL .......................................................................................
Register Call Summary for Register CM_L4SEC_AES1_CLKCTRL ...........................................
CM_L4SEC_AES2_CLKCTRL .......................................................................................
Register Call Summary for Register CM_L4SEC_AES2_CLKCTRL ...........................................
CM_L4SEC_DES3DES_CLKCTRL .................................................................................
Register Call Summary for Register CM_L4SEC_DES3DES_CLKCTRL ......................................
CM_L4SEC_FPKA_CLKCTRL .......................................................................................
Register Call Summary for Register CM_L4SEC_FPKA_CLKCTRL ...........................................
CM_L4SEC_RNG_CLKCTRL ........................................................................................
Register Call Summary for Register CM_L4SEC_RNG_CLKCTRL ............................................
CM_L4SEC_SHA2MD51_CLKCTRL ................................................................................
Register Call Summary for Register CM_L4SEC_SHA2MD51_CLKCTRL ....................................
CM_L4PER2_UART7_CLKCTRL....................................................................................
3-1061. Register Call Summary for Register CM_L4PER_MMC3_CLKCTRL
List of Tables
1038
1038
1039
1039
1040
1040
1041
1041
1042
1042
1043
1043
1044
1044
1046
1046
1047
1048
1048
1049
1050
1050
1051
1051
1052
1052
1052
1052
1053
1054
1055
1055
1056
1056
1057
1057
1058
1058
1059
1059
1059
1060
1060
1061
SPRUIC2D – January 2017 – Revised April 2019
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3-1107. Register Call Summary for Register CM_L4PER2_UART7_CLKCTRL ........................................ 1061
3-1108. CM_L4SEC_DMA_CRYPTO_CLKCTRL ........................................................................... 1062
3-1109. Register Call Summary for Register CM_L4SEC_DMA_CRYPTO_CLKCTRL ................................ 1062
3-1110. CM_L4PER2_UART8_CLKCTRL.................................................................................... 1063
3-1111. Register Call Summary for Register CM_L4PER2_UART8_CLKCTRL ........................................ 1063
3-1112. CM_L4PER2_UART9_CLKCTRL.................................................................................... 1064
3-1113. Register Call Summary for Register CM_L4PER2_UART9_CLKCTRL ........................................ 1064
3-1114. CM_L4PER2_DCAN2_CLKCTRL ................................................................................... 1065
3-1115. Register Call Summary for Register CM_L4PER2_DCAN2_CLKCTRL ........................................ 1065
3-1116. CM_L4SEC_SHA2MD52_CLKCTRL ................................................................................ 1066
3-1117. Register Call Summary for Register CM_L4SEC_SHA2MD52_CLKCTRL .................................... 1066
3-1118. CM_L4PER2_CLKSTCTRL
..........................................................................................
1067
3-1119. Register Call Summary for Register CM_L4PER2_CLKSTCTRL ............................................... 1070
3-1120. CM_L4PER2_DYNAMICDEP ........................................................................................ 1070
3-1121. Register Call Summary for Register CM_L4PER2_DYNAMICDEP ............................................. 1070
3-1122. CM_L4PER2_MCASP6_CLKCTRL ................................................................................. 1071
3-1123. Register Call Summary for Register CM_L4PER2_MCASP6_CLKCTRL ...................................... 1072
3-1124. CM_L4PER2_MCASP7_CLKCTRL ................................................................................. 1072
3-1125. Register Call Summary for Register CM_L4PER2_MCASP7_CLKCTRL ...................................... 1073
3-1126. CM_L4PER2_STATICDEP ........................................................................................... 1074
3-1127. Register Call Summary for Register CM_L4PER2_STATICDEP................................................ 1074
3-1128. CM_L4PER3_CLKSTCTRL
..........................................................................................
1075
3-1129. Register Call Summary for Register CM_L4PER3_CLKSTCTRL ............................................... 1076
3-1130. CM_L4PER3_DYNAMICDEP ........................................................................................ 1076
3-1131. Register Call Summary for Register CM_L4PER3_DYNAMICDEP ............................................. 1077
3-1132. CM_CORE__OCP_SOCKET Registers Mapping Summary ..................................................... 1077
3-1133. REVISION_CM_CORE................................................................................................ 1077
3-1134. Register Call Summary for Register REVISION_CM_CORE .................................................... 1077
..........................................................................
Register Call Summary for Register CM_CM_CORE_PROFILING_CLKCTRL ...............................
CM_CORE_DEBUG_CFG ............................................................................................
Register Call Summary for Register CM_CORE_DEBUG_CFG ................................................
CM_CORE__RESTORE Registers Mapping Summary ..........................................................
CM_L3MAIN1_CLKSTCTRL_RESTORE ...........................................................................
Register Call Summary for Register CM_L3MAIN1_CLKSTCTRL_RESTORE ...............................
CM_L4CFG_CLKSTCTRL_RESTORE .............................................................................
Register Call Summary for Register CM_L4CFG_CLKSTCTRL_RESTORE ..................................
CM_L4PER_CLKSTCTRL_RESTORE .............................................................................
Register Call Summary for Register CM_L4PER_CLKSTCTRL_RESTORE ..................................
CM_L3INIT_CLKSTCTRL_RESTORE ..............................................................................
Register Call Summary for Register CM_L3INIT_CLKSTCTRL_RESTORE ..................................
CM_L3INSTR_L3_MAIN_2_CLKCTRL_RESTORE...............................................................
Register Call Summary for Register CM_L3INSTR_L3_MAIN_2_CLKCTRL_RESTORE ...................
CM_L3INSTR_L3_INSTR_CLKCTRL_RESTORE ................................................................
Register Call Summary for Register CM_L3INSTR_L3_INSTR_CLKCTRL_RESTORE .....................
CM_L3INSTR_OCP_WP_NOC_CLKCTRL_RESTORE..........................................................
Register Call Summary for Register CM_L3INSTR_OCP_WP_NOC_CLKCTRL_RESTORE ..............
CM_CM_CORE_PROFILING_CLKCTRL_RESTORE ............................................................
Register Call Summary for Register CM_CM_CORE_PROFILING_CLKCTRL_RESTORE ................
3-1135. CM_CM_CORE_PROFILING_CLKCTRL
1078
3-1136.
1078
3-1137.
3-1138.
3-1139.
3-1140.
3-1141.
3-1142.
3-1143.
3-1144.
3-1145.
3-1146.
3-1147.
3-1148.
3-1149.
3-1150.
3-1151.
3-1152.
3-1153.
3-1154.
3-1155.
SPRUIC2D – January 2017 – Revised April 2019
Submit Documentation Feedback
Copyright © 2017–2019, Texas Instruments Incorporated
List of Tables
1078
1079
1079
1079
1079
1080
1080
1080
1080
1080
1081
1081
1081
1081
1081
1082
1082
1082
1082
115
www.ti.com
1082
3-1157.
1083
3-1158.
3-1159.
3-1160.
3-1161.
3-1162.
3-1163.
3-1164.
3-1165.
3-1166.
3-1167.
3-1168.
3-1169.
3-1170.
3-1171.
3-1172.
3-1173.
3-1174.
3-1175.
3-1176.
3-1177.
3-1178.
3-1179.
3-1180.
3-1181.
3-1182.
3-1183.
3-1184.
3-1185.
3-1186.
3-1187.
3-1188.
3-1189.
3-1190.
3-1191.
3-1192.
3-1193.
3-1194.
3-1195.
3-1196.
3-1197.
3-1198.
3-1199.
3-1200.
3-1201.
3-1202.
3-1203.
3-1204.
116
........................................................................
Register Call Summary for Register CM_L3MAIN1_DYNAMICDEP_RESTORE .............................
CM_L4CFG_DYNAMICDEP_RESTORE ...........................................................................
Register Call Summary for Register CM_L4CFG_DYNAMICDEP_RESTORE ...............................
CM_L4PER_DYNAMICDEP_RESTORE ...........................................................................
Register Call Summary for Register CM_L4PER_DYNAMICDEP_RESTORE ................................
CM_COREAON_IO_SRCOMP_CLKCTRL_RESTORE ..........................................................
CM_DMA_STATICDEP_RESTORE.................................................................................
Register Call Summary for Register CM_DMA_STATICDEP_RESTORE .....................................
SMARTREFLEX Registers Mapping Summary 1 .................................................................
SMARTREFLEX Registers Mapping Summary 2 .................................................................
SRCONFIG .............................................................................................................
SRSTATUS .............................................................................................................
SENVAL .................................................................................................................
SENMIN .................................................................................................................
SENMAX ................................................................................................................
SENAVG ................................................................................................................
AVGWEIGHT ...........................................................................................................
NVALUERECIPROCAL ...............................................................................................
IRQ_EOI ................................................................................................................
IRQSTATUS_RAW ....................................................................................................
IRQSTATUS ............................................................................................................
IRQENABLE_SET .....................................................................................................
IRQENABLE_CLR .....................................................................................................
SENERROR ............................................................................................................
ERRCONFIG ...........................................................................................................
CAM_PRM Registers Mapping Summary ..........................................................................
PM_CAM_PWRSTCTRL..............................................................................................
Register Call Summary for Register PM_CAM_PWRSTCTRL ..................................................
PM_CAM_PWRSTST .................................................................................................
Register Call Summary for Register PM_CAM_PWRSTST ......................................................
PM_CAM_VIP1_WKDEP .............................................................................................
Register Call Summary for Register PM_CAM_VIP1_WKDEP ..................................................
RM_CAM_VIP1_CONTEXT ..........................................................................................
Register Call Summary for Register RM_CAM_VIP1_CONTEXT ..............................................
PM_CAM_CAL_WKDEP ..............................................................................................
Register Call Summary for Register PM_CAM_CAL_WKDEP ..................................................
RM_CAM_CAL_CONTEXT...........................................................................................
Register Call Summary for Register RM_CAM_CAL_CONTEXT ...............................................
PM_CAM_VIP3_WKDEP .............................................................................................
RM_CAM_VIP3_CONTEXT ..........................................................................................
RM_CAM_LVDSRX_CONTEXT .....................................................................................
RM_CAM_CSI1_CONTEXT ..........................................................................................
RM_CAM_CSI2_CONTEXT ..........................................................................................
CKGEN_PRM Registers Mapping Summary.......................................................................
CM_CLKSEL_SYSCLK1 ..............................................................................................
Register Call Summary for Register CM_CLKSEL_SYSCLK1 ..................................................
CM_CLKSEL_WKUPAON ............................................................................................
Register Call Summary for Register CM_CLKSEL_WKUPAON ................................................
3-1156. CM_L3MAIN1_DYNAMICDEP_RESTORE
List of Tables
1083
1083
1083
1083
1084
1084
1084
1084
1085
1086
1087
1087
1088
1088
1088
1089
1089
1090
1090
1091
1092
1093
1093
1094
1094
1095
1096
1096
1097
1097
1098
1098
1099
1099
1100
1100
1101
1101
1102
1103
1103
1104
1104
1106
1106
1106
1106
SPRUIC2D – January 2017 – Revised April 2019
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3-1205. CM_CLKSEL_ABE_PLL_REF ....................................................................................... 1107
3-1206. Register Call Summary for Register CM_CLKSEL_ABE_PLL_REF ............................................ 1107
3-1207. CM_CLKSEL_SYS
....................................................................................................
1107
3-1208. Register Call Summary for Register CM_CLKSEL_SYS ......................................................... 1108
3-1209. CM_CLKSEL_ABE_PLL_BYPAS .................................................................................... 1108
3-1210. Register Call Summary for Register CM_CLKSEL_ABE_PLL_BYPAS ........................................ 1108
3-1211. CM_CLKSEL_ABE_PLL_SYS ....................................................................................... 1108
3-1212. Register Call Summary for Register CM_CLKSEL_ABE_PLL_SYS ............................................ 1109
3-1213. CM_CLKSEL_ABE_24M .............................................................................................. 1109
3-1214. Register Call Summary for Register CM_CLKSEL_ABE_24M .................................................. 1109
3-1215. CM_CLKSEL_ABE_SYS.............................................................................................. 1109
3-1216. Register Call Summary for Register CM_CLKSEL_ABE_SYS .................................................. 1110
3-1217. CM_CLKSEL_HDMI_MCASP_AUX ................................................................................. 1110
.....................................
CM_CLKSEL_HDMI_TIMER .........................................................................................
Register Call Summary for Register CM_CLKSEL_HDMI_TIMER..............................................
CM_CLKSEL_MCASP_SYS .........................................................................................
Register Call Summary for Register CM_CLKSEL_MCASP_SYS ..............................................
CM_CLKSEL_MLBP_MCASP .......................................................................................
Register Call Summary for Register CM_CLKSEL_MLBP_MCASP ............................................
CM_CLKSEL_MLB_MCASP .........................................................................................
Register Call Summary for Register CM_CLKSEL_MLB_MCASP ..............................................
CM_CLKSEL_PER_ABE_X1_GFCLK_MCASP_AUX ............................................................
Register Call Summary for Register CM_CLKSEL_PER_ABE_X1_GFCLK_MCASP_AUX ................
CM_CLKSEL_SYS_CLK1_32K ......................................................................................
CM_CLKSEL_TIMER_SYS...........................................................................................
Register Call Summary for Register CM_CLKSEL_TIMER_SYS ...............................................
CM_CLKSEL_VIDEO1_MCASP_AUX ..............................................................................
Register Call Summary for Register CM_CLKSEL_VIDEO1_MCASP_AUX ..................................
CM_CLKSEL_VIDEO1_TIMER ......................................................................................
Register Call Summary for Register CM_CLKSEL_VIDEO1_TIMER...........................................
CM_CLKSEL_VIDEO2_MCASP_AUX ..............................................................................
CM_CLKSEL_VIDEO2_TIMER ......................................................................................
CM_CLKSEL_CLKOUTMUX0 .......................................................................................
Register Call Summary for Register CM_CLKSEL_CLKOUTMUX0 ............................................
CM_CLKSEL_CLKOUTMUX1 .......................................................................................
Register Call Summary for Register CM_CLKSEL_CLKOUTMUX1 ............................................
CM_CLKSEL_CLKOUTMUX2 .......................................................................................
Register Call Summary for Register CM_CLKSEL_CLKOUTMUX2 ............................................
CM_CLKSEL_HDMI_PLL_SYS ......................................................................................
Register Call Summary for Register CM_CLKSEL_HDMI_PLL_SYS ..........................................
CM_CLKSEL_VIDEO1_PLL_SYS ...................................................................................
Register Call Summary for Register CM_CLKSEL_VIDEO1_PLL_SYS .......................................
CM_CLKSEL_VIDEO2_PLL_SYS ...................................................................................
CM_CLKSEL_ABE_CLK_DIV ........................................................................................
Register Call Summary for Register CM_CLKSEL_ABE_CLK_DIV ............................................
CM_CLKSEL_ABE_GICLK_DIV .....................................................................................
Register Call Summary for Register CM_CLKSEL_ABE_GICLK_DIV .........................................
CM_CLKSEL_AESS_FCLK_DIV ....................................................................................
3-1218. Register Call Summary for Register CM_CLKSEL_HDMI_MCASP_AUX
3-1219.
3-1220.
3-1221.
3-1222.
3-1223.
3-1224.
3-1225.
3-1226.
3-1227.
3-1228.
3-1229.
3-1230.
3-1231.
3-1232.
3-1233.
3-1234.
3-1235.
3-1236.
3-1237.
3-1238.
3-1239.
3-1240.
3-1241.
3-1242.
3-1243.
3-1244.
3-1245.
3-1246.
3-1247.
3-1248.
3-1249.
3-1250.
3-1251.
3-1252.
3-1253.
SPRUIC2D – January 2017 – Revised April 2019
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List of Tables
1110
1110
1111
1111
1111
1112
1112
1112
1113
1113
1113
1113
1114
1114
1114
1115
1115
1115
1116
1116
1117
1118
1119
1121
1121
1123
1123
1123
1123
1124
1124
1124
1124
1125
1125
1125
117
www.ti.com
3-1254. Register Call Summary for Register CM_CLKSEL_AESS_FCLK_DIV ......................................... 1125
3-1255. CM_CLKSEL_EVE_CLK .............................................................................................. 1126
3-1256. CM_CLKSEL_USB_OTG_CLK_CLKOUTMUX .................................................................... 1126
3-1257. Register Call Summary for Register CM_CLKSEL_USB_OTG_CLK_CLKOUTMUX ........................ 1126
3-1258. CM_CLKSEL_CORE_DPLL_OUT_CLK_CLKOUTMUX
.........................................................
1127
3-1259. Register Call Summary for Register CM_CLKSEL_CORE_DPLL_OUT_CLK_CLKOUTMUX .............. 1127
3-1260. CM_CLKSEL_DSP_GFCLK_CLKOUTMUX
.......................................................................
1127
3-1261. Register Call Summary for Register CM_CLKSEL_DSP_GFCLK_CLKOUTMUX ............................ 1128
3-1262. CM_CLKSEL_EMIF_PHY_GCLK_CLKOUTMUX ................................................................. 1128
3-1263. Register Call Summary for Register CM_CLKSEL_EMIF_PHY_GCLK_CLKOUTMUX ...................... 1128
3-1264. CM_CLKSEL_EMU_CLK_CLKOUTMUX ........................................................................... 1128
3-1265. Register Call Summary for Register CM_CLKSEL_EMU_CLK_CLKOUTMUX ............................... 1129
3-1266. CM_CLKSEL_FUNC_96M_AON_CLK_CLKOUTMUX ........................................................... 1129
3-1267. Register Call Summary for Register CM_CLKSEL_FUNC_96M_AON_CLK_CLKOUTMUX ................ 1129
3-1268. CM_CLKSEL_GMAC_250M_CLK_CLKOUTMUX
................................................................
1130
3-1269. Register Call Summary for Register CM_CLKSEL_GMAC_250M_CLK_CLKOUTMUX ..................... 1130
3-1270. CM_CLKSEL_GPU_GCLK_CLKOUTMUX ......................................................................... 1130
3-1271. Register Call Summary for Register CM_CLKSEL_GPU_GCLK_CLKOUTMUX ............................. 1131
3-1272. CM_CLKSEL_HDMI_CLK_CLKOUTMUX .......................................................................... 1131
3-1273. Register Call Summary for Register CM_CLKSEL_HDMI_CLK_CLKOUTMUX .............................. 1131
3-1274. CM_CLKSEL_IVA_GCLK_CLKOUTMUX .......................................................................... 1131
3-1275. Register Call Summary for Register CM_CLKSEL_IVA_GCLK_CLKOUTMUX ............................... 1132
3-1276. CM_CLKSEL_L3INIT_480M_GFCLK_CLKOUTMUX............................................................. 1132
3-1277. Register Call Summary for Register CM_CLKSEL_L3INIT_480M_GFCLK_CLKOUTMUX ................. 1132
3-1278. CM_CLKSEL_MPU_GCLK_CLKOUTMUX......................................................................... 1133
3-1279. Register Call Summary for Register CM_CLKSEL_MPU_GCLK_CLKOUTMUX ............................. 1133
3-1280. CM_CLKSEL_PCIE1_CLK_CLKOUTMUX ......................................................................... 1133
3-1281. Register Call Summary for Register CM_CLKSEL_PCIE1_CLK_CLKOUTMUX
.............................
1134
3-1282. CM_CLKSEL_PCIE2_CLK_CLKOUTMUX ......................................................................... 1134
1134
3-1284. CM_CLKSEL_PER_ABE_X1_CLK_CLKOUTMUX
1134
3-1285.
1135
3-1286.
3-1287.
3-1288.
3-1289.
3-1290.
3-1291.
3-1292.
3-1293.
3-1294.
3-1295.
3-1296.
3-1297.
3-1298.
3-1299.
3-1300.
3-1301.
3-1302.
118
.............................
...............................................................
Register Call Summary for Register CM_CLKSEL_PER_ABE_X1_CLK_CLKOUTMUX ....................
CM_CLKSEL_SATA_CLK_CLKOUTMUX ..........................................................................
Register Call Summary for Register CM_CLKSEL_SATA_CLK_CLKOUTMUX ..............................
CM_CLKSEL_OSC_32K_CLK_CLKOUTMUX.....................................................................
Register Call Summary for Register CM_CLKSEL_OSC_32K_CLK_CLKOUTMUX .........................
CM_CLKSEL_SYS_CLK1_CLKOUTMUX ..........................................................................
Register Call Summary for Register CM_CLKSEL_SYS_CLK1_CLKOUTMUX ..............................
CM_CLKSEL_SYS_CLK2_CLKOUTMUX ..........................................................................
Register Call Summary for Register CM_CLKSEL_SYS_CLK2_CLKOUTMUX ..............................
CM_CLKSEL_VIDEO1_CLK_CLKOUTMUX .......................................................................
Register Call Summary for Register CM_CLKSEL_VIDEO1_CLK_CLKOUTMUX ...........................
CM_CLKSEL_VIDEO2_CLK_CLKOUTMUX .......................................................................
CM_CLKSEL_ABE_LP_CLK .........................................................................................
Register Call Summary for Register CM_CLKSEL_ABE_LP_CLK .............................................
CM_CLKSEL_ADC_GFCLK ..........................................................................................
CM_CLKSEL_EVE_GFCLK_CLKOUTMUX........................................................................
COREAON_PRM Registers Mapping Summary...................................................................
PM_COREAON_SMARTREFLEX_MPU_WKDEP ................................................................
3-1283. Register Call Summary for Register CM_CLKSEL_PCIE2_CLK_CLKOUTMUX
List of Tables
1135
1135
1136
1136
1136
1137
1137
1137
1138
1138
1138
1139
1139
1139
1140
1140
1141
SPRUIC2D – January 2017 – Revised April 2019
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Copyright © 2017–2019, Texas Instruments Incorporated
www.ti.com
3-1303. RM_COREAON_SMARTREFLEX_MPU_CONTEXT ............................................................. 1143
3-1304. PM_COREAON_SMARTREFLEX_CORE_WKDEP .............................................................. 1143
3-1305. RM_COREAON_SMARTREFLEX_CORE_CONTEXT ........................................................... 1145
3-1306. PM_COREAON_SMARTREFLEX_GPU_WKDEP ................................................................ 1145
3-1307. RM_COREAON_SMARTREFLEX_GPU_CONTEXT ............................................................. 1147
3-1308. PM_COREAON_SMARTREFLEX_DSPEVE_WKDEP ........................................................... 1147
3-1309. RM_COREAON_SMARTREFLEX_DSPEVE_CONTEXT ........................................................ 1149
3-1310. PM_COREAON_SMARTREFLEX_IVAHD_WKDEP .............................................................. 1149
..........................................................
RM_COREAON_DUMMY_MODULE1_CONTEXT ...............................................................
RM_COREAON_DUMMY_MODULE2_CONTEXT ...............................................................
RM_COREAON_DUMMY_MODULE3_CONTEXT ...............................................................
RM_COREAON_DUMMY_MODULE4_CONTEXT ...............................................................
CORE_PRM Registers Mapping Summary ........................................................................
PM_CORE_PWRSTCTRL ............................................................................................
Register Call Summary for Register PM_CORE_PWRSTCTRL ................................................
PM_CORE_PWRSTST ...............................................................................................
Register Call Summary for Register PM_CORE_PWRSTST ....................................................
RM_L3MAIN1_L3_MAIN_1_CONTEXT ............................................................................
RM_L3MAIN1_GPMC_CONTEXT ..................................................................................
RM_L3MAIN1_MMU_EDMA_CONTEXT ...........................................................................
RM_L3MAIN1_MMU_PCIESS_CONTEXT .........................................................................
PM_L3MAIN1_OCMC_RAM1_WKDEP ............................................................................
Register Call Summary for Register PM_L3MAIN1_OCMC_RAM1_WKDEP .................................
RM_L3MAIN1_OCMC_RAM1_CONTEXT .........................................................................
PM_L3MAIN1_OCMC_RAM2_WKDEP ............................................................................
RM_L3MAIN1_OCMC_RAM2_CONTEXT .........................................................................
PM_L3MAIN1_OCMC_RAM3_WKDEP ............................................................................
RM_L3MAIN1_OCMC_RAM3_CONTEXT .........................................................................
RM_L3MAIN1_OCMC_ROM_CONTEXT...........................................................................
PM_L3MAIN1_TPCC_WKDEP ......................................................................................
Register Call Summary for Register PM_L3MAIN1_TPCC_WKDEP ...........................................
RM_L3MAIN1_TPCC_CONTEXT ...................................................................................
PM_L3MAIN1_TPTC1_WKDEP .....................................................................................
Register Call Summary for Register PM_L3MAIN1_TPTC1_WKDEP ..........................................
RM_L3MAIN1_TPTC1_CONTEXT ..................................................................................
PM_L3MAIN1_TPTC2_WKDEP .....................................................................................
Register Call Summary for Register PM_L3MAIN1_TPTC2_WKDEP ..........................................
RM_L3MAIN1_TPTC2_CONTEXT ..................................................................................
RM_L3MAIN1_VCP1_CONTEXT....................................................................................
RM_L3MAIN1_VCP2_CONTEXT....................................................................................
RM_L3MAIN1_SPARE_CME_CONTEXT ..........................................................................
RM_L3MAIN1_SPARE_HDMI_CONTEXT .........................................................................
RM_L3MAIN1_SPARE_ICM_CONTEXT ...........................................................................
RM_L3MAIN1_SPARE_IVA2_CONTEXT ..........................................................................
RM_L3MAIN1_SPARE_SATA2_CONTEXT .......................................................................
RM_L3MAIN1_SPARE_UNKNOWN4_CONTEXT ................................................................
RM_L3MAIN1_SPARE_UNKNOWN5_CONTEXT ................................................................
RM_L3MAIN1_SPARE_UNKNOWN6_CONTEXT ................................................................
3-1311. RM_COREAON_SMARTREFLEX_IVAHD_CONTEXT
1151
3-1312.
1151
3-1313.
3-1314.
3-1315.
3-1316.
3-1317.
3-1318.
3-1319.
3-1320.
3-1321.
3-1322.
3-1323.
3-1324.
3-1325.
3-1326.
3-1327.
3-1328.
3-1329.
3-1330.
3-1331.
3-1332.
3-1333.
3-1334.
3-1335.
3-1336.
3-1337.
3-1338.
3-1339.
3-1340.
3-1341.
3-1342.
3-1343.
3-1344.
3-1345.
3-1346.
3-1347.
3-1348.
3-1349.
3-1350.
3-1351.
SPRUIC2D – January 2017 – Revised April 2019
Submit Documentation Feedback
Copyright © 2017–2019, Texas Instruments Incorporated
List of Tables
1152
1152
1153
1153
1155
1156
1157
1158
1158
1159
1159
1160
1160
1161
1162
1162
1164
1164
1166
1166
1167
1168
1168
1169
1170
1170
1171
1172
1172
1173
1174
1174
1175
1175
1176
1176
1177
1177
1178
119
www.ti.com
3-1352. RM_L3MAIN1_SPARE_VIDEOPLL1_CONTEXT ................................................................. 1178
3-1353. RM_L3MAIN1_SPARE_VIDEOPLL2_CONTEXT ................................................................. 1179
3-1354. RM_L3MAIN1_SPARE_VIDEOPLL3_CONTEXT ................................................................. 1179
3-1355. RM_IPU2_RSTCTRL .................................................................................................. 1180
3-1356. Register Call Summary for Register RM_IPU2_RSTCTRL ...................................................... 1180
1180
3-1358.
1181
3-1359.
3-1360.
3-1361.
3-1362.
3-1363.
3-1364.
3-1365.
3-1366.
3-1367.
3-1368.
3-1369.
3-1370.
3-1371.
3-1372.
3-1373.
3-1374.
3-1375.
3-1376.
3-1377.
3-1378.
3-1379.
3-1380.
3-1381.
3-1382.
3-1383.
3-1384.
3-1385.
3-1386.
3-1387.
3-1388.
3-1389.
3-1390.
3-1391.
3-1392.
3-1393.
3-1394.
3-1395.
3-1396.
3-1397.
3-1398.
3-1399.
3-1400.
120
.....................................................................................................
Register Call Summary for Register RM_IPU2_RSTST ..........................................................
RM_IPU2_IPU2_CONTEXT ..........................................................................................
Register Call Summary for Register RM_IPU2_IPU2_CONTEXT ..............................................
RM_DMA_DMA_SYSTEM_CONTEXT .............................................................................
RM_EMIF_DMM_CONTEXT .........................................................................................
RM_EMIF_EMIF_OCP_FW_CONTEXT ............................................................................
RM_EMIF_EMIF1_CONTEXT .......................................................................................
RM_EMIF_EMIF2_CONTEXT .......................................................................................
RM_EMIF_EMIF_DLL_CONTEXT ..................................................................................
RM_ATL_ATL_CONTEXT ............................................................................................
RM_L4CFG_L4_CFG_CONTEXT ...................................................................................
RM_L4CFG_SPINLOCK_CONTEXT ...............................................................................
RM_L4CFG_MAILBOX1_CONTEXT ................................................................................
RM_L4CFG_SAR_ROM_CONTEXT ................................................................................
RM_L4CFG_OCP2SCP2_CONTEXT ...............................................................................
RM_L4CFG_MAILBOX2_CONTEXT ................................................................................
RM_L4CFG_MAILBOX3_CONTEXT ................................................................................
RM_L4CFG_MAILBOX4_CONTEXT ................................................................................
RM_L4CFG_MAILBOX5_CONTEXT ................................................................................
RM_L4CFG_MAILBOX6_CONTEXT ................................................................................
RM_L4CFG_MAILBOX7_CONTEXT ................................................................................
RM_L4CFG_MAILBOX8_CONTEXT ................................................................................
RM_L4CFG_MAILBOX9_CONTEXT ................................................................................
RM_L4CFG_MAILBOX10_CONTEXT ..............................................................................
RM_L4CFG_MAILBOX11_CONTEXT ..............................................................................
RM_L4CFG_MAILBOX12_CONTEXT ..............................................................................
RM_L4CFG_MAILBOX13_CONTEXT ..............................................................................
RM_L4CFG_SPARE_SMARTREFLEX_RTC_CONTEXT .......................................................
RM_L4CFG_SPARE_SMARTREFLEX_SDRAM_CONTEXT ...................................................
RM_L4CFG_SPARE_SMARTREFLEX_WKUP_CONTEXT .....................................................
RM_L4CFG_IO_DELAY_BLOCK_CONTEXT .....................................................................
RM_L3INSTR_L3_MAIN_2_CONTEXT ............................................................................
RM_L3INSTR_L3_INSTR_CONTEXT ..............................................................................
RM_L3INSTR_OCP_WP_NOC_CONTEXT........................................................................
CUSTEFUSE_PRM Registers Mapping Summary ................................................................
PM_CUSTEFUSE_PWRSTCTRL ...................................................................................
Register Call Summary for Register PM_CUSTEFUSE_PWRSTCTRL ........................................
PM_CUSTEFUSE_PWRSTST .......................................................................................
Register Call Summary for Register PM_CUSTEFUSE_PWRSTST ...........................................
RM_CUSTEFUSE_EFUSE_CTRL_CUST_CONTEXT ...........................................................
Register Call Summary for Register RM_CUSTEFUSE_EFUSE_CTRL_CUST_CONTEXT ................
DEVICE_PRM Registers Mapping Summary ......................................................................
PRM_RSTCTRL .......................................................................................................
3-1357. RM_IPU2_RSTST
List of Tables
1181
1182
1182
1183
1184
1184
1185
1185
1186
1186
1187
1187
1188
1188
1189
1189
1190
1190
1191
1191
1192
1192
1193
1193
1194
1194
1195
1195
1196
1196
1197
1197
1198
1199
1199
1200
1200
1201
1201
1201
1201
1203
SPRUIC2D – January 2017 – Revised April 2019
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3-1401. Register Call Summary for Register PRM_RSTCTRL ............................................................ 1204
3-1402. PRM_RSTST ........................................................................................................... 1204
3-1403. Register Call Summary for Register PRM_RSTST................................................................ 1206
3-1404. PRM_RSTTIME ........................................................................................................ 1206
3-1405. Register Call Summary for Register PRM_RSTTIME............................................................. 1206
3-1406. PRM_VOLTCTRL ...................................................................................................... 1207
3-1407. PRM_PWRREQCTRL ................................................................................................. 1208
3-1408. PRM_PSCON_COUNT ............................................................................................... 1209
3-1409. Register Call Summary for Register PRM_PSCON_COUNT .................................................... 1209
3-1410. PRM_IO_COUNT ...................................................................................................... 1209
..........................................................
PRM_IO_PMCTRL ....................................................................................................
Register Call Summary for Register PRM_IO_PMCTRL .........................................................
PRM_VOLTSETUP_WARMRESET .................................................................................
PRM_VOLTSETUP_CORE_OFF ....................................................................................
PRM_VOLTSETUP_MPU_OFF .....................................................................................
PRM_VOLTSETUP_MM_OFF .......................................................................................
PRM_VOLTSETUP_CORE_RET_SLEEP .........................................................................
PRM_VOLTSETUP_MPU_RET_SLEEP ...........................................................................
PRM_VOLTSETUP_MM_RET_SLEEP .............................................................................
PRM_VP_CORE_CONFIG ...........................................................................................
PRM_VP_CORE_STATUS ...........................................................................................
PRM_VP_CORE_VLIMITTO .........................................................................................
PRM_VP_CORE_VOLTAGE .........................................................................................
PRM_VP_CORE_VSTEPMAX .......................................................................................
PRM_VP_CORE_VSTEPMIN ........................................................................................
PRM_VP_MPU_CONFIG .............................................................................................
PRM_VP_MPU_STATUS .............................................................................................
PRM_VP_MPU_VLIMITTO ...........................................................................................
PRM_VP_MPU_VOLTAGE...........................................................................................
PRM_VP_MPU_VSTEPMAX .........................................................................................
PRM_VP_MPU_VSTEPMIN..........................................................................................
PRM_VP_MM_CONFIG ..............................................................................................
PRM_VP_MM_STATUS ..............................................................................................
PRM_VP_MM_VLIMITTO ............................................................................................
PRM_VP_MM_VOLTAGE ............................................................................................
PRM_VP_MM_VSTEPMAX ..........................................................................................
PRM_VP_MM_VSTEPMIN ...........................................................................................
PRM_VC_SMPS_CORE_CONFIG ..................................................................................
PRM_VC_SMPS_MM_CONFIG .....................................................................................
PRM_VC_SMPS_MPU_CONFIG....................................................................................
PRM_VC_VAL_CMD_VDD_CORE_L ..............................................................................
PRM_VC_VAL_CMD_VDD_MM_L ..................................................................................
PRM_VC_VAL_CMD_VDD_MPU_L ................................................................................
PRM_VC_VAL_BYPASS .............................................................................................
PRM_VC_CORE_ERRST ............................................................................................
PRM_VC_MM_ERRST................................................................................................
PRM_VC_MPU_ERRST ..............................................................................................
PRM_VC_BYPASS_ERRST .........................................................................................
3-1411. Register Call Summary for Register PRM_IO_COUNT
3-1412.
3-1413.
3-1414.
3-1415.
3-1416.
3-1417.
3-1418.
3-1419.
3-1420.
3-1421.
3-1422.
3-1423.
3-1424.
3-1425.
3-1426.
3-1427.
3-1428.
3-1429.
3-1430.
3-1431.
3-1432.
3-1433.
3-1434.
3-1435.
3-1436.
3-1437.
3-1438.
3-1439.
3-1440.
3-1441.
3-1442.
3-1443.
3-1444.
3-1445.
3-1446.
3-1447.
3-1448.
3-1449.
SPRUIC2D – January 2017 – Revised April 2019
Submit Documentation Feedback
Copyright © 2017–2019, Texas Instruments Incorporated
List of Tables
1210
1210
1211
1211
1212
1213
1214
1215
1216
1217
1218
1218
1219
1219
1219
1220
1220
1221
1221
1222
1222
1222
1223
1223
1224
1224
1224
1225
1225
1226
1228
1229
1229
1229
1230
1231
1232
1233
1234
121
www.ti.com
3-1450. PRM_VC_CFG_I2C_MODE .......................................................................................... 1234
3-1451. PRM_VC_CFG_I2C_CLK............................................................................................. 1235
3-1452. PRM_SRAM_COUNT ................................................................................................. 1235
3-1453. Register Call Summary for Register PRM_SRAM_COUNT...................................................... 1236
3-1454. PRM_SRAM_WKUP_SETUP ........................................................................................ 1236
3-1455. PRM_SLDO_CORE_SETUP ......................................................................................... 1236
3-1456. Register Call Summary for Register PRM_SLDO_CORE_SETUP ............................................. 1237
3-1457. PRM_SLDO_CORE_CTRL ........................................................................................... 1238
3-1458. Register Call Summary for Register PRM_SLDO_CORE_CTRL ............................................... 1238
3-1459. PRM_SLDO_MPU_SETUP........................................................................................... 1238
3-1460. Register Call Summary for Register PRM_SLDO_MPU_SETUP ............................................... 1239
3-1461. PRM_SLDO_MPU_CTRL............................................................................................. 1240
3-1462. Register Call Summary for Register PRM_SLDO_MPU_CTRL ................................................. 1240
3-1463. PRM_SLDO_GPU_SETUP ........................................................................................... 1240
3-1464. Register Call Summary for Register PRM_SLDO_GPU_SETUP ............................................... 1241
3-1465. PRM_SLDO_GPU_CTRL ............................................................................................. 1242
3-1466. Register Call Summary for Register PRM_SLDO_GPU_CTRL ................................................. 1242
3-1467. PRM_ABBLDO_MPU_SETUP ....................................................................................... 1242
1243
3-1469.
1243
3-1470.
3-1471.
3-1472.
3-1473.
3-1474.
3-1475.
3-1476.
3-1477.
3-1478.
3-1479.
3-1480.
3-1481.
3-1482.
3-1483.
3-1484.
3-1485.
3-1486.
3-1487.
3-1488.
3-1489.
3-1490.
3-1491.
3-1492.
3-1493.
3-1494.
3-1495.
3-1496.
3-1497.
3-1498.
122
...........................................
PRM_ABBLDO_MPU_CTRL .........................................................................................
Register Call Summary for Register PRM_ABBLDO_MPU_CTRL .............................................
PRM_ABBLDO_GPU_SETUP .......................................................................................
Register Call Summary for Register PRM_ABBLDO_GPU_SETUP ............................................
PRM_ABBLDO_GPU_CTRL .........................................................................................
Register Call Summary for Register PRM_ABBLDO_GPU_CTRL..............................................
PRM_BANDGAP_SETUP ............................................................................................
Register Call Summary for Register PRM_BANDGAP_SETUP .................................................
PRM_DEVICE_OFF_CTRL ..........................................................................................
PRM_PHASE1_CNDP ................................................................................................
PRM_PHASE2A_CNDP ..............................................................................................
PRM_PHASE2B_CNDP ..............................................................................................
PRM_MODEM_IF_CTRL .............................................................................................
PRM_VOLTST_MPU ..................................................................................................
PRM_VOLTST_MM ...................................................................................................
PRM_SLDO_DSPEVE_SETUP ......................................................................................
Register Call Summary for Register PRM_SLDO_DSPEVE_SETUP ..........................................
PRM_SLDO_IVA_SETUP ............................................................................................
Register Call Summary for Register PRM_SLDO_IVA_SETUP .................................................
PRM_ABBLDO_DSPEVE_CTRL ....................................................................................
Register Call Summary for Register PRM_ABBLDO_DSPEVE_CTRL ........................................
PRM_ABBLDO_IVA_CTRL...........................................................................................
Register Call Summary for Register PRM_ABBLDO_IVA_CTRL ...............................................
PRM_SLDO_DSPEVE_CTRL........................................................................................
Register Call Summary for Register PRM_SLDO_DSPEVE_CTRL ............................................
PRM_SLDO_IVA_CTRL ..............................................................................................
Register Call Summary for Register PRM_SLDO_IVA_CTRL ...................................................
PRM_ABBLDO_DSPEVE_SETUP ..................................................................................
Register Call Summary for Register PRM_ABBLDO_DSPEVE_SETUP.......................................
PRM_ABBLDO_IVA_SETUP .........................................................................................
3-1468. Register Call Summary for Register PRM_ABBLDO_MPU_SETUP
List of Tables
1244
1244
1245
1245
1246
1246
1246
1247
1247
1248
1248
1248
1249
1249
1250
1251
1251
1252
1253
1253
1254
1254
1255
1255
1255
1256
1256
1257
1257
SPRUIC2D – January 2017 – Revised April 2019
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3-1499. Register Call Summary for Register PRM_ABBLDO_IVA_SETUP ............................................. 1257
3-1500. DSP1_PRM Registers Mapping Summary ......................................................................... 1258
3-1501. PM_DSP1_PWRSTCTRL............................................................................................. 1258
3-1502. Register Call Summary for Register PM_DSP1_PWRSTCTRL ................................................. 1259
3-1503. PM_DSP1_PWRSTST ................................................................................................ 1259
3-1504. Register Call Summary for Register PM_DSP1_PWRSTST ..................................................... 1260
3-1505. RM_DSP1_RSTCTRL ................................................................................................. 1260
3-1506. Register Call Summary for Register RM_DSP1_RSTCTRL ..................................................... 1261
3-1507. RM_DSP1_RSTST .................................................................................................... 1261
3-1508. Register Call Summary for Register RM_DSP1_RSTST ......................................................... 1262
3-1509. RM_DSP1_DSP1_CONTEXT ........................................................................................ 1262
3-1510. Register Call Summary for Register RM_DSP1_DSP1_CONTEXT ............................................ 1262
3-1511. DSP2_PRM Registers Mapping Summary ......................................................................... 1263
3-1512. PM_DSP2_PWRSTCTRL............................................................................................. 1263
3-1513. PM_DSP2_PWRSTST ................................................................................................ 1264
3-1514. RM_DSP2_RSTCTRL ................................................................................................. 1265
3-1515. RM_DSP2_RSTST .................................................................................................... 1266
3-1516. RM_DSP2_DSP2_CONTEXT ........................................................................................ 1266
3-1517. DSS_PRM Registers Mapping Summary ........................................................................... 1267
3-1518. PM_DSS_PWRSTCTRL .............................................................................................. 1268
3-1519. Register Call Summary for Register PM_DSS_PWRSTCTRL................................................... 1268
3-1520. PM_DSS_PWRSTST .................................................................................................. 1269
3-1521. Register Call Summary for Register PM_DSS_PWRSTST ...................................................... 1270
3-1522. PM_DSS_DSS_WKDEP .............................................................................................. 1270
3-1523. Register Call Summary for Register PM_DSS_DSS_WKDEP
..................................................
1273
3-1524. RM_DSS_DSS_CONTEXT ........................................................................................... 1273
3-1525. Register Call Summary for Register RM_DSS_DSS_CONTEXT ............................................... 1274
3-1526. PM_DSS_DSS2_WKDEP
............................................................................................
1274
3-1527. Register Call Summary for Register PM_DSS_DSS2_WKDEP ................................................. 1276
3-1528. RM_DSS_BB2D_CONTEXT ......................................................................................... 1277
3-1529. Register Call Summary for Register RM_DSS_BB2D_CONTEXT .............................................. 1277
3-1530. RM_DSS_SDVENC_CONTEXT ..................................................................................... 1277
3-1531. EMU_CM Registers Mapping Summary ............................................................................ 1278
..............................................................................................
Register Call Summary for Register CM_EMU_CLKSTCTRL ...................................................
CM_EMU_DEBUGSS_CLKCTRL ...................................................................................
Register Call Summary for Register CM_EMU_DEBUGSS_CLKCTRL ........................................
CM_EMU_DYNAMICDEP ............................................................................................
Register Call Summary for Register CM_EMU_DYNAMICDEP .................................................
CM_EMU_MPU_EMU_DBG_CLKCTRL............................................................................
Register Call Summary for Register CM_EMU_MPU_EMU_DBG_CLKCTRL ................................
EMU_PRM Registers Mapping Summary ..........................................................................
PM_EMU_PWRSTCTRL..............................................................................................
PM_EMU_PWRSTST .................................................................................................
RM_EMU_DEBUGSS_CONTEXT ...................................................................................
EVE1_PRM Registers Mapping Summary .........................................................................
PM_EVE1_PWRSTCTRL .............................................................................................
PM_EVE1_PWRSTST ................................................................................................
RM_EVE1_RSTCTRL .................................................................................................
3-1532. CM_EMU_CLKSTCTRL
3-1533.
3-1534.
3-1535.
3-1536.
3-1537.
3-1538.
3-1539.
3-1540.
3-1541.
3-1542.
3-1543.
3-1544.
3-1545.
3-1546.
3-1547.
SPRUIC2D – January 2017 – Revised April 2019
Submit Documentation Feedback
Copyright © 2017–2019, Texas Instruments Incorporated
List of Tables
1278
1279
1279
1280
1280
1280
1280
1281
1281
1281
1282
1283
1283
1284
1285
1286
123
www.ti.com
1286
3-1549.
1287
3-1550.
3-1551.
3-1552.
3-1553.
3-1554.
3-1555.
3-1556.
3-1557.
3-1558.
3-1559.
3-1560.
3-1561.
3-1562.
3-1563.
3-1564.
3-1565.
3-1566.
3-1567.
3-1568.
3-1569.
3-1570.
3-1571.
3-1572.
3-1573.
3-1574.
3-1575.
3-1576.
3-1577.
3-1578.
3-1579.
3-1580.
3-1581.
3-1582.
3-1583.
3-1584.
3-1585.
3-1586.
3-1587.
3-1588.
3-1589.
3-1590.
3-1591.
3-1592.
3-1593.
3-1594.
3-1595.
3-1596.
124
....................................................................................................
PM_EVE1_EVE1_WKDEP ...........................................................................................
RM_EVE1_EVE1_CONTEXT ........................................................................................
EVE2_PRM Registers Mapping Summary .........................................................................
PM_EVE2_PWRSTCTRL .............................................................................................
PM_EVE2_PWRSTST ................................................................................................
RM_EVE2_RSTCTRL .................................................................................................
RM_EVE2_RSTST ....................................................................................................
PM_EVE2_EVE2_WKDEP ...........................................................................................
RM_EVE2_EVE2_CONTEXT ........................................................................................
EVE3_PRM Registers Mapping Summary .........................................................................
PM_EVE3_PWRSTCTRL .............................................................................................
PM_EVE3_PWRSTST ................................................................................................
RM_EVE3_RSTCTRL .................................................................................................
RM_EVE3_RSTST ....................................................................................................
PM_EVE3_EVE3_WKDEP ...........................................................................................
RM_EVE3_EVE3_CONTEXT ........................................................................................
EVE4_PRM Registers Mapping Summary .........................................................................
PM_EVE4_PWRSTCTRL .............................................................................................
PM_EVE4_PWRSTST ................................................................................................
RM_EVE4_RSTCTRL .................................................................................................
RM_EVE4_RSTST ....................................................................................................
PM_EVE4_EVE4_WKDEP ...........................................................................................
RM_EVE4_EVE4_CONTEXT ........................................................................................
GPU_PRM Registers Mapping Summary ..........................................................................
PM_GPU_PWRSTCTRL ..............................................................................................
Register Call Summary for Register PM_GPU_PWRSTCTRL ..................................................
PM_GPU_PWRSTST .................................................................................................
Register Call Summary for Register PM_GPU_PWRSTST ......................................................
RM_GPU_GPU_CONTEXT ..........................................................................................
Register Call Summary for Register RM_GPU_GPU_CONTEXT ...............................................
INSTR_PRM Registers Mapping Summary ........................................................................
PMI_IDENTICATION ..................................................................................................
Register Call Summary for Register PMI_IDENTICATION.......................................................
PMI_SYS_CONFIG ....................................................................................................
Register Call Summary for Register PMI_SYS_CONFIG ........................................................
PMI_STATUS ..........................................................................................................
Register Call Summary for Register PMI_STATUS ...............................................................
PMI_CONFIGURATION ..............................................................................................
Register Call Summary for Register PMI_CONFIGURATION ...................................................
PMI_CLASS_FILTERING .............................................................................................
Register Call Summary for Register PMI_CLASS_FILTERING .................................................
PMI_TRIGGERING ....................................................................................................
Register Call Summary for Register PMI_TRIGGERING.........................................................
PMI_SAMPLING .......................................................................................................
Register Call Summary for Register PMI_SAMPLING ............................................................
IPU_PRM Registers Mapping Summary ............................................................................
PM_IPU_PWRSTCTRL ...............................................................................................
Register Call Summary for Register PM_IPU_PWRSTCTRL....................................................
3-1548. RM_EVE1_RSTST
List of Tables
1288
1289
1289
1290
1291
1291
1292
1293
1294
1294
1295
1296
1296
1297
1298
1299
1299
1300
1301
1301
1302
1303
1304
1304
1305
1305
1306
1306
1307
1307
1307
1307
1308
1308
1308
1308
1309
1309
1309
1310
1310
1310
1310
1311
1311
1312
1313
SPRUIC2D – January 2017 – Revised April 2019
Submit Documentation Feedback
Copyright © 2017–2019, Texas Instruments Incorporated
www.ti.com
3-1597. PM_IPU_PWRSTST ................................................................................................... 1313
3-1598. Register Call Summary for Register PM_IPU_PWRSTST ....................................................... 1314
3-1599. RM_IPU1_RSTCTRL .................................................................................................. 1314
3-1600. Register Call Summary for Register RM_IPU1_RSTCTRL ...................................................... 1315
3-1601. RM_IPU1_RSTST
.....................................................................................................
1315
3-1602. Register Call Summary for Register RM_IPU1_RSTST .......................................................... 1316
3-1603. RM_IPU1_IPU1_CONTEXT .......................................................................................... 1316
3-1604. Register Call Summary for Register RM_IPU1_IPU1_CONTEXT .............................................. 1317
.........................................................................................
Register Call Summary for Register PM_IPU_MCASP1_WKDEP ..............................................
RM_IPU_MCASP1_CONTEXT ......................................................................................
PM_IPU_TIMER5_WKDEP...........................................................................................
Register Call Summary for Register PM_IPU_TIMER5_WKDEP ...............................................
RM_IPU_TIMER5_CONTEXT .......................................................................................
PM_IPU_TIMER6_WKDEP...........................................................................................
Register Call Summary for Register PM_IPU_TIMER6_WKDEP ...............................................
RM_IPU_TIMER6_CONTEXT .......................................................................................
PM_IPU_TIMER7_WKDEP...........................................................................................
Register Call Summary for Register PM_IPU_TIMER7_WKDEP ...............................................
RM_IPU_TIMER7_CONTEXT .......................................................................................
PM_IPU_TIMER8_WKDEP...........................................................................................
Register Call Summary for Register PM_IPU_TIMER8_WKDEP ...............................................
RM_IPU_TIMER8_CONTEXT .......................................................................................
PM_IPU_I2C5_WKDEP ...............................................................................................
Register Call Summary for Register PM_IPU_I2C5_WKDEP ...................................................
RM_IPU_I2C5_CONTEXT ............................................................................................
PM_IPU_UART6_WKDEP ............................................................................................
Register Call Summary for Register PM_IPU_UART6_WKDEP ................................................
RM_IPU_UART6_CONTEXT ........................................................................................
IVA_PRM Registers Mapping Summary ............................................................................
PM_IVA_PWRSTCTRL ...............................................................................................
Register Call Summary for Register PM_IVA_PWRSTCTRL ....................................................
PM_IVA_PWRSTST ...................................................................................................
Register Call Summary for Register PM_IVA_PWRSTST .......................................................
RM_IVA_RSTCTRL ...................................................................................................
Register Call Summary for Register RM_IVA_RSTCTRL ........................................................
RM_IVA_RSTST .......................................................................................................
Register Call Summary for Register RM_IVA_RSTST............................................................
RM_IVA_IVA_CONTEXT .............................................................................................
Register Call Summary for Register RM_IVA_IVA_CONTEXT ..................................................
RM_IVA_SL2_CONTEXT .............................................................................................
Register Call Summary for Register RM_IVA_SL2_CONTEXT .................................................
L3INIT_PRM Registers Mapping Summary ........................................................................
PM_L3INIT_PWRSTCTRL ...........................................................................................
Register Call Summary for Register PM_L3INIT_PWRSTCTRL ................................................
PM_L3INIT_PWRSTST ...............................................................................................
Register Call Summary for Register PM_L3INIT_PWRSTST....................................................
RM_PCIESS_RSTCTRL ..............................................................................................
Register Call Summary for Register RM_PCIESS_RSTCTRL ..................................................
3-1605. PM_IPU_MCASP1_WKDEP
1317
3-1606.
1319
3-1607.
3-1608.
3-1609.
3-1610.
3-1611.
3-1612.
3-1613.
3-1614.
3-1615.
3-1616.
3-1617.
3-1618.
3-1619.
3-1620.
3-1621.
3-1622.
3-1623.
3-1624.
3-1625.
3-1626.
3-1627.
3-1628.
3-1629.
3-1630.
3-1631.
3-1632.
3-1633.
3-1634.
3-1635.
3-1636.
3-1637.
3-1638.
3-1639.
3-1640.
3-1641.
3-1642.
3-1643.
3-1644.
3-1645.
SPRUIC2D – January 2017 – Revised April 2019
Submit Documentation Feedback
Copyright © 2017–2019, Texas Instruments Incorporated
List of Tables
1319
1320
1321
1321
1322
1323
1323
1324
1325
1325
1326
1327
1327
1328
1329
1329
1330
1331
1331
1332
1332
1333
1334
1335
1335
1336
1336
1337
1337
1338
1338
1338
1338
1340
1341
1341
1342
1342
1343
125
www.ti.com
1343
3-1647.
1343
3-1648.
3-1649.
3-1650.
3-1651.
3-1652.
3-1653.
3-1654.
3-1655.
3-1656.
3-1657.
3-1658.
3-1659.
3-1660.
3-1661.
3-1662.
3-1663.
3-1664.
3-1665.
3-1666.
3-1667.
3-1668.
3-1669.
3-1670.
3-1671.
3-1672.
3-1673.
3-1674.
3-1675.
3-1676.
3-1677.
3-1678.
3-1679.
3-1680.
3-1681.
3-1682.
3-1683.
3-1684.
3-1685.
3-1686.
3-1687.
3-1688.
3-1689.
3-1690.
3-1691.
3-1692.
3-1693.
3-1694.
126
.................................................................................................
Register Call Summary for Register RM_PCIESS_RSTST ......................................................
PM_L3INIT_MMC1_WKDEP .........................................................................................
Register Call Summary for Register PM_L3INIT_MMC1_WKDEP .............................................
RM_L3INIT_MMC1_CONTEXT ......................................................................................
PM_L3INIT_MMC2_WKDEP .........................................................................................
Register Call Summary for Register PM_L3INIT_MMC2_WKDEP .............................................
RM_L3INIT_MMC2_CONTEXT ......................................................................................
PM_L3INIT_USB_OTG_SS2_WKDEP .............................................................................
Register Call Summary for Register PM_L3INIT_USB_OTG_SS2_WKDEP ..................................
RM_L3INIT_USB_OTG_SS2_CONTEXT ..........................................................................
Register Call Summary for Register RM_L3INIT_USB_OTG_SS2_CONTEXT ...............................
PM_L3INIT_USB_OTG_SS3_WKDEP .............................................................................
Register Call Summary for Register PM_L3INIT_USB_OTG_SS3_WKDEP ..................................
RM_L3INIT_USB_OTG_SS3_CONTEXT ..........................................................................
Register Call Summary for Register RM_L3INIT_USB_OTG_SS3_CONTEXT ...............................
PM_L3INIT_USB_OTG_SS4_WKDEP .............................................................................
RM_L3INIT_USB_OTG_SS4_CONTEXT ..........................................................................
RM_L3INIT_MLB_SS_CONTEXT ...................................................................................
RM_L3INIT_IEEE1500_2_OCP_CONTEXT .......................................................................
PM_L3INIT_SATA_WKDEP ..........................................................................................
Register Call Summary for Register PM_L3INIT_SATA_WKDEP ..............................................
RM_L3INIT_SATA_CONTEXT .......................................................................................
Register Call Summary for Register RM_L3INIT_SATA_CONTEXT ...........................................
PM_PCIE_PCIESS1_WKDEP .......................................................................................
Register Call Summary for Register PM_PCIE_PCIESS1_WKDEP ............................................
RM_PCIE_PCIESS1_CONTEXT ....................................................................................
Register Call Summary for Register RM_PCIE_PCIESS1_CONTEXT .........................................
PM_PCIE_PCIESS2_WKDEP .......................................................................................
Register Call Summary for Register PM_PCIE_PCIESS2_WKDEP ............................................
RM_PCIE_PCIESS2_CONTEXT ....................................................................................
Register Call Summary for Register RM_PCIE_PCIESS2_CONTEXT .........................................
RM_GMAC_GMAC_CONTEXT ......................................................................................
RM_L3INIT_OCP2SCP1_CONTEXT ...............................................................................
RM_L3INIT_OCP2SCP3_CONTEXT ...............................................................................
PM_L3INIT_USB_OTG_SS1_WKDEP .............................................................................
Register Call Summary for Register PM_L3INIT_USB_OTG_SS1_WKDEP ..................................
RM_L3INIT_USB_OTG_SS1_CONTEXT ..........................................................................
Register Call Summary for Register RM_L3INIT_USB_OTG_SS1_CONTEXT ...............................
L4PER_PRM Registers Mapping Summary ........................................................................
PM_L4PER_PWRSTCTRL ...........................................................................................
PM_L4PER_PWRSTST ...............................................................................................
RM_L4PER2_L4PER2_CONTEXT ..................................................................................
RM_L4PER3_L4PER3_CONTEXT ..................................................................................
RM_L4PER2_PRUSS1_CONTEXT .................................................................................
RM_L4PER2_PRUSS2_CONTEXT .................................................................................
PM_L4PER_TIMER10_WKDEP .....................................................................................
Register Call Summary for Register PM_L4PER_TIMER10_WKDEP..........................................
RM_L4PER_TIMER10_CONTEXT ..................................................................................
3-1646. RM_PCIESS_RSTST
List of Tables
1344
1345
1345
1346
1347
1347
1348
1349
1349
1350
1350
1351
1352
1352
1353
1354
1355
1355
1356
1357
1357
1358
1358
1359
1359
1360
1360
1361
1361
1362
1362
1363
1363
1364
1365
1365
1366
1366
1369
1370
1371
1371
1372
1373
1373
1374
1375
SPRUIC2D – January 2017 – Revised April 2019
Submit Documentation Feedback
Copyright © 2017–2019, Texas Instruments Incorporated
www.ti.com
3-1695. PM_L4PER_TIMER11_WKDEP ..................................................................................... 1375
3-1696. Register Call Summary for Register PM_L4PER_TIMER11_WKDEP.......................................... 1376
3-1697. RM_L4PER_TIMER11_CONTEXT .................................................................................. 1377
3-1698. PM_L4PER_TIMER2_WKDEP....................................................................................... 1377
3-1699. Register Call Summary for Register PM_L4PER_TIMER2_WKDEP ........................................... 1378
...................................................................................
PM_L4PER_TIMER3_WKDEP.......................................................................................
Register Call Summary for Register PM_L4PER_TIMER3_WKDEP ...........................................
RM_L4PER_TIMER3_CONTEXT ...................................................................................
PM_L4PER_TIMER4_WKDEP.......................................................................................
Register Call Summary for Register PM_L4PER_TIMER4_WKDEP ...........................................
RM_L4PER_TIMER4_CONTEXT ...................................................................................
PM_L4PER_TIMER9_WKDEP.......................................................................................
Register Call Summary for Register PM_L4PER_TIMER9_WKDEP ...........................................
RM_L4PER_TIMER9_CONTEXT ...................................................................................
RM_L4PER_ELM_CONTEXT ........................................................................................
PM_L4PER_GPIO2_WKDEP ........................................................................................
Register Call Summary for Register PM_L4PER_GPIO2_WKDEP .............................................
RM_L4PER_GPIO2_CONTEXT .....................................................................................
PM_L4PER_GPIO3_WKDEP ........................................................................................
Register Call Summary for Register PM_L4PER_GPIO3_WKDEP .............................................
RM_L4PER_GPIO3_CONTEXT .....................................................................................
PM_L4PER_GPIO4_WKDEP ........................................................................................
Register Call Summary for Register PM_L4PER_GPIO4_WKDEP .............................................
RM_L4PER_GPIO4_CONTEXT .....................................................................................
PM_L4PER_GPIO5_WKDEP ........................................................................................
Register Call Summary for Register PM_L4PER_GPIO5_WKDEP .............................................
RM_L4PER_GPIO5_CONTEXT .....................................................................................
PM_L4PER_GPIO6_WKDEP ........................................................................................
Register Call Summary for Register PM_L4PER_GPIO6_WKDEP .............................................
RM_L4PER_GPIO6_CONTEXT .....................................................................................
RM_L4PER_HDQ1W_CONTEXT ...................................................................................
RM_L4PER2_PWMSS2_CONTEXT ................................................................................
RM_L4PER2_PWMSS3_CONTEXT ................................................................................
PM_L4PER_I2C1_WKDEP ...........................................................................................
Register Call Summary for Register PM_L4PER_I2C1_WKDEP ...............................................
RM_L4PER_I2C1_CONTEXT........................................................................................
PM_L4PER_I2C2_WKDEP ...........................................................................................
Register Call Summary for Register PM_L4PER_I2C2_WKDEP ...............................................
RM_L4PER_I2C2_CONTEXT........................................................................................
PM_L4PER_I2C3_WKDEP ...........................................................................................
Register Call Summary for Register PM_L4PER_I2C3_WKDEP ...............................................
RM_L4PER_I2C3_CONTEXT........................................................................................
PM_L4PER_I2C4_WKDEP ...........................................................................................
Register Call Summary for Register PM_L4PER_I2C4_WKDEP ...............................................
RM_L4PER_I2C4_CONTEXT........................................................................................
RM_L4PER_L4PER1_CONTEXT ...................................................................................
RM_L4PER2_PWMSS1_CONTEXT ................................................................................
PM_L4PER_TIMER13_WKDEP .....................................................................................
3-1700. RM_L4PER_TIMER2_CONTEXT
3-1701.
3-1702.
3-1703.
3-1704.
3-1705.
3-1706.
3-1707.
3-1708.
3-1709.
3-1710.
3-1711.
3-1712.
3-1713.
3-1714.
3-1715.
3-1716.
3-1717.
3-1718.
3-1719.
3-1720.
3-1721.
3-1722.
3-1723.
3-1724.
3-1725.
3-1726.
3-1727.
3-1728.
3-1729.
3-1730.
3-1731.
3-1732.
3-1733.
3-1734.
3-1735.
3-1736.
3-1737.
3-1738.
3-1739.
3-1740.
3-1741.
3-1742.
3-1743.
SPRUIC2D – January 2017 – Revised April 2019
Submit Documentation Feedback
Copyright © 2017–2019, Texas Instruments Incorporated
List of Tables
1379
1379
1380
1381
1381
1382
1383
1383
1384
1385
1385
1386
1388
1388
1389
1391
1391
1392
1394
1394
1395
1397
1397
1398
1400
1400
1401
1401
1402
1402
1404
1404
1405
1406
1406
1407
1408
1409
1409
1411
1411
1411
1412
1412
127
www.ti.com
3-1744. Register Call Summary for Register PM_L4PER_TIMER13_WKDEP.......................................... 1413
3-1745. RM_L4PER3_TIMER13_CONTEXT
................................................................................
1414
3-1746. PM_L4PER_TIMER14_WKDEP ..................................................................................... 1414
3-1747. Register Call Summary for Register PM_L4PER_TIMER14_WKDEP.......................................... 1415
3-1748. RM_L4PER3_TIMER14_CONTEXT
................................................................................
1416
3-1749. PM_L4PER_TIMER15_WKDEP ..................................................................................... 1416
3-1750. Register Call Summary for Register PM_L4PER_TIMER15_WKDEP.......................................... 1417
1418
3-1752. PM_L4PER_MCSPI1_WKDEP
1418
3-1753.
1419
3-1754.
3-1755.
3-1756.
3-1757.
3-1758.
3-1759.
3-1760.
3-1761.
3-1762.
3-1763.
3-1764.
3-1765.
3-1766.
3-1767.
3-1768.
3-1769.
3-1770.
3-1771.
3-1772.
3-1773.
3-1774.
3-1775.
3-1776.
3-1777.
3-1778.
3-1779.
3-1780.
3-1781.
3-1782.
3-1783.
3-1784.
3-1785.
3-1786.
3-1787.
3-1788.
3-1789.
3-1790.
3-1791.
3-1792.
128
................................................................................
......................................................................................
Register Call Summary for Register PM_L4PER_MCSPI1_WKDEP ...........................................
RM_L4PER_MCSPI1_CONTEXT ...................................................................................
PM_L4PER_MCSPI2_WKDEP ......................................................................................
Register Call Summary for Register PM_L4PER_MCSPI2_WKDEP ...........................................
RM_L4PER_MCSPI2_CONTEXT ...................................................................................
PM_L4PER_MCSPI3_WKDEP ......................................................................................
Register Call Summary for Register PM_L4PER_MCSPI3_WKDEP ...........................................
RM_L4PER_MCSPI3_CONTEXT ...................................................................................
PM_L4PER_MCSPI4_WKDEP ......................................................................................
Register Call Summary for Register PM_L4PER_MCSPI4_WKDEP ...........................................
RM_L4PER_MCSPI4_CONTEXT ...................................................................................
PM_L4PER_GPIO7_WKDEP ........................................................................................
Register Call Summary for Register PM_L4PER_GPIO7_WKDEP .............................................
RM_L4PER_GPIO7_CONTEXT .....................................................................................
PM_L4PER_GPIO8_WKDEP ........................................................................................
Register Call Summary for Register PM_L4PER_GPIO8_WKDEP .............................................
RM_L4PER_GPIO8_CONTEXT .....................................................................................
PM_L4PER_MMC3_WKDEP ........................................................................................
Register Call Summary for Register PM_L4PER_MMC3_WKDEP .............................................
RM_L4PER_MMC3_CONTEXT .....................................................................................
PM_L4PER_MMC4_WKDEP ........................................................................................
Register Call Summary for Register PM_L4PER_MMC4_WKDEP .............................................
RM_L4PER_MMC4_CONTEXT .....................................................................................
PM_L4PER_TIMER16_WKDEP .....................................................................................
Register Call Summary for Register PM_L4PER_TIMER16_WKDEP..........................................
RM_L4PER3_TIMER16_CONTEXT ................................................................................
PM_L4PER2_QSPI_WKDEP ........................................................................................
Register Call Summary for Register PM_L4PER2_QSPI_WKDEP .............................................
RM_L4PER2_QSPI_CONTEXT .....................................................................................
PM_L4PER_UART1_WKDEP........................................................................................
Register Call Summary for Register PM_L4PER_UART1_WKDEP ............................................
RM_L4PER_UART1_CONTEXT ....................................................................................
PM_L4PER_UART2_WKDEP........................................................................................
Register Call Summary for Register PM_L4PER_UART2_WKDEP ............................................
RM_L4PER_UART2_CONTEXT ....................................................................................
PM_L4PER_UART3_WKDEP........................................................................................
Register Call Summary for Register PM_L4PER_UART3_WKDEP ............................................
RM_L4PER_UART3_CONTEXT ....................................................................................
PM_L4PER_UART4_WKDEP........................................................................................
Register Call Summary for Register PM_L4PER_UART4_WKDEP ............................................
3-1751. RM_L4PER3_TIMER15_CONTEXT
List of Tables
1420
1420
1421
1422
1422
1423
1424
1424
1425
1426
1426
1428
1428
1429
1431
1431
1432
1433
1433
1434
1435
1435
1436
1437
1437
1438
1439
1439
1440
1441
1441
1442
1443
1443
1444
1445
1446
1446
1448
SPRUIC2D – January 2017 – Revised April 2019
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Copyright © 2017–2019, Texas Instruments Incorporated
www.ti.com
....................................................................................
PM_L4PER2_MCASP2_WKDEP ....................................................................................
Register Call Summary for Register PM_L4PER2_MCASP2_WKDEP ........................................
RM_L4PER2_MCASP2_CONTEXT .................................................................................
PM_L4PER2_MCASP3_WKDEP ....................................................................................
Register Call Summary for Register PM_L4PER2_MCASP3_WKDEP ........................................
RM_L4PER2_MCASP3_CONTEXT .................................................................................
PM_L4PER_UART5_WKDEP........................................................................................
Register Call Summary for Register PM_L4PER_UART5_WKDEP ............................................
RM_L4PER_UART5_CONTEXT ....................................................................................
PM_L4PER2_MCASP5_WKDEP ....................................................................................
Register Call Summary for Register PM_L4PER2_MCASP5_WKDEP ........................................
RM_L4PER2_MCASP5_CONTEXT .................................................................................
PM_L4PER2_MCASP6_WKDEP ....................................................................................
Register Call Summary for Register PM_L4PER2_MCASP6_WKDEP ........................................
RM_L4PER2_MCASP6_CONTEXT .................................................................................
PM_L4PER2_MCASP7_WKDEP ....................................................................................
Register Call Summary for Register PM_L4PER2_MCASP7_WKDEP ........................................
RM_L4PER2_MCASP7_CONTEXT .................................................................................
PM_L4PER2_MCASP8_WKDEP ....................................................................................
Register Call Summary for Register PM_L4PER2_MCASP8_WKDEP ........................................
RM_L4PER2_MCASP8_CONTEXT .................................................................................
PM_L4PER2_MCASP4_WKDEP ....................................................................................
Register Call Summary for Register PM_L4PER2_MCASP4_WKDEP ........................................
RM_L4PER2_MCASP4_CONTEXT .................................................................................
RM_L4SEC_AES1_CONTEXT ......................................................................................
RM_L4SEC_AES2_CONTEXT ......................................................................................
RM_L4SEC_DES3DES_CONTEXT .................................................................................
RM_L4SEC_FPKA_CONTEXT ......................................................................................
RM_L4SEC_RNG_CONTEXT .......................................................................................
RM_L4SEC_SHA2MD51_CONTEXT ...............................................................................
PM_L4PER2_UART7_WKDEP ......................................................................................
Register Call Summary for Register PM_L4PER2_UART7_WKDEP...........................................
RM_L4PER2_UART7_CONTEXT ...................................................................................
RM_L4SEC_DMA_CRYPTO_CONTEXT...........................................................................
PM_L4PER2_UART8_WKDEP ......................................................................................
Register Call Summary for Register PM_L4PER2_UART8_WKDEP...........................................
RM_L4PER2_UART8_CONTEXT ...................................................................................
PM_L4PER2_UART9_WKDEP ......................................................................................
Register Call Summary for Register PM_L4PER2_UART9_WKDEP...........................................
RM_L4PER2_UART9_CONTEXT ...................................................................................
PM_L4PER2_DCAN2_WKDEP ......................................................................................
Register Call Summary for Register PM_L4PER2_DCAN2_WKDEP ..........................................
RM_L4PER2_DCAN2_CONTEXT ...................................................................................
RM_L4SEC_SHA2MD52_CONTEXT ...............................................................................
MPU_PRM Registers Mapping Summary ..........................................................................
PM_MPU_PWRSTCTRL..............................................................................................
Register Call Summary for Register PM_MPU_PWRSTCTRL ..................................................
PM_MPU_PWRSTST .................................................................................................
3-1793. RM_L4PER_UART4_CONTEXT
3-1794.
3-1795.
3-1796.
3-1797.
3-1798.
3-1799.
3-1800.
3-1801.
3-1802.
3-1803.
3-1804.
3-1805.
3-1806.
3-1807.
3-1808.
3-1809.
3-1810.
3-1811.
3-1812.
3-1813.
3-1814.
3-1815.
3-1816.
3-1817.
3-1818.
3-1819.
3-1820.
3-1821.
3-1822.
3-1823.
3-1824.
3-1825.
3-1826.
3-1827.
3-1828.
3-1829.
3-1830.
3-1831.
3-1832.
3-1833.
3-1834.
3-1835.
3-1836.
3-1837.
3-1838.
3-1839.
3-1840.
3-1841.
SPRUIC2D – January 2017 – Revised April 2019
Submit Documentation Feedback
Copyright © 2017–2019, Texas Instruments Incorporated
List of Tables
1448
1449
1450
1450
1451
1452
1453
1453
1454
1455
1455
1457
1457
1458
1459
1459
1460
1461
1462
1462
1464
1464
1465
1466
1466
1467
1467
1468
1468
1469
1469
1470
1471
1471
1472
1473
1474
1474
1475
1476
1476
1477
1478
1478
1479
1479
1480
1481
1481
129
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3-1842. Register Call Summary for Register PM_MPU_PWRSTST ...................................................... 1482
3-1843. RM_MPU_MPU_CONTEXT .......................................................................................... 1482
3-1844. Register Call Summary for Register RM_MPU_MPU_CONTEXT
..............................................
1483
3-1845. OCP_SOCKET_PRM Registers Mapping Summary .............................................................. 1483
3-1846. REVISION_PRM ....................................................................................................... 1484
3-1847. Register Call Summary for Register REVISION_PRM............................................................ 1484
3-1848. PRM_IRQSTATUS_MPU ............................................................................................. 1484
3-1849. Register Call Summary for Register PRM_IRQSTATUS_MPU
.................................................
1486
3-1850. PRM_IRQSTATUS_MPU_2 .......................................................................................... 1486
3-1851. Register Call Summary for Register PRM_IRQSTATUS_MPU_2
..............................................
1487
3-1852. PRM_IRQENABLE_MPU ............................................................................................. 1487
3-1853. Register Call Summary for Register PRM_IRQENABLE_MPU
.................................................
1488
3-1854. PRM_IRQENABLE_MPU_2 .......................................................................................... 1489
..............................................
PRM_IRQSTATUS_IPU2 .............................................................................................
Register Call Summary for Register PRM_IRQSTATUS_IPU2 .................................................
PRM_IRQENABLE_IPU2 .............................................................................................
Register Call Summary for Register PRM_IRQENABLE_IPU2 .................................................
PRM_IRQSTATUS_DSP1 ............................................................................................
Register Call Summary for Register PRM_IRQSTATUS_DSP1 ................................................
PRM_IRQENABLE_DSP1 ............................................................................................
Register Call Summary for Register PRM_IRQENABLE_DSP1 ................................................
CM_PRM_PROFILING_CLKCTRL ..................................................................................
Register Call Summary for Register CM_PRM_PROFILING_CLKCTRL ......................................
PRM_IRQENABLE_DSP2 ............................................................................................
PRM_IRQENABLE_EVE1 ............................................................................................
PRM_IRQENABLE_EVE2 ............................................................................................
PRM_IRQENABLE_EVE3 ............................................................................................
PRM_IRQENABLE_EVE4 ............................................................................................
PRM_IRQENABLE_IPU1 .............................................................................................
Register Call Summary for Register PRM_IRQENABLE_IPU1 .................................................
PRM_IRQSTATUS_DSP2 ............................................................................................
PRM_IRQSTATUS_EVE1 ............................................................................................
PRM_IRQSTATUS_EVE2 ............................................................................................
PRM_IRQSTATUS_EVE3 ............................................................................................
PRM_IRQSTATUS_EVE4 ............................................................................................
PRM_IRQSTATUS_IPU1 .............................................................................................
Register Call Summary for Register PRM_IRQSTATUS_IPU1 .................................................
PRM_DEBUG_CFG1 ..................................................................................................
Register Call Summary for Register PRM_DEBUG_CFG1 ......................................................
PRM_DEBUG_CFG2 ..................................................................................................
Register Call Summary for Register PRM_DEBUG_CFG2 ......................................................
PRM_DEBUG_CFG3 ..................................................................................................
Register Call Summary for Register PRM_DEBUG_CFG3 ......................................................
PRM_DEBUG_CFG ...................................................................................................
Register Call Summary for Register PRM_DEBUG_CFG ........................................................
PRM_DEBUG_OUT ...................................................................................................
Register Call Summary for Register PRM_DEBUG_OUT ........................................................
RTC_PRM Registers Mapping Summary ...........................................................................
3-1855. Register Call Summary for Register PRM_IRQENABLE_MPU_2
3-1856.
3-1857.
3-1858.
3-1859.
3-1860.
3-1861.
3-1862.
3-1863.
3-1864.
3-1865.
3-1866.
3-1867.
3-1868.
3-1869.
3-1870.
3-1871.
3-1872.
3-1873.
3-1874.
3-1875.
3-1876.
3-1877.
3-1878.
3-1879.
3-1880.
3-1881.
3-1882.
3-1883.
3-1884.
3-1885.
3-1886.
3-1887.
3-1888.
3-1889.
3-1890.
130
List of Tables
1489
1489
1491
1492
1493
1494
1495
1496
1497
1498
1498
1498
1500
1501
1503
1504
1506
1507
1508
1509
1511
1513
1515
1516
1518
1518
1519
1519
1519
1519
1519
1520
1520
1520
1520
1520
SPRUIC2D – January 2017 – Revised April 2019
Submit Documentation Feedback
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www.ti.com
3-1891. PM_RTC_RTCSS_WKDEP .......................................................................................... 1521
3-1892. Register Call Summary for Register PM_RTC_RTCSS_WKDEP ............................................... 1523
3-1893. RM_RTC_RTCSS_CONTEXT ....................................................................................... 1523
3-1894. Register Call Summary for Register RM_RTC_RTCSS_CONTEXT ............................................ 1523
3-1895. VPE_PRM Registers Mapping Summary ........................................................................... 1524
3-1896. PM_VPE_PWRSTCTRL .............................................................................................. 1524
3-1897. Register Call Summary for Register PM_VPE_PWRSTCTRL ................................................... 1525
3-1898. PM_VPE_PWRSTST .................................................................................................. 1525
3-1899. Register Call Summary for Register PM_VPE_PWRSTST ...................................................... 1526
3-1900. PM_VPE_VPE_WKDEP .............................................................................................. 1526
3-1901. Register Call Summary for Register PM_VPE_VPE_WKDEP ................................................... 1527
3-1902. RM_VPE_VPE_CONTEXT ........................................................................................... 1528
3-1903. Register Call Summary for Register RM_VPE_VPE_CONTEXT................................................ 1528
3-1904. WKUPAON_CM Registers Mapping Summary .................................................................... 1528
3-1905. CM_WKUPAON_CLKSTCTRL....................................................................................... 1529
3-1906. Register Call Summary for Register CM_WKUPAON_CLKSTCTRL ........................................... 1531
3-1907. CM_WKUPAON_L4_WKUP_CLKCTRL ............................................................................ 1531
3-1908. Register Call Summary for Register CM_WKUPAON_L4_WKUP_CLKCTRL
................................
1532
3-1909. CM_WKUPAON_WD_TIMER1_CLKCTRL......................................................................... 1532
3-1910. CM_WKUPAON_WD_TIMER2_CLKCTRL......................................................................... 1533
3-1911. Register Call Summary for Register CM_WKUPAON_WD_TIMER2_CLKCTRL ............................. 1533
3-1912. CM_WKUPAON_GPIO1_CLKCTRL ................................................................................ 1534
3-1913. Register Call Summary for Register CM_WKUPAON_GPIO1_CLKCTRL ..................................... 1534
3-1914. CM_WKUPAON_TIMER1_CLKCTRL............................................................................... 1535
3-1915. Register Call Summary for Register CM_WKUPAON_TIMER1_CLKCTRL ................................... 1536
3-1916. CM_WKUPAON_TIMER12_CLKCTRL ............................................................................. 1536
3-1917. Register Call Summary for Register CM_WKUPAON_TIMER12_CLKCTRL .................................. 1536
3-1918. CM_WKUPAON_COUNTER_32K_CLKCTRL ..................................................................... 1537
.........................
CM_WKUPAON_SAR_RAM_CLKCTRL ...........................................................................
CM_WKUPAON_KBD_CLKCTRL ...................................................................................
Register Call Summary for Register CM_WKUPAON_KBD_CLKCTRL .......................................
CM_WKUPAON_UART10_CLKCTRL ..............................................................................
Register Call Summary for Register CM_WKUPAON_UART10_CLKCTRL ...................................
CM_WKUPAON_DCAN1_CLKCTRL ...............................................................................
Register Call Summary for Register CM_WKUPAON_DCAN1_CLKCTRL ....................................
CM_WKUPAON_SCRM_CLKCTRL.................................................................................
CM_WKUPAON_IO_SRCOMP_CLKCTRL ........................................................................
CM_WKUPAON_ADC_CLKCTRL ...................................................................................
CM_WKUPAON_SPARE_SAFETY1_CLKCTRL ..................................................................
CM_WKUPAON_SPARE_SAFETY2_CLKCTRL ..................................................................
CM_WKUPAON_SPARE_SAFETY3_CLKCTRL ..................................................................
CM_WKUPAON_SPARE_SAFETY4_CLKCTRL ..................................................................
CM_WKUPAON_SPARE_UNKNOWN2_CLKCTRL ..............................................................
CM_WKUPAON_SPARE_UNKNOWN3_CLKCTRL ..............................................................
WKUPAON_PRM Registers Mapping Summary ..................................................................
RM_WKUPAON_L4_WKUP_CONTEXT ...........................................................................
Register Call Summary for Register RM_WKUPAON_L4_WKUP_CONTEXT ................................
PM_WKUPAON_WD_TIMER1_WKDEP ...........................................................................
3-1919. Register Call Summary for Register CM_WKUPAON_COUNTER_32K_CLKCTRL
3-1920.
3-1921.
3-1922.
3-1923.
3-1924.
3-1925.
3-1926.
3-1927.
3-1928.
3-1929.
3-1930.
3-1931.
3-1932.
3-1933.
3-1934.
3-1935.
3-1936.
3-1937.
3-1938.
3-1939.
SPRUIC2D – January 2017 – Revised April 2019
Submit Documentation Feedback
Copyright © 2017–2019, Texas Instruments Incorporated
List of Tables
1537
1537
1538
1539
1539
1539
1540
1540
1541
1541
1542
1542
1543
1544
1544
1545
1546
1546
1547
1547
1548
131
www.ti.com
3-1940. RM_WKUPAON_WD_TIMER1_CONTEXT ........................................................................ 1549
3-1941. PM_WKUPAON_WD_TIMER2_WKDEP ........................................................................... 1550
3-1942. Register Call Summary for Register PM_WKUPAON_WD_TIMER2_WKDEP ................................ 1551
3-1943. RM_WKUPAON_WD_TIMER2_CONTEXT ........................................................................ 1551
3-1944. Register Call Summary for Register RM_WKUPAON_WD_TIMER2_CONTEXT............................. 1551
3-1945. PM_WKUPAON_GPIO1_WKDEP ................................................................................... 1552
3-1946. Register Call Summary for Register PM_WKUPAON_GPIO1_WKDEP ....................................... 1554
3-1947. RM_WKUPAON_GPIO1_CONTEXT ................................................................................ 1554
3-1948. Register Call Summary for Register RM_WKUPAON_GPIO1_CONTEXT .................................... 1554
3-1949. PM_WKUPAON_TIMER1_WKDEP ................................................................................. 1555
3-1950. Register Call Summary for Register PM_WKUPAON_TIMER1_WKDEP ...................................... 1556
3-1951. RM_WKUPAON_TIMER1_CONTEXT .............................................................................. 1556
3-1952. Register Call Summary for Register RM_WKUPAON_TIMER1_CONTEXT
..................................
1556
3-1953. PM_WKUPAON_TIMER12_WKDEP ................................................................................ 1557
3-1954. Register Call Summary for Register PM_WKUPAON_TIMER12_WKDEP .................................... 1558
............................................................................
3-1956. Register Call Summary for Register RM_WKUPAON_TIMER12_CONTEXT .................................
3-1957. RM_WKUPAON_COUNTER_32K_CONTEXT ....................................................................
3-1958. Register Call Summary for Register RM_WKUPAON_COUNTER_32K_CONTEXT .........................
3-1959. RM_WKUPAON_SAR_RAM_CONTEXT ...........................................................................
3-1960. PM_WKUPAON_KBD_WKDEP .....................................................................................
3-1961. Register Call Summary for Register PM_WKUPAON_KBD_WKDEP ..........................................
3-1962. RM_WKUPAON_KBD_CONTEXT ..................................................................................
3-1963. Register Call Summary for Register RM_WKUPAON_KBD_CONTEXT .......................................
3-1964. PM_WKUPAON_UART10_WKDEP .................................................................................
3-1965. Register Call Summary for Register PM_WKUPAON_UART10_WKDEP .....................................
3-1966. RM_WKUPAON_UART10_CONTEXT..............................................................................
3-1967. Register Call Summary for Register RM_WKUPAON_UART10_CONTEXT ..................................
3-1968. PM_WKUPAON_DCAN1_WKDEP ..................................................................................
3-1969. Register Call Summary for Register PM_WKUPAON_DCAN1_WKDEP ......................................
3-1970. RM_WKUPAON_DCAN1_CONTEXT ...............................................................................
3-1971. Register Call Summary for Register RM_WKUPAON_DCAN1_CONTEXT ...................................
3-1972. PM_WKUPAON_ADC_WKDEP .....................................................................................
3-1973. RM_WKUPAON_ADC_CONTEXT ..................................................................................
3-1974. RM_WKUPAON_SPARE_SAFETY1_CONTEXT .................................................................
3-1975. RM_WKUPAON_SPARE_SAFETY2_CONTEXT .................................................................
3-1976. RM_WKUPAON_SPARE_SAFETY3_CONTEXT .................................................................
3-1977. RM_WKUPAON_SPARE_SAFETY4_CONTEXT .................................................................
3-1978. RM_WKUPAON_SPARE_UNKNOWN2_CONTEXT .............................................................
3-1979. RM_WKUPAON_SPARE_UNKNOWN3_CONTEXT .............................................................
4-1.
MPU Subsystem Clocks Frequency Value Versus OPP ...........................................................
4-2.
AXI Access Memory Mapping ........................................................................................
4-3.
MPU_MA Registers Duplicated From the DMM Register Map ...................................................
4-4.
COUNTER_REALTIME Increment Values...........................................................................
4-5.
MPU_C0 State Transitions .............................................................................................
4-6.
MPU_C0 Supported Power States ....................................................................................
4-7.
MPU Subsystem Legal Power States ................................................................................
4-8.
Cortex-A15 MPU Subsystem Instance Summary ...................................................................
4-9.
Local PRCM Revision Register Mapping Summary ................................................................
3-1955. RM_WKUPAON_TIMER12_CONTEXT
132
List of Tables
1558
1558
1559
1559
1559
1560
1561
1561
1562
1562
1563
1563
1564
1564
1565
1566
1566
1566
1568
1568
1569
1569
1570
1570
1571
1579
1588
1590
1595
1600
1601
1601
1605
1605
SPRUIC2D – January 2017 – Revised April 2019
Submit Documentation Feedback
Copyright © 2017–2019, Texas Instruments Incorporated
www.ti.com
4-10.
REVISION_PRCM_MPU ............................................................................................... 1606
4-11.
Register Call Summary for Register REVISION_PRCM_MPU
4-12.
MPU_PRCM_DEVICE Registers Mapping Summary .............................................................. 1606
4-13.
PRM_RSTST
4-14.
4-15.
4-16.
4-17.
4-18.
4-19.
4-20.
4-21.
4-22.
4-23.
4-24.
4-25.
4-26.
4-27.
4-28.
4-29.
4-30.
4-31.
4-32.
4-33.
4-34.
4-35.
4-36.
4-37.
4-38.
4-39.
4-40.
4-41.
4-42.
4-43.
4-44.
4-45.
4-46.
4-47.
4-48.
4-49.
4-50.
4-51.
4-52.
4-53.
4-54.
4-55.
4-56.
4-57.
4-58.
...................................................
............................................................................................................
Register Call Summary for Register PRM_RSTST .................................................................
PRM_PSCON_COUNT.................................................................................................
Register Call Summary for Register PRM_PSCON_COUNT .....................................................
PRM_FRAC_INCREMENTER_NUMERATOR ......................................................................
Register Call Summary for Register PRM_FRAC_INCREMENTER_NUMERATOR ..........................
PRM_FRAC_INCREMENTER_DENUMERATOR_RELOAD .....................................................
Register Call Summary for Register PRM_FRAC_INCREMENTER_DENUMERATOR_RELOAD ..........
MPU_PRCM_PRM_C0 Registers Mapping Summary .............................................................
PM_CPU0_PWRSTCTRL ..............................................................................................
Register Call Summary for Register PM_CPU0_PWRSTCTRL ..................................................
PM_CPU0_PWRSTST .................................................................................................
Register Call Summary for Register PM_CPU0_PWRSTST ......................................................
RM_CPU0_CPU0_RSTCTRL .........................................................................................
Register Call Summary for Register RM_CPU0_CPU0_RSTCTRL ..............................................
RM_CPU0_CPU0_RSTST .............................................................................................
Register Call Summary for Register RM_CPU0_CPU0_RSTST .................................................
RM_CPU0_CPU0_CONTEXT .........................................................................................
Register Call Summary for Register RM_CPU0_CPU0_CONTEXT .............................................
MPU_PRCM_CM_C0 Registers Mapping Summary ...............................................................
CM_CPU0_CLKSTCTRL ...............................................................................................
Register Call Summary for Register CM_CPU0_CLKSTCTRL ...................................................
CM_CPU0_CPU0_CLKCTRL .........................................................................................
Register Call Summary for Register CM_CPU0_CPU0_CLKCTRL ..............................................
MPU_WUGEN Registers Mapping Summary .......................................................................
WKG_CONTROL_0 .....................................................................................................
Register Call Summary for Register WKG_CONTROL_0 .........................................................
WKG_ENB_A_0 .........................................................................................................
Register Call Summary for Register WKG_ENB_A_0..............................................................
WKG_ENB_B_0 .........................................................................................................
Register Call Summary for Register WKG_ENB_B_0..............................................................
WKG_ENB_C_0 .........................................................................................................
Register Call Summary for Register WKG_ENB_C_0 .............................................................
WKG_ENB_D_0 .........................................................................................................
Register Call Summary for Register WKG_ENB_D_0 .............................................................
WKG_ENB_E_0 .........................................................................................................
Register Call Summary for Register WKG_ENB_E_0..............................................................
STM_HWEVENTS_INV ................................................................................................
Register Call Summary for Register STM_HWEVENTS_INV .....................................................
AMBA_IF_MODE ........................................................................................................
Register Call Summary for Register AMBA_IF_MODE ............................................................
TIMESTAMPCYCLELO ................................................................................................
Register Call Summary for Register TIMESTAMPCYCLELO .....................................................
TIMESTAMPCYCLEHI .................................................................................................
Register Call Summary for Register TIMESTAMPCYCLEHI ......................................................
MPU_WD_TIMER Registers Mapping Summary ...................................................................
SPRUIC2D – January 2017 – Revised April 2019
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Copyright © 2017–2019, Texas Instruments Incorporated
List of Tables
1606
1607
1607
1608
1608
1609
1609
1609
1610
1610
1610
1611
1611
1612
1612
1612
1613
1613
1613
1614
1614
1614
1615
1615
1615
1615
1616
1617
1617
1618
1619
1620
1620
1621
1621
1622
1622
1623
1623
1625
1626
1626
1626
1626
1627
1627
1627
133
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4-59.
4-60.
4-61.
4-62.
4-63.
4-64.
4-65.
4-66.
4-67.
4-68.
4-69.
4-70.
4-71.
4-72.
4-73.
4-74.
4-75.
4-76.
4-77.
4-78.
4-79.
4-80.
4-81.
4-82.
4-83.
4-84.
4-85.
4-86.
4-87.
4-88.
4-89.
4-90.
4-91.
4-92.
4-93.
4-94.
4-95.
4-96.
4-97.
4-98.
4-99.
4-100.
4-101.
4-102.
4-103.
4-104.
4-105.
4-106.
4-107.
134
...........................................................................................
Register Call Summary for Register WDT_LOAD_REGISTER_0 ................................................
WDT_COUNT_REGISTER_0 .........................................................................................
Register Call Summary for Register WDT_COUNT_REGISTER_0 ..............................................
WDT_WARNING_REGISTER_0 ......................................................................................
Register Call Summary for Register WDT_WARNING_REGISTER_0 ..........................................
WDT_PRESCALER_REGISTER_0 ..................................................................................
Register Call Summary for Register WDT_PRESCALER_REGISTER_0 .......................................
WDT_CONTROL_REGISTER_0 ......................................................................................
Register Call Summary for Register WDT_CONTROL_REGISTER_0 ..........................................
WDT_RESET_STATUS_REGISTER_0 ..............................................................................
Register Call Summary for Register WDT_RESET_STATUS_REGISTER_0 ..................................
MPU_AXI2OCP_MISC Register Mapping Summary ...............................................................
MA_PRIORITY ..........................................................................................................
Register Call Summary for Register MA_PRIORITY ...............................................................
MPU_MA_LSM Register Mapping Summary ........................................................................
MPU_MA_WP Registers Mapping Summary ........................................................................
DBG_HWWP_CAP......................................................................................................
Register Call Summary for Register DBG_HWWP_CAP ..........................................................
TRIG_CTRL ..............................................................................................................
Register Call Summary for Register TRIG_CTRL ..................................................................
DBG_HWWP0_LW_ADDR0 ...........................................................................................
Register Call Summary for Register DBG_HWWP0_LW_ADDR0 ...............................................
DBG_HWWP0_HG_ADDR0 ...........................................................................................
Register Call Summary for Register DBG_HWWP0_HG_ADDR0 ...............................................
DBG_HWWP0_MAIN_CNTL ..........................................................................................
Register Call Summary for Register DBG_HWWP0_MAIN_CNTL ...............................................
DBG_HWWP0_AUX_CNTL ...........................................................................................
Register Call Summary for Register DBG_HWWP0_AUX_CNTL ................................................
DBG_HWWP0_MEM_CNTL ...........................................................................................
Register Call Summary for Register DBG_HWWP0_MEM_CNTL ...............................................
DBG_HWWP0_CHAIN_CNTL .........................................................................................
Register Call Summary for Register DBG_HWWP0_CHAIN_CNTL .............................................
DBG_HWWP0_LW_ADDR0_LOG ....................................................................................
Register Call Summary for Register DBG_HWWP0_LW_ADDR0_LOG ........................................
DBG_HWWP0_HG_ADDR0_LOG ....................................................................................
Register Call Summary for Register DBG_HWWP0_HG_ADDR0_LOG ........................................
DBG_HWWP0_DATA0_LOG ..........................................................................................
Register Call Summary for Register DBG_HWWP0_DATA0_LOG ..............................................
DBG_HWWP0_DATA1_LOG ..........................................................................................
Register Call Summary for Register DBG_HWWP0_DATA1_LOG ..............................................
DBG_HWWP0_DATA2_LOG ..........................................................................................
Register Call Summary for Register DBG_HWWP0_DATA2_LOG ..............................................
DBG_HWWP0_DATA3_LOG ..........................................................................................
Register Call Summary for Register DBG_HWWP0_DATA3_LOG ..............................................
DBG_HWWP0_TRANS_ATTR0_LOG ...............................................................................
Register Call Summary for Register DBG_HWWP0_TRANS_ATTR0_LOG ....................................
DBG_HWWP0_TRANS_ATTR1_LOG ...............................................................................
Register Call Summary for Register DBG_HWWP0_TRANS_ATTR1_LOG ....................................
WDT_LOAD_REGISTER_0
List of Tables
1627
1628
1628
1628
1628
1629
1629
1629
1629
1630
1630
1631
1631
1631
1631
1632
1632
1633
1634
1634
1634
1634
1634
1635
1635
1635
1636
1636
1637
1637
1638
1638
1639
1639
1639
1639
1640
1640
1640
1640
1641
1641
1641
1641
1641
1642
1643
1643
1643
SPRUIC2D – January 2017 – Revised April 2019
Submit Documentation Feedback
Copyright © 2017–2019, Texas Instruments Incorporated
www.ti.com
......................................................................
Register Call Summary for Register DBG_HWWP0_DATA_TRANS_ATTR0_LOG ...........................
DSP1 Integration Attributes ............................................................................................
DSP1 Clocks and Resets ..............................................................................................
DSP1 Hardware Interrupt Requests ..................................................................................
Summary of the DSP1 Hardware Resets ...........................................................................
DSP ERRINT Interrupt Mapping ......................................................................................
DSP1_EDMA Default Request Mapping .............................................................................
DSP_NoC Defined Connectivities .....................................................................................
C66x CPU View Map ...................................................................................................
DSP EDMA Controller View Map .....................................................................................
SDMA Target Port Memory Map ......................................................................................
DSP Subsystem Instance Summary ..................................................................................
DSP_ICFG Registers Mapping Summary............................................................................
DSP_SYSTEM and DSP1_SYSTEM Registers Mapping Summary .............................................
DSP_SYS_REVISION ..................................................................................................
Register Call Summary for Register DSP_SYS_REVISION ......................................................
DSP_SYS_HWINFO ....................................................................................................
Register Call Summary for Register DSP_SYS_HWINFO ........................................................
DSP_SYS_SYSCONFIG ...............................................................................................
Register Call Summary for Register DSP_SYS_SYSCONFIG ...................................................
DSP_SYS_STAT ........................................................................................................
Register Call Summary for Register DSP_SYS_STAT ............................................................
DSP_SYS_DISC_CONFIG ............................................................................................
Register Call Summary for Register DSP_SYS_DISC_CONFIG .................................................
DSP_SYS_BUS_CONFIG .............................................................................................
Register Call Summary for Register DSP_SYS_BUS_CONFIG ..................................................
DSP_SYS_MMU_CONFIG ............................................................................................
Register Call Summary for Register DSP_SYS_MMU_CONFIG .................................................
DSP_SYS_IRQWAKEEN0 .............................................................................................
Register Call Summary for Register DSP_SYS_IRQWAKEEN0 .................................................
DSP_SYS_IRQWAKEEN1 .............................................................................................
Register Call Summary for Register DSP_SYS_IRQWAKEEN1 .................................................
DSP_SYS_DMAWAKEEN0 ............................................................................................
Register Call Summary for Register DSP_SYS_DMAWAKEEN0 ................................................
DSP_SYS_DMAWAKEEN1 ............................................................................................
Register Call Summary for Register DSP_SYS_DMAWAKEEN1 ................................................
DSP_SYS_EVTOUT_SET .............................................................................................
Register Call Summary for Register DSP_SYS_EVTOUT_SET ..................................................
DSP_SYS_EVTOUT_CLR .............................................................................................
Register Call Summary for Register DSP_SYS_EVTOUT_CLR..................................................
DSP_SYS_ERRINT_IRQSTATUS_RAW ............................................................................
Register Call Summary for Register DSP_SYS_ERRINT_IRQSTATUS_RAW.................................
DSP_SYS_ERRINT_IRQSTATUS ....................................................................................
Register Call Summary for Register DSP_SYS_ERRINT_IRQSTATUS ........................................
DSP_SYS_ERRINT_IRQENABLE_SET .............................................................................
Register Call Summary for Register DSP_SYS_ERRINT_IRQENABLE_SET ..................................
DSP_SYS_ERRINT_IRQENABLE_CLR .............................................................................
Register Call Summary for Register DSP_SYS_ERRINT_IRQENABLE_CLR .................................
4-108. DBG_HWWP0_DATA_TRANS_ATTR0_LOG
1643
4-109.
1644
5-1.
5-2.
5-3.
5-4.
5-5.
5-6.
5-7.
5-8.
5-9.
5-10.
5-11.
5-12.
5-13.
5-14.
5-15.
5-16.
5-17.
5-18.
5-19.
5-20.
5-21.
5-22.
5-23.
5-24.
5-25.
5-26.
5-27.
5-28.
5-29.
5-30.
5-31.
5-32.
5-33.
5-34.
5-35.
5-36.
5-37.
5-38.
5-39.
5-40.
5-41.
5-42.
5-43.
5-44.
5-45.
5-46.
5-47.
SPRUIC2D – January 2017 – Revised April 2019
Submit Documentation Feedback
Copyright © 2017–2019, Texas Instruments Incorporated
List of Tables
1651
1652
1653
1666
1673
1677
1684
1687
1688
1689
1689
1690
1694
1695
1695
1696
1696
1696
1697
1697
1698
1698
1699
1699
1700
1701
1701
1701
1702
1702
1702
1703
1703
1703
1704
1704
1704
1704
1705
1705
1705
1705
1706
1706
1706
1706
1707
135
www.ti.com
5-48.
DSP_SYS_EDMAWAKE0_IRQSTATUS_RAW ..................................................................... 1707
5-49.
Register Call Summary for Register DSP_SYS_EDMAWAKE0_IRQSTATUS_RAW
5-50.
DSP_SYS_EDMAWAKE0_IRQSTATUS ............................................................................. 1707
5-51.
Register Call Summary for Register DSP_SYS_EDMAWAKE0_IRQSTATUS ................................. 1708
5-52.
DSP_SYS_EDMAWAKE0_IRQENABLE_SET ...................................................................... 1708
5-53.
Register Call Summary for Register DSP_SYS_EDMAWAKE0_IRQENABLE_SET
5-54.
5-55.
5-56.
5-57.
5-58.
5-59.
5-60.
5-61.
5-62.
5-63.
5-64.
5-65.
5-66.
5-67.
5-68.
5-69.
136
.........................
..........................
DSP_SYS_EDMAWAKE0_IRQENABLE_CLR ......................................................................
Register Call Summary for Register DSP_SYS_EDMAWAKE0_IRQENABLE_CLR ..........................
DSP_SYS_EDMAWAKE1_IRQSTATUS_RAW .....................................................................
Register Call Summary for Register DSP_SYS_EDMAWAKE1_IRQSTATUS_RAW .........................
DSP_SYS_EDMAWAKE1_IRQSTATUS .............................................................................
Register Call Summary for Register DSP_SYS_EDMAWAKE1_IRQSTATUS .................................
DSP_SYS_EDMAWAKE1_IRQENABLE_SET ......................................................................
Register Call Summary for Register DSP_SYS_EDMAWAKE1_IRQENABLE_SET ..........................
DSP_SYS_EDMAWAKE1_IRQENABLE_CLR ......................................................................
Register Call Summary for Register DSP_SYS_EDMAWAKE1_IRQENABLE_CLR ..........................
DSP_SYS_HW_DBGOUT_SEL .......................................................................................
Register Call Summary for Register DSP_SYS_HW_DBGOUT_SEL ...........................................
DSP_SYS_HW_DBGOUT_VAL .......................................................................................
Register Call Summary for Register DSP_SYS_HW_DBGOUT_VAL ...........................................
DSP_FW_L2_NOC_CFG and DSP1_FW_L2_NOC_CFG Registers Mapping Summary.....................
L3_DSPSS_INIT_OCP_MMU0_CTRL_TARG_OCP_FW_503000_ERROR_LOG_0 .........................
1707
1708
1708
1709
1709
1709
1709
1709
1710
1710
1710
1710
1710
1711
1711
1711
1712
1714
5-70.
Register Call Summary for Register
L3_DSPSS_INIT_OCP_MMU0_CTRL_TARG_OCP_FW_503000_ERROR_LOG_0 ......................... 1714
5-71.
L3_DSPSS_INIT_OCP_MMU0_CTRL_TARG_OCP_FW_503000_LOGICAL_ADDR_ERRLOG_0
........
1714
5-72.
Register Call Summary for Register
L3_DSPSS_INIT_OCP_MMU0_CTRL_TARG_OCP_FW_503000_LOGICAL_ADDR_ERRLOG_0
........
1715
5-73.
L3_DSPSS_INIT_OCP_MMU0_CTRL_TARG_OCP_FW_503000_REGUPDATE_CONTROL .............. 1715
5-74.
Register Call Summary for Register
L3_DSPSS_INIT_OCP_MMU0_CTRL_TARG_OCP_FW_503000_REGUPDATE_CONTROL .............. 1715
5-75.
L3_DSPSS_INIT_OCP_MMU0_CTRL_TARG_OCP_FW_503000_MRM_PERMISSION_REGION_LOW_
0 ........................................................................................................................... 1715
5-76.
Register Call Summary for Register
L3_DSPSS_INIT_OCP_MMU0_CTRL_TARG_OCP_FW_503000_MRM_PERMISSION_REGION_LOW_
0 ........................................................................................................................... 1716
5-77.
L3_DSPSS_INIT_OCP_MMU0_CTRL_TARG_OCP_FW_503000_MRM_PERMISSION_REGION_HIGH
_0 .......................................................................................................................... 1716
5-78.
Register Call Summary for Register
L3_DSPSS_INIT_OCP_MMU0_CTRL_TARG_OCP_FW_503000_MRM_PERMISSION_REGION_HIGH
_0 .......................................................................................................................... 1717
5-79.
L3_DSPSS_INIT_OCP_MMU0_CTRL_TARG_OCP_FW_503000_START_REGION_1 ..................... 1717
5-80.
Register Call Summary for Register
L3_DSPSS_INIT_OCP_MMU0_CTRL_TARG_OCP_FW_503000_START_REGION_1 ..................... 1718
5-81.
L3_DSPSS_INIT_OCP_MMU0_CTRL_TARG_OCP_FW_503000_END_REGION_1
........................
1718
5-82.
Register Call Summary for Register
L3_DSPSS_INIT_OCP_MMU0_CTRL_TARG_OCP_FW_503000_END_REGION_1
........................
1718
5-83.
L3_DSPSS_INIT_OCP_MMU0_CTRL_TARG_OCP_FW_503000_MRM_PERMISSION_REGION_LOW_
1 ........................................................................................................................... 1718
5-84.
Register Call Summary for Register
L3_DSPSS_INIT_OCP_MMU0_CTRL_TARG_OCP_FW_503000_MRM_PERMISSION_REGION_LOW_
1 ........................................................................................................................... 1719
5-85.
L3_DSPSS_INIT_OCP_MMU0_CTRL_TARG_OCP_FW_503000_MRM_PERMISSION_REGION_HIGH
_1 .......................................................................................................................... 1719
List of Tables
SPRUIC2D – January 2017 – Revised April 2019
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Copyright © 2017–2019, Texas Instruments Incorporated
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5-86.
Register Call Summary for Register
L3_DSPSS_INIT_OCP_MMU0_CTRL_TARG_OCP_FW_503000_MRM_PERMISSION_REGION_HIGH
_1 .......................................................................................................................... 1720
5-87.
L3_DSPSS_INIT_OCP_MMU1_CTRL_TARG_OCP_FW_504000_ERROR_LOG_0 ......................... 1720
5-88.
Register Call Summary for Register
L3_DSPSS_INIT_OCP_MMU1_CTRL_TARG_OCP_FW_504000_ERROR_LOG_0 ......................... 1721
5-89.
L3_DSPSS_INIT_OCP_MMU1_CTRL_TARG_OCP_FW_504000_LOGICAL_ADDR_ERRLOG_0
........
1721
5-90.
Register Call Summary for Register
L3_DSPSS_INIT_OCP_MMU1_CTRL_TARG_OCP_FW_504000_LOGICAL_ADDR_ERRLOG_0
........
1721
5-91.
L3_DSPSS_INIT_OCP_MMU1_CTRL_TARG_OCP_FW_504000_REGUPDATE_CONTROL .............. 1721
5-92.
Register Call Summary for Register
L3_DSPSS_INIT_OCP_MMU1_CTRL_TARG_OCP_FW_504000_REGUPDATE_CONTROL .............. 1722
5-93.
L3_DSPSS_INIT_OCP_MMU1_CTRL_TARG_OCP_FW_504000_MRM_PERMISSION_REGION_LOW_
0 ........................................................................................................................... 1722
5-94.
Register Call Summary for Register
L3_DSPSS_INIT_OCP_MMU1_CTRL_TARG_OCP_FW_504000_MRM_PERMISSION_REGION_LOW_
0 ........................................................................................................................... 1722
5-95.
L3_DSPSS_INIT_OCP_MMU1_CTRL_TARG_OCP_FW_504000_MRM_PERMISSION_REGION_HIGH
_0 .......................................................................................................................... 1723
5-96.
Register Call Summary for Register
L3_DSPSS_INIT_OCP_MMU1_CTRL_TARG_OCP_FW_504000_MRM_PERMISSION_REGION_HIGH
_0 .......................................................................................................................... 1724
5-97.
DSPNOC_FLAGMUX_ID_COREID
5-98.
5-99.
5-100.
5-101.
5-102.
5-103.
5-104.
5-105.
5-106.
5-107.
5-108.
5-109.
5-110.
5-111.
5-112.
5-113.
5-114.
5-115.
5-116.
5-117.
5-118.
5-119.
5-120.
5-121.
5-122.
5-123.
5-124.
5-125.
5-126.
..................................................................................
Register Call Summary for Register DSPNOC_FLAGMUX_ID_COREID .......................................
DSPNOC_FLAGMUX_ID_REVISIONID .............................................................................
Register Call Summary for Register DSPNOC_FLAGMUX_ID_REVISIONID ..................................
DSPNOC_FLAGMUX_FAULTEN .....................................................................................
Register Call Summary for Register DSPNOC_FLAGMUX_FAULTEN .........................................
DSPNOC_FLAGMUX_FAULTSTATUS ..............................................................................
Register Call Summary for Register DSPNOC_FLAGMUX_FAULTSTATUS...................................
DSPNOC_FLAGMUX_FLAGINEN0 ..................................................................................
Register Call Summary for Register DSPNOC_FLAGMUX_FLAGINEN0 .......................................
DSPNOC_FLAGMUX_FLAGINSTATUS0 ...........................................................................
Register Call Summary for Register DSPNOC_FLAGMUX_FLAGINSTATUS0 ................................
DSPNOC_ERRORLOG_ID_COREID ................................................................................
Register Call Summary for Register DSPNOC_ERRORLOG_ID_COREID .....................................
DSPNOC_ERRORLOG_ID_REVISIONID ...........................................................................
Register Call Summary for Register DSPNOC_ERRORLOG_ID_REVISIONID................................
DSPNOC_ERRORLOG_FAULTEN ..................................................................................
Register Call Summary for Register DSPNOC_ERRORLOG_FAULTEN .......................................
DSPNOC_ERRORLOG_ERRVLD ....................................................................................
Register Call Summary for Register DSPNOC_ERRORLOG_ERRVLD ........................................
DSPNOC_ERRORLOG_ERRCLR ....................................................................................
Register Call Summary for Register DSPNOC_ERRORLOG_ERRCLR ........................................
DSPNOC_ERRORLOG_ERRLOG0 ..................................................................................
Register Call Summary for Register DSPNOC_ERRORLOG_ERRLOG0 ......................................
DSPNOC_ERRORLOG_ERRLOG1 ..................................................................................
Register Call Summary for Register DSPNOC_ERRORLOG_ERRLOG1 ......................................
DSPNOC_ERRORLOG_ERRLOG3 ..................................................................................
Register Call Summary for Register DSPNOC_ERRORLOG_ERRLOG3 ......................................
DSPNOC_ERRORLOG_ERRLOG5 ..................................................................................
Register Call Summary for Register DSPNOC_ERRORLOG_ERRLOG5 ......................................
SPRUIC2D – January 2017 – Revised April 2019
Submit Documentation Feedback
Copyright © 2017–2019, Texas Instruments Incorporated
List of Tables
1724
1724
1724
1724
1724
1725
1725
1725
1725
1726
1726
1726
1726
1727
1727
1727
1727
1727
1728
1728
1728
1728
1728
1729
1729
1729
1729
1730
1730
1730
137
www.ti.com
7-1.
IPUx Integration Attributes ............................................................................................. 1737
7-2.
IPUx Hardware Requests .............................................................................................. 1737
7-3.
IPUx Clocks and Resets................................................................................................ 1738
7-4.
Local Clock Gating ...................................................................................................... 1743
7-5.
IPUx Subsystem Power Modes
7-6.
Power Mode Transitions................................................................................................ 1744
7-7.
IPUx_UNICACHE Configuration
7-8.
IPUx_UNICACHE_MMU Configuration............................................................................... 1747
7-9.
IPUx_MMU Behavior on Page-Fault .................................................................................. 1751
7-10.
IPU1 Subsystem Instance Summary ................................................................................. 1754
7-11.
IPU2 Subsystem Instance Summary ................................................................................. 1754
7-12.
IPU1_UNICACHE_CFG Registers Mapping Summary ............................................................ 1754
7-13.
IPU2_UNICACHE_CFG Registers Mapping Summary ............................................................ 1755
7-14.
CACHE_CONFIG ....................................................................................................... 1755
7-15.
Register Call Summary for Register CACHE_CONFIG ............................................................ 1756
7-16.
CACHE_INT
7-17.
7-18.
7-19.
7-20.
7-21.
7-22.
7-23.
7-24.
7-25.
7-26.
7-27.
7-28.
7-29.
7-30.
7-31.
7-32.
7-33.
7-34.
7-35.
7-36.
7-37.
7-38.
7-39.
7-40.
7-41.
7-42.
7-43.
7-44.
7-45.
7-46.
7-47.
7-48.
7-49.
138
.......................................................................................
......................................................................................
.............................................................................................................
Register Call Summary for Register CACHE_INT ..................................................................
CACHE_OCP ............................................................................................................
Register Call Summary for Register CACHE_OCP.................................................................
CACHE_MAINT .........................................................................................................
Register Call Summary for Register CACHE_MAINT ..............................................................
CACHE_MTSTART .....................................................................................................
Register Call Summary for Register CACHE_MTSTART ..........................................................
CACHE_MTEND ........................................................................................................
Register Call Summary for Register CACHE_MTEND .............................................................
CACHE_CTADDR.......................................................................................................
Register Call Summary for Register CACHE_CTADDR ...........................................................
CACHE_CTDATA .......................................................................................................
Register Call Summary for Register CACHE_CTDATA............................................................
IPU1_UNICACHE_SCTM Registers Mapping Summary ..........................................................
IPU2_UNICACHE_SCTM Registers Mapping Summary ..........................................................
CACHE_SCTM_CTCNTL ..............................................................................................
Register Call Summary for Register CACHE_SCTM_CTCNTL...................................................
CACHE_SCTM_TINTVLR_i ...........................................................................................
Register Call Summary for Register CACHE_SCTM_TINTVLR_i ................................................
CACHE_SCTM_CTDBGNUM .........................................................................................
Register Call Summary for Register CACHE_SCTM_CTDBGNUM ..............................................
CACHE_SCTM_CTGNBL ..............................................................................................
Register Call Summary for Register CACHE_SCTM_CTGNBL ..................................................
CACHE_SCTM_CTGRST..............................................................................................
Register Call Summary for Register CACHE_SCTM_CTGRST ..................................................
CACHE_SCTM_CTCR_WT_i .........................................................................................
Register Call Summary for Register CACHE_SCTM_CTCR_WT_i ..............................................
CACHE_SCTM_CTCR_WOT_j .......................................................................................
Register Call Summary for Register CACHE_SCTM_CTCR_WOT_j ............................................
CACHE_SCTM_CTCNTR_k ...........................................................................................
Register Call Summary for Register CACHE_SCTM_CTCNTR_k ...............................................
IPU1_UNICACHE_MMU (AMMU) Registers Mapping Summary .................................................
IPU2_UNICACHE_MMU (AMMU) Registers Mapping Summary .................................................
List of Tables
1744
1746
1756
1756
1757
1757
1758
1758
1759
1759
1759
1759
1760
1760
1760
1760
1761
1761
1762
1762
1763
1763
1763
1763
1764
1764
1764
1764
1765
1766
1766
1767
1768
1768
1768
1769
SPRUIC2D – January 2017 – Revised April 2019
Submit Documentation Feedback
Copyright © 2017–2019, Texas Instruments Incorporated
www.ti.com
7-50.
7-51.
7-52.
7-53.
7-54.
7-55.
7-56.
7-57.
7-58.
7-59.
7-60.
7-61.
7-62.
7-63.
7-64.
7-65.
7-66.
7-67.
7-68.
7-69.
7-70.
7-71.
7-72.
7-73.
7-74.
7-75.
7-76.
7-77.
7-78.
7-79.
7-80.
7-81.
7-82.
7-83.
7-84.
7-85.
7-86.
7-87.
7-88.
7-89.
7-90.
7-91.
8-1.
8-2.
8-3.
8-4.
8-5.
8-6.
8-7.
.....................................................................................
Register Call Summary for Register CACHE_MMU_LARGE_ADDR_i ..........................................
CACHE_MMU_LARGE_XLTE_i ......................................................................................
Register Call Summary for Register CACHE_MMU_LARGE_XLTE_i ...........................................
CACHE_MMU_LARGE_POLICY_i ...................................................................................
Register Call Summary for Register CACHE_MMU_LARGE_POLICY_i ........................................
CACHE_MMU_MED_ADDR_j .........................................................................................
Register Call Summary for Register CACHE_MMU_MED_ADDR_j .............................................
CACHE_MMU_MED_XLTE_j..........................................................................................
Register Call Summary for Register CACHE_MMU_MED_XLTE_j ..............................................
CACHE_MMU_MED_POLICY_j ......................................................................................
Register Call Summary for Register CACHE_MMU_MED_POLICY_j ...........................................
CACHE_MMU_SMALL_ADDR_k .....................................................................................
Register Call Summary for Register CACHE_MMU_SMALL_ADDR_k..........................................
Reset Value for CACHE_MMU_SMALL_ADDR_k[31:12] ADDRESS ...........................................
CACHE_MMU_SMALL_XLTE_k ......................................................................................
Register Call Summary for Register CACHE_MMU_SMALL_XLTE_k ..........................................
Reset Value for CACHE_MMU_SMALL_XLTE_k[31:12] ADDRESS ............................................
CACHE_MMU_SMALL_POLICY_k ...................................................................................
Register Call Summary for Register CACHE_MMU_SMALL_POLICY_k .......................................
CACHE_MMU_SMALL_MAINT_k ....................................................................................
Register Call Summary for Register CACHE_MMU_SMALL_MAINT_k .........................................
CACHE_MMU_MMUCONFIG .........................................................................................
Register Call Summary for Register CACHE_MMU_MMUCONFIG .............................................
IPU1_WUGEN Registers Mapping Summary .......................................................................
IPU2_WUGEN Registers Mapping Summary .......................................................................
CORTEXM4_CTRL_REG ..............................................................................................
Register Call Summary for Register CORTEXM4_CTRL_REG ..................................................
STANDBY_CORE_SYSCONFIG .....................................................................................
Register Call Summary for Register STANDBY_CORE_SYSCONFIG ..........................................
IDLE_CORE_SYSCONFIG ............................................................................................
Register Call Summary for Register IDLE_CORE_SYSCONFIG .................................................
WUGEN_MEVT0 ........................................................................................................
Register Call Summary for Register WUGEN_MEVT0 ............................................................
WUGEN_MEVT1 ........................................................................................................
Register Call Summary for Register WUGEN_MEVT1 ............................................................
IPU1_Cx_RW_TABLE Register Summary ...........................................................................
IPU2_Cx_RW_TABLE Register Summary ...........................................................................
CORTEXM4_RW_PID1 ................................................................................................
Register Call Summary for Register CORTEXM4_RW_PID1 .....................................................
CORTEXM4_RW_PID2 ................................................................................................
Register Call Summary for Register CORTEXM4_RW_PID2 .....................................................
CAMSS I/O Description ................................................................................................
CAL Integration Attributes ..............................................................................................
CAMSS Clocks and Resets ............................................................................................
CAL Hardware Requests ...............................................................................................
CAL Video Port Signals ................................................................................................
CSI2 Low Level Protocol Interrupts ...................................................................................
CSI2 Complex I/O Interrupts ...........................................................................................
CACHE_MMU_LARGE_ADDR_i
SPRUIC2D – January 2017 – Revised April 2019
Submit Documentation Feedback
Copyright © 2017–2019, Texas Instruments Incorporated
List of Tables
1770
1770
1770
1770
1771
1771
1772
1772
1772
1772
1773
1773
1774
1774
1774
1774
1775
1775
1775
1776
1776
1776
1777
1777
1777
1778
1778
1778
1779
1779
1779
1780
1780
1781
1781
1782
1782
1782
1783
1783
1783
1783
1787
1790
1790
1790
1791
1793
1793
139
www.ti.com
8-8.
8-9.
8-10.
8-11.
8-12.
8-13.
8-14.
8-15.
8-16.
8-17.
8-18.
8-19.
8-20.
8-21.
8-22.
8-23.
8-24.
8-25.
8-26.
8-27.
8-28.
8-29.
8-30.
8-31.
8-32.
8-33.
8-34.
8-35.
8-36.
8-37.
8-38.
8-39.
8-40.
8-41.
8-42.
8-43.
8-44.
8-45.
8-46.
8-47.
8-48.
8-49.
8-50.
8-51.
8-52.
8-53.
8-54.
8-55.
8-56.
140
.............................................................................................
CAL Line Number Interrupt ............................................................................................
CAL Video Port EOF Interrupt .........................................................................................
CSI2 PHY Possible Time-Out Value for RxMode Counter ........................................................
CSI2_PHY1 I/O Description............................................................................................
CSI2_PHY2 I/O Description............................................................................................
CSI2 Long Packet Structure Description .............................................................................
CSI2 ECC Event Logging ..............................................................................................
CSI2 Synchronization Codes ..........................................................................................
CAL DPCM Formats ....................................................................................................
Write DMA - Line Start Address Computation .......................................................................
CAL Registers Shadowing .............................................................................................
CAMSS Instance Summary ............................................................................................
CAL Registers Mapping Summary ....................................................................................
CAL_HL_REVISION ....................................................................................................
Register Call Summary for Register CAL_HL_REVISION .........................................................
CAL_HL_HWINFO ......................................................................................................
Register Call Summary for Register CAL_HL_HWINFO ...........................................................
CAL_HL_SYSCONFIG .................................................................................................
Register Call Summary for Register CAL_HL_SYSCONFIG ......................................................
CAL_HL_IRQ_EOI ......................................................................................................
Register Call Summary for Register CAL_HL_IRQ_EOI ...........................................................
CAL_HL_IRQSTATUS_RAW_j ........................................................................................
Register Call Summary for Register CAL_HL_IRQSTATUS_RAW_j ............................................
CAL_HL_IRQSTATUS_j................................................................................................
Register Call Summary for Register CAL_HL_IRQSTATUS_j ....................................................
CAL_HL_IRQENABLE_SET_j .........................................................................................
Register Call Summary for Register CAL_HL_IRQENABLE_SET_j .............................................
CAL_HL_IRQENABLE_CLR_j .........................................................................................
Register Call Summary for Register CAL_HL_IRQENABLE_CLR_j .............................................
CAL_PIX_PROC_i ......................................................................................................
Register Call Summary for Register CAL_PIX_PROC_i ...........................................................
CAL_CTRL ...............................................................................................................
Register Call Summary for Register CAL_CTRL....................................................................
CAL_CTRL1 .............................................................................................................
Register Call Summary for Register CAL_CTRL1 ..................................................................
CAL_LINE_NUMBER_EVT ............................................................................................
Register Call Summary for Register CAL_LINE_NUMBER_EVT .................................................
CAL_VPORT_CTRL1 ...................................................................................................
Register Call Summary for Register CAL_VPORT_CTRL1 .......................................................
CAL_VPORT_CTRL2 ...................................................................................................
Register Call Summary for Register CAL_VPORT_CTRL2 .......................................................
CAL_BYS_CTRL1.......................................................................................................
Register Call Summary for Register CAL_BYS_CTRL1 ...........................................................
CAL_BYS_CTRL2.......................................................................................................
Register Call Summary for Register CAL_BYS_CTRL2 ...........................................................
CAL_RD_DMA_CTRL ..................................................................................................
Register Call Summary for Register CAL_RD_DMA_CTRL .......................................................
CAL_RD_DMA_PIX_ADDR ............................................................................................
CAL Write DMA Interrupts
List of Tables
1794
1794
1795
1798
1804
1804
1809
1810
1811
1819
1827
1831
1833
1833
1835
1835
1835
1836
1836
1837
1837
1838
1838
1841
1842
1845
1845
1849
1849
1853
1853
1855
1855
1856
1856
1857
1857
1858
1858
1858
1859
1859
1859
1860
1860
1861
1861
1862
1862
SPRUIC2D – January 2017 – Revised April 2019
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Copyright © 2017–2019, Texas Instruments Incorporated
www.ti.com
8-57.
Register Call Summary for Register CAL_RD_DMA_PIX_ADDR ................................................ 1862
8-58.
CAL_RD_DMA_PIX_OFST ............................................................................................ 1862
8-59.
Register Call Summary for Register CAL_RD_DMA_PIX_OFST ................................................. 1863
8-60.
CAL_RD_DMA_XSIZE
8-61.
8-62.
8-63.
8-64.
8-65.
8-66.
8-67.
8-68.
8-69.
8-70.
8-71.
8-72.
8-73.
8-74.
8-75.
8-76.
8-77.
8-78.
8-79.
8-80.
8-81.
8-82.
8-83.
8-84.
8-85.
8-86.
8-87.
8-88.
8-89.
8-90.
8-91.
8-92.
8-93.
8-94.
8-95.
8-96.
8-97.
8-98.
8-99.
8-100.
8-101.
8-102.
8-103.
8-104.
8-105.
.................................................................................................
Register Call Summary for Register CAL_RD_DMA_XSIZE ......................................................
CAL_RD_DMA_YSIZE .................................................................................................
Register Call Summary for Register CAL_RD_DMA_YSIZE ......................................................
CAL_RD_DMA_INIT_ADDR ...........................................................................................
Register Call Summary for Register CAL_RD_DMA_INIT_ADDR ...............................................
CAL_RD_DMA_INIT_OFST ...........................................................................................
Register Call Summary for Register CAL_RD_DMA_INIT_OFST ................................................
CAL_RD_DMA_CTRL2.................................................................................................
Register Call Summary for Register CAL_RD_DMA_CTRL2 .....................................................
CAL_WR_DMA_CTRL_k ...............................................................................................
Register Call Summary for Register CAL_WR_DMA_CTRL_k ...................................................
CAL_WR_DMA_ADDR_k ..............................................................................................
Register Call Summary for Register CAL_WR_DMA_ADDR_k...................................................
CAL_WR_DMA_OFST_k ..............................................................................................
Register Call Summary for Register CAL_WR_DMA_OFST_k ...................................................
CAL_WR_DMA_XSIZE_k ..............................................................................................
Register Call Summary for Register CAL_WR_DMA_XSIZE_k ..................................................
CAL_CSI2_PPI_CTRL_l................................................................................................
Register Call Summary for Register CAL_CSI2_PPI_CTRL_l ....................................................
CAL_CSI2_COMPLEXIO_CFG_l .....................................................................................
Register Call Summary for Register CAL_CSI2_COMPLEXIO_CFG_l ..........................................
CAL_CSI2_COMPLEXIO_IRQSTATUS_l ...........................................................................
Register Call Summary for Register CAL_CSI2_COMPLEXIO_IRQSTATUS_l ................................
CAL_CSI2_SHORT_PACKET_l .......................................................................................
Register Call Summary for Register CAL_CSI2_SHORT_PACKET_l ...........................................
CAL_CSI2_COMPLEXIO_IRQENABLE_l ...........................................................................
Register Call Summary for Register CAL_CSI2_COMPLEXIO_IRQENABLE_l ................................
CAL_CSI2_TIMING_l ...................................................................................................
Register Call Summary for Register CAL_CSI2_TIMING_l........................................................
CAL_CSI2_VC_IRQENABLE_l ........................................................................................
Register Call Summary for Register CAL_CSI2_VC_IRQENABLE_l ............................................
CAL_CSI2_VC_IRQSTATUS_l ........................................................................................
Register Call Summary for Register CAL_CSI2_VC_IRQSTATUS_l ............................................
CAL_CSI2_CTX0_l......................................................................................................
Register Call Summary for Register CAL_CSI2_CTX0_l ..........................................................
CAL_CSI2_CTX1_l......................................................................................................
Register Call Summary for Register CAL_CSI2_CTX1_l ..........................................................
CAL_CSI2_CTX2_l......................................................................................................
Register Call Summary for Register CAL_CSI2_CTX2_l ..........................................................
CAL_CSI2_CTX3_l......................................................................................................
Register Call Summary for Register CAL_CSI2_CTX3_l ..........................................................
CAL_CSI2_CTX4_l......................................................................................................
Register Call Summary for Register CAL_CSI2_CTX4_l ..........................................................
CAL_CSI2_CTX5_l......................................................................................................
Register Call Summary for Register CAL_CSI2_CTX5_l ..........................................................
SPRUIC2D – January 2017 – Revised April 2019
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Copyright © 2017–2019, Texas Instruments Incorporated
List of Tables
1863
1863
1863
1864
1864
1864
1864
1865
1865
1866
1866
1867
1867
1868
1868
1869
1869
1869
1869
1870
1870
1872
1872
1876
1876
1876
1876
1879
1879
1880
1880
1882
1882
1885
1885
1886
1886
1886
1887
1887
1887
1888
1888
1889
1889
1890
141
www.ti.com
8-106. CAL_CSI2_CTX6_l...................................................................................................... 1890
8-107. Register Call Summary for Register CAL_CSI2_CTX6_l .......................................................... 1891
8-108. CAL_CSI2_CTX7_l...................................................................................................... 1891
8-109. Register Call Summary for Register CAL_CSI2_CTX7_l .......................................................... 1892
8-110. CAL_CSI2_STATUS0_l ................................................................................................ 1892
8-111. Register Call Summary for Register CAL_CSI2_STATUS0_l ..................................................... 1892
8-112. CAL_CSI2_STATUS1_l ................................................................................................ 1892
8-113. Register Call Summary for Register CAL_CSI2_STATUS1_l ..................................................... 1893
8-114. CAL_CSI2_STATUS2_l ................................................................................................ 1893
8-115. Register Call Summary for Register CAL_CSI2_STATUS2_l ..................................................... 1893
8-116. CAL_CSI2_STATUS3_l ................................................................................................ 1893
8-117. Register Call Summary for Register CAL_CSI2_STATUS3_l ..................................................... 1893
8-118. CAL_CSI2_STATUS4_l ................................................................................................ 1894
8-119. Register Call Summary for Register CAL_CSI2_STATUS4_l ..................................................... 1894
8-120. CAL_CSI2_STATUS5_l ................................................................................................ 1894
8-121. Register Call Summary for Register CAL_CSI2_STATUS5_l ..................................................... 1894
8-122. CAL_CSI2_STATUS6_l ................................................................................................ 1894
8-123. Register Call Summary for Register CAL_CSI2_STATUS6_l ..................................................... 1895
8-124. CAL_CSI2_STATUS7_l ................................................................................................ 1895
8-125. Register Call Summary for Register CAL_CSI2_STATUS7_l ..................................................... 1895
8-126. CSI2 PHY Registers Mapping Summary ............................................................................. 1896
8-127. REG0
.....................................................................................................................
1896
8-128. Register Call Summary for Register REG0 .......................................................................... 1897
1897
8-130.
1898
8-131.
8-132.
9-1.
9-2.
9-3.
9-4.
9-5.
9-6.
9-7.
9-8.
9-9.
9-10.
9-11.
9-12.
9-13.
9-14.
9-15.
9-16.
9-17.
9-18.
9-19.
9-20.
9-21.
9-22.
142
.....................................................................................................................
Register Call Summary for Register REG1 ..........................................................................
REG2 .....................................................................................................................
Register Call Summary for Register REG2 ..........................................................................
VIP1 Interface Signals ..................................................................................................
VIP1 Input Data Signals to RGB and YUV Color Components Mapping ........................................
VIP Integration Attributes ...............................................................................................
VIP Clocks and Resets .................................................................................................
VIP Hardware Requests ................................................................................................
VIP Slice Processing Path Control ....................................................................................
Polarity Table for FID Determination By VSYNC Skew ............................................................
Fourth Byte of EAV/SAV Code Word .................................................................................
Error Correction Matrix .................................................................................................
Multiplexing Configurations and Pixel Clock Rates .................................................................
Split Line Table ..........................................................................................................
Meta Data Layout .......................................................................................................
TI Line Mux Mode Channel ID Remapping ..........................................................................
Channel ID Embedded in EAV/SAV ..................................................................................
Valid Embedded Sync Mux Mode and Data Bus Width Combinations ..........................................
VIP_PARSER Interrupt Events ........................................................................................
Quantized Coefficients of HDTV Application with Video Data Range ............................................
Quantized Coefficients of HDTV Application with Graphics Data Range ........................................
Quantized Coefficients of SDTV Application with Video Data Range ............................................
Quantized Coefficients of SDTV Application with Graphics Data Range ........................................
Parameter Description ..................................................................................................
Vertical Scaler Configuration Parameters ............................................................................
8-129. REG1
List of Tables
1898
1899
1903
1905
1906
1907
1907
1910
1934
1938
1939
1941
1944
1944
1945
1946
1947
1951
1963
1963
1965
1966
1969
1970
SPRUIC2D – January 2017 – Revised April 2019
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Copyright © 2017–2019, Texas Instruments Incorporated
www.ti.com
9-23.
Register Group 1 ........................................................................................................ 1974
9-24.
Register Group 2 ........................................................................................................ 1974
9-25.
Register Group 3 ........................................................................................................ 1975
9-26.
Scaler Configuration .................................................................................................... 1975
9-27.
Vertical Scaler Configuration
9-28.
Coefficient Data Files ................................................................................................... 1978
9-29.
VPDMA Client Buffering and Functionality ........................................................................... 2001
9-30.
VPDMA Channels Assignment ........................................................................................ 2003
9-31.
VPDMA Interrupt Events ............................................................................................... 2008
9-32.
VIP Interrupt Sources ................................................................................................... 2010
9-33.
Data Packet Descriptor Word 0 Field Descriptions ................................................................. 2025
9-34.
Common ARGB in Memory (Byte Order) ............................................................................ 2026
9-35.
Common ARGB in 32-bit Memory/CPU Register ................................................................... 2026
9-36.
VPDMA ARGB in Memory (Byte Order).............................................................................. 2027
9-37.
VPDMA ARGB in 32-bit Memory/CPU Register
9-38.
VPDMA Descriptor RGB Data Type Mapping ....................................................................... 2027
9-39.
VPDMA Descriptor YUV Data Type Mapping ....................................................................... 2028
9-40.
Data Packet Descriptor Word 1 Field Description
9-41.
Data Packet Descriptor Word 2 Field Descriptions ................................................................. 2029
9-42.
Data Packet Descriptor Word 3 Field Descriptions ................................................................. 2030
9-43.
Data Packet Descriptor Word 4 Inbound Data Field Descriptions ................................................ 2031
9-44.
Data Packet Descriptor Word 4 Outbound Data Field Descriptions .............................................. 2031
9-45.
Data Packet Descriptor Word 5 Outbound Data Field Descriptions .............................................. 2032
9-46.
Configuration Descriptor Header Word0 Field Descriptions ....................................................... 2033
9-47.
Configuration Descriptor Header Word1 Field Descriptions ....................................................... 2033
9-48.
Configuration Descriptor Header Word2 Field Descriptions ....................................................... 2034
9-49.
Configuration Descriptor Header Word3 Field Descriptions ....................................................... 2034
9-50.
Address Data Block Format Field Descriptions ..................................................................... 2035
9-51.
Destination Field Description
9-52.
9-53.
9-54.
9-55.
9-56.
9-57.
9-58.
9-59.
9-60.
9-61.
9-62.
9-63.
9-64.
9-65.
9-66.
9-67.
9-68.
9-69.
9-70.
9-71.
..........................................................................................
....................................................................
..................................................................
..........................................................................................
Control Descriptor Header Description ...............................................................................
Control Descriptor Types Summary ..................................................................................
Sync on Client Field Descriptions (Word - 1) ........................................................................
Sync on Client Field Descriptions (Word - 3) ........................................................................
Sync on List Field Descriptions (Word - 3)...........................................................................
Sync on External Event Field Descriptions (Word - 3) .............................................................
Sync on Channel Field Descriptions (Word - 3) .....................................................................
Change Client Interrupt Field Descriptions (Word - 1) .............................................................
Change Client Interrupt Field Descriptions (Word - 2) .............................................................
Change Client Interrupt Field Descriptions (Word - 3) .............................................................
Send Interrupt Field Descriptions (Word - 3) ........................................................................
Reload List Field Descriptions (Word - 0) ............................................................................
Reload List Field Descriptions (Word - 1) ............................................................................
Reload List Field Descriptions (Word - 3) ............................................................................
Abort Channel Field Descriptions (Word - 3) ........................................................................
VIP Instance Summary .................................................................................................
VIP Top Level Registers Mapping Summary ........................................................................
VIP_CLKC_PID ..........................................................................................................
Register Call Summary for Register VIP_CLKC_PID ..............................................................
VIP_SYSCONFIG .......................................................................................................
SPRUIC2D – January 2017 – Revised April 2019
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Copyright © 2017–2019, Texas Instruments Incorporated
List of Tables
1975
2027
2029
2035
2036
2036
2037
2037
2037
2038
2038
2038
2038
2038
2039
2039
2039
2039
2040
2052
2052
2053
2053
2053
143
www.ti.com
9-72.
Register Call Summary for Register VIP_SYSCONFIG............................................................ 2054
9-73.
VIP_INTC_INTR0_STATUS_RAW0 .................................................................................. 2054
9-74.
Register Call Summary for Register VIP_INTC_INTR0_STATUS_RAW0
9-75.
VIP_INTC_INTR0_STATUS_RAW1 .................................................................................. 2056
9-76.
Register Call Summary for Register VIP_INTC_INTR0_STATUS_RAW1
9-77.
VIP_INTC_INTR0_STATUS_ENA0 ................................................................................... 2057
9-78.
Register Call Summary for Register VIP_INTC_INTR0_STATUS_ENA0 ....................................... 2059
9-79.
VIP_INTC_INTR0_STATUS_ENA1 ................................................................................... 2059
9-80.
Register Call Summary for Register VIP_INTC_INTR0_STATUS_ENA1 ....................................... 2060
9-81.
VIP_INTC_INTR0_ENA_SET0 ........................................................................................ 2060
9-82.
Register Call Summary for Register VIP_INTC_INTR0_ENA_SET0............................................. 2062
9-83.
VIP_INTC_INTR0_ENA_SET1 ........................................................................................ 2062
9-84.
Register Call Summary for Register VIP_INTC_INTR0_ENA_SET1............................................. 2063
9-85.
VIP_INTC_INTR0_ENA_CLR0 ........................................................................................ 2063
9-86.
Register Call Summary for Register VIP_INTC_INTR0_ENA_CLR0
9-87.
VIP_INTC_INTR0_ENA_CLR1 ........................................................................................ 2065
9-88.
Register Call Summary for Register VIP_INTC_INTR0_ENA_CLR1
9-89.
VIP_INTC_INTR1_STATUS_RAW0 .................................................................................. 2066
9-90.
Register Call Summary for Register VIP_INTC_INTR1_STATUS_RAW0
9-91.
9-92.
9-93.
9-94.
9-95.
9-96.
9-97.
9-98.
9-99.
9-100.
9-101.
9-102.
9-103.
9-104.
9-105.
9-106.
9-107.
9-108.
9-109.
9-110.
9-111.
9-112.
9-113.
9-114.
9-115.
9-116.
9-117.
9-118.
9-119.
9-120.
144
......................................
......................................
............................................
............................................
......................................
VIP_INTC_INTR1_STATUS_RAW1 ..................................................................................
Register Call Summary for Register VIP_INTC_INTR1_STATUS_RAW1 ......................................
VIP_INTC_INTR1_STATUS_ENA0 ...................................................................................
Register Call Summary for Register VIP_INTC_INTR1_STATUS_ENA0 .......................................
VIP_INTC_INTR1_STATUS_ENA1 ...................................................................................
Register Call Summary for Register VIP_INTC_INTR1_STATUS_ENA1 .......................................
VIP_INTC_INTR1_ENA_SET0 ........................................................................................
Register Call Summary for Register VIP_INTC_INTR1_ENA_SET0.............................................
VIP_INTC_INTR1_ENA_SET1 ........................................................................................
Register Call Summary for Register VIP_INTC_INTR1_ENA_SET1.............................................
VIP_INTC_INTR1_ENA_CLR0 ........................................................................................
Register Call Summary for Register VIP_INTC_INTR1_ENA_CLR0 ............................................
VIP_INTC_INTR1_ENA_CLR1 ........................................................................................
Register Call Summary for Register VIP_INTC_INTR1_ENA_CLR1 ............................................
VIP_INTC_EOI ..........................................................................................................
Register Call Summary for Register VIP_INTC_EOI ...............................................................
VIP_CLKC_CLKEN .....................................................................................................
Register Call Summary for Register VIP_CLKC_CLKEN ..........................................................
VIP_CLKC_RST .........................................................................................................
Register Call Summary for Register VIP_CLKC_RST .............................................................
VIP_CLKC_DPS .........................................................................................................
Register Call Summary for Register VIP_CLKC_DPS .............................................................
VIP_CLKC_VIP0DPS ...................................................................................................
Register Call Summary for Register VIP_CLKC_VIP0DPS .......................................................
VIP_CLKC_VIP1DPS ...................................................................................................
Register Call Summary for Register VIP_CLKC_VIP1DPS .......................................................
VIP Parser Registers Mapping Summary ............................................................................
VIP_MAIN ................................................................................................................
Register Call Summary for Register VIP_MAIN .....................................................................
VIP_PORT_A ............................................................................................................
List of Tables
2056
2057
2065
2066
2068
2068
2069
2069
2071
2071
2072
2072
2074
2074
2075
2075
2077
2077
2078
2078
2079
2079
2079
2079
2080
2080
2081
2081
2082
2083
2084
2084
2087
2087
2087
SPRUIC2D – January 2017 – Revised April 2019
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Copyright © 2017–2019, Texas Instruments Incorporated
www.ti.com
9-121. Register Call Summary for Register VIP_PORT_A ................................................................. 2089
9-122. VIP_XTRA_PORT_A
...................................................................................................
2089
9-123. Register Call Summary for Register VIP_XTRA_PORT_A ........................................................ 2090
9-124. VIP_PORT_B ............................................................................................................ 2090
9-125. Register Call Summary for Register VIP_PORT_B ................................................................. 2092
...................................................................................................
Register Call Summary for Register VIP_XTRA_PORT_B ........................................................
VIP_FIQ_MASK .........................................................................................................
Register Call Summary for Register VIP_FIQ_MASK ..............................................................
VIP_FIQ_CLEAR ........................................................................................................
Register Call Summary for Register VIP_FIQ_CLEAR ............................................................
VIP_FIQ_STATUS ......................................................................................................
Register Call Summary for Register VIP_FIQ_STATUS ...........................................................
VIP_OUTPUT_PORT_A_SRC_FID ..................................................................................
Register Call Summary for Register VIP_OUTPUT_PORT_A_SRC_FID .......................................
VIP_OUTPUT_PORT_A_ENC_FID ..................................................................................
Register Call Summary for Register VIP_OUTPUT_PORT_A_ENC_FID .......................................
VIP_OUTPUT_PORT_B_SRC_FID ..................................................................................
Register Call Summary for Register VIP_OUTPUT_PORT_B_SRC_FID .......................................
VIP_OUTPUT_PORT_B_ENC_FID ..................................................................................
Register Call Summary for Register VIP_OUTPUT_PORT_B_ENC_FID .......................................
VIP_OUTPUT_PORT_A_SRC0_SIZE ...............................................................................
Register Call Summary for Register VIP_OUTPUT_PORT_A_SRC0_SIZE ....................................
VIP_OUTPUT_PORT_A_SRC1_SIZE ...............................................................................
Register Call Summary for Register VIP_OUTPUT_PORT_A_SRC1_SIZE ....................................
VIP_OUTPUT_PORT_A_SRC2_SIZE ...............................................................................
Register Call Summary for Register VIP_OUTPUT_PORT_A_SRC2_SIZE ....................................
VIP_OUTPUT_PORT_A_SRC3_SIZE ...............................................................................
Register Call Summary for Register VIP_OUTPUT_PORT_A_SRC3_SIZE ....................................
VIP_OUTPUT_PORT_A_SRC4_SIZE ...............................................................................
Register Call Summary for Register VIP_OUTPUT_PORT_A_SRC4_SIZE ....................................
VIP_OUTPUT_PORT_A_SRC5_SIZE ...............................................................................
Register Call Summary for Register VIP_OUTPUT_PORT_A_SRC5_SIZE ....................................
VIP_OUTPUT_PORT_A_SRC6_SIZE ...............................................................................
Register Call Summary for Register VIP_OUTPUT_PORT_A_SRC6_SIZE ....................................
VIP_OUTPUT_PORT_A_SRC7_SIZE ...............................................................................
Register Call Summary for Register VIP_OUTPUT_PORT_A_SRC7_SIZE ....................................
VIP_OUTPUT_PORT_A_SRC8_SIZE ...............................................................................
Register Call Summary for Register VIP_OUTPUT_PORT_A_SRC8_SIZE ....................................
VIP_OUTPUT_PORT_A_SRC9_SIZE ...............................................................................
Register Call Summary for Register VIP_OUTPUT_PORT_A_SRC9_SIZE ....................................
VIP_OUTPUT_PORT_A_SRC10_SIZE ..............................................................................
Register Call Summary for Register VIP_OUTPUT_PORT_A_SRC10_SIZE ..................................
VIP_OUTPUT_PORT_A_SRC11_SIZE ..............................................................................
Register Call Summary for Register VIP_OUTPUT_PORT_A_SRC11_SIZE ..................................
VIP_OUTPUT_PORT_A_SRC12_SIZE ..............................................................................
Register Call Summary for Register VIP_OUTPUT_PORT_A_SRC12_SIZE ..................................
VIP_OUTPUT_PORT_A_SRC13_SIZE ..............................................................................
Register Call Summary for Register VIP_OUTPUT_PORT_A_SRC13_SIZE ..................................
9-126. VIP_XTRA_PORT_B
9-127.
9-128.
9-129.
9-130.
9-131.
9-132.
9-133.
9-134.
9-135.
9-136.
9-137.
9-138.
9-139.
9-140.
9-141.
9-142.
9-143.
9-144.
9-145.
9-146.
9-147.
9-148.
9-149.
9-150.
9-151.
9-152.
9-153.
9-154.
9-155.
9-156.
9-157.
9-158.
9-159.
9-160.
9-161.
9-162.
9-163.
9-164.
9-165.
9-166.
9-167.
9-168.
9-169.
SPRUIC2D – January 2017 – Revised April 2019
Submit Documentation Feedback
Copyright © 2017–2019, Texas Instruments Incorporated
List of Tables
2092
2093
2093
2094
2094
2096
2096
2097
2097
2098
2099
2100
2100
2102
2102
2103
2103
2104
2104
2104
2104
2105
2105
2105
2105
2106
2106
2106
2106
2106
2107
2107
2107
2107
2107
2108
2108
2108
2108
2109
2109
2109
2109
2109
145
www.ti.com
9-170. VIP_OUTPUT_PORT_A_SRC14_SIZE .............................................................................. 2110
9-171. Register Call Summary for Register VIP_OUTPUT_PORT_A_SRC14_SIZE
..................................
2110
9-172. VIP_OUTPUT_PORT_A_SRC15_SIZE .............................................................................. 2110
..................................
VIP_OUTPUT_PORT_B_SRC0_SIZE ...............................................................................
Register Call Summary for Register VIP_OUTPUT_PORT_B_SRC0_SIZE ....................................
VIP_OUTPUT_PORT_B_SRC1_SIZE ...............................................................................
Register Call Summary for Register VIP_OUTPUT_PORT_B_SRC1_SIZE ....................................
VIP_OUTPUT_PORT_B_SRC2_SIZE ...............................................................................
Register Call Summary for Register VIP_OUTPUT_PORT_B_SRC2_SIZE ....................................
VIP_OUTPUT_PORT_B_SRC3_SIZE ...............................................................................
Register Call Summary for Register VIP_OUTPUT_PORT_B_SRC3_SIZE ....................................
VIP_OUTPUT_PORT_B_SRC4_SIZE ...............................................................................
Register Call Summary for Register VIP_OUTPUT_PORT_B_SRC4_SIZE ....................................
VIP_OUTPUT_PORT_B_SRC5_SIZE ...............................................................................
Register Call Summary for Register VIP_OUTPUT_PORT_B_SRC5_SIZE ....................................
VIP_OUTPUT_PORT_B_SRC6_SIZE ...............................................................................
Register Call Summary for Register VIP_OUTPUT_PORT_B_SRC6_SIZE ....................................
VIP_OUTPUT_PORT_B_SRC7_SIZE ...............................................................................
Register Call Summary for Register VIP_OUTPUT_PORT_B_SRC7_SIZE ....................................
VIP_OUTPUT_PORT_B_SRC8_SIZE ...............................................................................
Register Call Summary for Register VIP_OUTPUT_PORT_B_SRC8_SIZE ....................................
VIP_OUTPUT_PORT_B_SRC9_SIZE ...............................................................................
Register Call Summary for Register VIP_OUTPUT_PORT_B_SRC9_SIZE ....................................
VIP_OUTPUT_PORT_B_SRC10_SIZE ..............................................................................
Register Call Summary for Register VIP_OUTPUT_PORT_B_SRC10_SIZE ..................................
VIP_OUTPUT_PORT_B_SRC11_SIZE ..............................................................................
Register Call Summary for Register VIP_OUTPUT_PORT_B_SRC11_SIZE ..................................
VIP_OUTPUT_PORT_B_SRC12_SIZE ..............................................................................
Register Call Summary for Register VIP_OUTPUT_PORT_B_SRC12_SIZE ..................................
VIP_OUTPUT_PORT_B_SRC13_SIZE ..............................................................................
Register Call Summary for Register VIP_OUTPUT_PORT_B_SRC13_SIZE ..................................
VIP_OUTPUT_PORT_B_SRC14_SIZE ..............................................................................
Register Call Summary for Register VIP_OUTPUT_PORT_B_SRC14_SIZE ..................................
VIP_OUTPUT_PORT_B_SRC15_SIZE ..............................................................................
Register Call Summary for Register VIP_OUTPUT_PORT_B_SRC15_SIZE ..................................
VIP_PORT_A_VDET_VEC ............................................................................................
Register Call Summary for Register VIP_PORT_A_VDET_VEC .................................................
VIP_PORT_B_VDET_VEC ............................................................................................
Register Call Summary for Register VIP_PORT_B_VDET_VEC .................................................
VIP_ANC_CROP_HORZ_PORT_A ..................................................................................
Register Call Summary for Register VIP_ANC_CROP_HORZ_PORT_A .......................................
VIP_ANC_CROP_VERT_PORT_A ...................................................................................
Register Call Summary for Register VIP_ANC_CROP_VERT_PORT_A .......................................
VIP_CROP_HORZ_PORT_A ..........................................................................................
Register Call Summary for Register VIP_CROP_HORZ_PORT_A ..............................................
VIP_CROP_VERT_PORT_A ..........................................................................................
Register Call Summary for Register VIP_CROP_VERT_PORT_A ...............................................
VIP_ANC_VIP_CROP_HORZ_PORT_B .............................................................................
9-173. Register Call Summary for Register VIP_OUTPUT_PORT_A_SRC15_SIZE
9-174.
9-175.
9-176.
9-177.
9-178.
9-179.
9-180.
9-181.
9-182.
9-183.
9-184.
9-185.
9-186.
9-187.
9-188.
9-189.
9-190.
9-191.
9-192.
9-193.
9-194.
9-195.
9-196.
9-197.
9-198.
9-199.
9-200.
9-201.
9-202.
9-203.
9-204.
9-205.
9-206.
9-207.
9-208.
9-209.
9-210.
9-211.
9-212.
9-213.
9-214.
9-215.
9-216.
9-217.
9-218.
146
List of Tables
2110
2110
2111
2111
2111
2111
2112
2112
2112
2112
2113
2113
2113
2113
2113
2114
2114
2114
2114
2114
2115
2115
2115
2115
2116
2116
2116
2116
2116
2117
2117
2117
2117
2117
2118
2118
2118
2118
2119
2119
2120
2120
2120
2120
2121
2121
SPRUIC2D – January 2017 – Revised April 2019
Submit Documentation Feedback
Copyright © 2017–2019, Texas Instruments Incorporated
www.ti.com
9-219. Register Call Summary for Register VIP_ANC_VIP_CROP_HORZ_PORT_B ................................. 2121
9-220. VIP_ANC_VIP_CROP_VERT_PORT_B ............................................................................. 2122
9-221. Register Call Summary for Register VIP_ANC_VIP_CROP_VERT_PORT_B .................................. 2122
9-222. VIP_CROP_HORZ_PORT_B .......................................................................................... 2122
9-223. Register Call Summary for Register VIP_CROP_HORZ_PORT_B .............................................. 2123
9-224. VIP_CROP_VERT_PORT_B .......................................................................................... 2123
9-225. Register Call Summary for Register VIP_CROP_VERT_PORT_B ............................................... 2123
9-226. VIP_XTRA6_PORT_A .................................................................................................. 2123
......................................................
VIP_XTRA7_PORT_B ..................................................................................................
Register Call Summary for Register VIP_XTRA7_PORT_B ......................................................
VIP_XTRA8_PORT_A ..................................................................................................
Register Call Summary for Register VIP_XTRA8_PORT_A ......................................................
VIP_XTRA9_PORT_B ..................................................................................................
Register Call Summary for Register VIP_XTRA9_PORT_B ......................................................
VIP CSC Registers Mapping Summary 1 ............................................................................
VIP_CSC00 ..............................................................................................................
Register Call Summary for Register VIP_CSC00 ...................................................................
VIP_CSC01 ..............................................................................................................
Register Call Summary for Register VIP_CSC01 ...................................................................
VIP_CSC02 ..............................................................................................................
Register Call Summary for Register VIP_CSC02 ...................................................................
VIP_CSC03 ..............................................................................................................
Register Call Summary for Register VIP_CSC03 ...................................................................
VIP_CSC04 ..............................................................................................................
Register Call Summary for Register VIP_CSC04 ...................................................................
VIP_CSC05 ..............................................................................................................
Register Call Summary for Register VIP_CSC05 ...................................................................
VIP SC Registers Mapping Summary 1 .............................................................................
VIP_CFG_SC0 ..........................................................................................................
Register Call Summary for Register VIP_CFG_SC0 ...............................................................
VIP_CFG_SC1 ..........................................................................................................
Register Call Summary for Register VIP_CFG_SC1 ...............................................................
VIP_CFG_SC2 ..........................................................................................................
Register Call Summary for Register VIP_CFG_SC2 ...............................................................
VIP_CFG_SC3 ..........................................................................................................
Register Call Summary for Register VIP_CFG_SC3 ...............................................................
VIP_CFG_SC4 ..........................................................................................................
Register Call Summary for Register VIP_CFG_SC4 ...............................................................
VIP_CFG_SC5 ..........................................................................................................
Register Call Summary for Register VIP_CFG_SC5 ...............................................................
VIP_CFG_SC6 ..........................................................................................................
Register Call Summary for Register VIP_CFG_SC6 ...............................................................
VIP_CFG_SC8 ..........................................................................................................
Register Call Summary for Register VIP_CFG_SC8 ...............................................................
VIP_CFG_SC9 ..........................................................................................................
Register Call Summary for Register VIP_CFG_SC9 ...............................................................
VIP_CFG_SC10 .........................................................................................................
Register Call Summary for Register VIP_CFG_SC10..............................................................
9-227. Register Call Summary for Register VIP_XTRA6_PORT_A
9-228.
9-229.
9-230.
9-231.
9-232.
9-233.
9-234.
9-235.
9-236.
9-237.
9-238.
9-239.
9-240.
9-241.
9-242.
9-243.
9-244.
9-245.
9-246.
9-247.
9-248.
9-249.
9-250.
9-251.
9-252.
9-253.
9-254.
9-255.
9-256.
9-257.
9-258.
9-259.
9-260.
9-261.
9-262.
9-263.
9-264.
9-265.
9-266.
9-267.
SPRUIC2D – January 2017 – Revised April 2019
Submit Documentation Feedback
Copyright © 2017–2019, Texas Instruments Incorporated
List of Tables
2124
2124
2125
2125
2125
2125
2126
2126
2126
2127
2127
2127
2127
2128
2128
2128
2128
2129
2129
2130
2130
2131
2132
2132
2133
2133
2133
2133
2134
2134
2134
2134
2135
2135
2136
2136
2136
2136
2137
2137
2137
147
www.ti.com
9-268. VIP_CFG_SC11 ......................................................................................................... 2137
9-269. Register Call Summary for Register VIP_CFG_SC11.............................................................. 2138
9-270. VIP_CFG_SC12 ......................................................................................................... 2138
9-271. Register Call Summary for Register VIP_CFG_SC12.............................................................. 2138
9-272. VIP_CFG_SC13 ......................................................................................................... 2138
9-273. Register Call Summary for Register VIP_CFG_SC13.............................................................. 2139
9-274. VIP_CFG_SC18 ......................................................................................................... 2139
9-275. Register Call Summary for Register VIP_CFG_SC18.............................................................. 2139
9-276. VIP_CFG_SC19 ......................................................................................................... 2139
9-277. Register Call Summary for Register VIP_CFG_SC19.............................................................. 2140
9-278. VIP_CFG_SC20 ......................................................................................................... 2140
9-279. Register Call Summary for Register VIP_CFG_SC20.............................................................. 2141
9-280. VIP_CFG_SC21 ......................................................................................................... 2141
9-281. Register Call Summary for Register VIP_CFG_SC21.............................................................. 2141
9-282. VIP_CFG_SC22 ......................................................................................................... 2141
9-283. Register Call Summary for Register VIP_CFG_SC22.............................................................. 2142
9-284. VIP_CFG_SC24 ......................................................................................................... 2142
9-285. Register Call Summary for Register VIP_CFG_SC24.............................................................. 2142
9-286. VIP_CFG_SC25 ......................................................................................................... 2142
9-287. Register Call Summary for Register VIP_CFG_SC25.............................................................. 2143
9-288. VIP VPDMA Registers Mapping Summary .......................................................................... 2145
9-289. VIP_PID
..................................................................................................................
2149
9-290. Register Call Summary for Register VIP_PID ....................................................................... 2149
9-291. VIP_LIST_ADDR ........................................................................................................ 2149
9-292. Register Call Summary for Register VIP_LIST_ADDR ............................................................. 2150
9-293. VIP_LIST_ATTR ......................................................................................................... 2150
9-294. Register Call Summary for Register VIP_LIST_ATTR ............................................................. 2151
9-295. VIP_LIST_STAT_SYNC ................................................................................................ 2151
2152
9-297.
2152
9-298.
9-299.
9-300.
9-301.
9-302.
9-303.
9-304.
9-305.
9-306.
9-307.
9-308.
9-309.
9-310.
9-311.
9-312.
9-313.
9-314.
9-315.
9-316.
148
....................................................
VIP_BG_RGB ............................................................................................................
Register Call Summary for Register VIP_BG_RGB ................................................................
VIP_BG_YUV ............................................................................................................
Register Call Summary for Register VIP_BG_YUV.................................................................
VIP_VPDMA_SETUP ...................................................................................................
Register Call Summary for Register VIP_VPDMA_SETUP .......................................................
VIP_MAX_SIZE1 ........................................................................................................
Register Call Summary for Register VIP_MAX_SIZE1 .............................................................
VIP_MAX_SIZE2 ........................................................................................................
Register Call Summary for Register VIP_MAX_SIZE2 .............................................................
VIP_MAX_SIZE3 ........................................................................................................
Register Call Summary for Register VIP_MAX_SIZE3 .............................................................
VIP_INT0_CHANNEL0_INT_STAT ...................................................................................
Register Call Summary for Register VIP_INT0_CHANNEL0_INT_STAT .......................................
VIP_INT0_CHANNEL0_INT_MASK ..................................................................................
Register Call Summary for Register VIP_INT0_CHANNEL0_INT_MASK .......................................
VIP_INT0_CHANNEL1_INT_STAT ...................................................................................
Register Call Summary for Register VIP_INT0_CHANNEL1_INT_STAT .......................................
VIP_INT0_CHANNEL1_INT_MASK ..................................................................................
Register Call Summary for Register VIP_INT0_CHANNEL1_INT_MASK .......................................
9-296. Register Call Summary for Register VIP_LIST_STAT_SYNC
List of Tables
2152
2152
2153
2153
2153
2153
2154
2154
2154
2154
2155
2155
2157
2157
2158
2159
2162
2162
2164
SPRUIC2D – January 2017 – Revised April 2019
Submit Documentation Feedback
Copyright © 2017–2019, Texas Instruments Incorporated
www.ti.com
9-317. VIP_INT0_CHANNEL2_INT_STAT ................................................................................... 2164
9-318. Register Call Summary for Register VIP_INT0_CHANNEL2_INT_STAT
.......................................
2168
9-319. VIP_INT0_CHANNEL2_INT_MASK .................................................................................. 2168
9-320. Register Call Summary for Register VIP_INT0_CHANNEL2_INT_MASK ....................................... 2171
9-321. VIP_INT0_CHANNEL3_INT_STAT ................................................................................... 2171
.......................................
VIP_INT0_CHANNEL3_INT_MASK ..................................................................................
Register Call Summary for Register VIP_INT0_CHANNEL3_INT_MASK .......................................
VIP_INT0_CHANNEL4_INT_STAT ...................................................................................
Register Call Summary for Register VIP_INT0_CHANNEL4_INT_STAT .......................................
VIP_INT0_CHANNEL4_INT_MASK ..................................................................................
Register Call Summary for Register VIP_INT0_CHANNEL4_INT_MASK .......................................
VIP_INT0_CHANNEL5_INT_STAT ...................................................................................
Register Call Summary for Register VIP_INT0_CHANNEL5_INT_STAT .......................................
VIP_INT0_CHANNEL5_INT_MASK ..................................................................................
Register Call Summary for Register VIP_INT0_CHANNEL5_INT_MASK .......................................
VIP_INT0_CLIENT0_INT_STAT ......................................................................................
Register Call Summary for Register VIP_INT0_CLIENT0_INT_STAT ...........................................
VIP_INT0_CLIENT0_INT_MASK .....................................................................................
Register Call Summary for Register VIP_INT0_CLIENT0_INT_MASK ..........................................
VIP_INT0_CLIENT1_INT_STAT ......................................................................................
Register Call Summary for Register VIP_INT0_CLIENT1_INT_STAT ...........................................
VIP_INT0_CLIENT1_INT_MASK .....................................................................................
Register Call Summary for Register VIP_INT0_CLIENT1_INT_MASK ..........................................
VIP_INT0_LIST0_INT_STAT ..........................................................................................
Register Call Summary for Register VIP_INT0_LIST0_INT_STAT ...............................................
VIP_INT0_LIST0_INT_MASK .........................................................................................
Register Call Summary for Register VIP_INT0_LIST0_INT_MASK ..............................................
VIP_INT1_CHANNEL0_INT_STAT ...................................................................................
Register Call Summary for Register VIP_INT1_CHANNEL0_INT_STAT .......................................
VIP_INT1_CHANNEL0_INT_MASK ..................................................................................
Register Call Summary for Register VIP_INT1_CHANNEL0_INT_MASK .......................................
VIP_INT1_CHANNEL1_INT_STAT ...................................................................................
Register Call Summary for Register VIP_INT1_CHANNEL1_INT_STAT .......................................
VIP_INT1_CHANNEL1_INT_MASK ..................................................................................
Register Call Summary for Register VIP_INT1_CHANNEL1_INT_MASK .......................................
VIP_INT1_CHANNEL2_INT_STAT ...................................................................................
Register Call Summary for Register VIP_INT1_CHANNEL2_INT_STAT .......................................
VIP_INT1_CHANNEL2_INT_MASK ..................................................................................
Register Call Summary for Register VIP_INT1_CHANNEL2_INT_MASK .......................................
VIP_INT1_CHANNEL3_INT_STAT ...................................................................................
Register Call Summary for Register VIP_INT1_CHANNEL3_INT_STAT .......................................
VIP_INT1_CHANNEL3_INT_MASK ..................................................................................
Register Call Summary for Register VIP_INT1_CHANNEL3_INT_MASK .......................................
VIP_INT1_CHANNEL4_INT_STAT ...................................................................................
Register Call Summary for Register VIP_INT1_CHANNEL4_INT_STAT .......................................
VIP_INT1_CHANNEL4_INT_MASK ..................................................................................
Register Call Summary for Register VIP_INT1_CHANNEL4_INT_MASK .......................................
VIP_INT1_CHANNEL5_INT_STAT ...................................................................................
9-322. Register Call Summary for Register VIP_INT0_CHANNEL3_INT_STAT
2175
9-323.
2175
9-324.
9-325.
9-326.
9-327.
9-328.
9-329.
9-330.
9-331.
9-332.
9-333.
9-334.
9-335.
9-336.
9-337.
9-338.
9-339.
9-340.
9-341.
9-342.
9-343.
9-344.
9-345.
9-346.
9-347.
9-348.
9-349.
9-350.
9-351.
9-352.
9-353.
9-354.
9-355.
9-356.
9-357.
9-358.
9-359.
9-360.
9-361.
9-362.
9-363.
9-364.
9-365.
SPRUIC2D – January 2017 – Revised April 2019
Submit Documentation Feedback
Copyright © 2017–2019, Texas Instruments Incorporated
List of Tables
2177
2177
2181
2181
2184
2184
2188
2188
2190
2190
2193
2193
2194
2194
2198
2198
2200
2200
2203
2204
2206
2206
2208
2208
2209
2210
2213
2213
2215
2215
2219
2219
2222
2222
2226
2226
2228
2228
2232
2232
2235
2235
149
www.ti.com
2239
9-367.
2239
9-368.
9-369.
9-370.
9-371.
9-372.
9-373.
9-374.
9-375.
9-376.
9-377.
9-378.
9-379.
9-380.
9-381.
9-382.
9-383.
9-384.
9-385.
9-386.
9-387.
9-388.
9-389.
9-390.
9-391.
9-392.
9-393.
9-394.
9-395.
9-396.
9-397.
9-398.
9-399.
9-400.
9-401.
9-402.
9-403.
9-404.
9-405.
9-406.
9-407.
9-408.
9-409.
9-410.
9-411.
9-412.
9-413.
9-414.
150
.......................................
VIP_INT1_CHANNEL5_INT_MASK ..................................................................................
Register Call Summary for Register VIP_INT1_CHANNEL5_INT_MASK .......................................
VIP_INT1_CLIENT0_INT_STAT ......................................................................................
Register Call Summary for Register VIP_INT1_CLIENT0_INT_STAT ...........................................
VIP_INT1_CLIENT0_INT_MASK .....................................................................................
Register Call Summary for Register VIP_INT1_CLIENT0_INT_MASK ..........................................
VIP_INT1_CLIENT1_INT_STAT ......................................................................................
Register Call Summary for Register VIP_INT1_CLIENT1_INT_STAT ...........................................
VIP_INT1_CLIENT1_INT_MASK .....................................................................................
Register Call Summary for Register VIP_INT1_CLIENT1_INT_MASK ..........................................
VIP_INT1_LIST0_INT_STAT ..........................................................................................
Register Call Summary for Register VIP_INT1_LIST0_INT_STAT ...............................................
VIP_INT1_LIST0_INT_MASK .........................................................................................
Register Call Summary for Register VIP_INT1_LIST0_INT_MASK ..............................................
VIP_PERF_MON0 ......................................................................................................
Register Call Summary for Register VIP_PERF_MON0 ...........................................................
VIP_PERF_MON1 ......................................................................................................
Register Call Summary for Register VIP_PERF_MON1 ...........................................................
VIP_PERF_MON2 ......................................................................................................
Register Call Summary for Register VIP_PERF_MON2 ...........................................................
VIP_PERF_MON3 ......................................................................................................
Register Call Summary for Register VIP_PERF_MON3 ...........................................................
VIP_PERF_MON4 ......................................................................................................
Register Call Summary for Register VIP_PERF_MON4 ...........................................................
VIP_PERF_MON5 ......................................................................................................
Register Call Summary for Register VIP_PERF_MON5 ...........................................................
VIP_PERF_MON6 ......................................................................................................
Register Call Summary for Register VIP_PERF_MON6 ...........................................................
VIP_PERF_MON7 ......................................................................................................
Register Call Summary for Register VIP_PERF_MON7 ...........................................................
VIP_PERF_MON8 ......................................................................................................
Register Call Summary for Register VIP_PERF_MON8 ...........................................................
VIP_PERF_MON9 ......................................................................................................
Register Call Summary for Register VIP_PERF_MON9 ...........................................................
VIP_PERF_MON10 .....................................................................................................
Register Call Summary for Register VIP_PERF_MON10 .........................................................
VIP_PERF_MON11 .....................................................................................................
Register Call Summary for Register VIP_PERF_MON11 .........................................................
VIP_PERF_MON12 .....................................................................................................
Register Call Summary for Register VIP_PERF_MON12 .........................................................
VIP_PERF_MON13 .....................................................................................................
Register Call Summary for Register VIP_PERF_MON13 .........................................................
VIP_PERF_MON14 .....................................................................................................
Register Call Summary for Register VIP_PERF_MON14 .........................................................
VIP_PERF_MON15 .....................................................................................................
Register Call Summary for Register VIP_PERF_MON15 .........................................................
VIP_PERF_MON16 .....................................................................................................
Register Call Summary for Register VIP_PERF_MON16 .........................................................
9-366. Register Call Summary for Register VIP_INT1_CHANNEL5_INT_STAT
List of Tables
2241
2241
2244
2244
2245
2245
2249
2249
2251
2251
2254
2255
2257
2257
2257
2258
2258
2258
2259
2259
2260
2260
2261
2261
2261
2262
2262
2262
2263
2263
2264
2264
2265
2265
2265
2266
2266
2266
2267
2267
2268
2268
2269
2269
2269
2270
2270
SPRUIC2D – January 2017 – Revised April 2019
Submit Documentation Feedback
Copyright © 2017–2019, Texas Instruments Incorporated
www.ti.com
9-415. VIP_PERF_MON17 ..................................................................................................... 2270
9-416. Register Call Summary for Register VIP_PERF_MON17
.........................................................
2271
9-417. VIP_PERF_MON18 ..................................................................................................... 2271
.........................................................
VIP_PERF_MON19 .....................................................................................................
Register Call Summary for Register VIP_PERF_MON19 .........................................................
VIP_PERF_MON20 .....................................................................................................
Register Call Summary for Register VIP_PERF_MON20 .........................................................
VIP_PERF_MON21 .....................................................................................................
Register Call Summary for Register VIP_PERF_MON21 .........................................................
VIP_PERF_MON22 .....................................................................................................
Register Call Summary for Register VIP_PERF_MON22 .........................................................
VIP_PERF_MON23 .....................................................................................................
Register Call Summary for Register VIP_PERF_MON23 .........................................................
VIP_PERF_MON24 .....................................................................................................
Register Call Summary for Register VIP_PERF_MON24 .........................................................
VIP_PERF_MON25 .....................................................................................................
Register Call Summary for Register VIP_PERF_MON25 .........................................................
VIP_PERF_MON26 .....................................................................................................
Register Call Summary for Register VIP_PERF_MON26 .........................................................
VIP_PERF_MON27 .....................................................................................................
Register Call Summary for Register VIP_PERF_MON27 .........................................................
VIP_PERF_MON28 .....................................................................................................
Register Call Summary for Register VIP_PERF_MON28 .........................................................
VIP_PERF_MON29 .....................................................................................................
Register Call Summary for Register VIP_PERF_MON29 .........................................................
VIP_PERF_MON30 .....................................................................................................
Register Call Summary for Register VIP_PERF_MON30 .........................................................
VIP_PERF_MON31 .....................................................................................................
Register Call Summary for Register VIP_PERF_MON31 .........................................................
VIP_PERF_MON32 .....................................................................................................
Register Call Summary for Register VIP_PERF_MON32 .........................................................
VIP_PERF_MON33 .....................................................................................................
Register Call Summary for Register VIP_PERF_MON33 .........................................................
VIP_PERF_MON34 .....................................................................................................
Register Call Summary for Register VIP_PERF_MON34 .........................................................
VIP_PERF_MON35 .....................................................................................................
Register Call Summary for Register VIP_PERF_MON35 .........................................................
VIP_PERF_MON36 .....................................................................................................
Register Call Summary for Register VIP_PERF_MON36 .........................................................
VIP_PERF_MON37 .....................................................................................................
Register Call Summary for Register VIP_PERF_MON37 .........................................................
VIP_PERF_MON38 .....................................................................................................
Register Call Summary for Register VIP_PERF_MON38 .........................................................
VIP_PERF_MON39 .....................................................................................................
Register Call Summary for Register VIP_PERF_MON39 .........................................................
VIP_PERF_MON40 .....................................................................................................
Register Call Summary for Register VIP_PERF_MON40 .........................................................
VIP_PERF_MON41 .....................................................................................................
9-418. Register Call Summary for Register VIP_PERF_MON18
9-419.
9-420.
9-421.
9-422.
9-423.
9-424.
9-425.
9-426.
9-427.
9-428.
9-429.
9-430.
9-431.
9-432.
9-433.
9-434.
9-435.
9-436.
9-437.
9-438.
9-439.
9-440.
9-441.
9-442.
9-443.
9-444.
9-445.
9-446.
9-447.
9-448.
9-449.
9-450.
9-451.
9-452.
9-453.
9-454.
9-455.
9-456.
9-457.
9-458.
9-459.
9-460.
9-461.
9-462.
9-463.
SPRUIC2D – January 2017 – Revised April 2019
Submit Documentation Feedback
Copyright © 2017–2019, Texas Instruments Incorporated
List of Tables
2272
2272
2273
2273
2273
2274
2274
2274
2275
2275
2276
2276
2277
2277
2277
2278
2278
2278
2279
2279
2280
2280
2281
2281
2281
2282
2282
2282
2283
2283
2284
2284
2285
2285
2285
2286
2286
2286
2287
2287
2288
2288
2289
2289
2290
2290
151
www.ti.com
.........................................................
VIP_PERF_MON42 .....................................................................................................
Register Call Summary for Register VIP_PERF_MON42 .........................................................
VIP_PERF_MON43 .....................................................................................................
Register Call Summary for Register VIP_PERF_MON43 .........................................................
VIP_PERF_MON44 .....................................................................................................
Register Call Summary for Register VIP_PERF_MON44 .........................................................
VIP_PERF_MON45 .....................................................................................................
Register Call Summary for Register VIP_PERF_MON45 .........................................................
VIP_PERF_MON46 .....................................................................................................
Register Call Summary for Register VIP_PERF_MON46 .........................................................
VIP_PERF_MON47 .....................................................................................................
Register Call Summary for Register VIP_PERF_MON47 .........................................................
VIP_PERF_MON48 .....................................................................................................
Register Call Summary for Register VIP_PERF_MON48 .........................................................
VIP_PERF_MON49 .....................................................................................................
Register Call Summary for Register VIP_PERF_MON49 .........................................................
VIP_PERF_MON50 .....................................................................................................
Register Call Summary for Register VIP_PERF_MON50 .........................................................
VIP_PERF_MON51 .....................................................................................................
Register Call Summary for Register VIP_PERF_MON51 .........................................................
VIP_PERF_MON52 .....................................................................................................
Register Call Summary for Register VIP_PERF_MON52 .........................................................
VIP_PERF_MON53 .....................................................................................................
Register Call Summary for Register VIP_PERF_MON53 .........................................................
VIP_PERF_MON54 .....................................................................................................
Register Call Summary for Register VIP_PERF_MON54 .........................................................
VIP_PERF_MON55 .....................................................................................................
Register Call Summary for Register VIP_PERF_MON55 .........................................................
VIP_PERF_MON56 .....................................................................................................
Register Call Summary for Register VIP_PERF_MON56 .........................................................
VIP_PERF_MON57 .....................................................................................................
Register Call Summary for Register VIP_PERF_MON57 .........................................................
VIP_PERF_MON58 .....................................................................................................
Register Call Summary for Register VIP_PERF_MON58 .........................................................
VIP_PERF_MON59 .....................................................................................................
Register Call Summary for Register VIP_PERF_MON59 .........................................................
VIP_PERF_MON60 .....................................................................................................
Register Call Summary for Register VIP_PERF_MON60 .........................................................
VIP_PERF_MON61 .....................................................................................................
Register Call Summary for Register VIP_PERF_MON61 .........................................................
VIP0_LO_Y_CSTAT ....................................................................................................
Register Call Summary for Register VIP0_LO_Y_CSTAT .........................................................
VIP0_LO_UV_CSTAT ..................................................................................................
Register Call Summary for Register VIP0_LO_UV_CSTAT .......................................................
VIP0_UP_Y_CSTAT ....................................................................................................
Register Call Summary for Register VIP0_UP_Y_CSTAT.........................................................
VIP0_UP_UV_CSTAT ..................................................................................................
Register Call Summary for Register VIP0_UP_UV_CSTAT .......................................................
9-464. Register Call Summary for Register VIP_PERF_MON41
9-465.
9-466.
9-467.
9-468.
9-469.
9-470.
9-471.
9-472.
9-473.
9-474.
9-475.
9-476.
9-477.
9-478.
9-479.
9-480.
9-481.
9-482.
9-483.
9-484.
9-485.
9-486.
9-487.
9-488.
9-489.
9-490.
9-491.
9-492.
9-493.
9-494.
9-495.
9-496.
9-497.
9-498.
9-499.
9-500.
9-501.
9-502.
9-503.
9-504.
9-505.
9-506.
9-507.
9-508.
9-509.
9-510.
9-511.
9-512.
152
List of Tables
2290
2290
2291
2291
2292
2292
2293
2293
2293
2294
2294
2294
2295
2295
2296
2296
2297
2297
2297
2298
2298
2298
2299
2299
2300
2300
2301
2301
2301
2302
2302
2302
2303
2303
2304
2304
2305
2305
2305
2306
2306
2306
2307
2307
2308
2308
2309
2309
2310
SPRUIC2D – January 2017 – Revised April 2019
Submit Documentation Feedback
Copyright © 2017–2019, Texas Instruments Incorporated
www.ti.com
9-513. VIP1_LO_Y_CSTAT .................................................................................................... 2310
9-514. Register Call Summary for Register VIP1_LO_Y_CSTAT ......................................................... 2310
9-515. VIP1_LO_UV_CSTAT .................................................................................................. 2311
9-516. Register Call Summary for Register VIP1_LO_UV_CSTAT ....................................................... 2311
9-517. VIP1_UP_Y_CSTAT .................................................................................................... 2311
9-518. Register Call Summary for Register VIP1_UP_Y_CSTAT......................................................... 2312
9-519. VIP1_UP_UV_CSTAT .................................................................................................. 2312
9-520. Register Call Summary for Register VIP1_UP_UV_CSTAT ....................................................... 2313
.......................................................................................................
Register Call Summary for Register VPI_CTL_CSTAT ............................................................
VIP0_ANC_A_CSTAT ..................................................................................................
Register Call Summary for Register VIP0_ANC_A_CSTAT .......................................................
VIP0_ANC_B_CSTAT ..................................................................................................
Register Call Summary for Register VIP0_ANC_B_CSTAT .......................................................
VIP1_ANC_A_CSTAT ..................................................................................................
Register Call Summary for Register VIP1_ANC_A_CSTAT .......................................................
VIP1_ANC_B_CSTAT ..................................................................................................
Register Call Summary for Register VIP1_ANC_B_CSTAT .......................................................
VPE Integration Attributes ..............................................................................................
VPE Clocks and Resets ................................................................................................
VPE Hardware Requests ...............................................................................................
Parameter Description ..................................................................................................
Vertical Scaler Configuration Parameters ............................................................................
Register Group 1 ........................................................................................................
Register Group 2 ........................................................................................................
Register Group 3 ........................................................................................................
Scaler Configuration ....................................................................................................
Vertical Scaler Configuration ..........................................................................................
Coefficient Data Files ...................................................................................................
Quantized Coefficients of HDTV Application with Video Data Range ............................................
Quantized Coefficients of HDTV Application with Graphics Data Range ........................................
Quantized Coefficients of SDTV Application with Video Data Range ............................................
Quantized Coefficients of SDTV Application with Graphics Data Range ........................................
VPDMA Modes of Operation...........................................................................................
VPDMA Client Buffering and Functionality ...........................................................................
VPDMA Channels Assignment ........................................................................................
VPDMA Interrupt Events ...............................................................................................
VPE Interrupt Sources ..................................................................................................
Data Packet Descriptor Word 0 Field Descriptions .................................................................
Common ARGB in Memory (Byte Order) ............................................................................
Common ARGB in 32-bit Memory/CPU Register ...................................................................
VPDMA ARGB in Memory (Byte Order)..............................................................................
VPDMA ARGB in 32-bit Memory/CPU Register ....................................................................
VPDMA Descriptor RGB Data Type Mapping .......................................................................
VPDMA Descriptor YUV Data Type Mapping .......................................................................
Data Packet Descriptor Word 1 Field Description ..................................................................
Data Packet Descriptor Word 2 Field Descriptions .................................................................
Data Packet Descriptor Word 3 Field Descriptions .................................................................
Data Packet Descriptor Word 4 Inbound Data Field Descriptions ................................................
9-521. VPI_CTL_CSTAT
2313
9-522.
2314
9-523.
9-524.
9-525.
9-526.
9-527.
9-528.
9-529.
9-530.
10-1.
10-2.
10-3.
10-4.
10-5.
10-6.
10-7.
10-8.
10-9.
10-10.
10-11.
10-12.
10-13.
10-14.
10-15.
10-16.
10-17.
10-18.
10-19.
10-20.
10-21.
10-22.
10-23.
10-24.
10-25.
10-26.
10-27.
10-28.
10-29.
10-30.
10-31.
SPRUIC2D – January 2017 – Revised April 2019
Submit Documentation Feedback
Copyright © 2017–2019, Texas Instruments Incorporated
List of Tables
2314
2315
2315
2316
2316
2316
2317
2317
2321
2322
2322
2335
2336
2340
2340
2341
2341
2341
2344
2368
2368
2370
2371
2375
2379
2379
2380
2382
2387
2388
2388
2389
2389
2389
2390
2391
2392
2392
2393
153
www.ti.com
10-32. Data Packet Descriptor Word 4 Outbound Data Field Descriptions .............................................. 2394
10-33. Data Packet Descriptor Word 5 Outbound Data Field Descriptions .............................................. 2395
10-34. Configuration Descriptor Header Word0 Field Descriptions ....................................................... 2396
10-35. Configuration Descriptor Header Word1 Field Descriptions ....................................................... 2396
10-36. Configuration Descriptor Header Word2 Field Descriptions ....................................................... 2396
10-37. Configuration Descriptor Header Word3 Field Descriptions ....................................................... 2397
10-38. Address Data Block Format Field Descriptions ..................................................................... 2397
10-39. Destination Field Description
..........................................................................................
2398
10-40. Control Descriptor Header Description ............................................................................... 2398
10-41. Control Descriptor Types Summary
..................................................................................
2399
10-42. Sync on Client Field Descriptions (Word - 1) ........................................................................ 2399
10-43. Sync on Client Field Descriptions (Word - 3) ........................................................................ 2399
10-44. Sync on List Field Descriptions (Word - 3)........................................................................... 2400
10-45. Sync on External Event Field Descriptions (Word - 3) ............................................................. 2400
10-46. Sync on Channel Field Descriptions (Word - 3) ..................................................................... 2400
2401
10-48.
2401
10-49.
10-50.
10-51.
10-52.
10-53.
10-54.
10-55.
10-56.
10-57.
10-58.
10-59.
10-60.
10-61.
10-62.
10-63.
10-64.
10-65.
10-66.
10-67.
10-68.
10-69.
10-70.
10-71.
10-72.
10-73.
10-74.
10-75.
10-76.
10-77.
10-78.
10-79.
10-80.
154
.............................................................
Change Client Interrupt Field Descriptions (Word - 2) .............................................................
Change Client Interrupt Field Descriptions (Word - 3) .............................................................
Send Interrupt Field Descriptions (Word - 3) ........................................................................
Reload List Field Descriptions (Word - 0) ............................................................................
Reload List Field Descriptions (Word - 1) ............................................................................
Reload List Field Descriptions (Word - 3) ............................................................................
Abort Channel Field Descriptions (Word - 3) ........................................................................
VPE Instance Summary ................................................................................................
VPE_CSC Registers Mapping Summary ............................................................................
VPE_CSC00 .............................................................................................................
Register Call Summary for Register VPE_CSC00 ..................................................................
VPE_CSC01 .............................................................................................................
Register Call Summary for Register VPE_CSC01 ..................................................................
VPE_CSC02 .............................................................................................................
Register Call Summary for Register VPE_CSC02 ..................................................................
VPE_CSC03 .............................................................................................................
Register Call Summary for Register VPE_CSC03 ..................................................................
VPE_CSC04 .............................................................................................................
Register Call Summary for Register VPE_CSC04 ..................................................................
VPE_CSC05 .............................................................................................................
Register Call Summary for Register VPE_CSC05 ..................................................................
VPE_SC Registers Mapping Summary ..............................................................................
VPE_CFG_SC0 .........................................................................................................
Register Call Summary for Register VPE_CFG_SC0 ..............................................................
VPE_CFG_SC1 .........................................................................................................
Register Call Summary for Register VPE_CFG_SC1 ..............................................................
VPE_CFG_SC2 .........................................................................................................
Register Call Summary for Register VPE_CFG_SC2 ..............................................................
VPE_CFG_SC3 .........................................................................................................
Register Call Summary for Register VPE_CFG_SC3 ..............................................................
VPE_CFG_SC4 .........................................................................................................
Register Call Summary for Register VPE_CFG_SC4 ..............................................................
VPE_CFG_SC5 .........................................................................................................
10-47. Change Client Interrupt Field Descriptions (Word - 1)
List of Tables
2401
2402
2402
2402
2402
2402
2420
2420
2421
2421
2421
2422
2422
2423
2423
2423
2423
2424
2424
2424
2425
2425
2427
2427
2428
2428
2428
2428
2429
2429
2430
2430
SPRUIC2D – January 2017 – Revised April 2019
Submit Documentation Feedback
Copyright © 2017–2019, Texas Instruments Incorporated
www.ti.com
10-81. Register Call Summary for Register VPE_CFG_SC5 .............................................................. 2430
10-82. VPE_CFG_SC6
.........................................................................................................
2430
10-83. Register Call Summary for Register VPE_CFG_SC6 .............................................................. 2431
.........................................................................................................
10-85. Register Call Summary for Register VPE_CFG_SC8 ..............................................................
10-86. VPE_CFG_SC9 .........................................................................................................
10-87. Register Call Summary for Register VPE_CFG_SC9 ..............................................................
10-88. VPE_CFG_SC10 ........................................................................................................
10-89. Register Call Summary for Register VPE_CFG_SC10 ............................................................
10-90. VPE_CFG_SC11 ........................................................................................................
10-91. Register Call Summary for Register VPE_CFG_SC11 ............................................................
10-92. VPE_CFG_SC12 ........................................................................................................
10-93. Register Call Summary for Register VPE_CFG_SC12 ............................................................
10-94. VPE_CFG_SC13 ........................................................................................................
10-95. Register Call Summary for Register VPE_CFG_SC13 ............................................................
10-96. VPE_CFG_SC18 ........................................................................................................
10-97. Register Call Summary for Register VPE_CFG_SC18 ............................................................
10-98. VPE_CFG_SC19 ........................................................................................................
10-99. Register Call Summary for Register VPE_CFG_SC19 ............................................................
10-100. VPE_CFG_SC20.......................................................................................................
10-101. Register Call Summary for Register VPE_CFG_SC20 ...........................................................
10-102. VPE_CFG_SC21.......................................................................................................
10-103. Register Call Summary for Register VPE_CFG_SC21 ...........................................................
10-104. VPE_CFG_SC22.......................................................................................................
10-105. Register Call Summary for Register VPE_CFG_SC22 ...........................................................
10-106. VPE_CFG_SC24.......................................................................................................
10-107. Register Call Summary for Register VPE_CFG_SC24 ...........................................................
10-108. VPE_CFG_SC25.......................................................................................................
10-109. Register Call Summary for Register VPE_CFG_SC25 ...........................................................
10-110. VPE_CHR_US Registers Mapping Summary ......................................................................
10-111. VPE_PID ................................................................................................................
10-112. Register Call Summary for Register VPE_PID.....................................................................
10-113. VPE_REG0 .............................................................................................................
10-114. Register Call Summary for Register VPE_REG0 ..................................................................
10-115. VPE_REG1 .............................................................................................................
10-116. Register Call Summary for Register VPE_REG1 ..................................................................
10-117. VPE_REG2 .............................................................................................................
10-118. Register Call Summary for Register VPE_REG2 ..................................................................
10-119. VPE_REG3 .............................................................................................................
10-120. Register Call Summary for Register VPE_REG3 ..................................................................
10-121. VPE_REG4 .............................................................................................................
10-122. Register Call Summary for Register VPE_REG4 ..................................................................
10-123. VPE_REG5 .............................................................................................................
10-124. Register Call Summary for Register VPE_REG5 ..................................................................
10-125. VPE_REG6 .............................................................................................................
10-126. Register Call Summary for Register VPE_REG6 ..................................................................
10-127. VPE_REG7 .............................................................................................................
10-128. Register Call Summary for Register VPE_REG7 ..................................................................
10-129. VPE_DEI Registers Mapping Summary ............................................................................
10-84. VPE_CFG_SC8
SPRUIC2D – January 2017 – Revised April 2019
Submit Documentation Feedback
Copyright © 2017–2019, Texas Instruments Incorporated
List of Tables
2431
2432
2432
2432
2432
2433
2433
2433
2433
2434
2434
2434
2434
2434
2435
2435
2435
2436
2436
2436
2436
2437
2437
2437
2438
2438
2438
2438
2439
2439
2439
2439
2440
2440
2440
2441
2441
2441
2442
2442
2442
2442
2443
2443
2443
2443
155
www.ti.com
10-130. VPE_DEI_REG0 ....................................................................................................... 2444
10-131. Register Call Summary for Register VPE_DEI_REG0 ............................................................ 2445
10-132. VPE_DEI_REG1 ....................................................................................................... 2445
10-133. Register Call Summary for Register VPE_DEI_REG1 ............................................................ 2445
10-134. VPE_DEI_REG2 ....................................................................................................... 2445
10-135. Register Call Summary for Register VPE_DEI_REG2 ............................................................ 2446
10-136. VPE_DEI_REG3 ....................................................................................................... 2446
10-137. Register Call Summary for Register VPE_DEI_REG3 ............................................................ 2447
10-138. VPE_DEI_REG4 ....................................................................................................... 2447
10-139. Register Call Summary for Register VPE_DEI_REG4 ............................................................ 2448
10-140. VPE_DEI_REG5 ....................................................................................................... 2448
10-141. Register Call Summary for Register VPE_DEI_REG5 ............................................................ 2448
10-142. VPE_DEI_REG6 ....................................................................................................... 2448
10-143. Register Call Summary for Register VPE_DEI_REG6 ............................................................ 2449
10-144. VPE_DEI_REG7 ....................................................................................................... 2449
10-145. Register Call Summary for Register VPE_DEI_REG7 ............................................................ 2449
10-146. VPE_DEI_REG8 ....................................................................................................... 2449
10-147. Register Call Summary for Register VPE_DEI_REG8 ............................................................ 2450
10-148. VPE_DEI_REG9 ....................................................................................................... 2450
10-149. Register Call Summary for Register VPE_DEI_REG9 ............................................................ 2450
10-150. VPE_DEI_REG10 ...................................................................................................... 2451
10-151. Register Call Summary for Register VPE_DEI_REG10 .......................................................... 2451
10-152. VPE_DEI_REG11 ...................................................................................................... 2452
10-153. Register Call Summary for Register VPE_DEI_REG11 .......................................................... 2452
10-154. VPE_DEI_REG12 ...................................................................................................... 2452
10-155. Register Call Summary for Register VPE_DEI_REG12 .......................................................... 2452
10-156. VPE_DEI_REG13 ...................................................................................................... 2453
10-157. Register Call Summary for Register VPE_DEI_REG13 .......................................................... 2453
10-158. VPE_DEI_REG14 ...................................................................................................... 2453
10-159. Register Call Summary for Register VPE_DEI_REG14 .......................................................... 2453
10-160. VPE_VPDMA Registers Mapping Summary ....................................................................... 2455
10-161. VPE_VPDMA_PID ..................................................................................................... 2458
10-162. Register Call Summary for Register VPE_VPDMA_PID
.........................................................
2459
10-163. VPE_LIST_ADDR ...................................................................................................... 2459
10-164. Register Call Summary for Register VPE_LIST_ADDR .......................................................... 2459
10-165. VPE_LIST_ATTR ...................................................................................................... 2460
10-166. Register Call Summary for Register VPE_LIST_ATTR ........................................................... 2460
10-167. VPE_LIST_STAT_SYNC
.............................................................................................
2461
10-168. Register Call Summary for Register VPE_LIST_STAT_SYNC .................................................. 2462
10-169. VPE_BG_RGB ......................................................................................................... 2462
10-170. Register Call Summary for Register VPE_BG_RGB .............................................................. 2462
10-171. VPE_BG_YUV.......................................................................................................... 2462
10-172. Register Call Summary for Register VPE_BG_YUV .............................................................. 2463
................................................................................................
Register Call Summary for Register VPE_VPDMA_SETUP .....................................................
VPE_MAX_SIZE1 ......................................................................................................
Register Call Summary for Register VPE_MAX_SIZE1 ..........................................................
VPE_MAX_SIZE2 ......................................................................................................
Register Call Summary for Register VPE_MAX_SIZE2 ..........................................................
10-173. VPE_VPDMA_SETUP
10-174.
10-175.
10-176.
10-177.
10-178.
156
List of Tables
2463
2463
2463
2464
2464
2464
SPRUIC2D – January 2017 – Revised April 2019
Submit Documentation Feedback
Copyright © 2017–2019, Texas Instruments Incorporated
www.ti.com
10-179. VPE_MAX_SIZE3 ...................................................................................................... 2464
10-180. Register Call Summary for Register VPE_MAX_SIZE3 .......................................................... 2465
10-181. VPE_INT0_CHANNEL0_INT_STAT................................................................................. 2465
10-182. Register Call Summary for Register VPE_INT0_CHANNEL0_INT_STAT ..................................... 2467
10-183. VPE_INT0_CHANNEL0_INT_MASK ................................................................................ 2467
10-184. Register Call Summary for Register VPE_INT0_CHANNEL0_INT_MASK .................................... 2468
10-185. VPE_INT0_CHANNEL1_INT_STAT................................................................................. 2469
10-186. Register Call Summary for Register VPE_INT0_CHANNEL1_INT_STAT ..................................... 2472
10-187. VPE_INT0_CHANNEL1_INT_MASK ................................................................................ 2472
10-188. Register Call Summary for Register VPE_INT0_CHANNEL1_INT_MASK .................................... 2475
10-189. VPE_INT0_CHANNEL2_INT_STAT................................................................................. 2475
10-190. Register Call Summary for Register VPE_INT0_CHANNEL2_INT_STAT ..................................... 2479
10-191. VPE_INT0_CHANNEL2_INT_MASK ................................................................................ 2479
10-192. Register Call Summary for Register VPE_INT0_CHANNEL2_INT_MASK .................................... 2482
10-193. VPE_INT0_CHANNEL3_INT_STAT................................................................................. 2482
10-194. Register Call Summary for Register VPE_INT0_CHANNEL3_INT_STAT ..................................... 2487
10-195. VPE_INT0_CHANNEL3_INT_MASK ................................................................................ 2487
10-196. Register Call Summary for Register VPE_INT0_CHANNEL3_INT_MASK .................................... 2489
10-197. VPE_INT0_CHANNEL4_INT_STAT................................................................................. 2489
10-198. Register Call Summary for Register VPE_INT0_CHANNEL4_INT_STAT ..................................... 2494
10-199. VPE_INT0_CHANNEL4_INT_MASK ................................................................................ 2494
10-200. Register Call Summary for Register VPE_INT0_CHANNEL4_INT_MASK .................................... 2496
10-201. VPE_INT0_CHANNEL5_INT_STAT................................................................................. 2497
10-202. Register Call Summary for Register VPE_INT0_CHANNEL5_INT_STAT ..................................... 2501
10-203. VPE_INT0_CHANNEL5_INT_MASK ................................................................................ 2501
10-204. Register Call Summary for Register VPE_INT0_CHANNEL5_INT_MASK .................................... 2503
10-205. VPE_INT0_CLIENT0_INT_STAT .................................................................................... 2503
10-206. Register Call Summary for Register VPE_INT0_CLIENT0_INT_STAT ........................................ 2506
10-207. VPE_INT0_CLIENT0_INT_MASK ................................................................................... 2506
10-208. Register Call Summary for Register VPE_INT0_CLIENT0_INT_MASK........................................ 2507
10-209. VPE_INT0_CLIENT1_INT_STAT .................................................................................... 2507
10-210. Register Call Summary for Register VPE_INT0_CLIENT1_INT_STAT ........................................ 2511
10-211. VPE_INT0_CLIENT1_INT_MASK ................................................................................... 2511
10-212. Register Call Summary for Register VPE_INT0_CLIENT1_INT_MASK........................................ 2513
10-213. VPE_INT0_LIST0_INT_STAT ........................................................................................ 2513
10-214. Register Call Summary for Register VPE_INT0_LIST0_INT_STAT ............................................ 2516
10-215. VPE_INT0_LIST0_INT_MASK ....................................................................................... 2516
10-216. Register Call Summary for Register VPE_INT0_LIST0_INT_MASK
...........................................
2518
10-217. VPE_PERF_MON0 .................................................................................................... 2519
10-218. Register Call Summary for Register VPE_PERF_MON0......................................................... 2520
10-219. VPE_PERF_MON1 .................................................................................................... 2520
10-220. Register Call Summary for Register VPE_PERF_MON1......................................................... 2521
10-221. VPE_PERF_MON2 .................................................................................................... 2521
10-222. Register Call Summary for Register VPE_PERF_MON2......................................................... 2522
10-223. VPE_PERF_MON3 .................................................................................................... 2523
10-224. Register Call Summary for Register VPE_PERF_MON3......................................................... 2524
10-225. VPE_PERF_MON4 .................................................................................................... 2524
10-226. Register Call Summary for Register VPE_PERF_MON4......................................................... 2525
10-227. VPE_PERF_MON5 .................................................................................................... 2525
SPRUIC2D – January 2017 – Revised April 2019
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List of Tables
157
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10-228. Register Call Summary for Register VPE_PERF_MON5......................................................... 2526
10-229. VPE_PERF_MON6 .................................................................................................... 2527
10-230. Register Call Summary for Register VPE_PERF_MON6......................................................... 2528
10-231. VPE_PERF_MON7 .................................................................................................... 2528
10-232. Register Call Summary for Register VPE_PERF_MON7......................................................... 2529
10-233. VPE_PERF_MON8 .................................................................................................... 2529
10-234. Register Call Summary for Register VPE_PERF_MON8......................................................... 2530
10-235. VPE_PERF_MON9 .................................................................................................... 2531
10-236. Register Call Summary for Register VPE_PERF_MON9......................................................... 2532
10-237. VPE_PERF_MON10
..................................................................................................
2532
10-238. Register Call Summary for Register VPE_PERF_MON10 ....................................................... 2533
10-239. VPE_PERF_MON11
..................................................................................................
2533
10-240. Register Call Summary for Register VPE_PERF_MON11 ....................................................... 2534
2535
10-242.
2536
10-243.
10-244.
10-245.
10-246.
10-247.
10-248.
10-249.
10-250.
10-251.
10-252.
10-253.
10-254.
10-255.
10-256.
10-257.
10-258.
10-259.
10-260.
10-261.
10-262.
10-263.
10-264.
10-265.
10-266.
10-267.
10-268.
10-269.
10-270.
10-271.
10-272.
10-273.
10-274.
10-275.
10-276.
158
..................................................................................................
Register Call Summary for Register VPE_PERF_MON12 .......................................................
VPE_PERF_MON13 ..................................................................................................
Register Call Summary for Register VPE_PERF_MON13 .......................................................
VPE_PERF_MON14 ..................................................................................................
Register Call Summary for Register VPE_PERF_MON14 .......................................................
VPE_PERF_MON15 ..................................................................................................
Register Call Summary for Register VPE_PERF_MON15 .......................................................
VPE_PERF_MON16 ..................................................................................................
Register Call Summary for Register VPE_PERF_MON16 .......................................................
VPE_PERF_MON17 ..................................................................................................
Register Call Summary for Register VPE_PERF_MON17 .......................................................
VPE_PERF_MON18 ..................................................................................................
Register Call Summary for Register VPE_PERF_MON18 .......................................................
VPE_PERF_MON19 ..................................................................................................
Register Call Summary for Register VPE_PERF_MON19 .......................................................
VPE_PERF_MON20 ..................................................................................................
Register Call Summary for Register VPE_PERF_MON20 .......................................................
VPE_PERF_MON21 ..................................................................................................
Register Call Summary for Register VPE_PERF_MON21 .......................................................
VPE_PERF_MON22 ..................................................................................................
Register Call Summary for Register VPE_PERF_MON22 .......................................................
VPE_PERF_MON23 ..................................................................................................
Register Call Summary for Register VPE_PERF_MON23 .......................................................
VPE_PERF_MON24 ..................................................................................................
Register Call Summary for Register VPE_PERF_MON24 .......................................................
VPE_PERF_MON25 ..................................................................................................
Register Call Summary for Register VPE_PERF_MON25 .......................................................
VPE_PERF_MON26 ..................................................................................................
Register Call Summary for Register VPE_PERF_MON26 .......................................................
VPE_PERF_MON27 ..................................................................................................
Register Call Summary for Register VPE_PERF_MON27 .......................................................
VPE_PERF_MON28 ..................................................................................................
Register Call Summary for Register VPE_PERF_MON28 .......................................................
VPE_PERF_MON29 ..................................................................................................
Register Call Summary for Register VPE_PERF_MON29 .......................................................
10-241. VPE_PERF_MON12
List of Tables
2536
2537
2537
2538
2539
2540
2540
2541
2541
2542
2543
2544
2544
2545
2545
2546
2547
2548
2548
2549
2549
2550
2551
2552
2552
2553
2553
2554
2555
2556
2556
2557
2557
2558
SPRUIC2D – January 2017 – Revised April 2019
Submit Documentation Feedback
Copyright © 2017–2019, Texas Instruments Incorporated
www.ti.com
..................................................................................................
Register Call Summary for Register VPE_PERF_MON30 .......................................................
VPE_PERF_MON31 ..................................................................................................
Register Call Summary for Register VPE_PERF_MON31 .......................................................
VPE_PERF_MON32 ..................................................................................................
Register Call Summary for Register VPE_PERF_MON32 .......................................................
VPE_PERF_MON33 ..................................................................................................
Register Call Summary for Register VPE_PERF_MON33 .......................................................
VPE_PERF_MON34 ..................................................................................................
Register Call Summary for Register VPE_PERF_MON34 .......................................................
VPE_PERF_MON35 ..................................................................................................
Register Call Summary for Register VPE_PERF_MON35 .......................................................
VPE_PERF_MON36 ..................................................................................................
Register Call Summary for Register VPE_PERF_MON36 .......................................................
VPE_PERF_MON37 ..................................................................................................
Register Call Summary for Register VPE_PERF_MON37 .......................................................
VPE_PERF_MON38 ..................................................................................................
Register Call Summary for Register VPE_PERF_MON38 .......................................................
VPE_PERF_MON39 ..................................................................................................
Register Call Summary for Register VPE_PERF_MON39 .......................................................
VPE_PERF_MON40 ..................................................................................................
Register Call Summary for Register VPE_PERF_MON40 .......................................................
VPE_PERF_MON41 ..................................................................................................
Register Call Summary for Register VPE_PERF_MON41 .......................................................
VPE_PERF_MON42 ..................................................................................................
Register Call Summary for Register VPE_PERF_MON42 .......................................................
VPE_PERF_MON43 ..................................................................................................
Register Call Summary for Register VPE_PERF_MON43 .......................................................
VPE_PERF_MON44 ..................................................................................................
Register Call Summary for Register VPE_PERF_MON44 .......................................................
VPE_PERF_MON45 ..................................................................................................
Register Call Summary for Register VPE_PERF_MON45 .......................................................
VPE_PERF_MON46 ..................................................................................................
Register Call Summary for Register VPE_PERF_MON46 .......................................................
VPE_PERF_MON47 ..................................................................................................
Register Call Summary for Register VPE_PERF_MON47 .......................................................
VPE_PERF_MON48 ..................................................................................................
Register Call Summary for Register VPE_PERF_MON48 .......................................................
VPE_PERF_MON49 ..................................................................................................
Register Call Summary for Register VPE_PERF_MON49 .......................................................
VPE_PERF_MON50 ..................................................................................................
Register Call Summary for Register VPE_PERF_MON50 .......................................................
VPE_PERF_MON51 ..................................................................................................
Register Call Summary for Register VPE_PERF_MON51 .......................................................
VPE_PERF_MON52 ..................................................................................................
Register Call Summary for Register VPE_PERF_MON52 .......................................................
VPE_PRI_CHROMA_CSTAT ........................................................................................
Register Call Summary for Register VPE_PRI_CHROMA_CSTAT .............................................
VPE_PRI_LUMA_CSTAT .............................................................................................
10-277. VPE_PERF_MON30
2559
10-278.
2560
10-279.
10-280.
10-281.
10-282.
10-283.
10-284.
10-285.
10-286.
10-287.
10-288.
10-289.
10-290.
10-291.
10-292.
10-293.
10-294.
10-295.
10-296.
10-297.
10-298.
10-299.
10-300.
10-301.
10-302.
10-303.
10-304.
10-305.
10-306.
10-307.
10-308.
10-309.
10-310.
10-311.
10-312.
10-313.
10-314.
10-315.
10-316.
10-317.
10-318.
10-319.
10-320.
10-321.
10-322.
10-323.
10-324.
10-325.
SPRUIC2D – January 2017 – Revised April 2019
Submit Documentation Feedback
Copyright © 2017–2019, Texas Instruments Incorporated
List of Tables
2560
2561
2561
2562
2563
2564
2564
2565
2565
2566
2567
2568
2568
2569
2569
2570
2571
2572
2572
2573
2573
2574
2574
2575
2575
2576
2577
2578
2578
2579
2579
2580
2580
2581
2581
2582
2583
2584
2584
2585
2585
2586
2586
2587
2588
2589
2589
159
www.ti.com
10-326. Register Call Summary for Register VPE_PRI_LUMA_CSTAT ................................................. 2590
10-327. VPE_PRI_FLD1_LUMA_CSTAT..................................................................................... 2590
10-328. Register Call Summary for Register VPE_PRI_FLD1_LUMA_CSTAT ......................................... 2590
10-329. VPE_PRI_FLD1_CHROMA_CSTAT ................................................................................ 2591
10-330. Register Call Summary for Register VPE_PRI_FLD1_CHROMA_CSTAT ..................................... 2592
10-331. VPE_PRI_FLD2_LUMA_CSTAT..................................................................................... 2592
10-332. Register Call Summary for Register VPE_PRI_FLD2_LUMA_CSTAT ......................................... 2593
10-333. VPE_PRI_FLD2_CHROMA_CSTAT ................................................................................ 2593
10-334. Register Call Summary for Register VPE_PRI_FLD2_CHROMA_CSTAT ..................................... 2594
10-335. VPE_PRI_MV0_CSTAT ............................................................................................... 2595
10-336. Register Call Summary for Register VPE_PRI_MV0_CSTAT ................................................... 2595
10-337. VPE_PRI_MV_OUT_CSTAT ......................................................................................... 2595
10-338. Register Call Summary for Register VPE_PRI_MV_OUT_CSTAT
.............................................
2596
10-339. VPE_VIP0_UP_Y_CSTAT ............................................................................................ 2596
10-340. Register Call Summary for Register VPE_VIP0_UP_Y_CSTAT ................................................ 2597
10-341. VPE_VIP0_UP_UV_CSTAT .......................................................................................... 2597
10-342. Register Call Summary for Register VPE_VIP0_UP_UV_CSTAT .............................................. 2598
10-343. VPE_VPI_CTL_CSTAT ............................................................................................... 2598
10-344. Register Call Summary for Register VPE_VPI_CTL_CSTAT .................................................... 2599
10-345. VPE Registers Mapping Summary .................................................................................. 2599
10-346. VPE_CLKC_PID ....................................................................................................... 2600
10-347. Register Call Summary for Register VPE_CLKC_PID ............................................................ 2600
10-348. VPE_SYSCONFIG ..................................................................................................... 2600
10-349. Register Call Summary for Register VPE_SYSCONFIG ......................................................... 2601
10-350. VPE_INTC_INTR0_STATUS_RAW0
...............................................................................
2601
10-351. Register Call Summary for Register VPE_INTC_INTR0_STATUS_RAW0 .................................... 2603
10-352. VPE_INTC_INTR0_STATUS_RAW1
...............................................................................
2603
10-353. Register Call Summary for Register VPE_INTC_INTR0_STATUS_RAW1 .................................... 2604
10-354. VPE_INTC_INTR0_STATUS_ENA0 ................................................................................ 2604
10-355. Register Call Summary for Register VPE_INTC_INTR0_STATUS_ENA0 ..................................... 2606
10-356. VPE_INTC_INTR0_STATUS_ENA1 ................................................................................ 2606
10-357. Register Call Summary for Register VPE_INTC_INTR0_STATUS_ENA1 ..................................... 2607
10-358. VPE_INTC_INTR0_ENA_SET0 ...................................................................................... 2607
10-359. Register Call Summary for Register VPE_INTC_INTR0_ENA_SET0 .......................................... 2608
10-360. VPE_INTC_INTR0_ENA_SET1 ...................................................................................... 2609
10-361. Register Call Summary for Register VPE_INTC_INTR0_ENA_SET1 .......................................... 2610
10-362. VPE_INTC_INTR0_ENA_CLR0
.....................................................................................
2610
10-363. Register Call Summary for Register VPE_INTC_INTR0_ENA_CLR0 .......................................... 2611
2612
10-365.
2613
10-366.
10-367.
10-368.
10-369.
10-370.
10-371.
10-372.
10-373.
10-374.
160
.....................................................................................
Register Call Summary for Register VPE_INTC_INTR0_ENA_CLR1 ..........................................
VPE_INTC_EOI ........................................................................................................
Register Call Summary for Register VPE_INTC_EOI.............................................................
VPE_CLKC_CLKEN ...................................................................................................
Register Call Summary for Register VPE_CLKC_CLKEN .......................................................
VPE_CLKC_RST ......................................................................................................
Register Call Summary for Register VPE_CLKC_RST ...........................................................
VPE_CLKC_DPS ......................................................................................................
Register Call Summary for Register VPE_CLKC_DPS ...........................................................
VPE_RANGE_MAP....................................................................................................
10-364. VPE_INTC_INTR0_ENA_CLR1
List of Tables
2613
2613
2613
2614
2614
2614
2614
2616
2616
SPRUIC2D – January 2017 – Revised April 2019
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10-375. Register Call Summary for Register VPE_RANGE_MAP ........................................................ 2616
..............................................................
11-1.
Display Subsystem DPI1 Interface Signals Mapping
11-2.
Display Subsystem DPI2 Interface Signals Mapping ............................................................... 2621
11-3.
Display Subsystem DPI3 Interface Signals Mapping
11-4.
11-5.
11-6.
11-7.
11-8.
11-9.
11-10.
11-11.
11-12.
11-13.
11-14.
11-15.
11-16.
11-17.
11-18.
11-19.
11-20.
11-21.
11-22.
11-23.
11-24.
11-25.
11-26.
11-27.
11-28.
11-29.
11-30.
11-31.
11-32.
11-33.
11-34.
11-35.
11-36.
11-37.
11-38.
11-39.
11-40.
11-41.
11-42.
11-43.
11-44.
11-45.
11-46.
11-47.
11-48.
..............................................................
Display Subsystem TV Parallel Interface Signals Mapping........................................................
Display Subsystem Hardware Requests .............................................................................
Display Subsystem Clocks .............................................................................................
Display Subsystem Modules Clock Sources.........................................................................
Display Subsystem Resets.............................................................................................
Display Subsystem Power Domains ..................................................................................
VIDEO PLL Operation Modes When Not Locked ...................................................................
DPLL_VIDEO Recommended Programming Values ...............................................................
DPLL_HDMI Operation Modes When Not Locked ..................................................................
DPLL_HDMI Register Call Summary for HDMI PLL Programming Sequence ..................................
DPLL_HDMI Recommended Programming Values ................................................................
DSS Initialization Sequence ...........................................................................................
Display Subsystem Instance Summary ..............................................................................
DSS Registers Mapping Summary....................................................................................
DSS_REVISION .........................................................................................................
Register Call Summary for Register DSS_REVISION .............................................................
DSS_SYSSTATUS ......................................................................................................
Register Call Summary for Register DSS_SYSSTATUS ..........................................................
DSS_CTRL ...............................................................................................................
Register Call Summary for Register DSS_CTRL ...................................................................
DSS_STATUS ...........................................................................................................
Register Call Summary for Register DSS_STATUS ................................................................
OCP2SCP2 Registers Mapping Summary ...........................................................................
OCP2SCP_REVISION .................................................................................................
Register Call Summary for Register OCP2SCP_REVISION ......................................................
OCP2SCP_SYSCONFIG ..............................................................................................
Register Call Summary for Register OCP2SCP_SYSCONFIG ...................................................
OCP2SCP_SYSSTATUS ..............................................................................................
Register Call Summary for Register OCP2SCP_SYSSTATUS ...................................................
OCP2SCP_TIMING .....................................................................................................
Register Call Summary for Register OCP2SCP_TIMING .........................................................
DPLL_VIDEO1 Registers Mapping Summary ......................................................................
PLL_CONTROL .........................................................................................................
Register Call Summary for Register PLL_CONTROL ..............................................................
PLL_STATUS ............................................................................................................
Register Call Summary for Register PLL_STATUS ................................................................
PLL_GO ..................................................................................................................
Register Call Summary for Register PLL_GO .......................................................................
PLL_CONFIGURATION1 ..............................................................................................
Register Call Summary for Register PLL_CONFIGURATION1 ...................................................
PLL_CONFIGURATION2 ..............................................................................................
Register Call Summary for Register PLL_CONFIGURATION2 ...................................................
PLL_CONFIGURATION3 ..............................................................................................
Register Call Summary for Register PLL_CONFIGURATION3 ...................................................
PLL_SSC_CONFIGURATION1 .......................................................................................
SPRUIC2D – January 2017 – Revised April 2019
Submit Documentation Feedback
Copyright © 2017–2019, Texas Instruments Incorporated
List of Tables
2621
2621
2622
2623
2625
2625
2626
2627
2633
2637
2640
2643
2645
2646
2647
2647
2647
2647
2648
2648
2648
2649
2649
2650
2651
2651
2651
2651
2652
2652
2652
2653
2653
2653
2654
2654
2655
2656
2656
2657
2657
2658
2658
2659
2660
2660
2660
161
www.ti.com
11-49. Register Call Summary for Register PLL_SSC_CONFIGURATION1 ............................................ 2660
11-50. PLL_SSC_CONFIGURATION2 ....................................................................................... 2661
11-51. Register Call Summary for Register PLL_SSC_CONFIGURATION2 ............................................ 2661
..............................................................................................
Register Call Summary for Register PLL_CONFIGURATION4 ...................................................
DPLL_HDMI Registers Mapping Summary ..........................................................................
PLLCTRL_HDMI_CONTROL ..........................................................................................
Register Call Summary for Register PLLCTRL_HDMI_CONTROL ..............................................
PLLCTRL_HDMI_STATUS ............................................................................................
Register Call Summary for Register PLLCTRL_HDMI_STATUS .................................................
PLLCTRL_HDMI_GO ...................................................................................................
Register Call Summary for Register PLLCTRL_HDMI_GO .......................................................
PLLCTRL_HDMI_CONFIGURATION1 ...............................................................................
Register Call Summary for Register PLLCTRL_HDMI_CONFIGURATION1 ...................................
PLLCTRL_HDMI_CONFIGURATION2 ...............................................................................
Register Call Summary for Register PLLCTRL_HDMI_CONFIGURATION2 ...................................
PLLCTRL_HDMI_CONFIGURATION3 ...............................................................................
Register Call Summary for Register PLLCTRL_HDMI_CONFIGURATION3 ...................................
PLLCTRL_HDMI_SSC_CONFIGURATION1 ........................................................................
Register Call Summary for Register PLLCTRL_HDMI_SSC_CONFIGURATION1 ............................
PLLCTRL_HDMI_SSC_CONFIGURATION2 ........................................................................
Register Call Summary for Register PLLCTRL_HDMI_SSC_CONFIGURATION2 ............................
PLLCTRL_HDMI_CONFIGURATION4 ...............................................................................
Register Call Summary for Register PLLCTRL_HDMI_CONFIGURATION4 ...................................
HDMI_WP Registers Mapping Summary ............................................................................
HDMI_WP_PWR_CTRL ................................................................................................
Register Call Summary for Register HDMI_WP_PWR_CTRL ....................................................
HDMI_WP_CLK .........................................................................................................
Register Call Summary for Register HDMI_WP_CLK ..............................................................
DSI1_A Registers Mapping Summary ................................................................................
DSI_CLK_CTRL .........................................................................................................
Register Call Summary for Register DSI_CLK_CTRL..............................................................
DISPC Parallel Interface Signals ......................................................................................
DSS Output Data Signals to RGB Color Components Mapping ..................................................
DISPC Programmable Fields in Bypass Mode ......................................................................
DISPC Integration Attributes ...........................................................................................
DISPC Clocks and Resets .............................................................................................
DISPC Hardware Requests ............................................................................................
DISPC Interrupts ........................................................................................................
DISPC DMA Buffer Size ................................................................................................
DISPC Register Settings for Accessing Image in Internal Memory ..............................................
DISPC Register Settings for Rotation Using TILER ................................................................
DISPC Rotation Mode Definition ......................................................................................
DISPC Rotation Orientation Definition ................................................................................
DISPC Memory Formats Supported ..................................................................................
DISPC Replication Enabled: RGB Pixel Formats Remapping Into ARGB40-10.10.10.10 ....................
DISPC Replication Disabled: RGB Pixel Formats Remapping Into ARGB40-10.10.10.10 ....................
DISPC Replication Enabled: RGB Pixel Formats Remapping Into ARGB32-8888 .............................
DISPC Replication Disabled: RGB Pixel Formats Remapping Into ARGB32-8888 ............................
11-52. PLL_CONFIGURATION4
11-53.
11-54.
11-55.
11-56.
11-57.
11-58.
11-59.
11-60.
11-61.
11-62.
11-63.
11-64.
11-65.
11-66.
11-67.
11-68.
11-69.
11-70.
11-71.
11-72.
11-73.
11-74.
11-75.
11-76.
11-77.
11-78.
11-79.
11-80.
11-81.
11-82.
11-83.
11-84.
11-85.
11-86.
11-87.
11-88.
11-89.
11-90.
11-91.
11-92.
11-93.
11-94.
11-95.
11-96.
11-97.
162
List of Tables
2661
2662
2662
2662
2663
2663
2664
2664
2664
2665
2665
2665
2667
2667
2667
2668
2668
2668
2669
2669
2669
2669
2670
2671
2671
2672
2672
2672
2673
2679
2682
2683
2688
2689
2689
2694
2696
2697
2705
2706
2706
2707
2710
2710
2713
2713
SPRUIC2D – January 2017 – Revised April 2019
Submit Documentation Feedback
Copyright © 2017–2019, Texas Instruments Incorporated
www.ti.com
..................................................
11-99. DISPC Line Buffer Width for Scaler Unit .............................................................................
11-100. DISPC Register Bit Field Associated to Coefficient for ARGB and Y Configuration in VIDp Scaler ........
11-101. DISPC Register Bit Field Associated to Coefficient for Cb and Cr Configuration in VIDp Scaler ...........
11-102. DISPC Vertical and Horizontal Accumulator Phase ...............................................................
11-103. DISPC Pixel Clock Frequency Limitations (Any Pixel Format) – Active Matrix Display ......................
11-104. DISPC CSC RGB to YUV Bit Field Setting .........................................................................
11-105. DISPC Register Bit Field Associated With Coefficient for ARGB and Y Configuration in WB Scaler ......
11-106. DISPC Register