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Texas Instruments DRA79x EVM CPU board user's (Rev. B) User guides
User's Guide
SPRUIF3B – May 2017 – Revised March 2019
DRA79x EVM CPU board
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Contents
Introduction ................................................................................................................... 2
Overview ...................................................................................................................... 3
Hardware...................................................................................................................... 8
Signal Multiplex Logic...................................................................................................... 22
USB3 Supported Configurations ......................................................................................... 30
References .................................................................................................................. 34
List of Figures
1
DRA71x, DRA79x, TDA2Ex-17, and AM570x CPU Board (Front and Back Views) ................................ 3
2
CPU Board – Front .......................................................................................................... 6
3
CPU Board – Back
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.......................................................................................................... 7
CPU Board Block Diagram ................................................................................................. 8
SoC Block Diagram.......................................................................................................... 9
Power Distribution Block Diagram ....................................................................................... 10
Reset Structure ............................................................................................................. 11
SoC Pinmux for GPMC and QSPI ...................................................................................... 23
MUX Diagram for GPMC and QSPI ..................................................................................... 23
SoC Pinmux for GPMC, VIN1, and VOUT3 ............................................................................ 24
MUX Diagram for GPMC, VIN1, and VOUT3 .......................................................................... 25
SoC Pinmux for GPMC and EMMC ..................................................................................... 25
MUX Diagram for GPMC and EMMC ................................................................................... 26
SoC Pinmux for VIN2A and EMU ....................................................................................... 26
MUX Diagram for VIN2A and EMU ...................................................................................... 27
SoC Pinmux for VIN2A and RGMII1 .................................................................................... 27
MUX Diagram for VIN2A and RGMII1 ................................................................................... 28
SoC Pinmux for RGMII0 and VIN1B .................................................................................... 28
MUX Diagram for RGMII0 and VIN1B ................................................................................... 29
SoC Pinmux for SPI2 and UART3 ...................................................................................... 29
MUX Diagram for SPI2 and UART3 ..................................................................................... 29
SoC Pinmux for DCAN2 ................................................................................................... 30
MUX Diagram for DCAN2 and I2C ...................................................................................... 30
Qualtek 3023009-01M USB 3.0 Micro-AB to Standard-B 1m (3.28’) ............................................... 31
SIIG JU-H40312-S14-Port USB 3.0 Super Speed USB Hub ......................................................... 31
Qualtek 3023007-01M USB 3.0 Micro-A to Micro-B 1m (3.28') ..................................................... 32
IOGEAR GUH374 4-Port USB 3.0 HUB ................................................................................ 32
Qualtek 3023005-01M USB 3.0 Standard-A to Micro-B 1m (3.28') ................................................. 33
List of Tables
1
SoC EVMs and Kits ......................................................................................................... 4
2
EVM Accessories ............................................................................................................ 4
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Introduction
www.ti.com
3
EVM Kit Truth Table ......................................................................................................... 4
4
12 V, 5A, 65W Compatible Wall Supplies
5
Reset Signals Structure ................................................................................................... 11
6
SoC Boot Mode Switch Settings ......................................................................................... 13
7
Board Controls for Memory Booting Options ........................................................................... 14
8
User LEDs................................................................................................................... 17
9
Power Monitor Mapping ................................................................................................... 17
10
I2C Device Address Chart ................................................................................................. 18
11
SoC GPIO Map ............................................................................................................. 18
12
I/O Expander Map .......................................................................................................... 19
13
Configuration EEPROM ................................................................................................... 21
14
Onboard MUX Setting and Control
..............................................................................
......................................................................................
11
22
Trademarks
ARM, Cortex are registered trademarks of ARM Limited.
IOGEAR is a registered trademark of ATEN INTERNATIONAL Co., Ltd.
Bluetooth is a registered trademark of Bluetooth SIG.
HDMI is a registered trademark of HDMI Licensing Administrator, Inc.
POWERVR is a trademark of Imagination Technologies Ltd.
MIPI is a trademark of MIPI Alliance.
Micron is a registered trademark of Micron Technology, Inc.
Molex is a registered trademark of Molex, Inc.
SIIG is a registered trademark of SIIG, Inc.
Samtec is a trademark of Samtec Inc.
Spansion is a trademark of Spansion Inc.
Wi-Fi is a registered trademark of Wi-Fi Alliance.
1
Introduction
•
•
•
•
•
ARM® Cortex®-A15 core
Two ARM Cortex®-M4 processing subsystems
C66x digital signal processor (DSP)
2D- and 3D-graphics processing units including the POWERVR™ SGX544 from Imagination
Technologies
High-definition image and video accelerator
The DRA79x evaluation module (EVM) is an evaluation platform designed to speed up development
efforts and reduce time to market for applications such as infotainment, reconfigurable digital cluster or
integrated digital cockpit. To allow scalability and reuse across DRA79x Jacinto Infotainment SoCs, the
EVM is based on the Jacinto 6 Entry DRA718 SoC, which incorporates a heterogeneous, scalable
architecture that includes a mixture of the following:
• ARM® Cortex®-A15 core
• Two ARM Cortex®-M4 processing subsystems
• C66x digital signal processor (DSP)
• 2D- and 3D-graphics processing units including the POWERVR™ SGX544 from Imagination
Technologies
• High-definition image and video accelerator
The EVM also integrates a host of peripherals including multicamera interfaces (both parallel and serial)
for LVDS-based surround view systems, displays, CAN, and Gigabit Ethernet audio video bridging (AVB).
The main CPU board integrates these key peripherals such as Ethernet or high-definition multimedia
interface (HDMI®), while the infotainment application daughter board (JAMR3) and LCD/TS daughter
board will complement the CPU board to deliver complete system to jump start your evaluation and
application development.
2
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Overview
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2
Overview
An EVM system is comprised of a CPU board with one or more application boards. The CPU board (see
Figure 1) can be used as a stand-alone for software debug and development. Each EVM system is
designed to let customers evaluate the processor performance and flexibility in the following targeted
markets:
• Automotive, radio sound processor (RSP), display audio, gateway, and infotainment applications
• Automotive, ADAS applications
The CPU board contains the DRA71x, DRA79x, TDA2Ex-17, and AM570x (superset part) applications
processor, a companion power solution (LP8733 and LP8732), DDR3 DRAM, several types of flash
memories (QSPI, eMMC, NAND, and NOR), and interface ports and expansion connectors. The board
provides additional support components that provide software debugging, signal routing, and configuration
controls that are not needed in a final product. Different versions of the CPU boards will be built to support
the development process that includes the following:
• Socketed processor for wakeup, early software development, and quick and easy chip revision
evaluation
• Soldered-down processor for high-performance use cases and evaluations
All other onboard components are soldered-down.
Figure 1. DRA71x, DRA79x, TDA2Ex-17, and AM570x CPU Board (Front and Back Views)
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Overview
2.1
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EVM System Configurations
Table 1 lists the SoC EVMs and kits.
Table 1. SoC EVMs and Kits
Systems
Description
Model Number
DRA71x, DRA79x, TDA2E-17, and AM570x
socketed CPU board (GP)
Socketed - CPU board ES2.0 GP (CPU board)
EVMX777BG-01-00-S0
DRA71x, DRA79x, TDA2Ex-17, and AM570x Soldered - CPU board ES2.0 GP (CPU board)
CPU board (GP)
EVMX777BG-01-00-00
DRA71x, DRA79x, TDA2Ex-17, and AM570x Soldered - CPU board ES2.0 HS (CPU board)
CPU board (HS)
EVMX777BH-01-00-00
DRA71x and DRA79x
Infotainment EVM kit
Soldered - CPU board ES2.0 GP (CPU board) with:
EVMX777G-01-20-00
• JAMR3 Tuner Apps board
• 10.1-inch, 1280 × 800 LCD/TS board
TDA2Ex-17 Vision EVM kit
Soldered - CPU board ES2.0 GP (CPU board):
with Vision Apps board
EVMX777G-01-40-00
DRA71x, DRA79x, TDA2Ex-17, and AM570x Soldered - CPU board ES2.0 GP (CPU board):
CPU EVM kit
with 10.1-inch, 1280 × 800 LCD/TS board
EVMX777G-01-00-00
Table 2 lists the EVM accessories
Table 2. EVM Accessories
Accessories
Description
Model Number
JAMR3 Tuner Application Board
Head-unit DIN form-factor Application Board with
radio tuners, multiple audio I/Os, and video input
extendibility
EVM5777JAMR3-V1-0
Vision Application Board
Support for multiple camera inputs for surround
view, stereo vision, and proprietary camera board
interfaces
EVMX777VISION-V2-0
10.1-inch, 1280 × 800, Display/Multitouch
Touchscreen
10.1-inch, 1280 × 800, LCD (24-bit color), with
Multitouch Touchscreen
EVMX777LCDTS-V1-0
Table 3 lists the EVM kit truth table.
Table 3. EVM Kit Truth Table
EVM or Kit Name
CPU
Board
JAMR3
App Board
Vision
App Board
LCD/TS
Daughter Board
Power Supply
Adapter
(2.1 to 2.5 mm)
DRA71x, DRA79x, TDA2E-17,
AM570x Socketed CPU board
(GP)
X
X
DRA71x, DRA79x, TDA2E-17,
AM570x CPU board (GP)
X
X
DRA71x, DRA79x, TDA2E-17,
AM570x CPU board (HS)
X
X
DRA71x and DRA79x
Infotainment EVM kit
X
TDA2E-17 Vision EVM kit
X
DRA71x, DRA79x, TDA2E-17,
and AM570x EVM kit
X
4
X
X
X
X
X
X
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2.2
CPU Board Feature List
•
•
•
•
•
•
•
•
•
Processor
– DRA71x, DRA79x, TDA2E-17, and AM570x (superset SoC) (17-mm × 17-mm package, 0.65-mm
pitch, with 25 × 25 via-channel array)
– Support for corresponding socket
Power supply
– 12-V DC input
– Optimized power management solution
– Compliant with SoC power sequencing requirements
– Integrated power measurement
PCB
– Dimension (W × D) 170 mm × 170 mm
– 100% PTH technology
Memory
– DRAM (DDR3L-1333 with ECC):
• 2GB (four 4Gb × 8 + one 4Gb × 8 ECC)
– Quad SPI flash: 256Mb
– EMMC flash: 8Gb (v.4.51 compliant)
– NAND flash: 2Gb
– NOR flash: 512Mb
– I2C EEPROM, 32Kb
– MicroSD card cage
Boot mode selection DIP switch
Digital temperature sensor (TMP102)
JTAG/Emulator:
– 60-pin MIPI™-60 JTAG/Trace connector
– Adapter for 20-pin CTI header: 10 × 2, 1.27-mm pitch
Supported interfaces and peripherals:
– CAN Interface – 2-wire PHY on DCAN1
– Two USB host receptacles – one USB 3.0 (micro-USB) and one USB 2.0 (mini-USB)
– Audio codec (AIC3106) with headphone out, line out, line in, and microphone in
– Three Video outputs (HDMI, FPD-Link III, LCD)
– Camera sensors support using the Leopard Imaging Module interface
– PCIe
– MLB and MLBP on the MICTOR connector
– RS-232 using the USB FTDI converter (mini-A/B USB)
– COM8 module interface for Bluetooth® and WLAN support
– Two RJ45 Gigabit Ethernet (DP83867)
– I2C GPIO expander
Expansion connectors to support application-specific boards.
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CPU Board Component Identification
Figure 2 shows the front of the board and Figure 3 shows the back.
CAN
USB2.0
RJ45 Gb ENET
Port 0
FPDLink III USART/
Transmitter Terminal
Pwr
Pwr Input
Toggle
Port 1
USB ID
Dip SW
MOST
Audio
Local Bus
LI Camera
Parallel
Ethernet
PCIe
SYSBOOT Dip Sw
HDMI
Display
Pwr LED
USB3.0
QSPI
Power ICs
WLAN/
Bluetooth
Module
(COM8Q)
Wake
Processor
Board Config Dip Sw
Reset Buttons
CSI2 DB
Power
Measurement
Usr LEDs
DDR3L Memory
MIPI-60
JTAG
Mic
L-IN
L-OUT
HP
Audio Jacks
Figure 2. CPU Board – Front
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Test Interface
Expansion Interface
LCD Panel
MicroSD
LI Camera
Serial
Figure 3. CPU Board – Back
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Hardware
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3
Hardware
3.1
Hardware Architecture
HP_OUT
McASP3
20MHz
22.5792MHz
AUXOSC
QSPI1
USB1
USB3.0
USB2
USB2.0
CONN1
VIN1B
CONN2
VIN2B
ePCI1
CONN3
Gbit PHY
RGMII1
Gbit PHY
DCAN2
DS90UH925Q
VOUT2
SATA
SATA
VOUT3
McASP2
SoC
GPMC
NOR FLASH
SYSBOOT SW
VIN1A
I2C2
SPI1
I2C1
M
U
X
UART3
McASP7
McASP6
MMC4
GPMC_CL
K
LCD/TS DB
COM8 DB
I2C1
SPI1
ID EEPROM
I2C1
I2C1
TEMP.SENSOR
GPIO EXP
DCAN2
NAND FLASH
MLB / MLBP
I2C 1/3/5
8-bit
LI CAMERA
HDMI
MLB/MLBP
MMC3
Mini-PCIe
HDMI
SPI2
eMMC
RGMII0
UART1
FT232R
DCAN1
CAN PHY
USB min AB
RGMII1
GPMC
Header
Header
MMC2
VOUT2
JTAG
Power
Balls
MIPI-60
CSI2-1
CSI2-0
Power
Measurement
Daughter
Card
CLK P/N
VIN2A
RGMII0
microSD Socket
MMC1
VIN1A
QSPI1
BUS LOGIC SWITCH FOR MUX /DEMUX
FPDLINK III
HEADER RJ45
RJ45
Expansion Connectors
QSPI FLASH
4-bit
McASP3
1.8V SHIFTER
LINE_OUT
AIC3106
MIC_IN
LINE_IN
DEVOSC
EMIF1
4Gb(x8)
4Gb(x8)
4Gb(x8)
4Gb(x8)
4Gb(x8) ECC
Figure 4 shows the functional block diagram of the CPU board.
I2C2
SPI1
LI Camera /
CSI2 DB
I2C-PMDC
Current
PWR, GND Monitoring
Circuits
Power Supplies
12V Conn
Figure 4. CPU Board Block Diagram
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3.2
DRA71x, DRA79x, TDA2E-17, and AM570x Processor
The processor is a highly integrated, programmable, SoC, silicon solution. Figure 5 shows the SoC block
diagram.
SOC
Figure 5. SoC Block Diagram
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3.3
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Power Architecture
Figure 6 shows the power distribution system of the EVM. The power-management solution is created
from four total devices (see Figure 6). A step-down 12 V to 3.3 V, 5-V converter provides the primary 3v3
and 5v0 power rails for the rest of the system. The LP8733 and LP8732 devices are optimized for the SoC
power needs and sequence requirements. A sink/source regulator provides the DDR termination.
vdd_dsp
12V Input
(Typical)
2st Stage Power
vdd_iva
LP8733-Q1
LM5140-Q1
5V0
Buck2
2.8 < Vin < 5.5V
3.8 < Vin < 65V
5V, 8V, 1.5 < Vo < 15V
@ ?.?A max
EN2
0.73 < Vo < 1.4V
@ 3.0A max
Vsteps = 5mV
LP8733-Q1
PG2
LM5140-Q1
Buck2
2.8 < Vin < 5.5V
vdd_mpu
VDD_DSP
1V06
VDD_DSP
VDD_IVAHD
Buck1
0.73 < Vo < 1.4V
@ 3.0A max
Vsteps = 5mV
VDD
1V15
VDD_MPU
3V3
Buck1
VDD_GPU
3.8 < Vin < 65V
VDD_CORE
3.3V, 5V, 1.5 < Vo < 15V
@ ?.?A max
EN1
vdd_gpu
vdd
CORE SUPPLIES
1st Stage Power
vdd_rtc
vdds_mlbp
vdds18v
vdds18v_ddr1
vdda_rtc
PG1
VDD_RTC
vdda_per
vdda_ddr
vdda_debug
LP8732-Q1
VDD_1V8
VSYS_PWRGOOD
EVM Specific
Power Up/Down Logic
J6SYS_SHUTDN
CPU I/O
2.8 < Vin < 5.5V
J6PWR_ENABLE
1V8
0.73 < Vo < 3.3V
@ 0.3A max
Vdo = 0.2V @ Iomax
1V8
2.5 < Vin < 5.5V
J6PWR_PORz
CPU I/O
0.8 < Vo < 3.3V
@ 0.3A max
Vdo = 0.2V @ Iomax
LP8733-Q1
J6PWR_PWRGOOD
DDR_PORz
DDR I/O
2.5 < Vin < 5.5V
(Optional)
LP8732-Q1
Control
2.5 < Vin < 5.5V
(Optional)
INTn
vdda_usb2
3V3/1V8
Optional for BOOT
TPS51200-Q1
VDDSHV8 (SDIO)
vdda_hdmi
VDDSHV11 (EMMC)
vdda_pcie0
vdda_pcie
(3v3 Optional based
on configuration)
LDO2
3V3
VDDA_USB3V3
DDR_REF
CLK/GPO2
PGOOD
LP8732-Q1
2.8 < Vin < 5.5V
Control
Buck2
0.73 < Vo < 1.4V
@ 1.5A max
Vsteps = 5mV
1V35
DDR Load Switch
TPS22965-Q1
Resistor
Divider
VDD_DDR
EN
LP8733-Q1
vdds_ddr1
Dual Voltage IO Rails (3v3)
x
INTn
CLK/GPO2
PORz Hold Function
TOP LEVEL
Second Stage Power
0V67
TPS51200-Q1
Sink/Source
2.3 < Vin < 3.5V
2.3 < REFIn < 3.5V
0V67
0.5 < Vo < 1.8V
@ 3A max
0.5 < REFo < 1.8V
@ 40mA max
VREF
VTT
Processor
x
OTP ID = 0x20
I2C: 0x61
LP8733-Q1
OTP ID = 0x2D
I2C: 0x60
1V8
x
LP8732-Q1
vddshv5
vddshv1
VDD/ VDDQ
SOC
x
3V3
TPS51200-Q1
x
EVM SYSTEM
GPO1
EN
LM5140-Q1
vdda33v_usb2
VDDSHVx
3V3
Control
PGOOD
First Stage Power
vddshv8
vdda33v_usb1
ddr1_vref0
VDDSHV Load Switch
TPS22965-Q1
DDR
CPU I/O
vdda_csi
vdda_sata
vdda_usb3
VDDSHV5 (RTC)
PGOOD
vdda_mpu_abe
vdda_usb1
LDO1
0.8 < Vo < 3.3V
@ 0.3A max
Vdo = 0.2V @ Iomax
vdda_video
vdda_osc
VDDA_1V8 (PHYs)
GPO1
EN
vdda_gpu
vdda_dsp_iva
Dual Voltage LDO
TPS74801
0.8 < Vo < 3.3V
@ 0.3A max
Vdo = 0.2V @ Iomax
LP8733-Q1
CPU I/O
VDDA_1V8 (PLLs)
vdda_gmac_core
LDO2
LP8732-Q1
EVM Specific
Reset Logic
VDDA_RTC
LDO1
LP8732-Q1
vdda_pllspare
SOC
0.73 < Vo < 1.4V
@ 1.5A max
Vsteps = 5mV
1V8
1.8V SUPPLIES
2.8 < Vin < 5.5V
Buck1
OTHER SUPPLIES
External Control/MCU
vddshv10
vddshv2
vddshv3
vddshv4
vddshv6
vddshv7
vddshv9
5V0
Figure 6. Power Distribution Block Diagram
An external power supply is required to power the EVM, but is not included as part of the EVM kit. The
external power supply requirements follow:
• Power jack: 2.5-mm ID, 5.5-mm OD
• Nom voltage: 12 VDC
• Maximum current: 5000 mA
• Efficiency level V
External power supply regulatory compliance certifications: recommended selection and use of an external
power supply which meets TI’s minimum electrical ratings requirement and complies with applicable
regional product regulatory and safety certification requirements, such as UL, CSA, VDE, CCC, and PSE.
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Table 4 lists the recommended and tested power supplies that can be used with the EVM.
Table 4. 12 V, 5A, 65W Compatible Wall Supplies
Manufacturer Part
Number
Digi-Key Part Number
Manufacturer
Output Connector
Notes
Required adapter,
provided in the EVM kits
102-3417-ND
SDI65--12-U-P5
CUI Inc.
Barrel plug,
2.1 mm x 5.5 mm
O.D. x 9.5 mm
62-1221-ND
KTPS65-1250DT-3PVI-C-P1
Volgen America/Kaga
Electronics USA
Barrel plug,
2.1 mm x 5.5 mm
O.D. x 9.5 mm
Required adapter,
provided in the EVM kits
102-3419-ND
SDI65-12-UD-P6
CUI Inc.
Barrel plug,
2.1 mm x 5.5 mm
O.D. x 9.5 mm
Required adapter,
provided in the EVM kits
SDI65-12-U-P6
CUI Inc.
Barrel plug,
2.1 mm x 5.5 mm
O.D. x 9.5 mm
SDI65-12-UD-P6
CUI Inc.
Barrel plug,
2.1 mm x 5.5 mm
O.D. x 9.5 mm
SDI65-12-U-P6-ND
SDI65-12-UD-P6-ND
3.4
Reset Structure
Figure 7 shows the reset structure. The power-on reset timing is primarily controlled from the system
power ICs (LP8733 and LP8732). Two push-buttons are provided for user-controlled resets. One button is
the power on reset (SW4) for a complete SoC reset. The other button is for a warm reset (SW5). The
warm reset can also be sourced from the MIPI-60 JTAG/Trace connector.
EMU_RSTn
RESETN
(Warm Reset)
CPU_RESETn
CPU_POR_RESETn
PCI_PORz
PMIC_RESET_IN
PORz
(Cold Reset)
PMIC_RESET_OUT
PMIC
RTC_PORZ
PMIC_RESWARMN
RSTOUT
System
RSTOUTn
Figure 7. Reset Structure
Table 5 summarizes the reset signals.
Table 5. Reset Signals Structure
Reset Type
Power-On Reset (PORn)
(as whole system reset)
Warm Reset
Reset Signal Sources
Comments
CPU_POR_RESETn
PORn reset push-button
PCI_PORz
PCIe inbound reset
PMIC_RESET_OUT
Power on reset from power ICs
CPU_RESETn
Warm reset push-button
EMU_RSTn
Reset from Emulator
PMIC Power-On Reset
PMIC_RESET_IN
PMIC reset input
Processor Reset Out
RSTOUTn
Reset output from processor to system,
PMIC (warm reset input)
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Clocks
The SoC supports up to two primary clock inputs. The device clock (OSC0) is sourced with a 20-MHz
clock. The auxiliary clock (OSC1) is sourced with a 22.5792-MHz clock. Both clocks are sourced from a
clock synthesizer (CDC925).
In addition to the SoC clock inputs, the EVM includes other clock sources. A 25-MHz clock is provided to
Ethernet PHY(s) and a 100-MHz clock is sourced for miniPCIe. Both the SoC and Ethernet clocks are
sourced from a clock synthesizer (CDC925).
3.6
3.6.1
Memory
SDRAM Memory
The EVM includes 2GB of DDR3L memory, and can operate at clock speeds up to 667 MHz (DDR31333). The memory is configured with four 4-Gb devices (x8b devices). ECC is supported.
• DDR3L device used: Micron® MT41K512M8RH-125-AA:E (4× 8b at 4Gb/each) (or equivalent)
• EEC device used: Micron MT41K512M8RH-125-AA:E (1× 8b at 4Gb) (or equivalent)
The DDR3L power is generated from the SoC power solution, and set to 1.35 V. It uses fly-by topology
with VTT termination. VTT supply is generated using a sink/source termination regulator (TPS51200).
3.6.2
QSPI Flash Memory
As a primary nonvolatile boot device, the EVM includes 256Mb of Quad-SPI flash memory. The device is
supported on CS0 of the QSPI interface. The interface can be configured to support either serial mode
(1×) or quad mode (4×).
• QSPI device used: Spansion™ S25FL256S
Booting from the QSPI flash memory is supported on the EVM. No EVM configuration is required because
the QSPI flash is enabled by default. Ensure the correct SoC boot mode is set using the SYS_BOOT
switches (SW3 and SW4).
3.6.3
EMMC Flash Memory
As a primary nonvolatile storage device, the EVM includes 8GB of EMMC flash memory. The memory
device is EMMC v4.51 compliant, and connects to the MMC2 port of the SoC. The design can supports
rates up to HS-200.
• EMMC device used: Micron MTFC8GLWDM-3M AIT Z
Booting from the EMMC flash memory is supported on the EVM. The onboard MUX must be able to
enable EMMC by setting SW8.p3 to on. Ensure the correct SoC boot mode is set using the SYS_BOOT
switches (SW3 and SW4).
3.6.4
MicroSD Card Cage
For nonvolatile storage expansion, the EVM includes a microSD card cage. The cage is connected to the
MMC1 port of the SoC. To support higher-speed cards that operate at lower voltages, the I/O supplies are
changed from 3v3 to 1v8 by setting GPIO7_11 to low. The SD card power can be cycled using I/O
expander (EXP2 and PP5). See the data manual for the SoC for specific information regarding supported
card types, densities, and speeds.
Booting from the microSD card cage is supported on the EVM. No EVM configuration is required as the
QSPI flash is enabled by default. Ensure the correct SoC boot mode is set using the SYS_BOOT switches
(SW3 and SW4).
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3.6.5
GPMC NOR Flash Memory
A 512Mb NOR flash memory (x16) is supported as a nonvolatile memory option on the EVM. The device
is supported on CS0, and therefore can also be used as a boot device. Booting from the NOR flash
memory is supported on the EVM. The onboard MUX must be able to enable the memory by setting
SW8.p2 to on. Ensure the correct SoC boot mode is set using the SYS_BOOT switches (SW3 and SW4).
• NOR device used: Spansion S29GL512S10TFI010
3.6.6
GPMC NAND Flash Memory
A 2Gb NAND flash memory (x16) is supported as a nonvolatile memory option on the EVM. The device is
supported on CS0, and therefore can also be used as a boot device. Booting from the NAND flash
memory is supported on the EVM. The onboard MUX must be able to enable the memory by setting
SW8.p1 to on. Ensure the correct SoC boot mode is set using the SYS_BOOT switches (SW3 and SW4).
• NAND device used: Micron MT29F2G16AADWP:D
3.6.7
Boot Modes
The SoC supports a variety of different boot modes, which is determined by the 16-bit system boot setting
present on the shared specific I/O balls during power-on sequence (see the TRM for details). Boot mode
selection is accomplished by the setting of DIP switches SW3 and SW4, as shown in Table 6, before
cycling power.
These SoC resources can be redeployed through both SoC pin EVM MUX settings to support alternate
interfaces after boot-up.
Table 6. SoC Boot Mode Switch Settings
CPU Board Net
DIP Switch Reference
Designator Position
Number Connections
GPMC_AD0
(sysboot0)
GPMC_D00
SW3.P1
On
GPMC_AD1
(sysboot1)
GPMC_D01
SW3.P2
Off
GPMC_AD2
(sysboot2)
GPMC_D02
SW3.P3
On
GPMC_AD3
(sysboot3)
GPMC_D03
SW3.P4
Off
GPMC_AD4
(sysboot4)
GPMC_D04
SW3.P5
On
GPMC_AD5
(sysboot5)
GPMC_D05
SW3.P6
Off
GPMC_AD6
(sysboot6)
GPMC_D06
SW3.P7
Off
GPMC_AD7
(sysboot7)
GPMC_D07
SW3.P8
Off
GPMC_AD8
(sysboot8)
GPMC_D08
SW4.P1
On
GPMC_AD9
(sysboot9)
GPMC_D09
SW4.P2
Off
GPMC_AD10
(sysboot10)
GPMC_D10
SW4.P3
Off
GPMC_AD11
(sysboot11)
GPMC_D11
SW4.P4
Off
GPMC_AD12
(sysboot12)
GPMC_D12
SW4.P5
Off
GPMC_AD13
(sysboot13)
GPMC_D13
SW4.P6
Off
GPMC_AD14
(sysboot14)
GPMC_D14
SW4.P7
Off
SoC Interface
(Internal System Boot Input)
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Table 6. SoC Boot Mode Switch Settings (continued)
SoC Interface
(Internal System Boot Input)
CPU Board Net
DIP Switch Reference
Designator Position
Number Connections
Factory Setting
GPMC_D15
SW4.P8
On
GPMC_AD15
(sysboot15)
In addition to SoC boot settings, EVM resources must also be set for the desired boot interface. Table 7
lists the boot interfaces that require selection. DIP switch SW8 is used to configure the various boot
memories.
Table 7. Board Controls for Memory Booting Options
Signals
Description
DIP Switch
Factory Setting
NAND_BOOTn(1)
On: Enable GPMC_nCS0 for NAND
flash boot
SW8.1
Off
NOR_BOOTn(1)
On: Enable GPMC_nCS0 for NOR flash
boot
SW8.2
Off
MMC2_BOOT
On: Enable MMC2 Interface for eMMC
flash boot
SW8.3
Off
Not Used
Not Used
SW8.4
Off
SW_VPP_EN
On: Enable VPP supply to SOC
(also requires I/O expander bit to be set)
SW8.5
Off
MCASP1_ENn
Low: Enable COMx signal paths
SW8.6
Off
NOR_ALT_ADDRn
Off: Selects default pin location for
GPMC ADDR
On: Selects alternate/new pin locations
for GPMC
SW8.7
Off
PCI_RESET_SEL
High: PCIe device may reset SoC.
Low: SoC may reset the PCIe device.
SW8.8
Off
GPMC_WPN
Low: Enable write protection of NAND
flash
SW5.9
Off
I2C_EEPROM_WP
High: Enable write protection of board
identification EEPROM
SW5.10
Off
(1) Routing control for GPMC_nCS0 is shared between the NOR and NAND flash memories. Ensure that only one DIP switch,
SW8.P1 or SW8.P2, is ever set to the on state at any time so that GMPC_nCS0 is connected to only one memory. Failure to
adhere to this requirement causes NOR and NAND memory data bus contention
3.6.8
JTAG/Emulator and Trace
The JTAG emulation interface is supported through the MIPI 60-pin interfaces. The EVM kit includes an
adapters for supporting other JTAG interfaces, including the 20-pin cJTAG interface from TI. Reset (warm
reset) using the emulator is supported.
Debug/Trace is also supported through the MIPI 60-pin connector. The EVM supports up to 20 trace bits.
At the SoC and EVM level, the trace pins are muxed with VIN2A and VOUT2 functions. Therefore, these
interfaces cannot be used simultaneously.
3.6.9
UART Terminal
The EVM supports a dual UART connection to be used for the user terminal. A FT2232 device transports
the UART information over USB to a host PC. The EVM is designed to use UART1 of the SoC as the
primary terminal connection, and is connected to port A of the USART transceiver. The USB-side of the
FT2232 device is powered from the USB port, and the connection stays active regardless of the power
state of the EVM. The green LED (D1) indicates that the USB connection is available.
• USART device to be used: FTD Chip FT232RQ
A USB cable (mini-B to type A) connects the EVM to a PC, and is included as part of the EVM kit.
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The EVM can support a second UART connection to the FT2232 device, intended for booting. However,
this configuration requires board modifications, and is recommended only for specific users.
3.6.10
DCAN and CAN Interfaces
The EVM supports access to two DCAN interfaces though pin headers. The device supports a single, 3pin, CAN interface, connecting DCAN1 through a CAN transceiver.
• CAN device used: Texas Instruments SN65HVDA541
3.6.11
Universal Serial Bus (USB)
Two independent USB ports are supported on the EVM. USB 3.0 Super-Speed bus (USB1) is supported
using port USB1 to a mini-AB type connector. This interface supports rates up to 5 GB/s. USB2.0 interface
is supported using port USB2 to a micro-AB type connector. It can supports rates up to 480 MB/s. Both
ports can operate in either host or device mode. VBUS can be supplied to the peripheral when in host
mode by enabling the VBUS switch (controlled through the SoC). However, the EVM cannot be powered
from VBUS when operating in device mode.
The EVM includes capabilities to set and read each ID pin of the connectors. This feature is supported
using the I/O expander (EXP2 P1 for USB1 and P2 for USB2). In addition, the DIP switch SW2 provides
the ability to manually set the individual ID value either high (off) or low (on).
3.6.12
Wired Ethernet
Dual Gigabit Ethernet ports are supported on the EVM. RGMII ports 0 and 1 drive the TI DP83867 Gigabit
PHYs. The PHYs are configured through the management data input/output bus (MDIO), with address set
to 0x2 (port 0) and 0x3 (port 1). PHYs are reset at power on, but can also be independently reset using
the I/O expander. Both ports share a common interrupt signal (GPIO6_16).
• I/O Expander Control: EXP1, P10 (PHY 0 Reset), P11 (PHY 1 Reset)
NOTE: For PHY configuration, users must configure the RGMII Control register (RGMIICTL) of the
DP83867 for RGMII mode, and configure the RGMII Delay Control register (RGMIIDCTL) for
a 0-ns TX delay and 2.25-ns RX delay. Set the I/O Drive Strength register
(IO_IMPEDANCE_CTRL) to maximum drive.
3.6.13
Video Output
The EVM supports three different options for supporting video output – HDMI display, LCD touch panel,
and FPD-Link III. Each option can be supported independently or all can be used simultaneously.
3.6.13.1
HDMI Display
The SoC includes a dedicated HDMI display, which is supported with a type A-HDMI connector. The
interface supports 1080p with 24b color. A communication channel (DDC/CEC) is provided to the HDMI
connector for communication with the HDMI panel. A monitor detect indication is also provided. The
DDC/CED interface and monitor detect signals (HPD) are translated through the transceiver, and can be
controlled using I/O from the expander.
• DDC Transceiver used: Texas Instruments TPD12S016
• I/O Expander Control: EXP3, P4 (level shift reg enable, HPD), and P5 (DDC/CEC enable)
3.6.13.2
LCD Touch Panel
The EVM supports an LCD panel interface for providing video output to an LCD panel. The SoC VOUT3
resource is used drive up to 24 bits of RGB data to the interface. The interface supports resource
connections for interfacing with a touch panel for advanced user interfaces. These resources include a
control bus (I2C1) and interrupt for touch indications (GPIOx). An LCD panel is not included with the CPU
EVM, but can be ordered and included as part of an assembly kit.
• Connector used: Molex®
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FPD-Link III Output/Panel
The EVM includes an FPD-Link III parallel to the serial interface on VOUT2. The device supports up to 24
bits of data and can operate at pixel rates up to 85 MHz. The interrupt is supported to enable backchannel communication, typically needed if supporting a touch screen. The transceiver is configured using
I2C (port 5, 0x1B).
• Serializer device used: Texas Instruments DS90UH925Q
• Connector used: Automotive HSD, right-angle plug for PCB, Rosenberger D4S20D-40ML5-Z
3.6.14
Video Input
3.6.14.1
Parallel Imaging
Parallel video input is supported through connections from external sensors and transceivers. The SoC
port VIN2A is routed to the connector interface and designed to mate with camera sensors from Leopard
Imaging. This approach provides flexibility for customers to select from a variety of available modules,
while also supporting connections of custom solutions. The attached module can be configured using
either I2C (port 5) or SPI (port 1).
• Connector used: FPC 36 position, 0.5 mm, Molex 052559-3679.
3.6.14.2
Serial Imaging
Serial video input is supported through connections from external sensors and transceivers. The SoC port
CSI2-0 is routed to the connector interface and designed to mate with camera sensors from Leopard
Imaging. This approach provides flexibility for customers to select from a variety of available modules.
Both serial ports (CSI2-0 and CSI2-1) are routed to an expansion connector for supporting a variety of
custom solutions. Both interfaces support additional signals for control and configuration of the attached
modules. These interfaces (I2C port 5 and SPI port 1) are translated to 1.8-V I/O (with resistor option to
leave at 3.3-V I/O).
• LI Connector used: FPC 36 position, 0.5 mm, Molex 052559-3679
• Connector used: Samtec™ QSH-020-01-L-D-DP-A
3.6.15
Mini-PCIe
The EVM supports a mini-PCIe (single lane) interface for connecting with a variety of external modules.
An onboard clock generator, CDCM9102, provides the 100-MHz reference clock to both the SoC and
attached modules. The EVM supports two different PCIe reset configurations; select one using the DIP
switch SW8 position 8. The default setting of on provides the SoC the ability to reset the PCIe peripheral.
The switch setting of off provides the PCIe peripheral the ability to reset the SoC.
3.6.16
Media Local Bus (MLB)
The EVM supports an MLB interface for connecting to external hardware (such as the SMSC
OS81110/2+0 Physical Interface Board). The interface supports both 3-pin MediaLB and 6-pin MediaLB+
configurations.
• Connector used: Samtec QSH-020-01-L-D-DP-A
3.6.17
Audio
The EVM supports onboard AIC3106 audio codec for analog audio conversions. Analog inputs are
supported on two 3.5-mm audio jacks, including stereo line inputs (P12) and mono microphone (P11).
Analog outputs are supported on two 3.5-mm audio jacks, providing stereo line outputs (P13) and stereo
headset (P14). The digital audio is connected to the SoC using the multichannel serial port (McASP3).
The codec requires a master clock (AHCLKX). The audio codec is configured using I2C1, and is accessed
at address 0x19.
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3.6.18
COM8 Module Interface
A connector is provided to facilitate plugging in of the TI COM8Q modules, which provide features such as
Bluetooth and Wi-Fi®. The COM8Q interface requires a 3.6-V power supply, thus a dedicated regulator is
provided. All signals on the COM8Q interface are required to 1.8 volts, therefore voltage translators are
placed to convert from the standard I/O levels of 3.3 V.
• Connector used: Samtec MEC6-150-02-S-D-RA1
3.6.19
eFuse Programming Supply
The EVM provides enabling and disabling support for the eFUSE programming supply. As a protection,
two separate steps are required to enable the programming supply. The DIP switch SW8.p5 must be set
to on (default is off) and the I/O expander (EXP2 and P13) must be low by software (default is high).
3.6.20
User Interface LEDs
The CPU board has four user interface LEDs for debug, status indication, and so on. Table 8 lists details
about the user interface LEDs and their controls.
Table 8. User LEDs
LED
Controlled By
DS2
I/O Expander EXP1, position P7
DS3
I/O Expander EXP1, position P6
DS4
I/O Expander EXP1, position P5
DS5
I/O Expander EXP1, position P4
3.6.21
Power Monitoring
The CPU board has provisions to monitor power for many of the systems core power rails. The
measurement system is implemented using the INA226 I2C current shunt and power monitors from TI. The
INA226 device monitors both power supply voltage and shunt current measurements. Information is
connected from the INA226 devices using dedicated I2C buses. The INA226 devices can be controlled
using off-board modules (FTDI USART, MSP430, or a similar device).
Table 9 lists a mapping of the current monitoring system. INA226 devices are at each shunt location.
Table 9. Power Monitor Mapping
I2C Address
Power Net
Shunt/Resistor
Description
I2C BUS A
0x40
VPIN_S1_3V3
20 mΩ
LP8733 Buck0 power input (core)
0x41
VPIN_S2_3V3
20 mΩ
LP8733 Buck1 power input (DSP)
0x42
VPIN_S3_3V3
20 mΩ
LP8732 Buck0 power input (1V8)
0x43
VPIN_S4_3V3
20 mΩ
LP8732 Buck1 power input (DDR)
0x44
VDD_CORE_AVS
10 mΩ
CPU Core power rail
0x45
VDD_DSP_AVS
10 mΩ
CPU DSP power rail
0x46
VDDS_1V8
10 mΩ
CPU 1V8 power rails
0x47
VDD_DDR_1V35
10 mΩ
CPU DDR power rail
0x48
VDA_1V8_PLL
10 mΩ
CPU PLL power rails
0x49
VDA_1V8_PHY
10 mΩ
CPU PHY power rails
0x4A
VDDSHV8
10 mΩ
CPU I/O power rail for VDDSHV8
0x4B
VDDA_USB3V3
10 mΩ
CPU USB3V3 power rail
0x4C
VDDSHV_3V3
10 mΩ
CPU I/O power rail (except VDDSHV8)
2
I C BUS B
0x40
EVM_12V
10 mΩ
Total system 12-V power rail
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Table 9. Power Monitor Mapping (continued)
2
I C Address
Power Net
Shunt/Resistor
Description
0x41
EVM_5V0
10 mΩ
Total system 5V0 power rail
0x42
VSYS_3V3
10 mΩ
Total system 3V3 power rail
0x43
VDD_DDR
10 mΩ
DDR memory power rail
0x44
EVM_1V8
10 mΩ
EVM 1V8 peripheral rail
0x45
EVM_3V3
10 mΩ
EVM 3V3 peripheral rail
I2C Peripheral Map
3.6.22
Table 10 lists the I2C interfaces available on the EVM, with a list of devices connected to each I2C
interface and its corresponding device address.
Table 10. I2C Device Address Chart
CPU Board
Part No.
I2C1
EEPROM
24WC256
X
0x50
Digital Temperature
Sensor
TMP102AIDRLT
X
0x48
GPIO Expander 1
PCF8575
X
0x20
GPIO Expander 2
PCF8575
X
GPIO Expander 3
PCF8575
MLB Connector
Connector
X
NA
LCD Interface
Connector
X
NA
COM8 Connector
Connector
X
NA
Audio Codec
TLV320AIC3106
X
0X19
Expansion
Connector
Connector
X
LP8733
X
0x60
LP8732
X
0x61
PMIC
I2C3
I2C4
I2C5
Device Address (7b)
0x21
X
X
0x26
X
NA
FPD Link
DS90UH925Q
X
0x1B
LI Camera
Connector
X
NA
CSI2 Camera
Connector
X
NA
3.6.23
GPIO List
Table 11 lists the SoC GPIOs. Signals used for GPIOs on expansion boards are not included in this list,
because they are dependent upon the application board used.
Table 11. SoC GPIO Map
Feature
Peripheral Device
EVM Board Net
Function
SoC GPIO (1)
Connectivity on Module
COM8 Connector
GP5[4]
BT_EN
GPIO5_4
Connectivity on Module
COM8 Connector
GP5[5]
GPS_PPS_OUT
GPIO5_5
Connectivity on Module
COM8 Connector
GP5[6]
GPS_TIME_STAMP
GPIO5_6
Connectivity on Module
COM8 Connector
GP5[7]
WLAN_IRQ
GPIO5_7
Connectivity on Module
COM8 Connector
GP5[8]
WL_EN
GPIO5_8
Media Local Bus (MLB)
MLB Connector
GP5[9]
NA
GPIO5_9
Media Local Bus (MLB)
MLB Connector
GP6_[28]
NA
GPIO6_28
I/O Expander
PCF8575
PCF8575_INT
IOEXP_IRQ
GPIO7_31
Gig Ethernet
Ethernet PHY(s)
ENET_INTSn
ENET_IRQ
GPIO6_16
(1)
18
Functional signals of pin MUX are not consider for this table. See the schematics for further details.
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Table 11. SoC GPIO Map (continued)
Feature
Peripheral Device
EVM Board Net
Function
SoC GPIO (1)
LCD Touch Panel
Display Connector
GP1[15]
TS_LCD_IRQ
GPIO1_15
FPD-Link Panel
FPD-Link Txmt
VOUT2_INTB
FPDTX_IRQ
GPIO3_38
Power Management
LP8733/32
LP_INTn
PMIC_IRQ
GPIO1_3
Power Management
Suspend2RAM
POWERHOLD_CLK
POWERDOWN
GPIO7_30
SD Card
Micro-SD
MMC1_SDCD
CARD_DETECT
GPIO6_27
SD Card
Micro-SD
SPI[1]_CS[1]
IO_VOLTAGE_LVL
GPIO7_11
Test
Automated Test
GP5[0]
USER_DEFINED
GPIO5_0
3.6.24
I/O Expander List
Table 12 lists the I/O expander map.
Table 12. I/O Expander Map
Device
EXP1
Slave
Address
0b0010 000
(0x20)
I2C I/F
I2C1
Expander I/O
Netname
Description
INT Number
PCF8575_INT
Interrupt output to SoC
P0
TS_LCD_GPIO1
Push-button switch 1
P1
TS_LCD_GPIO2
Push-button switch 2
P2
TS_LCD_GPIO3
Push-button switch 3
P3
TS_LCD_GPIO4
Push-button switch 4
P4
USER_LED1
User LED 1
P5
USER_LED2
User LED 2
P6
USER_LED3
User LED 3
P7
USER_LED4
User LED 4
P10
EXP_ETH0_RSTn
RGMII0 reset
P11
EXP_ETH1_RSTn
RGMII1 reset
P12
USB1-VBUS_OCN
USB1 overcurrent indication
P13
USB2-VBUS_OCN
USB2 overcurrent indication
P14
PCI_SW_RESETn
PCI interface software reset
P15
CON_LCD_PWR_DN
LCD board master power enable
P16
USB1-VBUS_DET
USB1 VBUS detection
P17
USB2-VBUS_DET
USB2 VBUS detection
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Table 12. I/O Expander Map (continued)
Device
EXP2
EXP3
20
Slave
Address
0b0010 001
(0x21)
0b0010 010
(0x26)
I2C I/F
I2C1
I2C5
Expander I/O
Netname
Description
INT Number
PCF8575_INT
Interrupt output to SoC
P0
SEL_GPMC_AD_VID_S0
MUX out control signal for GPMC versus
VOUT3B versus VIN1A
P1
USB1_ID
USB1 ID PIN
P2
USB2_ID
USB2 ID PIN
P3
SEL_I2C3_CAN2
MUX out control signal for I2C3 versus
DCAN2
P4
SEL_ENET_MUX_S0
MUX out control signal for RGMII0 versus
VIN
P5
MMC_PWR_ON
Power on regulator to MMC card
P6
NOR_ALT_ADDRn
MUX out control signals for alternate
location of GPMC control signals
P7
SEL_GPMC_AD_VID_S2
MUX out control signal for GPMC versus
VOUT3B versus VIN1A
P10
NAND_BOOTn
NAND boot chip select enable signal
P11
NOR_BOOTn
NOR boot chip select enable signal
P12
MMC2_BOOT
MUX out control signal for GPMC versus
MMC2
P13
PFC_VPP_ENn
Enable for VPP power supply
P14
VOUT2_S0
MUX out control signal for EMU versus
VIN2A versus VOUT2
P15
MCASP1_ENn
COM8 interface level shifter enable signal
P16
SEL_UART3_SPI2
MUX out control signal for UART3 versus
SPI2
P17
VOUT2_S1
MUX out control signal for EMU versus
VIN2A versus VOUT2
P0
PM_OEn
Enable to connect PM Bus with I2C3
P1
VIN6_SEL_S0
MUX out control signal for VIN6A and
McASPx
P2
VIN2_S0
MUX out control signal for EMAC1 and
VIN2A signals
P3
PM_SEL
Selection to connect I2C3 to either PM bus
1 or 2
P4
HDMI_CT_HPD
HDMI hot plug detect
P5
HDMI_LS_OE
HDMI level shifter enable
P6
VIN2_S2
MUX out control signal for VIN2A versus
expansion signals
P7
CAN_STB
CAN transceiver standby
P10
SEL_CSI2n
MUX out control signal for CSI2
configuration
P11
EXVIN2_S0
MUX out control signal for EMAC1 versus
VIN2A versus expansion signals
P12
EXVIN2_S2
MUX out control signal for EMAC1 versus
VIN2A versus expansion signals
P13
MMC3_SEL
MUX out control signal for MMC3 versus
VIN2B
P14
MMC2_BOOT_OVR_OEN
MMC2 DIP switch override enable
P15
MMC2_BOOT_OVR
MMC2 DIP switch override
P16
NOR_BOOT_OVR_OEN
NOR BOOT DIP switch override enable
P17
NOR_BOOT_OVR
NOR BOOT DIP switch override
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3.6.25
Configuration EEPROM
The CPU board contains an EEPROM memory device for storing and retrieving configuration information.
The EEPROM provides 256Kb (or 32KB) of storage space, and is accessible using I2C (the device
location information is in Table 10). The configuration ID information is programmed by the factory at the
time of manufacturing, and should not be altered. Table 13 lists the configuration data format within the
EEPROM.
• EEPROM device used: Catalyst Semiconductor CAT24C256WI-G
• I2C Bus/Address: I2C1, 0x50
Table 13. Configuration EEPROM
EEPROM Field
Byte Location
Value
(Rev A CPU Board
Example)
ID.HEADER
[3:0]
0xAA5533EE
Fixed value at start of header ID.
ID.BOARD_NAME
[19:4]
DRA79x, DRA71x (ASCII)
For J6Entry – fixed value of DRA79x,DRA71x
ID.VERSION_MAJOR
[21:20]
0x1
A = 0x1
B = 0x2
C = 0x3
ID.VERSION_MINOR
[23:22]
0x0
0x0 for major revision
0x1-0x15 for others
Description
ID.CONFIG_OPTION
[27:24]
0x0E
Bit 6: 1 – EMIF2 ECC Supported, 0 – No
Bit 5: 1 – EMIF2 Supported, 0 – No
Bit 4: 1 – EMIF1 ECC Supported, 0 – No
Bit 3: 1 – EMIF1 Supported, 0 – No
Bit 2: 1 – Extended Memory EEPROM Cfg
Support, 0 – No (1)
Bit 1: 1 – MAC addr in EEPROM (default)
Bit 0: 0 - QSPI (default), 1 - NOR
EMIF1_SIZE_BYTES
[31:28]
0x8000 0000
Memory size for EMIF1 in bytes (unsigned long)
EMIF2_SIZE_BYTES
[35:32]
0x0000 0000
Memory size for EMIF2 in bytes (unsigned long)
RESERVED
[55:36]
0x0
Reserved
0x7F00
00.0E.99.zz.yy.xx
Optional MAC address
_
MAC_ADDR
(1)
If Bit 2 is set to 0, all EEPROM data beyond is set to 0 (Not defined or Used). If Bit 2 is set to 1, mapping is according to the table.
For reference, a C-style coded structure is provided, as follows.
Struct EEPROM_ID_T
{
Unsigned long header;
4
Char board_name[16];
16
Unsigned short version_major;
2
Unsigned short version_minor;
2
Unsigned long config_option;
4
Unsigned long emif1_size_bytes;
4
Unsigned long emif2_size_bytes;
4
Char reserved[28];
20
} eeprom_id;
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Signal Multiplex Logic
Due to the high level of multiplexing on the SoC (over 16 levels), multiplex control logic is required to use
different signals on the same SoC pins with their various functionality. The following information provides
description of the logic.
An I2C-based I/O expander controls the onboard MUXs. Table 14 lists the specific bits assigned to each
MUX, as well as the specific settings for the various selections.
Table 14. Onboard MUX Setting and Control
MUX
Control Bits
A
NA
SW8.3
C
(RU4)
EXP3.P[15:14]
B
(RU9, RU11, RU24)
D
(RU6)
EXP3.P[6,2]
E
(RU12, RU23)
F
(RU27)
EXP2.P[7,0]
EXP2.P[17,14]
EXP3.P[12,11]
K
(RJ12)
EXP2.P16
L
(RU18)
EXP2.P3
J
(RU25)
M
(RU8)
G
(RU26)
H
(RU10)
22
EXP2.P4
EXP3.P13
SW8.7
EXP3.P1
Value
MUX Setting
NA
QSPI Memory (default)
NA
NOR Memory (requires resistor change)
Off
NOR Memory
On
EMMC Memory
00
EMMC Memory
01
Memory selected by SW8.3
10
NOR Memory
11
Memory selected by SW8.3 (default)
00
Reserved
01
VIN1A to Expansion
10
VOUT3 to LCD Panel
11
GPMC NOR/NAND (default)
00
Reserved
01
Peripheral selected by MUX E (desired default)
10
VIN2A to Expansion
11
Open (default)
00
Reserved
01
VOUT2 to FPD-Link III Transmitter
10
VIN2A to LI Camera
11
EMU (default)
00
Reserved
01
Peripheral selected by MUX E
10
VIN2A to Expansion
11
RGMII1 to Ethernet Port 1 (default)
0
UART3 to COM8Q
1
Route to Expansion (SPI2) (default)
0
Route to Expansion (I2C3)
1
Route to DCAN2 Connector (default)
0
Route to Expansion (VIN1B)
1
RGMII0 to Ethernet Port 0 (default)
0
Route to Expansion (VIN2B)
1
Route to Expansion (MMC3/legacy) (default)
Off
Use Default NOR Address (default)
On
Use Alternate NOR Address (with EMMC)
0
Route to COM8Q (MASP3/7)
1
Route to Expansion (McASP3/7) (default)
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4.1
GPMC and QSPI Selection (MUX A)
Figure 8 is part of the SoC pinmux table for the GPMC. The SoC device supports additional functions not
shown in the table. The functions shown are intended to reflect those supported on the EVM. These
functions include:
• Memory Bus (GPMC): A[18:13]
• Quad Serial Bus (QSPI): SCLK, D[3:0], CS[0], and RTCLK
Figure 8. SoC Pinmux for GPMC and QSPI
Mux A: Selects between NOR and QSPI memory support. The MUX is implemented using resistors. This
was due to the signal rate and routing restrictions of the QSPI device. To enable the GPMC signals to
NOR (shown in red), the board must be modified to move resistors. Figure 9 shows the MUX diagram for
GPMC and QSPI.
QSPI1
R-Mux
A1
B1
QSPI1_SCLK, _D[3:0],
_CS[0], _RTCLK
Mux
QSPI Memory
SoC
GPMC_A[18:13], _CS[2]
GPMC
A
B2
GPMC_A[18:13], _CS[2]
NOR Memory
Figure 9. MUX Diagram for GPMC and QSPI
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GPMC, VIN1, and VOUT3 Selection (MUX B)
Figure 10 is part of the SoC pinmux table for GPMC. The SoC device supports additional functions not
shown in the table. The functions shown are intended to reflect those supported on the EVM. These
functions include:
• Memory Bus (GPMC): AD[15:0], A[12:0]
• Video Input Port (VIN1A): CLK, HSYNC, VSYNC, DE, and D[23:0]
• Video Output Port (VOUT3): CLK, HSYNC, VSYNC, DE, and D[23:0]
• Boot Mode Selection (SYSBOOT): SYSBOOT[15:0]
Figure 10. SoC Pinmux for GPMC, VIN1, and VOUT3
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MUX B: Selects between NOR and NAND memories, LCD panel for video, and expansion. The selection
is made using the I/O expander 2, bits P7 and P0. The defaults is set to enable GPMC to NOR and NAND
memories – which is required for SYSBOOT mode latching. Figure 11 shows the MUX diagram for GPMC,
VIN1, and VOUT3
DIP Switch
(SYSBOOT)
NOR Memory
A1=B1 or A1=B2 or A1 = B3
CBT16214
SoC
A1
GPMC_A[12:0], _AD[15:0]
B1
GPMC
GPMC_A[12:0], _AD[15:0]
Mux
NAND
Memory
VOUT3
B
B3
B2
VOUT3_CLK, _VS, _HS,
_DE, _D[23:0]
LCD Panel
Connector
VIN1A
VIN1A_CLK, _VS, _HS, _DE,
_D[23:0]
Expansion
Connector
Figure 11. MUX Diagram for GPMC, VIN1, and VOUT3
4.3
GPMC and EMMC Selection (MUX C)
Figure 12 is part of the SoC pinmux table for GPMC. The SoC device supports additional functions not
shown in the table. The functions shown are intended to reflect those supported on the EVM. These
functions include:
• Memory Bus (GPMC): A[27:19]
• EMMC Memory (MMC2): CLK, CMD, D[7:0]
Figure 12. SoC Pinmux for GPMC and EMMC
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MUX C: Selects between NOR memory and EMMC memory. The selection is made using the I/O
expander 3, bits P15 and P14. If booting from EMMC, the DIP Switch SW8 position 3 is used to select
interface (by default). Figure 13 shows the MUX diagram for GPMC and EMMC.
A1=B1 or A1=B2
CBT16212
A1
Mux
B1
GPMC
GPMC_A[27:19], _CS[1]
NOR
Memory
SoC
GPMC_A[27:19], _CS[1]
MMC2
C
B2
MMC2_CLK, _CMD, _DA[7:0]
EMMC
Memory
Figure 13. MUX Diagram for GPMC and EMMC
4.4
VIN2A and EMU Selection (MUX D, MUX E)
Figure 14 is part of the SoC pinmux table for VIN2A. The SoC device supports additional functions not
shown in the table. The functions shown are intended to reflect those supported on the EVM. These
functions include:
• Video Input Port (VIN2A): CLK, HSYNC, VSYNC, DE, D[9:0]
• Video Output Port (VOUT2): CLK, HSYNC, VSYNC, DE, D[23:14]
• Debug/Trace (EMU): EMU[19:5]
Figure 14. SoC Pinmux for VIN2A and EMU
MUX D: Selects between onboard support and expansion support for the VIN2A, EMU signals. The
selection is made using the I/O expander 3, bits P6 and P2. The default mode is set to onboard peripheral
selection, such JTAG/Trace can be supported without I2C accesses.
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MUX E: Selects between LI Camera, FPD-Link transmitter, and JTAG/Trace. The selection is made using
the I/O expander 2, bits P17 and P14. The default mode is set to EM, such JTAG/Trace can be supported
without I2C accesses. Figure 15 shows the MUX diagram for VIN2A and EMU
A1=B2 or A1 = B3
CBT16214
SoC
A1
VIN2A_CLK, _VS, _HS, _DE,
_D[9:0]
B1
Mux
VIN2A
D
B3
VIN2A_CLK, _VS, _HS, _DE, _D[9:0]
B2
Expansion
Connector
A1=B1 or A1=B2 or A1=OPEN
VIN2A
CBT16212
VIN2A_CLK, _VS, _HS, _DE,
VIN2A_CLK, _VS, _HS, _DE, _D[9:0]
_D[9:0]
VIN2A
A1
Mux
LI Camera
Connector
VOUT3
EMU
EMU [19:5]
B1
E
MIPI-60
Connector
B2
VOUT3_CLK, _VS, _HS,
_DE, _D[9:0]
FPD-Link III
Transmitter
Figure 15. MUX Diagram for VIN2A and EMU
4.5
VIN2A and RGMII1 Selection (MUX F)
Figure 16 is part of the SoC pinmux table for VIN2A. The SoC device supports additional functions not
shown in the table. The functions shown are intended to reflect those supported on the EVM. These
functions include:
• Video Input Port (VIN2A): D[23:10]
• Gig Ethernet (RGMII1): TXC, TXCTL, TXD[3:0], RXC, RXCTL, RXD[3:0]
• Management Data I/O (MDIO): MCLK, D
Figure 16. SoC Pinmux for VIN2A and RGMII1
MUX F: Selects between Gig Ethernet and Expansion, and combines with MUX E to support the LI
Camera and FPD-Link transmitter. The selection is made using the I/O expander 3, bits P12 and P11, with
the default set to Gig Ethernet.
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The MDIO MUX setting shown (in red) is used only if the RGMII0 port is not selected. Otherwise, the
MDIO function is provided by other pins. The MUX selection for MDIO is automatic based on the RGMII0
MUX setting. Figure 17 shows the MUX diagram for VIN2A and RGMII1.
A1=B1 or A1=B2 or A1 = B3
CBT16214
SoC
A1
RGMII1, MDIO
RGMII1_TXC, _TXCTL, _TXD[3:0], _RXD, _RXCTL, _RXD[3:0]
MDIO_CLK, _D
B1
Mux
VIN2A_D[23:10]
VIN2A
F
B3
Ethernet
VIN2A_D[23:10]
B2
Expansion
Connector
A1=B1 or A1=B2
VIN2A
VIN2A
CBT16212
VIN2A_D[23:10]
A1
B1
VIN2A_D[13:10]
Mux
E
LI Camera
Connector
VOUT3
B2
VOUT3_D[23:10]
FPD-Link III
Transmitter
Figure 17. MUX Diagram for VIN2A and RGMII1
4.6
RGMII0 and VIN1B Selection (MUX J)
Figure 18 is part of the SoC pinmux table for RGMII0. The SoC device supports additional functions not
shown in the table. The functions shown are intended to reflect those supported on the EVM. These
functions include:
• Gig Ethernet (RGMII0): TXC, TXCTL, TXD[3:0], RXC, RXCTL, RXD[3:0]
• Management Data I/O (MDIO): MCLK, D
• Video Input Port (VIN1B): CLK, HSYNC, VSYNC, DE, [7:0]
Figure 18. SoC Pinmux for RGMII0 and VIN1B
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Mux J: Selects between Gig Ethernet and Expansion. The selection is made using the I/O expander 2, bit
P4, defaulting to Gig Ethernet. Figure 19 shows the MUX diagram for RGMII0 and VIN1B.
A1=B1 or A1=B2
CBT16212
A1
B1
RGMII0, MDIO
RGMII0_TXC, _TXCTL, _TXD[3:0],
_RXD, _RXCTL, _RXD[3:0]
MDIO_MCLK, _D
Ethernet
Mux
SoC
J
RGMII0_TXC, _TXCTL, _TXD[3:0],
_RXC, RXCTL, _RXD[3:0]
UART3_RXD, _TXD
MDIO_MCLK, _D
VIN1B
B2
VIN1B_CLK, _VS, _HS, _DE, _DA[7:0]
Expansion
Connector
Figure 19. MUX Diagram for RGMII0 and VIN1B
4.7
SPI2 and UART3 Selection (MUX K)
Figure 20 is part of the SoC pinmux table for SPI2. The SoC device supports additional functions not
shown in the table. The functions shown are intended to reflect those supported on the EVM. These
functions include:
• SPI Serial Bus (SPI2): SCLK, D[1:0], CS[0]
• UART Serial Bus (UART3): TXD, RXD, CTSN, RTSN
Figure 20. SoC Pinmux for SPI2 and UART3
MUX K: Selects between Bluetooth (COM8Q module) and expansion interface. The selection is made
using the I/O expander 2, bits P16, defaulting to expansion. Figure 21 shows the MUX diagram for SPI2
and UART3.
A1=B1 or A1=B2
UART3
CBT3257
A1
B1
UART3_TX, _RX, _CTS, _RTS
Mux
COM8Q
Connector
SoC
SPI2_SCLK, _D[1:0], _CS[0]
SPI2
K
B2
SPI2_SCLK, _D[1:0], _CS[0]
Expansion
Connector
Figure 21. MUX Diagram for SPI2 and UART3
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DCAN2 and I2C3 Selection (MUX L)
Figure 22 is part of the SoC pinmux table for DCAN2. The SoC device supports additional functions not
shown in the table. The functions shown are intended to reflect those supported on the EVM. These
functions include:
• Digital CAN Bus (DCAN2): TX, RX
• I2C Serial Bus (I2C3): SCL, SDA
Figure 22. SoC Pinmux for DCAN2
MUX L: Selects between DCAN2 header and expansion interface. The selection is made using the I/O
expander 2, bit P3, defaulting to onboard DCAN header. Figure 23 shows the MUX diagram for DCAN2
and I2C.
A1=B1 or A1=B2
I2C3
CBT3257
A1
B1
I2C3_SCL, _SDA
Expansion
Connector
Mux
SoC
GPIO6_[15:14]
DCAN2
L
B2
DCAN2_TX, _RX
DCAN2
Connector
Figure 23. MUX Diagram for DCAN2 and I2C
5
USB3 Supported Configurations
The following USB3.x combinations are supported:
• Micro-A plug to standard-B plug:
– Connect to hub or external drive/device that has a standard B receptacle.
• Micro-A plug to Micro-B plug:
– EVM connects to hub or external drive/device that has a Micro B receptacle.
– Host connects to the EVM acting as a device.
• Standard-A plug to Micro-B plug:
– Host connects to the EVM acting as a device.
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5.1
Option 1
Use a USB 3.0 Micro-AB to standard-B and USB 3.0 SIIG® hub as shown in Figure 24 and Figure 25.
uEVM5432 side
HUB side
Figure 24. Qualtek 3023009-01M USB 3.0 Micro-AB to Standard-B 1m (3.28’)
Figure 25. SIIG JU-H40312-S14-Port USB 3.0 Super Speed USB Hub
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Option 2
Use a USB 3.0 Micro-A to Micro-B and USB 3.0 IOGEAR® hub as shown in Figure 26 and Figure 27.
uEVM5432 side
USB3.0 HUB side
Figure 26. Qualtek 3023007-01M USB 3.0 Micro-A to Micro-B 1m (3.28')
Figure 27. IOGEAR GUH374 4-Port USB 3.0 HUB
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5.3
Option 3
Use a USB 3.0 standard-A to Micro-B as shown in Figure 28. The host PC connects to the EVM acting as
a device.
Host PC side
uEVM5432 side
Figure 28. Qualtek 3023005-01M USB 3.0 Standard-A to Micro-B 1m (3.28')
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References
6
References
•
•
•
•
•
34
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Texas
Texas
Texas
Texas
Texas
Instruments, DRA71x/DRA79x/TDA2Ex-17/AM570x CPU board
Instruments, DRA71x/DRA79x/TDA2Ex-17/AM570x CPU board
Instruments, DRA71x/DRA79x/TDA2Ex-17/AM570x CPU board
Instruments, DRA71x/DRA79x/TDA2Ex-17/AM570x CPU board
Instruments, DRA71x/DRA79x/TDA2Ex-17/AM570x CPU board
DRA79x EVM CPU board
PCB rev C
Schematic rev C1
BOM rev C
assembly drawing rev C
PCB drawing rev C
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Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Original (August 2017) to A Revision ..................................................................................................... Page
•
Update was made in Section 3.3.
.....................................................................................................
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